Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright: 2017 Cadence Design Systems, Inc.
4 *
5 * Author: Boris Brezillon <boris.brezillon@bootlin.com>
6 */
7
8#include <drm/drm_atomic_helper.h>
9#include <drm/drm_drv.h>
10#include <drm/drm_probe_helper.h>
11#include <video/mipi_display.h>
12
13#include <linux/clk.h>
14#include <linux/interrupt.h>
15#include <linux/iopoll.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_graph.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/reset.h>
22
23#include <linux/phy/phy-mipi-dphy.h>
24
25#include "cdns-dsi-core.h"
26#ifdef CONFIG_DRM_CDNS_DSI_J721E
27#include "cdns-dsi-j721e.h"
28#endif
29
30#define IP_CONF 0x0
31#define SP_HS_FIFO_DEPTH(x) (((x) & GENMASK(30, 26)) >> 26)
32#define SP_LP_FIFO_DEPTH(x) (((x) & GENMASK(25, 21)) >> 21)
33#define VRS_FIFO_DEPTH(x) (((x) & GENMASK(20, 16)) >> 16)
34#define DIRCMD_FIFO_DEPTH(x) (((x) & GENMASK(15, 13)) >> 13)
35#define SDI_IFACE_32 BIT(12)
36#define INTERNAL_DATAPATH_32 (0 << 10)
37#define INTERNAL_DATAPATH_16 (1 << 10)
38#define INTERNAL_DATAPATH_8 (3 << 10)
39#define INTERNAL_DATAPATH_SIZE ((x) & GENMASK(11, 10))
40#define NUM_IFACE(x) ((((x) & GENMASK(9, 8)) >> 8) + 1)
41#define MAX_LANE_NB(x) (((x) & GENMASK(7, 6)) >> 6)
42#define RX_FIFO_DEPTH(x) ((x) & GENMASK(5, 0))
43
44#define MCTL_MAIN_DATA_CTL 0x4
45#define TE_MIPI_POLLING_EN BIT(25)
46#define TE_HW_POLLING_EN BIT(24)
47#define DISP_EOT_GEN BIT(18)
48#define HOST_EOT_GEN BIT(17)
49#define DISP_GEN_CHECKSUM BIT(16)
50#define DISP_GEN_ECC BIT(15)
51#define BTA_EN BIT(14)
52#define READ_EN BIT(13)
53#define REG_TE_EN BIT(12)
54#define IF_TE_EN(x) BIT(8 + (x))
55#define TVG_SEL BIT(6)
56#define VID_EN BIT(5)
57#define IF_VID_SELECT(x) ((x) << 2)
58#define IF_VID_SELECT_MASK GENMASK(3, 2)
59#define IF_VID_MODE BIT(1)
60#define LINK_EN BIT(0)
61
62#define MCTL_MAIN_PHY_CTL 0x8
63#define HS_INVERT_DAT(x) BIT(19 + ((x) * 2))
64#define SWAP_PINS_DAT(x) BIT(18 + ((x) * 2))
65#define HS_INVERT_CLK BIT(17)
66#define SWAP_PINS_CLK BIT(16)
67#define HS_SKEWCAL_EN BIT(15)
68#define WAIT_BURST_TIME(x) ((x) << 10)
69#define DATA_ULPM_EN(x) BIT(6 + (x))
70#define CLK_ULPM_EN BIT(5)
71#define CLK_CONTINUOUS BIT(4)
72#define DATA_LANE_EN(x) BIT((x) - 1)
73
74#define MCTL_MAIN_EN 0xc
75#define DATA_FORCE_STOP BIT(17)
76#define CLK_FORCE_STOP BIT(16)
77#define IF_EN(x) BIT(13 + (x))
78#define DATA_LANE_ULPM_REQ(l) BIT(9 + (l))
79#define CLK_LANE_ULPM_REQ BIT(8)
80#define DATA_LANE_START(x) BIT(4 + (x))
81#define CLK_LANE_EN BIT(3)
82#define PLL_START BIT(0)
83
84#define MCTL_DPHY_CFG0 0x10
85#define DPHY_C_RSTB BIT(20)
86#define DPHY_D_RSTB(x) GENMASK(15 + (x), 16)
87#define DPHY_PLL_PDN BIT(10)
88#define DPHY_CMN_PDN BIT(9)
89#define DPHY_C_PDN BIT(8)
90#define DPHY_D_PDN(x) GENMASK(3 + (x), 4)
91#define DPHY_ALL_D_PDN GENMASK(7, 4)
92#define DPHY_PLL_PSO BIT(1)
93#define DPHY_CMN_PSO BIT(0)
94
95#define MCTL_DPHY_TIMEOUT1 0x14
96#define HSTX_TIMEOUT(x) ((x) << 4)
97#define HSTX_TIMEOUT_MAX GENMASK(17, 0)
98#define CLK_DIV(x) (x)
99#define CLK_DIV_MAX GENMASK(3, 0)
100
101#define MCTL_DPHY_TIMEOUT2 0x18
102#define LPRX_TIMEOUT(x) (x)
103
104#define MCTL_ULPOUT_TIME 0x1c
105#define DATA_LANE_ULPOUT_TIME(x) ((x) << 9)
106#define CLK_LANE_ULPOUT_TIME(x) (x)
107
108#define MCTL_3DVIDEO_CTL 0x20
109#define VID_VSYNC_3D_EN BIT(7)
110#define VID_VSYNC_3D_LR BIT(5)
111#define VID_VSYNC_3D_SECOND_EN BIT(4)
112#define VID_VSYNC_3DFORMAT_LINE (0 << 2)
113#define VID_VSYNC_3DFORMAT_FRAME (1 << 2)
114#define VID_VSYNC_3DFORMAT_PIXEL (2 << 2)
115#define VID_VSYNC_3DMODE_OFF 0
116#define VID_VSYNC_3DMODE_PORTRAIT 1
117#define VID_VSYNC_3DMODE_LANDSCAPE 2
118
119#define MCTL_MAIN_STS 0x24
120#define MCTL_MAIN_STS_CTL 0x130
121#define MCTL_MAIN_STS_CLR 0x150
122#define MCTL_MAIN_STS_FLAG 0x170
123#define HS_SKEWCAL_DONE BIT(11)
124#define IF_UNTERM_PKT_ERR(x) BIT(8 + (x))
125#define LPRX_TIMEOUT_ERR BIT(7)
126#define HSTX_TIMEOUT_ERR BIT(6)
127#define DATA_LANE_RDY(l) BIT(2 + (l))
128#define CLK_LANE_RDY BIT(1)
129#define PLL_LOCKED BIT(0)
130
131#define MCTL_DPHY_ERR 0x28
132#define MCTL_DPHY_ERR_CTL1 0x148
133#define MCTL_DPHY_ERR_CLR 0x168
134#define MCTL_DPHY_ERR_FLAG 0x188
135#define ERR_CONT_LP(x, l) BIT(18 + ((x) * 4) + (l))
136#define ERR_CONTROL(l) BIT(14 + (l))
137#define ERR_SYNESC(l) BIT(10 + (l))
138#define ERR_ESC(l) BIT(6 + (l))
139
140#define MCTL_DPHY_ERR_CTL2 0x14c
141#define ERR_CONT_LP_EDGE(x, l) BIT(12 + ((x) * 4) + (l))
142#define ERR_CONTROL_EDGE(l) BIT(8 + (l))
143#define ERR_SYN_ESC_EDGE(l) BIT(4 + (l))
144#define ERR_ESC_EDGE(l) BIT(0 + (l))
145
146#define MCTL_LANE_STS 0x2c
147#define PPI_C_TX_READY_HS BIT(18)
148#define DPHY_PLL_LOCK BIT(17)
149#define PPI_D_RX_ULPS_ESC(x) (((x) & GENMASK(15, 12)) >> 12)
150#define LANE_STATE_START 0
151#define LANE_STATE_IDLE 1
152#define LANE_STATE_WRITE 2
153#define LANE_STATE_ULPM 3
154#define LANE_STATE_READ 4
155#define DATA_LANE_STATE(l, val) \
156 (((val) >> (2 + 2 * (l) + ((l) ? 1 : 0))) & GENMASK((l) ? 1 : 2, 0))
157#define CLK_LANE_STATE_HS 2
158#define CLK_LANE_STATE(val) ((val) & GENMASK(1, 0))
159
160#define DSC_MODE_CTL 0x30
161#define DSC_MODE_EN BIT(0)
162
163#define DSC_CMD_SEND 0x34
164#define DSC_SEND_PPS BIT(0)
165#define DSC_EXECUTE_QUEUE BIT(1)
166
167#define DSC_PPS_WRDAT 0x38
168
169#define DSC_MODE_STS 0x3c
170#define DSC_PPS_DONE BIT(1)
171#define DSC_EXEC_DONE BIT(2)
172
173#define CMD_MODE_CTL 0x70
174#define IF_LP_EN(x) BIT(9 + (x))
175#define IF_VCHAN_ID(x, c) ((c) << ((x) * 2))
176
177#define CMD_MODE_CTL2 0x74
178#define TE_TIMEOUT(x) ((x) << 11)
179#define FILL_VALUE(x) ((x) << 3)
180#define ARB_IF_WITH_HIGHEST_PRIORITY(x) ((x) << 1)
181#define ARB_ROUND_ROBIN_MODE BIT(0)
182
183#define CMD_MODE_STS 0x78
184#define CMD_MODE_STS_CTL 0x134
185#define CMD_MODE_STS_CLR 0x154
186#define CMD_MODE_STS_FLAG 0x174
187#define ERR_IF_UNDERRUN(x) BIT(4 + (x))
188#define ERR_UNWANTED_READ BIT(3)
189#define ERR_TE_MISS BIT(2)
190#define ERR_NO_TE BIT(1)
191#define CSM_RUNNING BIT(0)
192
193#define DIRECT_CMD_SEND 0x80
194
195#define DIRECT_CMD_MAIN_SETTINGS 0x84
196#define TRIGGER_VAL(x) ((x) << 25)
197#define CMD_LP_EN BIT(24)
198#define CMD_SIZE(x) ((x) << 16)
199#define CMD_VCHAN_ID(x) ((x) << 14)
200#define CMD_DATATYPE(x) ((x) << 8)
201#define CMD_LONG BIT(3)
202#define WRITE_CMD 0
203#define READ_CMD 1
204#define TE_REQ 4
205#define TRIGGER_REQ 5
206#define BTA_REQ 6
207
208#define DIRECT_CMD_STS 0x88
209#define DIRECT_CMD_STS_CTL 0x138
210#define DIRECT_CMD_STS_CLR 0x158
211#define DIRECT_CMD_STS_FLAG 0x178
212#define RCVD_ACK_VAL(val) ((val) >> 16)
213#define RCVD_TRIGGER_VAL(val) (((val) & GENMASK(14, 11)) >> 11)
214#define READ_COMPLETED_WITH_ERR BIT(10)
215#define BTA_FINISHED BIT(9)
216#define BTA_COMPLETED BIT(8)
217#define TE_RCVD BIT(7)
218#define TRIGGER_RCVD BIT(6)
219#define ACK_WITH_ERR_RCVD BIT(5)
220#define ACK_RCVD BIT(4)
221#define READ_COMPLETED BIT(3)
222#define TRIGGER_COMPLETED BIT(2)
223#define WRITE_COMPLETED BIT(1)
224#define SENDING_CMD BIT(0)
225
226#define DIRECT_CMD_STOP_READ 0x8c
227
228#define DIRECT_CMD_WRDATA 0x90
229
230#define DIRECT_CMD_FIFO_RST 0x94
231
232#define DIRECT_CMD_RDDATA 0xa0
233
234#define DIRECT_CMD_RD_PROPS 0xa4
235#define RD_DCS BIT(18)
236#define RD_VCHAN_ID(val) (((val) >> 16) & GENMASK(1, 0))
237#define RD_SIZE(val) ((val) & GENMASK(15, 0))
238
239#define DIRECT_CMD_RD_STS 0xa8
240#define DIRECT_CMD_RD_STS_CTL 0x13c
241#define DIRECT_CMD_RD_STS_CLR 0x15c
242#define DIRECT_CMD_RD_STS_FLAG 0x17c
243#define ERR_EOT_WITH_ERR BIT(8)
244#define ERR_MISSING_EOT BIT(7)
245#define ERR_WRONG_LENGTH BIT(6)
246#define ERR_OVERSIZE BIT(5)
247#define ERR_RECEIVE BIT(4)
248#define ERR_UNDECODABLE BIT(3)
249#define ERR_CHECKSUM BIT(2)
250#define ERR_UNCORRECTABLE BIT(1)
251#define ERR_FIXED BIT(0)
252
253#define VID_MAIN_CTL 0xb0
254#define VID_IGNORE_MISS_VSYNC BIT(31)
255#define VID_FIELD_SW BIT(28)
256#define VID_INTERLACED_EN BIT(27)
257#define RECOVERY_MODE(x) ((x) << 25)
258#define RECOVERY_MODE_NEXT_HSYNC 0
259#define RECOVERY_MODE_NEXT_STOP_POINT 2
260#define RECOVERY_MODE_NEXT_VSYNC 3
261#define REG_BLKEOL_MODE(x) ((x) << 23)
262#define REG_BLKLINE_MODE(x) ((x) << 21)
263#define REG_BLK_MODE_NULL_PKT 0
264#define REG_BLK_MODE_BLANKING_PKT 1
265#define REG_BLK_MODE_LP 2
266#define SYNC_PULSE_HORIZONTAL BIT(20)
267#define SYNC_PULSE_ACTIVE BIT(19)
268#define BURST_MODE BIT(18)
269#define VID_PIXEL_MODE_MASK GENMASK(17, 14)
270#define VID_PIXEL_MODE_RGB565 (0 << 14)
271#define VID_PIXEL_MODE_RGB666_PACKED (1 << 14)
272#define VID_PIXEL_MODE_RGB666 (2 << 14)
273#define VID_PIXEL_MODE_RGB888 (3 << 14)
274#define VID_PIXEL_MODE_RGB101010 (4 << 14)
275#define VID_PIXEL_MODE_RGB121212 (5 << 14)
276#define VID_PIXEL_MODE_YUV420 (8 << 14)
277#define VID_PIXEL_MODE_YUV422_PACKED (9 << 14)
278#define VID_PIXEL_MODE_YUV422 (10 << 14)
279#define VID_PIXEL_MODE_YUV422_24B (11 << 14)
280#define VID_PIXEL_MODE_DSC_COMP (12 << 14)
281#define VID_DATATYPE(x) ((x) << 8)
282#define VID_VIRTCHAN_ID(iface, x) ((x) << (4 + (iface) * 2))
283#define STOP_MODE(x) ((x) << 2)
284#define START_MODE(x) (x)
285
286#define VID_VSIZE1 0xb4
287#define VFP_LEN(x) ((x) << 12)
288#define VBP_LEN(x) ((x) << 6)
289#define VSA_LEN(x) (x)
290
291#define VID_VSIZE2 0xb8
292#define VACT_LEN(x) (x)
293
294#define VID_HSIZE1 0xc0
295#define HBP_LEN(x) ((x) << 16)
296#define HSA_LEN(x) (x)
297
298#define VID_HSIZE2 0xc4
299#define HFP_LEN(x) ((x) << 16)
300#define HACT_LEN(x) (x)
301
302#define VID_BLKSIZE1 0xcc
303#define BLK_EOL_PKT_LEN(x) ((x) << 15)
304#define BLK_LINE_EVENT_PKT_LEN(x) (x)
305
306#define VID_BLKSIZE2 0xd0
307#define BLK_LINE_PULSE_PKT_LEN(x) (x)
308
309#define VID_PKT_TIME 0xd8
310#define BLK_EOL_DURATION(x) (x)
311
312#define VID_DPHY_TIME 0xdc
313#define REG_WAKEUP_TIME(x) ((x) << 17)
314#define REG_LINE_DURATION(x) (x)
315
316#define VID_ERR_COLOR1 0xe0
317#define COL_GREEN(x) ((x) << 12)
318#define COL_RED(x) (x)
319
320#define VID_ERR_COLOR2 0xe4
321#define PAD_VAL(x) ((x) << 12)
322#define COL_BLUE(x) (x)
323
324#define VID_VPOS 0xe8
325#define LINE_VAL(val) (((val) & GENMASK(14, 2)) >> 2)
326#define LINE_POS(val) ((val) & GENMASK(1, 0))
327
328#define VID_HPOS 0xec
329#define HORIZ_VAL(val) (((val) & GENMASK(17, 3)) >> 3)
330#define HORIZ_POS(val) ((val) & GENMASK(2, 0))
331
332#define VID_MODE_STS 0xf0
333#define VID_MODE_STS_CTL 0x140
334#define VID_MODE_STS_CLR 0x160
335#define VID_MODE_STS_FLAG 0x180
336#define VSG_RECOVERY BIT(10)
337#define ERR_VRS_WRONG_LEN BIT(9)
338#define ERR_LONG_READ BIT(8)
339#define ERR_LINE_WRITE BIT(7)
340#define ERR_BURST_WRITE BIT(6)
341#define ERR_SMALL_HEIGHT BIT(5)
342#define ERR_SMALL_LEN BIT(4)
343#define ERR_MISSING_VSYNC BIT(3)
344#define ERR_MISSING_HSYNC BIT(2)
345#define ERR_MISSING_DATA BIT(1)
346#define VSG_RUNNING BIT(0)
347
348#define VID_VCA_SETTING1 0xf4
349#define BURST_LP BIT(16)
350#define MAX_BURST_LIMIT(x) (x)
351
352#define VID_VCA_SETTING2 0xf8
353#define MAX_LINE_LIMIT(x) ((x) << 16)
354#define EXACT_BURST_LIMIT(x) (x)
355
356#define TVG_CTL 0xfc
357#define TVG_STRIPE_SIZE(x) ((x) << 5)
358#define TVG_MODE_MASK GENMASK(4, 3)
359#define TVG_MODE_SINGLE_COLOR (0 << 3)
360#define TVG_MODE_VSTRIPES (2 << 3)
361#define TVG_MODE_HSTRIPES (3 << 3)
362#define TVG_STOPMODE_MASK GENMASK(2, 1)
363#define TVG_STOPMODE_EOF (0 << 1)
364#define TVG_STOPMODE_EOL (1 << 1)
365#define TVG_STOPMODE_NOW (2 << 1)
366#define TVG_RUN BIT(0)
367
368#define TVG_IMG_SIZE 0x100
369#define TVG_NBLINES(x) ((x) << 16)
370#define TVG_LINE_SIZE(x) (x)
371
372#define TVG_COLOR1 0x104
373#define TVG_COL1_GREEN(x) ((x) << 12)
374#define TVG_COL1_RED(x) (x)
375
376#define TVG_COLOR1_BIS 0x108
377#define TVG_COL1_BLUE(x) (x)
378
379#define TVG_COLOR2 0x10c
380#define TVG_COL2_GREEN(x) ((x) << 12)
381#define TVG_COL2_RED(x) (x)
382
383#define TVG_COLOR2_BIS 0x110
384#define TVG_COL2_BLUE(x) (x)
385
386#define TVG_STS 0x114
387#define TVG_STS_CTL 0x144
388#define TVG_STS_CLR 0x164
389#define TVG_STS_FLAG 0x184
390#define TVG_STS_RUNNING BIT(0)
391
392#define STS_CTL_EDGE(e) ((e) << 16)
393
394#define DPHY_LANES_MAP 0x198
395#define DAT_REMAP_CFG(b, l) ((l) << ((b) * 8))
396
397#define DPI_IRQ_EN 0x1a0
398#define DPI_IRQ_CLR 0x1a4
399#define DPI_IRQ_STS 0x1a8
400#define PIXEL_BUF_OVERFLOW BIT(0)
401
402#define DPI_CFG 0x1ac
403#define DPI_CFG_FIFO_DEPTH(x) ((x) >> 16)
404#define DPI_CFG_FIFO_LEVEL(x) ((x) & GENMASK(15, 0))
405
406#define TEST_GENERIC 0x1f0
407#define TEST_STATUS(x) ((x) >> 16)
408#define TEST_CTRL(x) (x)
409
410#define ID_REG 0x1fc
411#define REV_VENDOR_ID(x) (((x) & GENMASK(31, 20)) >> 20)
412#define REV_PRODUCT_ID(x) (((x) & GENMASK(19, 12)) >> 12)
413#define REV_HW(x) (((x) & GENMASK(11, 8)) >> 8)
414#define REV_MAJOR(x) (((x) & GENMASK(7, 4)) >> 4)
415#define REV_MINOR(x) ((x) & GENMASK(3, 0))
416
417#define DSI_OUTPUT_PORT 0
418#define DSI_INPUT_PORT(inputid) (1 + (inputid))
419
420#define DSI_HBP_FRAME_OVERHEAD 12
421#define DSI_HSA_FRAME_OVERHEAD 14
422#define DSI_HFP_FRAME_OVERHEAD 6
423#define DSI_HSS_VSS_VSE_FRAME_OVERHEAD 4
424#define DSI_BLANKING_FRAME_OVERHEAD 6
425#define DSI_NULL_FRAME_OVERHEAD 6
426#define DSI_EOT_PKT_SIZE 4
427
428static inline struct cdns_dsi *input_to_dsi(struct cdns_dsi_input *input)
429{
430 return container_of(input, struct cdns_dsi, input);
431}
432
433static inline struct cdns_dsi *to_cdns_dsi(struct mipi_dsi_host *host)
434{
435 return container_of(host, struct cdns_dsi, base);
436}
437
438static inline struct cdns_dsi_input *
439bridge_to_cdns_dsi_input(struct drm_bridge *bridge)
440{
441 return container_of(bridge, struct cdns_dsi_input, bridge);
442}
443
444static unsigned int mode_to_dpi_hfp(const struct drm_display_mode *mode,
445 bool mode_valid_check)
446{
447 if (mode_valid_check)
448 return mode->hsync_start - mode->hdisplay;
449
450 return mode->crtc_hsync_start - mode->crtc_hdisplay;
451}
452
453static unsigned int dpi_to_dsi_timing(unsigned int dpi_timing,
454 unsigned int dpi_bpp,
455 unsigned int dsi_pkt_overhead)
456{
457 unsigned int dsi_timing = DIV_ROUND_UP(dpi_timing * dpi_bpp, 8);
458
459 if (dsi_timing < dsi_pkt_overhead)
460 dsi_timing = 0;
461 else
462 dsi_timing -= dsi_pkt_overhead;
463
464 return dsi_timing;
465}
466
467static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi,
468 const struct drm_display_mode *mode,
469 struct cdns_dsi_cfg *dsi_cfg,
470 bool mode_valid_check)
471{
472 struct cdns_dsi_output *output = &dsi->output;
473 unsigned int tmp;
474 bool sync_pulse = false;
475 int bpp;
476
477 memset(dsi_cfg, 0, sizeof(*dsi_cfg));
478
479 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
480 sync_pulse = true;
481
482 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
483
484 if (mode_valid_check)
485 tmp = mode->htotal -
486 (sync_pulse ? mode->hsync_end : mode->hsync_start);
487 else
488 tmp = mode->crtc_htotal -
489 (sync_pulse ?
490 mode->crtc_hsync_end : mode->crtc_hsync_start);
491
492 dsi_cfg->hbp = dpi_to_dsi_timing(tmp, bpp, DSI_HBP_FRAME_OVERHEAD);
493
494 if (sync_pulse) {
495 if (mode_valid_check)
496 tmp = mode->hsync_end - mode->hsync_start;
497 else
498 tmp = mode->crtc_hsync_end - mode->crtc_hsync_start;
499
500 dsi_cfg->hsa = dpi_to_dsi_timing(tmp, bpp,
501 DSI_HSA_FRAME_OVERHEAD);
502 }
503
504 dsi_cfg->hact = dpi_to_dsi_timing(mode_valid_check ?
505 mode->hdisplay : mode->crtc_hdisplay,
506 bpp, 0);
507 dsi_cfg->hfp = dpi_to_dsi_timing(mode_to_dpi_hfp(mode, mode_valid_check),
508 bpp, DSI_HFP_FRAME_OVERHEAD);
509
510 return 0;
511}
512
513static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi,
514 struct cdns_dsi_cfg *dsi_cfg,
515 struct phy_configure_opts_mipi_dphy *phy_cfg,
516 const struct drm_display_mode *mode,
517 bool mode_valid_check)
518{
519 struct cdns_dsi_output *output = &dsi->output;
520 unsigned long long dlane_bps;
521 unsigned long adj_dsi_htotal;
522 unsigned long dsi_htotal;
523 unsigned long dpi_htotal;
524 unsigned long dpi_hz;
525 unsigned int dsi_hfp_ext;
526 unsigned int lanes = output->dev->lanes;
527
528 dsi_htotal = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
529 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
530 dsi_htotal += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
531
532 dsi_htotal += dsi_cfg->hact;
533 dsi_htotal += dsi_cfg->hfp + DSI_HFP_FRAME_OVERHEAD;
534
535 /*
536 * Make sure DSI htotal is aligned on a lane boundary when calculating
537 * the expected data rate. This is done by extending HFP in case of
538 * misalignment.
539 */
540 adj_dsi_htotal = dsi_htotal;
541 if (dsi_htotal % lanes)
542 adj_dsi_htotal += lanes - (dsi_htotal % lanes);
543
544 dpi_hz = (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000;
545 dlane_bps = (unsigned long long)dpi_hz * adj_dsi_htotal;
546
547 /* data rate in bytes/sec is not an integer, refuse the mode. */
548 dpi_htotal = mode_valid_check ? mode->htotal : mode->crtc_htotal;
549 if (do_div(dlane_bps, lanes * dpi_htotal))
550 return -EINVAL;
551
552 /* data rate was in bytes/sec, convert to bits/sec. */
553 phy_cfg->hs_clk_rate = dlane_bps * 8;
554
555 dsi_hfp_ext = adj_dsi_htotal - dsi_htotal;
556 dsi_cfg->hfp += dsi_hfp_ext;
557 dsi_cfg->htotal = dsi_htotal + dsi_hfp_ext;
558
559 return 0;
560}
561
562static int cdns_dsi_check_conf(struct cdns_dsi *dsi,
563 const struct drm_display_mode *mode,
564 struct cdns_dsi_cfg *dsi_cfg,
565 bool mode_valid_check)
566{
567 struct cdns_dsi_output *output = &dsi->output;
568 struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
569 unsigned long dsi_hss_hsa_hse_hbp;
570 unsigned int nlanes = output->dev->lanes;
571 int ret;
572
573 ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check);
574 if (ret)
575 return ret;
576
577 phy_mipi_dphy_get_default_config(mode->crtc_clock * 1000,
578 mipi_dsi_pixel_format_to_bpp(output->dev->format),
579 nlanes, phy_cfg);
580
581 ret = cdns_dsi_adjust_phy_config(dsi, dsi_cfg, phy_cfg, mode, mode_valid_check);
582 if (ret)
583 return ret;
584
585 ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &output->phy_opts);
586 if (ret)
587 return ret;
588
589 dsi_hss_hsa_hse_hbp = dsi_cfg->hbp + DSI_HBP_FRAME_OVERHEAD;
590 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
591 dsi_hss_hsa_hse_hbp += dsi_cfg->hsa + DSI_HSA_FRAME_OVERHEAD;
592
593 /*
594 * Make sure DPI(HFP) > DSI(HSS+HSA+HSE+HBP) to guarantee that the FIFO
595 * is empty before we start a receiving a new line on the DPI
596 * interface.
597 */
598 if ((u64)phy_cfg->hs_clk_rate *
599 mode_to_dpi_hfp(mode, mode_valid_check) * nlanes <
600 (u64)dsi_hss_hsa_hse_hbp *
601 (mode_valid_check ? mode->clock : mode->crtc_clock) * 1000)
602 return -EINVAL;
603
604 return 0;
605}
606
607static int cdns_dsi_bridge_attach(struct drm_bridge *bridge,
608 enum drm_bridge_attach_flags flags)
609{
610 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
611 struct cdns_dsi *dsi = input_to_dsi(input);
612 struct cdns_dsi_output *output = &dsi->output;
613
614 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
615 dev_err(dsi->base.dev,
616 "cdns-dsi driver is only compatible with DRM devices supporting atomic updates");
617 return -ENOTSUPP;
618 }
619
620 return drm_bridge_attach(bridge->encoder, output->bridge, bridge,
621 flags);
622}
623
624static enum drm_mode_status
625cdns_dsi_bridge_mode_valid(struct drm_bridge *bridge,
626 const struct drm_display_info *info,
627 const struct drm_display_mode *mode)
628{
629 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
630 struct cdns_dsi *dsi = input_to_dsi(input);
631 struct cdns_dsi_output *output = &dsi->output;
632 struct cdns_dsi_cfg dsi_cfg;
633 int bpp, ret;
634
635 /*
636 * VFP_DSI should be less than VFP_DPI and VFP_DSI should be at
637 * least 1.
638 */
639 if (mode->vtotal - mode->vsync_end < 2)
640 return MODE_V_ILLEGAL;
641
642 /* VSA_DSI = VSA_DPI and must be at least 2. */
643 if (mode->vsync_end - mode->vsync_start < 2)
644 return MODE_V_ILLEGAL;
645
646 /* HACT must be 32-bits aligned. */
647 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format);
648 if ((mode->hdisplay * bpp) % 32)
649 return MODE_H_ILLEGAL;
650
651 ret = cdns_dsi_check_conf(dsi, mode, &dsi_cfg, true);
652 if (ret)
653 return MODE_BAD;
654
655 return MODE_OK;
656}
657
658static void cdns_dsi_bridge_disable(struct drm_bridge *bridge)
659{
660 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
661 struct cdns_dsi *dsi = input_to_dsi(input);
662 u32 val;
663
664 val = readl(dsi->regs + MCTL_MAIN_DATA_CTL);
665 val &= ~(IF_VID_SELECT_MASK | IF_VID_MODE | VID_EN | HOST_EOT_GEN |
666 DISP_EOT_GEN);
667 writel(val, dsi->regs + MCTL_MAIN_DATA_CTL);
668
669 val = readl(dsi->regs + MCTL_MAIN_EN) & ~IF_EN(input->id);
670 writel(val, dsi->regs + MCTL_MAIN_EN);
671
672 if (dsi->platform_ops && dsi->platform_ops->disable)
673 dsi->platform_ops->disable(dsi);
674
675 pm_runtime_put(dsi->base.dev);
676}
677
678static void cdns_dsi_bridge_post_disable(struct drm_bridge *bridge)
679{
680 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
681 struct cdns_dsi *dsi = input_to_dsi(input);
682
683 pm_runtime_put(dsi->base.dev);
684}
685
686static void cdns_dsi_hs_init(struct cdns_dsi *dsi)
687{
688 struct cdns_dsi_output *output = &dsi->output;
689 u32 status;
690
691 if (dsi->phy_initialized)
692 return;
693 /*
694 * Power all internal DPHY blocks down and maintain their reset line
695 * asserted before changing the DPHY config.
696 */
697 writel(DPHY_CMN_PSO | DPHY_PLL_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN |
698 DPHY_CMN_PDN | DPHY_PLL_PDN,
699 dsi->regs + MCTL_DPHY_CFG0);
700
701 phy_init(dsi->dphy);
702 phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY);
703 phy_configure(dsi->dphy, &output->phy_opts);
704 phy_power_on(dsi->dphy);
705
706 /* Activate the PLL and wait until it's locked. */
707 writel(PLL_LOCKED, dsi->regs + MCTL_MAIN_STS_CLR);
708 writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN,
709 dsi->regs + MCTL_DPHY_CFG0);
710 WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
711 status & PLL_LOCKED, 100, 100));
712 /* De-assert data and clock reset lines. */
713 writel(DPHY_CMN_PSO | DPHY_ALL_D_PDN | DPHY_C_PDN | DPHY_CMN_PDN |
714 DPHY_D_RSTB(output->dev->lanes) | DPHY_C_RSTB,
715 dsi->regs + MCTL_DPHY_CFG0);
716 dsi->phy_initialized = true;
717}
718
719static void cdns_dsi_init_link(struct cdns_dsi *dsi)
720{
721 struct cdns_dsi_output *output = &dsi->output;
722 unsigned long sysclk_period, ulpout;
723 u32 val;
724 int i;
725
726 if (dsi->link_initialized)
727 return;
728
729 val = 0;
730 for (i = 1; i < output->dev->lanes; i++)
731 val |= DATA_LANE_EN(i);
732
733 if (!(output->dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
734 val |= CLK_CONTINUOUS;
735
736 writel(val, dsi->regs + MCTL_MAIN_PHY_CTL);
737
738 /* ULPOUT should be set to 1ms and is expressed in sysclk cycles. */
739 sysclk_period = NSEC_PER_SEC / clk_get_rate(dsi->dsi_sys_clk);
740 ulpout = DIV_ROUND_UP(NSEC_PER_MSEC, sysclk_period);
741 writel(CLK_LANE_ULPOUT_TIME(ulpout) | DATA_LANE_ULPOUT_TIME(ulpout),
742 dsi->regs + MCTL_ULPOUT_TIME);
743
744 writel(LINK_EN, dsi->regs + MCTL_MAIN_DATA_CTL);
745
746 val = CLK_LANE_EN | PLL_START;
747 for (i = 0; i < output->dev->lanes; i++)
748 val |= DATA_LANE_START(i);
749
750 writel(val, dsi->regs + MCTL_MAIN_EN);
751
752 dsi->link_initialized = true;
753}
754
755static void cdns_dsi_bridge_enable(struct drm_bridge *bridge)
756{
757 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
758 struct cdns_dsi *dsi = input_to_dsi(input);
759 struct cdns_dsi_output *output = &dsi->output;
760 struct drm_display_mode *mode;
761 struct phy_configure_opts_mipi_dphy *phy_cfg = &output->phy_opts.mipi_dphy;
762 unsigned long tx_byte_period;
763 struct cdns_dsi_cfg dsi_cfg;
764 u32 tmp, reg_wakeup, div;
765 int nlanes;
766
767 if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
768 return;
769
770 if (dsi->platform_ops && dsi->platform_ops->enable)
771 dsi->platform_ops->enable(dsi);
772
773 mode = &bridge->encoder->crtc->state->adjusted_mode;
774 nlanes = output->dev->lanes;
775
776 WARN_ON_ONCE(cdns_dsi_check_conf(dsi, mode, &dsi_cfg, false));
777
778 cdns_dsi_hs_init(dsi);
779 cdns_dsi_init_link(dsi);
780
781 writel(HBP_LEN(dsi_cfg.hbp) | HSA_LEN(dsi_cfg.hsa),
782 dsi->regs + VID_HSIZE1);
783 writel(HFP_LEN(dsi_cfg.hfp) | HACT_LEN(dsi_cfg.hact),
784 dsi->regs + VID_HSIZE2);
785
786 writel(VBP_LEN(mode->crtc_vtotal - mode->crtc_vsync_end - 1) |
787 VFP_LEN(mode->crtc_vsync_start - mode->crtc_vdisplay) |
788 VSA_LEN(mode->crtc_vsync_end - mode->crtc_vsync_start + 1),
789 dsi->regs + VID_VSIZE1);
790 writel(mode->crtc_vdisplay, dsi->regs + VID_VSIZE2);
791
792 tmp = dsi_cfg.htotal -
793 (dsi_cfg.hsa + DSI_BLANKING_FRAME_OVERHEAD +
794 DSI_HSA_FRAME_OVERHEAD);
795 writel(BLK_LINE_PULSE_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE2);
796 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
797 writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
798 dsi->regs + VID_VCA_SETTING2);
799
800 tmp = dsi_cfg.htotal -
801 (DSI_HSS_VSS_VSE_FRAME_OVERHEAD + DSI_BLANKING_FRAME_OVERHEAD);
802 writel(BLK_LINE_EVENT_PKT_LEN(tmp), dsi->regs + VID_BLKSIZE1);
803 if (!(output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
804 writel(MAX_LINE_LIMIT(tmp - DSI_NULL_FRAME_OVERHEAD),
805 dsi->regs + VID_VCA_SETTING2);
806
807 tmp = DIV_ROUND_UP(dsi_cfg.htotal, nlanes) -
808 DIV_ROUND_UP(dsi_cfg.hsa, nlanes);
809
810 if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
811 tmp -= DIV_ROUND_UP(DSI_EOT_PKT_SIZE, nlanes);
812
813 tx_byte_period = DIV_ROUND_DOWN_ULL((u64)NSEC_PER_SEC * 8,
814 phy_cfg->hs_clk_rate);
815 reg_wakeup = (phy_cfg->hs_prepare + phy_cfg->hs_zero) / tx_byte_period;
816 writel(REG_WAKEUP_TIME(reg_wakeup) | REG_LINE_DURATION(tmp),
817 dsi->regs + VID_DPHY_TIME);
818
819 /*
820 * HSTX and LPRX timeouts are both expressed in TX byte clk cycles and
821 * both should be set to at least the time it takes to transmit a
822 * frame.
823 */
824 tmp = NSEC_PER_SEC / drm_mode_vrefresh(mode);
825 tmp /= tx_byte_period;
826
827 for (div = 0; div <= CLK_DIV_MAX; div++) {
828 if (tmp <= HSTX_TIMEOUT_MAX)
829 break;
830
831 tmp >>= 1;
832 }
833
834 if (tmp > HSTX_TIMEOUT_MAX)
835 tmp = HSTX_TIMEOUT_MAX;
836
837 writel(CLK_DIV(div) | HSTX_TIMEOUT(tmp),
838 dsi->regs + MCTL_DPHY_TIMEOUT1);
839
840 writel(LPRX_TIMEOUT(tmp), dsi->regs + MCTL_DPHY_TIMEOUT2);
841
842 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO) {
843 switch (output->dev->format) {
844 case MIPI_DSI_FMT_RGB888:
845 tmp = VID_PIXEL_MODE_RGB888 |
846 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_24);
847 break;
848
849 case MIPI_DSI_FMT_RGB666:
850 tmp = VID_PIXEL_MODE_RGB666 |
851 VID_DATATYPE(MIPI_DSI_PIXEL_STREAM_3BYTE_18);
852 break;
853
854 case MIPI_DSI_FMT_RGB666_PACKED:
855 tmp = VID_PIXEL_MODE_RGB666_PACKED |
856 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_18);
857 break;
858
859 case MIPI_DSI_FMT_RGB565:
860 tmp = VID_PIXEL_MODE_RGB565 |
861 VID_DATATYPE(MIPI_DSI_PACKED_PIXEL_STREAM_16);
862 break;
863
864 default:
865 dev_err(dsi->base.dev, "Unsupported DSI format\n");
866 return;
867 }
868
869 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
870 tmp |= SYNC_PULSE_ACTIVE | SYNC_PULSE_HORIZONTAL;
871
872 tmp |= REG_BLKLINE_MODE(REG_BLK_MODE_BLANKING_PKT) |
873 REG_BLKEOL_MODE(REG_BLK_MODE_BLANKING_PKT) |
874 RECOVERY_MODE(RECOVERY_MODE_NEXT_HSYNC) |
875 VID_IGNORE_MISS_VSYNC;
876
877 writel(tmp, dsi->regs + VID_MAIN_CTL);
878 }
879
880 tmp = readl(dsi->regs + MCTL_MAIN_DATA_CTL);
881 tmp &= ~(IF_VID_SELECT_MASK | HOST_EOT_GEN | IF_VID_MODE);
882
883 if (!(output->dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET))
884 tmp |= HOST_EOT_GEN;
885
886 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO)
887 tmp |= IF_VID_MODE | IF_VID_SELECT(input->id) | VID_EN;
888
889 writel(tmp, dsi->regs + MCTL_MAIN_DATA_CTL);
890
891 tmp = readl(dsi->regs + MCTL_MAIN_EN) | IF_EN(input->id);
892 writel(tmp, dsi->regs + MCTL_MAIN_EN);
893}
894
895static void cdns_dsi_bridge_pre_enable(struct drm_bridge *bridge)
896{
897 struct cdns_dsi_input *input = bridge_to_cdns_dsi_input(bridge);
898 struct cdns_dsi *dsi = input_to_dsi(input);
899
900 if (WARN_ON(pm_runtime_get_sync(dsi->base.dev) < 0))
901 return;
902
903 cdns_dsi_init_link(dsi);
904 cdns_dsi_hs_init(dsi);
905}
906
907static const struct drm_bridge_funcs cdns_dsi_bridge_funcs = {
908 .attach = cdns_dsi_bridge_attach,
909 .mode_valid = cdns_dsi_bridge_mode_valid,
910 .disable = cdns_dsi_bridge_disable,
911 .pre_enable = cdns_dsi_bridge_pre_enable,
912 .enable = cdns_dsi_bridge_enable,
913 .post_disable = cdns_dsi_bridge_post_disable,
914};
915
916static int cdns_dsi_attach(struct mipi_dsi_host *host,
917 struct mipi_dsi_device *dev)
918{
919 struct cdns_dsi *dsi = to_cdns_dsi(host);
920 struct cdns_dsi_output *output = &dsi->output;
921 struct cdns_dsi_input *input = &dsi->input;
922 struct drm_bridge *bridge;
923 struct drm_panel *panel;
924 struct device_node *np;
925 int ret;
926
927 /*
928 * We currently do not support connecting several DSI devices to the
929 * same host. In order to support that we'd need the DRM bridge
930 * framework to allow dynamic reconfiguration of the bridge chain.
931 */
932 if (output->dev)
933 return -EBUSY;
934
935 /* We do not support burst mode yet. */
936 if (dev->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
937 return -ENOTSUPP;
938
939 /*
940 * The host <-> device link might be described using an OF-graph
941 * representation, in this case we extract the device of_node from
942 * this representation, otherwise we use dsidev->dev.of_node which
943 * should have been filled by the core.
944 */
945 np = of_graph_get_remote_node(dsi->base.dev->of_node, DSI_OUTPUT_PORT,
946 dev->channel);
947 if (!np)
948 np = of_node_get(dev->dev.of_node);
949
950 panel = of_drm_find_panel(np);
951 if (!IS_ERR(panel)) {
952 bridge = drm_panel_bridge_add_typed(panel,
953 DRM_MODE_CONNECTOR_DSI);
954 } else {
955 bridge = of_drm_find_bridge(dev->dev.of_node);
956 if (!bridge)
957 bridge = ERR_PTR(-EINVAL);
958 }
959
960 of_node_put(np);
961
962 if (IS_ERR(bridge)) {
963 ret = PTR_ERR(bridge);
964 dev_err(host->dev, "failed to add DSI device %s (err = %d)",
965 dev->name, ret);
966 return ret;
967 }
968
969 output->dev = dev;
970 output->bridge = bridge;
971 output->panel = panel;
972
973 /*
974 * The DSI output has been properly configured, we can now safely
975 * register the input to the bridge framework so that it can take place
976 * in a display pipeline.
977 */
978 drm_bridge_add(&input->bridge);
979
980 return 0;
981}
982
983static int cdns_dsi_detach(struct mipi_dsi_host *host,
984 struct mipi_dsi_device *dev)
985{
986 struct cdns_dsi *dsi = to_cdns_dsi(host);
987 struct cdns_dsi_output *output = &dsi->output;
988 struct cdns_dsi_input *input = &dsi->input;
989
990 drm_bridge_remove(&input->bridge);
991 if (output->panel)
992 drm_panel_bridge_remove(output->bridge);
993
994 return 0;
995}
996
997static irqreturn_t cdns_dsi_interrupt(int irq, void *data)
998{
999 struct cdns_dsi *dsi = data;
1000 irqreturn_t ret = IRQ_NONE;
1001 u32 flag, ctl;
1002
1003 flag = readl(dsi->regs + DIRECT_CMD_STS_FLAG);
1004 if (flag) {
1005 ctl = readl(dsi->regs + DIRECT_CMD_STS_CTL);
1006 ctl &= ~flag;
1007 writel(ctl, dsi->regs + DIRECT_CMD_STS_CTL);
1008 complete(&dsi->direct_cmd_comp);
1009 ret = IRQ_HANDLED;
1010 }
1011
1012 return ret;
1013}
1014
1015static ssize_t cdns_dsi_transfer(struct mipi_dsi_host *host,
1016 const struct mipi_dsi_msg *msg)
1017{
1018 struct cdns_dsi *dsi = to_cdns_dsi(host);
1019 u32 cmd, sts, val, wait = WRITE_COMPLETED, ctl = 0;
1020 struct mipi_dsi_packet packet;
1021 int ret, i, tx_len, rx_len;
1022
1023 ret = pm_runtime_resume_and_get(host->dev);
1024 if (ret < 0)
1025 return ret;
1026
1027 cdns_dsi_init_link(dsi);
1028
1029 ret = mipi_dsi_create_packet(&packet, msg);
1030 if (ret)
1031 goto out;
1032
1033 tx_len = msg->tx_buf ? msg->tx_len : 0;
1034 rx_len = msg->rx_buf ? msg->rx_len : 0;
1035
1036 /* For read operations, the maximum TX len is 2. */
1037 if (rx_len && tx_len > 2) {
1038 ret = -ENOTSUPP;
1039 goto out;
1040 }
1041
1042 /* TX len is limited by the CMD FIFO depth. */
1043 if (tx_len > dsi->direct_cmd_fifo_depth) {
1044 ret = -ENOTSUPP;
1045 goto out;
1046 }
1047
1048 /* RX len is limited by the RX FIFO depth. */
1049 if (rx_len > dsi->rx_fifo_depth) {
1050 ret = -ENOTSUPP;
1051 goto out;
1052 }
1053
1054 cmd = CMD_SIZE(tx_len) | CMD_VCHAN_ID(msg->channel) |
1055 CMD_DATATYPE(msg->type);
1056
1057 if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1058 cmd |= CMD_LP_EN;
1059
1060 if (mipi_dsi_packet_format_is_long(msg->type))
1061 cmd |= CMD_LONG;
1062
1063 if (rx_len) {
1064 cmd |= READ_CMD;
1065 wait = READ_COMPLETED_WITH_ERR | READ_COMPLETED;
1066 ctl = READ_EN | BTA_EN;
1067 } else if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
1068 cmd |= BTA_REQ;
1069 wait = ACK_WITH_ERR_RCVD | ACK_RCVD;
1070 ctl = BTA_EN;
1071 }
1072
1073 writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) | ctl,
1074 dsi->regs + MCTL_MAIN_DATA_CTL);
1075
1076 writel(cmd, dsi->regs + DIRECT_CMD_MAIN_SETTINGS);
1077
1078 for (i = 0; i < tx_len; i += 4) {
1079 const u8 *buf = msg->tx_buf;
1080 int j;
1081
1082 val = 0;
1083 for (j = 0; j < 4 && j + i < tx_len; j++)
1084 val |= (u32)buf[i + j] << (8 * j);
1085
1086 writel(val, dsi->regs + DIRECT_CMD_WRDATA);
1087 }
1088
1089 /* Clear status flags before sending the command. */
1090 writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
1091 writel(wait, dsi->regs + DIRECT_CMD_STS_CTL);
1092 reinit_completion(&dsi->direct_cmd_comp);
1093 writel(0, dsi->regs + DIRECT_CMD_SEND);
1094
1095 wait_for_completion_timeout(&dsi->direct_cmd_comp,
1096 msecs_to_jiffies(1000));
1097
1098 sts = readl(dsi->regs + DIRECT_CMD_STS);
1099 writel(wait, dsi->regs + DIRECT_CMD_STS_CLR);
1100 writel(0, dsi->regs + DIRECT_CMD_STS_CTL);
1101
1102 writel(readl(dsi->regs + MCTL_MAIN_DATA_CTL) & ~ctl,
1103 dsi->regs + MCTL_MAIN_DATA_CTL);
1104
1105 /* We did not receive the events we were waiting for. */
1106 if (!(sts & wait)) {
1107 ret = -ETIMEDOUT;
1108 goto out;
1109 }
1110
1111 /* 'READ' or 'WRITE with ACK' failed. */
1112 if (sts & (READ_COMPLETED_WITH_ERR | ACK_WITH_ERR_RCVD)) {
1113 ret = -EIO;
1114 goto out;
1115 }
1116
1117 for (i = 0; i < rx_len; i += 4) {
1118 u8 *buf = msg->rx_buf;
1119 int j;
1120
1121 val = readl(dsi->regs + DIRECT_CMD_RDDATA);
1122 for (j = 0; j < 4 && j + i < rx_len; j++)
1123 buf[i + j] = val >> (8 * j);
1124 }
1125
1126out:
1127 pm_runtime_put(host->dev);
1128 return ret;
1129}
1130
1131static const struct mipi_dsi_host_ops cdns_dsi_ops = {
1132 .attach = cdns_dsi_attach,
1133 .detach = cdns_dsi_detach,
1134 .transfer = cdns_dsi_transfer,
1135};
1136
1137static int __maybe_unused cdns_dsi_resume(struct device *dev)
1138{
1139 struct cdns_dsi *dsi = dev_get_drvdata(dev);
1140
1141 reset_control_deassert(dsi->dsi_p_rst);
1142 clk_prepare_enable(dsi->dsi_p_clk);
1143 clk_prepare_enable(dsi->dsi_sys_clk);
1144
1145 return 0;
1146}
1147
1148static int __maybe_unused cdns_dsi_suspend(struct device *dev)
1149{
1150 struct cdns_dsi *dsi = dev_get_drvdata(dev);
1151
1152 clk_disable_unprepare(dsi->dsi_sys_clk);
1153 clk_disable_unprepare(dsi->dsi_p_clk);
1154 reset_control_assert(dsi->dsi_p_rst);
1155 dsi->link_initialized = false;
1156 return 0;
1157}
1158
1159static UNIVERSAL_DEV_PM_OPS(cdns_dsi_pm_ops, cdns_dsi_suspend, cdns_dsi_resume,
1160 NULL);
1161
1162static int cdns_dsi_drm_probe(struct platform_device *pdev)
1163{
1164 struct cdns_dsi *dsi;
1165 struct cdns_dsi_input *input;
1166 int ret, irq;
1167 u32 val;
1168
1169 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1170 if (!dsi)
1171 return -ENOMEM;
1172
1173 platform_set_drvdata(pdev, dsi);
1174
1175 input = &dsi->input;
1176
1177 dsi->regs = devm_platform_ioremap_resource(pdev, 0);
1178 if (IS_ERR(dsi->regs))
1179 return PTR_ERR(dsi->regs);
1180
1181 dsi->dsi_p_clk = devm_clk_get(&pdev->dev, "dsi_p_clk");
1182 if (IS_ERR(dsi->dsi_p_clk))
1183 return PTR_ERR(dsi->dsi_p_clk);
1184
1185 dsi->dsi_p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
1186 "dsi_p_rst");
1187 if (IS_ERR(dsi->dsi_p_rst))
1188 return PTR_ERR(dsi->dsi_p_rst);
1189
1190 dsi->dsi_sys_clk = devm_clk_get(&pdev->dev, "dsi_sys_clk");
1191 if (IS_ERR(dsi->dsi_sys_clk))
1192 return PTR_ERR(dsi->dsi_sys_clk);
1193
1194 irq = platform_get_irq(pdev, 0);
1195 if (irq < 0)
1196 return irq;
1197
1198 dsi->dphy = devm_phy_get(&pdev->dev, "dphy");
1199 if (IS_ERR(dsi->dphy))
1200 return PTR_ERR(dsi->dphy);
1201
1202 ret = clk_prepare_enable(dsi->dsi_p_clk);
1203 if (ret)
1204 return ret;
1205
1206 val = readl(dsi->regs + ID_REG);
1207 if (REV_VENDOR_ID(val) != 0xcad) {
1208 dev_err(&pdev->dev, "invalid vendor id\n");
1209 ret = -EINVAL;
1210 goto err_disable_pclk;
1211 }
1212
1213 dsi->platform_ops = of_device_get_match_data(&pdev->dev);
1214
1215 val = readl(dsi->regs + IP_CONF);
1216 dsi->direct_cmd_fifo_depth = 1 << (DIRCMD_FIFO_DEPTH(val) + 2);
1217 dsi->rx_fifo_depth = RX_FIFO_DEPTH(val);
1218 init_completion(&dsi->direct_cmd_comp);
1219
1220 writel(0, dsi->regs + MCTL_MAIN_DATA_CTL);
1221 writel(0, dsi->regs + MCTL_MAIN_EN);
1222 writel(0, dsi->regs + MCTL_MAIN_PHY_CTL);
1223
1224 /*
1225 * We only support the DPI input, so force input->id to
1226 * CDNS_DPI_INPUT.
1227 */
1228 input->id = CDNS_DPI_INPUT;
1229 input->bridge.funcs = &cdns_dsi_bridge_funcs;
1230 input->bridge.of_node = pdev->dev.of_node;
1231
1232 /* Mask all interrupts before registering the IRQ handler. */
1233 writel(0, dsi->regs + MCTL_MAIN_STS_CTL);
1234 writel(0, dsi->regs + MCTL_DPHY_ERR_CTL1);
1235 writel(0, dsi->regs + CMD_MODE_STS_CTL);
1236 writel(0, dsi->regs + DIRECT_CMD_STS_CTL);
1237 writel(0, dsi->regs + DIRECT_CMD_RD_STS_CTL);
1238 writel(0, dsi->regs + VID_MODE_STS_CTL);
1239 writel(0, dsi->regs + TVG_STS_CTL);
1240 writel(0, dsi->regs + DPI_IRQ_EN);
1241 ret = devm_request_irq(&pdev->dev, irq, cdns_dsi_interrupt, 0,
1242 dev_name(&pdev->dev), dsi);
1243 if (ret)
1244 goto err_disable_pclk;
1245
1246 pm_runtime_enable(&pdev->dev);
1247 dsi->base.dev = &pdev->dev;
1248 dsi->base.ops = &cdns_dsi_ops;
1249
1250 if (dsi->platform_ops && dsi->platform_ops->init) {
1251 ret = dsi->platform_ops->init(dsi);
1252 if (ret != 0) {
1253 dev_err(&pdev->dev, "platform initialization failed: %d\n",
1254 ret);
1255 goto err_disable_runtime_pm;
1256 }
1257 }
1258
1259 ret = mipi_dsi_host_register(&dsi->base);
1260 if (ret)
1261 goto err_deinit_platform;
1262
1263 clk_disable_unprepare(dsi->dsi_p_clk);
1264
1265 return 0;
1266
1267err_deinit_platform:
1268 if (dsi->platform_ops && dsi->platform_ops->deinit)
1269 dsi->platform_ops->deinit(dsi);
1270
1271err_disable_runtime_pm:
1272 pm_runtime_disable(&pdev->dev);
1273
1274err_disable_pclk:
1275 clk_disable_unprepare(dsi->dsi_p_clk);
1276
1277 return ret;
1278}
1279
1280static void cdns_dsi_drm_remove(struct platform_device *pdev)
1281{
1282 struct cdns_dsi *dsi = platform_get_drvdata(pdev);
1283
1284 mipi_dsi_host_unregister(&dsi->base);
1285
1286 if (dsi->platform_ops && dsi->platform_ops->deinit)
1287 dsi->platform_ops->deinit(dsi);
1288
1289 pm_runtime_disable(&pdev->dev);
1290}
1291
1292static const struct of_device_id cdns_dsi_of_match[] = {
1293 { .compatible = "cdns,dsi" },
1294#ifdef CONFIG_DRM_CDNS_DSI_J721E
1295 { .compatible = "ti,j721e-dsi", .data = &dsi_ti_j721e_ops, },
1296#endif
1297 { },
1298};
1299MODULE_DEVICE_TABLE(of, cdns_dsi_of_match);
1300
1301static struct platform_driver cdns_dsi_platform_driver = {
1302 .probe = cdns_dsi_drm_probe,
1303 .remove_new = cdns_dsi_drm_remove,
1304 .driver = {
1305 .name = "cdns-dsi",
1306 .of_match_table = cdns_dsi_of_match,
1307 .pm = &cdns_dsi_pm_ops,
1308 },
1309};
1310module_platform_driver(cdns_dsi_platform_driver);
1311
1312MODULE_AUTHOR("Boris Brezillon <boris.brezillon@bootlin.com>");
1313MODULE_DESCRIPTION("Cadence DSI driver");
1314MODULE_LICENSE("GPL");
1315MODULE_ALIAS("platform:cdns-dsi");
1316