1/*
   2 * Copyright 2017 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Rafał Miłecki <zajec5@gmail.com>
  23 *          Alex Deucher <alexdeucher@gmail.com>
  24 */
  25
  26#include "amdgpu.h"
  27#include "amdgpu_drv.h"
  28#include "amdgpu_pm.h"
  29#include "amdgpu_dpm.h"
  30#include "atom.h"
  31#include <linux/pci.h>
  32#include <linux/hwmon.h>
  33#include <linux/hwmon-sysfs.h>
  34#include <linux/nospec.h>
  35#include <linux/pm_runtime.h>
  36#include <asm/processor.h>
  37
  38#define MAX_NUM_OF_FEATURES_PER_SUBSET		8
  39#define MAX_NUM_OF_SUBSETS			8
  40
  41struct od_attribute {
  42	struct kobj_attribute	attribute;
  43	struct list_head	entry;
  44};
  45
  46struct od_kobj {
  47	struct kobject		kobj;
  48	struct list_head	entry;
  49	struct list_head	attribute;
  50	void			*priv;
  51};
  52
  53struct od_feature_ops {
  54	umode_t (*is_visible)(struct amdgpu_device *adev);
  55	ssize_t (*show)(struct kobject *kobj, struct kobj_attribute *attr,
  56			char *buf);
  57	ssize_t (*store)(struct kobject *kobj, struct kobj_attribute *attr,
  58			 const char *buf, size_t count);
  59};
  60
  61struct od_feature_item {
  62	const char		*name;
  63	struct od_feature_ops	ops;
  64};
  65
  66struct od_feature_container {
  67	char				*name;
  68	struct od_feature_ops		ops;
  69	struct od_feature_item		sub_feature[MAX_NUM_OF_FEATURES_PER_SUBSET];
  70};
  71
  72struct od_feature_set {
  73	struct od_feature_container	containers[MAX_NUM_OF_SUBSETS];
  74};
  75
  76static const struct hwmon_temp_label {
  77	enum PP_HWMON_TEMP channel;
  78	const char *label;
  79} temp_label[] = {
  80	{PP_TEMP_EDGE, "edge"},
  81	{PP_TEMP_JUNCTION, "junction"},
  82	{PP_TEMP_MEM, "mem"},
  83};
  84
  85const char * const amdgpu_pp_profile_name[] = {
  86	"BOOTUP_DEFAULT",
  87	"3D_FULL_SCREEN",
  88	"POWER_SAVING",
  89	"VIDEO",
  90	"VR",
  91	"COMPUTE",
  92	"CUSTOM",
  93	"WINDOW_3D",
  94	"CAPPED",
  95	"UNCAPPED",
  96};
  97
  98/**
  99 * DOC: power_dpm_state
 100 *
 101 * The power_dpm_state file is a legacy interface and is only provided for
 102 * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
 103 * certain power related parameters.  The file power_dpm_state is used for this.
 104 * It accepts the following arguments:
 105 *
 106 * - battery
 107 *
 108 * - balanced
 109 *
 110 * - performance
 111 *
 112 * battery
 113 *
 114 * On older GPUs, the vbios provided a special power state for battery
 115 * operation.  Selecting battery switched to this state.  This is no
 116 * longer provided on newer GPUs so the option does nothing in that case.
 117 *
 118 * balanced
 119 *
 120 * On older GPUs, the vbios provided a special power state for balanced
 121 * operation.  Selecting balanced switched to this state.  This is no
 122 * longer provided on newer GPUs so the option does nothing in that case.
 123 *
 124 * performance
 125 *
 126 * On older GPUs, the vbios provided a special power state for performance
 127 * operation.  Selecting performance switched to this state.  This is no
 128 * longer provided on newer GPUs so the option does nothing in that case.
 129 *
 130 */
 131
 132static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 133					  struct device_attribute *attr,
 134					  char *buf)
 135{
 136	struct drm_device *ddev = dev_get_drvdata(dev);
 137	struct amdgpu_device *adev = drm_to_adev(ddev);
 138	enum amd_pm_state_type pm;
 139	int ret;
 140
 141	if (amdgpu_in_reset(adev))
 142		return -EPERM;
 143	if (adev->in_suspend && !adev->in_runpm)
 144		return -EPERM;
 145
 146	ret = pm_runtime_get_sync(ddev->dev);
 147	if (ret < 0) {
 148		pm_runtime_put_autosuspend(ddev->dev);
 149		return ret;
 150	}
 151
 152	amdgpu_dpm_get_current_power_state(adev, &pm);
 153
 154	pm_runtime_mark_last_busy(ddev->dev);
 155	pm_runtime_put_autosuspend(ddev->dev);
 156
 157	return sysfs_emit(buf, "%s\n",
 158			  (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 159			  (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 160}
 161
 162static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 163					  struct device_attribute *attr,
 164					  const char *buf,
 165					  size_t count)
 166{
 167	struct drm_device *ddev = dev_get_drvdata(dev);
 168	struct amdgpu_device *adev = drm_to_adev(ddev);
 169	enum amd_pm_state_type  state;
 170	int ret;
 171
 172	if (amdgpu_in_reset(adev))
 173		return -EPERM;
 174	if (adev->in_suspend && !adev->in_runpm)
 175		return -EPERM;
 176
 177	if (strncmp("battery", buf, strlen("battery")) == 0)
 178		state = POWER_STATE_TYPE_BATTERY;
 179	else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 180		state = POWER_STATE_TYPE_BALANCED;
 181	else if (strncmp("performance", buf, strlen("performance")) == 0)
 182		state = POWER_STATE_TYPE_PERFORMANCE;
 183	else
 184		return -EINVAL;
 185
 186	ret = pm_runtime_get_sync(ddev->dev);
 187	if (ret < 0) {
 188		pm_runtime_put_autosuspend(ddev->dev);
 189		return ret;
 190	}
 191
 192	amdgpu_dpm_set_power_state(adev, state);
 193
 194	pm_runtime_mark_last_busy(ddev->dev);
 195	pm_runtime_put_autosuspend(ddev->dev);
 196
 197	return count;
 198}
 199
 200
 201/**
 202 * DOC: power_dpm_force_performance_level
 203 *
 204 * The amdgpu driver provides a sysfs API for adjusting certain power
 205 * related parameters.  The file power_dpm_force_performance_level is
 206 * used for this.  It accepts the following arguments:
 207 *
 208 * - auto
 209 *
 210 * - low
 211 *
 212 * - high
 213 *
 214 * - manual
 215 *
 216 * - profile_standard
 217 *
 218 * - profile_min_sclk
 219 *
 220 * - profile_min_mclk
 221 *
 222 * - profile_peak
 223 *
 224 * auto
 225 *
 226 * When auto is selected, the driver will attempt to dynamically select
 227 * the optimal power profile for current conditions in the driver.
 228 *
 229 * low
 230 *
 231 * When low is selected, the clocks are forced to the lowest power state.
 232 *
 233 * high
 234 *
 235 * When high is selected, the clocks are forced to the highest power state.
 236 *
 237 * manual
 238 *
 239 * When manual is selected, the user can manually adjust which power states
 240 * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 241 * and pp_dpm_pcie files and adjust the power state transition heuristics
 242 * via the pp_power_profile_mode sysfs file.
 243 *
 244 * profile_standard
 245 * profile_min_sclk
 246 * profile_min_mclk
 247 * profile_peak
 248 *
 249 * When the profiling modes are selected, clock and power gating are
 250 * disabled and the clocks are set for different profiling cases. This
 251 * mode is recommended for profiling specific work loads where you do
 252 * not want clock or power gating for clock fluctuation to interfere
 253 * with your results. profile_standard sets the clocks to a fixed clock
 254 * level which varies from asic to asic.  profile_min_sclk forces the sclk
 255 * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 256 * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 257 *
 258 */
 259
 260static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 261							    struct device_attribute *attr,
 262							    char *buf)
 263{
 264	struct drm_device *ddev = dev_get_drvdata(dev);
 265	struct amdgpu_device *adev = drm_to_adev(ddev);
 266	enum amd_dpm_forced_level level = 0xff;
 267	int ret;
 268
 269	if (amdgpu_in_reset(adev))
 270		return -EPERM;
 271	if (adev->in_suspend && !adev->in_runpm)
 272		return -EPERM;
 273
 274	ret = pm_runtime_get_sync(ddev->dev);
 275	if (ret < 0) {
 276		pm_runtime_put_autosuspend(ddev->dev);
 277		return ret;
 278	}
 279
 280	level = amdgpu_dpm_get_performance_level(adev);
 281
 282	pm_runtime_mark_last_busy(ddev->dev);
 283	pm_runtime_put_autosuspend(ddev->dev);
 284
 285	return sysfs_emit(buf, "%s\n",
 286			  (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 287			  (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 288			  (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 289			  (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 290			  (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 291			  (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 292			  (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 293			  (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 294			  (level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) ? "perf_determinism" :
 295			  "unknown");
 296}
 297
 298static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 299							    struct device_attribute *attr,
 300							    const char *buf,
 301							    size_t count)
 302{
 303	struct drm_device *ddev = dev_get_drvdata(dev);
 304	struct amdgpu_device *adev = drm_to_adev(ddev);
 305	enum amd_dpm_forced_level level;
 306	int ret = 0;
 307
 308	if (amdgpu_in_reset(adev))
 309		return -EPERM;
 310	if (adev->in_suspend && !adev->in_runpm)
 311		return -EPERM;
 312
 313	if (strncmp("low", buf, strlen("low")) == 0) {
 314		level = AMD_DPM_FORCED_LEVEL_LOW;
 315	} else if (strncmp("high", buf, strlen("high")) == 0) {
 316		level = AMD_DPM_FORCED_LEVEL_HIGH;
 317	} else if (strncmp("auto", buf, strlen("auto")) == 0) {
 318		level = AMD_DPM_FORCED_LEVEL_AUTO;
 319	} else if (strncmp("manual", buf, strlen("manual")) == 0) {
 320		level = AMD_DPM_FORCED_LEVEL_MANUAL;
 321	} else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 322		level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 323	} else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 324		level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 325	} else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 326		level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 327	} else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 328		level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 329	} else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 330		level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 331	} else if (strncmp("perf_determinism", buf, strlen("perf_determinism")) == 0) {
 332		level = AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM;
 333	}  else {
 334		return -EINVAL;
 335	}
 336
 337	ret = pm_runtime_get_sync(ddev->dev);
 338	if (ret < 0) {
 339		pm_runtime_put_autosuspend(ddev->dev);
 340		return ret;
 341	}
 342
 343	mutex_lock(&adev->pm.stable_pstate_ctx_lock);
 344	if (amdgpu_dpm_force_performance_level(adev, level)) {
 345		pm_runtime_mark_last_busy(ddev->dev);
 346		pm_runtime_put_autosuspend(ddev->dev);
 347		mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 348		return -EINVAL;
 349	}
 350	/* override whatever a user ctx may have set */
 351	adev->pm.stable_pstate_ctx = NULL;
 352	mutex_unlock(&adev->pm.stable_pstate_ctx_lock);
 353
 354	pm_runtime_mark_last_busy(ddev->dev);
 355	pm_runtime_put_autosuspend(ddev->dev);
 356
 357	return count;
 358}
 359
 360static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 361		struct device_attribute *attr,
 362		char *buf)
 363{
 364	struct drm_device *ddev = dev_get_drvdata(dev);
 365	struct amdgpu_device *adev = drm_to_adev(ddev);
 366	struct pp_states_info data;
 367	uint32_t i;
 368	int buf_len, ret;
 369
 370	if (amdgpu_in_reset(adev))
 371		return -EPERM;
 372	if (adev->in_suspend && !adev->in_runpm)
 373		return -EPERM;
 374
 375	ret = pm_runtime_get_sync(ddev->dev);
 376	if (ret < 0) {
 377		pm_runtime_put_autosuspend(ddev->dev);
 378		return ret;
 379	}
 380
 381	if (amdgpu_dpm_get_pp_num_states(adev, &data))
 382		memset(&data, 0, sizeof(data));
 383
 384	pm_runtime_mark_last_busy(ddev->dev);
 385	pm_runtime_put_autosuspend(ddev->dev);
 386
 387	buf_len = sysfs_emit(buf, "states: %d\n", data.nums);
 388	for (i = 0; i < data.nums; i++)
 389		buf_len += sysfs_emit_at(buf, buf_len, "%d %s\n", i,
 390				(data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 391				(data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 392				(data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 393				(data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 394
 395	return buf_len;
 396}
 397
 398static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 399		struct device_attribute *attr,
 400		char *buf)
 401{
 402	struct drm_device *ddev = dev_get_drvdata(dev);
 403	struct amdgpu_device *adev = drm_to_adev(ddev);
 404	struct pp_states_info data = {0};
 405	enum amd_pm_state_type pm = 0;
 406	int i = 0, ret = 0;
 407
 408	if (amdgpu_in_reset(adev))
 409		return -EPERM;
 410	if (adev->in_suspend && !adev->in_runpm)
 411		return -EPERM;
 412
 413	ret = pm_runtime_get_sync(ddev->dev);
 414	if (ret < 0) {
 415		pm_runtime_put_autosuspend(ddev->dev);
 416		return ret;
 417	}
 418
 419	amdgpu_dpm_get_current_power_state(adev, &pm);
 420
 421	ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 422
 423	pm_runtime_mark_last_busy(ddev->dev);
 424	pm_runtime_put_autosuspend(ddev->dev);
 425
 426	if (ret)
 427		return ret;
 428
 429	for (i = 0; i < data.nums; i++) {
 430		if (pm == data.states[i])
 431			break;
 432	}
 433
 434	if (i == data.nums)
 435		i = -EINVAL;
 436
 437	return sysfs_emit(buf, "%d\n", i);
 438}
 439
 440static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 441		struct device_attribute *attr,
 442		char *buf)
 443{
 444	struct drm_device *ddev = dev_get_drvdata(dev);
 445	struct amdgpu_device *adev = drm_to_adev(ddev);
 446
 447	if (amdgpu_in_reset(adev))
 448		return -EPERM;
 449	if (adev->in_suspend && !adev->in_runpm)
 450		return -EPERM;
 451
 452	if (adev->pm.pp_force_state_enabled)
 453		return amdgpu_get_pp_cur_state(dev, attr, buf);
 454	else
 455		return sysfs_emit(buf, "\n");
 456}
 457
 458static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 459		struct device_attribute *attr,
 460		const char *buf,
 461		size_t count)
 462{
 463	struct drm_device *ddev = dev_get_drvdata(dev);
 464	struct amdgpu_device *adev = drm_to_adev(ddev);
 465	enum amd_pm_state_type state = 0;
 466	struct pp_states_info data;
 467	unsigned long idx;
 468	int ret;
 469
 470	if (amdgpu_in_reset(adev))
 471		return -EPERM;
 472	if (adev->in_suspend && !adev->in_runpm)
 473		return -EPERM;
 474
 475	adev->pm.pp_force_state_enabled = false;
 476
 477	if (strlen(buf) == 1)
 478		return count;
 479
 480	ret = kstrtoul(buf, 0, &idx);
 481	if (ret || idx >= ARRAY_SIZE(data.states))
 482		return -EINVAL;
 483
 484	idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 485
 486	ret = pm_runtime_get_sync(ddev->dev);
 487	if (ret < 0) {
 488		pm_runtime_put_autosuspend(ddev->dev);
 489		return ret;
 490	}
 491
 492	ret = amdgpu_dpm_get_pp_num_states(adev, &data);
 493	if (ret)
 494		goto err_out;
 495
 496	state = data.states[idx];
 497
 498	/* only set user selected power states */
 499	if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 500	    state != POWER_STATE_TYPE_DEFAULT) {
 501		ret = amdgpu_dpm_dispatch_task(adev,
 502				AMD_PP_TASK_ENABLE_USER_STATE, &state);
 503		if (ret)
 504			goto err_out;
 505
 506		adev->pm.pp_force_state_enabled = true;
 507	}
 508
 509	pm_runtime_mark_last_busy(ddev->dev);
 510	pm_runtime_put_autosuspend(ddev->dev);
 511
 512	return count;
 513
 514err_out:
 515	pm_runtime_mark_last_busy(ddev->dev);
 516	pm_runtime_put_autosuspend(ddev->dev);
 517	return ret;
 518}
 519
 520/**
 521 * DOC: pp_table
 522 *
 523 * The amdgpu driver provides a sysfs API for uploading new powerplay
 524 * tables.  The file pp_table is used for this.  Reading the file
 525 * will dump the current power play table.  Writing to the file
 526 * will attempt to upload a new powerplay table and re-initialize
 527 * powerplay using that new table.
 528 *
 529 */
 530
 531static ssize_t amdgpu_get_pp_table(struct device *dev,
 532		struct device_attribute *attr,
 533		char *buf)
 534{
 535	struct drm_device *ddev = dev_get_drvdata(dev);
 536	struct amdgpu_device *adev = drm_to_adev(ddev);
 537	char *table = NULL;
 538	int size, ret;
 539
 540	if (amdgpu_in_reset(adev))
 541		return -EPERM;
 542	if (adev->in_suspend && !adev->in_runpm)
 543		return -EPERM;
 544
 545	ret = pm_runtime_get_sync(ddev->dev);
 546	if (ret < 0) {
 547		pm_runtime_put_autosuspend(ddev->dev);
 548		return ret;
 549	}
 550
 551	size = amdgpu_dpm_get_pp_table(adev, &table);
 552
 553	pm_runtime_mark_last_busy(ddev->dev);
 554	pm_runtime_put_autosuspend(ddev->dev);
 555
 556	if (size <= 0)
 557		return size;
 558
 559	if (size >= PAGE_SIZE)
 560		size = PAGE_SIZE - 1;
 561
 562	memcpy(buf, table, size);
 563
 564	return size;
 565}
 566
 567static ssize_t amdgpu_set_pp_table(struct device *dev,
 568		struct device_attribute *attr,
 569		const char *buf,
 570		size_t count)
 571{
 572	struct drm_device *ddev = dev_get_drvdata(dev);
 573	struct amdgpu_device *adev = drm_to_adev(ddev);
 574	int ret = 0;
 575
 576	if (amdgpu_in_reset(adev))
 577		return -EPERM;
 578	if (adev->in_suspend && !adev->in_runpm)
 579		return -EPERM;
 580
 581	ret = pm_runtime_get_sync(ddev->dev);
 582	if (ret < 0) {
 583		pm_runtime_put_autosuspend(ddev->dev);
 584		return ret;
 585	}
 586
 587	ret = amdgpu_dpm_set_pp_table(adev, buf, count);
 588
 589	pm_runtime_mark_last_busy(ddev->dev);
 590	pm_runtime_put_autosuspend(ddev->dev);
 591
 592	if (ret)
 593		return ret;
 594
 595	return count;
 596}
 597
 598/**
 599 * DOC: pp_od_clk_voltage
 600 *
 601 * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 602 * in each power level within a power state.  The pp_od_clk_voltage is used for
 603 * this.
 604 *
 605 * Note that the actual memory controller clock rate are exposed, not
 606 * the effective memory clock of the DRAMs. To translate it, use the
 607 * following formula:
 608 *
 609 * Clock conversion (Mhz):
 610 *
 611 * HBM: effective_memory_clock = memory_controller_clock * 1
 612 *
 613 * G5: effective_memory_clock = memory_controller_clock * 1
 614 *
 615 * G6: effective_memory_clock = memory_controller_clock * 2
 616 *
 617 * DRAM data rate (MT/s):
 618 *
 619 * HBM: effective_memory_clock * 2 = data_rate
 620 *
 621 * G5: effective_memory_clock * 4 = data_rate
 622 *
 623 * G6: effective_memory_clock * 8 = data_rate
 624 *
 625 * Bandwidth (MB/s):
 626 *
 627 * data_rate * vram_bit_width / 8 = memory_bandwidth
 628 *
 629 * Some examples:
 630 *
 631 * G5 on RX460:
 632 *
 633 * memory_controller_clock = 1750 Mhz
 634 *
 635 * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 636 *
 637 * data rate = 1750 * 4 = 7000 MT/s
 638 *
 639 * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 640 *
 641 * G6 on RX5700:
 642 *
 643 * memory_controller_clock = 875 Mhz
 644 *
 645 * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 646 *
 647 * data rate = 1750 * 8 = 14000 MT/s
 648 *
 649 * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 650 *
 651 * < For Vega10 and previous ASICs >
 652 *
 653 * Reading the file will display:
 654 *
 655 * - a list of engine clock levels and voltages labeled OD_SCLK
 656 *
 657 * - a list of memory clock levels and voltages labeled OD_MCLK
 658 *
 659 * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 660 *
 661 * To manually adjust these settings, first select manual using
 662 * power_dpm_force_performance_level. Enter a new value for each
 663 * level by writing a string that contains "s/m level clock voltage" to
 664 * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 665 * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 666 * 810 mV.  When you have edited all of the states as needed, write
 667 * "c" (commit) to the file to commit your changes.  If you want to reset to the
 668 * default power levels, write "r" (reset) to the file to reset them.
 669 *
 670 *
 671 * < For Vega20 and newer ASICs >
 672 *
 673 * Reading the file will display:
 674 *
 675 * - minimum and maximum engine clock labeled OD_SCLK
 676 *
 677 * - minimum(not available for Vega20 and Navi1x) and maximum memory
 678 *   clock labeled OD_MCLK
 679 *
 680 * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 681 *   They can be used to calibrate the sclk voltage curve. This is
 682 *   available for Vega20 and NV1X.
 683 *
 684 * - voltage offset(in mV) applied on target voltage calculation.
 685 *   This is available for Sienna Cichlid, Navy Flounder, Dimgrey
 686 *   Cavefish and some later SMU13 ASICs. For these ASICs, the target
 687 *   voltage calculation can be illustrated by "voltage = voltage
 688 *   calculated from v/f curve + overdrive vddgfx offset"
 689 *
 690 * - a list of valid ranges for sclk, mclk, voltage curve points
 691 *   or voltage offset labeled OD_RANGE
 692 *
 693 * < For APUs >
 694 *
 695 * Reading the file will display:
 696 *
 697 * - minimum and maximum engine clock labeled OD_SCLK
 698 *
 699 * - a list of valid ranges for sclk labeled OD_RANGE
 700 *
 701 * < For VanGogh >
 702 *
 703 * Reading the file will display:
 704 *
 705 * - minimum and maximum engine clock labeled OD_SCLK
 706 * - minimum and maximum core clocks labeled OD_CCLK
 707 *
 708 * - a list of valid ranges for sclk and cclk labeled OD_RANGE
 709 *
 710 * To manually adjust these settings:
 711 *
 712 * - First select manual using power_dpm_force_performance_level
 713 *
 714 * - For clock frequency setting, enter a new value by writing a
 715 *   string that contains "s/m index clock" to the file. The index
 716 *   should be 0 if to set minimum clock. And 1 if to set maximum
 717 *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 718 *   "m 1 800" will update maximum mclk to be 800Mhz. For core
 719 *   clocks on VanGogh, the string contains "p core index clock".
 720 *   E.g., "p 2 0 800" would set the minimum core clock on core
 721 *   2 to 800Mhz.
 722 *
 723 *   For sclk voltage curve supported by Vega20 and NV1X, enter the new
 724 *   values by writing a string that contains "vc point clock voltage"
 725 *   to the file. The points are indexed by 0, 1 and 2. E.g., "vc 0 300
 726 *   600" will update point1 with clock set as 300Mhz and voltage as 600mV.
 727 *   "vc 2 1000 1000" will update point3 with clock set as 1000Mhz and
 728 *   voltage 1000mV.
 729 *
 730 *   For voltage offset supported by Sienna Cichlid, Navy Flounder, Dimgrey
 731 *   Cavefish and some later SMU13 ASICs, enter the new value by writing a
 732 *   string that contains "vo offset". E.g., "vo -10" will update the extra
 733 *   voltage offset applied to the whole v/f curve line as -10mv.
 734 *
 735 * - When you have edited all of the states as needed, write "c" (commit)
 736 *   to the file to commit your changes
 737 *
 738 * - If you want to reset to the default power levels, write "r" (reset)
 739 *   to the file to reset them
 740 *
 741 */
 742
 743static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 744		struct device_attribute *attr,
 745		const char *buf,
 746		size_t count)
 747{
 748	struct drm_device *ddev = dev_get_drvdata(dev);
 749	struct amdgpu_device *adev = drm_to_adev(ddev);
 750	int ret;
 751	uint32_t parameter_size = 0;
 752	long parameter[64];
 753	char buf_cpy[128];
 754	char *tmp_str;
 755	char *sub_str;
 756	const char delimiter[3] = {' ', '\n', '\0'};
 757	uint32_t type;
 758
 759	if (amdgpu_in_reset(adev))
 760		return -EPERM;
 761	if (adev->in_suspend && !adev->in_runpm)
 762		return -EPERM;
 763
 764	if (count > 127 || count == 0)
 765		return -EINVAL;
 766
 767	if (*buf == 's')
 768		type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 769	else if (*buf == 'p')
 770		type = PP_OD_EDIT_CCLK_VDDC_TABLE;
 771	else if (*buf == 'm')
 772		type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 773	else if (*buf == 'r')
 774		type = PP_OD_RESTORE_DEFAULT_TABLE;
 775	else if (*buf == 'c')
 776		type = PP_OD_COMMIT_DPM_TABLE;
 777	else if (!strncmp(buf, "vc", 2))
 778		type = PP_OD_EDIT_VDDC_CURVE;
 779	else if (!strncmp(buf, "vo", 2))
 780		type = PP_OD_EDIT_VDDGFX_OFFSET;
 781	else
 782		return -EINVAL;
 783
 784	memcpy(buf_cpy, buf, count);
 785	buf_cpy[count] = 0;
 786
 787	tmp_str = buf_cpy;
 788
 789	if ((type == PP_OD_EDIT_VDDC_CURVE) ||
 790	     (type == PP_OD_EDIT_VDDGFX_OFFSET))
 791		tmp_str++;
 792	while (isspace(*++tmp_str));
 793
 794	while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
 795		if (strlen(sub_str) == 0)
 796			continue;
 797		ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 798		if (ret)
 799			return -EINVAL;
 800		parameter_size++;
 801
 802		if (!tmp_str)
 803			break;
 804
 805		while (isspace(*tmp_str))
 806			tmp_str++;
 807	}
 808
 809	ret = pm_runtime_get_sync(ddev->dev);
 810	if (ret < 0) {
 811		pm_runtime_put_autosuspend(ddev->dev);
 812		return ret;
 813	}
 814
 815	if (amdgpu_dpm_set_fine_grain_clk_vol(adev,
 816					      type,
 817					      parameter,
 818					      parameter_size))
 819		goto err_out;
 820
 821	if (amdgpu_dpm_odn_edit_dpm_table(adev, type,
 822					  parameter, parameter_size))
 823		goto err_out;
 824
 825	if (type == PP_OD_COMMIT_DPM_TABLE) {
 826		if (amdgpu_dpm_dispatch_task(adev,
 827					     AMD_PP_TASK_READJUST_POWER_STATE,
 828					     NULL))
 829			goto err_out;
 830	}
 831
 832	pm_runtime_mark_last_busy(ddev->dev);
 833	pm_runtime_put_autosuspend(ddev->dev);
 834
 835	return count;
 836
 837err_out:
 838	pm_runtime_mark_last_busy(ddev->dev);
 839	pm_runtime_put_autosuspend(ddev->dev);
 840	return -EINVAL;
 841}
 842
 843static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 844		struct device_attribute *attr,
 845		char *buf)
 846{
 847	struct drm_device *ddev = dev_get_drvdata(dev);
 848	struct amdgpu_device *adev = drm_to_adev(ddev);
 849	int size = 0;
 850	int ret;
 851	enum pp_clock_type od_clocks[6] = {
 852		OD_SCLK,
 853		OD_MCLK,
 854		OD_VDDC_CURVE,
 855		OD_RANGE,
 856		OD_VDDGFX_OFFSET,
 857		OD_CCLK,
 858	};
 859	uint clk_index;
 860
 861	if (amdgpu_in_reset(adev))
 862		return -EPERM;
 863	if (adev->in_suspend && !adev->in_runpm)
 864		return -EPERM;
 865
 866	ret = pm_runtime_get_sync(ddev->dev);
 867	if (ret < 0) {
 868		pm_runtime_put_autosuspend(ddev->dev);
 869		return ret;
 870	}
 871
 872	for (clk_index = 0 ; clk_index < 6 ; clk_index++) {
 873		ret = amdgpu_dpm_emit_clock_levels(adev, od_clocks[clk_index], buf, &size);
 874		if (ret)
 875			break;
 876	}
 877	if (ret == -ENOENT) {
 878		size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 879		size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf + size);
 880		size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf + size);
 881		size += amdgpu_dpm_print_clock_levels(adev, OD_VDDGFX_OFFSET, buf + size);
 882		size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf + size);
 883		size += amdgpu_dpm_print_clock_levels(adev, OD_CCLK, buf + size);
 884	}
 885
 886	if (size == 0)
 887		size = sysfs_emit(buf, "\n");
 888
 889	pm_runtime_mark_last_busy(ddev->dev);
 890	pm_runtime_put_autosuspend(ddev->dev);
 891
 892	return size;
 893}
 894
 895/**
 896 * DOC: pp_features
 897 *
 898 * The amdgpu driver provides a sysfs API for adjusting what powerplay
 899 * features to be enabled. The file pp_features is used for this. And
 900 * this is only available for Vega10 and later dGPUs.
 901 *
 902 * Reading back the file will show you the followings:
 903 * - Current ppfeature masks
 904 * - List of the all supported powerplay features with their naming,
 905 *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 906 *
 907 * To manually enable or disable a specific feature, just set or clear
 908 * the corresponding bit from original ppfeature masks and input the
 909 * new ppfeature masks.
 910 */
 911static ssize_t amdgpu_set_pp_features(struct device *dev,
 912				      struct device_attribute *attr,
 913				      const char *buf,
 914				      size_t count)
 915{
 916	struct drm_device *ddev = dev_get_drvdata(dev);
 917	struct amdgpu_device *adev = drm_to_adev(ddev);
 918	uint64_t featuremask;
 919	int ret;
 920
 921	if (amdgpu_in_reset(adev))
 922		return -EPERM;
 923	if (adev->in_suspend && !adev->in_runpm)
 924		return -EPERM;
 925
 926	ret = kstrtou64(buf, 0, &featuremask);
 927	if (ret)
 928		return -EINVAL;
 929
 930	ret = pm_runtime_get_sync(ddev->dev);
 931	if (ret < 0) {
 932		pm_runtime_put_autosuspend(ddev->dev);
 933		return ret;
 934	}
 935
 936	ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 937
 938	pm_runtime_mark_last_busy(ddev->dev);
 939	pm_runtime_put_autosuspend(ddev->dev);
 940
 941	if (ret)
 942		return -EINVAL;
 943
 944	return count;
 945}
 946
 947static ssize_t amdgpu_get_pp_features(struct device *dev,
 948				      struct device_attribute *attr,
 949				      char *buf)
 950{
 951	struct drm_device *ddev = dev_get_drvdata(dev);
 952	struct amdgpu_device *adev = drm_to_adev(ddev);
 953	ssize_t size;
 954	int ret;
 955
 956	if (amdgpu_in_reset(adev))
 957		return -EPERM;
 958	if (adev->in_suspend && !adev->in_runpm)
 959		return -EPERM;
 960
 961	ret = pm_runtime_get_sync(ddev->dev);
 962	if (ret < 0) {
 963		pm_runtime_put_autosuspend(ddev->dev);
 964		return ret;
 965	}
 966
 967	size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 968	if (size <= 0)
 969		size = sysfs_emit(buf, "\n");
 970
 971	pm_runtime_mark_last_busy(ddev->dev);
 972	pm_runtime_put_autosuspend(ddev->dev);
 973
 974	return size;
 975}
 976
 977/**
 978 * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
 979 *
 980 * The amdgpu driver provides a sysfs API for adjusting what power levels
 981 * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
 982 * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
 983 * this.
 984 *
 985 * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
 986 * Vega10 and later ASICs.
 987 * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
 988 *
 989 * Reading back the files will show you the available power levels within
 990 * the power state and the clock information for those levels. If deep sleep is
 991 * applied to a clock, the level will be denoted by a special level 'S:'
 992 * E.g., ::
 993 *
 994 *  S: 19Mhz *
 995 *  0: 615Mhz
 996 *  1: 800Mhz
 997 *  2: 888Mhz
 998 *  3: 1000Mhz
 999 *
1000 *
1001 * To manually adjust these states, first select manual using
1002 * power_dpm_force_performance_level.
1003 * Secondly, enter a new value for each level by inputing a string that
1004 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1005 * E.g.,
1006 *
1007 * .. code-block:: bash
1008 *
1009 *	echo "4 5 6" > pp_dpm_sclk
1010 *
1011 * will enable sclk levels 4, 5, and 6.
1012 *
1013 * NOTE: change to the dcefclk max dpm level is not supported now
1014 */
1015
1016static ssize_t amdgpu_get_pp_dpm_clock(struct device *dev,
1017		enum pp_clock_type type,
1018		char *buf)
1019{
1020	struct drm_device *ddev = dev_get_drvdata(dev);
1021	struct amdgpu_device *adev = drm_to_adev(ddev);
1022	int size = 0;
1023	int ret = 0;
1024
1025	if (amdgpu_in_reset(adev))
1026		return -EPERM;
1027	if (adev->in_suspend && !adev->in_runpm)
1028		return -EPERM;
1029
1030	ret = pm_runtime_get_sync(ddev->dev);
1031	if (ret < 0) {
1032		pm_runtime_put_autosuspend(ddev->dev);
1033		return ret;
1034	}
1035
1036	ret = amdgpu_dpm_emit_clock_levels(adev, type, buf, &size);
1037	if (ret == -ENOENT)
1038		size = amdgpu_dpm_print_clock_levels(adev, type, buf);
1039
1040	if (size == 0)
1041		size = sysfs_emit(buf, "\n");
1042
1043	pm_runtime_mark_last_busy(ddev->dev);
1044	pm_runtime_put_autosuspend(ddev->dev);
1045
1046	return size;
1047}
1048
1049/*
1050 * Worst case: 32 bits individually specified, in octal at 12 characters
1051 * per line (+1 for \n).
1052 */
1053#define AMDGPU_MASK_BUF_MAX	(32 * 13)
1054
1055static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1056{
1057	int ret;
1058	unsigned long level;
1059	char *sub_str = NULL;
1060	char *tmp;
1061	char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1062	const char delimiter[3] = {' ', '\n', '\0'};
1063	size_t bytes;
1064
1065	*mask = 0;
1066
1067	bytes = min(count, sizeof(buf_cpy) - 1);
1068	memcpy(buf_cpy, buf, bytes);
1069	buf_cpy[bytes] = '\0';
1070	tmp = buf_cpy;
1071	while ((sub_str = strsep(&tmp, delimiter)) != NULL) {
1072		if (strlen(sub_str)) {
1073			ret = kstrtoul(sub_str, 0, &level);
1074			if (ret || level > 31)
1075				return -EINVAL;
1076			*mask |= 1 << level;
1077		} else
1078			break;
1079	}
1080
1081	return 0;
1082}
1083
1084static ssize_t amdgpu_set_pp_dpm_clock(struct device *dev,
1085		enum pp_clock_type type,
1086		const char *buf,
1087		size_t count)
1088{
1089	struct drm_device *ddev = dev_get_drvdata(dev);
1090	struct amdgpu_device *adev = drm_to_adev(ddev);
1091	int ret;
1092	uint32_t mask = 0;
1093
1094	if (amdgpu_in_reset(adev))
1095		return -EPERM;
1096	if (adev->in_suspend && !adev->in_runpm)
1097		return -EPERM;
1098
1099	ret = amdgpu_read_mask(buf, count, &mask);
1100	if (ret)
1101		return ret;
1102
1103	ret = pm_runtime_get_sync(ddev->dev);
1104	if (ret < 0) {
1105		pm_runtime_put_autosuspend(ddev->dev);
1106		return ret;
1107	}
1108
1109	ret = amdgpu_dpm_force_clock_level(adev, type, mask);
1110
1111	pm_runtime_mark_last_busy(ddev->dev);
1112	pm_runtime_put_autosuspend(ddev->dev);
1113
1114	if (ret)
1115		return -EINVAL;
1116
1117	return count;
1118}
1119
1120static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1121		struct device_attribute *attr,
1122		char *buf)
1123{
1124	return amdgpu_get_pp_dpm_clock(dev, PP_SCLK, buf);
1125}
1126
1127static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1128		struct device_attribute *attr,
1129		const char *buf,
1130		size_t count)
1131{
1132	return amdgpu_set_pp_dpm_clock(dev, PP_SCLK, buf, count);
1133}
1134
1135static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1136		struct device_attribute *attr,
1137		char *buf)
1138{
1139	return amdgpu_get_pp_dpm_clock(dev, PP_MCLK, buf);
1140}
1141
1142static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1143		struct device_attribute *attr,
1144		const char *buf,
1145		size_t count)
1146{
1147	return amdgpu_set_pp_dpm_clock(dev, PP_MCLK, buf, count);
1148}
1149
1150static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1151		struct device_attribute *attr,
1152		char *buf)
1153{
1154	return amdgpu_get_pp_dpm_clock(dev, PP_SOCCLK, buf);
1155}
1156
1157static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1158		struct device_attribute *attr,
1159		const char *buf,
1160		size_t count)
1161{
1162	return amdgpu_set_pp_dpm_clock(dev, PP_SOCCLK, buf, count);
1163}
1164
1165static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1166		struct device_attribute *attr,
1167		char *buf)
1168{
1169	return amdgpu_get_pp_dpm_clock(dev, PP_FCLK, buf);
1170}
1171
1172static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1173		struct device_attribute *attr,
1174		const char *buf,
1175		size_t count)
1176{
1177	return amdgpu_set_pp_dpm_clock(dev, PP_FCLK, buf, count);
1178}
1179
1180static ssize_t amdgpu_get_pp_dpm_vclk(struct device *dev,
1181		struct device_attribute *attr,
1182		char *buf)
1183{
1184	return amdgpu_get_pp_dpm_clock(dev, PP_VCLK, buf);
1185}
1186
1187static ssize_t amdgpu_set_pp_dpm_vclk(struct device *dev,
1188		struct device_attribute *attr,
1189		const char *buf,
1190		size_t count)
1191{
1192	return amdgpu_set_pp_dpm_clock(dev, PP_VCLK, buf, count);
1193}
1194
1195static ssize_t amdgpu_get_pp_dpm_vclk1(struct device *dev,
1196		struct device_attribute *attr,
1197		char *buf)
1198{
1199	return amdgpu_get_pp_dpm_clock(dev, PP_VCLK1, buf);
1200}
1201
1202static ssize_t amdgpu_set_pp_dpm_vclk1(struct device *dev,
1203		struct device_attribute *attr,
1204		const char *buf,
1205		size_t count)
1206{
1207	return amdgpu_set_pp_dpm_clock(dev, PP_VCLK1, buf, count);
1208}
1209
1210static ssize_t amdgpu_get_pp_dpm_dclk(struct device *dev,
1211		struct device_attribute *attr,
1212		char *buf)
1213{
1214	return amdgpu_get_pp_dpm_clock(dev, PP_DCLK, buf);
1215}
1216
1217static ssize_t amdgpu_set_pp_dpm_dclk(struct device *dev,
1218		struct device_attribute *attr,
1219		const char *buf,
1220		size_t count)
1221{
1222	return amdgpu_set_pp_dpm_clock(dev, PP_DCLK, buf, count);
1223}
1224
1225static ssize_t amdgpu_get_pp_dpm_dclk1(struct device *dev,
1226		struct device_attribute *attr,
1227		char *buf)
1228{
1229	return amdgpu_get_pp_dpm_clock(dev, PP_DCLK1, buf);
1230}
1231
1232static ssize_t amdgpu_set_pp_dpm_dclk1(struct device *dev,
1233		struct device_attribute *attr,
1234		const char *buf,
1235		size_t count)
1236{
1237	return amdgpu_set_pp_dpm_clock(dev, PP_DCLK1, buf, count);
1238}
1239
1240static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1241		struct device_attribute *attr,
1242		char *buf)
1243{
1244	return amdgpu_get_pp_dpm_clock(dev, PP_DCEFCLK, buf);
1245}
1246
1247static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1248		struct device_attribute *attr,
1249		const char *buf,
1250		size_t count)
1251{
1252	return amdgpu_set_pp_dpm_clock(dev, PP_DCEFCLK, buf, count);
1253}
1254
1255static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1256		struct device_attribute *attr,
1257		char *buf)
1258{
1259	return amdgpu_get_pp_dpm_clock(dev, PP_PCIE, buf);
1260}
1261
1262static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1263		struct device_attribute *attr,
1264		const char *buf,
1265		size_t count)
1266{
1267	return amdgpu_set_pp_dpm_clock(dev, PP_PCIE, buf, count);
1268}
1269
1270static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1271		struct device_attribute *attr,
1272		char *buf)
1273{
1274	struct drm_device *ddev = dev_get_drvdata(dev);
1275	struct amdgpu_device *adev = drm_to_adev(ddev);
1276	uint32_t value = 0;
1277	int ret;
1278
1279	if (amdgpu_in_reset(adev))
1280		return -EPERM;
1281	if (adev->in_suspend && !adev->in_runpm)
1282		return -EPERM;
1283
1284	ret = pm_runtime_get_sync(ddev->dev);
1285	if (ret < 0) {
1286		pm_runtime_put_autosuspend(ddev->dev);
1287		return ret;
1288	}
1289
1290	value = amdgpu_dpm_get_sclk_od(adev);
1291
1292	pm_runtime_mark_last_busy(ddev->dev);
1293	pm_runtime_put_autosuspend(ddev->dev);
1294
1295	return sysfs_emit(buf, "%d\n", value);
1296}
1297
1298static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1299		struct device_attribute *attr,
1300		const char *buf,
1301		size_t count)
1302{
1303	struct drm_device *ddev = dev_get_drvdata(dev);
1304	struct amdgpu_device *adev = drm_to_adev(ddev);
1305	int ret;
1306	long int value;
1307
1308	if (amdgpu_in_reset(adev))
1309		return -EPERM;
1310	if (adev->in_suspend && !adev->in_runpm)
1311		return -EPERM;
1312
1313	ret = kstrtol(buf, 0, &value);
1314
1315	if (ret)
1316		return -EINVAL;
1317
1318	ret = pm_runtime_get_sync(ddev->dev);
1319	if (ret < 0) {
1320		pm_runtime_put_autosuspend(ddev->dev);
1321		return ret;
1322	}
1323
1324	amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1325
1326	pm_runtime_mark_last_busy(ddev->dev);
1327	pm_runtime_put_autosuspend(ddev->dev);
1328
1329	return count;
1330}
1331
1332static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1333		struct device_attribute *attr,
1334		char *buf)
1335{
1336	struct drm_device *ddev = dev_get_drvdata(dev);
1337	struct amdgpu_device *adev = drm_to_adev(ddev);
1338	uint32_t value = 0;
1339	int ret;
1340
1341	if (amdgpu_in_reset(adev))
1342		return -EPERM;
1343	if (adev->in_suspend && !adev->in_runpm)
1344		return -EPERM;
1345
1346	ret = pm_runtime_get_sync(ddev->dev);
1347	if (ret < 0) {
1348		pm_runtime_put_autosuspend(ddev->dev);
1349		return ret;
1350	}
1351
1352	value = amdgpu_dpm_get_mclk_od(adev);
1353
1354	pm_runtime_mark_last_busy(ddev->dev);
1355	pm_runtime_put_autosuspend(ddev->dev);
1356
1357	return sysfs_emit(buf, "%d\n", value);
1358}
1359
1360static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1361		struct device_attribute *attr,
1362		const char *buf,
1363		size_t count)
1364{
1365	struct drm_device *ddev = dev_get_drvdata(dev);
1366	struct amdgpu_device *adev = drm_to_adev(ddev);
1367	int ret;
1368	long int value;
1369
1370	if (amdgpu_in_reset(adev))
1371		return -EPERM;
1372	if (adev->in_suspend && !adev->in_runpm)
1373		return -EPERM;
1374
1375	ret = kstrtol(buf, 0, &value);
1376
1377	if (ret)
1378		return -EINVAL;
1379
1380	ret = pm_runtime_get_sync(ddev->dev);
1381	if (ret < 0) {
1382		pm_runtime_put_autosuspend(ddev->dev);
1383		return ret;
1384	}
1385
1386	amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1387
1388	pm_runtime_mark_last_busy(ddev->dev);
1389	pm_runtime_put_autosuspend(ddev->dev);
1390
1391	return count;
1392}
1393
1394/**
1395 * DOC: pp_power_profile_mode
1396 *
1397 * The amdgpu driver provides a sysfs API for adjusting the heuristics
1398 * related to switching between power levels in a power state.  The file
1399 * pp_power_profile_mode is used for this.
1400 *
1401 * Reading this file outputs a list of all of the predefined power profiles
1402 * and the relevant heuristics settings for that profile.
1403 *
1404 * To select a profile or create a custom profile, first select manual using
1405 * power_dpm_force_performance_level.  Writing the number of a predefined
1406 * profile to pp_power_profile_mode will enable those heuristics.  To
1407 * create a custom set of heuristics, write a string of numbers to the file
1408 * starting with the number of the custom profile along with a setting
1409 * for each heuristic parameter.  Due to differences across asic families
1410 * the heuristic parameters vary from family to family.
1411 *
1412 */
1413
1414static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1415		struct device_attribute *attr,
1416		char *buf)
1417{
1418	struct drm_device *ddev = dev_get_drvdata(dev);
1419	struct amdgpu_device *adev = drm_to_adev(ddev);
1420	ssize_t size;
1421	int ret;
1422
1423	if (amdgpu_in_reset(adev))
1424		return -EPERM;
1425	if (adev->in_suspend && !adev->in_runpm)
1426		return -EPERM;
1427
1428	ret = pm_runtime_get_sync(ddev->dev);
1429	if (ret < 0) {
1430		pm_runtime_put_autosuspend(ddev->dev);
1431		return ret;
1432	}
1433
1434	size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1435	if (size <= 0)
1436		size = sysfs_emit(buf, "\n");
1437
1438	pm_runtime_mark_last_busy(ddev->dev);
1439	pm_runtime_put_autosuspend(ddev->dev);
1440
1441	return size;
1442}
1443
1444
1445static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1446		struct device_attribute *attr,
1447		const char *buf,
1448		size_t count)
1449{
1450	int ret;
1451	struct drm_device *ddev = dev_get_drvdata(dev);
1452	struct amdgpu_device *adev = drm_to_adev(ddev);
1453	uint32_t parameter_size = 0;
1454	long parameter[64];
1455	char *sub_str, buf_cpy[128];
1456	char *tmp_str;
1457	uint32_t i = 0;
1458	char tmp[2];
1459	long int profile_mode = 0;
1460	const char delimiter[3] = {' ', '\n', '\0'};
1461
1462	if (amdgpu_in_reset(adev))
1463		return -EPERM;
1464	if (adev->in_suspend && !adev->in_runpm)
1465		return -EPERM;
1466
1467	tmp[0] = *(buf);
1468	tmp[1] = '\0';
1469	ret = kstrtol(tmp, 0, &profile_mode);
1470	if (ret)
1471		return -EINVAL;
1472
1473	if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1474		if (count < 2 || count > 127)
1475			return -EINVAL;
1476		while (isspace(*++buf))
1477			i++;
1478		memcpy(buf_cpy, buf, count-i);
1479		tmp_str = buf_cpy;
1480		while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
1481			if (strlen(sub_str) == 0)
1482				continue;
1483			ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1484			if (ret)
1485				return -EINVAL;
1486			parameter_size++;
1487			while (isspace(*tmp_str))
1488				tmp_str++;
1489		}
1490	}
1491	parameter[parameter_size] = profile_mode;
1492
1493	ret = pm_runtime_get_sync(ddev->dev);
1494	if (ret < 0) {
1495		pm_runtime_put_autosuspend(ddev->dev);
1496		return ret;
1497	}
1498
1499	ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1500
1501	pm_runtime_mark_last_busy(ddev->dev);
1502	pm_runtime_put_autosuspend(ddev->dev);
1503
1504	if (!ret)
1505		return count;
1506
1507	return -EINVAL;
1508}
1509
1510static int amdgpu_hwmon_get_sensor_generic(struct amdgpu_device *adev,
1511					   enum amd_pp_sensors sensor,
1512					   void *query)
1513{
1514	int r, size = sizeof(uint32_t);
1515
1516	if (amdgpu_in_reset(adev))
1517		return -EPERM;
1518	if (adev->in_suspend && !adev->in_runpm)
1519		return -EPERM;
1520
1521	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
1522	if (r < 0) {
1523		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1524		return r;
1525	}
1526
1527	/* get the sensor value */
1528	r = amdgpu_dpm_read_sensor(adev, sensor, query, &size);
1529
1530	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
1531	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
1532
1533	return r;
1534}
1535
1536/**
1537 * DOC: gpu_busy_percent
1538 *
1539 * The amdgpu driver provides a sysfs API for reading how busy the GPU
1540 * is as a percentage.  The file gpu_busy_percent is used for this.
1541 * The SMU firmware computes a percentage of load based on the
1542 * aggregate activity level in the IP cores.
1543 */
1544static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1545					   struct device_attribute *attr,
1546					   char *buf)
1547{
1548	struct drm_device *ddev = dev_get_drvdata(dev);
1549	struct amdgpu_device *adev = drm_to_adev(ddev);
1550	unsigned int value;
1551	int r;
1552
1553	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_LOAD, &value);
1554	if (r)
1555		return r;
1556
1557	return sysfs_emit(buf, "%d\n", value);
1558}
1559
1560/**
1561 * DOC: mem_busy_percent
1562 *
1563 * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1564 * is as a percentage.  The file mem_busy_percent is used for this.
1565 * The SMU firmware computes a percentage of load based on the
1566 * aggregate activity level in the IP cores.
1567 */
1568static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1569					   struct device_attribute *attr,
1570					   char *buf)
1571{
1572	struct drm_device *ddev = dev_get_drvdata(dev);
1573	struct amdgpu_device *adev = drm_to_adev(ddev);
1574	unsigned int value;
1575	int r;
1576
1577	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_LOAD, &value);
1578	if (r)
1579		return r;
1580
1581	return sysfs_emit(buf, "%d\n", value);
1582}
1583
1584/**
1585 * DOC: pcie_bw
1586 *
1587 * The amdgpu driver provides a sysfs API for estimating how much data
1588 * has been received and sent by the GPU in the last second through PCIe.
1589 * The file pcie_bw is used for this.
1590 * The Perf counters count the number of received and sent messages and return
1591 * those values, as well as the maximum payload size of a PCIe packet (mps).
1592 * Note that it is not possible to easily and quickly obtain the size of each
1593 * packet transmitted, so we output the max payload size (mps) to allow for
1594 * quick estimation of the PCIe bandwidth usage
1595 */
1596static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1597		struct device_attribute *attr,
1598		char *buf)
1599{
1600	struct drm_device *ddev = dev_get_drvdata(dev);
1601	struct amdgpu_device *adev = drm_to_adev(ddev);
1602	uint64_t count0 = 0, count1 = 0;
1603	int ret;
1604
1605	if (amdgpu_in_reset(adev))
1606		return -EPERM;
1607	if (adev->in_suspend && !adev->in_runpm)
1608		return -EPERM;
1609
1610	if (adev->flags & AMD_IS_APU)
1611		return -ENODATA;
1612
1613	if (!adev->asic_funcs->get_pcie_usage)
1614		return -ENODATA;
1615
1616	ret = pm_runtime_get_sync(ddev->dev);
1617	if (ret < 0) {
1618		pm_runtime_put_autosuspend(ddev->dev);
1619		return ret;
1620	}
1621
1622	amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1623
1624	pm_runtime_mark_last_busy(ddev->dev);
1625	pm_runtime_put_autosuspend(ddev->dev);
1626
1627	return sysfs_emit(buf, "%llu %llu %i\n",
1628			  count0, count1, pcie_get_mps(adev->pdev));
1629}
1630
1631/**
1632 * DOC: unique_id
1633 *
1634 * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1635 * The file unique_id is used for this.
1636 * This will provide a Unique ID that will persist from machine to machine
1637 *
1638 * NOTE: This will only work for GFX9 and newer. This file will be absent
1639 * on unsupported ASICs (GFX8 and older)
1640 */
1641static ssize_t amdgpu_get_unique_id(struct device *dev,
1642		struct device_attribute *attr,
1643		char *buf)
1644{
1645	struct drm_device *ddev = dev_get_drvdata(dev);
1646	struct amdgpu_device *adev = drm_to_adev(ddev);
1647
1648	if (amdgpu_in_reset(adev))
1649		return -EPERM;
1650	if (adev->in_suspend && !adev->in_runpm)
1651		return -EPERM;
1652
1653	if (adev->unique_id)
1654		return sysfs_emit(buf, "%016llx\n", adev->unique_id);
1655
1656	return 0;
1657}
1658
1659/**
1660 * DOC: thermal_throttling_logging
1661 *
1662 * Thermal throttling pulls down the clock frequency and thus the performance.
1663 * It's an useful mechanism to protect the chip from overheating. Since it
1664 * impacts performance, the user controls whether it is enabled and if so,
1665 * the log frequency.
1666 *
1667 * Reading back the file shows you the status(enabled or disabled) and
1668 * the interval(in seconds) between each thermal logging.
1669 *
1670 * Writing an integer to the file, sets a new logging interval, in seconds.
1671 * The value should be between 1 and 3600. If the value is less than 1,
1672 * thermal logging is disabled. Values greater than 3600 are ignored.
1673 */
1674static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1675						     struct device_attribute *attr,
1676						     char *buf)
1677{
1678	struct drm_device *ddev = dev_get_drvdata(dev);
1679	struct amdgpu_device *adev = drm_to_adev(ddev);
1680
1681	return sysfs_emit(buf, "%s: thermal throttling logging %s, with interval %d seconds\n",
1682			  adev_to_drm(adev)->unique,
1683			  atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1684			  adev->throttling_logging_rs.interval / HZ + 1);
1685}
1686
1687static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1688						     struct device_attribute *attr,
1689						     const char *buf,
1690						     size_t count)
1691{
1692	struct drm_device *ddev = dev_get_drvdata(dev);
1693	struct amdgpu_device *adev = drm_to_adev(ddev);
1694	long throttling_logging_interval;
1695	unsigned long flags;
1696	int ret = 0;
1697
1698	ret = kstrtol(buf, 0, &throttling_logging_interval);
1699	if (ret)
1700		return ret;
1701
1702	if (throttling_logging_interval > 3600)
1703		return -EINVAL;
1704
1705	if (throttling_logging_interval > 0) {
1706		raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1707		/*
1708		 * Reset the ratelimit timer internals.
1709		 * This can effectively restart the timer.
1710		 */
1711		adev->throttling_logging_rs.interval =
1712			(throttling_logging_interval - 1) * HZ;
1713		adev->throttling_logging_rs.begin = 0;
1714		adev->throttling_logging_rs.printed = 0;
1715		adev->throttling_logging_rs.missed = 0;
1716		raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1717
1718		atomic_set(&adev->throttling_logging_enabled, 1);
1719	} else {
1720		atomic_set(&adev->throttling_logging_enabled, 0);
1721	}
1722
1723	return count;
1724}
1725
1726/**
1727 * DOC: apu_thermal_cap
1728 *
1729 * The amdgpu driver provides a sysfs API for retrieving/updating thermal
1730 * limit temperature in millidegrees Celsius
1731 *
1732 * Reading back the file shows you core limit value
1733 *
1734 * Writing an integer to the file, sets a new thermal limit. The value
1735 * should be between 0 and 100. If the value is less than 0 or greater
1736 * than 100, then the write request will be ignored.
1737 */
1738static ssize_t amdgpu_get_apu_thermal_cap(struct device *dev,
1739					 struct device_attribute *attr,
1740					 char *buf)
1741{
1742	int ret, size;
1743	u32 limit;
1744	struct drm_device *ddev = dev_get_drvdata(dev);
1745	struct amdgpu_device *adev = drm_to_adev(ddev);
1746
1747	ret = pm_runtime_get_sync(ddev->dev);
1748	if (ret < 0) {
1749		pm_runtime_put_autosuspend(ddev->dev);
1750		return ret;
1751	}
1752
1753	ret = amdgpu_dpm_get_apu_thermal_limit(adev, &limit);
1754	if (!ret)
1755		size = sysfs_emit(buf, "%u\n", limit);
1756	else
1757		size = sysfs_emit(buf, "failed to get thermal limit\n");
1758
1759	pm_runtime_mark_last_busy(ddev->dev);
1760	pm_runtime_put_autosuspend(ddev->dev);
1761
1762	return size;
1763}
1764
1765static ssize_t amdgpu_set_apu_thermal_cap(struct device *dev,
1766					 struct device_attribute *attr,
1767					 const char *buf,
1768					 size_t count)
1769{
1770	int ret;
1771	u32 value;
1772	struct drm_device *ddev = dev_get_drvdata(dev);
1773	struct amdgpu_device *adev = drm_to_adev(ddev);
1774
1775	ret = kstrtou32(buf, 10, &value);
1776	if (ret)
1777		return ret;
1778
1779	if (value > 100) {
1780		dev_err(dev, "Invalid argument !\n");
1781		return -EINVAL;
1782	}
1783
1784	ret = pm_runtime_get_sync(ddev->dev);
1785	if (ret < 0) {
1786		pm_runtime_put_autosuspend(ddev->dev);
1787		return ret;
1788	}
1789
1790	ret = amdgpu_dpm_set_apu_thermal_limit(adev, value);
1791	if (ret) {
1792		dev_err(dev, "failed to update thermal limit\n");
1793		return ret;
1794	}
1795
1796	pm_runtime_mark_last_busy(ddev->dev);
1797	pm_runtime_put_autosuspend(ddev->dev);
1798
1799	return count;
1800}
1801
1802static int amdgpu_pm_metrics_attr_update(struct amdgpu_device *adev,
1803					 struct amdgpu_device_attr *attr,
1804					 uint32_t mask,
1805					 enum amdgpu_device_attr_states *states)
1806{
1807	if (amdgpu_dpm_get_pm_metrics(adev, NULL, 0) == -EOPNOTSUPP)
1808		*states = ATTR_STATE_UNSUPPORTED;
1809
1810	return 0;
1811}
1812
1813static ssize_t amdgpu_get_pm_metrics(struct device *dev,
1814				     struct device_attribute *attr, char *buf)
1815{
1816	struct drm_device *ddev = dev_get_drvdata(dev);
1817	struct amdgpu_device *adev = drm_to_adev(ddev);
1818	ssize_t size = 0;
1819	int ret;
1820
1821	if (amdgpu_in_reset(adev))
1822		return -EPERM;
1823	if (adev->in_suspend && !adev->in_runpm)
1824		return -EPERM;
1825
1826	ret = pm_runtime_get_sync(ddev->dev);
1827	if (ret < 0) {
1828		pm_runtime_put_autosuspend(ddev->dev);
1829		return ret;
1830	}
1831
1832	size = amdgpu_dpm_get_pm_metrics(adev, buf, PAGE_SIZE);
1833
1834	pm_runtime_mark_last_busy(ddev->dev);
1835	pm_runtime_put_autosuspend(ddev->dev);
1836
1837	return size;
1838}
1839
1840/**
1841 * DOC: gpu_metrics
1842 *
1843 * The amdgpu driver provides a sysfs API for retrieving current gpu
1844 * metrics data. The file gpu_metrics is used for this. Reading the
1845 * file will dump all the current gpu metrics data.
1846 *
1847 * These data include temperature, frequency, engines utilization,
1848 * power consume, throttler status, fan speed and cpu core statistics(
1849 * available for APU only). That's it will give a snapshot of all sensors
1850 * at the same time.
1851 */
1852static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1853				      struct device_attribute *attr,
1854				      char *buf)
1855{
1856	struct drm_device *ddev = dev_get_drvdata(dev);
1857	struct amdgpu_device *adev = drm_to_adev(ddev);
1858	void *gpu_metrics;
1859	ssize_t size = 0;
1860	int ret;
1861
1862	if (amdgpu_in_reset(adev))
1863		return -EPERM;
1864	if (adev->in_suspend && !adev->in_runpm)
1865		return -EPERM;
1866
1867	ret = pm_runtime_get_sync(ddev->dev);
1868	if (ret < 0) {
1869		pm_runtime_put_autosuspend(ddev->dev);
1870		return ret;
1871	}
1872
1873	size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
1874	if (size <= 0)
1875		goto out;
1876
1877	if (size >= PAGE_SIZE)
1878		size = PAGE_SIZE - 1;
1879
1880	memcpy(buf, gpu_metrics, size);
1881
1882out:
1883	pm_runtime_mark_last_busy(ddev->dev);
1884	pm_runtime_put_autosuspend(ddev->dev);
1885
1886	return size;
1887}
1888
1889static int amdgpu_show_powershift_percent(struct device *dev,
1890					char *buf, enum amd_pp_sensors sensor)
1891{
1892	struct drm_device *ddev = dev_get_drvdata(dev);
1893	struct amdgpu_device *adev = drm_to_adev(ddev);
1894	uint32_t ss_power;
1895	int r = 0, i;
1896
1897	r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1898	if (r == -EOPNOTSUPP) {
1899		/* sensor not available on dGPU, try to read from APU */
1900		adev = NULL;
1901		mutex_lock(&mgpu_info.mutex);
1902		for (i = 0; i < mgpu_info.num_gpu; i++) {
1903			if (mgpu_info.gpu_ins[i].adev->flags & AMD_IS_APU) {
1904				adev = mgpu_info.gpu_ins[i].adev;
1905				break;
1906			}
1907		}
1908		mutex_unlock(&mgpu_info.mutex);
1909		if (adev)
1910			r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&ss_power);
1911	}
1912
1913	if (r)
1914		return r;
1915
1916	return sysfs_emit(buf, "%u%%\n", ss_power);
1917}
1918
1919/**
1920 * DOC: smartshift_apu_power
1921 *
1922 * The amdgpu driver provides a sysfs API for reporting APU power
1923 * shift in percentage if platform supports smartshift. Value 0 means that
1924 * there is no powershift and values between [1-100] means that the power
1925 * is shifted to APU, the percentage of boost is with respect to APU power
1926 * limit on the platform.
1927 */
1928
1929static ssize_t amdgpu_get_smartshift_apu_power(struct device *dev, struct device_attribute *attr,
1930					       char *buf)
1931{
1932	return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_APU_SHARE);
1933}
1934
1935/**
1936 * DOC: smartshift_dgpu_power
1937 *
1938 * The amdgpu driver provides a sysfs API for reporting dGPU power
1939 * shift in percentage if platform supports smartshift. Value 0 means that
1940 * there is no powershift and values between [1-100] means that the power is
1941 * shifted to dGPU, the percentage of boost is with respect to dGPU power
1942 * limit on the platform.
1943 */
1944
1945static ssize_t amdgpu_get_smartshift_dgpu_power(struct device *dev, struct device_attribute *attr,
1946						char *buf)
1947{
1948	return amdgpu_show_powershift_percent(dev, buf, AMDGPU_PP_SENSOR_SS_DGPU_SHARE);
1949}
1950
1951/**
1952 * DOC: smartshift_bias
1953 *
1954 * The amdgpu driver provides a sysfs API for reporting the
1955 * smartshift(SS2.0) bias level. The value ranges from -100 to 100
1956 * and the default is 0. -100 sets maximum preference to APU
1957 * and 100 sets max perference to dGPU.
1958 */
1959
1960static ssize_t amdgpu_get_smartshift_bias(struct device *dev,
1961					  struct device_attribute *attr,
1962					  char *buf)
1963{
1964	int r = 0;
1965
1966	r = sysfs_emit(buf, "%d\n", amdgpu_smartshift_bias);
1967
1968	return r;
1969}
1970
1971static ssize_t amdgpu_set_smartshift_bias(struct device *dev,
1972					  struct device_attribute *attr,
1973					  const char *buf, size_t count)
1974{
1975	struct drm_device *ddev = dev_get_drvdata(dev);
1976	struct amdgpu_device *adev = drm_to_adev(ddev);
1977	int r = 0;
1978	int bias = 0;
1979
1980	if (amdgpu_in_reset(adev))
1981		return -EPERM;
1982	if (adev->in_suspend && !adev->in_runpm)
1983		return -EPERM;
1984
1985	r = pm_runtime_get_sync(ddev->dev);
1986	if (r < 0) {
1987		pm_runtime_put_autosuspend(ddev->dev);
1988		return r;
1989	}
1990
1991	r = kstrtoint(buf, 10, &bias);
1992	if (r)
1993		goto out;
1994
1995	if (bias > AMDGPU_SMARTSHIFT_MAX_BIAS)
1996		bias = AMDGPU_SMARTSHIFT_MAX_BIAS;
1997	else if (bias < AMDGPU_SMARTSHIFT_MIN_BIAS)
1998		bias = AMDGPU_SMARTSHIFT_MIN_BIAS;
1999
2000	amdgpu_smartshift_bias = bias;
2001	r = count;
2002
2003	/* TODO: update bias level with SMU message */
2004
2005out:
2006	pm_runtime_mark_last_busy(ddev->dev);
2007	pm_runtime_put_autosuspend(ddev->dev);
2008	return r;
2009}
2010
2011static int ss_power_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2012				uint32_t mask, enum amdgpu_device_attr_states *states)
2013{
2014	if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
2015		*states = ATTR_STATE_UNSUPPORTED;
2016
2017	return 0;
2018}
2019
2020static int ss_bias_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2021			       uint32_t mask, enum amdgpu_device_attr_states *states)
2022{
2023	uint32_t ss_power;
2024
2025	if (!amdgpu_device_supports_smart_shift(adev_to_drm(adev)))
2026		*states = ATTR_STATE_UNSUPPORTED;
2027	else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_APU_SHARE,
2028		 (void *)&ss_power))
2029		*states = ATTR_STATE_UNSUPPORTED;
2030	else if (amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
2031		 (void *)&ss_power))
2032		*states = ATTR_STATE_UNSUPPORTED;
2033
2034	return 0;
2035}
2036
2037/* Following items will be read out to indicate current plpd policy:
2038 *  - -1: none
2039 *  - 0: disallow
2040 *  - 1: default
2041 *  - 2: optimized
2042 */
2043static ssize_t amdgpu_get_xgmi_plpd_policy(struct device *dev,
2044					   struct device_attribute *attr,
2045					   char *buf)
2046{
2047	struct drm_device *ddev = dev_get_drvdata(dev);
2048	struct amdgpu_device *adev = drm_to_adev(ddev);
2049	char *mode_desc = "none";
2050	int mode;
2051
2052	if (amdgpu_in_reset(adev))
2053		return -EPERM;
2054	if (adev->in_suspend && !adev->in_runpm)
2055		return -EPERM;
2056
2057	mode = amdgpu_dpm_get_xgmi_plpd_mode(adev, &mode_desc);
2058
2059	return sysfs_emit(buf, "%d: %s\n", mode, mode_desc);
2060}
2061
2062/* Following argument value is expected from user to change plpd policy
2063 *  - arg 0: disallow plpd
2064 *  - arg 1: default policy
2065 *  - arg 2: optimized policy
2066 */
2067static ssize_t amdgpu_set_xgmi_plpd_policy(struct device *dev,
2068					   struct device_attribute *attr,
2069					   const char *buf, size_t count)
2070{
2071	struct drm_device *ddev = dev_get_drvdata(dev);
2072	struct amdgpu_device *adev = drm_to_adev(ddev);
2073	int mode, ret;
2074
2075	if (amdgpu_in_reset(adev))
2076		return -EPERM;
2077	if (adev->in_suspend && !adev->in_runpm)
2078		return -EPERM;
2079
2080	ret = kstrtos32(buf, 0, &mode);
2081	if (ret)
2082		return -EINVAL;
2083
2084	ret = pm_runtime_get_sync(ddev->dev);
2085	if (ret < 0) {
2086		pm_runtime_put_autosuspend(ddev->dev);
2087		return ret;
2088	}
2089
2090	ret = amdgpu_dpm_set_xgmi_plpd_mode(adev, mode);
2091
2092	pm_runtime_mark_last_busy(ddev->dev);
2093	pm_runtime_put_autosuspend(ddev->dev);
2094
2095	if (ret)
2096		return ret;
2097
2098	return count;
2099}
2100
2101static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2102	AMDGPU_DEVICE_ATTR_RW(power_dpm_state,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2103	AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,	ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2104	AMDGPU_DEVICE_ATTR_RO(pp_num_states,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2105	AMDGPU_DEVICE_ATTR_RO(pp_cur_state,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2106	AMDGPU_DEVICE_ATTR_RW(pp_force_state,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2107	AMDGPU_DEVICE_ATTR_RW(pp_table,					ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2108	AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2109	AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2110	AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2111	AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2112	AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2113	AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk1,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2114	AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2115	AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk1,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2116	AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2117	AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2118	AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,				ATTR_FLAG_BASIC),
2119	AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,				ATTR_FLAG_BASIC),
2120	AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,			ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2121	AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,			ATTR_FLAG_BASIC),
2122	AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2123	AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2124	AMDGPU_DEVICE_ATTR_RO(pcie_bw,					ATTR_FLAG_BASIC),
2125	AMDGPU_DEVICE_ATTR_RW(pp_features,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2126	AMDGPU_DEVICE_ATTR_RO(unique_id,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2127	AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,		ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2128	AMDGPU_DEVICE_ATTR_RW(apu_thermal_cap,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2129	AMDGPU_DEVICE_ATTR_RO(gpu_metrics,				ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2130	AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,			ATTR_FLAG_BASIC,
2131			      .attr_update = ss_power_attr_update),
2132	AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,			ATTR_FLAG_BASIC,
2133			      .attr_update = ss_power_attr_update),
2134	AMDGPU_DEVICE_ATTR_RW(smartshift_bias,				ATTR_FLAG_BASIC,
2135			      .attr_update = ss_bias_attr_update),
2136	AMDGPU_DEVICE_ATTR_RW(xgmi_plpd_policy,				ATTR_FLAG_BASIC),
2137	AMDGPU_DEVICE_ATTR_RO(pm_metrics,				ATTR_FLAG_BASIC,
2138			      .attr_update = amdgpu_pm_metrics_attr_update),
2139};
2140
2141static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2142			       uint32_t mask, enum amdgpu_device_attr_states *states)
2143{
2144	struct device_attribute *dev_attr = &attr->dev_attr;
2145	uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
2146	uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
2147	const char *attr_name = dev_attr->attr.name;
2148
2149	if (!(attr->flags & mask)) {
2150		*states = ATTR_STATE_UNSUPPORTED;
2151		return 0;
2152	}
2153
2154#define DEVICE_ATTR_IS(_name)	(!strcmp(attr_name, #_name))
2155
2156	if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2157		if (gc_ver < IP_VERSION(9, 0, 0))
2158			*states = ATTR_STATE_UNSUPPORTED;
2159	} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2160		if (gc_ver < IP_VERSION(9, 0, 0) ||
2161		    !amdgpu_device_has_display_hardware(adev))
2162			*states = ATTR_STATE_UNSUPPORTED;
2163	} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2164		if (mp1_ver < IP_VERSION(10, 0, 0))
2165			*states = ATTR_STATE_UNSUPPORTED;
2166	} else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2167		*states = ATTR_STATE_UNSUPPORTED;
2168		if (amdgpu_dpm_is_overdrive_supported(adev))
2169			*states = ATTR_STATE_SUPPORTED;
2170	} else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2171		if ((adev->flags & AMD_IS_APU &&
2172		     gc_ver != IP_VERSION(9, 4, 3)) ||
2173		    gc_ver == IP_VERSION(9, 0, 1))
2174			*states = ATTR_STATE_UNSUPPORTED;
2175	} else if (DEVICE_ATTR_IS(pcie_bw)) {
2176		/* PCIe Perf counters won't work on APU nodes */
2177		if (adev->flags & AMD_IS_APU)
2178			*states = ATTR_STATE_UNSUPPORTED;
2179	} else if (DEVICE_ATTR_IS(unique_id)) {
2180		switch (gc_ver) {
2181		case IP_VERSION(9, 0, 1):
2182		case IP_VERSION(9, 4, 0):
2183		case IP_VERSION(9, 4, 1):
2184		case IP_VERSION(9, 4, 2):
2185		case IP_VERSION(9, 4, 3):
2186		case IP_VERSION(10, 3, 0):
2187		case IP_VERSION(11, 0, 0):
2188		case IP_VERSION(11, 0, 1):
2189		case IP_VERSION(11, 0, 2):
2190		case IP_VERSION(11, 0, 3):
2191			*states = ATTR_STATE_SUPPORTED;
2192			break;
2193		default:
2194			*states = ATTR_STATE_UNSUPPORTED;
2195		}
2196	} else if (DEVICE_ATTR_IS(pp_features)) {
2197		if ((adev->flags & AMD_IS_APU &&
2198		     gc_ver != IP_VERSION(9, 4, 3)) ||
2199		    gc_ver < IP_VERSION(9, 0, 0))
2200			*states = ATTR_STATE_UNSUPPORTED;
2201	} else if (DEVICE_ATTR_IS(gpu_metrics)) {
2202		if (gc_ver < IP_VERSION(9, 1, 0))
2203			*states = ATTR_STATE_UNSUPPORTED;
2204	} else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
2205		if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2206		      gc_ver == IP_VERSION(10, 3, 0) ||
2207		      gc_ver == IP_VERSION(10, 1, 2) ||
2208		      gc_ver == IP_VERSION(11, 0, 0) ||
2209		      gc_ver == IP_VERSION(11, 0, 2) ||
2210		      gc_ver == IP_VERSION(11, 0, 3) ||
2211		      gc_ver == IP_VERSION(9, 4, 3)))
2212			*states = ATTR_STATE_UNSUPPORTED;
2213	} else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
2214		if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2215			   gc_ver == IP_VERSION(10, 3, 0) ||
2216			   gc_ver == IP_VERSION(11, 0, 2) ||
2217			   gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2218			*states = ATTR_STATE_UNSUPPORTED;
2219	} else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
2220		if (!(gc_ver == IP_VERSION(10, 3, 1) ||
2221		      gc_ver == IP_VERSION(10, 3, 0) ||
2222		      gc_ver == IP_VERSION(10, 1, 2) ||
2223		      gc_ver == IP_VERSION(11, 0, 0) ||
2224		      gc_ver == IP_VERSION(11, 0, 2) ||
2225		      gc_ver == IP_VERSION(11, 0, 3) ||
2226		      gc_ver == IP_VERSION(9, 4, 3)))
2227			*states = ATTR_STATE_UNSUPPORTED;
2228	} else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
2229		if (!((gc_ver == IP_VERSION(10, 3, 1) ||
2230			   gc_ver == IP_VERSION(10, 3, 0) ||
2231			   gc_ver == IP_VERSION(11, 0, 2) ||
2232			   gc_ver == IP_VERSION(11, 0, 3)) && adev->vcn.num_vcn_inst >= 2))
2233			*states = ATTR_STATE_UNSUPPORTED;
2234	} else if (DEVICE_ATTR_IS(pp_power_profile_mode)) {
2235		if (amdgpu_dpm_get_power_profile_mode(adev, NULL) == -EOPNOTSUPP)
2236			*states = ATTR_STATE_UNSUPPORTED;
2237		else if ((gc_ver == IP_VERSION(10, 3, 0) ||
2238			  gc_ver == IP_VERSION(11, 0, 3)) && amdgpu_sriov_vf(adev))
2239			*states = ATTR_STATE_UNSUPPORTED;
2240	} else if (DEVICE_ATTR_IS(xgmi_plpd_policy)) {
2241		if (amdgpu_dpm_get_xgmi_plpd_mode(adev, NULL) == XGMI_PLPD_NONE)
2242			*states = ATTR_STATE_UNSUPPORTED;
2243	} else if (DEVICE_ATTR_IS(pp_mclk_od)) {
2244		if (amdgpu_dpm_get_mclk_od(adev) == -EOPNOTSUPP)
2245			*states = ATTR_STATE_UNSUPPORTED;
2246	} else if (DEVICE_ATTR_IS(pp_sclk_od)) {
2247		if (amdgpu_dpm_get_sclk_od(adev) == -EOPNOTSUPP)
2248			*states = ATTR_STATE_UNSUPPORTED;
2249	} else if (DEVICE_ATTR_IS(apu_thermal_cap)) {
2250		u32 limit;
2251
2252		if (amdgpu_dpm_get_apu_thermal_limit(adev, &limit) ==
2253		    -EOPNOTSUPP)
2254			*states = ATTR_STATE_UNSUPPORTED;
2255	} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
2256		if (gc_ver == IP_VERSION(9, 4, 2) ||
2257		    gc_ver == IP_VERSION(9, 4, 3))
2258			*states = ATTR_STATE_UNSUPPORTED;
2259	}
2260
2261	switch (gc_ver) {
2262	case IP_VERSION(9, 4, 1):
2263	case IP_VERSION(9, 4, 2):
2264		/* the Mi series card does not support standalone mclk/socclk/fclk level setting */
2265		if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2266		    DEVICE_ATTR_IS(pp_dpm_socclk) ||
2267		    DEVICE_ATTR_IS(pp_dpm_fclk)) {
2268			dev_attr->attr.mode &= ~S_IWUGO;
2269			dev_attr->store = NULL;
2270		}
2271		break;
2272	case IP_VERSION(10, 3, 0):
2273		if (DEVICE_ATTR_IS(power_dpm_force_performance_level) &&
2274		    amdgpu_sriov_vf(adev)) {
2275			dev_attr->attr.mode &= ~0222;
2276			dev_attr->store = NULL;
2277		}
2278		break;
2279	default:
2280		break;
2281	}
2282
2283	if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2284		/* SMU MP1 does not support dcefclk level setting */
2285		if (gc_ver >= IP_VERSION(10, 0, 0)) {
2286			dev_attr->attr.mode &= ~S_IWUGO;
2287			dev_attr->store = NULL;
2288		}
2289	}
2290
2291	/* setting should not be allowed from VF if not in one VF mode */
2292	if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
2293		dev_attr->attr.mode &= ~S_IWUGO;
2294		dev_attr->store = NULL;
2295	}
2296
2297#undef DEVICE_ATTR_IS
2298
2299	return 0;
2300}
2301
2302
2303static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2304				     struct amdgpu_device_attr *attr,
2305				     uint32_t mask, struct list_head *attr_list)
2306{
2307	int ret = 0;
2308	enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2309	struct amdgpu_device_attr_entry *attr_entry;
2310	struct device_attribute *dev_attr;
2311	const char *name;
2312
2313	int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2314			   uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2315
2316	if (!attr)
2317		return -EINVAL;
2318
2319	dev_attr = &attr->dev_attr;
2320	name = dev_attr->attr.name;
2321
2322	attr_update = attr->attr_update ? attr->attr_update : default_attr_update;
2323
2324	ret = attr_update(adev, attr, mask, &attr_states);
2325	if (ret) {
2326		dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2327			name, ret);
2328		return ret;
2329	}
2330
2331	if (attr_states == ATTR_STATE_UNSUPPORTED)
2332		return 0;
2333
2334	ret = device_create_file(adev->dev, dev_attr);
2335	if (ret) {
2336		dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2337			name, ret);
2338	}
2339
2340	attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2341	if (!attr_entry)
2342		return -ENOMEM;
2343
2344	attr_entry->attr = attr;
2345	INIT_LIST_HEAD(&attr_entry->entry);
2346
2347	list_add_tail(&attr_entry->entry, attr_list);
2348
2349	return ret;
2350}
2351
2352static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2353{
2354	struct device_attribute *dev_attr = &attr->dev_attr;
2355
2356	device_remove_file(adev->dev, dev_attr);
2357}
2358
2359static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2360					     struct list_head *attr_list);
2361
2362static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2363					    struct amdgpu_device_attr *attrs,
2364					    uint32_t counts,
2365					    uint32_t mask,
2366					    struct list_head *attr_list)
2367{
2368	int ret = 0;
2369	uint32_t i = 0;
2370
2371	for (i = 0; i < counts; i++) {
2372		ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2373		if (ret)
2374			goto failed;
2375	}
2376
2377	return 0;
2378
2379failed:
2380	amdgpu_device_attr_remove_groups(adev, attr_list);
2381
2382	return ret;
2383}
2384
2385static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2386					     struct list_head *attr_list)
2387{
2388	struct amdgpu_device_attr_entry *entry, *entry_tmp;
2389
2390	if (list_empty(attr_list))
2391		return ;
2392
2393	list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2394		amdgpu_device_attr_remove(adev, entry->attr);
2395		list_del(&entry->entry);
2396		kfree(entry);
2397	}
2398}
2399
2400static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2401				      struct device_attribute *attr,
2402				      char *buf)
2403{
2404	struct amdgpu_device *adev = dev_get_drvdata(dev);
2405	int channel = to_sensor_dev_attr(attr)->index;
2406	int r, temp = 0;
2407
2408	if (channel >= PP_TEMP_MAX)
2409		return -EINVAL;
2410
2411	switch (channel) {
2412	case PP_TEMP_JUNCTION:
2413		/* get current junction temperature */
2414		r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2415					   (void *)&temp);
2416		break;
2417	case PP_TEMP_EDGE:
2418		/* get current edge temperature */
2419		r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2420					   (void *)&temp);
2421		break;
2422	case PP_TEMP_MEM:
2423		/* get current memory temperature */
2424		r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2425					   (void *)&temp);
2426		break;
2427	default:
2428		r = -EINVAL;
2429		break;
2430	}
2431
2432	if (r)
2433		return r;
2434
2435	return sysfs_emit(buf, "%d\n", temp);
2436}
2437
2438static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2439					     struct device_attribute *attr,
2440					     char *buf)
2441{
2442	struct amdgpu_device *adev = dev_get_drvdata(dev);
2443	int hyst = to_sensor_dev_attr(attr)->index;
2444	int temp;
2445
2446	if (hyst)
2447		temp = adev->pm.dpm.thermal.min_temp;
2448	else
2449		temp = adev->pm.dpm.thermal.max_temp;
2450
2451	return sysfs_emit(buf, "%d\n", temp);
2452}
2453
2454static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2455					     struct device_attribute *attr,
2456					     char *buf)
2457{
2458	struct amdgpu_device *adev = dev_get_drvdata(dev);
2459	int hyst = to_sensor_dev_attr(attr)->index;
2460	int temp;
2461
2462	if (hyst)
2463		temp = adev->pm.dpm.thermal.min_hotspot_temp;
2464	else
2465		temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2466
2467	return sysfs_emit(buf, "%d\n", temp);
2468}
2469
2470static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2471					     struct device_attribute *attr,
2472					     char *buf)
2473{
2474	struct amdgpu_device *adev = dev_get_drvdata(dev);
2475	int hyst = to_sensor_dev_attr(attr)->index;
2476	int temp;
2477
2478	if (hyst)
2479		temp = adev->pm.dpm.thermal.min_mem_temp;
2480	else
2481		temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2482
2483	return sysfs_emit(buf, "%d\n", temp);
2484}
2485
2486static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2487					     struct device_attribute *attr,
2488					     char *buf)
2489{
2490	int channel = to_sensor_dev_attr(attr)->index;
2491
2492	if (channel >= PP_TEMP_MAX)
2493		return -EINVAL;
2494
2495	return sysfs_emit(buf, "%s\n", temp_label[channel].label);
2496}
2497
2498static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2499					     struct device_attribute *attr,
2500					     char *buf)
2501{
2502	struct amdgpu_device *adev = dev_get_drvdata(dev);
2503	int channel = to_sensor_dev_attr(attr)->index;
2504	int temp = 0;
2505
2506	if (channel >= PP_TEMP_MAX)
2507		return -EINVAL;
2508
2509	switch (channel) {
2510	case PP_TEMP_JUNCTION:
2511		temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2512		break;
2513	case PP_TEMP_EDGE:
2514		temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2515		break;
2516	case PP_TEMP_MEM:
2517		temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2518		break;
2519	}
2520
2521	return sysfs_emit(buf, "%d\n", temp);
2522}
2523
2524static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2525					    struct device_attribute *attr,
2526					    char *buf)
2527{
2528	struct amdgpu_device *adev = dev_get_drvdata(dev);
2529	u32 pwm_mode = 0;
2530	int ret;
2531
2532	if (amdgpu_in_reset(adev))
2533		return -EPERM;
2534	if (adev->in_suspend && !adev->in_runpm)
2535		return -EPERM;
2536
2537	ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2538	if (ret < 0) {
2539		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2540		return ret;
2541	}
2542
2543	ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2544
2545	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2546	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2547
2548	if (ret)
2549		return -EINVAL;
2550
2551	return sysfs_emit(buf, "%u\n", pwm_mode);
2552}
2553
2554static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2555					    struct device_attribute *attr,
2556					    const char *buf,
2557					    size_t count)
2558{
2559	struct amdgpu_device *adev = dev_get_drvdata(dev);
2560	int err, ret;
2561	u32 pwm_mode;
2562	int value;
2563
2564	if (amdgpu_in_reset(adev))
2565		return -EPERM;
2566	if (adev->in_suspend && !adev->in_runpm)
2567		return -EPERM;
2568
2569	err = kstrtoint(buf, 10, &value);
2570	if (err)
2571		return err;
2572
2573	if (value == 0)
2574		pwm_mode = AMD_FAN_CTRL_NONE;
2575	else if (value == 1)
2576		pwm_mode = AMD_FAN_CTRL_MANUAL;
2577	else if (value == 2)
2578		pwm_mode = AMD_FAN_CTRL_AUTO;
2579	else
2580		return -EINVAL;
2581
2582	ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2583	if (ret < 0) {
2584		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2585		return ret;
2586	}
2587
2588	ret = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2589
2590	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2591	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2592
2593	if (ret)
2594		return -EINVAL;
2595
2596	return count;
2597}
2598
2599static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2600					 struct device_attribute *attr,
2601					 char *buf)
2602{
2603	return sysfs_emit(buf, "%i\n", 0);
2604}
2605
2606static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2607					 struct device_attribute *attr,
2608					 char *buf)
2609{
2610	return sysfs_emit(buf, "%i\n", 255);
2611}
2612
2613static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2614				     struct device_attribute *attr,
2615				     const char *buf, size_t count)
2616{
2617	struct amdgpu_device *adev = dev_get_drvdata(dev);
2618	int err;
2619	u32 value;
2620	u32 pwm_mode;
2621
2622	if (amdgpu_in_reset(adev))
2623		return -EPERM;
2624	if (adev->in_suspend && !adev->in_runpm)
2625		return -EPERM;
2626
2627	err = kstrtou32(buf, 10, &value);
2628	if (err)
2629		return err;
2630
2631	err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2632	if (err < 0) {
2633		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2634		return err;
2635	}
2636
2637	err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2638	if (err)
2639		goto out;
2640
2641	if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2642		pr_info("manual fan speed control should be enabled first\n");
2643		err = -EINVAL;
2644		goto out;
2645	}
2646
2647	err = amdgpu_dpm_set_fan_speed_pwm(adev, value);
2648
2649out:
2650	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2651	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2652
2653	if (err)
2654		return err;
2655
2656	return count;
2657}
2658
2659static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2660				     struct device_attribute *attr,
2661				     char *buf)
2662{
2663	struct amdgpu_device *adev = dev_get_drvdata(dev);
2664	int err;
2665	u32 speed = 0;
2666
2667	if (amdgpu_in_reset(adev))
2668		return -EPERM;
2669	if (adev->in_suspend && !adev->in_runpm)
2670		return -EPERM;
2671
2672	err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2673	if (err < 0) {
2674		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2675		return err;
2676	}
2677
2678	err = amdgpu_dpm_get_fan_speed_pwm(adev, &speed);
2679
2680	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2681	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2682
2683	if (err)
2684		return err;
2685
2686	return sysfs_emit(buf, "%i\n", speed);
2687}
2688
2689static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2690					   struct device_attribute *attr,
2691					   char *buf)
2692{
2693	struct amdgpu_device *adev = dev_get_drvdata(dev);
2694	int err;
2695	u32 speed = 0;
2696
2697	if (amdgpu_in_reset(adev))
2698		return -EPERM;
2699	if (adev->in_suspend && !adev->in_runpm)
2700		return -EPERM;
2701
2702	err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2703	if (err < 0) {
2704		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2705		return err;
2706	}
2707
2708	err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2709
2710	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2711	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2712
2713	if (err)
2714		return err;
2715
2716	return sysfs_emit(buf, "%i\n", speed);
2717}
2718
2719static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2720					 struct device_attribute *attr,
2721					 char *buf)
2722{
2723	struct amdgpu_device *adev = dev_get_drvdata(dev);
2724	u32 min_rpm = 0;
2725	int r;
2726
2727	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2728				   (void *)&min_rpm);
2729
2730	if (r)
2731		return r;
2732
2733	return sysfs_emit(buf, "%d\n", min_rpm);
2734}
2735
2736static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2737					 struct device_attribute *attr,
2738					 char *buf)
2739{
2740	struct amdgpu_device *adev = dev_get_drvdata(dev);
2741	u32 max_rpm = 0;
2742	int r;
2743
2744	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2745				   (void *)&max_rpm);
2746
2747	if (r)
2748		return r;
2749
2750	return sysfs_emit(buf, "%d\n", max_rpm);
2751}
2752
2753static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2754					   struct device_attribute *attr,
2755					   char *buf)
2756{
2757	struct amdgpu_device *adev = dev_get_drvdata(dev);
2758	int err;
2759	u32 rpm = 0;
2760
2761	if (amdgpu_in_reset(adev))
2762		return -EPERM;
2763	if (adev->in_suspend && !adev->in_runpm)
2764		return -EPERM;
2765
2766	err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2767	if (err < 0) {
2768		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2769		return err;
2770	}
2771
2772	err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2773
2774	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2775	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2776
2777	if (err)
2778		return err;
2779
2780	return sysfs_emit(buf, "%i\n", rpm);
2781}
2782
2783static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2784				     struct device_attribute *attr,
2785				     const char *buf, size_t count)
2786{
2787	struct amdgpu_device *adev = dev_get_drvdata(dev);
2788	int err;
2789	u32 value;
2790	u32 pwm_mode;
2791
2792	if (amdgpu_in_reset(adev))
2793		return -EPERM;
2794	if (adev->in_suspend && !adev->in_runpm)
2795		return -EPERM;
2796
2797	err = kstrtou32(buf, 10, &value);
2798	if (err)
2799		return err;
2800
2801	err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2802	if (err < 0) {
2803		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2804		return err;
2805	}
2806
2807	err = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2808	if (err)
2809		goto out;
2810
2811	if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2812		err = -ENODATA;
2813		goto out;
2814	}
2815
2816	err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2817
2818out:
2819	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2820	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2821
2822	if (err)
2823		return err;
2824
2825	return count;
2826}
2827
2828static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2829					    struct device_attribute *attr,
2830					    char *buf)
2831{
2832	struct amdgpu_device *adev = dev_get_drvdata(dev);
2833	u32 pwm_mode = 0;
2834	int ret;
2835
2836	if (amdgpu_in_reset(adev))
2837		return -EPERM;
2838	if (adev->in_suspend && !adev->in_runpm)
2839		return -EPERM;
2840
2841	ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2842	if (ret < 0) {
2843		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2844		return ret;
2845	}
2846
2847	ret = amdgpu_dpm_get_fan_control_mode(adev, &pwm_mode);
2848
2849	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2850	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2851
2852	if (ret)
2853		return -EINVAL;
2854
2855	return sysfs_emit(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2856}
2857
2858static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2859					    struct device_attribute *attr,
2860					    const char *buf,
2861					    size_t count)
2862{
2863	struct amdgpu_device *adev = dev_get_drvdata(dev);
2864	int err;
2865	int value;
2866	u32 pwm_mode;
2867
2868	if (amdgpu_in_reset(adev))
2869		return -EPERM;
2870	if (adev->in_suspend && !adev->in_runpm)
2871		return -EPERM;
2872
2873	err = kstrtoint(buf, 10, &value);
2874	if (err)
2875		return err;
2876
2877	if (value == 0)
2878		pwm_mode = AMD_FAN_CTRL_AUTO;
2879	else if (value == 1)
2880		pwm_mode = AMD_FAN_CTRL_MANUAL;
2881	else
2882		return -EINVAL;
2883
2884	err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2885	if (err < 0) {
2886		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2887		return err;
2888	}
2889
2890	err = amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2891
2892	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2893	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2894
2895	if (err)
2896		return -EINVAL;
2897
2898	return count;
2899}
2900
2901static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2902					struct device_attribute *attr,
2903					char *buf)
2904{
2905	struct amdgpu_device *adev = dev_get_drvdata(dev);
2906	u32 vddgfx;
2907	int r;
2908
2909	/* get the voltage */
2910	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDGFX,
2911				   (void *)&vddgfx);
2912	if (r)
2913		return r;
2914
2915	return sysfs_emit(buf, "%d\n", vddgfx);
2916}
2917
2918static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2919					      struct device_attribute *attr,
2920					      char *buf)
2921{
2922	return sysfs_emit(buf, "vddgfx\n");
2923}
2924
2925static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2926				       struct device_attribute *attr,
2927				       char *buf)
2928{
2929	struct amdgpu_device *adev = dev_get_drvdata(dev);
2930	u32 vddnb;
2931	int r;
2932
2933	/* only APUs have vddnb */
2934	if  (!(adev->flags & AMD_IS_APU))
2935		return -EINVAL;
2936
2937	/* get the voltage */
2938	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_VDDNB,
2939				   (void *)&vddnb);
2940	if (r)
2941		return r;
2942
2943	return sysfs_emit(buf, "%d\n", vddnb);
2944}
2945
2946static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2947					      struct device_attribute *attr,
2948					      char *buf)
2949{
2950	return sysfs_emit(buf, "vddnb\n");
2951}
2952
2953static int amdgpu_hwmon_get_power(struct device *dev,
2954				  enum amd_pp_sensors sensor)
2955{
2956	struct amdgpu_device *adev = dev_get_drvdata(dev);
2957	unsigned int uw;
2958	u32 query = 0;
2959	int r;
2960
2961	r = amdgpu_hwmon_get_sensor_generic(adev, sensor, (void *)&query);
2962	if (r)
2963		return r;
2964
2965	/* convert to microwatts */
2966	uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2967
2968	return uw;
2969}
2970
2971static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2972					   struct device_attribute *attr,
2973					   char *buf)
2974{
2975	ssize_t val;
2976
2977	val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_AVG_POWER);
2978	if (val < 0)
2979		return val;
2980
2981	return sysfs_emit(buf, "%zd\n", val);
2982}
2983
2984static ssize_t amdgpu_hwmon_show_power_input(struct device *dev,
2985					     struct device_attribute *attr,
2986					     char *buf)
2987{
2988	ssize_t val;
2989
2990	val = amdgpu_hwmon_get_power(dev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER);
2991	if (val < 0)
2992		return val;
2993
2994	return sysfs_emit(buf, "%zd\n", val);
2995}
2996
2997static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
2998					struct device_attribute *attr,
2999					char *buf,
3000					enum pp_power_limit_level pp_limit_level)
3001{
3002	struct amdgpu_device *adev = dev_get_drvdata(dev);
3003	enum pp_power_type power_type = to_sensor_dev_attr(attr)->index;
3004	uint32_t limit;
3005	ssize_t size;
3006	int r;
3007
3008	if (amdgpu_in_reset(adev))
3009		return -EPERM;
3010	if (adev->in_suspend && !adev->in_runpm)
3011		return -EPERM;
3012
3013	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3014	if (r < 0) {
3015		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3016		return r;
3017	}
3018
3019	r = amdgpu_dpm_get_power_limit(adev, &limit,
3020				      pp_limit_level, power_type);
3021
3022	if (!r)
3023		size = sysfs_emit(buf, "%u\n", limit * 1000000);
3024	else
3025		size = sysfs_emit(buf, "\n");
3026
3027	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3028	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3029
3030	return size;
3031}
3032
3033static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
3034					 struct device_attribute *attr,
3035					 char *buf)
3036{
3037	return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MIN);
3038}
3039
3040static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
3041					 struct device_attribute *attr,
3042					 char *buf)
3043{
3044	return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_MAX);
3045
3046}
3047
3048static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
3049					 struct device_attribute *attr,
3050					 char *buf)
3051{
3052	return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_CURRENT);
3053
3054}
3055
3056static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
3057					 struct device_attribute *attr,
3058					 char *buf)
3059{
3060	return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf, PP_PWR_LIMIT_DEFAULT);
3061
3062}
3063
3064static ssize_t amdgpu_hwmon_show_power_label(struct device *dev,
3065					 struct device_attribute *attr,
3066					 char *buf)
3067{
3068	struct amdgpu_device *adev = dev_get_drvdata(dev);
3069	uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3070
3071	if (gc_ver == IP_VERSION(10, 3, 1))
3072		return sysfs_emit(buf, "%s\n",
3073				  to_sensor_dev_attr(attr)->index == PP_PWR_TYPE_FAST ?
3074				  "fastPPT" : "slowPPT");
3075	else
3076		return sysfs_emit(buf, "PPT\n");
3077}
3078
3079static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
3080		struct device_attribute *attr,
3081		const char *buf,
3082		size_t count)
3083{
3084	struct amdgpu_device *adev = dev_get_drvdata(dev);
3085	int limit_type = to_sensor_dev_attr(attr)->index;
3086	int err;
3087	u32 value;
3088
3089	if (amdgpu_in_reset(adev))
3090		return -EPERM;
3091	if (adev->in_suspend && !adev->in_runpm)
3092		return -EPERM;
3093
3094	if (amdgpu_sriov_vf(adev))
3095		return -EINVAL;
3096
3097	err = kstrtou32(buf, 10, &value);
3098	if (err)
3099		return err;
3100
3101	value = value / 1000000; /* convert to Watt */
3102	value |= limit_type << 24;
3103
3104	err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3105	if (err < 0) {
3106		pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3107		return err;
3108	}
3109
3110	err = amdgpu_dpm_set_power_limit(adev, value);
3111
3112	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3113	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3114
3115	if (err)
3116		return err;
3117
3118	return count;
3119}
3120
3121static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3122				      struct device_attribute *attr,
3123				      char *buf)
3124{
3125	struct amdgpu_device *adev = dev_get_drvdata(dev);
3126	uint32_t sclk;
3127	int r;
3128
3129	/* get the sclk */
3130	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3131				   (void *)&sclk);
3132	if (r)
3133		return r;
3134
3135	return sysfs_emit(buf, "%u\n", sclk * 10 * 1000);
3136}
3137
3138static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3139					    struct device_attribute *attr,
3140					    char *buf)
3141{
3142	return sysfs_emit(buf, "sclk\n");
3143}
3144
3145static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3146				      struct device_attribute *attr,
3147				      char *buf)
3148{
3149	struct amdgpu_device *adev = dev_get_drvdata(dev);
3150	uint32_t mclk;
3151	int r;
3152
3153	/* get the sclk */
3154	r = amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3155				   (void *)&mclk);
3156	if (r)
3157		return r;
3158
3159	return sysfs_emit(buf, "%u\n", mclk * 10 * 1000);
3160}
3161
3162static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3163					    struct device_attribute *attr,
3164					    char *buf)
3165{
3166	return sysfs_emit(buf, "mclk\n");
3167}
3168
3169/**
3170 * DOC: hwmon
3171 *
3172 * The amdgpu driver exposes the following sensor interfaces:
3173 *
3174 * - GPU temperature (via the on-die sensor)
3175 *
3176 * - GPU voltage
3177 *
3178 * - Northbridge voltage (APUs only)
3179 *
3180 * - GPU power
3181 *
3182 * - GPU fan
3183 *
3184 * - GPU gfx/compute engine clock
3185 *
3186 * - GPU memory clock (dGPU only)
3187 *
3188 * hwmon interfaces for GPU temperature:
3189 *
3190 * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3191 *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3192 *
3193 * - temp[1-3]_label: temperature channel label
3194 *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3195 *
3196 * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3197 *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3198 *
3199 * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3200 *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3201 *
3202 * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3203 *   - these are supported on SOC15 dGPUs only
3204 *
3205 * hwmon interfaces for GPU voltage:
3206 *
3207 * - in0_input: the voltage on the GPU in millivolts
3208 *
3209 * - in1_input: the voltage on the Northbridge in millivolts
3210 *
3211 * hwmon interfaces for GPU power:
3212 *
3213 * - power1_average: average power used by the SoC in microWatts.  On APUs this includes the CPU.
3214 *
3215 * - power1_input: instantaneous power used by the SoC in microWatts.  On APUs this includes the CPU.
3216 *
3217 * - power1_cap_min: minimum cap supported in microWatts
3218 *
3219 * - power1_cap_max: maximum cap supported in microWatts
3220 *
3221 * - power1_cap: selected power cap in microWatts
3222 *
3223 * hwmon interfaces for GPU fan:
3224 *
3225 * - pwm1: pulse width modulation fan level (0-255)
3226 *
3227 * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3228 *
3229 * - pwm1_min: pulse width modulation fan control minimum level (0)
3230 *
3231 * - pwm1_max: pulse width modulation fan control maximum level (255)
3232 *
3233 * - fan1_min: a minimum value Unit: revolution/min (RPM)
3234 *
3235 * - fan1_max: a maximum value Unit: revolution/max (RPM)
3236 *
3237 * - fan1_input: fan speed in RPM
3238 *
3239 * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3240 *
3241 * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3242 *
3243 * NOTE: DO NOT set the fan speed via "pwm1" and "fan[1-\*]_target" interfaces at the same time.
3244 *       That will get the former one overridden.
3245 *
3246 * hwmon interfaces for GPU clocks:
3247 *
3248 * - freq1_input: the gfx/compute clock in hertz
3249 *
3250 * - freq2_input: the memory clock in hertz
3251 *
3252 * You can use hwmon tools like sensors to view this information on your system.
3253 *
3254 */
3255
3256static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3257static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3258static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3259static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3260static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3261static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3262static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3263static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3264static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3265static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3266static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3267static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3268static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3269static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3270static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3271static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3272static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3273static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3274static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3275static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3276static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3277static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3278static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3279static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3280static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3281static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3282static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3283static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3284static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3285static SENSOR_DEVICE_ATTR(power1_input, S_IRUGO, amdgpu_hwmon_show_power_input, NULL, 0);
3286static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3287static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3288static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3289static SENSOR_DEVICE_ATTR(power1_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 0);
3290static SENSOR_DEVICE_ATTR(power1_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 0);
3291static SENSOR_DEVICE_ATTR(power2_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 1);
3292static SENSOR_DEVICE_ATTR(power2_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 1);
3293static SENSOR_DEVICE_ATTR(power2_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 1);
3294static SENSOR_DEVICE_ATTR(power2_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 1);
3295static SENSOR_DEVICE_ATTR(power2_cap_default, S_IRUGO, amdgpu_hwmon_show_power_cap_default, NULL, 1);
3296static SENSOR_DEVICE_ATTR(power2_label, S_IRUGO, amdgpu_hwmon_show_power_label, NULL, 1);
3297static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3298static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3299static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3300static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3301
3302static struct attribute *hwmon_attributes[] = {
3303	&sensor_dev_attr_temp1_input.dev_attr.attr,
3304	&sensor_dev_attr_temp1_crit.dev_attr.attr,
3305	&sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3306	&sensor_dev_attr_temp2_input.dev_attr.attr,
3307	&sensor_dev_attr_temp2_crit.dev_attr.attr,
3308	&sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3309	&sensor_dev_attr_temp3_input.dev_attr.attr,
3310	&sensor_dev_attr_temp3_crit.dev_attr.attr,
3311	&sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3312	&sensor_dev_attr_temp1_emergency.dev_attr.attr,
3313	&sensor_dev_attr_temp2_emergency.dev_attr.attr,
3314	&sensor_dev_attr_temp3_emergency.dev_attr.attr,
3315	&sensor_dev_attr_temp1_label.dev_attr.attr,
3316	&sensor_dev_attr_temp2_label.dev_attr.attr,
3317	&sensor_dev_attr_temp3_label.dev_attr.attr,
3318	&sensor_dev_attr_pwm1.dev_attr.attr,
3319	&sensor_dev_attr_pwm1_enable.dev_attr.attr,
3320	&sensor_dev_attr_pwm1_min.dev_attr.attr,
3321	&sensor_dev_attr_pwm1_max.dev_attr.attr,
3322	&sensor_dev_attr_fan1_input.dev_attr.attr,
3323	&sensor_dev_attr_fan1_min.dev_attr.attr,
3324	&sensor_dev_attr_fan1_max.dev_attr.attr,
3325	&sensor_dev_attr_fan1_target.dev_attr.attr,
3326	&sensor_dev_attr_fan1_enable.dev_attr.attr,
3327	&sensor_dev_attr_in0_input.dev_attr.attr,
3328	&sensor_dev_attr_in0_label.dev_attr.attr,
3329	&sensor_dev_attr_in1_input.dev_attr.attr,
3330	&sensor_dev_attr_in1_label.dev_attr.attr,
3331	&sensor_dev_attr_power1_average.dev_attr.attr,
3332	&sensor_dev_attr_power1_input.dev_attr.attr,
3333	&sensor_dev_attr_power1_cap_max.dev_attr.attr,
3334	&sensor_dev_attr_power1_cap_min.dev_attr.attr,
3335	&sensor_dev_attr_power1_cap.dev_attr.attr,
3336	&sensor_dev_attr_power1_cap_default.dev_attr.attr,
3337	&sensor_dev_attr_power1_label.dev_attr.attr,
3338	&sensor_dev_attr_power2_average.dev_attr.attr,
3339	&sensor_dev_attr_power2_cap_max.dev_attr.attr,
3340	&sensor_dev_attr_power2_cap_min.dev_attr.attr,
3341	&sensor_dev_attr_power2_cap.dev_attr.attr,
3342	&sensor_dev_attr_power2_cap_default.dev_attr.attr,
3343	&sensor_dev_attr_power2_label.dev_attr.attr,
3344	&sensor_dev_attr_freq1_input.dev_attr.attr,
3345	&sensor_dev_attr_freq1_label.dev_attr.attr,
3346	&sensor_dev_attr_freq2_input.dev_attr.attr,
3347	&sensor_dev_attr_freq2_label.dev_attr.attr,
3348	NULL
3349};
3350
3351static umode_t hwmon_attributes_visible(struct kobject *kobj,
3352					struct attribute *attr, int index)
3353{
3354	struct device *dev = kobj_to_dev(kobj);
3355	struct amdgpu_device *adev = dev_get_drvdata(dev);
3356	umode_t effective_mode = attr->mode;
3357	uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
3358	uint32_t tmp;
3359
3360	/* under pp one vf mode manage of hwmon attributes is not supported */
3361	if (amdgpu_sriov_is_pp_one_vf(adev))
3362		effective_mode &= ~S_IWUSR;
3363
3364	/* Skip fan attributes if fan is not present */
3365	if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3366	    attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3367	    attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3368	    attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3369	    attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3370	    attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3371	    attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3372	    attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3373	    attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3374		return 0;
3375
3376	/* Skip fan attributes on APU */
3377	if ((adev->flags & AMD_IS_APU) &&
3378	    (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3379	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3380	     attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3381	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3382	     attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3383	     attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3384	     attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3385	     attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3386	     attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3387		return 0;
3388
3389	/* Skip crit temp on APU */
3390	if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
3391	    (gc_ver == IP_VERSION(9, 4, 3))) &&
3392	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3393	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3394		return 0;
3395
3396	/* Skip limit attributes if DPM is not enabled */
3397	if (!adev->pm.dpm_enabled &&
3398	    (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3399	     attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3400	     attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3401	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3402	     attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3403	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3404	     attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3405	     attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3406	     attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3407	     attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3408	     attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3409		return 0;
3410
3411	/* mask fan attributes if we have no bindings for this asic to expose */
3412	if (((amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3413	      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3414	    ((amdgpu_dpm_get_fan_control_mode(adev, NULL) == -EOPNOTSUPP) &&
3415	     attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3416		effective_mode &= ~S_IRUGO;
3417
3418	if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3419	      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3420	      ((amdgpu_dpm_set_fan_control_mode(adev, U32_MAX) == -EOPNOTSUPP) &&
3421	      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3422		effective_mode &= ~S_IWUSR;
3423
3424	/* not implemented yet for APUs other than GC 10.3.1 (vangogh) and 9.4.3 */
3425	if (((adev->family == AMDGPU_FAMILY_SI) ||
3426	     ((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(10, 3, 1)) &&
3427	      (gc_ver != IP_VERSION(9, 4, 3)))) &&
3428	    (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3429	     attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr ||
3430	     attr == &sensor_dev_attr_power1_cap.dev_attr.attr ||
3431	     attr == &sensor_dev_attr_power1_cap_default.dev_attr.attr))
3432		return 0;
3433
3434	/* not implemented yet for APUs having < GC 9.3.0 (Renoir) */
3435	if (((adev->family == AMDGPU_FAMILY_SI) ||
3436	     ((adev->flags & AMD_IS_APU) && (gc_ver < IP_VERSION(9, 3, 0)))) &&
3437	    (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3438		return 0;
3439
3440	/* not all products support both average and instantaneous */
3441	if (attr == &sensor_dev_attr_power1_average.dev_attr.attr &&
3442	    amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&tmp) == -EOPNOTSUPP)
3443		return 0;
3444	if (attr == &sensor_dev_attr_power1_input.dev_attr.attr &&
3445	    amdgpu_hwmon_get_sensor_generic(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&tmp) == -EOPNOTSUPP)
3446		return 0;
3447
3448	/* hide max/min values if we can't both query and manage the fan */
3449	if (((amdgpu_dpm_set_fan_speed_pwm(adev, U32_MAX) == -EOPNOTSUPP) &&
3450	      (amdgpu_dpm_get_fan_speed_pwm(adev, NULL) == -EOPNOTSUPP) &&
3451	      (amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3452	      (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP)) &&
3453	    (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3454	     attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3455		return 0;
3456
3457	if ((amdgpu_dpm_set_fan_speed_rpm(adev, U32_MAX) == -EOPNOTSUPP) &&
3458	     (amdgpu_dpm_get_fan_speed_rpm(adev, NULL) == -EOPNOTSUPP) &&
3459	     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3460	     attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3461		return 0;
3462
3463	if ((adev->family == AMDGPU_FAMILY_SI ||	/* not implemented yet */
3464	     adev->family == AMDGPU_FAMILY_KV ||	/* not implemented yet */
3465	     (gc_ver == IP_VERSION(9, 4, 3))) &&
3466	    (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3467	     attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3468		return 0;
3469
3470	/* only APUs other than gc 9,4,3 have vddnb */
3471	if ((!(adev->flags & AMD_IS_APU) || (gc_ver == IP_VERSION(9, 4, 3))) &&
3472	    (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3473	     attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3474		return 0;
3475
3476	/* no mclk on APUs other than gc 9,4,3*/
3477	if (((adev->flags & AMD_IS_APU) && (gc_ver != IP_VERSION(9, 4, 3))) &&
3478	    (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3479	     attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3480		return 0;
3481
3482	if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3483	    (gc_ver != IP_VERSION(9, 4, 3)) &&
3484	    (attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3485	     attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3486	     attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3487	     attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3488	     attr == &sensor_dev_attr_temp3_label.dev_attr.attr ||
3489	     attr == &sensor_dev_attr_temp3_crit.dev_attr.attr))
3490		return 0;
3491
3492	/* hotspot temperature for gc 9,4,3*/
3493	if (gc_ver == IP_VERSION(9, 4, 3)) {
3494		if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
3495		    attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3496		    attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
3497			return 0;
3498
3499		if (attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3500		    attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr)
3501			return attr->mode;
3502	}
3503
3504	/* only SOC15 dGPUs support hotspot and mem temperatures */
3505	if (((adev->flags & AMD_IS_APU) || gc_ver < IP_VERSION(9, 0, 0)) &&
3506	    (attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3507	     attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3508	     attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3509	     attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3510	     attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr))
3511		return 0;
3512
3513	/* only Vangogh has fast PPT limit and power labels */
3514	if (!(gc_ver == IP_VERSION(10, 3, 1)) &&
3515	    (attr == &sensor_dev_attr_power2_average.dev_attr.attr ||
3516	     attr == &sensor_dev_attr_power2_cap_max.dev_attr.attr ||
3517	     attr == &sensor_dev_attr_power2_cap_min.dev_attr.attr ||
3518	     attr == &sensor_dev_attr_power2_cap.dev_attr.attr ||
3519	     attr == &sensor_dev_attr_power2_cap_default.dev_attr.attr ||
3520	     attr == &sensor_dev_attr_power2_label.dev_attr.attr))
3521		return 0;
3522
3523	return effective_mode;
3524}
3525
3526static const struct attribute_group hwmon_attrgroup = {
3527	.attrs = hwmon_attributes,
3528	.is_visible = hwmon_attributes_visible,
3529};
3530
3531static const struct attribute_group *hwmon_groups[] = {
3532	&hwmon_attrgroup,
3533	NULL
3534};
3535
3536static int amdgpu_retrieve_od_settings(struct amdgpu_device *adev,
3537				       enum pp_clock_type od_type,
3538				       char *buf)
3539{
3540	int size = 0;
3541	int ret;
3542
3543	if (amdgpu_in_reset(adev))
3544		return -EPERM;
3545	if (adev->in_suspend && !adev->in_runpm)
3546		return -EPERM;
3547
3548	ret = pm_runtime_get_sync(adev->dev);
3549	if (ret < 0) {
3550		pm_runtime_put_autosuspend(adev->dev);
3551		return ret;
3552	}
3553
3554	size = amdgpu_dpm_print_clock_levels(adev, od_type, buf);
3555	if (size == 0)
3556		size = sysfs_emit(buf, "\n");
3557
3558	pm_runtime_mark_last_busy(adev->dev);
3559	pm_runtime_put_autosuspend(adev->dev);
3560
3561	return size;
3562}
3563
3564static int parse_input_od_command_lines(const char *buf,
3565					size_t count,
3566					u32 *type,
3567					long *params,
3568					uint32_t *num_of_params)
3569{
3570	const char delimiter[3] = {' ', '\n', '\0'};
3571	uint32_t parameter_size = 0;
3572	char buf_cpy[128] = {0};
3573	char *tmp_str, *sub_str;
3574	int ret;
3575
3576	if (count > sizeof(buf_cpy) - 1)
3577		return -EINVAL;
3578
3579	memcpy(buf_cpy, buf, count);
3580	tmp_str = buf_cpy;
3581
3582	/* skip heading spaces */
3583	while (isspace(*tmp_str))
3584		tmp_str++;
3585
3586	switch (*tmp_str) {
3587	case 'c':
3588		*type = PP_OD_COMMIT_DPM_TABLE;
3589		return 0;
3590	case 'r':
3591		params[parameter_size] = *type;
3592		*num_of_params = 1;
3593		*type = PP_OD_RESTORE_DEFAULT_TABLE;
3594		return 0;
3595	default:
3596		break;
3597	}
3598
3599	while ((sub_str = strsep(&tmp_str, delimiter)) != NULL) {
3600		if (strlen(sub_str) == 0)
3601			continue;
3602
3603		ret = kstrtol(sub_str, 0, &params[parameter_size]);
3604		if (ret)
3605			return -EINVAL;
3606		parameter_size++;
3607
3608		while (isspace(*tmp_str))
3609			tmp_str++;
3610	}
3611
3612	*num_of_params = parameter_size;
3613
3614	return 0;
3615}
3616
3617static int
3618amdgpu_distribute_custom_od_settings(struct amdgpu_device *adev,
3619				     enum PP_OD_DPM_TABLE_COMMAND cmd_type,
3620				     const char *in_buf,
3621				     size_t count)
3622{
3623	uint32_t parameter_size = 0;
3624	long parameter[64];
3625	int ret;
3626
3627	if (amdgpu_in_reset(adev))
3628		return -EPERM;
3629	if (adev->in_suspend && !adev->in_runpm)
3630		return -EPERM;
3631
3632	ret = parse_input_od_command_lines(in_buf,
3633					   count,
3634					   &cmd_type,
3635					   parameter,
3636					   &parameter_size);
3637	if (ret)
3638		return ret;
3639
3640	ret = pm_runtime_get_sync(adev->dev);
3641	if (ret < 0)
3642		goto err_out0;
3643
3644	ret = amdgpu_dpm_odn_edit_dpm_table(adev,
3645					    cmd_type,
3646					    parameter,
3647					    parameter_size);
3648	if (ret)
3649		goto err_out1;
3650
3651	if (cmd_type == PP_OD_COMMIT_DPM_TABLE) {
3652		ret = amdgpu_dpm_dispatch_task(adev,
3653					       AMD_PP_TASK_READJUST_POWER_STATE,
3654					       NULL);
3655		if (ret)
3656			goto err_out1;
3657	}
3658
3659	pm_runtime_mark_last_busy(adev->dev);
3660	pm_runtime_put_autosuspend(adev->dev);
3661
3662	return count;
3663
3664err_out1:
3665	pm_runtime_mark_last_busy(adev->dev);
3666err_out0:
3667	pm_runtime_put_autosuspend(adev->dev);
3668
3669	return ret;
3670}
3671
3672/**
3673 * DOC: fan_curve
3674 *
3675 * The amdgpu driver provides a sysfs API for checking and adjusting the fan
3676 * control curve line.
3677 *
3678 * Reading back the file shows you the current settings(temperature in Celsius
3679 * degree and fan speed in pwm) applied to every anchor point of the curve line
3680 * and their permitted ranges if changable.
3681 *
3682 * Writing a desired string(with the format like "anchor_point_index temperature
3683 * fan_speed_in_pwm") to the file, change the settings for the specific anchor
3684 * point accordingly.
3685 *
3686 * When you have finished the editing, write "c" (commit) to the file to commit
3687 * your changes.
3688 *
3689 * If you want to reset to the default value, write "r" (reset) to the file to
3690 * reset them
3691 *
3692 * There are two fan control modes supported: auto and manual. With auto mode,
3693 * PMFW handles the fan speed control(how fan speed reacts to ASIC temperature).
3694 * While with manual mode, users can set their own fan curve line as what
3695 * described here. Normally the ASIC is booted up with auto mode. Any
3696 * settings via this interface will switch the fan control to manual mode
3697 * implicitly.
3698 */
3699static ssize_t fan_curve_show(struct kobject *kobj,
3700			      struct kobj_attribute *attr,
3701			      char *buf)
3702{
3703	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3704	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3705
3706	return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_CURVE, buf);
3707}
3708
3709static ssize_t fan_curve_store(struct kobject *kobj,
3710			       struct kobj_attribute *attr,
3711			       const char *buf,
3712			       size_t count)
3713{
3714	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3715	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3716
3717	return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3718							     PP_OD_EDIT_FAN_CURVE,
3719							     buf,
3720							     count);
3721}
3722
3723static umode_t fan_curve_visible(struct amdgpu_device *adev)
3724{
3725	umode_t umode = 0000;
3726
3727	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_RETRIEVE)
3728		umode |= S_IRUSR | S_IRGRP | S_IROTH;
3729
3730	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_CURVE_SET)
3731		umode |= S_IWUSR;
3732
3733	return umode;
3734}
3735
3736/**
3737 * DOC: acoustic_limit_rpm_threshold
3738 *
3739 * The amdgpu driver provides a sysfs API for checking and adjusting the
3740 * acoustic limit in RPM for fan control.
3741 *
3742 * Reading back the file shows you the current setting and the permitted
3743 * ranges if changable.
3744 *
3745 * Writing an integer to the file, change the setting accordingly.
3746 *
3747 * When you have finished the editing, write "c" (commit) to the file to commit
3748 * your changes.
3749 *
3750 * If you want to reset to the default value, write "r" (reset) to the file to
3751 * reset them
3752 *
3753 * This setting works under auto fan control mode only. It adjusts the PMFW's
3754 * behavior about the maximum speed in RPM the fan can spin. Setting via this
3755 * interface will switch the fan control to auto mode implicitly.
3756 */
3757static ssize_t acoustic_limit_threshold_show(struct kobject *kobj,
3758					     struct kobj_attribute *attr,
3759					     char *buf)
3760{
3761	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3762	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3763
3764	return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_LIMIT, buf);
3765}
3766
3767static ssize_t acoustic_limit_threshold_store(struct kobject *kobj,
3768					      struct kobj_attribute *attr,
3769					      const char *buf,
3770					      size_t count)
3771{
3772	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3773	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3774
3775	return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3776							     PP_OD_EDIT_ACOUSTIC_LIMIT,
3777							     buf,
3778							     count);
3779}
3780
3781static umode_t acoustic_limit_threshold_visible(struct amdgpu_device *adev)
3782{
3783	umode_t umode = 0000;
3784
3785	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_RETRIEVE)
3786		umode |= S_IRUSR | S_IRGRP | S_IROTH;
3787
3788	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_LIMIT_THRESHOLD_SET)
3789		umode |= S_IWUSR;
3790
3791	return umode;
3792}
3793
3794/**
3795 * DOC: acoustic_target_rpm_threshold
3796 *
3797 * The amdgpu driver provides a sysfs API for checking and adjusting the
3798 * acoustic target in RPM for fan control.
3799 *
3800 * Reading back the file shows you the current setting and the permitted
3801 * ranges if changable.
3802 *
3803 * Writing an integer to the file, change the setting accordingly.
3804 *
3805 * When you have finished the editing, write "c" (commit) to the file to commit
3806 * your changes.
3807 *
3808 * If you want to reset to the default value, write "r" (reset) to the file to
3809 * reset them
3810 *
3811 * This setting works under auto fan control mode only. It can co-exist with
3812 * other settings which can work also under auto mode. It adjusts the PMFW's
3813 * behavior about the maximum speed in RPM the fan can spin when ASIC
3814 * temperature is not greater than target temperature. Setting via this
3815 * interface will switch the fan control to auto mode implicitly.
3816 */
3817static ssize_t acoustic_target_threshold_show(struct kobject *kobj,
3818					      struct kobj_attribute *attr,
3819					      char *buf)
3820{
3821	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3822	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3823
3824	return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_ACOUSTIC_TARGET, buf);
3825}
3826
3827static ssize_t acoustic_target_threshold_store(struct kobject *kobj,
3828					       struct kobj_attribute *attr,
3829					       const char *buf,
3830					       size_t count)
3831{
3832	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3833	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3834
3835	return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3836							     PP_OD_EDIT_ACOUSTIC_TARGET,
3837							     buf,
3838							     count);
3839}
3840
3841static umode_t acoustic_target_threshold_visible(struct amdgpu_device *adev)
3842{
3843	umode_t umode = 0000;
3844
3845	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_RETRIEVE)
3846		umode |= S_IRUSR | S_IRGRP | S_IROTH;
3847
3848	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_ACOUSTIC_TARGET_THRESHOLD_SET)
3849		umode |= S_IWUSR;
3850
3851	return umode;
3852}
3853
3854/**
3855 * DOC: fan_target_temperature
3856 *
3857 * The amdgpu driver provides a sysfs API for checking and adjusting the
3858 * target tempeature in Celsius degree for fan control.
3859 *
3860 * Reading back the file shows you the current setting and the permitted
3861 * ranges if changable.
3862 *
3863 * Writing an integer to the file, change the setting accordingly.
3864 *
3865 * When you have finished the editing, write "c" (commit) to the file to commit
3866 * your changes.
3867 *
3868 * If you want to reset to the default value, write "r" (reset) to the file to
3869 * reset them
3870 *
3871 * This setting works under auto fan control mode only. It can co-exist with
3872 * other settings which can work also under auto mode. Paring with the
3873 * acoustic_target_rpm_threshold setting, they define the maximum speed in
3874 * RPM the fan can spin when ASIC temperature is not greater than target
3875 * temperature. Setting via this interface will switch the fan control to
3876 * auto mode implicitly.
3877 */
3878static ssize_t fan_target_temperature_show(struct kobject *kobj,
3879					   struct kobj_attribute *attr,
3880					   char *buf)
3881{
3882	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3883	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3884
3885	return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_TARGET_TEMPERATURE, buf);
3886}
3887
3888static ssize_t fan_target_temperature_store(struct kobject *kobj,
3889					    struct kobj_attribute *attr,
3890					    const char *buf,
3891					    size_t count)
3892{
3893	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3894	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3895
3896	return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3897							     PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
3898							     buf,
3899							     count);
3900}
3901
3902static umode_t fan_target_temperature_visible(struct amdgpu_device *adev)
3903{
3904	umode_t umode = 0000;
3905
3906	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE)
3907		umode |= S_IRUSR | S_IRGRP | S_IROTH;
3908
3909	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET)
3910		umode |= S_IWUSR;
3911
3912	return umode;
3913}
3914
3915/**
3916 * DOC: fan_minimum_pwm
3917 *
3918 * The amdgpu driver provides a sysfs API for checking and adjusting the
3919 * minimum fan speed in PWM.
3920 *
3921 * Reading back the file shows you the current setting and the permitted
3922 * ranges if changable.
3923 *
3924 * Writing an integer to the file, change the setting accordingly.
3925 *
3926 * When you have finished the editing, write "c" (commit) to the file to commit
3927 * your changes.
3928 *
3929 * If you want to reset to the default value, write "r" (reset) to the file to
3930 * reset them
3931 *
3932 * This setting works under auto fan control mode only. It can co-exist with
3933 * other settings which can work also under auto mode. It adjusts the PMFW's
3934 * behavior about the minimum fan speed in PWM the fan should spin. Setting
3935 * via this interface will switch the fan control to auto mode implicitly.
3936 */
3937static ssize_t fan_minimum_pwm_show(struct kobject *kobj,
3938				    struct kobj_attribute *attr,
3939				    char *buf)
3940{
3941	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3942	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3943
3944	return (ssize_t)amdgpu_retrieve_od_settings(adev, OD_FAN_MINIMUM_PWM, buf);
3945}
3946
3947static ssize_t fan_minimum_pwm_store(struct kobject *kobj,
3948				     struct kobj_attribute *attr,
3949				     const char *buf,
3950				     size_t count)
3951{
3952	struct od_kobj *container = container_of(kobj, struct od_kobj, kobj);
3953	struct amdgpu_device *adev = (struct amdgpu_device *)container->priv;
3954
3955	return (ssize_t)amdgpu_distribute_custom_od_settings(adev,
3956							     PP_OD_EDIT_FAN_MINIMUM_PWM,
3957							     buf,
3958							     count);
3959}
3960
3961static umode_t fan_minimum_pwm_visible(struct amdgpu_device *adev)
3962{
3963	umode_t umode = 0000;
3964
3965	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE)
3966		umode |= S_IRUSR | S_IRGRP | S_IROTH;
3967
3968	if (adev->pm.od_feature_mask & OD_OPS_SUPPORT_FAN_MINIMUM_PWM_SET)
3969		umode |= S_IWUSR;
3970
3971	return umode;
3972}
3973
3974static struct od_feature_set amdgpu_od_set = {
3975	.containers = {
3976		[0] = {
3977			.name = "fan_ctrl",
3978			.sub_feature = {
3979				[0] = {
3980					.name = "fan_curve",
3981					.ops = {
3982						.is_visible = fan_curve_visible,
3983						.show = fan_curve_show,
3984						.store = fan_curve_store,
3985					},
3986				},
3987				[1] = {
3988					.name = "acoustic_limit_rpm_threshold",
3989					.ops = {
3990						.is_visible = acoustic_limit_threshold_visible,
3991						.show = acoustic_limit_threshold_show,
3992						.store = acoustic_limit_threshold_store,
3993					},
3994				},
3995				[2] = {
3996					.name = "acoustic_target_rpm_threshold",
3997					.ops = {
3998						.is_visible = acoustic_target_threshold_visible,
3999						.show = acoustic_target_threshold_show,
4000						.store = acoustic_target_threshold_store,
4001					},
4002				},
4003				[3] = {
4004					.name = "fan_target_temperature",
4005					.ops = {
4006						.is_visible = fan_target_temperature_visible,
4007						.show = fan_target_temperature_show,
4008						.store = fan_target_temperature_store,
4009					},
4010				},
4011				[4] = {
4012					.name = "fan_minimum_pwm",
4013					.ops = {
4014						.is_visible = fan_minimum_pwm_visible,
4015						.show = fan_minimum_pwm_show,
4016						.store = fan_minimum_pwm_store,
4017					},
4018				},
4019			},
4020		},
4021	},
4022};
4023
4024static void od_kobj_release(struct kobject *kobj)
4025{
4026	struct od_kobj *od_kobj = container_of(kobj, struct od_kobj, kobj);
4027
4028	kfree(od_kobj);
4029}
4030
4031static const struct kobj_type od_ktype = {
4032	.release	= od_kobj_release,
4033	.sysfs_ops	= &kobj_sysfs_ops,
4034};
4035
4036static void amdgpu_od_set_fini(struct amdgpu_device *adev)
4037{
4038	struct od_kobj *container, *container_next;
4039	struct od_attribute *attribute, *attribute_next;
4040
4041	if (list_empty(&adev->pm.od_kobj_list))
4042		return;
4043
4044	list_for_each_entry_safe(container, container_next,
4045				 &adev->pm.od_kobj_list, entry) {
4046		list_del(&container->entry);
4047
4048		list_for_each_entry_safe(attribute, attribute_next,
4049					 &container->attribute, entry) {
4050			list_del(&attribute->entry);
4051			sysfs_remove_file(&container->kobj,
4052					  &attribute->attribute.attr);
4053			kfree(attribute);
4054		}
4055
4056		kobject_put(&container->kobj);
4057	}
4058}
4059
4060static bool amdgpu_is_od_feature_supported(struct amdgpu_device *adev,
4061					   struct od_feature_ops *feature_ops)
4062{
4063	umode_t mode;
4064
4065	if (!feature_ops->is_visible)
4066		return false;
4067
4068	/*
4069	 * If the feature has no user read and write mode set,
4070	 * we can assume the feature is actually not supported.(?)
4071	 * And the revelant sysfs interface should not be exposed.
4072	 */
4073	mode = feature_ops->is_visible(adev);
4074	if (mode & (S_IRUSR | S_IWUSR))
4075		return true;
4076
4077	return false;
4078}
4079
4080static bool amdgpu_od_is_self_contained(struct amdgpu_device *adev,
4081					struct od_feature_container *container)
4082{
4083	int i;
4084
4085	/*
4086	 * If there is no valid entry within the container, the container
4087	 * is recognized as a self contained container. And the valid entry
4088	 * here means it has a valid naming and it is visible/supported by
4089	 * the ASIC.
4090	 */
4091	for (i = 0; i < ARRAY_SIZE(container->sub_feature); i++) {
4092		if (container->sub_feature[i].name &&
4093		    amdgpu_is_od_feature_supported(adev,
4094			&container->sub_feature[i].ops))
4095			return false;
4096	}
4097
4098	return true;
4099}
4100
4101static int amdgpu_od_set_init(struct amdgpu_device *adev)
4102{
4103	struct od_kobj *top_set, *sub_set;
4104	struct od_attribute *attribute;
4105	struct od_feature_container *container;
4106	struct od_feature_item *feature;
4107	int i, j;
4108	int ret;
4109
4110	/* Setup the top `gpu_od` directory which holds all other OD interfaces */
4111	top_set = kzalloc(sizeof(*top_set), GFP_KERNEL);
4112	if (!top_set)
4113		return -ENOMEM;
4114	list_add(&top_set->entry, &adev->pm.od_kobj_list);
4115
4116	ret = kobject_init_and_add(&top_set->kobj,
4117				   &od_ktype,
4118				   &adev->dev->kobj,
4119				   "%s",
4120				   "gpu_od");
4121	if (ret)
4122		goto err_out;
4123	INIT_LIST_HEAD(&top_set->attribute);
4124	top_set->priv = adev;
4125
4126	for (i = 0; i < ARRAY_SIZE(amdgpu_od_set.containers); i++) {
4127		container = &amdgpu_od_set.containers[i];
4128
4129		if (!container->name)
4130			continue;
4131
4132		/*
4133		 * If there is valid entries within the container, the container
4134		 * will be presented as a sub directory and all its holding entries
4135		 * will be presented as plain files under it.
4136		 * While if there is no valid entry within the container, the container
4137		 * itself will be presented as a plain file under top `gpu_od` directory.
4138		 */
4139		if (amdgpu_od_is_self_contained(adev, container)) {
4140			if (!amdgpu_is_od_feature_supported(adev,
4141			     &container->ops))
4142				continue;
4143
4144			/*
4145			 * The container is presented as a plain file under top `gpu_od`
4146			 * directory.
4147			 */
4148			attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4149			if (!attribute) {
4150				ret = -ENOMEM;
4151				goto err_out;
4152			}
4153			list_add(&attribute->entry, &top_set->attribute);
4154
4155			attribute->attribute.attr.mode =
4156					container->ops.is_visible(adev);
4157			attribute->attribute.attr.name = container->name;
4158			attribute->attribute.show =
4159					container->ops.show;
4160			attribute->attribute.store =
4161					container->ops.store;
4162			ret = sysfs_create_file(&top_set->kobj,
4163						&attribute->attribute.attr);
4164			if (ret)
4165				goto err_out;
4166		} else {
4167			/* The container is presented as a sub directory. */
4168			sub_set = kzalloc(sizeof(*sub_set), GFP_KERNEL);
4169			if (!sub_set) {
4170				ret = -ENOMEM;
4171				goto err_out;
4172			}
4173			list_add(&sub_set->entry, &adev->pm.od_kobj_list);
4174
4175			ret = kobject_init_and_add(&sub_set->kobj,
4176						   &od_ktype,
4177						   &top_set->kobj,
4178						   "%s",
4179						   container->name);
4180			if (ret)
4181				goto err_out;
4182			INIT_LIST_HEAD(&sub_set->attribute);
4183			sub_set->priv = adev;
4184
4185			for (j = 0; j < ARRAY_SIZE(container->sub_feature); j++) {
4186				feature = &container->sub_feature[j];
4187				if (!feature->name)
4188					continue;
4189
4190				if (!amdgpu_is_od_feature_supported(adev,
4191				     &feature->ops))
4192					continue;
4193
4194				/*
4195				 * With the container presented as a sub directory, the entry within
4196				 * it is presented as a plain file under the sub directory.
4197				 */
4198				attribute = kzalloc(sizeof(*attribute), GFP_KERNEL);
4199				if (!attribute) {
4200					ret = -ENOMEM;
4201					goto err_out;
4202				}
4203				list_add(&attribute->entry, &sub_set->attribute);
4204
4205				attribute->attribute.attr.mode =
4206						feature->ops.is_visible(adev);
4207				attribute->attribute.attr.name = feature->name;
4208				attribute->attribute.show =
4209						feature->ops.show;
4210				attribute->attribute.store =
4211						feature->ops.store;
4212				ret = sysfs_create_file(&sub_set->kobj,
4213							&attribute->attribute.attr);
4214				if (ret)
4215					goto err_out;
4216			}
4217		}
4218	}
4219
4220	return 0;
4221
4222err_out:
4223	amdgpu_od_set_fini(adev);
4224
4225	return ret;
4226}
4227
4228int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
4229{
4230	enum amdgpu_sriov_vf_mode mode;
4231	uint32_t mask = 0;
4232	int ret;
4233
4234	if (adev->pm.sysfs_initialized)
4235		return 0;
4236
4237	INIT_LIST_HEAD(&adev->pm.pm_attr_list);
4238
4239	if (adev->pm.dpm_enabled == 0)
4240		return 0;
4241
4242	mode = amdgpu_virt_get_sriov_vf_mode(adev);
4243
4244	/* under multi-vf mode, the hwmon attributes are all not supported */
4245	if (mode != SRIOV_VF_MODE_MULTI_VF) {
4246		adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
4247														DRIVER_NAME, adev,
4248														hwmon_groups);
4249		if (IS_ERR(adev->pm.int_hwmon_dev)) {
4250			ret = PTR_ERR(adev->pm.int_hwmon_dev);
4251			dev_err(adev->dev, "Unable to register hwmon device: %d\n", ret);
4252			return ret;
4253		}
4254	}
4255
4256	switch (mode) {
4257	case SRIOV_VF_MODE_ONE_VF:
4258		mask = ATTR_FLAG_ONEVF;
4259		break;
4260	case SRIOV_VF_MODE_MULTI_VF:
4261		mask = 0;
4262		break;
4263	case SRIOV_VF_MODE_BARE_METAL:
4264	default:
4265		mask = ATTR_FLAG_MASK_ALL;
4266		break;
4267	}
4268
4269	ret = amdgpu_device_attr_create_groups(adev,
4270					       amdgpu_device_attrs,
4271					       ARRAY_SIZE(amdgpu_device_attrs),
4272					       mask,
4273					       &adev->pm.pm_attr_list);
4274	if (ret)
4275		goto err_out0;
4276
4277	if (amdgpu_dpm_is_overdrive_supported(adev)) {
4278		ret = amdgpu_od_set_init(adev);
4279		if (ret)
4280			goto err_out1;
4281	}
4282
4283	adev->pm.sysfs_initialized = true;
4284
4285	return 0;
4286
4287err_out1:
4288	amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4289err_out0:
4290	if (adev->pm.int_hwmon_dev)
4291		hwmon_device_unregister(adev->pm.int_hwmon_dev);
4292
4293	return ret;
4294}
4295
4296void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
4297{
4298	amdgpu_od_set_fini(adev);
4299
4300	if (adev->pm.int_hwmon_dev)
4301		hwmon_device_unregister(adev->pm.int_hwmon_dev);
4302
4303	amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
4304}
4305
4306/*
4307 * Debugfs info
4308 */
4309#if defined(CONFIG_DEBUG_FS)
4310
4311static void amdgpu_debugfs_prints_cpu_info(struct seq_file *m,
4312					   struct amdgpu_device *adev)
4313{
4314	uint16_t *p_val;
4315	uint32_t size;
4316	int i;
4317	uint32_t num_cpu_cores = amdgpu_dpm_get_num_cpu_cores(adev);
4318
4319	if (amdgpu_dpm_is_cclk_dpm_supported(adev)) {
4320		p_val = kcalloc(num_cpu_cores, sizeof(uint16_t),
4321				GFP_KERNEL);
4322
4323		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
4324					    (void *)p_val, &size)) {
4325			for (i = 0; i < num_cpu_cores; i++)
4326				seq_printf(m, "\t%u MHz (CPU%d)\n",
4327					   *(p_val + i), i);
4328		}
4329
4330		kfree(p_val);
4331	}
4332}
4333
4334static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
4335{
4336	uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
4337	uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
4338	uint32_t value;
4339	uint64_t value64 = 0;
4340	uint32_t query = 0;
4341	int size;
4342
4343	/* GPU Clocks */
4344	size = sizeof(value);
4345	seq_printf(m, "GFX Clocks and Power:\n");
4346
4347	amdgpu_debugfs_prints_cpu_info(m, adev);
4348
4349	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
4350		seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
4351	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
4352		seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
4353	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
4354		seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
4355	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
4356		seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
4357	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
4358		seq_printf(m, "\t%u mV (VDDGFX)\n", value);
4359	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
4360		seq_printf(m, "\t%u mV (VDDNB)\n", value);
4361	size = sizeof(uint32_t);
4362	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_AVG_POWER, (void *)&query, &size)) {
4363		if (adev->flags & AMD_IS_APU)
4364			seq_printf(m, "\t%u.%02u W (average SoC including CPU)\n", query >> 8, query & 0xff);
4365		else
4366			seq_printf(m, "\t%u.%02u W (average SoC)\n", query >> 8, query & 0xff);
4367	}
4368	size = sizeof(uint32_t);
4369	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_INPUT_POWER, (void *)&query, &size)) {
4370		if (adev->flags & AMD_IS_APU)
4371			seq_printf(m, "\t%u.%02u W (current SoC including CPU)\n", query >> 8, query & 0xff);
4372		else
4373			seq_printf(m, "\t%u.%02u W (current SoC)\n", query >> 8, query & 0xff);
4374	}
4375	size = sizeof(value);
4376	seq_printf(m, "\n");
4377
4378	/* GPU Temp */
4379	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
4380		seq_printf(m, "GPU Temperature: %u C\n", value/1000);
4381
4382	/* GPU Load */
4383	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
4384		seq_printf(m, "GPU Load: %u %%\n", value);
4385	/* MEM Load */
4386	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
4387		seq_printf(m, "MEM Load: %u %%\n", value);
4388
4389	seq_printf(m, "\n");
4390
4391	/* SMC feature mask */
4392	if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
4393		seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
4394
4395	/* ASICs greater than CHIP_VEGA20 supports these sensors */
4396	if (gc_ver != IP_VERSION(9, 4, 0) && mp1_ver > IP_VERSION(9, 0, 0)) {
4397		/* VCN clocks */
4398		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
4399			if (!value) {
4400				seq_printf(m, "VCN: Powered down\n");
4401			} else {
4402				seq_printf(m, "VCN: Powered up\n");
4403				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4404					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4405				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4406					seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4407			}
4408		}
4409		seq_printf(m, "\n");
4410	} else {
4411		/* UVD clocks */
4412		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
4413			if (!value) {
4414				seq_printf(m, "UVD: Powered down\n");
4415			} else {
4416				seq_printf(m, "UVD: Powered up\n");
4417				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
4418					seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
4419				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
4420					seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
4421			}
4422		}
4423		seq_printf(m, "\n");
4424
4425		/* VCE clocks */
4426		if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
4427			if (!value) {
4428				seq_printf(m, "VCE: Powered down\n");
4429			} else {
4430				seq_printf(m, "VCE: Powered up\n");
4431				if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
4432					seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
4433			}
4434		}
4435	}
4436
4437	return 0;
4438}
4439
4440static const struct cg_flag_name clocks[] = {
4441	{AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
4442	{AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
4443	{AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
4444	{AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
4445	{AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
4446	{AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
4447	{AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
4448	{AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
4449	{AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
4450	{AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
4451	{AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
4452	{AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
4453	{AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
4454	{AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
4455	{AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
4456	{AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
4457	{AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
4458	{AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
4459	{AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
4460	{AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
4461	{AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
4462	{AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
4463	{AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
4464	{AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
4465	{AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
4466	{AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
4467	{AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
4468	{AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
4469	{AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
4470	{AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
4471	{AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
4472	{AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
4473	{AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
4474	{AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
4475	{0, NULL},
4476};
4477
4478static void amdgpu_parse_cg_state(struct seq_file *m, u64 flags)
4479{
4480	int i;
4481
4482	for (i = 0; clocks[i].flag; i++)
4483		seq_printf(m, "\t%s: %s\n", clocks[i].name,
4484			   (flags & clocks[i].flag) ? "On" : "Off");
4485}
4486
4487static int amdgpu_debugfs_pm_info_show(struct seq_file *m, void *unused)
4488{
4489	struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
4490	struct drm_device *dev = adev_to_drm(adev);
4491	u64 flags = 0;
4492	int r;
4493
4494	if (amdgpu_in_reset(adev))
4495		return -EPERM;
4496	if (adev->in_suspend && !adev->in_runpm)
4497		return -EPERM;
4498
4499	r = pm_runtime_get_sync(dev->dev);
4500	if (r < 0) {
4501		pm_runtime_put_autosuspend(dev->dev);
4502		return r;
4503	}
4504
4505	if (amdgpu_dpm_debugfs_print_current_performance_level(adev, m)) {
4506		r = amdgpu_debugfs_pm_info_pp(m, adev);
4507		if (r)
4508			goto out;
4509	}
4510
4511	amdgpu_device_ip_get_clockgating_state(adev, &flags);
4512
4513	seq_printf(m, "Clock Gating Flags Mask: 0x%llx\n", flags);
4514	amdgpu_parse_cg_state(m, flags);
4515	seq_printf(m, "\n");
4516
4517out:
4518	pm_runtime_mark_last_busy(dev->dev);
4519	pm_runtime_put_autosuspend(dev->dev);
4520
4521	return r;
4522}
4523
4524DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_pm_info);
4525
4526/*
4527 * amdgpu_pm_priv_buffer_read - Read memory region allocated to FW
4528 *
4529 * Reads debug memory region allocated to PMFW
4530 */
4531static ssize_t amdgpu_pm_prv_buffer_read(struct file *f, char __user *buf,
4532					 size_t size, loff_t *pos)
4533{
4534	struct amdgpu_device *adev = file_inode(f)->i_private;
4535	size_t smu_prv_buf_size;
4536	void *smu_prv_buf;
4537	int ret = 0;
4538
4539	if (amdgpu_in_reset(adev))
4540		return -EPERM;
4541	if (adev->in_suspend && !adev->in_runpm)
4542		return -EPERM;
4543
4544	ret = amdgpu_dpm_get_smu_prv_buf_details(adev, &smu_prv_buf, &smu_prv_buf_size);
4545	if (ret)
4546		return ret;
4547
4548	if (!smu_prv_buf || !smu_prv_buf_size)
4549		return -EINVAL;
4550
4551	return simple_read_from_buffer(buf, size, pos, smu_prv_buf,
4552				       smu_prv_buf_size);
4553}
4554
4555static const struct file_operations amdgpu_debugfs_pm_prv_buffer_fops = {
4556	.owner = THIS_MODULE,
4557	.open = simple_open,
4558	.read = amdgpu_pm_prv_buffer_read,
4559	.llseek = default_llseek,
4560};
4561
4562#endif
4563
4564void amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
4565{
4566#if defined(CONFIG_DEBUG_FS)
4567	struct drm_minor *minor = adev_to_drm(adev)->primary;
4568	struct dentry *root = minor->debugfs_root;
4569
4570	if (!adev->pm.dpm_enabled)
4571		return;
4572
4573	debugfs_create_file("amdgpu_pm_info", 0444, root, adev,
4574			    &amdgpu_debugfs_pm_info_fops);
4575
4576	if (adev->pm.smu_prv_buffer_size > 0)
4577		debugfs_create_file_size("amdgpu_pm_prv_buffer", 0444, root,
4578					 adev,
4579					 &amdgpu_debugfs_pm_prv_buffer_fops,
4580					 adev->pm.smu_prv_buffer_size);
4581
4582	amdgpu_dpm_stb_debug_fs_init(adev);
4583#endif
4584}