Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright (C) 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#if !defined (_navi10_ENUM_HEADER)
22#define _navi10_ENUM_HEADER
23
24#ifndef _DRIVER_BUILD
25#ifndef GL_ZERO
26#define GL__ZERO BLEND_ZERO
27#define GL__ONE BLEND_ONE
28#define GL__SRC_COLOR BLEND_SRC_COLOR
29#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
30#define GL__DST_COLOR BLEND_DST_COLOR
31#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
32#define GL__SRC_ALPHA BLEND_SRC_ALPHA
33#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
34#define GL__DST_ALPHA BLEND_DST_ALPHA
35#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
36#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
37#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
38#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
39#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
40#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
41#endif
42#endif
43
44/*******************************************************
45 * GDS DATA_TYPE Enums
46 *******************************************************/
47
48#ifndef ENUMS_GDS_PERFCOUNT_SELECT_H
49#define ENUMS_GDS_PERFCOUNT_SELECT_H
50typedef enum GDS_PERFCOUNT_SELECT {
51 GDS_PERF_SEL_DS_ADDR_CONFL = 0,
52 GDS_PERF_SEL_DS_BANK_CONFL = 1,
53 GDS_PERF_SEL_WBUF_FLUSH = 2,
54 GDS_PERF_SEL_WR_COMP = 3,
55 GDS_PERF_SEL_WBUF_WR = 4,
56 GDS_PERF_SEL_RBUF_HIT = 5,
57 GDS_PERF_SEL_RBUF_MISS = 6,
58 GDS_PERF_SEL_SE0_SH0_NORET = 7,
59 GDS_PERF_SEL_SE0_SH0_RET = 8,
60 GDS_PERF_SEL_SE0_SH0_ORD_CNT = 9,
61 GDS_PERF_SEL_SE0_SH0_2COMP_REQ = 10,
62 GDS_PERF_SEL_SE0_SH0_ORD_WAVE_VALID = 11,
63 GDS_PERF_SEL_SE0_SH0_GDS_DATA_VALID = 12,
64 GDS_PERF_SEL_SE0_SH0_GDS_STALL_BY_ORD = 13,
65 GDS_PERF_SEL_SE0_SH0_GDS_WR_OP = 14,
66 GDS_PERF_SEL_SE0_SH0_GDS_RD_OP = 15,
67 GDS_PERF_SEL_SE0_SH0_GDS_ATOM_OP = 16,
68 GDS_PERF_SEL_SE0_SH0_GDS_REL_OP = 17,
69 GDS_PERF_SEL_SE0_SH0_GDS_CMPXCH_OP = 18,
70 GDS_PERF_SEL_SE0_SH0_GDS_BYTE_OP = 19,
71 GDS_PERF_SEL_SE0_SH0_GDS_SHORT_OP = 20,
72 GDS_PERF_SEL_SE0_SH1_NORET = 21,
73 GDS_PERF_SEL_SE0_SH1_RET = 22,
74 GDS_PERF_SEL_SE0_SH1_ORD_CNT = 23,
75 GDS_PERF_SEL_SE0_SH1_2COMP_REQ = 24,
76 GDS_PERF_SEL_SE0_SH1_ORD_WAVE_VALID = 25,
77 GDS_PERF_SEL_SE0_SH1_GDS_DATA_VALID = 26,
78 GDS_PERF_SEL_SE0_SH1_GDS_STALL_BY_ORD = 27,
79 GDS_PERF_SEL_SE0_SH1_GDS_WR_OP = 28,
80 GDS_PERF_SEL_SE0_SH1_GDS_RD_OP = 29,
81 GDS_PERF_SEL_SE0_SH1_GDS_ATOM_OP = 30,
82 GDS_PERF_SEL_SE0_SH1_GDS_REL_OP = 31,
83 GDS_PERF_SEL_SE0_SH1_GDS_CMPXCH_OP = 32,
84 GDS_PERF_SEL_SE0_SH1_GDS_BYTE_OP = 33,
85 GDS_PERF_SEL_SE0_SH1_GDS_SHORT_OP = 34,
86 GDS_PERF_SEL_SE1_SH0_NORET = 35,
87 GDS_PERF_SEL_SE1_SH0_RET = 36,
88 GDS_PERF_SEL_SE1_SH0_ORD_CNT = 37,
89 GDS_PERF_SEL_SE1_SH0_2COMP_REQ = 38,
90 GDS_PERF_SEL_SE1_SH0_ORD_WAVE_VALID = 39,
91 GDS_PERF_SEL_SE1_SH0_GDS_DATA_VALID = 40,
92 GDS_PERF_SEL_SE1_SH0_GDS_STALL_BY_ORD = 41,
93 GDS_PERF_SEL_SE1_SH0_GDS_WR_OP = 42,
94 GDS_PERF_SEL_SE1_SH0_GDS_RD_OP = 43,
95 GDS_PERF_SEL_SE1_SH0_GDS_ATOM_OP = 44,
96 GDS_PERF_SEL_SE1_SH0_GDS_REL_OP = 45,
97 GDS_PERF_SEL_SE1_SH0_GDS_CMPXCH_OP = 46,
98 GDS_PERF_SEL_SE1_SH0_GDS_BYTE_OP = 47,
99 GDS_PERF_SEL_SE1_SH0_GDS_SHORT_OP = 48,
100 GDS_PERF_SEL_SE1_SH1_NORET = 49,
101 GDS_PERF_SEL_SE1_SH1_RET = 50,
102 GDS_PERF_SEL_SE1_SH1_ORD_CNT = 51,
103 GDS_PERF_SEL_SE1_SH1_2COMP_REQ = 52,
104 GDS_PERF_SEL_SE1_SH1_ORD_WAVE_VALID = 53,
105 GDS_PERF_SEL_SE1_SH1_GDS_DATA_VALID = 54,
106 GDS_PERF_SEL_SE1_SH1_GDS_STALL_BY_ORD = 55,
107 GDS_PERF_SEL_SE1_SH1_GDS_WR_OP = 56,
108 GDS_PERF_SEL_SE1_SH1_GDS_RD_OP = 57,
109 GDS_PERF_SEL_SE1_SH1_GDS_ATOM_OP = 58,
110 GDS_PERF_SEL_SE1_SH1_GDS_REL_OP = 59,
111 GDS_PERF_SEL_SE1_SH1_GDS_CMPXCH_OP = 60,
112 GDS_PERF_SEL_SE1_SH1_GDS_BYTE_OP = 61,
113 GDS_PERF_SEL_SE1_SH1_GDS_SHORT_OP = 62,
114 GDS_PERF_SEL_SE2_SH0_NORET = 63,
115 GDS_PERF_SEL_SE2_SH0_RET = 64,
116 GDS_PERF_SEL_SE2_SH0_ORD_CNT = 65,
117 GDS_PERF_SEL_SE2_SH0_2COMP_REQ = 66,
118 GDS_PERF_SEL_SE2_SH0_ORD_WAVE_VALID = 67,
119 GDS_PERF_SEL_SE2_SH0_GDS_DATA_VALID = 68,
120 GDS_PERF_SEL_SE2_SH0_GDS_STALL_BY_ORD = 69,
121 GDS_PERF_SEL_SE2_SH0_GDS_WR_OP = 70,
122 GDS_PERF_SEL_SE2_SH0_GDS_RD_OP = 71,
123 GDS_PERF_SEL_SE2_SH0_GDS_ATOM_OP = 72,
124 GDS_PERF_SEL_SE2_SH0_GDS_REL_OP = 73,
125 GDS_PERF_SEL_SE2_SH0_GDS_CMPXCH_OP = 74,
126 GDS_PERF_SEL_SE2_SH0_GDS_BYTE_OP = 75,
127 GDS_PERF_SEL_SE2_SH0_GDS_SHORT_OP = 76,
128 GDS_PERF_SEL_SE2_SH1_NORET = 77,
129 GDS_PERF_SEL_SE2_SH1_RET = 78,
130 GDS_PERF_SEL_SE2_SH1_ORD_CNT = 79,
131 GDS_PERF_SEL_SE2_SH1_2COMP_REQ = 80,
132 GDS_PERF_SEL_SE2_SH1_ORD_WAVE_VALID = 81,
133 GDS_PERF_SEL_SE2_SH1_GDS_DATA_VALID = 82,
134 GDS_PERF_SEL_SE2_SH1_GDS_STALL_BY_ORD = 83,
135 GDS_PERF_SEL_SE2_SH1_GDS_WR_OP = 84,
136 GDS_PERF_SEL_SE2_SH1_GDS_RD_OP = 85,
137 GDS_PERF_SEL_SE2_SH1_GDS_ATOM_OP = 86,
138 GDS_PERF_SEL_SE2_SH1_GDS_REL_OP = 87,
139 GDS_PERF_SEL_SE2_SH1_GDS_CMPXCH_OP = 88,
140 GDS_PERF_SEL_SE2_SH1_GDS_BYTE_OP = 89,
141 GDS_PERF_SEL_SE2_SH1_GDS_SHORT_OP = 90,
142 GDS_PERF_SEL_SE3_SH0_NORET = 91,
143 GDS_PERF_SEL_SE3_SH0_RET = 92,
144 GDS_PERF_SEL_SE3_SH0_ORD_CNT = 93,
145 GDS_PERF_SEL_SE3_SH0_2COMP_REQ = 94,
146 GDS_PERF_SEL_SE3_SH0_ORD_WAVE_VALID = 95,
147 GDS_PERF_SEL_SE3_SH0_GDS_DATA_VALID = 96,
148 GDS_PERF_SEL_SE3_SH0_GDS_STALL_BY_ORD = 97,
149 GDS_PERF_SEL_SE3_SH0_GDS_WR_OP = 98,
150 GDS_PERF_SEL_SE3_SH0_GDS_RD_OP = 99,
151 GDS_PERF_SEL_SE3_SH0_GDS_ATOM_OP = 100,
152 GDS_PERF_SEL_SE3_SH0_GDS_REL_OP = 101,
153 GDS_PERF_SEL_SE3_SH0_GDS_CMPXCH_OP = 102,
154 GDS_PERF_SEL_SE3_SH0_GDS_BYTE_OP = 103,
155 GDS_PERF_SEL_SE3_SH0_GDS_SHORT_OP = 104,
156 GDS_PERF_SEL_SE3_SH1_NORET = 105,
157 GDS_PERF_SEL_SE3_SH1_RET = 106,
158 GDS_PERF_SEL_SE3_SH1_ORD_CNT = 107,
159 GDS_PERF_SEL_SE3_SH1_2COMP_REQ = 108,
160 GDS_PERF_SEL_SE3_SH1_ORD_WAVE_VALID = 109,
161 GDS_PERF_SEL_SE3_SH1_GDS_DATA_VALID = 110,
162 GDS_PERF_SEL_SE3_SH1_GDS_STALL_BY_ORD = 111,
163 GDS_PERF_SEL_SE3_SH1_GDS_WR_OP = 112,
164 GDS_PERF_SEL_SE3_SH1_GDS_RD_OP = 113,
165 GDS_PERF_SEL_SE3_SH1_GDS_ATOM_OP = 114,
166 GDS_PERF_SEL_SE3_SH1_GDS_REL_OP = 115,
167 GDS_PERF_SEL_SE3_SH1_GDS_CMPXCH_OP = 116,
168 GDS_PERF_SEL_SE3_SH1_GDS_BYTE_OP = 117,
169 GDS_PERF_SEL_SE3_SH1_GDS_SHORT_OP = 118,
170 GDS_PERF_SEL_GWS_RELEASED = 119,
171 GDS_PERF_SEL_GWS_BYPASS = 120,
172} GDS_PERFCOUNT_SELECT;
173#endif /*ENUMS_GDS_PERFCOUNT_SELECT_H*/
174
175/*******************************************************
176 * Chip Enums
177 *******************************************************/
178
179/*
180 * GATCL1RequestType enum
181 */
182
183typedef enum GATCL1RequestType {
184GATCL1_TYPE_NORMAL = 0x00000000,
185GATCL1_TYPE_SHOOTDOWN = 0x00000001,
186GATCL1_TYPE_BYPASS = 0x00000002,
187} GATCL1RequestType;
188
189/*
190 * UTCL1RequestType enum
191 */
192
193typedef enum UTCL1RequestType {
194UTCL1_TYPE_NORMAL = 0x00000000,
195UTCL1_TYPE_SHOOTDOWN = 0x00000001,
196UTCL1_TYPE_BYPASS = 0x00000002,
197} UTCL1RequestType;
198
199/*
200 * UTCL1FaultType enum
201 */
202
203typedef enum UTCL1FaultType {
204UTCL1_XNACK_SUCCESS = 0x00000000,
205UTCL1_XNACK_RETRY = 0x00000001,
206UTCL1_XNACK_PRT = 0x00000002,
207UTCL1_XNACK_NO_RETRY = 0x00000003,
208} UTCL1FaultType;
209
210/*
211 * UTCL0RequestType enum
212 */
213
214typedef enum UTCL0RequestType {
215UTCL0_TYPE_NORMAL = 0x00000000,
216UTCL0_TYPE_SHOOTDOWN = 0x00000001,
217UTCL0_TYPE_BYPASS = 0x00000002,
218} UTCL0RequestType;
219
220/*
221 * UTCL0FaultType enum
222 */
223
224typedef enum UTCL0FaultType {
225UTCL0_XNACK_SUCCESS = 0x00000000,
226UTCL0_XNACK_RETRY = 0x00000001,
227UTCL0_XNACK_PRT = 0x00000002,
228UTCL0_XNACK_NO_RETRY = 0x00000003,
229} UTCL0FaultType;
230
231/*
232 * VMEMCMD_RETURN_ORDER enum
233 */
234
235typedef enum VMEMCMD_RETURN_ORDER {
236VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000,
237VMEMCMD_RETURN_IN_ORDER = 0x00000001,
238VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002,
239} VMEMCMD_RETURN_ORDER;
240
241/*
242 * GL0V_CACHE_POLICIES enum
243 */
244
245typedef enum GL0V_CACHE_POLICIES {
246GL0V_CACHE_POLICY_MISS_LRU = 0x00000000,
247GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001,
248GL0V_CACHE_POLICY_HIT_LRU = 0x00000002,
249GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003,
250} GL0V_CACHE_POLICIES;
251
252/*
253 * GL1_CACHE_POLICIES enum
254 */
255
256typedef enum GL1_CACHE_POLICIES {
257GL1_CACHE_POLICY_MISS_LRU = 0x00000000,
258GL1_CACHE_POLICY_MISS_EVICT = 0x00000001,
259GL1_CACHE_POLICY_HIT_LRU = 0x00000002,
260GL1_CACHE_POLICY_HIT_EVICT = 0x00000003,
261} GL1_CACHE_POLICIES;
262
263/*
264 * GL1_CACHE_STORE_POLICIES enum
265 */
266
267typedef enum GL1_CACHE_STORE_POLICIES {
268GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000,
269} GL1_CACHE_STORE_POLICIES;
270
271/*
272 * TCC_CACHE_POLICIES enum
273 */
274
275typedef enum TCC_CACHE_POLICIES {
276TCC_CACHE_POLICY_LRU = 0x00000000,
277TCC_CACHE_POLICY_STREAM = 0x00000001,
278} TCC_CACHE_POLICIES;
279
280/*
281 * TCC_MTYPE enum
282 */
283
284typedef enum TCC_MTYPE {
285MTYPE_NC = 0x00000000,
286MTYPE_WC = 0x00000001,
287MTYPE_CC = 0x00000002,
288} TCC_MTYPE;
289
290/*
291 * GL2_CACHE_POLICIES enum
292 */
293
294typedef enum GL2_CACHE_POLICIES {
295GL2_CACHE_POLICY_LRU = 0x00000000,
296GL2_CACHE_POLICY_STREAM = 0x00000001,
297GL2_CACHE_POLICY_NOA = 0x00000002,
298GL2_CACHE_POLICY_BYPASS = 0x00000003,
299} GL2_CACHE_POLICIES;
300
301/*
302 * MTYPE enum
303 */
304
305typedef enum MTYPE {
306MTYPE_C_RW_US = 0x00000000,
307MTYPE_RESERVED_1 = 0x00000001,
308MTYPE_C_RO_S = 0x00000002,
309MTYPE_UC = 0x00000003,
310MTYPE_C_RW_S = 0x00000004,
311MTYPE_RESERVED_5 = 0x00000005,
312MTYPE_C_RO_US = 0x00000006,
313MTYPE_RESERVED_7 = 0x00000007,
314} MTYPE;
315
316/*
317 * RMI_CID enum
318 */
319
320typedef enum RMI_CID {
321RMI_CID_CC = 0x00000000,
322RMI_CID_FC = 0x00000001,
323RMI_CID_CM = 0x00000002,
324RMI_CID_DC = 0x00000003,
325RMI_CID_Z = 0x00000004,
326RMI_CID_S = 0x00000005,
327RMI_CID_TILE = 0x00000006,
328RMI_CID_ZPCPSD = 0x00000007,
329} RMI_CID;
330
331/*
332 * WritePolicy enum
333 */
334
335typedef enum WritePolicy {
336CACHE_LRU_WR = 0x00000000,
337CACHE_STREAM = 0x00000001,
338CACHE_BYPASS = 0x00000002,
339UNCACHED_WR = 0x00000003,
340} WritePolicy;
341
342/*
343 * ReadPolicy enum
344 */
345
346typedef enum ReadPolicy {
347CACHE_LRU_RD = 0x00000000,
348CACHE_NOA = 0x00000001,
349UNCACHED_RD = 0x00000002,
350RESERVED_RDPOLICY = 0x00000003,
351} ReadPolicy;
352
353/*
354 * PERFMON_COUNTER_MODE enum
355 */
356
357typedef enum PERFMON_COUNTER_MODE {
358PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
359PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
360PERFMON_COUNTER_MODE_MAX = 0x00000002,
361PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
362PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
363PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
364PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
365PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
366PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
367PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
368PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
369} PERFMON_COUNTER_MODE;
370
371/*
372 * PERFMON_SPM_MODE enum
373 */
374
375typedef enum PERFMON_SPM_MODE {
376PERFMON_SPM_MODE_OFF = 0x00000000,
377PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
378PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
379PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
380PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
381PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
382PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
383PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
384PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
385PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
386PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
387} PERFMON_SPM_MODE;
388
389/*
390 * SurfaceTiling enum
391 */
392
393typedef enum SurfaceTiling {
394ARRAY_LINEAR = 0x00000000,
395ARRAY_TILED = 0x00000001,
396} SurfaceTiling;
397
398/*
399 * SurfaceArray enum
400 */
401
402typedef enum SurfaceArray {
403ARRAY_1D = 0x00000000,
404ARRAY_2D = 0x00000001,
405ARRAY_3D = 0x00000002,
406ARRAY_3D_SLICE = 0x00000003,
407} SurfaceArray;
408
409/*
410 * ColorArray enum
411 */
412
413typedef enum ColorArray {
414ARRAY_2D_ALT_COLOR = 0x00000000,
415ARRAY_2D_COLOR = 0x00000001,
416ARRAY_3D_SLICE_COLOR = 0x00000003,
417} ColorArray;
418
419/*
420 * DepthArray enum
421 */
422
423typedef enum DepthArray {
424ARRAY_2D_ALT_DEPTH = 0x00000000,
425ARRAY_2D_DEPTH = 0x00000001,
426} DepthArray;
427
428/*
429 * ENUM_NUM_SIMD_PER_CU enum
430 */
431
432typedef enum ENUM_NUM_SIMD_PER_CU {
433NUM_SIMD_PER_CU = 0x00000002,
434} ENUM_NUM_SIMD_PER_CU;
435
436/*
437 * DSM_ENABLE_ERROR_INJECT enum
438 */
439
440typedef enum DSM_ENABLE_ERROR_INJECT {
441DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
442DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
443DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
444DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
445} DSM_ENABLE_ERROR_INJECT;
446
447/*
448 * DSM_SELECT_INJECT_DELAY enum
449 */
450
451typedef enum DSM_SELECT_INJECT_DELAY {
452DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
453DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
454} DSM_SELECT_INJECT_DELAY;
455
456/*
457 * DSM_DATA_SEL enum
458 */
459
460typedef enum DSM_DATA_SEL {
461DSM_DATA_SEL_DISABLE = 0x00000000,
462DSM_DATA_SEL_0 = 0x00000001,
463DSM_DATA_SEL_1 = 0x00000002,
464DSM_DATA_SEL_BOTH = 0x00000003,
465} DSM_DATA_SEL;
466
467/*
468 * DSM_SINGLE_WRITE enum
469 */
470
471typedef enum DSM_SINGLE_WRITE {
472DSM_SINGLE_WRITE_DIS = 0x00000000,
473DSM_SINGLE_WRITE_EN = 0x00000001,
474} DSM_SINGLE_WRITE;
475
476/*
477 * Hdp_SurfaceEndian enum
478 */
479
480typedef enum Hdp_SurfaceEndian {
481HDP_ENDIAN_NONE = 0x00000000,
482HDP_ENDIAN_8IN16 = 0x00000001,
483HDP_ENDIAN_8IN32 = 0x00000002,
484HDP_ENDIAN_8IN64 = 0x00000003,
485} Hdp_SurfaceEndian;
486
487/*******************************************************
488 * CNVC_CFG Enums
489 *******************************************************/
490
491/*
492 * CNVC_ENABLE enum
493 */
494
495typedef enum CNVC_ENABLE {
496CNVC_DIS = 0x00000000,
497CNVC_EN = 0x00000001,
498} CNVC_ENABLE;
499
500/*
501 * CNVC_BYPASS enum
502 */
503
504typedef enum CNVC_BYPASS {
505CNVC_BYPASS_DISABLE = 0x00000000,
506CNVC_BYPASS_EN = 0x00000001,
507} CNVC_BYPASS;
508
509/*
510 * CNVC_PENDING enum
511 */
512
513typedef enum CNVC_PENDING {
514CNVC_NOT_PENDING = 0x00000000,
515CNVC_YES_PENDING = 0x00000001,
516} CNVC_PENDING;
517
518/*
519 * DENORM_TRUNCATE enum
520 */
521
522typedef enum DENORM_TRUNCATE {
523CNVC_ROUND = 0x00000000,
524CNVC_TRUNCATE = 0x00000001,
525} DENORM_TRUNCATE;
526
527/*
528 * PIX_EXPAND_MODE enum
529 */
530
531typedef enum PIX_EXPAND_MODE {
532PIX_DYNAMIC_EXPANSION = 0x00000000,
533PIX_ZERO_EXPANSION = 0x00000001,
534} PIX_EXPAND_MODE;
535
536/*
537 * SURFACE_PIXEL_FORMAT enum
538 */
539
540typedef enum SURFACE_PIXEL_FORMAT {
541ARGB1555 = 0x00000001,
542RGBA5551 = 0x00000002,
543RGB565 = 0x00000003,
544BGR565 = 0x00000004,
545ARGB4444 = 0x00000005,
546RGBA4444 = 0x00000006,
547ARGB8888 = 0x00000008,
548RGBA8888 = 0x00000009,
549ARGB2101010 = 0x0000000a,
550RGBA1010102 = 0x0000000b,
551AYCrCb8888 = 0x0000000c,
552YCrCbA8888 = 0x0000000d,
553ACrYCb8888 = 0x0000000e,
554CrYCbA8888 = 0x0000000f,
555ARGB16161616_10MSB = 0x00000010,
556RGBA16161616_10MSB = 0x00000011,
557ARGB16161616_10LSB = 0x00000012,
558RGBA16161616_10LSB = 0x00000013,
559ARGB16161616_12MSB = 0x00000014,
560RGBA16161616_12MSB = 0x00000015,
561ARGB16161616_12LSB = 0x00000016,
562RGBA16161616_12LSB = 0x00000017,
563ARGB16161616_FLOAT = 0x00000018,
564RGBA16161616_FLOAT = 0x00000019,
565ARGB16161616_UNORM = 0x0000001a,
566RGBA16161616_UNORM = 0x0000001b,
567ARGB16161616_SNORM = 0x0000001c,
568RGBA16161616_SNORM = 0x0000001d,
569AYCrCb16161616_10MSB = 0x00000020,
570AYCrCb16161616_10LSB = 0x00000021,
571YCrCbA16161616_10MSB = 0x00000022,
572YCrCbA16161616_10LSB = 0x00000023,
573ACrYCb16161616_10MSB = 0x00000024,
574ACrYCb16161616_10LSB = 0x00000025,
575CrYCbA16161616_10MSB = 0x00000026,
576CrYCbA16161616_10LSB = 0x00000027,
577AYCrCb16161616_12MSB = 0x00000028,
578AYCrCb16161616_12LSB = 0x00000029,
579YCrCbA16161616_12MSB = 0x0000002a,
580YCrCbA16161616_12LSB = 0x0000002b,
581ACrYCb16161616_12MSB = 0x0000002c,
582ACrYCb16161616_12LSB = 0x0000002d,
583CrYCbA16161616_12MSB = 0x0000002e,
584CrYCbA16161616_12LSB = 0x0000002f,
585Y8_CrCb88_420_PLANAR = 0x00000040,
586Y8_CbCr88_420_PLANAR = 0x00000041,
587Y10_CrCb1010_420_PLANAR = 0x00000042,
588Y10_CbCr1010_420_PLANAR = 0x00000043,
589Y12_CrCb1212_420_PLANAR = 0x00000044,
590Y12_CbCr1212_420_PLANAR = 0x00000045,
591YCrYCb8888_422_PACKED = 0x00000048,
592YCbYCr8888_422_PACKED = 0x00000049,
593CrYCbY8888_422_PACKED = 0x0000004a,
594CbYCrY8888_422_PACKED = 0x0000004b,
595YCrYCb10101010_422_PACKED = 0x0000004c,
596YCbYCr10101010_422_PACKED = 0x0000004d,
597CrYCbY10101010_422_PACKED = 0x0000004e,
598CbYCrY10101010_422_PACKED = 0x0000004f,
599YCrYCb12121212_422_PACKED = 0x00000050,
600YCbYCr12121212_422_PACKED = 0x00000051,
601CrYCbY12121212_422_PACKED = 0x00000052,
602CbYCrY12121212_422_PACKED = 0x00000053,
603RGB111110_FIX = 0x00000070,
604BGR101111_FIX = 0x00000071,
605ACrYCb2101010 = 0x00000072,
606CrYCbA1010102 = 0x00000073,
607RGB111110_FLOAT = 0x00000076,
608BGR101111_FLOAT = 0x00000077,
609MONO_8 = 0x00000078,
610MONO_10MSB = 0x00000079,
611MONO_10LSB = 0x0000007a,
612MONO_12MSB = 0x0000007b,
613MONO_12LSB = 0x0000007c,
614MONO_16 = 0x0000007d,
615} SURFACE_PIXEL_FORMAT;
616
617/*
618 * XNORM enum
619 */
620
621typedef enum XNORM {
622XNORM_A = 0x00000000,
623XNORM_B = 0x00000001,
624} XNORM;
625
626/*
627 * COLOR_KEYER_MODE enum
628 */
629
630typedef enum COLOR_KEYER_MODE {
631FORCE_00 = 0x00000000,
632FORCE_FF = 0x00000001,
633RANGE_00 = 0x00000002,
634RANGE_FF = 0x00000003,
635} COLOR_KEYER_MODE;
636
637/*******************************************************
638 * CNVC_CUR Enums
639 *******************************************************/
640
641/*
642 * CUR_ENABLE enum
643 */
644
645typedef enum CUR_ENABLE {
646CUR_DIS = 0x00000000,
647CUR_EN = 0x00000001,
648} CUR_ENABLE;
649
650/*
651 * CUR_PENDING enum
652 */
653
654typedef enum CUR_PENDING {
655CUR_NOT_PENDING = 0x00000000,
656CUR_YES_PENDING = 0x00000001,
657} CUR_PENDING;
658
659/*
660 * CUR_EXPAND_MODE enum
661 */
662
663typedef enum CUR_EXPAND_MODE {
664CUR_DYNAMIC_EXPANSION = 0x00000000,
665CUR_ZERO_EXPANSION = 0x00000001,
666} CUR_EXPAND_MODE;
667
668/*
669 * CUR_ROM_EN enum
670 */
671
672typedef enum CUR_ROM_EN {
673CUR_FP_NO_ROM = 0x00000000,
674CUR_FP_USE_ROM = 0x00000001,
675} CUR_ROM_EN;
676
677/*
678 * CUR_MODE enum
679 */
680
681typedef enum CUR_MODE {
682MONO_2BIT = 0x00000000,
683COLOR_24BIT_1BIT_AND = 0x00000001,
684COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
685COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
686COLOR_64BIT_FP_PREMULT = 0x00000004,
687COLOR_64BIT_FP_UNPREMULT = 0x00000005,
688} CUR_MODE;
689
690/*
691 * CUR_INV_CLAMP enum
692 */
693
694typedef enum CUR_INV_CLAMP {
695CUR_CLAMP_DIS = 0x00000000,
696CUR_CLAMP_EN = 0x00000001,
697} CUR_INV_CLAMP;
698
699/*******************************************************
700 * DSCL Enums
701 *******************************************************/
702
703/*
704 * SCL_COEF_FILTER_TYPE_SEL enum
705 */
706
707typedef enum SCL_COEF_FILTER_TYPE_SEL {
708SCL_COEF_LUMA_VERT_FILTER = 0x00000000,
709SCL_COEF_LUMA_HORZ_FILTER = 0x00000001,
710SCL_COEF_CHROMA_VERT_FILTER = 0x00000002,
711SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003,
712SCL_COEF_ALPHA_VERT_FILTER = 0x00000004,
713SCL_COEF_ALPHA_HORZ_FILTER = 0x00000005,
714} SCL_COEF_FILTER_TYPE_SEL;
715
716/*
717 * DSCL_MODE_SEL enum
718 */
719
720typedef enum DSCL_MODE_SEL {
721DSCL_MODE_SCALING_444_BYPASS = 0x00000000,
722DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001,
723DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002,
724DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003,
725DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004,
726DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005,
727DSCL_MODE_DSCL_BYPASS = 0x00000006,
728} DSCL_MODE_SEL;
729
730/*
731 * SCL_AUTOCAL_MODE enum
732 */
733
734typedef enum SCL_AUTOCAL_MODE {
735AUTOCAL_MODE_OFF = 0x00000000,
736AUTOCAL_MODE_AUTOSCALE = 0x00000001,
737AUTOCAL_MODE_AUTOCENTER = 0x00000002,
738AUTOCAL_MODE_AUTOREPLICATE = 0x00000003,
739} SCL_AUTOCAL_MODE;
740
741/*
742 * SCL_COEF_RAM_SEL enum
743 */
744
745typedef enum SCL_COEF_RAM_SEL {
746SCL_COEF_RAM_SEL_0 = 0x00000000,
747SCL_COEF_RAM_SEL_1 = 0x00000001,
748} SCL_COEF_RAM_SEL;
749
750/*
751 * SCL_CHROMA_COEF enum
752 */
753
754typedef enum SCL_CHROMA_COEF {
755SCL_CHROMA_COEF_LUMA = 0x00000000,
756SCL_CHROMA_COEF_CHROMA = 0x00000001,
757} SCL_CHROMA_COEF;
758
759/*
760 * SCL_ALPHA_COEF enum
761 */
762
763typedef enum SCL_ALPHA_COEF {
764SCL_ALPHA_COEF_LUMA = 0x00000000,
765SCL_ALPHA_COEF_ALPHA = 0x00000001,
766} SCL_ALPHA_COEF;
767
768/*
769 * COEF_RAM_SELECT_RD enum
770 */
771
772typedef enum COEF_RAM_SELECT_RD {
773COEF_RAM_SELECT_BACK = 0x00000000,
774COEF_RAM_SELECT_CURRENT = 0x00000001,
775} COEF_RAM_SELECT_RD;
776
777/*
778 * SCL_2TAP_HARDCODE enum
779 */
780
781typedef enum SCL_2TAP_HARDCODE {
782SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000,
783SCL_COEF_2TAP_HARDCODE_ON = 0x00000001,
784} SCL_2TAP_HARDCODE;
785
786/*
787 * SCL_SHARP_EN enum
788 */
789
790typedef enum SCL_SHARP_EN {
791SCL_SHARP_DISABLE = 0x00000000,
792SCL_SHARP_ENABLE = 0x00000001,
793} SCL_SHARP_EN;
794
795/*
796 * SCL_BOUNDARY enum
797 */
798
799typedef enum SCL_BOUNDARY {
800SCL_BOUNDARY_EDGE = 0x00000000,
801SCL_BOUNDARY_BLACK = 0x00000001,
802} SCL_BOUNDARY;
803
804/*
805 * LB_INTERLEAVE_EN enum
806 */
807
808typedef enum LB_INTERLEAVE_EN {
809LB_INTERLEAVE_DISABLE = 0x00000000,
810LB_INTERLEAVE_ENABLE = 0x00000001,
811} LB_INTERLEAVE_EN;
812
813/*
814 * LB_ALPHA_EN enum
815 */
816
817typedef enum LB_ALPHA_EN {
818LB_ALPHA_DISABLE = 0x00000000,
819LB_ALPHA_ENABLE = 0x00000001,
820} LB_ALPHA_EN;
821
822/*
823 * OBUF_BYPASS_SEL enum
824 */
825
826typedef enum OBUF_BYPASS_SEL {
827OBUF_BYPASS_DIS = 0x00000000,
828OBUF_BYPASS_EN = 0x00000001,
829} OBUF_BYPASS_SEL;
830
831/*
832 * OBUF_USE_FULL_BUFFER_SEL enum
833 */
834
835typedef enum OBUF_USE_FULL_BUFFER_SEL {
836OBUF_RECOUT = 0x00000000,
837OBUF_FULL = 0x00000001,
838} OBUF_USE_FULL_BUFFER_SEL;
839
840/*
841 * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
842 */
843
844typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
845OBUF_FULL_RECOUT = 0x00000000,
846OBUF_HALF_RECOUT = 0x00000001,
847} OBUF_IS_HALF_RECOUT_WIDTH_SEL;
848
849/*******************************************************
850 * CM Enums
851 *******************************************************/
852
853/*
854 * CM_BYPASS enum
855 */
856
857typedef enum CM_BYPASS {
858NON_BYPASS = 0x00000000,
859BYPASS_EN = 0x00000001,
860} CM_BYPASS;
861
862/*
863 * CM_EN enum
864 */
865
866typedef enum CM_EN {
867CM_DISABLE = 0x00000000,
868CM_ENABLE = 0x00000001,
869} CM_EN;
870
871/*
872 * CM_PENDING enum
873 */
874
875typedef enum CM_PENDING {
876CM_NOT_PENDING = 0x00000000,
877CM_YES_PENDING = 0x00000001,
878} CM_PENDING;
879
880/*
881 * CM_DATA_SIGNED enum
882 */
883
884typedef enum CM_DATA_SIGNED {
885UNSIGNED = 0x00000000,
886SIGNED = 0x00000001,
887} CM_DATA_SIGNED;
888
889/*
890 * CM_WRITE_BASE_ONLY enum
891 */
892
893typedef enum CM_WRITE_BASE_ONLY {
894WRITE_BOTH = 0x00000000,
895WRITE_BASE_ONLY = 0x00000001,
896} CM_WRITE_BASE_ONLY;
897
898/*
899 * CM_LUT_4_CONFIG_ENUM enum
900 */
901
902typedef enum CM_LUT_4_CONFIG_ENUM {
903LUT_4CFG_NO_MEMORY = 0x00000000,
904LUT_4CFG_ROM_A = 0x00000001,
905LUT_4CFG_ROM_B = 0x00000002,
906LUT_4CFG_MEMORY_A = 0x00000003,
907LUT_4CFG_MEMORY_B = 0x00000004,
908} CM_LUT_4_CONFIG_ENUM;
909
910/*
911 * CM_LUT_2_CONFIG_ENUM enum
912 */
913
914typedef enum CM_LUT_2_CONFIG_ENUM {
915LUT_2CFG_NO_MEMORY = 0x00000000,
916LUT_2CFG_MEMORY_A = 0x00000001,
917LUT_2CFG_MEMORY_B = 0x00000002,
918} CM_LUT_2_CONFIG_ENUM;
919
920/*
921 * CM_LUT_4_MODE_ENUM enum
922 */
923
924typedef enum CM_LUT_4_MODE_ENUM {
925LUT_4_MODE_BYPASS = 0x00000000,
926LUT_4_MODE_ROMA_LUT = 0x00000001,
927LUT_4_MODE_ROMB_LUT = 0x00000002,
928LUT_4_MODE_RAMA_LUT = 0x00000003,
929LUT_4_MODE_RAMB_LUT = 0x00000004,
930} CM_LUT_4_MODE_ENUM;
931
932/*
933 * CM_LUT_2_MODE_ENUM enum
934 */
935
936typedef enum CM_LUT_2_MODE_ENUM {
937LUT_2_MODE_BYPASS = 0x00000000,
938LUT_2_MODE_RAMA_LUT = 0x00000001,
939LUT_2_MODE_RAMB_LUT = 0x00000002,
940} CM_LUT_2_MODE_ENUM;
941
942/*
943 * CM_LUT_RAM_SEL enum
944 */
945
946typedef enum CM_LUT_RAM_SEL {
947RAMA_ACCESS = 0x00000000,
948RAMB_ACCESS = 0x00000001,
949} CM_LUT_RAM_SEL;
950
951/*
952 * CM_LUT_NUM_SEG enum
953 */
954
955typedef enum CM_LUT_NUM_SEG {
956SEGMENTS_1 = 0x00000000,
957SEGMENTS_2 = 0x00000001,
958SEGMENTS_4 = 0x00000002,
959SEGMENTS_8 = 0x00000003,
960SEGMENTS_16 = 0x00000004,
961SEGMENTS_32 = 0x00000005,
962SEGMENTS_64 = 0x00000006,
963SEGMENTS_128 = 0x00000007,
964} CM_LUT_NUM_SEG;
965
966/*
967 * CM_ICSC_MODE_ENUM enum
968 */
969
970typedef enum CM_ICSC_MODE_ENUM {
971BYPASS_ICSC = 0x00000000,
972COEF_ICSC = 0x00000001,
973COEF_ICSC_B = 0x00000002,
974} CM_ICSC_MODE_ENUM;
975
976/*
977 * CM_GAMUT_REMAP_MODE_ENUM enum
978 */
979
980typedef enum CM_GAMUT_REMAP_MODE_ENUM {
981BYPASS_GAMUT = 0x00000000,
982GAMUT_COEF = 0x00000001,
983GAMUT_COEF_B = 0x00000002,
984} CM_GAMUT_REMAP_MODE_ENUM;
985
986/*
987 * CM_COEF_FORMAT_ENUM enum
988 */
989
990typedef enum CM_COEF_FORMAT_ENUM {
991FIX_S2_13 = 0x00000000,
992FIX_S3_12 = 0x00000001,
993} CM_COEF_FORMAT_ENUM;
994
995/*
996 * CMC_LUT_2_CONFIG_ENUM enum
997 */
998
999typedef enum CMC_LUT_2_CONFIG_ENUM {
1000CMC_LUT_2CFG_NO_MEMORY = 0x00000000,
1001CMC_LUT_2CFG_MEMORY_A = 0x00000001,
1002CMC_LUT_2CFG_MEMORY_B = 0x00000002,
1003} CMC_LUT_2_CONFIG_ENUM;
1004
1005/*
1006 * CMC_LUT_2_MODE_ENUM enum
1007 */
1008
1009typedef enum CMC_LUT_2_MODE_ENUM {
1010CMC_LUT_2_MODE_BYPASS = 0x00000000,
1011CMC_LUT_2_MODE_RAMA_LUT = 0x00000001,
1012CMC_LUT_2_MODE_RAMB_LUT = 0x00000002,
1013} CMC_LUT_2_MODE_ENUM;
1014
1015/*
1016 * CMC_LUT_RAM_SEL enum
1017 */
1018
1019typedef enum CMC_LUT_RAM_SEL {
1020CMC_RAMA_ACCESS = 0x00000000,
1021CMC_RAMB_ACCESS = 0x00000001,
1022} CMC_LUT_RAM_SEL;
1023
1024/*
1025 * CMC_3DLUT_RAM_SEL enum
1026 */
1027
1028typedef enum CMC_3DLUT_RAM_SEL {
1029CMC_RAM0_ACCESS = 0x00000000,
1030CMC_RAM1_ACCESS = 0x00000001,
1031CMC_RAM2_ACCESS = 0x00000002,
1032CMC_RAM3_ACCESS = 0x00000003,
1033} CMC_3DLUT_RAM_SEL;
1034
1035/*
1036 * CMC_LUT_NUM_SEG enum
1037 */
1038
1039typedef enum CMC_LUT_NUM_SEG {
1040CMC_SEGMENTS_1 = 0x00000000,
1041CMC_SEGMENTS_2 = 0x00000001,
1042CMC_SEGMENTS_4 = 0x00000002,
1043CMC_SEGMENTS_8 = 0x00000003,
1044CMC_SEGMENTS_16 = 0x00000004,
1045CMC_SEGMENTS_32 = 0x00000005,
1046CMC_SEGMENTS_64 = 0x00000006,
1047CMC_SEGMENTS_128 = 0x00000007,
1048} CMC_LUT_NUM_SEG;
1049
1050/*
1051 * CMC_3DLUT_30BIT_ENUM enum
1052 */
1053
1054typedef enum CMC_3DLUT_30BIT_ENUM {
1055CMC_3DLUT_36BIT = 0x00000000,
1056CMC_3DLUT_30BIT = 0x00000001,
1057} CMC_3DLUT_30BIT_ENUM;
1058
1059/*
1060 * CMC_3DLUT_SIZE_ENUM enum
1061 */
1062
1063typedef enum CMC_3DLUT_SIZE_ENUM {
1064CMC_3DLUT_17CUBE = 0x00000000,
1065CMC_3DLUT_9CUBE = 0x00000001,
1066} CMC_3DLUT_SIZE_ENUM;
1067
1068/*******************************************************
1069 * DPP_TOP Enums
1070 *******************************************************/
1071
1072/*
1073 * TEST_CLK_SEL enum
1074 */
1075
1076typedef enum TEST_CLK_SEL {
1077TEST_CLK_SEL_0 = 0x00000000,
1078TEST_CLK_SEL_1 = 0x00000001,
1079TEST_CLK_SEL_2 = 0x00000002,
1080TEST_CLK_SEL_3 = 0x00000003,
1081TEST_CLK_SEL_4 = 0x00000004,
1082TEST_CLK_SEL_5 = 0x00000005,
1083TEST_CLK_SEL_6 = 0x00000006,
1084TEST_CLK_SEL_7 = 0x00000007,
1085TEST_CLK_SEL_8 = 0x00000008,
1086} TEST_CLK_SEL;
1087
1088/*
1089 * CRC_SRC_SEL enum
1090 */
1091
1092typedef enum CRC_SRC_SEL {
1093CRC_SRC_0 = 0x00000000,
1094CRC_SRC_1 = 0x00000001,
1095CRC_SRC_2 = 0x00000002,
1096CRC_SRC_3 = 0x00000003,
1097} CRC_SRC_SEL;
1098
1099/*
1100 * CRC_IN_PIX_SEL enum
1101 */
1102
1103typedef enum CRC_IN_PIX_SEL {
1104CRC_IN_PIX_0 = 0x00000000,
1105CRC_IN_PIX_1 = 0x00000001,
1106CRC_IN_PIX_2 = 0x00000002,
1107CRC_IN_PIX_3 = 0x00000003,
1108CRC_IN_PIX_4 = 0x00000004,
1109CRC_IN_PIX_5 = 0x00000005,
1110CRC_IN_PIX_6 = 0x00000006,
1111CRC_IN_PIX_7 = 0x00000007,
1112} CRC_IN_PIX_SEL;
1113
1114/*
1115 * CRC_CUR_BITS_SEL enum
1116 */
1117
1118typedef enum CRC_CUR_BITS_SEL {
1119CRC_CUR_BITS_0 = 0x00000000,
1120CRC_CUR_BITS_1 = 0x00000001,
1121} CRC_CUR_BITS_SEL;
1122
1123/*
1124 * CRC_IN_CUR_SEL enum
1125 */
1126
1127typedef enum CRC_IN_CUR_SEL {
1128CRC_IN_CUR_0 = 0x00000000,
1129CRC_IN_CUR_1 = 0x00000001,
1130} CRC_IN_CUR_SEL;
1131
1132/*
1133 * CRC_CUR_SEL enum
1134 */
1135
1136typedef enum CRC_CUR_SEL {
1137CRC_CUR_0 = 0x00000000,
1138CRC_CUR_1 = 0x00000001,
1139} CRC_CUR_SEL;
1140
1141/*
1142 * CRC_STEREO_SEL enum
1143 */
1144
1145typedef enum CRC_STEREO_SEL {
1146CRC_STEREO_0 = 0x00000000,
1147CRC_STEREO_1 = 0x00000001,
1148CRC_STEREO_2 = 0x00000002,
1149CRC_STEREO_3 = 0x00000003,
1150} CRC_STEREO_SEL;
1151
1152/*
1153 * CRC_INTERLACE_SEL enum
1154 */
1155
1156typedef enum CRC_INTERLACE_SEL {
1157CRC_INTERLACE_0 = 0x00000000,
1158CRC_INTERLACE_1 = 0x00000001,
1159CRC_INTERLACE_2 = 0x00000002,
1160CRC_INTERLACE_3 = 0x00000003,
1161} CRC_INTERLACE_SEL;
1162
1163/*******************************************************
1164 * DC_PERFMON Enums
1165 *******************************************************/
1166
1167/*
1168 * PERFCOUNTER_CVALUE_SEL enum
1169 */
1170
1171typedef enum PERFCOUNTER_CVALUE_SEL {
1172PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
1173PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
1174PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
1175PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
1176PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
1177PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
1178PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
1179PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
1180} PERFCOUNTER_CVALUE_SEL;
1181
1182/*
1183 * PERFCOUNTER_INC_MODE enum
1184 */
1185
1186typedef enum PERFCOUNTER_INC_MODE {
1187PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
1188PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
1189PERFCOUNTER_INC_MODE_LSB = 0x00000002,
1190PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
1191PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
1192} PERFCOUNTER_INC_MODE;
1193
1194/*
1195 * PERFCOUNTER_HW_CNTL_SEL enum
1196 */
1197
1198typedef enum PERFCOUNTER_HW_CNTL_SEL {
1199PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
1200PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
1201} PERFCOUNTER_HW_CNTL_SEL;
1202
1203/*
1204 * PERFCOUNTER_RUNEN_MODE enum
1205 */
1206
1207typedef enum PERFCOUNTER_RUNEN_MODE {
1208PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
1209PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
1210} PERFCOUNTER_RUNEN_MODE;
1211
1212/*
1213 * PERFCOUNTER_CNTOFF_START_DIS enum
1214 */
1215
1216typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1217PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
1218PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
1219} PERFCOUNTER_CNTOFF_START_DIS;
1220
1221/*
1222 * PERFCOUNTER_RESTART_EN enum
1223 */
1224
1225typedef enum PERFCOUNTER_RESTART_EN {
1226PERFCOUNTER_RESTART_DISABLE = 0x00000000,
1227PERFCOUNTER_RESTART_ENABLE = 0x00000001,
1228} PERFCOUNTER_RESTART_EN;
1229
1230/*
1231 * PERFCOUNTER_INT_EN enum
1232 */
1233
1234typedef enum PERFCOUNTER_INT_EN {
1235PERFCOUNTER_INT_DISABLE = 0x00000000,
1236PERFCOUNTER_INT_ENABLE = 0x00000001,
1237} PERFCOUNTER_INT_EN;
1238
1239/*
1240 * PERFCOUNTER_OFF_MASK enum
1241 */
1242
1243typedef enum PERFCOUNTER_OFF_MASK {
1244PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
1245PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
1246} PERFCOUNTER_OFF_MASK;
1247
1248/*
1249 * PERFCOUNTER_ACTIVE enum
1250 */
1251
1252typedef enum PERFCOUNTER_ACTIVE {
1253PERFCOUNTER_IS_IDLE = 0x00000000,
1254PERFCOUNTER_IS_ACTIVE = 0x00000001,
1255} PERFCOUNTER_ACTIVE;
1256
1257/*
1258 * PERFCOUNTER_INT_TYPE enum
1259 */
1260
1261typedef enum PERFCOUNTER_INT_TYPE {
1262PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
1263PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
1264} PERFCOUNTER_INT_TYPE;
1265
1266/*
1267 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1268 */
1269
1270typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1271PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
1272PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
1273PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
1274} PERFCOUNTER_COUNTED_VALUE_TYPE;
1275
1276/*
1277 * PERFCOUNTER_HW_STOP1_SEL enum
1278 */
1279
1280typedef enum PERFCOUNTER_HW_STOP1_SEL {
1281PERFCOUNTER_HW_STOP1_0 = 0x00000000,
1282PERFCOUNTER_HW_STOP1_1 = 0x00000001,
1283} PERFCOUNTER_HW_STOP1_SEL;
1284
1285/*
1286 * PERFCOUNTER_HW_STOP2_SEL enum
1287 */
1288
1289typedef enum PERFCOUNTER_HW_STOP2_SEL {
1290PERFCOUNTER_HW_STOP2_0 = 0x00000000,
1291PERFCOUNTER_HW_STOP2_1 = 0x00000001,
1292} PERFCOUNTER_HW_STOP2_SEL;
1293
1294/*
1295 * PERFCOUNTER_CNTL_SEL enum
1296 */
1297
1298typedef enum PERFCOUNTER_CNTL_SEL {
1299PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
1300PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
1301PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
1302PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
1303PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
1304PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
1305PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
1306PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
1307} PERFCOUNTER_CNTL_SEL;
1308
1309/*
1310 * PERFCOUNTER_CNT0_STATE enum
1311 */
1312
1313typedef enum PERFCOUNTER_CNT0_STATE {
1314PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
1315PERFCOUNTER_CNT0_STATE_START = 0x00000001,
1316PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
1317PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
1318} PERFCOUNTER_CNT0_STATE;
1319
1320/*
1321 * PERFCOUNTER_STATE_SEL0 enum
1322 */
1323
1324typedef enum PERFCOUNTER_STATE_SEL0 {
1325PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
1326PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
1327} PERFCOUNTER_STATE_SEL0;
1328
1329/*
1330 * PERFCOUNTER_CNT1_STATE enum
1331 */
1332
1333typedef enum PERFCOUNTER_CNT1_STATE {
1334PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
1335PERFCOUNTER_CNT1_STATE_START = 0x00000001,
1336PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
1337PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
1338} PERFCOUNTER_CNT1_STATE;
1339
1340/*
1341 * PERFCOUNTER_STATE_SEL1 enum
1342 */
1343
1344typedef enum PERFCOUNTER_STATE_SEL1 {
1345PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
1346PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
1347} PERFCOUNTER_STATE_SEL1;
1348
1349/*
1350 * PERFCOUNTER_CNT2_STATE enum
1351 */
1352
1353typedef enum PERFCOUNTER_CNT2_STATE {
1354PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
1355PERFCOUNTER_CNT2_STATE_START = 0x00000001,
1356PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
1357PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
1358} PERFCOUNTER_CNT2_STATE;
1359
1360/*
1361 * PERFCOUNTER_STATE_SEL2 enum
1362 */
1363
1364typedef enum PERFCOUNTER_STATE_SEL2 {
1365PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
1366PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
1367} PERFCOUNTER_STATE_SEL2;
1368
1369/*
1370 * PERFCOUNTER_CNT3_STATE enum
1371 */
1372
1373typedef enum PERFCOUNTER_CNT3_STATE {
1374PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
1375PERFCOUNTER_CNT3_STATE_START = 0x00000001,
1376PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
1377PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
1378} PERFCOUNTER_CNT3_STATE;
1379
1380/*
1381 * PERFCOUNTER_STATE_SEL3 enum
1382 */
1383
1384typedef enum PERFCOUNTER_STATE_SEL3 {
1385PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
1386PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
1387} PERFCOUNTER_STATE_SEL3;
1388
1389/*
1390 * PERFCOUNTER_CNT4_STATE enum
1391 */
1392
1393typedef enum PERFCOUNTER_CNT4_STATE {
1394PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
1395PERFCOUNTER_CNT4_STATE_START = 0x00000001,
1396PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
1397PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
1398} PERFCOUNTER_CNT4_STATE;
1399
1400/*
1401 * PERFCOUNTER_STATE_SEL4 enum
1402 */
1403
1404typedef enum PERFCOUNTER_STATE_SEL4 {
1405PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
1406PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
1407} PERFCOUNTER_STATE_SEL4;
1408
1409/*
1410 * PERFCOUNTER_CNT5_STATE enum
1411 */
1412
1413typedef enum PERFCOUNTER_CNT5_STATE {
1414PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
1415PERFCOUNTER_CNT5_STATE_START = 0x00000001,
1416PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
1417PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
1418} PERFCOUNTER_CNT5_STATE;
1419
1420/*
1421 * PERFCOUNTER_STATE_SEL5 enum
1422 */
1423
1424typedef enum PERFCOUNTER_STATE_SEL5 {
1425PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
1426PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
1427} PERFCOUNTER_STATE_SEL5;
1428
1429/*
1430 * PERFCOUNTER_CNT6_STATE enum
1431 */
1432
1433typedef enum PERFCOUNTER_CNT6_STATE {
1434PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
1435PERFCOUNTER_CNT6_STATE_START = 0x00000001,
1436PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
1437PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
1438} PERFCOUNTER_CNT6_STATE;
1439
1440/*
1441 * PERFCOUNTER_STATE_SEL6 enum
1442 */
1443
1444typedef enum PERFCOUNTER_STATE_SEL6 {
1445PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
1446PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
1447} PERFCOUNTER_STATE_SEL6;
1448
1449/*
1450 * PERFCOUNTER_CNT7_STATE enum
1451 */
1452
1453typedef enum PERFCOUNTER_CNT7_STATE {
1454PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
1455PERFCOUNTER_CNT7_STATE_START = 0x00000001,
1456PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
1457PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
1458} PERFCOUNTER_CNT7_STATE;
1459
1460/*
1461 * PERFCOUNTER_STATE_SEL7 enum
1462 */
1463
1464typedef enum PERFCOUNTER_STATE_SEL7 {
1465PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
1466PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
1467} PERFCOUNTER_STATE_SEL7;
1468
1469/*
1470 * PERFMON_STATE enum
1471 */
1472
1473typedef enum PERFMON_STATE {
1474PERFMON_STATE_RESET = 0x00000000,
1475PERFMON_STATE_START = 0x00000001,
1476PERFMON_STATE_FREEZE = 0x00000002,
1477PERFMON_STATE_HW = 0x00000003,
1478} PERFMON_STATE;
1479
1480/*
1481 * PERFMON_CNTOFF_AND_OR enum
1482 */
1483
1484typedef enum PERFMON_CNTOFF_AND_OR {
1485PERFMON_CNTOFF_OR = 0x00000000,
1486PERFMON_CNTOFF_AND = 0x00000001,
1487} PERFMON_CNTOFF_AND_OR;
1488
1489/*
1490 * PERFMON_CNTOFF_INT_EN enum
1491 */
1492
1493typedef enum PERFMON_CNTOFF_INT_EN {
1494PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
1495PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
1496} PERFMON_CNTOFF_INT_EN;
1497
1498/*
1499 * PERFMON_CNTOFF_INT_TYPE enum
1500 */
1501
1502typedef enum PERFMON_CNTOFF_INT_TYPE {
1503PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
1504PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
1505} PERFMON_CNTOFF_INT_TYPE;
1506
1507/*******************************************************
1508 * HUBP Enums
1509 *******************************************************/
1510
1511/*
1512 * ROTATION_ANGLE enum
1513 */
1514
1515typedef enum ROTATION_ANGLE {
1516ROTATE_0_DEGREES = 0x00000000,
1517ROTATE_90_DEGREES = 0x00000001,
1518ROTATE_180_DEGREES = 0x00000002,
1519ROTATE_270_DEGREES = 0x00000003,
1520} ROTATION_ANGLE;
1521
1522/*
1523 * H_MIRROR_EN enum
1524 */
1525
1526typedef enum H_MIRROR_EN {
1527HW_MIRRORING_DISABLE = 0x00000000,
1528HW_MIRRORING_ENABLE = 0x00000001,
1529} H_MIRROR_EN;
1530
1531/*
1532 * NUM_PIPES enum
1533 */
1534
1535typedef enum NUM_PIPES {
1536ONE_PIPE = 0x00000000,
1537TWO_PIPES = 0x00000001,
1538FOUR_PIPES = 0x00000002,
1539EIGHT_PIPES = 0x00000003,
1540SIXTEEN_PIPES = 0x00000004,
1541THIRTY_TWO_PIPES = 0x00000005,
1542SIXTY_FOUR_PIPES = 0x00000006,
1543} NUM_PIPES;
1544
1545/*
1546 * NUM_BANKS enum
1547 */
1548
1549typedef enum NUM_BANKS {
1550ONE_BANK = 0x00000000,
1551TWO_BANKS = 0x00000001,
1552FOUR_BANKS = 0x00000002,
1553EIGHT_BANKS = 0x00000003,
1554SIXTEEN_BANKS = 0x00000004,
1555} NUM_BANKS;
1556
1557/*
1558 * SW_MODE enum
1559 */
1560
1561typedef enum SW_MODE {
1562SWIZZLE_LINEAR = 0x00000000,
1563SWIZZLE_4KB_S = 0x00000005,
1564SWIZZLE_4KB_D = 0x00000006,
1565SWIZZLE_64KB_S = 0x00000009,
1566SWIZZLE_64KB_D = 0x0000000a,
1567SWIZZLE_VAR_S = 0x0000000d,
1568SWIZZLE_VAR_D = 0x0000000e,
1569SWIZZLE_64KB_S_T = 0x00000011,
1570SWIZZLE_64KB_D_T = 0x00000012,
1571SWIZZLE_4KB_S_X = 0x00000015,
1572SWIZZLE_4KB_D_X = 0x00000016,
1573SWIZZLE_64KB_S_X = 0x00000019,
1574SWIZZLE_64KB_D_X = 0x0000001a,
1575SWIZZLE_64KB_R_X = 0x0000001b,
1576SWIZZLE_VAR_S_X = 0x0000001d,
1577SWIZZLE_VAR_D_X = 0x0000001e,
1578} SW_MODE;
1579
1580/*
1581 * PIPE_INTERLEAVE enum
1582 */
1583
1584typedef enum PIPE_INTERLEAVE {
1585PIPE_INTERLEAVE_256B = 0x00000000,
1586PIPE_INTERLEAVE_512B = 0x00000001,
1587PIPE_INTERLEAVE_1KB = 0x00000002,
1588} PIPE_INTERLEAVE;
1589
1590/*
1591 * LEGACY_PIPE_INTERLEAVE enum
1592 */
1593
1594typedef enum LEGACY_PIPE_INTERLEAVE {
1595LEGACY_PIPE_INTERLEAVE_256B = 0x00000000,
1596LEGACY_PIPE_INTERLEAVE_512B = 0x00000001,
1597} LEGACY_PIPE_INTERLEAVE;
1598
1599/*
1600 * NUM_SE enum
1601 */
1602
1603typedef enum NUM_SE {
1604ONE_SHADER_ENGIN = 0x00000000,
1605TWO_SHADER_ENGINS = 0x00000001,
1606FOUR_SHADER_ENGINS = 0x00000002,
1607EIGHT_SHADER_ENGINS = 0x00000003,
1608} NUM_SE;
1609
1610/*
1611 * NUM_RB_PER_SE enum
1612 */
1613
1614typedef enum NUM_RB_PER_SE {
1615ONE_RB_PER_SE = 0x00000000,
1616TWO_RB_PER_SE = 0x00000001,
1617FOUR_RB_PER_SE = 0x00000002,
1618} NUM_RB_PER_SE;
1619
1620/*
1621 * MAX_COMPRESSED_FRAGS enum
1622 */
1623
1624typedef enum MAX_COMPRESSED_FRAGS {
1625ONE_FRAGMENT = 0x00000000,
1626TWO_FRAGMENTS = 0x00000001,
1627FOUR_FRAGMENTS = 0x00000002,
1628EIGHT_FRAGMENTS = 0x00000003,
1629} MAX_COMPRESSED_FRAGS;
1630
1631/*
1632 * DIM_TYPE enum
1633 */
1634
1635typedef enum DIM_TYPE {
1636DIM_TYPE_1D = 0x00000000,
1637DIM_TYPE_2D = 0x00000001,
1638DIM_TYPE_3D = 0x00000002,
1639DIM_TYPE_RESERVED = 0x00000003,
1640} DIM_TYPE;
1641
1642/*
1643 * META_LINEAR enum
1644 */
1645
1646typedef enum META_LINEAR {
1647META_SURF_TILED = 0x00000000,
1648META_SURF_LINEAR = 0x00000001,
1649} META_LINEAR;
1650
1651/*
1652 * RB_ALIGNED enum
1653 */
1654
1655typedef enum RB_ALIGNED {
1656RB_UNALIGNED_META_SURF = 0x00000000,
1657RB_ALIGNED_META_SURF = 0x00000001,
1658} RB_ALIGNED;
1659
1660/*
1661 * PIPE_ALIGNED enum
1662 */
1663
1664typedef enum PIPE_ALIGNED {
1665PIPE_UNALIGNED_SURF = 0x00000000,
1666PIPE_ALIGNED_SURF = 0x00000001,
1667} PIPE_ALIGNED;
1668
1669/*
1670 * ARRAY_MODE enum
1671 */
1672
1673typedef enum ARRAY_MODE {
1674AM_LINEAR_GENERAL = 0x00000000,
1675AM_LINEAR_ALIGNED = 0x00000001,
1676AM_1D_TILED_THIN1 = 0x00000002,
1677AM_1D_TILED_THICK = 0x00000003,
1678AM_2D_TILED_THIN1 = 0x00000004,
1679AM_PRT_TILED_THIN1 = 0x00000005,
1680AM_PRT_2D_TILED_THIN1 = 0x00000006,
1681AM_2D_TILED_THICK = 0x00000007,
1682AM_2D_TILED_XTHICK = 0x00000008,
1683AM_PRT_TILED_THICK = 0x00000009,
1684AM_PRT_2D_TILED_THICK = 0x0000000a,
1685AM_PRT_3D_TILED_THIN1 = 0x0000000b,
1686AM_3D_TILED_THIN1 = 0x0000000c,
1687AM_3D_TILED_THICK = 0x0000000d,
1688AM_3D_TILED_XTHICK = 0x0000000e,
1689AM_PRT_3D_TILED_THICK = 0x0000000f,
1690} ARRAY_MODE;
1691
1692/*
1693 * PIPE_CONFIG enum
1694 */
1695
1696typedef enum PIPE_CONFIG {
1697P2 = 0x00000000,
1698P4_8x16 = 0x00000004,
1699P4_16x16 = 0x00000005,
1700P4_16x32 = 0x00000006,
1701P4_32x32 = 0x00000007,
1702P8_16x16_8x16 = 0x00000008,
1703P8_16x32_8x16 = 0x00000009,
1704P8_32x32_8x16 = 0x0000000a,
1705P8_16x32_16x16 = 0x0000000b,
1706P8_32x32_16x16 = 0x0000000c,
1707P8_32x32_16x32 = 0x0000000d,
1708P8_32x64_32x32 = 0x0000000e,
1709P16_32x32_8x16 = 0x00000010,
1710P16_32x32_16x16 = 0x00000011,
1711P16_ADDR_SURF = 0x00000012,
1712} PIPE_CONFIG;
1713
1714/*
1715 * MICRO_TILE_MODE_NEW enum
1716 */
1717
1718typedef enum MICRO_TILE_MODE_NEW {
1719DISPLAY_MICRO_TILING = 0x00000000,
1720THIN_MICRO_TILING = 0x00000001,
1721DEPTH_MICRO_TILING = 0x00000002,
1722ROTATED_MICRO_TILING = 0x00000003,
1723THICK_MICRO_TILING = 0x00000004,
1724} MICRO_TILE_MODE_NEW;
1725
1726/*
1727 * TILE_SPLIT enum
1728 */
1729
1730typedef enum TILE_SPLIT {
1731SURF_TILE_SPLIT_64B = 0x00000000,
1732SURF_TILE_SPLIT_128B = 0x00000001,
1733SURF_TILE_SPLIT_256B = 0x00000002,
1734SURF_TILE_SPLIT_512B = 0x00000003,
1735SURF_TILE_SPLIT_1KB = 0x00000004,
1736SURF_TILE_SPLIT_2KB = 0x00000005,
1737SURF_TILE_SPLIT_4KB = 0x00000006,
1738} TILE_SPLIT;
1739
1740/*
1741 * BANK_WIDTH enum
1742 */
1743
1744typedef enum BANK_WIDTH {
1745SURF_BANK_WIDTH_1 = 0x00000000,
1746SURF_BANK_WIDTH_2 = 0x00000001,
1747SURF_BANK_WIDTH_4 = 0x00000002,
1748SURF_BANK_WIDTH_8 = 0x00000003,
1749} BANK_WIDTH;
1750
1751/*
1752 * BANK_HEIGHT enum
1753 */
1754
1755typedef enum BANK_HEIGHT {
1756SURF_BANK_HEIGHT_1 = 0x00000000,
1757SURF_BANK_HEIGHT_2 = 0x00000001,
1758SURF_BANK_HEIGHT_4 = 0x00000002,
1759SURF_BANK_HEIGHT_8 = 0x00000003,
1760} BANK_HEIGHT;
1761
1762/*
1763 * MACRO_TILE_ASPECT enum
1764 */
1765
1766typedef enum MACRO_TILE_ASPECT {
1767SURF_MACRO_ASPECT_1 = 0x00000000,
1768SURF_MACRO_ASPECT_2 = 0x00000001,
1769SURF_MACRO_ASPECT_4 = 0x00000002,
1770SURF_MACRO_ASPECT_8 = 0x00000003,
1771} MACRO_TILE_ASPECT;
1772
1773/*
1774 * LEGACY_NUM_BANKS enum
1775 */
1776
1777typedef enum LEGACY_NUM_BANKS {
1778SURF_2_BANK = 0x00000000,
1779SURF_4_BANK = 0x00000001,
1780SURF_8_BANK = 0x00000002,
1781SURF_16_BANK = 0x00000003,
1782} LEGACY_NUM_BANKS;
1783
1784/*
1785 * SWATH_HEIGHT enum
1786 */
1787
1788typedef enum SWATH_HEIGHT {
1789SWATH_HEIGHT_1L = 0x00000000,
1790SWATH_HEIGHT_2L = 0x00000001,
1791SWATH_HEIGHT_4L = 0x00000002,
1792SWATH_HEIGHT_8L = 0x00000003,
1793SWATH_HEIGHT_16L = 0x00000004,
1794} SWATH_HEIGHT;
1795
1796/*
1797 * PTE_ROW_HEIGHT_LINEAR enum
1798 */
1799
1800typedef enum PTE_ROW_HEIGHT_LINEAR {
1801PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000,
1802PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001,
1803PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002,
1804PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003,
1805PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004,
1806PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005,
1807PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006,
1808PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007,
1809} PTE_ROW_HEIGHT_LINEAR;
1810
1811/*
1812 * CHUNK_SIZE enum
1813 */
1814
1815typedef enum CHUNK_SIZE {
1816CHUNK_SIZE_1KB = 0x00000000,
1817CHUNK_SIZE_2KB = 0x00000001,
1818CHUNK_SIZE_4KB = 0x00000002,
1819CHUNK_SIZE_8KB = 0x00000003,
1820CHUNK_SIZE_16KB = 0x00000004,
1821CHUNK_SIZE_32KB = 0x00000005,
1822CHUNK_SIZE_64KB = 0x00000006,
1823} CHUNK_SIZE;
1824
1825/*
1826 * MIN_CHUNK_SIZE enum
1827 */
1828
1829typedef enum MIN_CHUNK_SIZE {
1830NO_MIN_CHUNK_SIZE = 0x00000000,
1831MIN_CHUNK_SIZE_256B = 0x00000001,
1832MIN_CHUNK_SIZE_512B = 0x00000002,
1833MIN_CHUNK_SIZE_1024B = 0x00000003,
1834} MIN_CHUNK_SIZE;
1835
1836/*
1837 * META_CHUNK_SIZE enum
1838 */
1839
1840typedef enum META_CHUNK_SIZE {
1841META_CHUNK_SIZE_1KB = 0x00000000,
1842META_CHUNK_SIZE_2KB = 0x00000001,
1843META_CHUNK_SIZE_4KB = 0x00000002,
1844META_CHUNK_SIZE_8KB = 0x00000003,
1845} META_CHUNK_SIZE;
1846
1847/*
1848 * MIN_META_CHUNK_SIZE enum
1849 */
1850
1851typedef enum MIN_META_CHUNK_SIZE {
1852NO_MIN_META_CHUNK_SIZE = 0x00000000,
1853MIN_META_CHUNK_SIZE_64B = 0x00000001,
1854MIN_META_CHUNK_SIZE_128B = 0x00000002,
1855MIN_META_CHUNK_SIZE_256B = 0x00000003,
1856} MIN_META_CHUNK_SIZE;
1857
1858/*
1859 * DPTE_GROUP_SIZE enum
1860 */
1861
1862typedef enum DPTE_GROUP_SIZE {
1863DPTE_GROUP_SIZE_64B = 0x00000000,
1864DPTE_GROUP_SIZE_128B = 0x00000001,
1865DPTE_GROUP_SIZE_256B = 0x00000002,
1866DPTE_GROUP_SIZE_512B = 0x00000003,
1867DPTE_GROUP_SIZE_1024B = 0x00000004,
1868DPTE_GROUP_SIZE_2048B = 0x00000005,
1869DPTE_GROUP_SIZE_4096B = 0x00000006,
1870DPTE_GROUP_SIZE_8192B = 0x00000007,
1871} DPTE_GROUP_SIZE;
1872
1873/*
1874 * MPTE_GROUP_SIZE enum
1875 */
1876
1877typedef enum MPTE_GROUP_SIZE {
1878MPTE_GROUP_SIZE_64B = 0x00000000,
1879MPTE_GROUP_SIZE_128B = 0x00000001,
1880MPTE_GROUP_SIZE_256B = 0x00000002,
1881MPTE_GROUP_SIZE_512B = 0x00000003,
1882MPTE_GROUP_SIZE_1024B = 0x00000004,
1883MPTE_GROUP_SIZE_2048B = 0x00000005,
1884MPTE_GROUP_SIZE_4096B = 0x00000006,
1885MPTE_GROUP_SIZE_8192B = 0x00000007,
1886} MPTE_GROUP_SIZE;
1887
1888/*
1889 * HUBP_BLANK_EN enum
1890 */
1891
1892typedef enum HUBP_BLANK_EN {
1893HUBP_BLANK_SW_DEASSERT = 0x00000000,
1894HUBP_BLANK_SW_ASSERT = 0x00000001,
1895} HUBP_BLANK_EN;
1896
1897/*
1898 * HUBP_DISABLE enum
1899 */
1900
1901typedef enum HUBP_DISABLE {
1902HUBP_ENABLED = 0x00000000,
1903HUBP_DISABLED = 0x00000001,
1904} HUBP_DISABLE;
1905
1906/*
1907 * HUBP_TTU_DISABLE enum
1908 */
1909
1910typedef enum HUBP_TTU_DISABLE {
1911HUBP_TTU_ENABLED = 0x00000000,
1912HUBP_TTU_DISABLED = 0x00000001,
1913} HUBP_TTU_DISABLE;
1914
1915/*
1916 * HUBP_NO_OUTSTANDING_REQ enum
1917 */
1918
1919typedef enum HUBP_NO_OUTSTANDING_REQ {
1920OUTSTANDING_REQ = 0x00000000,
1921NO_OUTSTANDING_REQ = 0x00000001,
1922} HUBP_NO_OUTSTANDING_REQ;
1923
1924/*
1925 * HUBP_IN_BLANK enum
1926 */
1927
1928typedef enum HUBP_IN_BLANK {
1929HUBP_IN_ACTIVE = 0x00000000,
1930HUBP_IN_VBLANK = 0x00000001,
1931} HUBP_IN_BLANK;
1932
1933/*
1934 * HUBP_VTG_SEL enum
1935 */
1936
1937typedef enum HUBP_VTG_SEL {
1938VTG_SEL_0 = 0x00000000,
1939VTG_SEL_1 = 0x00000001,
1940VTG_SEL_2 = 0x00000002,
1941VTG_SEL_3 = 0x00000003,
1942VTG_SEL_4 = 0x00000004,
1943VTG_SEL_5 = 0x00000005,
1944} HUBP_VTG_SEL;
1945
1946/*
1947 * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1948 */
1949
1950typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1951VREADY_BEFORE_VSYNC = 0x00000000,
1952VREADY_AT_OR_AFTER_VSYNC = 0x00000001,
1953} HUBP_VREADY_AT_OR_AFTER_VSYNC;
1954
1955/*
1956 * VMPG_SIZE enum
1957 */
1958
1959typedef enum VMPG_SIZE {
1960VMPG_SIZE_4KB = 0x00000000,
1961VMPG_SIZE_64KB = 0x00000001,
1962} VMPG_SIZE;
1963
1964/*
1965 * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1966 */
1967
1968typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1969HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000,
1970HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001,
1971HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002,
1972HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003,
1973} HUBP_MEASURE_WIN_MODE_DCFCLK;
1974
1975/*******************************************************
1976 * HUBPREQ Enums
1977 *******************************************************/
1978
1979/*
1980 * SURFACE_TMZ enum
1981 */
1982
1983typedef enum SURFACE_TMZ {
1984SURFACE_IS_NOT_TMZ = 0x00000000,
1985SURFACE_IS_TMZ = 0x00000001,
1986} SURFACE_TMZ;
1987
1988/*
1989 * SURFACE_DCC enum
1990 */
1991
1992typedef enum SURFACE_DCC {
1993SURFACE_IS_NOT_DCC = 0x00000000,
1994SURFACE_IS_DCC = 0x00000001,
1995} SURFACE_DCC;
1996
1997/*
1998 * SURFACE_DCC_IND_64B enum
1999 */
2000
2001typedef enum SURFACE_DCC_IND_64B {
2002SURFACE_DCC_IS_NOT_IND_64B = 0x00000000,
2003SURFACE_DCC_IS_IND_64B = 0x00000001,
2004} SURFACE_DCC_IND_64B;
2005
2006/*
2007 * SURFACE_FLIP_TYPE enum
2008 */
2009
2010typedef enum SURFACE_FLIP_TYPE {
2011SURFACE_V_FLIP = 0x00000000,
2012SURFACE_I_FLIP = 0x00000001,
2013} SURFACE_FLIP_TYPE;
2014
2015/*
2016 * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2017 */
2018
2019typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2020FLIP_ANY_FRAME = 0x00000000,
2021FLIP_LEFT_EYE = 0x00000001,
2022FLIP_RIGHT_EYE = 0x00000002,
2023SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003,
2024} SURFACE_FLIP_MODE_FOR_STEREOSYNC;
2025
2026/*
2027 * SURFACE_UPDATE_LOCK enum
2028 */
2029
2030typedef enum SURFACE_UPDATE_LOCK {
2031SURFACE_UPDATE_IS_UNLOCKED = 0x00000000,
2032SURFACE_UPDATE_IS_LOCKED = 0x00000001,
2033} SURFACE_UPDATE_LOCK;
2034
2035/*
2036 * SURFACE_FLIP_IN_STEREOSYNC enum
2037 */
2038
2039typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2040SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000,
2041SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001,
2042} SURFACE_FLIP_IN_STEREOSYNC;
2043
2044/*
2045 * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2046 */
2047
2048typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2049SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000,
2050SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001,
2051} SURFACE_FLIP_STEREO_SELECT_DISABLE;
2052
2053/*
2054 * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2055 */
2056
2057typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2058SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000,
2059SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001,
2060} SURFACE_FLIP_STEREO_SELECT_POLARITY;
2061
2062/*
2063 * SURFACE_INUSE_RAED_NO_LATCH enum
2064 */
2065
2066typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2067SURFACE_INUSE_IS_LATCHED = 0x00000000,
2068SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001,
2069} SURFACE_INUSE_RAED_NO_LATCH;
2070
2071/*
2072 * INT_MASK enum
2073 */
2074
2075typedef enum INT_MASK {
2076INT_DISABLED = 0x00000000,
2077INT_ENABLED = 0x00000001,
2078} INT_MASK;
2079
2080/*
2081 * SURFACE_FLIP_INT_TYPE enum
2082 */
2083
2084typedef enum SURFACE_FLIP_INT_TYPE {
2085SURFACE_FLIP_INT_LEVEL = 0x00000000,
2086SURFACE_FLIP_INT_PULSE = 0x00000001,
2087} SURFACE_FLIP_INT_TYPE;
2088
2089/*
2090 * SURFACE_FLIP_AWAY_INT_TYPE enum
2091 */
2092
2093typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2094SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000,
2095SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001,
2096} SURFACE_FLIP_AWAY_INT_TYPE;
2097
2098/*
2099 * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2100 */
2101
2102typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2103SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000,
2104SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001,
2105SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002,
2106SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003,
2107SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004,
2108SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005,
2109SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006,
2110SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007,
2111SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008,
2112SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009,
2113SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a,
2114SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b,
2115SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c,
2116SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d,
2117SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e,
2118SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f,
2119} SURFACE_FLIP_VUPDATE_SKIP_NUM;
2120
2121/*
2122 * DFQ_SIZE enum
2123 */
2124
2125typedef enum DFQ_SIZE {
2126DFQ_SIZE_0 = 0x00000000,
2127DFQ_SIZE_1 = 0x00000001,
2128DFQ_SIZE_2 = 0x00000002,
2129DFQ_SIZE_3 = 0x00000003,
2130DFQ_SIZE_4 = 0x00000004,
2131DFQ_SIZE_5 = 0x00000005,
2132DFQ_SIZE_6 = 0x00000006,
2133DFQ_SIZE_7 = 0x00000007,
2134} DFQ_SIZE;
2135
2136/*
2137 * DFQ_MIN_FREE_ENTRIES enum
2138 */
2139
2140typedef enum DFQ_MIN_FREE_ENTRIES {
2141DFQ_MIN_FREE_ENTRIES_0 = 0x00000000,
2142DFQ_MIN_FREE_ENTRIES_1 = 0x00000001,
2143DFQ_MIN_FREE_ENTRIES_2 = 0x00000002,
2144DFQ_MIN_FREE_ENTRIES_3 = 0x00000003,
2145DFQ_MIN_FREE_ENTRIES_4 = 0x00000004,
2146DFQ_MIN_FREE_ENTRIES_5 = 0x00000005,
2147DFQ_MIN_FREE_ENTRIES_6 = 0x00000006,
2148DFQ_MIN_FREE_ENTRIES_7 = 0x00000007,
2149} DFQ_MIN_FREE_ENTRIES;
2150
2151/*
2152 * DFQ_NUM_ENTRIES enum
2153 */
2154
2155typedef enum DFQ_NUM_ENTRIES {
2156DFQ_NUM_ENTRIES_0 = 0x00000000,
2157DFQ_NUM_ENTRIES_1 = 0x00000001,
2158DFQ_NUM_ENTRIES_2 = 0x00000002,
2159DFQ_NUM_ENTRIES_3 = 0x00000003,
2160DFQ_NUM_ENTRIES_4 = 0x00000004,
2161DFQ_NUM_ENTRIES_5 = 0x00000005,
2162DFQ_NUM_ENTRIES_6 = 0x00000006,
2163DFQ_NUM_ENTRIES_7 = 0x00000007,
2164DFQ_NUM_ENTRIES_8 = 0x00000008,
2165} DFQ_NUM_ENTRIES;
2166
2167/*
2168 * FLIP_RATE enum
2169 */
2170
2171typedef enum FLIP_RATE {
2172FLIP_RATE_0 = 0x00000000,
2173FLIP_RATE_1 = 0x00000001,
2174FLIP_RATE_2 = 0x00000002,
2175FLIP_RATE_3 = 0x00000003,
2176FLIP_RATE_4 = 0x00000004,
2177FLIP_RATE_5 = 0x00000005,
2178FLIP_RATE_6 = 0x00000006,
2179FLIP_RATE_7 = 0x00000007,
2180} FLIP_RATE;
2181
2182/*******************************************************
2183 * HUBPRET Enums
2184 *******************************************************/
2185
2186/*
2187 * DETILE_BUFFER_PACKER_ENABLE enum
2188 */
2189
2190typedef enum DETILE_BUFFER_PACKER_ENABLE {
2191DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000,
2192DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001,
2193} DETILE_BUFFER_PACKER_ENABLE;
2194
2195/*
2196 * CROSSBAR_FOR_ALPHA enum
2197 */
2198
2199typedef enum CROSSBAR_FOR_ALPHA {
2200ALPHA_DATA_ON_ALPHA_PORT = 0x00000000,
2201ALPHA_DATA_ON_Y_G_PORT = 0x00000001,
2202ALPHA_DATA_ON_CB_B_PORT = 0x00000002,
2203ALPHA_DATA_ON_CR_R_PORT = 0x00000003,
2204} CROSSBAR_FOR_ALPHA;
2205
2206/*
2207 * CROSSBAR_FOR_Y_G enum
2208 */
2209
2210typedef enum CROSSBAR_FOR_Y_G {
2211Y_G_DATA_ON_ALPHA_PORT = 0x00000000,
2212Y_G_DATA_ON_Y_G_PORT = 0x00000001,
2213Y_G_DATA_ON_CB_B_PORT = 0x00000002,
2214Y_G_DATA_ON_CR_R_PORT = 0x00000003,
2215} CROSSBAR_FOR_Y_G;
2216
2217/*
2218 * CROSSBAR_FOR_CB_B enum
2219 */
2220
2221typedef enum CROSSBAR_FOR_CB_B {
2222CB_B_DATA_ON_ALPHA_PORT = 0x00000000,
2223CB_B_DATA_ON_Y_G_PORT = 0x00000001,
2224CB_B_DATA_ON_CB_B_PORT = 0x00000002,
2225CB_B_DATA_ON_CR_R_PORT = 0x00000003,
2226} CROSSBAR_FOR_CB_B;
2227
2228/*
2229 * CROSSBAR_FOR_CR_R enum
2230 */
2231
2232typedef enum CROSSBAR_FOR_CR_R {
2233CR_R_DATA_ON_ALPHA_PORT = 0x00000000,
2234CR_R_DATA_ON_Y_G_PORT = 0x00000001,
2235CR_R_DATA_ON_CB_B_PORT = 0x00000002,
2236CR_R_DATA_ON_CR_R_PORT = 0x00000003,
2237} CROSSBAR_FOR_CR_R;
2238
2239/*
2240 * DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2241 */
2242
2243typedef enum DET_MEM_PWR_LIGHT_SLEEP_MODE {
2244DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2245DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2246DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2247} DET_MEM_PWR_LIGHT_SLEEP_MODE;
2248
2249/*
2250 * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2251 */
2252
2253typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2254PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2255PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2256} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;
2257
2258/*******************************************************
2259 * CURSOR Enums
2260 *******************************************************/
2261
2262/*
2263 * CURSOR_ENABLE enum
2264 */
2265
2266typedef enum CURSOR_ENABLE {
2267CURSOR_IS_DISABLE = 0x00000000,
2268CURSOR_IS_ENABLE = 0x00000001,
2269} CURSOR_ENABLE;
2270
2271/*
2272 * CURSOR_2X_MAGNIFY enum
2273 */
2274
2275typedef enum CURSOR_2X_MAGNIFY {
2276CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000,
2277CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001,
2278} CURSOR_2X_MAGNIFY;
2279
2280/*
2281 * CURSOR_MODE enum
2282 */
2283
2284typedef enum CURSOR_MODE {
2285CURSOR_MONO_2BIT = 0x00000000,
2286CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001,
2287CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
2288CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
2289CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004,
2290CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005,
2291} CURSOR_MODE;
2292
2293/*
2294 * CURSOR_SURFACE_TMZ enum
2295 */
2296
2297typedef enum CURSOR_SURFACE_TMZ {
2298CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000,
2299CURSOR_SURFACE_IS_TMZ = 0x00000001,
2300} CURSOR_SURFACE_TMZ;
2301
2302/*
2303 * CURSOR_SNOOP enum
2304 */
2305
2306typedef enum CURSOR_SNOOP {
2307CURSOR_IS_NOT_SNOOP = 0x00000000,
2308CURSOR_IS_SNOOP = 0x00000001,
2309} CURSOR_SNOOP;
2310
2311/*
2312 * CURSOR_SYSTEM enum
2313 */
2314
2315typedef enum CURSOR_SYSTEM {
2316CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000,
2317CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001,
2318} CURSOR_SYSTEM;
2319
2320/*
2321 * CURSOR_PITCH enum
2322 */
2323
2324typedef enum CURSOR_PITCH {
2325CURSOR_PITCH_64_PIXELS = 0x00000000,
2326CURSOR_PITCH_128_PIXELS = 0x00000001,
2327CURSOR_PITCH_256_PIXELS = 0x00000002,
2328} CURSOR_PITCH;
2329
2330/*
2331 * CURSOR_LINES_PER_CHUNK enum
2332 */
2333
2334typedef enum CURSOR_LINES_PER_CHUNK {
2335CURSOR_LINE_PER_CHUNK_1 = 0x00000000,
2336CURSOR_LINE_PER_CHUNK_2 = 0x00000001,
2337CURSOR_LINE_PER_CHUNK_4 = 0x00000002,
2338CURSOR_LINE_PER_CHUNK_8 = 0x00000003,
2339CURSOR_LINE_PER_CHUNK_16 = 0x00000004,
2340} CURSOR_LINES_PER_CHUNK;
2341
2342/*
2343 * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2344 */
2345
2346typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2347CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000,
2348CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001,
2349} CURSOR_PERFMON_LATENCY_MEASURE_EN;
2350
2351/*
2352 * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2353 */
2354
2355typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2356CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000,
2357CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001,
2358} CURSOR_PERFMON_LATENCY_MEASURE_SEL;
2359
2360/*
2361 * CURSOR_STEREO_EN enum
2362 */
2363
2364typedef enum CURSOR_STEREO_EN {
2365CURSOR_STEREO_IS_DISABLED = 0x00000000,
2366CURSOR_STEREO_IS_ENABLED = 0x00000001,
2367} CURSOR_STEREO_EN;
2368
2369/*
2370 * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2371 */
2372
2373typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2374CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000,
2375CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001,
2376} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;
2377
2378/*
2379 * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2380 */
2381
2382typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2383CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2384CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2385CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2386} CROB_MEM_PWR_LIGHT_SLEEP_MODE;
2387
2388/*
2389 * DMDATA_UPDATED enum
2390 */
2391
2392typedef enum DMDATA_UPDATED {
2393DMDATA_NOT_UPDATED = 0x00000000,
2394DMDATA_WAS_UPDATED = 0x00000001,
2395} DMDATA_UPDATED;
2396
2397/*
2398 * DMDATA_REPEAT enum
2399 */
2400
2401typedef enum DMDATA_REPEAT {
2402DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000,
2403DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001,
2404} DMDATA_REPEAT;
2405
2406/*
2407 * DMDATA_MODE enum
2408 */
2409
2410typedef enum DMDATA_MODE {
2411DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000,
2412DMDATA_HARDWARE_UPDATE_MODE = 0x00000001,
2413} DMDATA_MODE;
2414
2415/*
2416 * DMDATA_QOS_MODE enum
2417 */
2418
2419typedef enum DMDATA_QOS_MODE {
2420DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000,
2421DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001,
2422} DMDATA_QOS_MODE;
2423
2424/*
2425 * DMDATA_DONE enum
2426 */
2427
2428typedef enum DMDATA_DONE {
2429DMDATA_NOT_SENT_TO_DIG = 0x00000000,
2430DMDATA_SENT_TO_DIG = 0x00000001,
2431} DMDATA_DONE;
2432
2433/*
2434 * DMDATA_UNDERFLOW enum
2435 */
2436
2437typedef enum DMDATA_UNDERFLOW {
2438DMDATA_NOT_UNDERFLOW = 0x00000000,
2439DMDATA_UNDERFLOWED = 0x00000001,
2440} DMDATA_UNDERFLOW;
2441
2442/*
2443 * DMDATA_UNDERFLOW_CLEAR enum
2444 */
2445
2446typedef enum DMDATA_UNDERFLOW_CLEAR {
2447DMDATA_DONT_CLEAR = 0x00000000,
2448DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001,
2449} DMDATA_UNDERFLOW_CLEAR;
2450
2451/*******************************************************
2452 * HUBPXFC Enums
2453 *******************************************************/
2454
2455/*
2456 * HUBP_XFC_PIXEL_FORMAT_ENUM enum
2457 */
2458
2459typedef enum HUBP_XFC_PIXEL_FORMAT_ENUM {
2460HUBP_XFC_PIXEL_IS_32BPP = 0x00000000,
2461HUBP_XFC_PIXEL_IS_64BPP = 0x00000001,
2462} HUBP_XFC_PIXEL_FORMAT_ENUM;
2463
2464/*
2465 * HUBP_XFC_FRAME_MODE_ENUM enum
2466 */
2467
2468typedef enum HUBP_XFC_FRAME_MODE_ENUM {
2469HUBP_XFC_PARTIAL_FRAME_MODE = 0x00000000,
2470HUBP_XFC_FULL_FRAME_MODE = 0x00000001,
2471} HUBP_XFC_FRAME_MODE_ENUM;
2472
2473/*
2474 * HUBP_XFC_CHUNK_SIZE_ENUM enum
2475 */
2476
2477typedef enum HUBP_XFC_CHUNK_SIZE_ENUM {
2478HUBP_XFC_CHUNK_SIZE_256B = 0x00000000,
2479HUBP_XFC_CHUNK_SIZE_512B = 0x00000001,
2480HUBP_XFC_CHUNK_SIZE_1KB = 0x00000002,
2481HUBP_XFC_CHUNK_SIZE_2KB = 0x00000003,
2482HUBP_XFC_CHUNK_SIZE_4KB = 0x00000004,
2483HUBP_XFC_CHUNK_SIZE_8KB = 0x00000005,
2484HUBP_XFC_CHUNK_SIZE_16KB = 0x00000006,
2485HUBP_XFC_CHUNK_SIZE_32KB = 0x00000007,
2486} HUBP_XFC_CHUNK_SIZE_ENUM;
2487
2488/*******************************************************
2489 * XFC Enums
2490 *******************************************************/
2491
2492/*
2493 * MMHUBBUB_XFC_XFCMON_MODE_ENUM enum
2494 */
2495
2496typedef enum MMHUBBUB_XFC_XFCMON_MODE_ENUM {
2497MMHUBBUB_XFC_XFCMON_MODE_ONE_SHOT = 0x00000000,
2498MMHUBBUB_XFC_XFCMON_MODE_CONTINUOUS = 0x00000001,
2499MMHUBBUB_XFC_XFCMON_MODE_PERIODS = 0x00000002,
2500} MMHUBBUB_XFC_XFCMON_MODE_ENUM;
2501
2502/*
2503 * MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM enum
2504 */
2505
2506typedef enum MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM {
2507MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_SYSHUB = 0x00000000,
2508MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_MMHUB = 0x00000001,
2509} MMHUBBUB_XFC_XFCMON_INTERFACE_SEL_ENUM;
2510
2511/*******************************************************
2512 * XFCP Enums
2513 *******************************************************/
2514
2515/*
2516 * MMHUBBUB_XFC_PIXEL_FORMAT_ENUM enum
2517 */
2518
2519typedef enum MMHUBBUB_XFC_PIXEL_FORMAT_ENUM {
2520MMHUBBUB_XFC_PIXEL_IS_32BPP = 0x00000000,
2521MMHUBBUB_XFC_PIXEL_IS_64BPP = 0x00000001,
2522} MMHUBBUB_XFC_PIXEL_FORMAT_ENUM;
2523
2524/*
2525 * MMHUBBUB_XFC_FRAME_MODE_ENUM enum
2526 */
2527
2528typedef enum MMHUBBUB_XFC_FRAME_MODE_ENUM {
2529MMHUBBUB_XFC_PARTIAL_FRAME_MODE = 0x00000000,
2530MMHUBBUB_XFC_FULL_FRAME_MODE = 0x00000001,
2531} MMHUBBUB_XFC_FRAME_MODE_ENUM;
2532
2533/*******************************************************
2534 * MPC_CFG Enums
2535 *******************************************************/
2536
2537/*
2538 * MPC_CFG_MPC_TEST_CLK_SEL enum
2539 */
2540
2541typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2542MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000,
2543MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001,
2544MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002,
2545MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003,
2546} MPC_CFG_MPC_TEST_CLK_SEL;
2547
2548/*
2549 * MPC_CRC_CALC_MODE enum
2550 */
2551
2552typedef enum MPC_CRC_CALC_MODE {
2553MPC_CRC_ONE_SHOT_MODE = 0x00000000,
2554MPC_CRC_CONTINUOUS_MODE = 0x00000001,
2555} MPC_CRC_CALC_MODE;
2556
2557/*
2558 * MPC_CRC_CALC_STEREO_MODE enum
2559 */
2560
2561typedef enum MPC_CRC_CALC_STEREO_MODE {
2562MPC_CRC_STEREO_MODE_LEFT = 0x00000000,
2563MPC_CRC_STEREO_MODE_RIGHT = 0x00000001,
2564MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002,
2565MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003,
2566} MPC_CRC_CALC_STEREO_MODE;
2567
2568/*
2569 * MPC_CRC_CALC_INTERLACE_MODE enum
2570 */
2571
2572typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2573MPC_CRC_INTERLACE_MODE_TOP = 0x00000000,
2574MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
2575MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002,
2576MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003,
2577} MPC_CRC_CALC_INTERLACE_MODE;
2578
2579/*
2580 * MPC_CRC_SOURCE_SELECT enum
2581 */
2582
2583typedef enum MPC_CRC_SOURCE_SELECT {
2584MPC_CRC_SOURCE_SEL_DPP = 0x00000000,
2585MPC_CRC_SOURCE_SEL_OPP = 0x00000001,
2586MPC_CRC_SOURCE_SEL_DWB = 0x00000002,
2587MPC_CRC_SOURCE_SEL_OTHER = 0x00000003,
2588} MPC_CRC_SOURCE_SELECT;
2589
2590/*
2591 * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2592 */
2593
2594typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2595MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2596MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2597} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;
2598
2599/*
2600 * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2601 */
2602
2603typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2604MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2605MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2606} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;
2607
2608/*
2609 * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2610 */
2611
2612typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2613MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2614MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2615} MPC_CFG_CFG_VUPDATE_LOCK_SET;
2616
2617/*
2618 * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2619 */
2620
2621typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2622MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2623MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2624} MPC_CFG_ADR_VUPDATE_LOCK_SET;
2625
2626/*
2627 * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2628 */
2629
2630typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2631MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2632MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2633} MPC_CFG_CUR_VUPDATE_LOCK_SET;
2634
2635/*
2636 * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2637 */
2638
2639typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2640MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000,
2641MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001,
2642} MPC_OUT_RATE_CONTROL_DISABLE_SET;
2643
2644/*
2645 * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2646 */
2647
2648typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2649MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000,
2650MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001,
2651MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002,
2652MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003,
2653MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004,
2654MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005,
2655MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006,
2656MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007,
2657} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;
2658
2659/*******************************************************
2660 * MPC_OCSC Enums
2661 *******************************************************/
2662
2663/*
2664 * MPC_OCSC_COEF_FORMAT enum
2665 */
2666
2667typedef enum MPC_OCSC_COEF_FORMAT {
2668MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000,
2669MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001,
2670} MPC_OCSC_COEF_FORMAT;
2671
2672/*
2673 * MPC_OUT_CSC_MODE enum
2674 */
2675
2676typedef enum MPC_OUT_CSC_MODE {
2677MPC_OUT_CSC_MODE_0 = 0x00000000,
2678MPC_OUT_CSC_MODE_1 = 0x00000001,
2679MPC_OUT_CSC_MODE_2 = 0x00000002,
2680MPC_OUT_CSC_MODE_RSV = 0x00000003,
2681} MPC_OUT_CSC_MODE;
2682
2683/*******************************************************
2684 * MPCC Enums
2685 *******************************************************/
2686
2687/*
2688 * MPCC_CONTROL_MPCC_MODE enum
2689 */
2690
2691typedef enum MPCC_CONTROL_MPCC_MODE {
2692MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000,
2693MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001,
2694MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002,
2695MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003,
2696} MPCC_CONTROL_MPCC_MODE;
2697
2698/*
2699 * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2700 */
2701
2702typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2703MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000,
2704MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
2705MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002,
2706MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003,
2707} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;
2708
2709/*
2710 * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2711 */
2712
2713typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2714MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000,
2715MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001,
2716} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;
2717
2718/*
2719 * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2720 */
2721
2722typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2723MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
2724MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
2725} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;
2726
2727/*
2728 * MPCC_SM_CONTROL_MPCC_SM_EN enum
2729 */
2730
2731typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
2732MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000,
2733MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001,
2734} MPCC_SM_CONTROL_MPCC_SM_EN;
2735
2736/*
2737 * MPCC_SM_CONTROL_MPCC_SM_MODE enum
2738 */
2739
2740typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
2741MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000,
2742MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
2743MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
2744MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
2745} MPCC_SM_CONTROL_MPCC_SM_MODE;
2746
2747/*
2748 * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
2749 */
2750
2751typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
2752MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000,
2753MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001,
2754} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;
2755
2756/*
2757 * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
2758 */
2759
2760typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
2761MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000,
2762MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001,
2763} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;
2764
2765/*
2766 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
2767 */
2768
2769typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
2770MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
2771MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
2772MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
2773MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
2774} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;
2775
2776/*
2777 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
2778 */
2779
2780typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
2781MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
2782MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
2783MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
2784MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
2785} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;
2786
2787/*
2788 * MPCC_STALL_STATUS_MPCC_STALL_INT_ACK enum
2789 */
2790
2791typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_ACK {
2792MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_FALSE = 0x00000000,
2793MPCC_STALL_STATUS_MPCC_STALL_INT_ACK_TRUE = 0x00000001,
2794} MPCC_STALL_STATUS_MPCC_STALL_INT_ACK;
2795
2796/*
2797 * MPCC_STALL_STATUS_MPCC_STALL_INT_MASK enum
2798 */
2799
2800typedef enum MPCC_STALL_STATUS_MPCC_STALL_INT_MASK {
2801MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_FALSE = 0x00000000,
2802MPCC_STALL_STATUS_MPCC_STALL_INT_MASK_TRUE = 0x00000001,
2803} MPCC_STALL_STATUS_MPCC_STALL_INT_MASK;
2804
2805/*
2806 * MPCC_BG_COLOR_BPC enum
2807 */
2808
2809typedef enum MPCC_BG_COLOR_BPC {
2810MPCC_BG_COLOR_BPC_8bit = 0x00000000,
2811MPCC_BG_COLOR_BPC_9bit = 0x00000001,
2812MPCC_BG_COLOR_BPC_10bit = 0x00000002,
2813MPCC_BG_COLOR_BPC_11bit = 0x00000003,
2814MPCC_BG_COLOR_BPC_12bit = 0x00000004,
2815} MPCC_BG_COLOR_BPC;
2816
2817/*
2818 * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2819 */
2820
2821typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2822MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000,
2823MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001,
2824} MPCC_CONTROL_MPCC_BOT_GAIN_MODE;
2825
2826/*******************************************************
2827 * MPCC_OGAM Enums
2828 *******************************************************/
2829
2830/*
2831 * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
2832 */
2833
2834typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
2835MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000,
2836MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001,
2837} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;
2838
2839/*
2840 * MPCC_OGAM_MODE_MPCC_OGAM_MODE enum
2841 */
2842
2843typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE {
2844MPCC_OGAM_MODE_0 = 0x00000000,
2845MPCC_OGAM_MODE_1 = 0x00000001,
2846MPCC_OGAM_MODE_2 = 0x00000002,
2847MPCC_OGAM_MODE_RSV = 0x00000003,
2848} MPCC_OGAM_MODE_MPCC_OGAM_MODE;
2849
2850/*******************************************************
2851 * DPG Enums
2852 *******************************************************/
2853
2854/*
2855 * ENUM_DPG_EN enum
2856 */
2857
2858typedef enum ENUM_DPG_EN {
2859ENUM_DPG_DISABLE = 0x00000000,
2860ENUM_DPG_ENABLE = 0x00000001,
2861} ENUM_DPG_EN;
2862
2863/*
2864 * ENUM_DPG_MODE enum
2865 */
2866
2867typedef enum ENUM_DPG_MODE {
2868ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000,
2869ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001,
2870ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002,
2871ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003,
2872ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004,
2873ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005,
2874ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006,
2875ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007,
2876} ENUM_DPG_MODE;
2877
2878/*
2879 * ENUM_DPG_DYNAMIC_RANGE enum
2880 */
2881
2882typedef enum ENUM_DPG_DYNAMIC_RANGE {
2883ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000,
2884ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001,
2885} ENUM_DPG_DYNAMIC_RANGE;
2886
2887/*
2888 * ENUM_DPG_BIT_DEPTH enum
2889 */
2890
2891typedef enum ENUM_DPG_BIT_DEPTH {
2892ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000,
2893ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001,
2894ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002,
2895ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003,
2896} ENUM_DPG_BIT_DEPTH;
2897
2898/*
2899 * ENUM_DPG_FIELD_POLARITY enum
2900 */
2901
2902typedef enum ENUM_DPG_FIELD_POLARITY {
2903ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
2904ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
2905} ENUM_DPG_FIELD_POLARITY;
2906
2907/*******************************************************
2908 * FMT Enums
2909 *******************************************************/
2910
2911/*
2912 * FMT_CONTROL_PIXEL_ENCODING enum
2913 */
2914
2915typedef enum FMT_CONTROL_PIXEL_ENCODING {
2916FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
2917FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
2918FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
2919FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
2920} FMT_CONTROL_PIXEL_ENCODING;
2921
2922/*
2923 * FMT_CONTROL_SUBSAMPLING_MODE enum
2924 */
2925
2926typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
2927FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
2928FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
2929FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
2930FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
2931} FMT_CONTROL_SUBSAMPLING_MODE;
2932
2933/*
2934 * FMT_CONTROL_SUBSAMPLING_ORDER enum
2935 */
2936
2937typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
2938FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
2939FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
2940} FMT_CONTROL_SUBSAMPLING_ORDER;
2941
2942/*
2943 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
2944 */
2945
2946typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
2947FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
2948FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
2949} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
2950
2951/*
2952 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
2953 */
2954
2955typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
2956FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
2957FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
2958} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
2959
2960/*
2961 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
2962 */
2963
2964typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
2965FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
2966FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
2967FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
2968} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
2969
2970/*
2971 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
2972 */
2973
2974typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
2975FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
2976FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
2977FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
2978} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
2979
2980/*
2981 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
2982 */
2983
2984typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
2985FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
2986FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
2987FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
2988} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
2989
2990/*
2991 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
2992 */
2993
2994typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
2995FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
2996FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
2997} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
2998
2999/*
3000 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3001 */
3002
3003typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3004FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
3005FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
3006FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
3007FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3008} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3009
3010/*
3011 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3012 */
3013
3014typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3015FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
3016FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
3017FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
3018FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
3019} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3020
3021/*
3022 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3023 */
3024
3025typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3026FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
3027FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
3028FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
3029FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3030} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3031
3032/*
3033 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3034 */
3035
3036typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3037FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3038FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3039} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3040
3041/*
3042 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3043 */
3044
3045typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3046FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
3047FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
3048FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
3049FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
3050FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
3051FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
3052FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
3053FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3054} FMT_CLAMP_CNTL_COLOR_FORMAT;
3055
3056/*
3057 * FMT_SPATIAL_DITHER_MODE enum
3058 */
3059
3060typedef enum FMT_SPATIAL_DITHER_MODE {
3061FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
3062FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
3063FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
3064FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
3065} FMT_SPATIAL_DITHER_MODE;
3066
3067/*
3068 * FMT_DYNAMIC_EXP_MODE enum
3069 */
3070
3071typedef enum FMT_DYNAMIC_EXP_MODE {
3072FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
3073FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
3074} FMT_DYNAMIC_EXP_MODE;
3075
3076/*
3077 * FMTMEM_PWR_FORCE_CTRL enum
3078 */
3079
3080typedef enum FMTMEM_PWR_FORCE_CTRL {
3081FMTMEM_NO_FORCE_REQUEST = 0x00000000,
3082FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
3083FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
3084FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
3085} FMTMEM_PWR_FORCE_CTRL;
3086
3087/*
3088 * FMTMEM_PWR_DIS_CTRL enum
3089 */
3090
3091typedef enum FMTMEM_PWR_DIS_CTRL {
3092FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
3093FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
3094} FMTMEM_PWR_DIS_CTRL;
3095
3096/*
3097 * FMT_POWER_STATE_ENUM enum
3098 */
3099
3100typedef enum FMT_POWER_STATE_ENUM {
3101FMT_POWER_STATE_ENUM_ON = 0x00000000,
3102FMT_POWER_STATE_ENUM_LS = 0x00000001,
3103FMT_POWER_STATE_ENUM_DS = 0x00000002,
3104FMT_POWER_STATE_ENUM_SD = 0x00000003,
3105} FMT_POWER_STATE_ENUM;
3106
3107/*
3108 * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3109 */
3110
3111typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3112FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000,
3113FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001,
3114} FMT_STEREOSYNC_OVERRIDE_CONTROL;
3115
3116/*
3117 * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3118 */
3119
3120typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3121FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000,
3122FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001,
3123FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002,
3124FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003,
3125} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;
3126
3127/*
3128 * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3129 */
3130
3131typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3132FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000,
3133FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001,
3134} FMT_FRAME_RANDOM_ENABLE_CONTROL;
3135
3136/*
3137 * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3138 */
3139
3140typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3141FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000,
3142FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001,
3143} FMT_RGB_RANDOM_ENABLE_CONTROL;
3144
3145/*
3146 * ENUM_FMT_PTI_FIELD_POLARITY enum
3147 */
3148
3149typedef enum ENUM_FMT_PTI_FIELD_POLARITY {
3150ENUM_FMT_PTI_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
3151ENUM_FMT_PTI_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
3152} ENUM_FMT_PTI_FIELD_POLARITY;
3153
3154/*******************************************************
3155 * OPP_PIPE Enums
3156 *******************************************************/
3157
3158/*
3159 * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3160 */
3161
3162typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3163OPP_PIPE_CLOCK_DISABLE = 0x00000000,
3164OPP_PIPE_CLOCK_ENABLE = 0x00000001,
3165} OPP_PIPE_CLOCK_ENABLE_CONTROL;
3166
3167/*
3168 * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3169 */
3170
3171typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3172OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000,
3173OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001,
3174} OPP_PIPE_DIGTIAL_BYPASS_CONTROL;
3175
3176/*******************************************************
3177 * OPP_PIPE_CRC Enums
3178 *******************************************************/
3179
3180/*
3181 * OPP_PIPE_CRC_EN enum
3182 */
3183
3184typedef enum OPP_PIPE_CRC_EN {
3185OPP_PIPE_CRC_DISABLE = 0x00000000,
3186OPP_PIPE_CRC_ENABLE = 0x00000001,
3187} OPP_PIPE_CRC_EN;
3188
3189/*
3190 * OPP_PIPE_CRC_CONT_EN enum
3191 */
3192
3193typedef enum OPP_PIPE_CRC_CONT_EN {
3194OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000,
3195OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001,
3196} OPP_PIPE_CRC_CONT_EN;
3197
3198/*
3199 * OPP_PIPE_CRC_STEREO_MODE enum
3200 */
3201
3202typedef enum OPP_PIPE_CRC_STEREO_MODE {
3203OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000,
3204OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001,
3205OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002,
3206OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003,
3207} OPP_PIPE_CRC_STEREO_MODE;
3208
3209/*
3210 * OPP_PIPE_CRC_STEREO_EN enum
3211 */
3212
3213typedef enum OPP_PIPE_CRC_STEREO_EN {
3214OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000,
3215OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001,
3216} OPP_PIPE_CRC_STEREO_EN;
3217
3218/*
3219 * OPP_PIPE_CRC_INTERLACE_MODE enum
3220 */
3221
3222typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3223OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000,
3224OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
3225OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002,
3226OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003,
3227} OPP_PIPE_CRC_INTERLACE_MODE;
3228
3229/*
3230 * OPP_PIPE_CRC_INTERLACE_EN enum
3231 */
3232
3233typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3234OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000,
3235OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001,
3236} OPP_PIPE_CRC_INTERLACE_EN;
3237
3238/*
3239 * OPP_PIPE_CRC_PIXEL_SELECT enum
3240 */
3241
3242typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3243OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000,
3244OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001,
3245OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002,
3246OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003,
3247} OPP_PIPE_CRC_PIXEL_SELECT;
3248
3249/*
3250 * OPP_PIPE_CRC_SOURCE_SELECT enum
3251 */
3252
3253typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3254OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000,
3255OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001,
3256} OPP_PIPE_CRC_SOURCE_SELECT;
3257
3258/*
3259 * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3260 */
3261
3262typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3263OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000,
3264OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001,
3265} OPP_PIPE_CRC_ONE_SHOT_PENDING;
3266
3267/*******************************************************
3268 * OPP_TOP Enums
3269 *******************************************************/
3270
3271/*
3272 * OPP_TOP_CLOCK_GATING_CONTROL enum
3273 */
3274
3275typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3276OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000,
3277OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001,
3278} OPP_TOP_CLOCK_GATING_CONTROL;
3279
3280/*
3281 * OPP_TOP_CLOCK_ENABLE_STATUS enum
3282 */
3283
3284typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3285OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000,
3286OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001,
3287} OPP_TOP_CLOCK_ENABLE_STATUS;
3288
3289/*
3290 * OPP_TEST_CLK_SEL_CONTROL enum
3291 */
3292
3293typedef enum OPP_TEST_CLK_SEL_CONTROL {
3294OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
3295OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001,
3296OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002,
3297OPP_TEST_CLK_SEL_RESERVED0 = 0x00000003,
3298OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000004,
3299OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000005,
3300OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x00000006,
3301OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x00000007,
3302OPP_TEST_CLK_SEL_DISPCLK_OPP4 = 0x00000008,
3303OPP_TEST_CLK_SEL_DISPCLK_OPP5 = 0x00000009,
3304} OPP_TEST_CLK_SEL_CONTROL;
3305
3306/*******************************************************
3307 * OTG Enums
3308 *******************************************************/
3309
3310/*
3311 * OTG_CONTROL_OTG_START_POINT_CNTL enum
3312 */
3313
3314typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3315OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000,
3316OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001,
3317} OTG_CONTROL_OTG_START_POINT_CNTL;
3318
3319/*
3320 * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3321 */
3322
3323typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3324OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
3325OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001,
3326} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;
3327
3328/*
3329 * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3330 */
3331
3332typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3333OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
3334OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
3335OTG_CONTROL_OTG_DISABLE_POINT_CNTL_RESERVED = 0x00000002,
3336OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
3337} OTG_CONTROL_OTG_DISABLE_POINT_CNTL;
3338
3339/*
3340 * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3341 */
3342
3343typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3344OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
3345OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
3346} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;
3347
3348/*
3349 * OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE enum
3350 */
3351
3352typedef enum OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE {
3353OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_FALSE = 0x00000000,
3354OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE_TRUE = 0x00000001,
3355} OTG_CONTROL_OTG_DISP_READ_REQUEST_DISABLE;
3356
3357/*
3358 * OTG_CONTROL_OTG_SOF_PULL_EN enum
3359 */
3360
3361typedef enum OTG_CONTROL_OTG_SOF_PULL_EN {
3362OTG_CONTROL_OTG_SOF_PULL_EN_FALSE = 0x00000000,
3363OTG_CONTROL_OTG_SOF_PULL_EN_TRUE = 0x00000001,
3364} OTG_CONTROL_OTG_SOF_PULL_EN;
3365
3366/*
3367 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
3368 */
3369
3370typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
3371OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
3372OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
3373} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;
3374
3375/*
3376 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
3377 */
3378
3379typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
3380OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
3381OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
3382} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;
3383
3384/*
3385 * OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN enum
3386 */
3387
3388typedef enum OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN {
3389OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_FALSE = 0x00000000,
3390OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN_TRUE = 0x00000001,
3391} OTG_V_TOTAL_CONTROL_OTG_SET_V_TOTAL_MIN_MASK_EN;
3392
3393/*
3394 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
3395 */
3396
3397typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
3398OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
3399OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
3400} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;
3401
3402/*
3403 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
3404 */
3405
3406typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
3407OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
3408OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
3409} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;
3410
3411/*
3412 * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
3413 */
3414
3415typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
3416OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000,
3417OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001,
3418} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;
3419
3420/*
3421 * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK enum
3422 */
3423
3424typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK {
3425OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_FALSE = 0x00000000,
3426OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK_TRUE = 0x00000001,
3427} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURED_ACK;
3428
3429/*
3430 * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
3431 */
3432
3433typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
3434OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
3435OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
3436} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;
3437
3438/*
3439 * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
3440 */
3441
3442typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
3443OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000,
3444OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001,
3445} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;
3446
3447/*
3448 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
3449 */
3450
3451typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
3452OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000,
3453OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
3454OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
3455OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
3456OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
3457OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
3458OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
3459OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
3460OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
3461OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
3462OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
3463OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
3464OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
3465OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
3466OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e,
3467OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
3468OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
3469OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
3470OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012,
3471OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013,
3472OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014,
3473OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
3474OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
3475OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017,
3476OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
3477} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;
3478
3479/*
3480 * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
3481 */
3482
3483typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
3484OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000,
3485OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
3486OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
3487OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
3488OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
3489OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005,
3490OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006,
3491OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007,
3492} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;
3493
3494/*
3495 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
3496 */
3497
3498typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
3499OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000,
3500OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
3501OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
3502OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
3503OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
3504OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
3505OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
3506OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
3507OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
3508OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
3509OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
3510OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
3511OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
3512OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
3513OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_DSI_FORCE_TOTAL = 0x0000000e,
3514OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
3515OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
3516OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
3517OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012,
3518OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013,
3519OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014,
3520OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
3521OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
3522OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017,
3523OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
3524} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;
3525
3526/*
3527 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
3528 */
3529
3530typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
3531OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
3532OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
3533OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
3534OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
3535OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG4 = 0x00000004,
3536OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG5 = 0x00000005,
3537} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;
3538
3539/*
3540 * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
3541 */
3542
3543typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
3544OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000,
3545OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
3546OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
3547OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
3548OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
3549OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005,
3550OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006,
3551OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007,
3552} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;
3553
3554/*
3555 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
3556 */
3557
3558typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
3559OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
3560OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
3561OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
3562OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
3563OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG4 = 0x00000004,
3564OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG5 = 0x00000005,
3565} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;
3566
3567/*
3568 * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
3569 */
3570
3571typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
3572OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
3573OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
3574} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;
3575
3576/*
3577 * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
3578 */
3579
3580typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
3581OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000,
3582OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001,
3583} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;
3584
3585/*
3586 * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
3587 */
3588
3589typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
3590OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
3591OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
3592} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;
3593
3594/*
3595 * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
3596 */
3597
3598typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
3599OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000,
3600OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001,
3601} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;
3602
3603/*
3604 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
3605 */
3606
3607typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
3608OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
3609OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
3610OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
3611OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
3612} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;
3613
3614/*
3615 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
3616 */
3617
3618typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
3619OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
3620OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
3621} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;
3622
3623/*
3624 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
3625 */
3626
3627typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
3628OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
3629OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
3630} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;
3631
3632/*
3633 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
3634 */
3635
3636typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
3637OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
3638OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
3639} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;
3640
3641/*
3642 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
3643 */
3644
3645typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
3646OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
3647OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001,
3648OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002,
3649OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003,
3650OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004,
3651OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005,
3652OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006,
3653OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007,
3654OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008,
3655OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009,
3656OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a,
3657OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b,
3658OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c,
3659OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d,
3660OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e,
3661OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DSI_FREEZE = 0x0000000f,
3662OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010,
3663OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011,
3664OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012,
3665OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013,
3666} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT;
3667
3668/*
3669 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
3670 */
3671
3672typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
3673OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
3674OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
3675} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY;
3676
3677/*
3678 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
3679 */
3680
3681typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
3682OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
3683OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
3684} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY;
3685
3686/*
3687 * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
3688 */
3689
3690typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
3691OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
3692OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
3693OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
3694OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
3695} OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE;
3696
3697/*
3698 * OTG_CONTROL_OTG_MASTER_EN enum
3699 */
3700
3701typedef enum OTG_CONTROL_OTG_MASTER_EN {
3702OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000,
3703OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001,
3704} OTG_CONTROL_OTG_MASTER_EN;
3705
3706/*
3707 * OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN enum
3708 */
3709
3710typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN {
3711OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_FALSE = 0x00000000,
3712OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN_TRUE = 0x00000001,
3713} OTG_BLANK_CONTROL_OTG_BLANK_DATA_EN;
3714
3715/*
3716 * OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE enum
3717 */
3718
3719typedef enum OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE {
3720OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_FALSE = 0x00000000,
3721OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE_TRUE = 0x00000001,
3722} OTG_BLANK_CONTROL_OTG_BLANK_DE_MODE;
3723
3724/*
3725 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
3726 */
3727
3728typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
3729OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000,
3730OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001,
3731} OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE;
3732
3733/*
3734 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
3735 */
3736
3737typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
3738OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
3739OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001,
3740OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002,
3741OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
3742} OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD;
3743
3744/*
3745 * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY enum
3746 */
3747
3748typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY {
3749OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_FALSE = 0x00000000,
3750OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY_TRUE = 0x00000001,
3751} OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_INDICATION_OUTPUT_POLARITY;
3752
3753/*
3754 * OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT enum
3755 */
3756
3757typedef enum OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT {
3758OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_FALSE = 0x00000000,
3759OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT_TRUE = 0x00000001,
3760} OTG_FIELD_INDICATION_CONTROL_OTG_FIELD_ALIGNMENT;
3761
3762/*
3763 * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3764 */
3765
3766typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3767OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
3768OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
3769} OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN;
3770
3771/*
3772 * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
3773 */
3774
3775typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
3776OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
3777OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
3778} OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE;
3779
3780/*
3781 * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
3782 */
3783
3784typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
3785OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
3786OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
3787} OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;
3788
3789/*
3790 * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
3791 */
3792
3793typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
3794OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
3795OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
3796OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
3797OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
3798} OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE;
3799
3800/*
3801 * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
3802 */
3803
3804typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
3805OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
3806OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
3807} OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY;
3808
3809/*
3810 * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
3811 */
3812
3813typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
3814OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
3815OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
3816} OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY;
3817
3818/*
3819 * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
3820 */
3821
3822typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
3823OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000,
3824OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001,
3825} OTG_STEREO_CONTROL_OTG_STEREO_EN;
3826
3827/*
3828 * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
3829 */
3830
3831typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
3832OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000,
3833OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001,
3834} OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR;
3835
3836/*
3837 * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
3838 */
3839
3840typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
3841OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
3842OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
3843OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
3844OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
3845} OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL;
3846
3847/*
3848 * OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY enum
3849 */
3850
3851typedef enum OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY {
3852OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_FALSE = 0x00000000,
3853OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY_TRUE = 0x00000001,
3854} OTG_START_LINE_CONTROL_OTG_PROGRESSIVE_START_LINE_EARLY;
3855
3856/*
3857 * OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY enum
3858 */
3859
3860typedef enum OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY {
3861OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_FALSE = 0x00000000,
3862OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY_TRUE = 0x00000001,
3863} OTG_START_LINE_CONTROL_OTG_INTERLACE_START_LINE_EARLY;
3864
3865/*
3866 * OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN enum
3867 */
3868
3869typedef enum OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN {
3870OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_FALSE = 0x00000000,
3871OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN_TRUE = 0x00000001,
3872} OTG_START_LINE_CONTROL_OTG_LEGACY_REQUESTOR_EN;
3873
3874/*
3875 * OTG_START_LINE_CONTROL_OTG_PREFETCH_EN enum
3876 */
3877
3878typedef enum OTG_START_LINE_CONTROL_OTG_PREFETCH_EN {
3879OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_FALSE = 0x00000000,
3880OTG_START_LINE_CONTROL_OTG_PREFETCH_EN_TRUE = 0x00000001,
3881} OTG_START_LINE_CONTROL_OTG_PREFETCH_EN;
3882
3883/*
3884 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
3885 */
3886
3887typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
3888OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
3889OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
3890} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK;
3891
3892/*
3893 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
3894 */
3895
3896typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
3897OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
3898OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
3899} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE;
3900
3901/*
3902 * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK enum
3903 */
3904
3905typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK {
3906OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_FALSE = 0x00000000,
3907OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK_TRUE = 0x00000001,
3908} OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_MSK;
3909
3910/*
3911 * OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE enum
3912 */
3913
3914typedef enum OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE {
3915OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_FALSE = 0x00000000,
3916OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE_TRUE = 0x00000001,
3917} OTG_INTERRUPT_CONTROL_OTG_V_UPDATE_INT_TYPE;
3918
3919/*
3920 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
3921 */
3922
3923typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
3924OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
3925OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
3926} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK;
3927
3928/*
3929 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
3930 */
3931
3932typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
3933OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
3934OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
3935} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE;
3936
3937/*
3938 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
3939 */
3940
3941typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
3942OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
3943OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
3944} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK;
3945
3946/*
3947 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
3948 */
3949
3950typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
3951OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
3952OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
3953} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
3954
3955/*
3956 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
3957 */
3958
3959typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
3960OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000,
3961OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001,
3962} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK;
3963
3964/*
3965 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
3966 */
3967
3968typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
3969OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000,
3970OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001,
3971} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE;
3972
3973/*
3974 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
3975 */
3976
3977typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
3978OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000,
3979OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001,
3980} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK;
3981
3982/*
3983 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
3984 */
3985
3986typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
3987OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000,
3988OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001,
3989} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE;
3990
3991/*
3992 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
3993 */
3994
3995typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
3996OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
3997OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
3998} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK;
3999
4000/*
4001 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4002 */
4003
4004typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4005OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
4006OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
4007} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE;
4008
4009/*
4010 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4011 */
4012
4013typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4014OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
4015OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
4016} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK;
4017
4018/*
4019 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4020 */
4021
4022typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4023OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
4024OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
4025} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE;
4026
4027/*
4028 * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4029 */
4030
4031typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4032OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000,
4033OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001,
4034} OTG_UPDATE_LOCK_OTG_UPDATE_LOCK;
4035
4036/*
4037 * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4038 */
4039
4040typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4041OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000,
4042OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001,
4043} OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY;
4044
4045/*
4046 * OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN enum
4047 */
4048
4049typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN {
4050OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_FALSE = 0x00000000,
4051OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN_TRUE = 0x00000001,
4052} OTG_DOUBLE_BUFFER_CONTROL_OTG_BLANK_DATA_DOUBLE_BUFFER_EN;
4053
4054/*
4055 * OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE enum
4056 */
4057
4058typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE {
4059OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
4060OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
4061OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002,
4062OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003,
4063} OTG_DOUBLE_BUFFER_CONTROL_OTG_RANGE_TIMING_DBUF_UPDATE_MODE;
4064
4065/*
4066 * OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE enum
4067 */
4068
4069typedef enum OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE {
4070OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_FALSE = 0x00000000,
4071OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE_TRUE = 0x00000001,
4072} OTG_VGA_PARAMETER_CAPTURE_MODE_OTG_VGA_PARAMETER_CAPTURE_MODE;
4073
4074/*
4075 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
4076 */
4077
4078typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
4079MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
4080MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
4081} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
4082
4083/*
4084 * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4085 */
4086
4087typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4088OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000,
4089OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001,
4090OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002,
4091OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003,
4092} OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME;
4093
4094/*
4095 * MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK enum
4096 */
4097
4098typedef enum MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK {
4099MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_FALSE = 0x00000000,
4100MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK_TRUE = 0x00000001,
4101} MASTER_UPDATE_LOCK_UNDERFLOW_UPDATE_LOCK;
4102
4103/*
4104 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
4105 */
4106
4107typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
4108MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
4109MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001,
4110MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002,
4111MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
4112} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
4113
4114/*
4115 * OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE enum
4116 */
4117
4118typedef enum OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE {
4119OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DISABLE = 0x00000000,
4120OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_DEBUG = 0x00000001,
4121OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE_NORMAL = 0x00000002,
4122} OTG_MVP_INBAND_CNTL_INSERT_OTG_MVP_INBAND_OUT_MODE;
4123
4124/*
4125 * OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR enum
4126 */
4127
4128typedef enum OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR {
4129OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_FALSE = 0x00000000,
4130OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR_TRUE = 0x00000001,
4131} OTG_MVP_STATUS_OTG_FLIP_NOW_CLEAR;
4132
4133/*
4134 * OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR enum
4135 */
4136
4137typedef enum OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR {
4138OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_FALSE = 0x00000000,
4139OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR_TRUE = 0x00000001,
4140} OTG_MVP_STATUS_OTG_AFR_HSYNC_SWITCH_DONE_CLEAR;
4141
4142/*
4143 * OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR enum
4144 */
4145
4146typedef enum OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR {
4147OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_FALSE = 0x00000000,
4148OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR_TRUE = 0x00000001,
4149} OTG_V_UPDATE_INT_STATUS_OTG_V_UPDATE_INT_CLEAR;
4150
4151/*
4152 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4153 */
4154
4155typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4156OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
4157OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
4158} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
4159
4160/*
4161 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4162 */
4163
4164typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4165OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
4166OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
4167} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE;
4168
4169/*
4170 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4171 */
4172
4173typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4174OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
4175OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
4176} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR;
4177
4178/*
4179 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4180 */
4181
4182typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4183OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
4184OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
4185} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE;
4186
4187/*
4188 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4189 */
4190
4191typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4192OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
4193OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
4194} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR;
4195
4196/*
4197 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4198 */
4199
4200typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4201OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
4202OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
4203} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE;
4204
4205/*
4206 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4207 */
4208
4209typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4210OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
4211OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
4212} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE;
4213
4214/*
4215 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4216 */
4217
4218typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4219OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
4220OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
4221} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR;
4222
4223/*
4224 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4225 */
4226
4227typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4228OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
4229OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
4230} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE;
4231
4232/*
4233 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4234 */
4235
4236typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4237OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
4238OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
4239} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE;
4240
4241/*
4242 * OTG_CRC_CNTL_OTG_CRC_EN enum
4243 */
4244
4245typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4246OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000,
4247OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001,
4248} OTG_CRC_CNTL_OTG_CRC_EN;
4249
4250/*
4251 * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
4252 */
4253
4254typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
4255OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000,
4256OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001,
4257} OTG_CRC_CNTL_OTG_CRC_CONT_EN;
4258
4259/*
4260 * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4261 */
4262
4263typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4264OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000,
4265OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001,
4266OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
4267OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
4268} OTG_CRC_CNTL_OTG_CRC_STEREO_MODE;
4269
4270/*
4271 * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4272 */
4273
4274typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4275OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000,
4276OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
4277OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
4278OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
4279} OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE;
4280
4281/*
4282 * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4283 */
4284
4285typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4286OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
4287OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
4288} OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS;
4289
4290/*
4291 * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4292 */
4293
4294typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4295OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000,
4296OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001,
4297OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002,
4298OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003,
4299OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004,
4300OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005,
4301OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006,
4302OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007,
4303} OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT;
4304
4305/*
4306 * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4307 */
4308
4309typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4310OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000,
4311OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001,
4312OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002,
4313OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003,
4314OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004,
4315OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005,
4316OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006,
4317OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007,
4318} OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT;
4319
4320/*
4321 * OTG_CRC_CNTL2_OTG_CRC_DSC_MODE enum
4322 */
4323
4324typedef enum OTG_CRC_CNTL2_OTG_CRC_DSC_MODE {
4325OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_FALSE = 0x00000000,
4326OTG_CRC_CNTL2_OTG_CRC_DSC_MODE_TRUE = 0x00000001,
4327} OTG_CRC_CNTL2_OTG_CRC_DSC_MODE;
4328
4329/*
4330 * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE enum
4331 */
4332
4333typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE {
4334OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_FALSE = 0x00000000,
4335OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE_TRUE = 0x00000001,
4336} OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_COMBINE_MODE;
4337
4338/*
4339 * OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE enum
4340 */
4341
4342typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE {
4343OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_DSIABLE = 0x00000000,
4344OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_1 = 0x00000001,
4345OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_2 = 0x00000002,
4346OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE_3 = 0x00000003,
4347} OTG_CRC_CNTL2_OTG_CRC_DATA_STREAM_SPLIT_MODE;
4348
4349/*
4350 * OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT enum
4351 */
4352
4353typedef enum OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT {
4354OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_0 = 0x00000000,
4355OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_1 = 0x00000001,
4356OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_2 = 0x00000002,
4357OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT_3 = 0x00000003,
4358} OTG_CRC_CNTL2_OTG_CRC_DATA_FORMAT;
4359
4360/*
4361 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE enum
4362 */
4363
4364typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE {
4365OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_DISABLE = 0x00000000,
4366OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_ONESHOT = 0x00000001,
4367OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_CONTINUOUS = 0x00000002,
4368OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE_RESERVED = 0x00000003,
4369} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_ENABLE;
4370
4371/*
4372 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE enum
4373 */
4374
4375typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE {
4376OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_FALSE = 0x00000000,
4377OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE_TRUE = 0x00000001,
4378} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HCOUNT_MODE_ENABLE;
4379
4380/*
4381 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE enum
4382 */
4383
4384typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE {
4385OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_FALSE = 0x00000000,
4386OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE_TRUE = 0x00000001,
4387} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_ENABLE;
4388
4389/*
4390 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW enum
4391 */
4392
4393typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW {
4394OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_1pixel = 0x00000000,
4395OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_2pixel = 0x00000001,
4396OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_3pixel = 0x00000002,
4397OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW_4pixel = 0x00000003,
4398} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_JITTER_FILTERING_WINDOW;
4399
4400/*
4401 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE enum
4402 */
4403
4404typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE {
4405OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_FALSE = 0x00000000,
4406OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE_TRUE = 0x00000001,
4407} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_ENABLE;
4408
4409/*
4410 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE enum
4411 */
4412
4413typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE {
4414OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_FALSE = 0x00000000,
4415OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE_TRUE = 0x00000001,
4416} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_WINDOW_UPDATE;
4417
4418/*
4419 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY enum
4420 */
4421
4422typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY {
4423OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_FALSE = 0x00000000,
4424OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY_TRUE = 0x00000001,
4425} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_VSYNC_POLARITY;
4426
4427/*
4428 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY enum
4429 */
4430
4431typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY {
4432OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_FALSE = 0x00000000,
4433OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY_TRUE = 0x00000001,
4434} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_HSYNC_POLARITY;
4435
4436/*
4437 * OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE enum
4438 */
4439
4440typedef enum OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE {
4441OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_FALSE = 0x00000000,
4442OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE_TRUE = 0x00000001,
4443} OTG_EXT_TIMING_SYNC_CONTROL_OTG_EXT_TIMING_SYNC_INTERLACE_MODE;
4444
4445/*
4446 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE enum
4447 */
4448
4449typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE {
4450OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_FALSE = 0x00000000,
4451OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE_TRUE = 0x00000001,
4452} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_ENABLE;
4453
4454/*
4455 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR enum
4456 */
4457
4458typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR {
4459OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_FALSE = 0x00000000,
4460OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR_TRUE = 0x00000001,
4461} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_CLEAR;
4462
4463/*
4464 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE enum
4465 */
4466
4467typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE {
4468OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_FALSE = 0x00000000,
4469OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE_TRUE = 0x00000001,
4470} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_INT_TYPE;
4471
4472/*
4473 * OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT enum
4474 */
4475
4476typedef enum OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT {
4477OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_1FRAME = 0x00000000,
4478OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_2FRAME = 0x00000001,
4479OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_4FRAME = 0x00000002,
4480OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_8FRAME = 0x00000003,
4481OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_16FRAME = 0x00000004,
4482OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_32FRAME = 0x00000005,
4483OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_64FRAME = 0x00000006,
4484OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT_128FRAME = 0x00000007,
4485} OTG_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_LOSS_FRAME_COUNT;
4486
4487/*
4488 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE enum
4489 */
4490
4491typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE {
4492OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_FALSE = 0x00000000,
4493OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE_TRUE = 0x00000001,
4494} OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_ENABLE;
4495
4496/*
4497 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR enum
4498 */
4499
4500typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR {
4501OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_FALSE = 0x00000000,
4502OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR_TRUE = 0x00000001,
4503} OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_CLEAR;
4504
4505/*
4506 * OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE enum
4507 */
4508
4509typedef enum OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE {
4510OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_FALSE = 0x00000000,
4511OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE_TRUE = 0x00000001,
4512} OTG_EXT_TIMING_SYNC_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_INT_TYPE;
4513
4514/*
4515 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE enum
4516 */
4517
4518typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE {
4519OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_FALSE = 0x00000000,
4520OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE_TRUE = 0x00000001,
4521} OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_ENABLE;
4522
4523/*
4524 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR enum
4525 */
4526
4527typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR {
4528OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_FALSE = 0x00000000,
4529OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR_TRUE = 0x00000001,
4530} OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_CLEAR;
4531
4532/*
4533 * OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE enum
4534 */
4535
4536typedef enum OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE {
4537OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_FALSE = 0x00000000,
4538OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE_TRUE = 0x00000001,
4539} OTG_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL_OTG_EXT_TIMING_SYNC_SIGNAL_INT_TYPE;
4540
4541/*
4542 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4543 */
4544
4545typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4546OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
4547OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
4548} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE;
4549
4550/*
4551 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4552 */
4553
4554typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4555OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
4556OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
4557} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR;
4558
4559/*
4560 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4561 */
4562
4563typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4564OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000,
4565OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001,
4566} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE;
4567
4568/*
4569 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4570 */
4571
4572typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4573OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
4574OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
4575} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE;
4576
4577/*
4578 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4579 */
4580
4581typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4582OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
4583OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
4584} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE;
4585
4586/*
4587 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
4588 */
4589
4590typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
4591OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000,
4592OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001,
4593} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN;
4594
4595/*
4596 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
4597 */
4598
4599typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
4600OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
4601OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
4602} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB;
4603
4604/*
4605 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
4606 */
4607
4608typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
4609OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
4610OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
4611OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
4612OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
4613} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE;
4614
4615/*
4616 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
4617 */
4618
4619typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
4620OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
4621OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
4622} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR;
4623
4624/*
4625 * OTG_V_SYNC_A_POL enum
4626 */
4627
4628typedef enum OTG_V_SYNC_A_POL {
4629OTG_V_SYNC_A_POL_HIGH = 0x00000000,
4630OTG_V_SYNC_A_POL_LOW = 0x00000001,
4631} OTG_V_SYNC_A_POL;
4632
4633/*
4634 * OTG_H_SYNC_A_POL enum
4635 */
4636
4637typedef enum OTG_H_SYNC_A_POL {
4638OTG_H_SYNC_A_POL_HIGH = 0x00000000,
4639OTG_H_SYNC_A_POL_LOW = 0x00000001,
4640} OTG_H_SYNC_A_POL;
4641
4642/*
4643 * OTG_HORZ_REPETITION_COUNT enum
4644 */
4645
4646typedef enum OTG_HORZ_REPETITION_COUNT {
4647OTG_HORZ_REPETITION_COUNT_0 = 0x00000000,
4648OTG_HORZ_REPETITION_COUNT_1 = 0x00000001,
4649OTG_HORZ_REPETITION_COUNT_2 = 0x00000002,
4650OTG_HORZ_REPETITION_COUNT_3 = 0x00000003,
4651OTG_HORZ_REPETITION_COUNT_4 = 0x00000004,
4652OTG_HORZ_REPETITION_COUNT_5 = 0x00000005,
4653OTG_HORZ_REPETITION_COUNT_6 = 0x00000006,
4654OTG_HORZ_REPETITION_COUNT_7 = 0x00000007,
4655OTG_HORZ_REPETITION_COUNT_8 = 0x00000008,
4656OTG_HORZ_REPETITION_COUNT_9 = 0x00000009,
4657OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a,
4658OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b,
4659OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c,
4660OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d,
4661OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e,
4662OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f,
4663} OTG_HORZ_REPETITION_COUNT;
4664
4665/*
4666 * MASTER_UPDATE_LOCK_SEL enum
4667 */
4668
4669typedef enum MASTER_UPDATE_LOCK_SEL {
4670MASTER_UPDATE_LOCK_SEL_0 = 0x00000000,
4671MASTER_UPDATE_LOCK_SEL_1 = 0x00000001,
4672MASTER_UPDATE_LOCK_SEL_2 = 0x00000002,
4673MASTER_UPDATE_LOCK_SEL_3 = 0x00000003,
4674MASTER_UPDATE_LOCK_SEL_4 = 0x00000004,
4675MASTER_UPDATE_LOCK_SEL_5 = 0x00000005,
4676} MASTER_UPDATE_LOCK_SEL;
4677
4678/*
4679 * DRR_UPDATE_LOCK_SEL enum
4680 */
4681
4682typedef enum DRR_UPDATE_LOCK_SEL {
4683DRR_UPDATE_LOCK_SEL_0 = 0x00000000,
4684DRR_UPDATE_LOCK_SEL_1 = 0x00000001,
4685DRR_UPDATE_LOCK_SEL_2 = 0x00000002,
4686DRR_UPDATE_LOCK_SEL_3 = 0x00000003,
4687DRR_UPDATE_LOCK_SEL_4 = 0x00000004,
4688DRR_UPDATE_LOCK_SEL_5 = 0x00000005,
4689} DRR_UPDATE_LOCK_SEL;
4690
4691/*
4692 * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4693 */
4694
4695typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4696OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000,
4697OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001,
4698OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002,
4699OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003,
4700OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG4 = 0x00000004,
4701OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG5 = 0x00000005,
4702} OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL;
4703
4704/*
4705 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4706 */
4707
4708typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4709MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000,
4710MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001,
4711MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000002,
4712} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD;
4713
4714/*
4715 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4716 */
4717
4718typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4719MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000,
4720MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001,
4721MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002,
4722MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003,
4723} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL;
4724
4725/*
4726 * OTG_H_TIMING_DIV_BY2 enum
4727 */
4728
4729typedef enum OTG_H_TIMING_DIV_BY2 {
4730OTG_H_TIMING_DIV_BY2_FALSE = 0x00000000,
4731OTG_H_TIMING_DIV_BY2_TRUE = 0x00000001,
4732} OTG_H_TIMING_DIV_BY2;
4733
4734/*
4735 * OTG_H_TIMING_DIV_BY2_UPDATE_MODE enum
4736 */
4737
4738typedef enum OTG_H_TIMING_DIV_BY2_UPDATE_MODE {
4739OTG_H_TIMING_DIV_BY2_UPDATE_MODE_0 = 0x00000000,
4740OTG_H_TIMING_DIV_BY2_UPDATE_MODE_1 = 0x00000001,
4741} OTG_H_TIMING_DIV_BY2_UPDATE_MODE;
4742
4743/*
4744 * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4745 */
4746
4747typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4748OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4749OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4750OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4751OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4752} OTG_TRIGA_RISING_EDGE_DETECT_CNTL;
4753
4754/*
4755 * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4756 */
4757
4758typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4759OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4760OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4761OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4762OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4763} OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;
4764
4765/*
4766 * OTG_TRIGA_FREQUENCY_SELECT enum
4767 */
4768
4769typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4770OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000,
4771OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001,
4772OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002,
4773OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003,
4774} OTG_TRIGA_FREQUENCY_SELECT;
4775
4776/*
4777 * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4778 */
4779
4780typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4781OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4782OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4783OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4784OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4785} OTG_TRIGB_RISING_EDGE_DETECT_CNTL;
4786
4787/*
4788 * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4789 */
4790
4791typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4792OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4793OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4794OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4795OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4796} OTG_TRIGB_FALLING_EDGE_DETECT_CNTL;
4797
4798/*
4799 * OTG_TRIGB_FREQUENCY_SELECT enum
4800 */
4801
4802typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4803OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000,
4804OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001,
4805OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002,
4806OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003,
4807} OTG_TRIGB_FREQUENCY_SELECT;
4808
4809/*
4810 * OTG_PIPE_ABORT enum
4811 */
4812
4813typedef enum OTG_PIPE_ABORT {
4814OTG_PIPE_ABORT_0 = 0x00000000,
4815OTG_PIPE_ABORT_1 = 0x00000001,
4816} OTG_PIPE_ABORT;
4817
4818/*
4819 * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4820 */
4821
4822typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4823OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000,
4824OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001,
4825} OTG_MASTER_UPDATE_LOCK_GSL_EN;
4826
4827/*
4828 * OTG_PTI_CONTROL_OTG_PIT_EN enum
4829 */
4830
4831typedef enum OTG_PTI_CONTROL_OTG_PIT_EN {
4832OTG_PTI_CONTROL_OTG_PIT_EN_FALSE = 0x00000000,
4833OTG_PTI_CONTROL_OTG_PIT_EN_TRUE = 0x00000001,
4834} OTG_PTI_CONTROL_OTG_PIT_EN;
4835
4836/*
4837 * OTG_GSL_MASTER_MODE enum
4838 */
4839
4840typedef enum OTG_GSL_MASTER_MODE {
4841OTG_GSL_MASTER_MODE_0 = 0x00000000,
4842OTG_GSL_MASTER_MODE_1 = 0x00000001,
4843OTG_GSL_MASTER_MODE_2 = 0x00000002,
4844OTG_GSL_MASTER_MODE_3 = 0x00000003,
4845} OTG_GSL_MASTER_MODE;
4846
4847/*******************************************************
4848 * DMCUB Enums
4849 *******************************************************/
4850
4851/*
4852 * DC_DMCUB_TIMER_WINDOW enum
4853 */
4854
4855typedef enum DC_DMCUB_TIMER_WINDOW {
4856BITS_31_0 = 0x00000000,
4857BITS_32_1 = 0x00000001,
4858BITS_33_2 = 0x00000002,
4859BITS_34_3 = 0x00000003,
4860BITS_35_4 = 0x00000004,
4861BITS_36_5 = 0x00000005,
4862BITS_37_6 = 0x00000006,
4863BITS_38_7 = 0x00000007,
4864} DC_DMCUB_TIMER_WINDOW;
4865
4866/*
4867 * DC_DMCUB_INT_TYPE enum
4868 */
4869
4870typedef enum DC_DMCUB_INT_TYPE {
4871INT_LEVEL = 0x00000000,
4872INT_PULSE = 0x00000001,
4873} DC_DMCUB_INT_TYPE;
4874
4875/*******************************************************
4876 * RBBMIF Enums
4877 *******************************************************/
4878
4879/*
4880 * INVALID_REG_ACCESS_TYPE enum
4881 */
4882
4883typedef enum INVALID_REG_ACCESS_TYPE {
4884REG_UNALLOCATED_ADDR_WRITE = 0x00000000,
4885REG_UNALLOCATED_ADDR_READ = 0x00000001,
4886REG_VIRTUAL_WRITE = 0x00000002,
4887REG_VIRTUAL_READ = 0x00000003,
4888} INVALID_REG_ACCESS_TYPE;
4889
4890/*******************************************************
4891 * IHC Enums
4892 *******************************************************/
4893
4894/*
4895 * DMU_DC_GPU_TIMER_START_POSITION enum
4896 */
4897
4898typedef enum DMU_DC_GPU_TIMER_START_POSITION {
4899DMU_GPU_TIMER_START_0_END_27 = 0x00000000,
4900DMU_GPU_TIMER_START_1_END_28 = 0x00000001,
4901DMU_GPU_TIMER_START_2_END_29 = 0x00000002,
4902DMU_GPU_TIMER_START_3_END_30 = 0x00000003,
4903DMU_GPU_TIMER_START_4_END_31 = 0x00000004,
4904DMU_GPU_TIMER_START_6_END_33 = 0x00000005,
4905DMU_GPU_TIMER_START_8_END_35 = 0x00000006,
4906DMU_GPU_TIMER_START_10_END_37 = 0x00000007,
4907} DMU_DC_GPU_TIMER_START_POSITION;
4908
4909/*
4910 * DMU_DC_GPU_TIMER_READ_SELECT enum
4911 */
4912
4913typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
4914DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000,
4915DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001,
4916DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002,
4917DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003,
4918DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004,
4919DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005,
4920DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006,
4921DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007,
4922DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_8 = 0x00000008,
4923DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_9 = 0x00000009,
4924DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_10 = 0x0000000a,
4925DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_11 = 0x0000000b,
4926DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c,
4927DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d,
4928DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e,
4929DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f,
4930DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010,
4931DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011,
4932DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012,
4933DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013,
4934DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_STARTUP_20 = 0x00000014,
4935DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_STARTUP_21 = 0x00000015,
4936DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_STARTUP_22 = 0x00000016,
4937DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_STARTUP_23 = 0x00000017,
4938DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018,
4939DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019,
4940DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a,
4941DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b,
4942DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c,
4943DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d,
4944DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e,
4945DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f,
4946DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VSYNC_NOM_32 = 0x00000020,
4947DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VSYNC_NOM_33 = 0x00000021,
4948DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VSYNC_NOM_34 = 0x00000022,
4949DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VSYNC_NOM_35 = 0x00000023,
4950DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024,
4951DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025,
4952DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026,
4953DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027,
4954DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028,
4955DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029,
4956DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a,
4957DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b,
4958DMU_GPU_TIMER_READ_SELECT_LOWER_D5_VREADY_44 = 0x0000002c,
4959DMU_GPU_TIMER_READ_SELECT_UPPER_D5_VREADY_45 = 0x0000002d,
4960DMU_GPU_TIMER_READ_SELECT_LOWER_D6_VREADY_46 = 0x0000002e,
4961DMU_GPU_TIMER_READ_SELECT_UPPER_D6_VREADY_47 = 0x0000002f,
4962DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030,
4963DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031,
4964DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032,
4965DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033,
4966DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034,
4967DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035,
4968DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036,
4969DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037,
4970DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_56 = 0x00000038,
4971DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_57 = 0x00000039,
4972DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_58 = 0x0000003a,
4973DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_59 = 0x0000003b,
4974RESERVED_60 = 0x0000003c,
4975RESERVED_61 = 0x0000003d,
4976RESERVED_62 = 0x0000003e,
4977RESERVED_63 = 0x0000003f,
4978DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040,
4979DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041,
4980DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042,
4981DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043,
4982DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044,
4983DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045,
4984DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046,
4985DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047,
4986DMU_GPU_TIMER_READ_SELECT_LOWER_D5_V_UPDATE_NO_LOCK_72 = 0x00000048,
4987DMU_GPU_TIMER_READ_SELECT_UPPER_D5_V_UPDATE_NO_LOCK_73 = 0x00000049,
4988DMU_GPU_TIMER_READ_SELECT_LOWER_D6_V_UPDATE_NO_LOCK_74 = 0x0000004a,
4989DMU_GPU_TIMER_READ_SELECT_UPPER_D6_V_UPDATE_NO_LOCK_75 = 0x0000004b,
4990DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c,
4991DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d,
4992DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e,
4993DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f,
4994DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050,
4995DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051,
4996DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052,
4997DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053,
4998DMU_GPU_TIMER_READ_SELECT_LOWER_D5_FLIP_AWAY_84 = 0x00000054,
4999DMU_GPU_TIMER_READ_SELECT_UPPER_D5_FLIP_AWAY_85 = 0x00000055,
5000DMU_GPU_TIMER_READ_SELECT_LOWER_D6_FLIP_AWAY_86 = 0x00000056,
5001DMU_GPU_TIMER_READ_SELECT_UPPER_D6_FLIP_AWAY_87 = 0x00000057,
5002RESERVED_88 = 0x00000058,
5003RESERVED_89 = 0x00000059,
5004RESERVED_90 = 0x0000005a,
5005RESERVED_91 = 0x0000005b,
5006} DMU_DC_GPU_TIMER_READ_SELECT;
5007
5008/*
5009 * IHC_INTERRUPT_LINE_STATUS enum
5010 */
5011
5012typedef enum IHC_INTERRUPT_LINE_STATUS {
5013INTERRUPT_LINE_NOT_ASSERTED = 0x00000000,
5014INTERRUPT_LINE_ASSERTED = 0x00000001,
5015} IHC_INTERRUPT_LINE_STATUS;
5016
5017/*******************************************************
5018 * DMU_MISC Enums
5019 *******************************************************/
5020
5021/*
5022 * DMU_CLOCK_GATING_DISABLE enum
5023 */
5024
5025typedef enum DMU_CLOCK_GATING_DISABLE {
5026DMU_ENABLE_CLOCK_GATING = 0x00000000,
5027DMU_DISABLE_CLOCK_GATING = 0x00000001,
5028} DMU_CLOCK_GATING_DISABLE;
5029
5030/*
5031 * DMU_CLOCK_ON enum
5032 */
5033
5034typedef enum DMU_CLOCK_ON {
5035DMU_CLOCK_STATUS_ON = 0x00000000,
5036DMU_CLOCK_STATUS_OFF = 0x00000001,
5037} DMU_CLOCK_ON;
5038
5039/*
5040 * DC_SMU_INTERRUPT_ENABLE enum
5041 */
5042
5043typedef enum DC_SMU_INTERRUPT_ENABLE {
5044DISABLE_THE_INTERRUPT = 0x00000000,
5045ENABLE_THE_INTERRUPT = 0x00000001,
5046} DC_SMU_INTERRUPT_ENABLE;
5047
5048/*
5049 * STATIC_SCREEN_SMU_INTR enum
5050 */
5051
5052typedef enum STATIC_SCREEN_SMU_INTR {
5053STATIC_SCREEN_SMU_INTR_NOOP = 0x00000000,
5054SET_STATIC_SCREEN_SMU_INTR = 0x00000001,
5055} STATIC_SCREEN_SMU_INTR;
5056
5057/*******************************************************
5058 * DCCG Enums
5059 *******************************************************/
5060
5061/*
5062 * ENABLE enum
5063 */
5064
5065typedef enum ENABLE {
5066DISABLE_THE_FEATURE = 0x00000000,
5067ENABLE_THE_FEATURE = 0x00000001,
5068} ENABLE;
5069
5070/*
5071 * DS_HW_CAL_ENABLE enum
5072 */
5073
5074typedef enum DS_HW_CAL_ENABLE {
5075DS_HW_CAL_DIS = 0x00000000,
5076DS_HW_CAL_EN = 0x00000001,
5077} DS_HW_CAL_ENABLE;
5078
5079/*
5080 * ENABLE_CLOCK enum
5081 */
5082
5083typedef enum ENABLE_CLOCK {
5084DISABLE_THE_CLOCK = 0x00000000,
5085ENABLE_THE_CLOCK = 0x00000001,
5086} ENABLE_CLOCK;
5087
5088/*
5089 * CLEAR_SMU_INTR enum
5090 */
5091
5092typedef enum CLEAR_SMU_INTR {
5093SMU_INTR_STATUS_NOOP = 0x00000000,
5094SMU_INTR_STATUS_CLEAR = 0x00000001,
5095} CLEAR_SMU_INTR;
5096
5097/*
5098 * JITTER_REMOVE_DISABLE enum
5099 */
5100
5101typedef enum JITTER_REMOVE_DISABLE {
5102ENABLE_JITTER_REMOVAL = 0x00000000,
5103DISABLE_JITTER_REMOVAL = 0x00000001,
5104} JITTER_REMOVE_DISABLE;
5105
5106/*
5107 * DS_REF_SRC enum
5108 */
5109
5110typedef enum DS_REF_SRC {
5111DS_REF_IS_XTALIN = 0x00000000,
5112DS_REF_IS_EXT_GENLOCK = 0x00000001,
5113DS_REF_IS_PCIE = 0x00000002,
5114} DS_REF_SRC;
5115
5116/*
5117 * DISABLE_CLOCK_GATING enum
5118 */
5119
5120typedef enum DISABLE_CLOCK_GATING {
5121CLOCK_GATING_ENABLED = 0x00000000,
5122CLOCK_GATING_DISABLED = 0x00000001,
5123} DISABLE_CLOCK_GATING;
5124
5125/*
5126 * DISABLE_CLOCK_GATING_IN_DCO enum
5127 */
5128
5129typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5130CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
5131CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
5132} DISABLE_CLOCK_GATING_IN_DCO;
5133
5134/*
5135 * DCCG_DEEP_COLOR_CNTL enum
5136 */
5137
5138typedef enum DCCG_DEEP_COLOR_CNTL {
5139DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
5140DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
5141DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
5142DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
5143} DCCG_DEEP_COLOR_CNTL;
5144
5145/*
5146 * REFCLK_CLOCK_EN enum
5147 */
5148
5149typedef enum REFCLK_CLOCK_EN {
5150REFCLK_CLOCK_EN_XTALIN_CLK = 0x00000000,
5151REFCLK_CLOCK_EN_ALLOW_SRC_SEL = 0x00000001,
5152} REFCLK_CLOCK_EN;
5153
5154/*
5155 * REFCLK_SRC_SEL enum
5156 */
5157
5158typedef enum REFCLK_SRC_SEL {
5159REFCLK_SRC_SEL_PCIE_REFCLK = 0x00000000,
5160REFCLK_SRC_SEL_CPL_REFCLK = 0x00000001,
5161} REFCLK_SRC_SEL;
5162
5163/*
5164 * DPREFCLK_SRC_SEL enum
5165 */
5166
5167typedef enum DPREFCLK_SRC_SEL {
5168DPREFCLK_SRC_SEL_CK = 0x00000000,
5169DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
5170DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
5171DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
5172} DPREFCLK_SRC_SEL;
5173
5174/*
5175 * XTAL_REF_SEL enum
5176 */
5177
5178typedef enum XTAL_REF_SEL {
5179XTAL_REF_SEL_1X = 0x00000000,
5180XTAL_REF_SEL_2X = 0x00000001,
5181} XTAL_REF_SEL;
5182
5183/*
5184 * XTAL_REF_CLOCK_SOURCE_SEL enum
5185 */
5186
5187typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5188XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
5189XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001,
5190} XTAL_REF_CLOCK_SOURCE_SEL;
5191
5192/*
5193 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5194 */
5195
5196typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5197MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5198MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5199} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5200
5201/*
5202 * ALLOW_SR_ON_TRANS_REQ enum
5203 */
5204
5205typedef enum ALLOW_SR_ON_TRANS_REQ {
5206ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
5207ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
5208} ALLOW_SR_ON_TRANS_REQ;
5209
5210/*
5211 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5212 */
5213
5214typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5215MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5216MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5217} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5218
5219/*
5220 * PIPE_PIXEL_RATE_SOURCE enum
5221 */
5222
5223typedef enum PIPE_PIXEL_RATE_SOURCE {
5224PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
5225PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
5226PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
5227} PIPE_PIXEL_RATE_SOURCE;
5228
5229/*
5230 * TEST_CLK_DIV_SEL enum
5231 */
5232
5233typedef enum TEST_CLK_DIV_SEL {
5234NO_DIV = 0x00000000,
5235DIV_2 = 0x00000001,
5236DIV_4 = 0x00000002,
5237DIV_8 = 0x00000003,
5238} TEST_CLK_DIV_SEL;
5239
5240/*
5241 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5242 */
5243
5244typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5245PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
5246PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
5247PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
5248PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
5249PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYE = 0x00000004,
5250PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYF = 0x00000005,
5251PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000006,
5252} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
5253
5254/*
5255 * PIPE_PIXEL_RATE_PLL_SOURCE enum
5256 */
5257
5258typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5259PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
5260PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
5261} PIPE_PIXEL_RATE_PLL_SOURCE;
5262
5263/*
5264 * DP_DTO_DS_DISABLE enum
5265 */
5266
5267typedef enum DP_DTO_DS_DISABLE {
5268DP_DTO_DESPREAD_DISABLE = 0x00000000,
5269DP_DTO_DESPREAD_ENABLE = 0x00000001,
5270} DP_DTO_DS_DISABLE;
5271
5272/*
5273 * OTG_ADD_PIXEL enum
5274 */
5275
5276typedef enum OTG_ADD_PIXEL {
5277OTG_ADD_PIXEL_NOOP = 0x00000000,
5278OTG_ADD_PIXEL_FORCE = 0x00000001,
5279} OTG_ADD_PIXEL;
5280
5281/*
5282 * OTG_DROP_PIXEL enum
5283 */
5284
5285typedef enum OTG_DROP_PIXEL {
5286OTG_DROP_PIXEL_NOOP = 0x00000000,
5287OTG_DROP_PIXEL_FORCE = 0x00000001,
5288} OTG_DROP_PIXEL;
5289
5290/*
5291 * SYMCLK_FE_FORCE_EN enum
5292 */
5293
5294typedef enum SYMCLK_FE_FORCE_EN {
5295SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000,
5296SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001,
5297} SYMCLK_FE_FORCE_EN;
5298
5299/*
5300 * SYMCLK_FE_FORCE_SRC enum
5301 */
5302
5303typedef enum SYMCLK_FE_FORCE_SRC {
5304SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000,
5305SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001,
5306SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002,
5307SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003,
5308SYMCLK_FE_FORCE_SRC_UNIPHYE = 0x00000004,
5309SYMCLK_FE_FORCE_SRC_UNIPHYF = 0x00000005,
5310SYMCLK_FE_FORCE_SRC_RESERVED = 0x00000006,
5311} SYMCLK_FE_FORCE_SRC;
5312
5313/*
5314 * DVOACLK_COARSE_SKEW_CNTL enum
5315 */
5316
5317typedef enum DVOACLK_COARSE_SKEW_CNTL {
5318DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
5319DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
5320DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
5321DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
5322DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004,
5323DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005,
5324DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006,
5325DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007,
5326DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008,
5327DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009,
5328DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a,
5329DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b,
5330DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c,
5331DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d,
5332DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e,
5333DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f,
5334DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010,
5335DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011,
5336DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012,
5337DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013,
5338DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014,
5339DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015,
5340DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016,
5341DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017,
5342DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018,
5343DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019,
5344DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a,
5345DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b,
5346DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c,
5347DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d,
5348DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e,
5349} DVOACLK_COARSE_SKEW_CNTL;
5350
5351/*
5352 * DVOACLK_FINE_SKEW_CNTL enum
5353 */
5354
5355typedef enum DVOACLK_FINE_SKEW_CNTL {
5356DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
5357DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
5358DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
5359DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
5360DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004,
5361DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005,
5362DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006,
5363DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007,
5364} DVOACLK_FINE_SKEW_CNTL;
5365
5366/*
5367 * DVOACLKD_IN_PHASE enum
5368 */
5369
5370typedef enum DVOACLKD_IN_PHASE {
5371DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5372DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5373} DVOACLKD_IN_PHASE;
5374
5375/*
5376 * DVOACLKC_IN_PHASE enum
5377 */
5378
5379typedef enum DVOACLKC_IN_PHASE {
5380DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5381DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5382} DVOACLKC_IN_PHASE;
5383
5384/*
5385 * DVOACLKC_MVP_IN_PHASE enum
5386 */
5387
5388typedef enum DVOACLKC_MVP_IN_PHASE {
5389DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5390DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5391} DVOACLKC_MVP_IN_PHASE;
5392
5393/*
5394 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
5395 */
5396
5397typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
5398DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
5399DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001,
5400} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
5401
5402/*
5403 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5404 */
5405
5406typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5407DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000,
5408DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001,
5409DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002,
5410DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003,
5411DCCG_AUDIO_DTO0_SOURCE_SEL_OTG4 = 0x00000004,
5412DCCG_AUDIO_DTO0_SOURCE_SEL_OTG5 = 0x00000005,
5413DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000006,
5414} DCCG_AUDIO_DTO0_SOURCE_SEL;
5415
5416/*
5417 * DCCG_AUDIO_DTO_SEL enum
5418 */
5419
5420typedef enum DCCG_AUDIO_DTO_SEL {
5421DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
5422DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
5423DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
5424} DCCG_AUDIO_DTO_SEL;
5425
5426/*
5427 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5428 */
5429
5430typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5431DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
5432DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK1 = 0x00000001,
5433} DCCG_AUDIO_DTO2_SOURCE_SEL;
5434
5435/*
5436 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5437 */
5438
5439typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5440DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
5441DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
5442} DCCG_AUDIO_DTO_USE_512FBR_DTO;
5443
5444/*
5445 * DISPCLK_FREQ_RAMP_DONE enum
5446 */
5447
5448typedef enum DISPCLK_FREQ_RAMP_DONE {
5449DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
5450DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
5451} DISPCLK_FREQ_RAMP_DONE;
5452
5453/*
5454 * DCCG_FIFO_ERRDET_RESET enum
5455 */
5456
5457typedef enum DCCG_FIFO_ERRDET_RESET {
5458DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
5459DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
5460} DCCG_FIFO_ERRDET_RESET;
5461
5462/*
5463 * DCCG_FIFO_ERRDET_STATE enum
5464 */
5465
5466typedef enum DCCG_FIFO_ERRDET_STATE {
5467DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000,
5468DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001,
5469} DCCG_FIFO_ERRDET_STATE;
5470
5471/*
5472 * DCCG_FIFO_ERRDET_OVR_EN enum
5473 */
5474
5475typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5476DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
5477DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
5478} DCCG_FIFO_ERRDET_OVR_EN;
5479
5480/*
5481 * DISPCLK_CHG_FWD_CORR_DISABLE enum
5482 */
5483
5484typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5485DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
5486DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
5487} DISPCLK_CHG_FWD_CORR_DISABLE;
5488
5489/*
5490 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5491 */
5492
5493typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5494DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
5495DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
5496} DC_MEM_GLOBAL_PWR_REQ_DIS;
5497
5498/*
5499 * DCCG_PERF_RUN enum
5500 */
5501
5502typedef enum DCCG_PERF_RUN {
5503DCCG_PERF_RUN_NOOP = 0x00000000,
5504DCCG_PERF_RUN_START = 0x00000001,
5505} DCCG_PERF_RUN;
5506
5507/*
5508 * DCCG_PERF_MODE_VSYNC enum
5509 */
5510
5511typedef enum DCCG_PERF_MODE_VSYNC {
5512DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
5513DCCG_PERF_MODE_VSYNC_START = 0x00000001,
5514} DCCG_PERF_MODE_VSYNC;
5515
5516/*
5517 * DCCG_PERF_MODE_HSYNC enum
5518 */
5519
5520typedef enum DCCG_PERF_MODE_HSYNC {
5521DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
5522DCCG_PERF_MODE_HSYNC_START = 0x00000001,
5523} DCCG_PERF_MODE_HSYNC;
5524
5525/*
5526 * DCCG_PERF_OTG_SELECT enum
5527 */
5528
5529typedef enum DCCG_PERF_OTG_SELECT {
5530DCCG_PERF_SEL_OTG0 = 0x00000000,
5531DCCG_PERF_SEL_OTG1 = 0x00000001,
5532DCCG_PERF_SEL_OTG2 = 0x00000002,
5533DCCG_PERF_SEL_OTG3 = 0x00000003,
5534DCCG_PERF_SEL_OTG4 = 0x00000004,
5535DCCG_PERF_SEL_OTG5 = 0x00000005,
5536DCCG_PERF_SEL_RESERVED = 0x00000006,
5537} DCCG_PERF_OTG_SELECT;
5538
5539/*
5540 * CLOCK_BRANCH_SOFT_RESET enum
5541 */
5542
5543typedef enum CLOCK_BRANCH_SOFT_RESET {
5544CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
5545CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
5546} CLOCK_BRANCH_SOFT_RESET;
5547
5548/*
5549 * PLL_CFG_IF_SOFT_RESET enum
5550 */
5551
5552typedef enum PLL_CFG_IF_SOFT_RESET {
5553PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
5554PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
5555} PLL_CFG_IF_SOFT_RESET;
5556
5557/*
5558 * DVO_ENABLE_RST enum
5559 */
5560
5561typedef enum DVO_ENABLE_RST {
5562DVO_ENABLE_RST_DISABLE = 0x00000000,
5563DVO_ENABLE_RST_ENABLE = 0x00000001,
5564} DVO_ENABLE_RST;
5565
5566/*
5567 * DS_JITTER_COUNT_SRC_SEL enum
5568 */
5569
5570typedef enum DS_JITTER_COUNT_SRC_SEL {
5571DS_JITTER_COUNT_SRC_SEL0 = 0x00000000,
5572DS_JITTER_COUNT_SRC_SEL1 = 0x00000001,
5573} DS_JITTER_COUNT_SRC_SEL;
5574
5575/*
5576 * DIO_FIFO_ERROR enum
5577 */
5578
5579typedef enum DIO_FIFO_ERROR {
5580DIO_FIFO_ERROR_00 = 0x00000000,
5581DIO_FIFO_ERROR_01 = 0x00000001,
5582DIO_FIFO_ERROR_10 = 0x00000002,
5583DIO_FIFO_ERROR_11 = 0x00000003,
5584} DIO_FIFO_ERROR;
5585
5586/*
5587 * VSYNC_CNT_REFCLK_SEL enum
5588 */
5589
5590typedef enum VSYNC_CNT_REFCLK_SEL {
5591VSYNC_CNT_REFCLK_SEL_0 = 0x00000000,
5592VSYNC_CNT_REFCLK_SEL_1 = 0x00000001,
5593} VSYNC_CNT_REFCLK_SEL;
5594
5595/*
5596 * VSYNC_CNT_RESET_SEL enum
5597 */
5598
5599typedef enum VSYNC_CNT_RESET_SEL {
5600VSYNC_CNT_RESET_SEL_0 = 0x00000000,
5601VSYNC_CNT_RESET_SEL_1 = 0x00000001,
5602} VSYNC_CNT_RESET_SEL;
5603
5604/*
5605 * VSYNC_CNT_LATCH_MASK enum
5606 */
5607
5608typedef enum VSYNC_CNT_LATCH_MASK {
5609VSYNC_CNT_LATCH_MASK_0 = 0x00000000,
5610VSYNC_CNT_LATCH_MASK_1 = 0x00000001,
5611} VSYNC_CNT_LATCH_MASK;
5612
5613/*******************************************************
5614 * HPD Enums
5615 *******************************************************/
5616
5617/*
5618 * HPD_INT_CONTROL_ACK enum
5619 */
5620
5621typedef enum HPD_INT_CONTROL_ACK {
5622HPD_INT_CONTROL_ACK_0 = 0x00000000,
5623HPD_INT_CONTROL_ACK_1 = 0x00000001,
5624} HPD_INT_CONTROL_ACK;
5625
5626/*
5627 * HPD_INT_CONTROL_POLARITY enum
5628 */
5629
5630typedef enum HPD_INT_CONTROL_POLARITY {
5631HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
5632HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
5633} HPD_INT_CONTROL_POLARITY;
5634
5635/*
5636 * HPD_INT_CONTROL_RX_INT_ACK enum
5637 */
5638
5639typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5640HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
5641HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
5642} HPD_INT_CONTROL_RX_INT_ACK;
5643
5644/*******************************************************
5645 * DP Enums
5646 *******************************************************/
5647
5648/*
5649 * DP_MSO_NUM_OF_SST_LINKS enum
5650 */
5651
5652typedef enum DP_MSO_NUM_OF_SST_LINKS {
5653DP_MSO_ONE_SSTLINK = 0x00000000,
5654DP_MSO_TWO_SSTLINK = 0x00000001,
5655DP_MSO_FOUR_SSTLINK = 0x00000002,
5656} DP_MSO_NUM_OF_SST_LINKS;
5657
5658/*
5659 * DP_SYNC_POLARITY enum
5660 */
5661
5662typedef enum DP_SYNC_POLARITY {
5663DP_SYNC_POLARITY_ACTIVE_HIGH = 0x00000000,
5664DP_SYNC_POLARITY_ACTIVE_LOW = 0x00000001,
5665} DP_SYNC_POLARITY;
5666
5667/*
5668 * DP_COMBINE_PIXEL_NUM enum
5669 */
5670
5671typedef enum DP_COMBINE_PIXEL_NUM {
5672DP_COMBINE_ONE_PIXEL = 0x00000000,
5673DP_COMBINE_TWO_PIXEL = 0x00000001,
5674DP_COMBINE_FOUR_PIXEL = 0x00000002,
5675} DP_COMBINE_PIXEL_NUM;
5676
5677/*
5678 * DP_LINK_TRAINING_COMPLETE enum
5679 */
5680
5681typedef enum DP_LINK_TRAINING_COMPLETE {
5682DP_LINK_TRAINING_NOT_COMPLETE = 0x00000000,
5683DP_LINK_TRAINING_ALREADY_COMPLETE = 0x00000001,
5684} DP_LINK_TRAINING_COMPLETE;
5685
5686/*
5687 * DP_EMBEDDED_PANEL_MODE enum
5688 */
5689
5690typedef enum DP_EMBEDDED_PANEL_MODE {
5691DP_EXTERNAL_PANEL = 0x00000000,
5692DP_EMBEDDED_PANEL = 0x00000001,
5693} DP_EMBEDDED_PANEL_MODE;
5694
5695/*
5696 * DP_PIXEL_ENCODING enum
5697 */
5698
5699typedef enum DP_PIXEL_ENCODING {
5700DP_PIXEL_ENCODING_RGB444 = 0x00000000,
5701DP_PIXEL_ENCODING_YCBCR422 = 0x00000001,
5702DP_PIXEL_ENCODING_YCBCR444 = 0x00000002,
5703DP_PIXEL_ENCODING_RGB_WIDE_GAMUT = 0x00000003,
5704DP_PIXEL_ENCODING_Y_ONLY = 0x00000004,
5705DP_PIXEL_ENCODING_YCBCR420 = 0x00000005,
5706DP_PIXEL_ENCODING_RESERVED = 0x00000006,
5707} DP_PIXEL_ENCODING;
5708
5709/*
5710 * DP_COMPONENT_DEPTH enum
5711 */
5712
5713typedef enum DP_COMPONENT_DEPTH {
5714DP_COMPONENT_DEPTH_6BPC = 0x00000000,
5715DP_COMPONENT_DEPTH_8BPC = 0x00000001,
5716DP_COMPONENT_DEPTH_10BPC = 0x00000002,
5717DP_COMPONENT_DEPTH_12BPC = 0x00000003,
5718DP_COMPONENT_DEPTH_16BPC_RESERVED = 0x00000004,
5719DP_COMPONENT_DEPTH_RESERVED = 0x00000005,
5720} DP_COMPONENT_DEPTH;
5721
5722/*
5723 * DP_UDI_LANES enum
5724 */
5725
5726typedef enum DP_UDI_LANES {
5727DP_UDI_1_LANE = 0x00000000,
5728DP_UDI_2_LANES = 0x00000001,
5729DP_UDI_LANES_RESERVED = 0x00000002,
5730DP_UDI_4_LANES = 0x00000003,
5731} DP_UDI_LANES;
5732
5733/*
5734 * DP_VID_STREAM_DIS_DEFER enum
5735 */
5736
5737typedef enum DP_VID_STREAM_DIS_DEFER {
5738DP_VID_STREAM_DIS_NO_DEFER = 0x00000000,
5739DP_VID_STREAM_DIS_DEFER_TO_HBLANK = 0x00000001,
5740DP_VID_STREAM_DIS_DEFER_TO_VBLANK = 0x00000002,
5741} DP_VID_STREAM_DIS_DEFER;
5742
5743/*
5744 * DP_STEER_OVERFLOW_ACK enum
5745 */
5746
5747typedef enum DP_STEER_OVERFLOW_ACK {
5748DP_STEER_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
5749DP_STEER_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
5750} DP_STEER_OVERFLOW_ACK;
5751
5752/*
5753 * DP_STEER_OVERFLOW_MASK enum
5754 */
5755
5756typedef enum DP_STEER_OVERFLOW_MASK {
5757DP_STEER_OVERFLOW_MASKED = 0x00000000,
5758DP_STEER_OVERFLOW_UNMASK = 0x00000001,
5759} DP_STEER_OVERFLOW_MASK;
5760
5761/*
5762 * DP_TU_OVERFLOW_ACK enum
5763 */
5764
5765typedef enum DP_TU_OVERFLOW_ACK {
5766DP_TU_OVERFLOW_ACK_NO_EFFECT = 0x00000000,
5767DP_TU_OVERFLOW_ACK_CLR_INTERRUPT = 0x00000001,
5768} DP_TU_OVERFLOW_ACK;
5769
5770/*
5771 * DP_VID_M_N_DOUBLE_BUFFER_MODE enum
5772 */
5773
5774typedef enum DP_VID_M_N_DOUBLE_BUFFER_MODE {
5775DP_VID_M_N_DOUBLE_BUFFER_AFTER_VID_M_UPDATE = 0x00000000,
5776DP_VID_M_N_DOUBLE_BUFFER_AT_FRAME_START = 0x00000001,
5777} DP_VID_M_N_DOUBLE_BUFFER_MODE;
5778
5779/*
5780 * DP_VID_M_N_GEN_EN enum
5781 */
5782
5783typedef enum DP_VID_M_N_GEN_EN {
5784DP_VID_M_N_PROGRAMMED_VIA_REG = 0x00000000,
5785DP_VID_M_N_CALC_AUTO = 0x00000001,
5786} DP_VID_M_N_GEN_EN;
5787
5788/*
5789 * DP_VID_N_MUL enum
5790 */
5791
5792typedef enum DP_VID_N_MUL {
5793DP_VID_M_1X_INPUT_PIXEL_RATE = 0x00000000,
5794DP_VID_M_2X_INPUT_PIXEL_RATE = 0x00000001,
5795DP_VID_M_4X_INPUT_PIXEL_RATE = 0x00000002,
5796DP_VID_M_8X_INPUT_PIXEL_RATE = 0x00000003,
5797} DP_VID_N_MUL;
5798
5799/*
5800 * DP_VID_ENHANCED_FRAME_MODE enum
5801 */
5802
5803typedef enum DP_VID_ENHANCED_FRAME_MODE {
5804VID_NORMAL_FRAME_MODE = 0x00000000,
5805VID_ENHANCED_MODE = 0x00000001,
5806} DP_VID_ENHANCED_FRAME_MODE;
5807
5808/*
5809 * DP_VID_VBID_FIELD_POL enum
5810 */
5811
5812typedef enum DP_VID_VBID_FIELD_POL {
5813DP_VID_VBID_FIELD_POL_NORMAL = 0x00000000,
5814DP_VID_VBID_FIELD_POL_INV = 0x00000001,
5815} DP_VID_VBID_FIELD_POL;
5816
5817/*
5818 * DP_VID_STREAM_DISABLE_ACK enum
5819 */
5820
5821typedef enum DP_VID_STREAM_DISABLE_ACK {
5822ID_STREAM_DISABLE_NO_ACK = 0x00000000,
5823ID_STREAM_DISABLE_ACKED = 0x00000001,
5824} DP_VID_STREAM_DISABLE_ACK;
5825
5826/*
5827 * DP_VID_STREAM_DISABLE_MASK enum
5828 */
5829
5830typedef enum DP_VID_STREAM_DISABLE_MASK {
5831VID_STREAM_DISABLE_MASKED = 0x00000000,
5832VID_STREAM_DISABLE_UNMASK = 0x00000001,
5833} DP_VID_STREAM_DISABLE_MASK;
5834
5835/*
5836 * DPHY_ATEST_SEL_LANE0 enum
5837 */
5838
5839typedef enum DPHY_ATEST_SEL_LANE0 {
5840DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
5841DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
5842} DPHY_ATEST_SEL_LANE0;
5843
5844/*
5845 * DPHY_ATEST_SEL_LANE1 enum
5846 */
5847
5848typedef enum DPHY_ATEST_SEL_LANE1 {
5849DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
5850DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
5851} DPHY_ATEST_SEL_LANE1;
5852
5853/*
5854 * DPHY_ATEST_SEL_LANE2 enum
5855 */
5856
5857typedef enum DPHY_ATEST_SEL_LANE2 {
5858DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
5859DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
5860} DPHY_ATEST_SEL_LANE2;
5861
5862/*
5863 * DPHY_ATEST_SEL_LANE3 enum
5864 */
5865
5866typedef enum DPHY_ATEST_SEL_LANE3 {
5867DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
5868DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
5869} DPHY_ATEST_SEL_LANE3;
5870
5871/*
5872 * DPHY_BYPASS enum
5873 */
5874
5875typedef enum DPHY_BYPASS {
5876DPHY_8B10B_OUTPUT = 0x00000000,
5877DPHY_DBG_OUTPUT = 0x00000001,
5878} DPHY_BYPASS;
5879
5880/*
5881 * DPHY_SKEW_BYPASS enum
5882 */
5883
5884typedef enum DPHY_SKEW_BYPASS {
5885DPHY_WITH_SKEW = 0x00000000,
5886DPHY_NO_SKEW = 0x00000001,
5887} DPHY_SKEW_BYPASS;
5888
5889/*
5890 * DPHY_TRAINING_PATTERN_SEL enum
5891 */
5892
5893typedef enum DPHY_TRAINING_PATTERN_SEL {
5894DPHY_TRAINING_PATTERN_1 = 0x00000000,
5895DPHY_TRAINING_PATTERN_2 = 0x00000001,
5896DPHY_TRAINING_PATTERN_3 = 0x00000002,
5897DPHY_TRAINING_PATTERN_4 = 0x00000003,
5898} DPHY_TRAINING_PATTERN_SEL;
5899
5900/*
5901 * DPHY_8B10B_RESET enum
5902 */
5903
5904typedef enum DPHY_8B10B_RESET {
5905DPHY_8B10B_NOT_RESET = 0x00000000,
5906DPHY_8B10B_RESETET = 0x00000001,
5907} DPHY_8B10B_RESET;
5908
5909/*
5910 * DP_DPHY_8B10B_EXT_DISP enum
5911 */
5912
5913typedef enum DP_DPHY_8B10B_EXT_DISP {
5914DP_DPHY_8B10B_EXT_DISP_ZERO = 0x00000000,
5915DP_DPHY_8B10B_EXT_DISP_ONE = 0x00000001,
5916} DP_DPHY_8B10B_EXT_DISP;
5917
5918/*
5919 * DPHY_8B10B_CUR_DISP enum
5920 */
5921
5922typedef enum DPHY_8B10B_CUR_DISP {
5923DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
5924DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
5925} DPHY_8B10B_CUR_DISP;
5926
5927/*
5928 * DPHY_PRBS_EN enum
5929 */
5930
5931typedef enum DPHY_PRBS_EN {
5932DPHY_PRBS_DISABLE = 0x00000000,
5933DPHY_PRBS_ENABLE = 0x00000001,
5934} DPHY_PRBS_EN;
5935
5936/*
5937 * DPHY_PRBS_SEL enum
5938 */
5939
5940typedef enum DPHY_PRBS_SEL {
5941DPHY_PRBS7_SELECTED = 0x00000000,
5942DPHY_PRBS23_SELECTED = 0x00000001,
5943DPHY_PRBS11_SELECTED = 0x00000002,
5944} DPHY_PRBS_SEL;
5945
5946/*
5947 * DPHY_FEC_ENABLE enum
5948 */
5949
5950typedef enum DPHY_FEC_ENABLE {
5951DPHY_FEC_DISABLED = 0x00000000,
5952DPHY_FEC_ENABLED = 0x00000001,
5953} DPHY_FEC_ENABLE;
5954
5955/*
5956 * FEC_ACTIVE_STATUS enum
5957 */
5958
5959typedef enum FEC_ACTIVE_STATUS {
5960DPHY_FEC_NOT_ACTIVE = 0x00000000,
5961DPHY_FEC_ACTIVE = 0x00000001,
5962} FEC_ACTIVE_STATUS;
5963
5964/*
5965 * DPHY_FEC_READY enum
5966 */
5967
5968typedef enum DPHY_FEC_READY {
5969DPHY_FEC_READY_EN = 0x00000000,
5970DPHY_FEC_READY_DIS = 0x00000001,
5971} DPHY_FEC_READY;
5972
5973/*
5974 * DPHY_LOAD_BS_COUNT_START enum
5975 */
5976
5977typedef enum DPHY_LOAD_BS_COUNT_START {
5978DPHY_LOAD_BS_COUNT_STARTED = 0x00000000,
5979DPHY_LOAD_BS_COUNT_NOT_STARTED = 0x00000001,
5980} DPHY_LOAD_BS_COUNT_START;
5981
5982/*
5983 * DPHY_CRC_EN enum
5984 */
5985
5986typedef enum DPHY_CRC_EN {
5987DPHY_CRC_DISABLED = 0x00000000,
5988DPHY_CRC_ENABLED = 0x00000001,
5989} DPHY_CRC_EN;
5990
5991/*
5992 * DPHY_CRC_CONT_EN enum
5993 */
5994
5995typedef enum DPHY_CRC_CONT_EN {
5996DPHY_CRC_ONE_SHOT = 0x00000000,
5997DPHY_CRC_CONTINUOUS = 0x00000001,
5998} DPHY_CRC_CONT_EN;
5999
6000/*
6001 * DPHY_CRC_FIELD enum
6002 */
6003
6004typedef enum DPHY_CRC_FIELD {
6005DPHY_CRC_START_FROM_TOP_FIELD = 0x00000000,
6006DPHY_CRC_START_FROM_BOTTOM_FIELD = 0x00000001,
6007} DPHY_CRC_FIELD;
6008
6009/*
6010 * DPHY_CRC_SEL enum
6011 */
6012
6013typedef enum DPHY_CRC_SEL {
6014DPHY_CRC_LANE0_SELECTED = 0x00000000,
6015DPHY_CRC_LANE1_SELECTED = 0x00000001,
6016DPHY_CRC_LANE2_SELECTED = 0x00000002,
6017DPHY_CRC_LANE3_SELECTED = 0x00000003,
6018} DPHY_CRC_SEL;
6019
6020/*
6021 * DPHY_RX_FAST_TRAINING_CAPABLE enum
6022 */
6023
6024typedef enum DPHY_RX_FAST_TRAINING_CAPABLE {
6025DPHY_FAST_TRAINING_NOT_CAPABLE_0 = 0x00000000,
6026DPHY_FAST_TRAINING_CAPABLE = 0x00000001,
6027} DPHY_RX_FAST_TRAINING_CAPABLE;
6028
6029/*
6030 * DP_SEC_COLLISION_ACK enum
6031 */
6032
6033typedef enum DP_SEC_COLLISION_ACK {
6034DP_SEC_COLLISION_ACK_NO_EFFECT = 0x00000000,
6035DP_SEC_COLLISION_ACK_CLR_FLAG = 0x00000001,
6036} DP_SEC_COLLISION_ACK;
6037
6038/*
6039 * DP_SEC_AUDIO_MUTE enum
6040 */
6041
6042typedef enum DP_SEC_AUDIO_MUTE {
6043DP_SEC_AUDIO_MUTE_HW_CTRL = 0x00000000,
6044DP_SEC_AUDIO_MUTE_SW_CTRL = 0x00000001,
6045} DP_SEC_AUDIO_MUTE;
6046
6047/*
6048 * DP_SEC_TIMESTAMP_MODE enum
6049 */
6050
6051typedef enum DP_SEC_TIMESTAMP_MODE {
6052DP_SEC_TIMESTAMP_PROGRAMMABLE_MODE = 0x00000000,
6053DP_SEC_TIMESTAMP_AUTO_CALC_MODE = 0x00000001,
6054} DP_SEC_TIMESTAMP_MODE;
6055
6056/*
6057 * DP_SEC_ASP_PRIORITY enum
6058 */
6059
6060typedef enum DP_SEC_ASP_PRIORITY {
6061DP_SEC_ASP_LOW_PRIORITY = 0x00000000,
6062DP_SEC_ASP_HIGH_PRIORITY = 0x00000001,
6063} DP_SEC_ASP_PRIORITY;
6064
6065/*
6066 * DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE enum
6067 */
6068
6069typedef enum DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE {
6070DP_SEC_ASP_CHANNEL_COUNT_FROM_AZ = 0x00000000,
6071DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE_ENABLED = 0x00000001,
6072} DP_SEC_ASP_CHANNEL_COUNT_OVERRIDE;
6073
6074/*
6075 * DP_MSE_SAT_UPDATE_ACT enum
6076 */
6077
6078typedef enum DP_MSE_SAT_UPDATE_ACT {
6079DP_MSE_SAT_UPDATE_NO_ACTION = 0x00000000,
6080DP_MSE_SAT_UPDATE_WITH_TRIGGER = 0x00000001,
6081DP_MSE_SAT_UPDATE_WITHOUT_TRIGGER = 0x00000002,
6082} DP_MSE_SAT_UPDATE_ACT;
6083
6084/*
6085 * DP_MSE_LINK_LINE enum
6086 */
6087
6088typedef enum DP_MSE_LINK_LINE {
6089DP_MSE_LINK_LINE_32_MTP_LONG = 0x00000000,
6090DP_MSE_LINK_LINE_64_MTP_LONG = 0x00000001,
6091DP_MSE_LINK_LINE_128_MTP_LONG = 0x00000002,
6092DP_MSE_LINK_LINE_256_MTP_LONG = 0x00000003,
6093} DP_MSE_LINK_LINE;
6094
6095/*
6096 * DP_MSE_BLANK_CODE enum
6097 */
6098
6099typedef enum DP_MSE_BLANK_CODE {
6100DP_MSE_BLANK_CODE_SF_FILLED = 0x00000000,
6101DP_MSE_BLANK_CODE_ZERO_FILLED = 0x00000001,
6102} DP_MSE_BLANK_CODE;
6103
6104/*
6105 * DP_MSE_TIMESTAMP_MODE enum
6106 */
6107
6108typedef enum DP_MSE_TIMESTAMP_MODE {
6109DP_MSE_TIMESTAMP_CALC_BASED_ON_LINK_RATE = 0x00000000,
6110DP_MSE_TIMESTAMP_CALC_BASED_ON_VC_RATE = 0x00000001,
6111} DP_MSE_TIMESTAMP_MODE;
6112
6113/*
6114 * DP_MSE_ZERO_ENCODER enum
6115 */
6116
6117typedef enum DP_MSE_ZERO_ENCODER {
6118DP_MSE_NOT_ZERO_FE_ENCODER = 0x00000000,
6119DP_MSE_ZERO_FE_ENCODER = 0x00000001,
6120} DP_MSE_ZERO_ENCODER;
6121
6122/*
6123 * DP_DPHY_HBR2_PATTERN_CONTROL_MODE enum
6124 */
6125
6126typedef enum DP_DPHY_HBR2_PATTERN_CONTROL_MODE {
6127DP_DPHY_HBR2_PASS_THROUGH = 0x00000000,
6128DP_DPHY_HBR2_PATTERN_1 = 0x00000001,
6129DP_DPHY_HBR2_PATTERN_2_NEG = 0x00000002,
6130DP_DPHY_HBR2_PATTERN_3 = 0x00000003,
6131DP_DPHY_HBR2_PATTERN_2_POS = 0x00000006,
6132} DP_DPHY_HBR2_PATTERN_CONTROL_MODE;
6133
6134/*
6135 * DPHY_CRC_MST_PHASE_ERROR_ACK enum
6136 */
6137
6138typedef enum DPHY_CRC_MST_PHASE_ERROR_ACK {
6139DPHY_CRC_MST_PHASE_ERROR_NO_ACK = 0x00000000,
6140DPHY_CRC_MST_PHASE_ERROR_ACKED = 0x00000001,
6141} DPHY_CRC_MST_PHASE_ERROR_ACK;
6142
6143/*
6144 * DPHY_SW_FAST_TRAINING_START enum
6145 */
6146
6147typedef enum DPHY_SW_FAST_TRAINING_START {
6148DPHY_SW_FAST_TRAINING_NOT_STARTED = 0x00000000,
6149DPHY_SW_FAST_TRAINING_STARTED = 0x00000001,
6150} DPHY_SW_FAST_TRAINING_START;
6151
6152/*
6153 * DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN enum
6154 */
6155
6156typedef enum DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN {
6157DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_DISABLED = 0x00000000,
6158DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_ENABLED = 0x00000001,
6159} DP_DPHY_FAST_TRAINING_VBLANK_EDGE_DETECT_EN;
6160
6161/*
6162 * DP_DPHY_FAST_TRAINING_COMPLETE_MASK enum
6163 */
6164
6165typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_MASK {
6166DP_DPHY_FAST_TRAINING_COMPLETE_MASKED = 0x00000000,
6167DP_DPHY_FAST_TRAINING_COMPLETE_NOT_MASKED = 0x00000001,
6168} DP_DPHY_FAST_TRAINING_COMPLETE_MASK;
6169
6170/*
6171 * DP_DPHY_FAST_TRAINING_COMPLETE_ACK enum
6172 */
6173
6174typedef enum DP_DPHY_FAST_TRAINING_COMPLETE_ACK {
6175DP_DPHY_FAST_TRAINING_COMPLETE_NOT_ACKED = 0x00000000,
6176DP_DPHY_FAST_TRAINING_COMPLETE_ACKED = 0x00000001,
6177} DP_DPHY_FAST_TRAINING_COMPLETE_ACK;
6178
6179/*
6180 * DP_MSA_V_TIMING_OVERRIDE_EN enum
6181 */
6182
6183typedef enum DP_MSA_V_TIMING_OVERRIDE_EN {
6184MSA_V_TIMING_OVERRIDE_DISABLED = 0x00000000,
6185MSA_V_TIMING_OVERRIDE_ENABLED = 0x00000001,
6186} DP_MSA_V_TIMING_OVERRIDE_EN;
6187
6188/*
6189 * DP_SEC_GSP0_PRIORITY enum
6190 */
6191
6192typedef enum DP_SEC_GSP0_PRIORITY {
6193SEC_GSP0_PRIORITY_LOW = 0x00000000,
6194SEC_GSP0_PRIORITY_HIGH = 0x00000001,
6195} DP_SEC_GSP0_PRIORITY;
6196
6197/*
6198 * DP_SEC_GSP_SEND enum
6199 */
6200
6201typedef enum DP_SEC_GSP_SEND {
6202NOT_SENT = 0x00000000,
6203FORCE_SENT = 0x00000001,
6204} DP_SEC_GSP_SEND;
6205
6206/*
6207 * DP_SEC_GSP_SEND_ANY_LINE enum
6208 */
6209
6210typedef enum DP_SEC_GSP_SEND_ANY_LINE {
6211SEND_AT_LINK_NUMBER = 0x00000000,
6212SEND_AT_EARLIEST_TIME = 0x00000001,
6213} DP_SEC_GSP_SEND_ANY_LINE;
6214
6215/*
6216 * DP_SEC_LINE_REFERENCE enum
6217 */
6218
6219typedef enum DP_SEC_LINE_REFERENCE {
6220REFER_TO_DP_SOF = 0x00000000,
6221REFER_TO_OTG_SOF = 0x00000001,
6222} DP_SEC_LINE_REFERENCE;
6223
6224/*
6225 * DP_SEC_GSP_SEND_PPS enum
6226 */
6227
6228typedef enum DP_SEC_GSP_SEND_PPS {
6229SEND_NORMAL_PACKET = 0x00000000,
6230SEND_PPS_PACKET = 0x00000001,
6231} DP_SEC_GSP_SEND_PPS;
6232
6233/*
6234 * DP_ML_PHY_SEQ_MODE enum
6235 */
6236
6237typedef enum DP_ML_PHY_SEQ_MODE {
6238DP_ML_PHY_SEQ_LINE_NUM = 0x00000000,
6239DP_ML_PHY_SEQ_IMMEDIATE = 0x00000001,
6240} DP_ML_PHY_SEQ_MODE;
6241
6242/*
6243 * DP_LINK_TRAINING_SWITCH_MODE enum
6244 */
6245
6246typedef enum DP_LINK_TRAINING_SWITCH_MODE {
6247DP_LINK_TRAINING_SWITCH_TO_IDLE = 0x00000000,
6248DP_LINK_TRAINING_SWITCH_TO_VIDEO = 0x00000001,
6249} DP_LINK_TRAINING_SWITCH_MODE;
6250
6251/*
6252 * DP_DSC_MODE enum
6253 */
6254
6255typedef enum DP_DSC_MODE {
6256DP_DSC_DISABLE = 0x00000000,
6257DP_DSC_444_SIMPLE_422 = 0x00000001,
6258DP_DSC_NATIVE_422_420 = 0x00000002,
6259} DP_DSC_MODE;
6260
6261/*******************************************************
6262 * DIG Enums
6263 *******************************************************/
6264
6265/*
6266 * HDMI_KEEPOUT_MODE enum
6267 */
6268
6269typedef enum HDMI_KEEPOUT_MODE {
6270HDMI_KEEPOUT_0_650PIX_AFTER_VSYNC = 0x00000000,
6271HDMI_KEEPOUT_509_650PIX_AFTER_VSYNC = 0x00000001,
6272} HDMI_KEEPOUT_MODE;
6273
6274/*
6275 * HDMI_CLOCK_CHANNEL_RATE enum
6276 */
6277
6278typedef enum HDMI_CLOCK_CHANNEL_RATE {
6279HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE = 0x00000000,
6280HDMI_CLOCK_CHANNEL_FREQ_QUARTER_TO_CHAR_RATE = 0x00000001,
6281} HDMI_CLOCK_CHANNEL_RATE;
6282
6283/*
6284 * HDMI_NO_EXTRA_NULL_PACKET_FILLED enum
6285 */
6286
6287typedef enum HDMI_NO_EXTRA_NULL_PACKET_FILLED {
6288HDMI_EXTRA_NULL_PACKET_FILLED_ENABLE = 0x00000000,
6289HDMI_EXTRA_NULL_PACKET_FILLED_DISABLE = 0x00000001,
6290} HDMI_NO_EXTRA_NULL_PACKET_FILLED;
6291
6292/*
6293 * HDMI_PACKET_GEN_VERSION enum
6294 */
6295
6296typedef enum HDMI_PACKET_GEN_VERSION {
6297HDMI_PACKET_GEN_VERSION_OLD = 0x00000000,
6298HDMI_PACKET_GEN_VERSION_NEW = 0x00000001,
6299} HDMI_PACKET_GEN_VERSION;
6300
6301/*
6302 * HDMI_ERROR_ACK enum
6303 */
6304
6305typedef enum HDMI_ERROR_ACK {
6306HDMI_ERROR_ACK_INT = 0x00000000,
6307HDMI_ERROR_NOT_ACK = 0x00000001,
6308} HDMI_ERROR_ACK;
6309
6310/*
6311 * HDMI_ERROR_MASK enum
6312 */
6313
6314typedef enum HDMI_ERROR_MASK {
6315HDMI_ERROR_MASK_INT = 0x00000000,
6316HDMI_ERROR_NOT_MASK = 0x00000001,
6317} HDMI_ERROR_MASK;
6318
6319/*
6320 * HDMI_DEEP_COLOR_DEPTH enum
6321 */
6322
6323typedef enum HDMI_DEEP_COLOR_DEPTH {
6324HDMI_DEEP_COLOR_DEPTH_24BPP = 0x00000000,
6325HDMI_DEEP_COLOR_DEPTH_30BPP = 0x00000001,
6326HDMI_DEEP_COLOR_DEPTH_36BPP = 0x00000002,
6327HDMI_DEEP_COLOR_DEPTH_48BPP = 0x00000003,
6328} HDMI_DEEP_COLOR_DEPTH;
6329
6330/*
6331 * HDMI_AUDIO_DELAY_EN enum
6332 */
6333
6334typedef enum HDMI_AUDIO_DELAY_EN {
6335HDMI_AUDIO_DELAY_DISABLE = 0x00000000,
6336HDMI_AUDIO_DELAY_58CLK = 0x00000001,
6337HDMI_AUDIO_DELAY_56CLK = 0x00000002,
6338HDMI_AUDIO_DELAY_RESERVED = 0x00000003,
6339} HDMI_AUDIO_DELAY_EN;
6340
6341/*
6342 * HDMI_AUDIO_SEND_MAX_PACKETS enum
6343 */
6344
6345typedef enum HDMI_AUDIO_SEND_MAX_PACKETS {
6346HDMI_NOT_SEND_MAX_AUDIO_PACKETS = 0x00000000,
6347HDMI_SEND_MAX_AUDIO_PACKETS = 0x00000001,
6348} HDMI_AUDIO_SEND_MAX_PACKETS;
6349
6350/*
6351 * HDMI_ACR_SEND enum
6352 */
6353
6354typedef enum HDMI_ACR_SEND {
6355HDMI_ACR_NOT_SEND = 0x00000000,
6356HDMI_ACR_PKT_SEND = 0x00000001,
6357} HDMI_ACR_SEND;
6358
6359/*
6360 * HDMI_ACR_CONT enum
6361 */
6362
6363typedef enum HDMI_ACR_CONT {
6364HDMI_ACR_CONT_DISABLE = 0x00000000,
6365HDMI_ACR_CONT_ENABLE = 0x00000001,
6366} HDMI_ACR_CONT;
6367
6368/*
6369 * HDMI_ACR_SELECT enum
6370 */
6371
6372typedef enum HDMI_ACR_SELECT {
6373HDMI_ACR_SELECT_HW = 0x00000000,
6374HDMI_ACR_SELECT_32K = 0x00000001,
6375HDMI_ACR_SELECT_44K = 0x00000002,
6376HDMI_ACR_SELECT_48K = 0x00000003,
6377} HDMI_ACR_SELECT;
6378
6379/*
6380 * HDMI_ACR_SOURCE enum
6381 */
6382
6383typedef enum HDMI_ACR_SOURCE {
6384HDMI_ACR_SOURCE_HW = 0x00000000,
6385HDMI_ACR_SOURCE_SW = 0x00000001,
6386} HDMI_ACR_SOURCE;
6387
6388/*
6389 * HDMI_ACR_N_MULTIPLE enum
6390 */
6391
6392typedef enum HDMI_ACR_N_MULTIPLE {
6393HDMI_ACR_0_MULTIPLE_RESERVED = 0x00000000,
6394HDMI_ACR_1_MULTIPLE = 0x00000001,
6395HDMI_ACR_2_MULTIPLE = 0x00000002,
6396HDMI_ACR_3_MULTIPLE_RESERVED = 0x00000003,
6397HDMI_ACR_4_MULTIPLE = 0x00000004,
6398HDMI_ACR_5_MULTIPLE_RESERVED = 0x00000005,
6399HDMI_ACR_6_MULTIPLE_RESERVED = 0x00000006,
6400HDMI_ACR_7_MULTIPLE_RESERVED = 0x00000007,
6401} HDMI_ACR_N_MULTIPLE;
6402
6403/*
6404 * HDMI_ACR_AUDIO_PRIORITY enum
6405 */
6406
6407typedef enum HDMI_ACR_AUDIO_PRIORITY {
6408HDMI_ACR_PKT_HIGH_PRIORITY_THAN_AUDIO_SAMPLE = 0x00000000,
6409HDMI_AUDIO_SAMPLE_HIGH_PRIORITY_THAN_ACR_PKT = 0x00000001,
6410} HDMI_ACR_AUDIO_PRIORITY;
6411
6412/*
6413 * HDMI_NULL_SEND enum
6414 */
6415
6416typedef enum HDMI_NULL_SEND {
6417HDMI_NULL_NOT_SEND = 0x00000000,
6418HDMI_NULL_PKT_SEND = 0x00000001,
6419} HDMI_NULL_SEND;
6420
6421/*
6422 * HDMI_GC_SEND enum
6423 */
6424
6425typedef enum HDMI_GC_SEND {
6426HDMI_GC_NOT_SEND = 0x00000000,
6427HDMI_GC_PKT_SEND = 0x00000001,
6428} HDMI_GC_SEND;
6429
6430/*
6431 * HDMI_GC_CONT enum
6432 */
6433
6434typedef enum HDMI_GC_CONT {
6435HDMI_GC_CONT_DISABLE = 0x00000000,
6436HDMI_GC_CONT_ENABLE = 0x00000001,
6437} HDMI_GC_CONT;
6438
6439/*
6440 * HDMI_ISRC_SEND enum
6441 */
6442
6443typedef enum HDMI_ISRC_SEND {
6444HDMI_ISRC_NOT_SEND = 0x00000000,
6445HDMI_ISRC_PKT_SEND = 0x00000001,
6446} HDMI_ISRC_SEND;
6447
6448/*
6449 * HDMI_ISRC_CONT enum
6450 */
6451
6452typedef enum HDMI_ISRC_CONT {
6453HDMI_ISRC_CONT_DISABLE = 0x00000000,
6454HDMI_ISRC_CONT_ENABLE = 0x00000001,
6455} HDMI_ISRC_CONT;
6456
6457/*
6458 * HDMI_AUDIO_INFO_SEND enum
6459 */
6460
6461typedef enum HDMI_AUDIO_INFO_SEND {
6462HDMI_AUDIO_INFO_NOT_SEND = 0x00000000,
6463HDMI_AUDIO_INFO_PKT_SEND = 0x00000001,
6464} HDMI_AUDIO_INFO_SEND;
6465
6466/*
6467 * HDMI_AUDIO_INFO_CONT enum
6468 */
6469
6470typedef enum HDMI_AUDIO_INFO_CONT {
6471HDMI_AUDIO_INFO_CONT_DISABLE = 0x00000000,
6472HDMI_AUDIO_INFO_CONT_ENABLE = 0x00000001,
6473} HDMI_AUDIO_INFO_CONT;
6474
6475/*
6476 * HDMI_MPEG_INFO_SEND enum
6477 */
6478
6479typedef enum HDMI_MPEG_INFO_SEND {
6480HDMI_MPEG_INFO_NOT_SEND = 0x00000000,
6481HDMI_MPEG_INFO_PKT_SEND = 0x00000001,
6482} HDMI_MPEG_INFO_SEND;
6483
6484/*
6485 * HDMI_MPEG_INFO_CONT enum
6486 */
6487
6488typedef enum HDMI_MPEG_INFO_CONT {
6489HDMI_MPEG_INFO_CONT_DISABLE = 0x00000000,
6490HDMI_MPEG_INFO_CONT_ENABLE = 0x00000001,
6491} HDMI_MPEG_INFO_CONT;
6492
6493/*
6494 * HDMI_GENERIC_SEND enum
6495 */
6496
6497typedef enum HDMI_GENERIC_SEND {
6498HDMI_GENERIC_NOT_SEND = 0x00000000,
6499HDMI_GENERIC_PKT_SEND = 0x00000001,
6500} HDMI_GENERIC_SEND;
6501
6502/*
6503 * HDMI_GENERIC_CONT enum
6504 */
6505
6506typedef enum HDMI_GENERIC_CONT {
6507HDMI_GENERIC_CONT_DISABLE = 0x00000000,
6508HDMI_GENERIC_CONT_ENABLE = 0x00000001,
6509} HDMI_GENERIC_CONT;
6510
6511/*
6512 * HDMI_GC_AVMUTE_CONT enum
6513 */
6514
6515typedef enum HDMI_GC_AVMUTE_CONT {
6516HDMI_GC_AVMUTE_CONT_DISABLE = 0x00000000,
6517HDMI_GC_AVMUTE_CONT_ENABLE = 0x00000001,
6518} HDMI_GC_AVMUTE_CONT;
6519
6520/*
6521 * HDMI_PACKING_PHASE_OVERRIDE enum
6522 */
6523
6524typedef enum HDMI_PACKING_PHASE_OVERRIDE {
6525HDMI_PACKING_PHASE_SET_BY_HW = 0x00000000,
6526HDMI_PACKING_PHASE_SET_BY_SW = 0x00000001,
6527} HDMI_PACKING_PHASE_OVERRIDE;
6528
6529/*
6530 * TMDS_PIXEL_ENCODING enum
6531 */
6532
6533typedef enum TMDS_PIXEL_ENCODING {
6534TMDS_PIXEL_ENCODING_444_OR_420 = 0x00000000,
6535TMDS_PIXEL_ENCODING_422 = 0x00000001,
6536} TMDS_PIXEL_ENCODING;
6537
6538/*
6539 * TMDS_COLOR_FORMAT enum
6540 */
6541
6542typedef enum TMDS_COLOR_FORMAT {
6543TMDS_COLOR_FORMAT__24BPP__TWIN30BPP_MSB__DUAL48BPP = 0x00000000,
6544TMDS_COLOR_FORMAT_TWIN30BPP_LSB = 0x00000001,
6545TMDS_COLOR_FORMAT_DUAL30BPP = 0x00000002,
6546TMDS_COLOR_FORMAT_RESERVED = 0x00000003,
6547} TMDS_COLOR_FORMAT;
6548
6549/*
6550 * TMDS_STEREOSYNC_CTL_SEL_REG enum
6551 */
6552
6553typedef enum TMDS_STEREOSYNC_CTL_SEL_REG {
6554TMDS_STEREOSYNC_CTL0 = 0x00000000,
6555TMDS_STEREOSYNC_CTL1 = 0x00000001,
6556TMDS_STEREOSYNC_CTL2 = 0x00000002,
6557TMDS_STEREOSYNC_CTL3 = 0x00000003,
6558} TMDS_STEREOSYNC_CTL_SEL_REG;
6559
6560/*
6561 * TMDS_CTL0_DATA_SEL enum
6562 */
6563
6564typedef enum TMDS_CTL0_DATA_SEL {
6565TMDS_CTL0_DATA_SEL0_RESERVED = 0x00000000,
6566TMDS_CTL0_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
6567TMDS_CTL0_DATA_SEL2_VSYNC = 0x00000002,
6568TMDS_CTL0_DATA_SEL3_RESERVED = 0x00000003,
6569TMDS_CTL0_DATA_SEL4_HSYNC = 0x00000004,
6570TMDS_CTL0_DATA_SEL5_SEL7_RESERVED = 0x00000005,
6571TMDS_CTL0_DATA_SEL8_RANDOM_DATA = 0x00000006,
6572TMDS_CTL0_DATA_SEL9_SEL15_RANDOM_DATA = 0x00000007,
6573} TMDS_CTL0_DATA_SEL;
6574
6575/*
6576 * TMDS_CTL0_DATA_INVERT enum
6577 */
6578
6579typedef enum TMDS_CTL0_DATA_INVERT {
6580TMDS_CTL0_DATA_NORMAL = 0x00000000,
6581TMDS_CTL0_DATA_INVERT_EN = 0x00000001,
6582} TMDS_CTL0_DATA_INVERT;
6583
6584/*
6585 * TMDS_CTL0_DATA_MODULATION enum
6586 */
6587
6588typedef enum TMDS_CTL0_DATA_MODULATION {
6589TMDS_CTL0_DATA_MODULATION_DISABLE = 0x00000000,
6590TMDS_CTL0_DATA_MODULATION_BIT0 = 0x00000001,
6591TMDS_CTL0_DATA_MODULATION_BIT1 = 0x00000002,
6592TMDS_CTL0_DATA_MODULATION_BIT2 = 0x00000003,
6593} TMDS_CTL0_DATA_MODULATION;
6594
6595/*
6596 * TMDS_CTL0_PATTERN_OUT_EN enum
6597 */
6598
6599typedef enum TMDS_CTL0_PATTERN_OUT_EN {
6600TMDS_CTL0_PATTERN_OUT_DISABLE = 0x00000000,
6601TMDS_CTL0_PATTERN_OUT_ENABLE = 0x00000001,
6602} TMDS_CTL0_PATTERN_OUT_EN;
6603
6604/*
6605 * TMDS_CTL1_DATA_SEL enum
6606 */
6607
6608typedef enum TMDS_CTL1_DATA_SEL {
6609TMDS_CTL1_DATA_SEL0_RESERVED = 0x00000000,
6610TMDS_CTL1_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
6611TMDS_CTL1_DATA_SEL2_VSYNC = 0x00000002,
6612TMDS_CTL1_DATA_SEL3_RESERVED = 0x00000003,
6613TMDS_CTL1_DATA_SEL4_HSYNC = 0x00000004,
6614TMDS_CTL1_DATA_SEL5_SEL7_RESERVED = 0x00000005,
6615TMDS_CTL1_DATA_SEL8_BLANK_TIME = 0x00000006,
6616TMDS_CTL1_DATA_SEL9_SEL15_RESERVED = 0x00000007,
6617} TMDS_CTL1_DATA_SEL;
6618
6619/*
6620 * TMDS_CTL1_DATA_INVERT enum
6621 */
6622
6623typedef enum TMDS_CTL1_DATA_INVERT {
6624TMDS_CTL1_DATA_NORMAL = 0x00000000,
6625TMDS_CTL1_DATA_INVERT_EN = 0x00000001,
6626} TMDS_CTL1_DATA_INVERT;
6627
6628/*
6629 * TMDS_CTL1_DATA_MODULATION enum
6630 */
6631
6632typedef enum TMDS_CTL1_DATA_MODULATION {
6633TMDS_CTL1_DATA_MODULATION_DISABLE = 0x00000000,
6634TMDS_CTL1_DATA_MODULATION_BIT0 = 0x00000001,
6635TMDS_CTL1_DATA_MODULATION_BIT1 = 0x00000002,
6636TMDS_CTL1_DATA_MODULATION_BIT2 = 0x00000003,
6637} TMDS_CTL1_DATA_MODULATION;
6638
6639/*
6640 * TMDS_CTL1_PATTERN_OUT_EN enum
6641 */
6642
6643typedef enum TMDS_CTL1_PATTERN_OUT_EN {
6644TMDS_CTL1_PATTERN_OUT_DISABLE = 0x00000000,
6645TMDS_CTL1_PATTERN_OUT_ENABLE = 0x00000001,
6646} TMDS_CTL1_PATTERN_OUT_EN;
6647
6648/*
6649 * TMDS_CTL2_DATA_SEL enum
6650 */
6651
6652typedef enum TMDS_CTL2_DATA_SEL {
6653TMDS_CTL2_DATA_SEL0_RESERVED = 0x00000000,
6654TMDS_CTL2_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
6655TMDS_CTL2_DATA_SEL2_VSYNC = 0x00000002,
6656TMDS_CTL2_DATA_SEL3_RESERVED = 0x00000003,
6657TMDS_CTL2_DATA_SEL4_HSYNC = 0x00000004,
6658TMDS_CTL2_DATA_SEL5_SEL7_RESERVED = 0x00000005,
6659TMDS_CTL2_DATA_SEL8_BLANK_TIME = 0x00000006,
6660TMDS_CTL2_DATA_SEL9_SEL15_RESERVED = 0x00000007,
6661} TMDS_CTL2_DATA_SEL;
6662
6663/*
6664 * TMDS_CTL2_DATA_INVERT enum
6665 */
6666
6667typedef enum TMDS_CTL2_DATA_INVERT {
6668TMDS_CTL2_DATA_NORMAL = 0x00000000,
6669TMDS_CTL2_DATA_INVERT_EN = 0x00000001,
6670} TMDS_CTL2_DATA_INVERT;
6671
6672/*
6673 * TMDS_CTL2_DATA_MODULATION enum
6674 */
6675
6676typedef enum TMDS_CTL2_DATA_MODULATION {
6677TMDS_CTL2_DATA_MODULATION_DISABLE = 0x00000000,
6678TMDS_CTL2_DATA_MODULATION_BIT0 = 0x00000001,
6679TMDS_CTL2_DATA_MODULATION_BIT1 = 0x00000002,
6680TMDS_CTL2_DATA_MODULATION_BIT2 = 0x00000003,
6681} TMDS_CTL2_DATA_MODULATION;
6682
6683/*
6684 * TMDS_CTL2_PATTERN_OUT_EN enum
6685 */
6686
6687typedef enum TMDS_CTL2_PATTERN_OUT_EN {
6688TMDS_CTL2_PATTERN_OUT_DISABLE = 0x00000000,
6689TMDS_CTL2_PATTERN_OUT_ENABLE = 0x00000001,
6690} TMDS_CTL2_PATTERN_OUT_EN;
6691
6692/*
6693 * TMDS_CTL3_DATA_INVERT enum
6694 */
6695
6696typedef enum TMDS_CTL3_DATA_INVERT {
6697TMDS_CTL3_DATA_NORMAL = 0x00000000,
6698TMDS_CTL3_DATA_INVERT_EN = 0x00000001,
6699} TMDS_CTL3_DATA_INVERT;
6700
6701/*
6702 * TMDS_CTL3_DATA_MODULATION enum
6703 */
6704
6705typedef enum TMDS_CTL3_DATA_MODULATION {
6706TMDS_CTL3_DATA_MODULATION_DISABLE = 0x00000000,
6707TMDS_CTL3_DATA_MODULATION_BIT0 = 0x00000001,
6708TMDS_CTL3_DATA_MODULATION_BIT1 = 0x00000002,
6709TMDS_CTL3_DATA_MODULATION_BIT2 = 0x00000003,
6710} TMDS_CTL3_DATA_MODULATION;
6711
6712/*
6713 * TMDS_CTL3_PATTERN_OUT_EN enum
6714 */
6715
6716typedef enum TMDS_CTL3_PATTERN_OUT_EN {
6717TMDS_CTL3_PATTERN_OUT_DISABLE = 0x00000000,
6718TMDS_CTL3_PATTERN_OUT_ENABLE = 0x00000001,
6719} TMDS_CTL3_PATTERN_OUT_EN;
6720
6721/*
6722 * TMDS_CTL3_DATA_SEL enum
6723 */
6724
6725typedef enum TMDS_CTL3_DATA_SEL {
6726TMDS_CTL3_DATA_SEL0_RESERVED = 0x00000000,
6727TMDS_CTL3_DATA_SEL1_DISPLAY_ENABLE = 0x00000001,
6728TMDS_CTL3_DATA_SEL2_VSYNC = 0x00000002,
6729TMDS_CTL3_DATA_SEL3_RESERVED = 0x00000003,
6730TMDS_CTL3_DATA_SEL4_HSYNC = 0x00000004,
6731TMDS_CTL3_DATA_SEL5_SEL7_RESERVED = 0x00000005,
6732TMDS_CTL3_DATA_SEL8_BLANK_TIME = 0x00000006,
6733TMDS_CTL3_DATA_SEL9_SEL15_RESERVED = 0x00000007,
6734} TMDS_CTL3_DATA_SEL;
6735
6736/*
6737 * DIG_FE_CNTL_SOURCE_SELECT enum
6738 */
6739
6740typedef enum DIG_FE_CNTL_SOURCE_SELECT {
6741DIG_FE_SOURCE_FROM_OTG0 = 0x00000000,
6742DIG_FE_SOURCE_FROM_OTG1 = 0x00000001,
6743DIG_FE_SOURCE_FROM_OTG2 = 0x00000002,
6744DIG_FE_SOURCE_FROM_OTG3 = 0x00000003,
6745DIG_FE_SOURCE_FROM_OTG4 = 0x00000004,
6746DIG_FE_SOURCE_FROM_OTG5 = 0x00000005,
6747DIG_FE_SOURCE_RESERVED = 0x00000006,
6748} DIG_FE_CNTL_SOURCE_SELECT;
6749
6750/*
6751 * DIG_FE_CNTL_STEREOSYNC_SELECT enum
6752 */
6753
6754typedef enum DIG_FE_CNTL_STEREOSYNC_SELECT {
6755DIG_FE_STEREOSYNC_FROM_OTG0 = 0x00000000,
6756DIG_FE_STEREOSYNC_FROM_OTG1 = 0x00000001,
6757DIG_FE_STEREOSYNC_FROM_OTG2 = 0x00000002,
6758DIG_FE_STEREOSYNC_FROM_OTG3 = 0x00000003,
6759DIG_FE_STEREOSYNC_FROM_OTG4 = 0x00000004,
6760DIG_FE_STEREOSYNC_FROM_OTG5 = 0x00000005,
6761DIG_FE_STEREOSYNC_RESERVED = 0x00000006,
6762} DIG_FE_CNTL_STEREOSYNC_SELECT;
6763
6764/*
6765 * DIG_FIFO_READ_CLOCK_SRC enum
6766 */
6767
6768typedef enum DIG_FIFO_READ_CLOCK_SRC {
6769DIG_FIFO_READ_CLOCK_SRC_FROM_DCCG = 0x00000000,
6770DIG_FIFO_READ_CLOCK_SRC_FROM_DISPLAY_PIPE = 0x00000001,
6771} DIG_FIFO_READ_CLOCK_SRC;
6772
6773/*
6774 * DIG_OUTPUT_CRC_CNTL_LINK_SEL enum
6775 */
6776
6777typedef enum DIG_OUTPUT_CRC_CNTL_LINK_SEL {
6778DIG_OUTPUT_CRC_ON_LINK0 = 0x00000000,
6779DIG_OUTPUT_CRC_ON_LINK1 = 0x00000001,
6780} DIG_OUTPUT_CRC_CNTL_LINK_SEL;
6781
6782/*
6783 * DIG_OUTPUT_CRC_DATA_SEL enum
6784 */
6785
6786typedef enum DIG_OUTPUT_CRC_DATA_SEL {
6787DIG_OUTPUT_CRC_FOR_FULLFRAME = 0x00000000,
6788DIG_OUTPUT_CRC_FOR_ACTIVEONLY = 0x00000001,
6789DIG_OUTPUT_CRC_FOR_VBI = 0x00000002,
6790DIG_OUTPUT_CRC_FOR_AUDIO = 0x00000003,
6791} DIG_OUTPUT_CRC_DATA_SEL;
6792
6793/*
6794 * DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN enum
6795 */
6796
6797typedef enum DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN {
6798DIG_IN_NORMAL_OPERATION = 0x00000000,
6799DIG_IN_DEBUG_MODE = 0x00000001,
6800} DIG_TEST_PATTERN_TEST_PATTERN_OUT_EN;
6801
6802/*
6803 * DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL enum
6804 */
6805
6806typedef enum DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL {
6807DIG_10BIT_TEST_PATTERN = 0x00000000,
6808DIG_ALTERNATING_TEST_PATTERN = 0x00000001,
6809} DIG_TEST_PATTERN_HALF_CLOCK_PATTERN_SEL;
6810
6811/*
6812 * DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN enum
6813 */
6814
6815typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN {
6816DIG_TEST_PATTERN_NORMAL = 0x00000000,
6817DIG_TEST_PATTERN_RANDOM = 0x00000001,
6818} DIG_TEST_PATTERN_RANDOM_PATTERN_OUT_EN;
6819
6820/*
6821 * DIG_TEST_PATTERN_RANDOM_PATTERN_RESET enum
6822 */
6823
6824typedef enum DIG_TEST_PATTERN_RANDOM_PATTERN_RESET {
6825DIG_RANDOM_PATTERN_ENABLED = 0x00000000,
6826DIG_RANDOM_PATTERN_RESETED = 0x00000001,
6827} DIG_TEST_PATTERN_RANDOM_PATTERN_RESET;
6828
6829/*
6830 * DIG_TEST_PATTERN_EXTERNAL_RESET_EN enum
6831 */
6832
6833typedef enum DIG_TEST_PATTERN_EXTERNAL_RESET_EN {
6834DIG_TEST_PATTERN_EXTERNAL_RESET_ENABLE = 0x00000000,
6835DIG_TEST_PATTERN_EXTERNAL_RESET_BY_EXT_SIG = 0x00000001,
6836} DIG_TEST_PATTERN_EXTERNAL_RESET_EN;
6837
6838/*
6839 * DIG_RANDOM_PATTERN_SEED_RAN_PAT enum
6840 */
6841
6842typedef enum DIG_RANDOM_PATTERN_SEED_RAN_PAT {
6843DIG_RANDOM_PATTERN_SEED_RAN_PAT_ALL_PIXELS = 0x00000000,
6844DIG_RANDOM_PATTERN_SEED_RAN_PAT_DE_HIGH = 0x00000001,
6845} DIG_RANDOM_PATTERN_SEED_RAN_PAT;
6846
6847/*
6848 * DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL enum
6849 */
6850
6851typedef enum DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL {
6852DIG_FIFO_USE_OVERWRITE_LEVEL = 0x00000000,
6853DIG_FIFO_USE_CAL_AVERAGE_LEVEL = 0x00000001,
6854} DIG_FIFO_STATUS_USE_OVERWRITE_LEVEL;
6855
6856/*
6857 * DIG_FIFO_ERROR_ACK enum
6858 */
6859
6860typedef enum DIG_FIFO_ERROR_ACK {
6861DIG_FIFO_ERROR_ACK_INT = 0x00000000,
6862DIG_FIFO_ERROR_NOT_ACK = 0x00000001,
6863} DIG_FIFO_ERROR_ACK;
6864
6865/*
6866 * DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE enum
6867 */
6868
6869typedef enum DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE {
6870DIG_FIFO_NOT_FORCE_RECAL_AVERAGE = 0x00000000,
6871DIG_FIFO_FORCE_RECAL_AVERAGE_LEVEL = 0x00000001,
6872} DIG_FIFO_STATUS_FORCE_RECAL_AVERAGE;
6873
6874/*
6875 * DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX enum
6876 */
6877
6878typedef enum DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX {
6879DIG_FIFO_NOT_FORCE_RECOMP_MINMAX = 0x00000000,
6880DIG_FIFO_FORCE_RECOMP_MINMAX = 0x00000001,
6881} DIG_FIFO_STATUS_FORCE_RECOMP_MINMAX;
6882
6883/*
6884 * AFMT_INTERRUPT_STATUS_CHG_MASK enum
6885 */
6886
6887typedef enum AFMT_INTERRUPT_STATUS_CHG_MASK {
6888AFMT_INTERRUPT_DISABLE = 0x00000000,
6889AFMT_INTERRUPT_ENABLE = 0x00000001,
6890} AFMT_INTERRUPT_STATUS_CHG_MASK;
6891
6892/*
6893 * HDMI_GC_AVMUTE enum
6894 */
6895
6896typedef enum HDMI_GC_AVMUTE {
6897HDMI_GC_AVMUTE_SET = 0x00000000,
6898HDMI_GC_AVMUTE_UNSET = 0x00000001,
6899} HDMI_GC_AVMUTE;
6900
6901/*
6902 * HDMI_DEFAULT_PAHSE enum
6903 */
6904
6905typedef enum HDMI_DEFAULT_PAHSE {
6906HDMI_DEFAULT_PHASE_IS_0 = 0x00000000,
6907HDMI_DEFAULT_PHASE_IS_1 = 0x00000001,
6908} HDMI_DEFAULT_PAHSE;
6909
6910/*
6911 * AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD enum
6912 */
6913
6914typedef enum AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD {
6915AFMT_AUDIO_LAYOUT_DETERMINED_BY_AZ_AUDIO_CHANNEL_STATUS = 0x00000000,
6916AFMT_AUDIO_LAYOUT_OVRD_BY_REGISTER = 0x00000001,
6917} AFMT_AUDIO_PACKET_CONTROL2_AUDIO_LAYOUT_OVRD;
6918
6919/*
6920 * AUDIO_LAYOUT_SELECT enum
6921 */
6922
6923typedef enum AUDIO_LAYOUT_SELECT {
6924AUDIO_LAYOUT_0 = 0x00000000,
6925AUDIO_LAYOUT_1 = 0x00000001,
6926} AUDIO_LAYOUT_SELECT;
6927
6928/*
6929 * AFMT_AUDIO_CRC_CONTROL_CONT enum
6930 */
6931
6932typedef enum AFMT_AUDIO_CRC_CONTROL_CONT {
6933AFMT_AUDIO_CRC_ONESHOT = 0x00000000,
6934AFMT_AUDIO_CRC_AUTO_RESTART = 0x00000001,
6935} AFMT_AUDIO_CRC_CONTROL_CONT;
6936
6937/*
6938 * AFMT_AUDIO_CRC_CONTROL_SOURCE enum
6939 */
6940
6941typedef enum AFMT_AUDIO_CRC_CONTROL_SOURCE {
6942AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_INPUT = 0x00000000,
6943AFMT_AUDIO_CRC_SOURCE_FROM_FIFO_OUTPUT = 0x00000001,
6944} AFMT_AUDIO_CRC_CONTROL_SOURCE;
6945
6946/*
6947 * AFMT_AUDIO_CRC_CONTROL_CH_SEL enum
6948 */
6949
6950typedef enum AFMT_AUDIO_CRC_CONTROL_CH_SEL {
6951AFMT_AUDIO_CRC_CH0_SIG = 0x00000000,
6952AFMT_AUDIO_CRC_CH1_SIG = 0x00000001,
6953AFMT_AUDIO_CRC_CH2_SIG = 0x00000002,
6954AFMT_AUDIO_CRC_CH3_SIG = 0x00000003,
6955AFMT_AUDIO_CRC_CH4_SIG = 0x00000004,
6956AFMT_AUDIO_CRC_CH5_SIG = 0x00000005,
6957AFMT_AUDIO_CRC_CH6_SIG = 0x00000006,
6958AFMT_AUDIO_CRC_CH7_SIG = 0x00000007,
6959AFMT_AUDIO_CRC_RESERVED_8 = 0x00000008,
6960AFMT_AUDIO_CRC_RESERVED_9 = 0x00000009,
6961AFMT_AUDIO_CRC_RESERVED_10 = 0x0000000a,
6962AFMT_AUDIO_CRC_RESERVED_11 = 0x0000000b,
6963AFMT_AUDIO_CRC_RESERVED_12 = 0x0000000c,
6964AFMT_AUDIO_CRC_RESERVED_13 = 0x0000000d,
6965AFMT_AUDIO_CRC_RESERVED_14 = 0x0000000e,
6966AFMT_AUDIO_CRC_AUDIO_SAMPLE_COUNT = 0x0000000f,
6967} AFMT_AUDIO_CRC_CONTROL_CH_SEL;
6968
6969/*
6970 * AFMT_RAMP_CONTROL0_SIGN enum
6971 */
6972
6973typedef enum AFMT_RAMP_CONTROL0_SIGN {
6974AFMT_RAMP_SIGNED = 0x00000000,
6975AFMT_RAMP_UNSIGNED = 0x00000001,
6976} AFMT_RAMP_CONTROL0_SIGN;
6977
6978/*
6979 * AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND enum
6980 */
6981
6982typedef enum AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND {
6983AFMT_AUDIO_PACKET_SENT_DISABLED = 0x00000000,
6984AFMT_AUDIO_PACKET_SENT_ENABLED = 0x00000001,
6985} AFMT_AUDIO_PACKET_CONTROL_AUDIO_SAMPLE_SEND;
6986
6987/*
6988 * AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS enum
6989 */
6990
6991typedef enum AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS {
6992AFMT_NOT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED_RESERVED = 0x00000000,
6993AFMT_RESET_AUDIO_FIFO_WHEN_AUDIO_DISABLED = 0x00000001,
6994} AFMT_AUDIO_PACKET_CONTROL_RESET_FIFO_WHEN_AUDIO_DIS;
6995
6996/*
6997 * AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE enum
6998 */
6999
7000typedef enum AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE {
7001AFMT_INFOFRAME_SOURCE_FROM_AZALIA_BLOCK = 0x00000000,
7002AFMT_INFOFRAME_SOURCE_FROM_AFMT_REGISTERS = 0x00000001,
7003} AFMT_INFOFRAME_CONTROL0_AUDIO_INFO_SOURCE;
7004
7005/*
7006 * AFMT_AUDIO_SRC_CONTROL_SELECT enum
7007 */
7008
7009typedef enum AFMT_AUDIO_SRC_CONTROL_SELECT {
7010AFMT_AUDIO_SRC_FROM_AZ_STREAM0 = 0x00000000,
7011AFMT_AUDIO_SRC_FROM_AZ_STREAM1 = 0x00000001,
7012AFMT_AUDIO_SRC_FROM_AZ_STREAM2 = 0x00000002,
7013AFMT_AUDIO_SRC_FROM_AZ_STREAM3 = 0x00000003,
7014AFMT_AUDIO_SRC_FROM_AZ_STREAM4 = 0x00000004,
7015AFMT_AUDIO_SRC_FROM_AZ_STREAM5 = 0x00000005,
7016AFMT_AUDIO_SRC_RESERVED = 0x00000006,
7017} AFMT_AUDIO_SRC_CONTROL_SELECT;
7018
7019/*
7020 * DIG_BE_CNTL_MODE enum
7021 */
7022
7023typedef enum DIG_BE_CNTL_MODE {
7024DIG_BE_DP_SST_MODE = 0x00000000,
7025DIG_BE_RESERVED1 = 0x00000001,
7026DIG_BE_TMDS_DVI_MODE = 0x00000002,
7027DIG_BE_TMDS_HDMI_MODE = 0x00000003,
7028DIG_BE_RESERVED4 = 0x00000004,
7029DIG_BE_DP_MST_MODE = 0x00000005,
7030DIG_BE_RESERVED2 = 0x00000006,
7031DIG_BE_RESERVED3 = 0x00000007,
7032} DIG_BE_CNTL_MODE;
7033
7034/*
7035 * DIG_BE_CNTL_HPD_SELECT enum
7036 */
7037
7038typedef enum DIG_BE_CNTL_HPD_SELECT {
7039DIG_BE_CNTL_HPD1 = 0x00000000,
7040DIG_BE_CNTL_HPD2 = 0x00000001,
7041DIG_BE_CNTL_HPD3 = 0x00000002,
7042DIG_BE_CNTL_HPD4 = 0x00000003,
7043DIG_BE_CNTL_HPD5 = 0x00000004,
7044DIG_BE_CNTL_HPD6 = 0x00000005,
7045DIG_BE_CNTL_NO_HPD = 0x00000006,
7046} DIG_BE_CNTL_HPD_SELECT;
7047
7048/*
7049 * LVTMA_RANDOM_PATTERN_SEED_RAN_PAT enum
7050 */
7051
7052typedef enum LVTMA_RANDOM_PATTERN_SEED_RAN_PAT {
7053LVTMA_RANDOM_PATTERN_SEED_ALL_PIXELS = 0x00000000,
7054LVTMA_RANDOM_PATTERN_SEED_ONLY_DE_HIGH = 0x00000001,
7055} LVTMA_RANDOM_PATTERN_SEED_RAN_PAT;
7056
7057/*
7058 * TMDS_SYNC_PHASE enum
7059 */
7060
7061typedef enum TMDS_SYNC_PHASE {
7062TMDS_NOT_SYNC_PHASE_ON_FRAME_START = 0x00000000,
7063TMDS_SYNC_PHASE_ON_FRAME_START = 0x00000001,
7064} TMDS_SYNC_PHASE;
7065
7066/*
7067 * TMDS_DATA_SYNCHRONIZATION_DSINTSEL enum
7068 */
7069
7070typedef enum TMDS_DATA_SYNCHRONIZATION_DSINTSEL {
7071TMDS_DATA_SYNCHRONIZATION_DSINTSEL_PCLK_TMDS = 0x00000000,
7072TMDS_DATA_SYNCHRONIZATION_DSINTSEL_TMDS_PLL = 0x00000001,
7073} TMDS_DATA_SYNCHRONIZATION_DSINTSEL;
7074
7075/*
7076 * TMDS_TRANSMITTER_ENABLE_HPD_MASK enum
7077 */
7078
7079typedef enum TMDS_TRANSMITTER_ENABLE_HPD_MASK {
7080TMDS_TRANSMITTER_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7081TMDS_TRANSMITTER_HPD_MASK_OVERRIDE = 0x00000001,
7082} TMDS_TRANSMITTER_ENABLE_HPD_MASK;
7083
7084/*
7085 * TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK enum
7086 */
7087
7088typedef enum TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK {
7089TMDS_TRANSMITTER_LNKCEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7090TMDS_TRANSMITTER_LNKCEN_HPD_MASK_OVERRIDE = 0x00000001,
7091} TMDS_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK;
7092
7093/*
7094 * TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK enum
7095 */
7096
7097typedef enum TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK {
7098TMDS_TRANSMITTER_LNKDEN_HPD_MASK_NOT_OVERRIDE = 0x00000000,
7099TMDS_TRANSMITTER_LNKDEN_HPD_MASK_OVERRIDE = 0x00000001,
7100} TMDS_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK;
7101
7102/*
7103 * TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK enum
7104 */
7105
7106typedef enum TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK {
7107TMDS_TRANSMITTER_HPD_NOT_OVERRIDE_PLL_ENABLE = 0x00000000,
7108TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_DISCON = 0x00000001,
7109TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE_ON_CON = 0x00000002,
7110TMDS_TRANSMITTER_HPD_OVERRIDE_PLL_ENABLE = 0x00000003,
7111} TMDS_TRANSMITTER_CONTROL_PLL_ENABLE_HPD_MASK;
7112
7113/*
7114 * TMDS_TRANSMITTER_CONTROL_IDSCKSELA enum
7115 */
7116
7117typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELA {
7118TMDS_TRANSMITTER_IDSCKSELA_USE_IPIXCLK = 0x00000000,
7119TMDS_TRANSMITTER_IDSCKSELA_USE_IDCLK = 0x00000001,
7120} TMDS_TRANSMITTER_CONTROL_IDSCKSELA;
7121
7122/*
7123 * TMDS_TRANSMITTER_CONTROL_IDSCKSELB enum
7124 */
7125
7126typedef enum TMDS_TRANSMITTER_CONTROL_IDSCKSELB {
7127TMDS_TRANSMITTER_IDSCKSELB_USE_IPIXCLK = 0x00000000,
7128TMDS_TRANSMITTER_IDSCKSELB_USE_IDCLK = 0x00000001,
7129} TMDS_TRANSMITTER_CONTROL_IDSCKSELB;
7130
7131/*
7132 * TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN enum
7133 */
7134
7135typedef enum TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN {
7136TMDS_TRANSMITTER_PLL_PWRUP_SEQ_DISABLE = 0x00000000,
7137TMDS_TRANSMITTER_PLL_PWRUP_SEQ_ENABLE = 0x00000001,
7138} TMDS_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN;
7139
7140/*
7141 * TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK enum
7142 */
7143
7144typedef enum TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK {
7145TMDS_TRANSMITTER_PLL_NOT_RST_ON_HPD = 0x00000000,
7146TMDS_TRANSMITTER_PLL_RST_ON_HPD = 0x00000001,
7147} TMDS_TRANSMITTER_CONTROL_PLL_RESET_HPD_MASK;
7148
7149/*
7150 * TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS enum
7151 */
7152
7153typedef enum TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS {
7154TMDS_TRANSMITTER_TMCLK_FROM_TMDS_TMCLK = 0x00000000,
7155TMDS_TRANSMITTER_TMCLK_FROM_PADS = 0x00000001,
7156} TMDS_TRANSMITTER_CONTROL_TMCLK_FROM_PADS;
7157
7158/*
7159 * TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS enum
7160 */
7161
7162typedef enum TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS {
7163TMDS_TRANSMITTER_TDCLK_FROM_TMDS_TDCLK = 0x00000000,
7164TMDS_TRANSMITTER_TDCLK_FROM_PADS = 0x00000001,
7165} TMDS_TRANSMITTER_CONTROL_TDCLK_FROM_PADS;
7166
7167/*
7168 * TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN enum
7169 */
7170
7171typedef enum TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN {
7172TMDS_TRANSMITTER_PLLSEL_BY_HW = 0x00000000,
7173TMDS_TRANSMITTER_PLLSEL_OVERWRITE_BY_SW = 0x00000001,
7174} TMDS_TRANSMITTER_CONTROL_PLLSEL_OVERWRITE_EN;
7175
7176/*
7177 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA enum
7178 */
7179
7180typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA {
7181TMDS_TRANSMITTER_BYPASS_PLLA_COHERENT = 0x00000000,
7182TMDS_TRANSMITTER_BYPASS_PLLA_INCOHERENT = 0x00000001,
7183} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLA;
7184
7185/*
7186 * TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB enum
7187 */
7188
7189typedef enum TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB {
7190TMDS_TRANSMITTER_BYPASS_PLLB_COHERENT = 0x00000000,
7191TMDS_TRANSMITTER_BYPASS_PLLB_INCOHERENT = 0x00000001,
7192} TMDS_TRANSMITTER_CONTROL_BYPASS_PLLB;
7193
7194/*
7195 * TMDS_REG_TEST_OUTPUTA_CNTLA enum
7196 */
7197
7198typedef enum TMDS_REG_TEST_OUTPUTA_CNTLA {
7199TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA0 = 0x00000000,
7200TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA1 = 0x00000001,
7201TMDS_REG_TEST_OUTPUTA_CNTLA_OTDATA2 = 0x00000002,
7202TMDS_REG_TEST_OUTPUTA_CNTLA_NA = 0x00000003,
7203} TMDS_REG_TEST_OUTPUTA_CNTLA;
7204
7205/*
7206 * TMDS_REG_TEST_OUTPUTB_CNTLB enum
7207 */
7208
7209typedef enum TMDS_REG_TEST_OUTPUTB_CNTLB {
7210TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB0 = 0x00000000,
7211TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB1 = 0x00000001,
7212TMDS_REG_TEST_OUTPUTB_CNTLB_OTDATB2 = 0x00000002,
7213TMDS_REG_TEST_OUTPUTB_CNTLB_NA = 0x00000003,
7214} TMDS_REG_TEST_OUTPUTB_CNTLB;
7215
7216/*
7217 * AFMT_VBI_GSP_INDEX enum
7218 */
7219
7220typedef enum AFMT_VBI_GSP_INDEX {
7221AFMT_VBI_GSP0_INDEX = 0x00000000,
7222AFMT_VBI_GSP1_INDEX = 0x00000001,
7223AFMT_VBI_GSP2_INDEX = 0x00000002,
7224AFMT_VBI_GSP3_INDEX = 0x00000003,
7225AFMT_VBI_GSP4_INDEX = 0x00000004,
7226AFMT_VBI_GSP5_INDEX = 0x00000005,
7227AFMT_VBI_GSP6_INDEX = 0x00000006,
7228AFMT_VBI_GSP7_INDEX = 0x00000007,
7229AFMT_VBI_GSP8_INDEX = 0x00000008,
7230AFMT_VBI_GSP9_INDEX = 0x00000009,
7231AFMT_VBI_GSP10_INDEX = 0x0000000a,
7232} AFMT_VBI_GSP_INDEX;
7233
7234/*
7235 * DIG_DIGITAL_BYPASS_SEL enum
7236 */
7237
7238typedef enum DIG_DIGITAL_BYPASS_SEL {
7239DIG_DIGITAL_BYPASS_SEL_BYPASS = 0x00000000,
7240DIG_DIGITAL_BYPASS_SEL_36BPP = 0x00000001,
7241DIG_DIGITAL_BYPASS_SEL_48BPP_LSB = 0x00000002,
7242DIG_DIGITAL_BYPASS_SEL_48BPP_MSB = 0x00000003,
7243DIG_DIGITAL_BYPASS_SEL_10BPP_LSB = 0x00000004,
7244DIG_DIGITAL_BYPASS_SEL_12BPC_LSB = 0x00000005,
7245DIG_DIGITAL_BYPASS_SEL_ALPHA = 0x00000006,
7246} DIG_DIGITAL_BYPASS_SEL;
7247
7248/*
7249 * DIG_INPUT_PIXEL_SEL enum
7250 */
7251
7252typedef enum DIG_INPUT_PIXEL_SEL {
7253DIG_ALL_PIXEL = 0x00000000,
7254DIG_EVEN_PIXEL_ONLY = 0x00000001,
7255DIG_ODD_PIXEL_ONLY = 0x00000002,
7256} DIG_INPUT_PIXEL_SEL;
7257
7258/*
7259 * DOLBY_VISION_ENABLE enum
7260 */
7261
7262typedef enum DOLBY_VISION_ENABLE {
7263DOLBY_VISION_ENABLED = 0x00000000,
7264DOLBY_VISION_DISABLED = 0x00000001,
7265} DOLBY_VISION_ENABLE;
7266
7267/*
7268 * METADATA_HUBP_SEL enum
7269 */
7270
7271typedef enum METADATA_HUBP_SEL {
7272METADATA_HUBP_SEL_0 = 0x00000000,
7273METADATA_HUBP_SEL_1 = 0x00000001,
7274METADATA_HUBP_SEL_2 = 0x00000002,
7275METADATA_HUBP_SEL_3 = 0x00000003,
7276METADATA_HUBP_SEL_4 = 0x00000004,
7277METADATA_HUBP_SEL_5 = 0x00000005,
7278METADATA_HUBP_SEL_RESERVED = 0x00000006,
7279} METADATA_HUBP_SEL;
7280
7281/*
7282 * METADATA_STREAM_TYPE_SEL enum
7283 */
7284
7285typedef enum METADATA_STREAM_TYPE_SEL {
7286METADATA_STREAM_DP = 0x00000000,
7287METADATA_STREAM_DVE = 0x00000001,
7288} METADATA_STREAM_TYPE_SEL;
7289
7290/*
7291 * HDMI_METADATA_ENABLE enum
7292 */
7293
7294typedef enum HDMI_METADATA_ENABLE {
7295HDMI_METADATA_NOT_SEND = 0x00000000,
7296HDMI_METADATA_PKT_SEND = 0x00000001,
7297} HDMI_METADATA_ENABLE;
7298
7299/*
7300 * HDMI_PACKET_LINE_REFERENCE enum
7301 */
7302
7303typedef enum HDMI_PACKET_LINE_REFERENCE {
7304HDMI_PKT_LINE_REF_VSYNC = 0x00000000,
7305HDMI_PKT_LINE_REF_OTGSOF = 0x00000001,
7306} HDMI_PACKET_LINE_REFERENCE;
7307
7308/*******************************************************
7309 * DP_AUX Enums
7310 *******************************************************/
7311
7312/*
7313 * DP_AUX_CONTROL_HPD_SEL enum
7314 */
7315
7316typedef enum DP_AUX_CONTROL_HPD_SEL {
7317DP_AUX_CONTROL_HPD1_SELECTED = 0x00000000,
7318DP_AUX_CONTROL_HPD2_SELECTED = 0x00000001,
7319DP_AUX_CONTROL_HPD3_SELECTED = 0x00000002,
7320DP_AUX_CONTROL_HPD4_SELECTED = 0x00000003,
7321DP_AUX_CONTROL_HPD5_SELECTED = 0x00000004,
7322DP_AUX_CONTROL_HPD6_SELECTED = 0x00000005,
7323DP_AUX_CONTROL_NO_HPD_SELECTED = 0x00000006,
7324} DP_AUX_CONTROL_HPD_SEL;
7325
7326/*
7327 * DP_AUX_CONTROL_TEST_MODE enum
7328 */
7329
7330typedef enum DP_AUX_CONTROL_TEST_MODE {
7331DP_AUX_CONTROL_TEST_MODE_DISABLE = 0x00000000,
7332DP_AUX_CONTROL_TEST_MODE_ENABLE = 0x00000001,
7333} DP_AUX_CONTROL_TEST_MODE;
7334
7335/*
7336 * DP_AUX_SW_CONTROL_SW_GO enum
7337 */
7338
7339typedef enum DP_AUX_SW_CONTROL_SW_GO {
7340DP_AUX_SW_CONTROL_SW__NOT_GO = 0x00000000,
7341DP_AUX_SW_CONTROL_SW__GO = 0x00000001,
7342} DP_AUX_SW_CONTROL_SW_GO;
7343
7344/*
7345 * DP_AUX_SW_CONTROL_LS_READ_TRIG enum
7346 */
7347
7348typedef enum DP_AUX_SW_CONTROL_LS_READ_TRIG {
7349DP_AUX_SW_CONTROL_LS_READ__NOT_TRIG = 0x00000000,
7350DP_AUX_SW_CONTROL_LS_READ__TRIG = 0x00000001,
7351} DP_AUX_SW_CONTROL_LS_READ_TRIG;
7352
7353/*
7354 * DP_AUX_ARB_CONTROL_ARB_PRIORITY enum
7355 */
7356
7357typedef enum DP_AUX_ARB_CONTROL_ARB_PRIORITY {
7358DP_AUX_ARB_CONTROL_ARB_PRIORITY__GTC_LS_SW = 0x00000000,
7359DP_AUX_ARB_CONTROL_ARB_PRIORITY__LS_GTC_SW = 0x00000001,
7360DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_LS_GTC = 0x00000002,
7361DP_AUX_ARB_CONTROL_ARB_PRIORITY__SW_GTC_LS = 0x00000003,
7362} DP_AUX_ARB_CONTROL_ARB_PRIORITY;
7363
7364/*
7365 * DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ enum
7366 */
7367
7368typedef enum DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ {
7369DP_AUX_ARB_CONTROL__NOT_USE_AUX_REG_REQ = 0x00000000,
7370DP_AUX_ARB_CONTROL__USE_AUX_REG_REQ = 0x00000001,
7371} DP_AUX_ARB_CONTROL_USE_AUX_REG_REQ;
7372
7373/*
7374 * DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG enum
7375 */
7376
7377typedef enum DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG {
7378DP_AUX_ARB_CONTROL__DONE_NOT_USING_AUX_REG = 0x00000000,
7379DP_AUX_ARB_CONTROL__DONE_USING_AUX_REG = 0x00000001,
7380} DP_AUX_ARB_CONTROL_DONE_USING_AUX_REG;
7381
7382/*
7383 * DP_AUX_INT_ACK enum
7384 */
7385
7386typedef enum DP_AUX_INT_ACK {
7387DP_AUX_INT__NOT_ACK = 0x00000000,
7388DP_AUX_INT__ACK = 0x00000001,
7389} DP_AUX_INT_ACK;
7390
7391/*
7392 * DP_AUX_LS_UPDATE_ACK enum
7393 */
7394
7395typedef enum DP_AUX_LS_UPDATE_ACK {
7396DP_AUX_INT_LS_UPDATE_NOT_ACK = 0x00000000,
7397DP_AUX_INT_LS_UPDATE_ACK = 0x00000001,
7398} DP_AUX_LS_UPDATE_ACK;
7399
7400/*
7401 * DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL enum
7402 */
7403
7404typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL {
7405DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__DIVIDED_SYM_CLK = 0x00000000,
7406DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL__FROM_DCCG_MICROSECOND_REF = 0x00000001,
7407} DP_AUX_DPHY_TX_REF_CONTROL_TX_REF_SEL;
7408
7409/*
7410 * DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE enum
7411 */
7412
7413typedef enum DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE {
7414DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__1MHZ = 0x00000000,
7415DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__2MHZ = 0x00000001,
7416DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__4MHZ = 0x00000002,
7417DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE__8MHZ = 0x00000003,
7418} DP_AUX_DPHY_TX_REF_CONTROL_TX_RATE;
7419
7420/*
7421 * DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY enum
7422 */
7423
7424typedef enum DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY {
7425DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__0 = 0x00000000,
7426DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__16US = 0x00000001,
7427DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__32US = 0x00000002,
7428DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__64US = 0x00000003,
7429DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__128US = 0x00000004,
7430DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY__256US = 0x00000005,
7431} DP_AUX_DPHY_TX_CONTROL_MODE_DET_CHECK_DELAY;
7432
7433/*
7434 * DP_AUX_DPHY_RX_CONTROL_START_WINDOW enum
7435 */
7436
7437typedef enum DP_AUX_DPHY_RX_CONTROL_START_WINDOW {
7438DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO2_PERIOD = 0x00000000,
7439DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO4_PERIOD = 0x00000001,
7440DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO8_PERIOD = 0x00000002,
7441DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO16_PERIOD = 0x00000003,
7442DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO32_PERIOD = 0x00000004,
7443DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO64_PERIOD = 0x00000005,
7444DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO128_PERIOD = 0x00000006,
7445DP_AUX_DPHY_RX_CONTROL_START_WINDOW__1TO256_PERIOD = 0x00000007,
7446} DP_AUX_DPHY_RX_CONTROL_START_WINDOW;
7447
7448/*
7449 * DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW enum
7450 */
7451
7452typedef enum DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW {
7453DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO2_PERIOD = 0x00000000,
7454DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO4_PERIOD = 0x00000001,
7455DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO8_PERIOD = 0x00000002,
7456DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO16_PERIOD = 0x00000003,
7457DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO32_PERIOD = 0x00000004,
7458DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO64_PERIOD = 0x00000005,
7459DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO128_PERIOD = 0x00000006,
7460DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW__1TO256_PERIOD = 0x00000007,
7461} DP_AUX_DPHY_RX_CONTROL_RECEIVE_WINDOW;
7462
7463/*
7464 * DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN enum
7465 */
7466
7467typedef enum DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN {
7468DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__6_EDGES = 0x00000000,
7469DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__10_EDGES = 0x00000001,
7470DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__18_EDGES = 0x00000002,
7471DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN__RESERVED = 0x00000003,
7472} DP_AUX_DPHY_RX_CONTROL_HALF_SYM_DETECT_LEN;
7473
7474/*
7475 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT enum
7476 */
7477
7478typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT {
7479DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000000,
7480DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_PHASE_DETECT = 0x00000001,
7481} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_PHASE_DETECT;
7482
7483/*
7484 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START enum
7485 */
7486
7487typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START {
7488DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_START = 0x00000000,
7489DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_START = 0x00000001,
7490} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_START;
7491
7492/*
7493 * DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP enum
7494 */
7495
7496typedef enum DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP {
7497DP_AUX_DPHY_RX_CONTROL__NOT_ALLOW_BELOW_THRESHOLD_STOP = 0x00000000,
7498DP_AUX_DPHY_RX_CONTROL__ALLOW_BELOW_THRESHOLD_STOP = 0x00000001,
7499} DP_AUX_DPHY_RX_CONTROL_ALLOW_BELOW_THRESHOLD_STOP;
7500
7501/*
7502 * DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN enum
7503 */
7504
7505typedef enum DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN {
7506DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__2_HALF_SYMBOLS = 0x00000000,
7507DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__4_HALF_SYMBOLS = 0x00000001,
7508DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__6_HALF_SYMBOLS = 0x00000002,
7509DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN__8_HALF_SYMBOLS = 0x00000003,
7510} DP_AUX_DPHY_RX_CONTROL_PHASE_DETECT_LEN;
7511
7512/*
7513 * DP_AUX_RX_TIMEOUT_LEN_MUL enum
7514 */
7515
7516typedef enum DP_AUX_RX_TIMEOUT_LEN_MUL {
7517DP_AUX_RX_TIMEOUT_LEN_NO_MUL = 0x00000000,
7518DP_AUX_RX_TIMEOUT_LEN_MUL_2 = 0x00000001,
7519DP_AUX_RX_TIMEOUT_LEN_MUL_4 = 0x00000002,
7520DP_AUX_RX_TIMEOUT_LEN_MUL_8 = 0x00000003,
7521} DP_AUX_RX_TIMEOUT_LEN_MUL;
7522
7523/*
7524 * DP_AUX_TX_PRECHARGE_LEN_MUL enum
7525 */
7526
7527typedef enum DP_AUX_TX_PRECHARGE_LEN_MUL {
7528DP_AUX_TX_PRECHARGE_LEN_NO_MUL = 0x00000000,
7529DP_AUX_TX_PRECHARGE_LEN_MUL_2 = 0x00000001,
7530DP_AUX_TX_PRECHARGE_LEN_MUL_4 = 0x00000002,
7531DP_AUX_TX_PRECHARGE_LEN_MUL_8 = 0x00000003,
7532} DP_AUX_TX_PRECHARGE_LEN_MUL;
7533
7534/*
7535 * DP_AUX_DPHY_RX_DETECTION_THRESHOLD enum
7536 */
7537
7538typedef enum DP_AUX_DPHY_RX_DETECTION_THRESHOLD {
7539DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 = 0x00000000,
7540DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 = 0x00000001,
7541DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 = 0x00000002,
7542DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 = 0x00000003,
7543DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 = 0x00000004,
7544DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 = 0x00000005,
7545DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 = 0x00000006,
7546DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 = 0x00000007,
7547} DP_AUX_DPHY_RX_DETECTION_THRESHOLD;
7548
7549/*
7550 * DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ enum
7551 */
7552
7553typedef enum DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ {
7554DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_ALLOW_REQ_FROM_OTHER_AUX = 0x00000000,
7555DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ_FROM_OTHER_AUX = 0x00000001,
7556} DP_AUX_GTC_SYNC_CONTROL_GTC_SYNC_BLOCK_REQ;
7557
7558/*
7559 * DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW enum
7560 */
7561
7562typedef enum DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW {
7563DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__300US = 0x00000000,
7564DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__400US = 0x00000001,
7565DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__500US = 0x00000002,
7566DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW__600US = 0x00000003,
7567} DP_AUX_GTC_SYNC_CONTROL_INTERVAL_RESET_WINDOW;
7568
7569/*
7570 * DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT enum
7571 */
7572
7573typedef enum DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT {
7574DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__4_ATTAMPS = 0x00000000,
7575DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__8_ATTAMPS = 0x00000001,
7576DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__16_ATTAMPS = 0x00000002,
7577DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT__RESERVED = 0x00000003,
7578} DP_AUX_GTC_SYNC_CONTROL_OFFSET_CALC_MAX_ATTEMPT;
7579
7580/*
7581 * DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN enum
7582 */
7583
7584typedef enum DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN {
7585DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__0 = 0x00000000,
7586DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__64 = 0x00000001,
7587DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__128 = 0x00000002,
7588DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN__256 = 0x00000003,
7589} DP_AUX_GTC_SYNC_ERROR_CONTROL_LOCK_ACQ_TIMEOUT_LEN;
7590
7591/*
7592 * DP_AUX_ERR_OCCURRED_ACK enum
7593 */
7594
7595typedef enum DP_AUX_ERR_OCCURRED_ACK {
7596DP_AUX_ERR_OCCURRED__NOT_ACK = 0x00000000,
7597DP_AUX_ERR_OCCURRED__ACK = 0x00000001,
7598} DP_AUX_ERR_OCCURRED_ACK;
7599
7600/*
7601 * DP_AUX_POTENTIAL_ERR_REACHED_ACK enum
7602 */
7603
7604typedef enum DP_AUX_POTENTIAL_ERR_REACHED_ACK {
7605DP_AUX_POTENTIAL_ERR_REACHED__NOT_ACK = 0x00000000,
7606DP_AUX_POTENTIAL_ERR_REACHED__ACK = 0x00000001,
7607} DP_AUX_POTENTIAL_ERR_REACHED_ACK;
7608
7609/*
7610 * DP_AUX_DEFINITE_ERR_REACHED_ACK enum
7611 */
7612
7613typedef enum DP_AUX_DEFINITE_ERR_REACHED_ACK {
7614ALPHA_DP_AUX_DEFINITE_ERR_REACHED_NOT_ACK = 0x00000000,
7615ALPHA_DP_AUX_DEFINITE_ERR_REACHED_ACK = 0x00000001,
7616} DP_AUX_DEFINITE_ERR_REACHED_ACK;
7617
7618/*
7619 * DP_AUX_RESET enum
7620 */
7621
7622typedef enum DP_AUX_RESET {
7623DP_AUX_RESET_DEASSERTED = 0x00000000,
7624DP_AUX_RESET_ASSERTED = 0x00000001,
7625} DP_AUX_RESET;
7626
7627/*
7628 * DP_AUX_RESET_DONE enum
7629 */
7630
7631typedef enum DP_AUX_RESET_DONE {
7632DP_AUX_RESET_SEQUENCE_NOT_DONE = 0x00000000,
7633DP_AUX_RESET_SEQUENCE_DONE = 0x00000001,
7634} DP_AUX_RESET_DONE;
7635
7636/*
7637 * DP_AUX_PHY_WAKE_PRIORITY enum
7638 */
7639
7640typedef enum DP_AUX_PHY_WAKE_PRIORITY {
7641DP_AUX_PHY_WAKE_HIGH_PRIORITY = 0x00000000,
7642DP_AUX_PHY_WAKE_LOW_PRIORITY = 0x00000001,
7643} DP_AUX_PHY_WAKE_PRIORITY;
7644
7645/*******************************************************
7646 * DOUT_I2C Enums
7647 *******************************************************/
7648
7649/*
7650 * DOUT_I2C_CONTROL_GO enum
7651 */
7652
7653typedef enum DOUT_I2C_CONTROL_GO {
7654DOUT_I2C_CONTROL_STOP_TRANSFER = 0x00000000,
7655DOUT_I2C_CONTROL_START_TRANSFER = 0x00000001,
7656} DOUT_I2C_CONTROL_GO;
7657
7658/*
7659 * DOUT_I2C_CONTROL_SOFT_RESET enum
7660 */
7661
7662typedef enum DOUT_I2C_CONTROL_SOFT_RESET {
7663DOUT_I2C_CONTROL_NOT_RESET_I2C_CONTROLLER = 0x00000000,
7664DOUT_I2C_CONTROL_RESET_I2C_CONTROLLER = 0x00000001,
7665} DOUT_I2C_CONTROL_SOFT_RESET;
7666
7667/*
7668 * DOUT_I2C_CONTROL_SEND_RESET enum
7669 */
7670
7671typedef enum DOUT_I2C_CONTROL_SEND_RESET {
7672DOUT_I2C_CONTROL__NOT_SEND_RESET = 0x00000000,
7673DOUT_I2C_CONTROL__SEND_RESET = 0x00000001,
7674} DOUT_I2C_CONTROL_SEND_RESET;
7675
7676/*
7677 * DOUT_I2C_CONTROL_SEND_RESET_LENGTH enum
7678 */
7679
7680typedef enum DOUT_I2C_CONTROL_SEND_RESET_LENGTH {
7681DOUT_I2C_CONTROL__SEND_RESET_LENGTH_9 = 0x00000000,
7682DOUT_I2C_CONTROL__SEND_RESET_LENGTH_10 = 0x00000001,
7683} DOUT_I2C_CONTROL_SEND_RESET_LENGTH;
7684
7685/*
7686 * DOUT_I2C_CONTROL_SW_STATUS_RESET enum
7687 */
7688
7689typedef enum DOUT_I2C_CONTROL_SW_STATUS_RESET {
7690DOUT_I2C_CONTROL_NOT_RESET_SW_STATUS = 0x00000000,
7691DOUT_I2C_CONTROL_RESET_SW_STATUS = 0x00000001,
7692} DOUT_I2C_CONTROL_SW_STATUS_RESET;
7693
7694/*
7695 * DOUT_I2C_CONTROL_DDC_SELECT enum
7696 */
7697
7698typedef enum DOUT_I2C_CONTROL_DDC_SELECT {
7699DOUT_I2C_CONTROL_SELECT_DDC1 = 0x00000000,
7700DOUT_I2C_CONTROL_SELECT_DDC2 = 0x00000001,
7701DOUT_I2C_CONTROL_SELECT_DDC3 = 0x00000002,
7702DOUT_I2C_CONTROL_SELECT_DDC4 = 0x00000003,
7703DOUT_I2C_CONTROL_SELECT_DDC5 = 0x00000004,
7704DOUT_I2C_CONTROL_SELECT_DDC6 = 0x00000005,
7705DOUT_I2C_CONTROL_SELECT_DDCVGA = 0x00000006,
7706} DOUT_I2C_CONTROL_DDC_SELECT;
7707
7708/*
7709 * DOUT_I2C_CONTROL_TRANSACTION_COUNT enum
7710 */
7711
7712typedef enum DOUT_I2C_CONTROL_TRANSACTION_COUNT {
7713DOUT_I2C_CONTROL_TRANS0 = 0x00000000,
7714DOUT_I2C_CONTROL_TRANS0_TRANS1 = 0x00000001,
7715DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2 = 0x00000002,
7716DOUT_I2C_CONTROL_TRANS0_TRANS1_TRANS2_TRANS3 = 0x00000003,
7717} DOUT_I2C_CONTROL_TRANSACTION_COUNT;
7718
7719/*
7720 * DOUT_I2C_ARBITRATION_SW_PRIORITY enum
7721 */
7722
7723typedef enum DOUT_I2C_ARBITRATION_SW_PRIORITY {
7724DOUT_I2C_ARBITRATION_SW_PRIORITY_NORMAL = 0x00000000,
7725DOUT_I2C_ARBITRATION_SW_PRIORITY_HIGH = 0x00000001,
7726DOUT_I2C_ARBITRATION_SW_PRIORITY_0_RESERVED = 0x00000002,
7727DOUT_I2C_ARBITRATION_SW_PRIORITY_1_RESERVED = 0x00000003,
7728} DOUT_I2C_ARBITRATION_SW_PRIORITY;
7729
7730/*
7731 * DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO enum
7732 */
7733
7734typedef enum DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO {
7735DOUT_I2C_ARBITRATION_SW_QUEUE_ENABLED = 0x00000000,
7736DOUT_I2C_ARBITRATION_SW_QUEUE_DISABLED = 0x00000001,
7737} DOUT_I2C_ARBITRATION_NO_QUEUED_SW_GO;
7738
7739/*
7740 * DOUT_I2C_ARBITRATION_ABORT_XFER enum
7741 */
7742
7743typedef enum DOUT_I2C_ARBITRATION_ABORT_XFER {
7744DOUT_I2C_ARBITRATION_NOT_ABORT_CURRENT_TRANSFER = 0x00000000,
7745DOUT_I2C_ARBITRATION_ABORT_CURRENT_TRANSFER = 0x00000001,
7746} DOUT_I2C_ARBITRATION_ABORT_XFER;
7747
7748/*
7749 * DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ enum
7750 */
7751
7752typedef enum DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ {
7753DOUT_I2C_ARBITRATION__NOT_USE_I2C_REG_REQ = 0x00000000,
7754DOUT_I2C_ARBITRATION__USE_I2C_REG_REQ = 0x00000001,
7755} DOUT_I2C_ARBITRATION_USE_I2C_REG_REQ;
7756
7757/*
7758 * DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG enum
7759 */
7760
7761typedef enum DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG {
7762DOUT_I2C_ARBITRATION_DONE__NOT_USING_I2C_REG = 0x00000000,
7763DOUT_I2C_ARBITRATION_DONE__USING_I2C_REG = 0x00000001,
7764} DOUT_I2C_ARBITRATION_DONE_USING_I2C_REG;
7765
7766/*
7767 * DOUT_I2C_ACK enum
7768 */
7769
7770typedef enum DOUT_I2C_ACK {
7771DOUT_I2C_NO_ACK = 0x00000000,
7772DOUT_I2C_ACK_TO_CLEAN = 0x00000001,
7773} DOUT_I2C_ACK;
7774
7775/*
7776 * DOUT_I2C_DDC_SPEED_THRESHOLD enum
7777 */
7778
7779typedef enum DOUT_I2C_DDC_SPEED_THRESHOLD {
7780DOUT_I2C_DDC_SPEED_THRESHOLD_BIG_THAN_ZERO = 0x00000000,
7781DOUT_I2C_DDC_SPEED_THRESHOLD_QUATER_OF_TOTAL_SAMPLE = 0x00000001,
7782DOUT_I2C_DDC_SPEED_THRESHOLD_HALF_OF_TOTAL_SAMPLE = 0x00000002,
7783DOUT_I2C_DDC_SPEED_THRESHOLD_THREE_QUATERS_OF_TOTAL_SAMPLE = 0x00000003,
7784} DOUT_I2C_DDC_SPEED_THRESHOLD;
7785
7786/*
7787 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN enum
7788 */
7789
7790typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN {
7791DOUT_I2C_DDC_SETUP_DATA_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
7792DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SDA = 0x00000001,
7793} DOUT_I2C_DDC_SETUP_DATA_DRIVE_EN;
7794
7795/*
7796 * DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL enum
7797 */
7798
7799typedef enum DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL {
7800DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_10MCLKS = 0x00000000,
7801DOUT_I2C_DDC_SETUP_DATA_DRIVE_FOR_20MCLKS = 0x00000001,
7802} DOUT_I2C_DDC_SETUP_DATA_DRIVE_SEL;
7803
7804/*
7805 * DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE enum
7806 */
7807
7808typedef enum DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE {
7809DOUT_I2C_DDC_SETUP_EDID_DETECT_CONNECT = 0x00000000,
7810DOUT_I2C_DDC_SETUP_EDID_DETECT_DISCONNECT = 0x00000001,
7811} DOUT_I2C_DDC_SETUP_EDID_DETECT_MODE;
7812
7813/*
7814 * DOUT_I2C_DDC_EDID_DETECT_STATUS enum
7815 */
7816
7817typedef enum DOUT_I2C_DDC_EDID_DETECT_STATUS {
7818DOUT_I2C_DDC_SETUP_EDID_CONNECT_DETECTED = 0x00000000,
7819DOUT_I2C_DDC_SETUP_EDID_DISCONNECT_DETECTED = 0x00000001,
7820} DOUT_I2C_DDC_EDID_DETECT_STATUS;
7821
7822/*
7823 * DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN enum
7824 */
7825
7826typedef enum DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN {
7827DOUT_I2C_DDC_SETUP_CLK_DRIVE_BY_EXTERNAL_RESISTOR = 0x00000000,
7828DOUT_I2C_DDC_SETUP_I2C_PAD_DRIVE_SCL = 0x00000001,
7829} DOUT_I2C_DDC_SETUP_CLK_DRIVE_EN;
7830
7831/*
7832 * DOUT_I2C_TRANSACTION_STOP_ON_NACK enum
7833 */
7834
7835typedef enum DOUT_I2C_TRANSACTION_STOP_ON_NACK {
7836DOUT_I2C_TRANSACTION_STOP_CURRENT_TRANS = 0x00000000,
7837DOUT_I2C_TRANSACTION_STOP_ALL_TRANS = 0x00000001,
7838} DOUT_I2C_TRANSACTION_STOP_ON_NACK;
7839
7840/*
7841 * DOUT_I2C_DATA_INDEX_WRITE enum
7842 */
7843
7844typedef enum DOUT_I2C_DATA_INDEX_WRITE {
7845DOUT_I2C_DATA__NOT_INDEX_WRITE = 0x00000000,
7846DOUT_I2C_DATA__INDEX_WRITE = 0x00000001,
7847} DOUT_I2C_DATA_INDEX_WRITE;
7848
7849/*
7850 * DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET enum
7851 */
7852
7853typedef enum DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET {
7854DOUT_I2C_EDID_NOT_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000000,
7855DOUT_I2C_EDID_SEND_RESET_BEFORE_EDID_READ_TRACTION = 0x00000001,
7856} DOUT_I2C_EDID_DETECT_CTRL_SEND_RESET;
7857
7858/*
7859 * DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE enum
7860 */
7861
7862typedef enum DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE {
7863DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__LEVEL = 0x00000000,
7864DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE__PULSE = 0x00000001,
7865} DOUT_I2C_READ_REQUEST_INTERRUPT_TYPE;
7866
7867/*******************************************************
7868 * DIO_MISC Enums
7869 *******************************************************/
7870
7871/*
7872 * DIOMEM_PWR_FORCE_CTRL enum
7873 */
7874
7875typedef enum DIOMEM_PWR_FORCE_CTRL {
7876DIOMEM_NO_FORCE_REQUEST = 0x00000000,
7877DIOMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
7878DIOMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
7879DIOMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
7880} DIOMEM_PWR_FORCE_CTRL;
7881
7882/*
7883 * DIOMEM_PWR_FORCE_CTRL2 enum
7884 */
7885
7886typedef enum DIOMEM_PWR_FORCE_CTRL2 {
7887DIOMEM_NO_FORCE_REQ = 0x00000000,
7888DIOMEM_FORCE_LIGHT_SLEEP_REQ = 0x00000001,
7889} DIOMEM_PWR_FORCE_CTRL2;
7890
7891/*
7892 * DIOMEM_PWR_DIS_CTRL enum
7893 */
7894
7895typedef enum DIOMEM_PWR_DIS_CTRL {
7896DIOMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
7897DIOMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
7898} DIOMEM_PWR_DIS_CTRL;
7899
7900/*
7901 * CLOCK_GATING_EN enum
7902 */
7903
7904typedef enum CLOCK_GATING_EN {
7905CLOCK_GATING_ENABLE = 0x00000000,
7906CLOCK_GATING_DISABLE = 0x00000001,
7907} CLOCK_GATING_EN;
7908
7909/*
7910 * DIOMEM_PWR_SEL_CTRL enum
7911 */
7912
7913typedef enum DIOMEM_PWR_SEL_CTRL {
7914DIOMEM_DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
7915DIOMEM_DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
7916DIOMEM_DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
7917} DIOMEM_PWR_SEL_CTRL;
7918
7919/*
7920 * DIOMEM_PWR_SEL_CTRL2 enum
7921 */
7922
7923typedef enum DIOMEM_PWR_SEL_CTRL2 {
7924DIOMEM_DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
7925DIOMEM_DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
7926} DIOMEM_PWR_SEL_CTRL2;
7927
7928/*
7929 * PM_ASSERT_RESET enum
7930 */
7931
7932typedef enum PM_ASSERT_RESET {
7933PM_ASSERT_RESET_0 = 0x00000000,
7934PM_ASSERT_RESET_1 = 0x00000001,
7935} PM_ASSERT_RESET;
7936
7937/*
7938 * DAC_MUX_SELECT enum
7939 */
7940
7941typedef enum DAC_MUX_SELECT {
7942DAC_MUX_SELECT_DACA = 0x00000000,
7943DAC_MUX_SELECT_DACB = 0x00000001,
7944} DAC_MUX_SELECT;
7945
7946/*
7947 * TMDS_MUX_SELECT enum
7948 */
7949
7950typedef enum TMDS_MUX_SELECT {
7951TMDS_MUX_SELECT_B = 0x00000000,
7952TMDS_MUX_SELECT_G = 0x00000001,
7953TMDS_MUX_SELECT_R = 0x00000002,
7954TMDS_MUX_SELECT_RESERVED = 0x00000003,
7955} TMDS_MUX_SELECT;
7956
7957/*
7958 * SOFT_RESET enum
7959 */
7960
7961typedef enum SOFT_RESET {
7962SOFT_RESET_0 = 0x00000000,
7963SOFT_RESET_1 = 0x00000001,
7964} SOFT_RESET;
7965
7966/*
7967 * GENERIC_STEREOSYNC_SEL enum
7968 */
7969
7970typedef enum GENERIC_STEREOSYNC_SEL {
7971GENERIC_STEREOSYNC_SEL_D1 = 0x00000000,
7972GENERIC_STEREOSYNC_SEL_D2 = 0x00000001,
7973GENERIC_STEREOSYNC_SEL_D3 = 0x00000002,
7974GENERIC_STEREOSYNC_SEL_D4 = 0x00000003,
7975GENERIC_STEREOSYNC_SEL_D5 = 0x00000004,
7976GENERIC_STEREOSYNC_SEL_D6 = 0x00000005,
7977GENERIC_STEREOSYNC_SEL_RESERVED = 0x00000006,
7978} GENERIC_STEREOSYNC_SEL;
7979
7980/*
7981 * DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE enum
7982 */
7983
7984typedef enum DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE {
7985DIO_HDMI_RXSTATUS_TIMER_TYPE_LEVEL = 0x00000000,
7986DIO_HDMI_RXSTATUS_TIMER_TYPE_PULSE = 0x00000001,
7987} DIO_HDMI_RXSTATUS_TIMER_CONTROL_DIO_HDMI_RXSTATUS_TIMER_TYPE;
7988
7989/*
7990 * DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE enum
7991 */
7992
7993typedef enum DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE {
7994DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_0 = 0x00000000,
7995DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE_1 = 0x00000001,
7996} DX_PROTECTION_DX_PIPE_ENC_REQUIRED_TYPE;
7997
7998/*******************************************************
7999 * DCIO Enums
8000 *******************************************************/
8001
8002/*
8003 * DCIO_DC_GENERICA_SEL enum
8004 */
8005
8006typedef enum DCIO_DC_GENERICA_SEL {
8007DCIO_GENERICA_SEL_DACA_STEREOSYNC = 0x00000000,
8008DCIO_GENERICA_SEL_STEREOSYNC = 0x00000001,
8009DCIO_GENERICA_SEL_DACA_PIXCLK = 0x00000002,
8010DCIO_GENERICA_SEL_DACB_PIXCLK = 0x00000003,
8011DCIO_GENERICA_SEL_DVOA_CTL3 = 0x00000004,
8012DCIO_GENERICA_SEL_P1_PLLCLK = 0x00000005,
8013DCIO_GENERICA_SEL_P2_PLLCLK = 0x00000006,
8014DCIO_GENERICA_SEL_DVOA_STEREOSYNC = 0x00000007,
8015DCIO_GENERICA_SEL_DACA_FIELD_NUMBER = 0x00000008,
8016DCIO_GENERICA_SEL_DACB_FIELD_NUMBER = 0x00000009,
8017DCIO_GENERICA_SEL_GENERICA_DCCG = 0x0000000a,
8018DCIO_GENERICA_SEL_SYNCEN = 0x0000000b,
8019DCIO_GENERICA_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
8020DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
8021DCIO_GENERICA_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
8022DCIO_GENERICA_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
8023DCIO_GENERICA_SEL_GENERICA_DPRX = 0x00000010,
8024DCIO_GENERICA_SEL_GENERICB_DPRX = 0x00000011,
8025} DCIO_DC_GENERICA_SEL;
8026
8027/*
8028 * DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL enum
8029 */
8030
8031typedef enum DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL {
8032DCIO_UNIPHYA_TEST_REFDIV_CLK = 0x00000000,
8033DCIO_UNIPHYB_TEST_REFDIV_CLK = 0x00000001,
8034DCIO_UNIPHYC_TEST_REFDIV_CLK = 0x00000002,
8035DCIO_UNIPHYD_TEST_REFDIV_CLK = 0x00000003,
8036DCIO_UNIPHYE_TEST_REFDIV_CLK = 0x00000004,
8037DCIO_UNIPHYF_TEST_REFDIV_CLK = 0x00000005,
8038DCIO_UNIPHYG_TEST_REFDIV_CLK = 0x00000006,
8039} DCIO_DC_GENERIC_UNIPHY_REFDIV_CLK_SEL;
8040
8041/*
8042 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL enum
8043 */
8044
8045typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL {
8046DCIO_UNIPHYA_FBDIV_CLK = 0x00000000,
8047DCIO_UNIPHYB_FBDIV_CLK = 0x00000001,
8048DCIO_UNIPHYC_FBDIV_CLK = 0x00000002,
8049DCIO_UNIPHYD_FBDIV_CLK = 0x00000003,
8050DCIO_UNIPHYE_FBDIV_CLK = 0x00000004,
8051DCIO_UNIPHYF_FBDIV_CLK = 0x00000005,
8052DCIO_UNIPHYG_FBDIV_CLK = 0x00000006,
8053} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_SEL;
8054
8055/*
8056 * DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL enum
8057 */
8058
8059typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL {
8060DCIO_UNIPHYA_FBDIV_SSC_CLK = 0x00000000,
8061DCIO_UNIPHYB_FBDIV_SSC_CLK = 0x00000001,
8062DCIO_UNIPHYC_FBDIV_SSC_CLK = 0x00000002,
8063DCIO_UNIPHYD_FBDIV_SSC_CLK = 0x00000003,
8064DCIO_UNIPHYE_FBDIV_SSC_CLK = 0x00000004,
8065DCIO_UNIPHYF_FBDIV_SSC_CLK = 0x00000005,
8066DCIO_UNIPHYG_FBDIV_SSC_CLK = 0x00000006,
8067} DCIO_DC_GENERIC_UNIPHY_FBDIV_SSC_CLK_SEL;
8068
8069/*
8070 * DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL enum
8071 */
8072
8073typedef enum DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL {
8074DCIO_UNIPHYA_TEST_FBDIV_CLK_DIV2 = 0x00000000,
8075DCIO_UNIPHYB_TEST_FBDIV_CLK_DIV2 = 0x00000001,
8076DCIO_UNIPHYC_TEST_FBDIV_CLK_DIV2 = 0x00000002,
8077DCIO_UNIPHYD_TEST_FBDIV_CLK_DIV2 = 0x00000003,
8078DCIO_UNIPHYE_TEST_FBDIV_CLK_DIV2 = 0x00000004,
8079DCIO_UNIPHYF_TEST_FBDIV_CLK_DIV2 = 0x00000005,
8080DCIO_UNIPHYG_TEST_FBDIV_CLK_DIV2 = 0x00000006,
8081} DCIO_DC_GENERIC_UNIPHY_FBDIV_CLK_DIV2_SEL;
8082
8083/*
8084 * DCIO_DC_GENERICB_SEL enum
8085 */
8086
8087typedef enum DCIO_DC_GENERICB_SEL {
8088DCIO_GENERICB_SEL_DACA_STEREOSYNC = 0x00000000,
8089DCIO_GENERICB_SEL_STEREOSYNC = 0x00000001,
8090DCIO_GENERICB_SEL_DACA_PIXCLK = 0x00000002,
8091DCIO_GENERICB_SEL_DACB_PIXCLK = 0x00000003,
8092DCIO_GENERICB_SEL_DVOA_CTL3 = 0x00000004,
8093DCIO_GENERICB_SEL_P1_PLLCLK = 0x00000005,
8094DCIO_GENERICB_SEL_P2_PLLCLK = 0x00000006,
8095DCIO_GENERICB_SEL_DVOA_STEREOSYNC = 0x00000007,
8096DCIO_GENERICB_SEL_DACA_FIELD_NUMBER = 0x00000008,
8097DCIO_GENERICB_SEL_DACB_FIELD_NUMBER = 0x00000009,
8098DCIO_GENERICB_SEL_GENERICB_DCCG = 0x0000000a,
8099DCIO_GENERICB_SEL_SYNCEN = 0x0000000b,
8100DCIO_GENERICB_SEL_UNIPHY_REFDIV_CLK = 0x0000000c,
8101DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK = 0x0000000d,
8102DCIO_GENERICB_SEL_UNIPHY_FBDIV_SSC_CLK = 0x0000000e,
8103DCIO_GENERICB_SEL_UNIPHY_FBDIV_CLK_DIV2 = 0x0000000f,
8104} DCIO_DC_GENERICB_SEL;
8105
8106/*
8107 * DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL enum
8108 */
8109
8110typedef enum DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL {
8111DCIO_HSYNCA_OUTPUT_SEL_DISABLE = 0x00000000,
8112DCIO_HSYNCA_OUTPUT_SEL_PPLL1 = 0x00000001,
8113DCIO_HSYNCA_OUTPUT_SEL_PPLL2 = 0x00000002,
8114DCIO_HSYNCA_OUTPUT_SEL_RESERVED = 0x00000003,
8115} DCIO_DC_REF_CLK_CNTL_HSYNCA_OUTPUT_SEL;
8116
8117/*
8118 * DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL enum
8119 */
8120
8121typedef enum DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL {
8122DCIO_GENLK_CLK_OUTPUT_SEL_DISABLE = 0x00000000,
8123DCIO_GENLK_CLK_OUTPUT_SEL_PPLL1 = 0x00000001,
8124DCIO_GENLK_CLK_OUTPUT_SEL_PPLL2 = 0x00000002,
8125DCIO_GENLK_CLK_OUTPUT_SEL_RESERVED_VALUE3 = 0x00000003,
8126} DCIO_DC_REF_CLK_CNTL_GENLK_CLK_OUTPUT_SEL;
8127
8128/*
8129 * DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION enum
8130 */
8131
8132typedef enum DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION {
8133DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_3_CLOCKS = 0x00000000,
8134DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_7_CLOCKS = 0x00000001,
8135DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_11_CLOCKS = 0x00000002,
8136DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_15_CLOCKS = 0x00000003,
8137DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_19_CLOCKS = 0x00000004,
8138DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_23_CLOCKS = 0x00000005,
8139DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_27_CLOCKS = 0x00000006,
8140DCIO_UNIPHY_MINIMUM_PIXVLD_LOW_DURATION_31_CLOCKS = 0x00000007,
8141} DCIO_UNIPHY_LINK_CNTL_MINIMUM_PIXVLD_LOW_DURATION;
8142
8143/*
8144 * DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT enum
8145 */
8146
8147typedef enum DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT {
8148DCIO_UNIPHY_CHANNEL_NO_INVERSION = 0x00000000,
8149DCIO_UNIPHY_CHANNEL_INVERTED = 0x00000001,
8150} DCIO_UNIPHY_LINK_CNTL_CHANNEL_INVERT;
8151
8152/*
8153 * DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK enum
8154 */
8155
8156typedef enum DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK {
8157DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_DISALLOW = 0x00000000,
8158DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW = 0x00000001,
8159DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_DEBOUNCED = 0x00000002,
8160DCIO_UNIPHY_LINK_ENABLE_HPD_MASK_ALLOW_TOGGLE_FILTERED = 0x00000003,
8161} DCIO_UNIPHY_LINK_CNTL_ENABLE_HPD_MASK;
8162
8163/*
8164 * DCIO_UNIPHY_CHANNEL_XBAR_SOURCE enum
8165 */
8166
8167typedef enum DCIO_UNIPHY_CHANNEL_XBAR_SOURCE {
8168DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH0 = 0x00000000,
8169DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH1 = 0x00000001,
8170DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH2 = 0x00000002,
8171DCIO_UNIPHY_CHANNEL_XBAR_SOURCE_CH3 = 0x00000003,
8172} DCIO_UNIPHY_CHANNEL_XBAR_SOURCE;
8173
8174/*
8175 * DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN enum
8176 */
8177
8178typedef enum DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN {
8179DCIO_VIP_MUX_EN_DVO = 0x00000000,
8180DCIO_VIP_MUX_EN_VIP = 0x00000001,
8181} DCIO_DC_DVODATA_CONFIG_VIP_MUX_EN;
8182
8183/*
8184 * DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN enum
8185 */
8186
8187typedef enum DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN {
8188DCIO_VIP_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
8189DCIO_VIP_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
8190} DCIO_DC_DVODATA_CONFIG_VIP_ALTER_MAPPING_EN;
8191
8192/*
8193 * DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN enum
8194 */
8195
8196typedef enum DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN {
8197DCIO_DVO_ALTER_MAPPING_EN_DEFAULT = 0x00000000,
8198DCIO_DVO_ALTER_MAPPING_EN_ALTERNATIVE = 0x00000001,
8199} DCIO_DC_DVODATA_CONFIG_DVO_ALTER_MAPPING_EN;
8200
8201/*
8202 * DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN enum
8203 */
8204
8205typedef enum DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN {
8206DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_ENABLE = 0x00000000,
8207DCIO_LVTMA_PWRSEQ_DISABLE_SYNCEN_CONTROL_OF_TX_DISABLE = 0x00000001,
8208} DCIO_LVTMA_PWRSEQ_CNTL_DISABLE_SYNCEN_CONTROL_OF_TX_EN;
8209
8210/*
8211 * DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE enum
8212 */
8213
8214typedef enum DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE {
8215DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_OFF = 0x00000000,
8216DCIO_LVTMA_PWRSEQ_TARGET_STATE_LCD_ON = 0x00000001,
8217} DCIO_LVTMA_PWRSEQ_CNTL_TARGET_STATE;
8218
8219/*
8220 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL enum
8221 */
8222
8223typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL {
8224DCIO_LVTMA_SYNCEN_POL_NON_INVERT = 0x00000000,
8225DCIO_LVTMA_SYNCEN_POL_INVERT = 0x00000001,
8226} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_SYNCEN_POL;
8227
8228/*
8229 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON enum
8230 */
8231
8232typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON {
8233DCIO_LVTMA_DIGON_OFF = 0x00000000,
8234DCIO_LVTMA_DIGON_ON = 0x00000001,
8235} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON;
8236
8237/*
8238 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL enum
8239 */
8240
8241typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL {
8242DCIO_LVTMA_DIGON_POL_NON_INVERT = 0x00000000,
8243DCIO_LVTMA_DIGON_POL_INVERT = 0x00000001,
8244} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_DIGON_POL;
8245
8246/*
8247 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON enum
8248 */
8249
8250typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON {
8251DCIO_LVTMA_BLON_OFF = 0x00000000,
8252DCIO_LVTMA_BLON_ON = 0x00000001,
8253} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON;
8254
8255/*
8256 * DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL enum
8257 */
8258
8259typedef enum DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL {
8260DCIO_LVTMA_BLON_POL_NON_INVERT = 0x00000000,
8261DCIO_LVTMA_BLON_POL_INVERT = 0x00000001,
8262} DCIO_LVTMA_PWRSEQ_CNTL_LVTMA_BLON_POL;
8263
8264/*
8265 * DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN enum
8266 */
8267
8268typedef enum DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN {
8269DCIO_LVTMA_VARY_BL_OVERRIDE_EN_BLON = 0x00000000,
8270DCIO_LVTMA_VARY_BL_OVERRIDE_EN_SEPARATE = 0x00000001,
8271} DCIO_LVTMA_PWRSEQ_DELAY2_LVTMA_VARY_BL_OVERRIDE_EN;
8272
8273/*
8274 * DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN enum
8275 */
8276
8277typedef enum DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN {
8278DCIO_BL_PWM_FRACTIONAL_DISABLE = 0x00000000,
8279DCIO_BL_PWM_FRACTIONAL_ENABLE = 0x00000001,
8280} DCIO_BL_PWM_CNTL_BL_PWM_FRACTIONAL_EN;
8281
8282/*
8283 * DCIO_BL_PWM_CNTL_BL_PWM_EN enum
8284 */
8285
8286typedef enum DCIO_BL_PWM_CNTL_BL_PWM_EN {
8287DCIO_BL_PWM_DISABLE = 0x00000000,
8288DCIO_BL_PWM_ENABLE = 0x00000001,
8289} DCIO_BL_PWM_CNTL_BL_PWM_EN;
8290
8291/*
8292 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE enum
8293 */
8294
8295typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE {
8296DCIO_BL_PWM_OVERRIDE_BL_OUT_DISABLE = 0x00000000,
8297DCIO_BL_PWM_OVERRIDE_BL_OUT_ENABLE = 0x00000001,
8298} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_BL_OUT_ENABLE;
8299
8300/*
8301 * DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN enum
8302 */
8303
8304typedef enum DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN {
8305DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_NORMAL = 0x00000000,
8306DCIO_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN_PWM = 0x00000001,
8307} DCIO_BL_PWM_CNTL2_BL_PWM_OVERRIDE_LVTMA_PWRSEQ_EN;
8308
8309/*
8310 * DCIO_BL_PWM_GRP1_REG_LOCK enum
8311 */
8312
8313typedef enum DCIO_BL_PWM_GRP1_REG_LOCK {
8314DCIO_BL_PWM_GRP1_REG_LOCK_DISABLE = 0x00000000,
8315DCIO_BL_PWM_GRP1_REG_LOCK_ENABLE = 0x00000001,
8316} DCIO_BL_PWM_GRP1_REG_LOCK;
8317
8318/*
8319 * DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START enum
8320 */
8321
8322typedef enum DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START {
8323DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_DISABLE = 0x00000000,
8324DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START_ENABLE = 0x00000001,
8325} DCIO_BL_PWM_GRP1_UPDATE_AT_FRAME_START;
8326
8327/*
8328 * DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL enum
8329 */
8330
8331typedef enum DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL {
8332DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER1 = 0x00000000,
8333DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER2 = 0x00000001,
8334DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER3 = 0x00000002,
8335DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER4 = 0x00000003,
8336DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER5 = 0x00000004,
8337DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL_CONTROLLER6 = 0x00000005,
8338} DCIO_BL_PWM_GRP1_FRAME_START_DISP_SEL;
8339
8340/*
8341 * DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN enum
8342 */
8343
8344typedef enum DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN {
8345DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL_PWM = 0x00000000,
8346DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN_BL1_PWM = 0x00000001,
8347} DCIO_BL_PWM_GRP1_READBACK_DB_REG_VALUE_EN;
8348
8349/*
8350 * DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN enum
8351 */
8352
8353typedef enum DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN {
8354DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_ENABLE = 0x00000000,
8355DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_DISABLE = 0x00000001,
8356} DCIO_BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN;
8357
8358/*
8359 * DCIO_GSL_SEL enum
8360 */
8361
8362typedef enum DCIO_GSL_SEL {
8363DCIO_GSL_SEL_GROUP_0 = 0x00000000,
8364DCIO_GSL_SEL_GROUP_1 = 0x00000001,
8365DCIO_GSL_SEL_GROUP_2 = 0x00000002,
8366} DCIO_GSL_SEL;
8367
8368/*
8369 * DCIO_GENLK_CLK_GSL_MASK enum
8370 */
8371
8372typedef enum DCIO_GENLK_CLK_GSL_MASK {
8373DCIO_GENLK_CLK_GSL_MASK_NO = 0x00000000,
8374DCIO_GENLK_CLK_GSL_MASK_TIMING = 0x00000001,
8375DCIO_GENLK_CLK_GSL_MASK_STEREO = 0x00000002,
8376} DCIO_GENLK_CLK_GSL_MASK;
8377
8378/*
8379 * DCIO_GENLK_VSYNC_GSL_MASK enum
8380 */
8381
8382typedef enum DCIO_GENLK_VSYNC_GSL_MASK {
8383DCIO_GENLK_VSYNC_GSL_MASK_NO = 0x00000000,
8384DCIO_GENLK_VSYNC_GSL_MASK_TIMING = 0x00000001,
8385DCIO_GENLK_VSYNC_GSL_MASK_STEREO = 0x00000002,
8386} DCIO_GENLK_VSYNC_GSL_MASK;
8387
8388/*
8389 * DCIO_SWAPLOCK_A_GSL_MASK enum
8390 */
8391
8392typedef enum DCIO_SWAPLOCK_A_GSL_MASK {
8393DCIO_SWAPLOCK_A_GSL_MASK_NO = 0x00000000,
8394DCIO_SWAPLOCK_A_GSL_MASK_TIMING = 0x00000001,
8395DCIO_SWAPLOCK_A_GSL_MASK_STEREO = 0x00000002,
8396} DCIO_SWAPLOCK_A_GSL_MASK;
8397
8398/*
8399 * DCIO_SWAPLOCK_B_GSL_MASK enum
8400 */
8401
8402typedef enum DCIO_SWAPLOCK_B_GSL_MASK {
8403DCIO_SWAPLOCK_B_GSL_MASK_NO = 0x00000000,
8404DCIO_SWAPLOCK_B_GSL_MASK_TIMING = 0x00000001,
8405DCIO_SWAPLOCK_B_GSL_MASK_STEREO = 0x00000002,
8406} DCIO_SWAPLOCK_B_GSL_MASK;
8407
8408/*
8409 * DCIO_DC_GPU_TIMER_START_POSITION enum
8410 */
8411
8412typedef enum DCIO_DC_GPU_TIMER_START_POSITION {
8413DCIO_GPU_TIMER_START_0_END_27 = 0x00000000,
8414DCIO_GPU_TIMER_START_1_END_28 = 0x00000001,
8415DCIO_GPU_TIMER_START_2_END_29 = 0x00000002,
8416DCIO_GPU_TIMER_START_3_END_30 = 0x00000003,
8417DCIO_GPU_TIMER_START_4_END_31 = 0x00000004,
8418DCIO_GPU_TIMER_START_6_END_33 = 0x00000005,
8419DCIO_GPU_TIMER_START_8_END_35 = 0x00000006,
8420DCIO_GPU_TIMER_START_10_END_37 = 0x00000007,
8421} DCIO_DC_GPU_TIMER_START_POSITION;
8422
8423/*
8424 * DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL enum
8425 */
8426
8427typedef enum DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL {
8428DCIO_TEST_CLK_SEL_DISPCLK = 0x00000000,
8429DCIO_TEST_CLK_SEL_GATED_DISPCLK = 0x00000001,
8430DCIO_TEST_CLK_SEL_SOCCLK = 0x00000002,
8431} DCIO_CLOCK_CNTL_DCIO_TEST_CLK_SEL;
8432
8433/*
8434 * DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS enum
8435 */
8436
8437typedef enum DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS {
8438DCIO_DISPCLK_R_DCIO_GATE_DISABLE = 0x00000000,
8439DCIO_DISPCLK_R_DCIO_GATE_ENABLE = 0x00000001,
8440} DCIO_CLOCK_CNTL_DISPCLK_R_DCIO_GATE_DIS;
8441
8442/*
8443 * DCIO_DIO_OTG_EXT_VSYNC_MUX enum
8444 */
8445
8446typedef enum DCIO_DIO_OTG_EXT_VSYNC_MUX {
8447DCIO_EXT_VSYNC_MUX_SWAPLOCKB = 0x00000000,
8448DCIO_EXT_VSYNC_MUX_OTG0 = 0x00000001,
8449DCIO_EXT_VSYNC_MUX_OTG1 = 0x00000002,
8450DCIO_EXT_VSYNC_MUX_OTG2 = 0x00000003,
8451DCIO_EXT_VSYNC_MUX_OTG3 = 0x00000004,
8452DCIO_EXT_VSYNC_MUX_OTG4 = 0x00000005,
8453DCIO_EXT_VSYNC_MUX_OTG5 = 0x00000006,
8454DCIO_EXT_VSYNC_MUX_GENERICB = 0x00000007,
8455} DCIO_DIO_OTG_EXT_VSYNC_MUX;
8456
8457/*
8458 * DCIO_DIO_EXT_VSYNC_MASK enum
8459 */
8460
8461typedef enum DCIO_DIO_EXT_VSYNC_MASK {
8462DCIO_EXT_VSYNC_MASK_NONE = 0x00000000,
8463DCIO_EXT_VSYNC_MASK_PIPE0 = 0x00000001,
8464DCIO_EXT_VSYNC_MASK_PIPE1 = 0x00000002,
8465DCIO_EXT_VSYNC_MASK_PIPE2 = 0x00000003,
8466DCIO_EXT_VSYNC_MASK_PIPE3 = 0x00000004,
8467DCIO_EXT_VSYNC_MASK_PIPE4 = 0x00000005,
8468DCIO_EXT_VSYNC_MASK_PIPE5 = 0x00000006,
8469DCIO_EXT_VSYNC_MASK_NONE_DUPLICATE = 0x00000007,
8470} DCIO_DIO_EXT_VSYNC_MASK;
8471
8472/*
8473 * DCIO_DSYNC_SOFT_RESET enum
8474 */
8475
8476typedef enum DCIO_DSYNC_SOFT_RESET {
8477DCIO_DSYNC_SOFT_RESET_DEASSERT = 0x00000000,
8478DCIO_DSYNC_SOFT_RESET_ASSERT = 0x00000001,
8479} DCIO_DSYNC_SOFT_RESET;
8480
8481/*
8482 * DCIO_DACA_SOFT_RESET enum
8483 */
8484
8485typedef enum DCIO_DACA_SOFT_RESET {
8486DCIO_DACA_SOFT_RESET_DEASSERT = 0x00000000,
8487DCIO_DACA_SOFT_RESET_ASSERT = 0x00000001,
8488} DCIO_DACA_SOFT_RESET;
8489
8490/*
8491 * DCIO_DCRXPHY_SOFT_RESET enum
8492 */
8493
8494typedef enum DCIO_DCRXPHY_SOFT_RESET {
8495DCIO_DCRXPHY_SOFT_RESET_DEASSERT = 0x00000000,
8496DCIO_DCRXPHY_SOFT_RESET_ASSERT = 0x00000001,
8497} DCIO_DCRXPHY_SOFT_RESET;
8498
8499/*
8500 * DCIO_DPHY_LANE_SEL enum
8501 */
8502
8503typedef enum DCIO_DPHY_LANE_SEL {
8504DCIO_DPHY_LANE_SEL_LANE0 = 0x00000000,
8505DCIO_DPHY_LANE_SEL_LANE1 = 0x00000001,
8506DCIO_DPHY_LANE_SEL_LANE2 = 0x00000002,
8507DCIO_DPHY_LANE_SEL_LANE3 = 0x00000003,
8508} DCIO_DPHY_LANE_SEL;
8509
8510/*
8511 * DCIO_DPCS_INTERRUPT_TYPE enum
8512 */
8513
8514typedef enum DCIO_DPCS_INTERRUPT_TYPE {
8515DCIO_DPCS_INTERRUPT_TYPE_LEVEL_BASED = 0x00000000,
8516DCIO_DPCS_INTERRUPT_TYPE_PULSE_BASED = 0x00000001,
8517} DCIO_DPCS_INTERRUPT_TYPE;
8518
8519/*
8520 * DCIO_DPCS_INTERRUPT_MASK enum
8521 */
8522
8523typedef enum DCIO_DPCS_INTERRUPT_MASK {
8524DCIO_DPCS_INTERRUPT_DISABLE = 0x00000000,
8525DCIO_DPCS_INTERRUPT_ENABLE = 0x00000001,
8526} DCIO_DPCS_INTERRUPT_MASK;
8527
8528/*
8529 * DCIO_DC_GPU_TIMER_READ_SELECT enum
8530 */
8531
8532typedef enum DCIO_DC_GPU_TIMER_READ_SELECT {
8533DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE = 0x00000000,
8534DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE = 0x00000001,
8535DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_P_FLIP = 0x00000002,
8536DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_P_FLIP = 0x00000003,
8537DCIO_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM = 0x00000004,
8538DCIO_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM = 0x00000005,
8539} DCIO_DC_GPU_TIMER_READ_SELECT;
8540
8541/*
8542 * DCIO_IMPCAL_STEP_DELAY enum
8543 */
8544
8545typedef enum DCIO_IMPCAL_STEP_DELAY {
8546DCIO_IMPCAL_STEP_DELAY_1us = 0x00000000,
8547DCIO_IMPCAL_STEP_DELAY_2us = 0x00000001,
8548DCIO_IMPCAL_STEP_DELAY_3us = 0x00000002,
8549DCIO_IMPCAL_STEP_DELAY_4us = 0x00000003,
8550DCIO_IMPCAL_STEP_DELAY_5us = 0x00000004,
8551DCIO_IMPCAL_STEP_DELAY_6us = 0x00000005,
8552DCIO_IMPCAL_STEP_DELAY_7us = 0x00000006,
8553DCIO_IMPCAL_STEP_DELAY_8us = 0x00000007,
8554DCIO_IMPCAL_STEP_DELAY_9us = 0x00000008,
8555DCIO_IMPCAL_STEP_DELAY_10us = 0x00000009,
8556DCIO_IMPCAL_STEP_DELAY_11us = 0x0000000a,
8557DCIO_IMPCAL_STEP_DELAY_12us = 0x0000000b,
8558DCIO_IMPCAL_STEP_DELAY_13us = 0x0000000c,
8559DCIO_IMPCAL_STEP_DELAY_14us = 0x0000000d,
8560DCIO_IMPCAL_STEP_DELAY_15us = 0x0000000e,
8561DCIO_IMPCAL_STEP_DELAY_16us = 0x0000000f,
8562} DCIO_IMPCAL_STEP_DELAY;
8563
8564/*
8565 * DCIO_UNIPHY_IMPCAL_SEL enum
8566 */
8567
8568typedef enum DCIO_UNIPHY_IMPCAL_SEL {
8569DCIO_UNIPHY_IMPCAL_SEL_TEMPERATURE = 0x00000000,
8570DCIO_UNIPHY_IMPCAL_SEL_BINARY = 0x00000001,
8571} DCIO_UNIPHY_IMPCAL_SEL;
8572
8573/*******************************************************
8574 * DCIO_CHIP Enums
8575 *******************************************************/
8576
8577/*
8578 * DCIOCHIP_HPD_SEL enum
8579 */
8580
8581typedef enum DCIOCHIP_HPD_SEL {
8582DCIOCHIP_HPD_SEL_ASYNC = 0x00000000,
8583DCIOCHIP_HPD_SEL_CLOCKED = 0x00000001,
8584} DCIOCHIP_HPD_SEL;
8585
8586/*
8587 * DCIOCHIP_PAD_MODE enum
8588 */
8589
8590typedef enum DCIOCHIP_PAD_MODE {
8591DCIOCHIP_PAD_MODE_DDC = 0x00000000,
8592DCIOCHIP_PAD_MODE_DP = 0x00000001,
8593} DCIOCHIP_PAD_MODE;
8594
8595/*
8596 * DCIOCHIP_AUXSLAVE_PAD_MODE enum
8597 */
8598
8599typedef enum DCIOCHIP_AUXSLAVE_PAD_MODE {
8600DCIOCHIP_AUXSLAVE_PAD_MODE_I2C = 0x00000000,
8601DCIOCHIP_AUXSLAVE_PAD_MODE_AUX = 0x00000001,
8602} DCIOCHIP_AUXSLAVE_PAD_MODE;
8603
8604/*
8605 * DCIOCHIP_INVERT enum
8606 */
8607
8608typedef enum DCIOCHIP_INVERT {
8609DCIOCHIP_POL_NON_INVERT = 0x00000000,
8610DCIOCHIP_POL_INVERT = 0x00000001,
8611} DCIOCHIP_INVERT;
8612
8613/*
8614 * DCIOCHIP_PD_EN enum
8615 */
8616
8617typedef enum DCIOCHIP_PD_EN {
8618DCIOCHIP_PD_EN_NOTALLOW = 0x00000000,
8619DCIOCHIP_PD_EN_ALLOW = 0x00000001,
8620} DCIOCHIP_PD_EN;
8621
8622/*
8623 * DCIOCHIP_GPIO_MASK_EN enum
8624 */
8625
8626typedef enum DCIOCHIP_GPIO_MASK_EN {
8627DCIOCHIP_GPIO_MASK_EN_HARDWARE = 0x00000000,
8628DCIOCHIP_GPIO_MASK_EN_SOFTWARE = 0x00000001,
8629} DCIOCHIP_GPIO_MASK_EN;
8630
8631/*
8632 * DCIOCHIP_MASK enum
8633 */
8634
8635typedef enum DCIOCHIP_MASK {
8636DCIOCHIP_MASK_DISABLE = 0x00000000,
8637DCIOCHIP_MASK_ENABLE = 0x00000001,
8638} DCIOCHIP_MASK;
8639
8640/*
8641 * DCIOCHIP_GPIO_I2C_MASK enum
8642 */
8643
8644typedef enum DCIOCHIP_GPIO_I2C_MASK {
8645DCIOCHIP_GPIO_I2C_MASK_DISABLE = 0x00000000,
8646DCIOCHIP_GPIO_I2C_MASK_ENABLE = 0x00000001,
8647} DCIOCHIP_GPIO_I2C_MASK;
8648
8649/*
8650 * DCIOCHIP_GPIO_I2C_DRIVE enum
8651 */
8652
8653typedef enum DCIOCHIP_GPIO_I2C_DRIVE {
8654DCIOCHIP_GPIO_I2C_DRIVE_LOW = 0x00000000,
8655DCIOCHIP_GPIO_I2C_DRIVE_HIGH = 0x00000001,
8656} DCIOCHIP_GPIO_I2C_DRIVE;
8657
8658/*
8659 * DCIOCHIP_GPIO_I2C_EN enum
8660 */
8661
8662typedef enum DCIOCHIP_GPIO_I2C_EN {
8663DCIOCHIP_GPIO_I2C_DISABLE = 0x00000000,
8664DCIOCHIP_GPIO_I2C_ENABLE = 0x00000001,
8665} DCIOCHIP_GPIO_I2C_EN;
8666
8667/*
8668 * DCIOCHIP_MASK_4BIT enum
8669 */
8670
8671typedef enum DCIOCHIP_MASK_4BIT {
8672DCIOCHIP_MASK_4BIT_DISABLE = 0x00000000,
8673DCIOCHIP_MASK_4BIT_ENABLE = 0x0000000f,
8674} DCIOCHIP_MASK_4BIT;
8675
8676/*
8677 * DCIOCHIP_ENABLE_4BIT enum
8678 */
8679
8680typedef enum DCIOCHIP_ENABLE_4BIT {
8681DCIOCHIP_4BIT_DISABLE = 0x00000000,
8682DCIOCHIP_4BIT_ENABLE = 0x0000000f,
8683} DCIOCHIP_ENABLE_4BIT;
8684
8685/*
8686 * DCIOCHIP_MASK_5BIT enum
8687 */
8688
8689typedef enum DCIOCHIP_MASK_5BIT {
8690DCIOCHIP_MASIK_5BIT_DISABLE = 0x00000000,
8691DCIOCHIP_MASIK_5BIT_ENABLE = 0x0000001f,
8692} DCIOCHIP_MASK_5BIT;
8693
8694/*
8695 * DCIOCHIP_ENABLE_5BIT enum
8696 */
8697
8698typedef enum DCIOCHIP_ENABLE_5BIT {
8699DCIOCHIP_5BIT_DISABLE = 0x00000000,
8700DCIOCHIP_5BIT_ENABLE = 0x0000001f,
8701} DCIOCHIP_ENABLE_5BIT;
8702
8703/*
8704 * DCIOCHIP_MASK_2BIT enum
8705 */
8706
8707typedef enum DCIOCHIP_MASK_2BIT {
8708DCIOCHIP_MASK_2BIT_DISABLE = 0x00000000,
8709DCIOCHIP_MASK_2BIT_ENABLE = 0x00000003,
8710} DCIOCHIP_MASK_2BIT;
8711
8712/*
8713 * DCIOCHIP_ENABLE_2BIT enum
8714 */
8715
8716typedef enum DCIOCHIP_ENABLE_2BIT {
8717DCIOCHIP_2BIT_DISABLE = 0x00000000,
8718DCIOCHIP_2BIT_ENABLE = 0x00000003,
8719} DCIOCHIP_ENABLE_2BIT;
8720
8721/*
8722 * DCIOCHIP_REF_27_SRC_SEL enum
8723 */
8724
8725typedef enum DCIOCHIP_REF_27_SRC_SEL {
8726DCIOCHIP_REF_27_SRC_SEL_XTAL_DIVIDER = 0x00000000,
8727DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_DIVIDER = 0x00000001,
8728DCIOCHIP_REF_27_SRC_SEL_XTAL_BYPASS = 0x00000002,
8729DCIOCHIP_REF_27_SRC_SEL_DISP_CLKIN2_BYPASS = 0x00000003,
8730} DCIOCHIP_REF_27_SRC_SEL;
8731
8732/*
8733 * DCIOCHIP_DVO_VREFPON enum
8734 */
8735
8736typedef enum DCIOCHIP_DVO_VREFPON {
8737DCIOCHIP_DVO_VREFPON_DISABLE = 0x00000000,
8738DCIOCHIP_DVO_VREFPON_ENABLE = 0x00000001,
8739} DCIOCHIP_DVO_VREFPON;
8740
8741/*
8742 * DCIOCHIP_DVO_VREFSEL enum
8743 */
8744
8745typedef enum DCIOCHIP_DVO_VREFSEL {
8746DCIOCHIP_DVO_VREFSEL_ONCHIP = 0x00000000,
8747DCIOCHIP_DVO_VREFSEL_EXTERNAL = 0x00000001,
8748} DCIOCHIP_DVO_VREFSEL;
8749
8750/*
8751 * DCIOCHIP_SPDIF1_IMODE enum
8752 */
8753
8754typedef enum DCIOCHIP_SPDIF1_IMODE {
8755DCIOCHIP_SPDIF1_IMODE_OE_A = 0x00000000,
8756DCIOCHIP_SPDIF1_IMODE_TSTE_TSTO = 0x00000001,
8757} DCIOCHIP_SPDIF1_IMODE;
8758
8759/*
8760 * DCIOCHIP_AUX_FALLSLEWSEL enum
8761 */
8762
8763typedef enum DCIOCHIP_AUX_FALLSLEWSEL {
8764DCIOCHIP_AUX_FALLSLEWSEL_LOW = 0x00000000,
8765DCIOCHIP_AUX_FALLSLEWSEL_HIGH0 = 0x00000001,
8766DCIOCHIP_AUX_FALLSLEWSEL_HIGH1 = 0x00000002,
8767DCIOCHIP_AUX_FALLSLEWSEL_ULTRAHIGH = 0x00000003,
8768} DCIOCHIP_AUX_FALLSLEWSEL;
8769
8770/*
8771 * DCIOCHIP_I2C_FALLSLEWSEL enum
8772 */
8773
8774typedef enum DCIOCHIP_I2C_FALLSLEWSEL {
8775DCIOCHIP_I2C_FALLSLEWSEL_00 = 0x00000000,
8776DCIOCHIP_I2C_FALLSLEWSEL_01 = 0x00000001,
8777DCIOCHIP_I2C_FALLSLEWSEL_10 = 0x00000002,
8778DCIOCHIP_I2C_FALLSLEWSEL_11 = 0x00000003,
8779} DCIOCHIP_I2C_FALLSLEWSEL;
8780
8781/*
8782 * DCIOCHIP_AUX_SPIKESEL enum
8783 */
8784
8785typedef enum DCIOCHIP_AUX_SPIKESEL {
8786DCIOCHIP_AUX_SPIKESEL_50NS = 0x00000000,
8787DCIOCHIP_AUX_SPIKESEL_10NS = 0x00000001,
8788} DCIOCHIP_AUX_SPIKESEL;
8789
8790/*
8791 * DCIOCHIP_AUX_CSEL0P9 enum
8792 */
8793
8794typedef enum DCIOCHIP_AUX_CSEL0P9 {
8795DCIOCHIP_AUX_CSEL_DEC1P0 = 0x00000000,
8796DCIOCHIP_AUX_CSEL_DEC0P9 = 0x00000001,
8797} DCIOCHIP_AUX_CSEL0P9;
8798
8799/*
8800 * DCIOCHIP_AUX_CSEL1P1 enum
8801 */
8802
8803typedef enum DCIOCHIP_AUX_CSEL1P1 {
8804DCIOCHIP_AUX_CSEL_INC1P0 = 0x00000000,
8805DCIOCHIP_AUX_CSEL_INC1P1 = 0x00000001,
8806} DCIOCHIP_AUX_CSEL1P1;
8807
8808/*
8809 * DCIOCHIP_AUX_RSEL0P9 enum
8810 */
8811
8812typedef enum DCIOCHIP_AUX_RSEL0P9 {
8813DCIOCHIP_AUX_RSEL_DEC1P0 = 0x00000000,
8814DCIOCHIP_AUX_RSEL_DEC0P9 = 0x00000001,
8815} DCIOCHIP_AUX_RSEL0P9;
8816
8817/*
8818 * DCIOCHIP_AUX_RSEL1P1 enum
8819 */
8820
8821typedef enum DCIOCHIP_AUX_RSEL1P1 {
8822DCIOCHIP_AUX_RSEL_INC1P0 = 0x00000000,
8823DCIOCHIP_AUX_RSEL_INC1P1 = 0x00000001,
8824} DCIOCHIP_AUX_RSEL1P1;
8825
8826/*
8827 * DCIOCHIP_AUX_HYS_TUNE enum
8828 */
8829
8830typedef enum DCIOCHIP_AUX_HYS_TUNE {
8831DCIOCHIP_AUX_HYS_TUNE_0 = 0x00000000,
8832DCIOCHIP_AUX_HYS_TUNE_1 = 0x00000001,
8833DCIOCHIP_AUX_HYS_TUNE_2 = 0x00000002,
8834DCIOCHIP_AUX_HYS_TUNE_3 = 0x00000003,
8835} DCIOCHIP_AUX_HYS_TUNE;
8836
8837/*
8838 * DCIOCHIP_AUX_VOD_TUNE enum
8839 */
8840
8841typedef enum DCIOCHIP_AUX_VOD_TUNE {
8842DCIOCHIP_AUX_VOD_TUNE_0 = 0x00000000,
8843DCIOCHIP_AUX_VOD_TUNE_1 = 0x00000001,
8844DCIOCHIP_AUX_VOD_TUNE_2 = 0x00000002,
8845DCIOCHIP_AUX_VOD_TUNE_3 = 0x00000003,
8846} DCIOCHIP_AUX_VOD_TUNE;
8847
8848/*
8849 * DCIOCHIP_I2C_VPH_1V2_EN enum
8850 */
8851
8852typedef enum DCIOCHIP_I2C_VPH_1V2_EN {
8853DCIOCHIP_I2C_VPH_1V2_EN_0 = 0x00000000,
8854DCIOCHIP_I2C_VPH_1V2_EN_1 = 0x00000001,
8855} DCIOCHIP_I2C_VPH_1V2_EN;
8856
8857/*
8858 * DCIOCHIP_I2C_COMPSEL enum
8859 */
8860
8861typedef enum DCIOCHIP_I2C_COMPSEL {
8862DCIOCHIP_I2C_REC_SCHMIT = 0x00000000,
8863DCIOCHIP_I2C_REC_COMPARATOR = 0x00000001,
8864} DCIOCHIP_I2C_COMPSEL;
8865
8866/*
8867 * DCIOCHIP_AUX_ALL_PWR_OK enum
8868 */
8869
8870typedef enum DCIOCHIP_AUX_ALL_PWR_OK {
8871DCIOCHIP_AUX_ALL_PWR_OK_0 = 0x00000000,
8872DCIOCHIP_AUX_ALL_PWR_OK_1 = 0x00000001,
8873} DCIOCHIP_AUX_ALL_PWR_OK;
8874
8875/*
8876 * DCIOCHIP_I2C_RECEIVER_SEL enum
8877 */
8878
8879typedef enum DCIOCHIP_I2C_RECEIVER_SEL {
8880DCIOCHIP_I2C_RECEIVER_SEL_0 = 0x00000000,
8881DCIOCHIP_I2C_RECEIVER_SEL_1 = 0x00000001,
8882DCIOCHIP_I2C_RECEIVER_SEL_2 = 0x00000002,
8883DCIOCHIP_I2C_RECEIVER_SEL_3 = 0x00000003,
8884} DCIOCHIP_I2C_RECEIVER_SEL;
8885
8886/*
8887 * DCIOCHIP_AUX_RECEIVER_SEL enum
8888 */
8889
8890typedef enum DCIOCHIP_AUX_RECEIVER_SEL {
8891DCIOCHIP_AUX_RECEIVER_SEL_0 = 0x00000000,
8892DCIOCHIP_AUX_RECEIVER_SEL_1 = 0x00000001,
8893DCIOCHIP_AUX_RECEIVER_SEL_2 = 0x00000002,
8894DCIOCHIP_AUX_RECEIVER_SEL_3 = 0x00000003,
8895} DCIOCHIP_AUX_RECEIVER_SEL;
8896
8897/*******************************************************
8898 * AZCONTROLLER Enums
8899 *******************************************************/
8900
8901/*
8902 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL enum
8903 */
8904
8905typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL {
8906GENERIC_AZ_CONTROLLER_REGISTER_DISABLE = 0x00000000,
8907GENERIC_AZ_CONTROLLER_REGISTER_ENABLE = 0x00000001,
8908} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL;
8909
8910/*
8911 * GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED enum
8912 */
8913
8914typedef enum GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED {
8915GENERIC_AZ_CONTROLLER_REGISTER_DISABLE_RESERVED = 0x00000000,
8916GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_RESERVED = 0x00000001,
8917} GENERIC_AZ_CONTROLLER_REGISTER_ENABLE_CONTROL_RESERVED;
8918
8919/*
8920 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS enum
8921 */
8922
8923typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS {
8924GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET = 0x00000000,
8925GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET = 0x00000001,
8926} GENERIC_AZ_CONTROLLER_REGISTER_STATUS;
8927
8928/*
8929 * GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED enum
8930 */
8931
8932typedef enum GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED {
8933GENERIC_AZ_CONTROLLER_REGISTER_STATUS_NOT_SET_RESERVED = 0x00000000,
8934GENERIC_AZ_CONTROLLER_REGISTER_STATUS_SET_RESERVED = 0x00000001,
8935} GENERIC_AZ_CONTROLLER_REGISTER_STATUS_RESERVED;
8936
8937/*
8938 * AZ_GLOBAL_CAPABILITIES enum
8939 */
8940
8941typedef enum AZ_GLOBAL_CAPABILITIES {
8942AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_NOT_SUPPORTED = 0x00000000,
8943AZ_GLOBAL_CAPABILITIES_SIXTY_FOUR_BIT_ADDRESS_SUPPORTED = 0x00000001,
8944} AZ_GLOBAL_CAPABILITIES;
8945
8946/*
8947 * GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE enum
8948 */
8949
8950typedef enum GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE {
8951ACCEPT_UNSOLICITED_RESPONSE_NOT_ENABLE = 0x00000000,
8952ACCEPT_UNSOLICITED_RESPONSE_ENABLE = 0x00000001,
8953} GLOBAL_CONTROL_ACCEPT_UNSOLICITED_RESPONSE;
8954
8955/*
8956 * GLOBAL_CONTROL_FLUSH_CONTROL enum
8957 */
8958
8959typedef enum GLOBAL_CONTROL_FLUSH_CONTROL {
8960FLUSH_CONTROL_FLUSH_NOT_STARTED = 0x00000000,
8961FLUSH_CONTROL_FLUSH_STARTED = 0x00000001,
8962} GLOBAL_CONTROL_FLUSH_CONTROL;
8963
8964/*
8965 * GLOBAL_CONTROL_CONTROLLER_RESET enum
8966 */
8967
8968typedef enum GLOBAL_CONTROL_CONTROLLER_RESET {
8969CONTROLLER_RESET_AZ_CONTROLLER_IN_RESET = 0x00000000,
8970CONTROLLER_RESET_AZ_CONTROLLER_NOT_IN_RESET = 0x00000001,
8971} GLOBAL_CONTROL_CONTROLLER_RESET;
8972
8973/*
8974 * AZ_STATE_CHANGE_STATUS enum
8975 */
8976
8977typedef enum AZ_STATE_CHANGE_STATUS {
8978AZ_STATE_CHANGE_STATUS_CODEC_NOT_PRESENT = 0x00000000,
8979AZ_STATE_CHANGE_STATUS_CODEC_PRESENT = 0x00000001,
8980} AZ_STATE_CHANGE_STATUS;
8981
8982/*
8983 * GLOBAL_STATUS_FLUSH_STATUS enum
8984 */
8985
8986typedef enum GLOBAL_STATUS_FLUSH_STATUS {
8987GLOBAL_STATUS_FLUSH_STATUS_FLUSH_NOT_ENDED = 0x00000000,
8988GLOBAL_STATUS_FLUSH_STATUS_FLUSH_ENDED = 0x00000001,
8989} GLOBAL_STATUS_FLUSH_STATUS;
8990
8991/*
8992 * STREAM_0_SYNCHRONIZATION enum
8993 */
8994
8995typedef enum STREAM_0_SYNCHRONIZATION {
8996STREAM_0_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
8997STREAM_0_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
8998} STREAM_0_SYNCHRONIZATION;
8999
9000/*
9001 * STREAM_1_SYNCHRONIZATION enum
9002 */
9003
9004typedef enum STREAM_1_SYNCHRONIZATION {
9005STREAM_1_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
9006STREAM_1_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
9007} STREAM_1_SYNCHRONIZATION;
9008
9009/*
9010 * STREAM_2_SYNCHRONIZATION enum
9011 */
9012
9013typedef enum STREAM_2_SYNCHRONIZATION {
9014STREAM_2_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
9015STREAM_2_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
9016} STREAM_2_SYNCHRONIZATION;
9017
9018/*
9019 * STREAM_3_SYNCHRONIZATION enum
9020 */
9021
9022typedef enum STREAM_3_SYNCHRONIZATION {
9023STREAM_3_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
9024STREAM_3_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
9025} STREAM_3_SYNCHRONIZATION;
9026
9027/*
9028 * STREAM_4_SYNCHRONIZATION enum
9029 */
9030
9031typedef enum STREAM_4_SYNCHRONIZATION {
9032STREAM_4_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
9033STREAM_4_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
9034} STREAM_4_SYNCHRONIZATION;
9035
9036/*
9037 * STREAM_5_SYNCHRONIZATION enum
9038 */
9039
9040typedef enum STREAM_5_SYNCHRONIZATION {
9041STREAM_5_SYNCHRONIZATION_STEAM_NOT_STOPPED = 0x00000000,
9042STREAM_5_SYNCHRONIZATION_STEAM_STOPPED = 0x00000001,
9043} STREAM_5_SYNCHRONIZATION;
9044
9045/*
9046 * STREAM_6_SYNCHRONIZATION enum
9047 */
9048
9049typedef enum STREAM_6_SYNCHRONIZATION {
9050STREAM_6_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9051STREAM_6_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9052} STREAM_6_SYNCHRONIZATION;
9053
9054/*
9055 * STREAM_7_SYNCHRONIZATION enum
9056 */
9057
9058typedef enum STREAM_7_SYNCHRONIZATION {
9059STREAM_7_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9060STREAM_7_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9061} STREAM_7_SYNCHRONIZATION;
9062
9063/*
9064 * STREAM_8_SYNCHRONIZATION enum
9065 */
9066
9067typedef enum STREAM_8_SYNCHRONIZATION {
9068STREAM_8_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9069STREAM_8_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9070} STREAM_8_SYNCHRONIZATION;
9071
9072/*
9073 * STREAM_9_SYNCHRONIZATION enum
9074 */
9075
9076typedef enum STREAM_9_SYNCHRONIZATION {
9077STREAM_9_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9078STREAM_9_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9079} STREAM_9_SYNCHRONIZATION;
9080
9081/*
9082 * STREAM_10_SYNCHRONIZATION enum
9083 */
9084
9085typedef enum STREAM_10_SYNCHRONIZATION {
9086STREAM_10_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9087STREAM_10_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9088} STREAM_10_SYNCHRONIZATION;
9089
9090/*
9091 * STREAM_11_SYNCHRONIZATION enum
9092 */
9093
9094typedef enum STREAM_11_SYNCHRONIZATION {
9095STREAM_11_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9096STREAM_11_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9097} STREAM_11_SYNCHRONIZATION;
9098
9099/*
9100 * STREAM_12_SYNCHRONIZATION enum
9101 */
9102
9103typedef enum STREAM_12_SYNCHRONIZATION {
9104STREAM_12_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9105STREAM_12_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9106} STREAM_12_SYNCHRONIZATION;
9107
9108/*
9109 * STREAM_13_SYNCHRONIZATION enum
9110 */
9111
9112typedef enum STREAM_13_SYNCHRONIZATION {
9113STREAM_13_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9114STREAM_13_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9115} STREAM_13_SYNCHRONIZATION;
9116
9117/*
9118 * STREAM_14_SYNCHRONIZATION enum
9119 */
9120
9121typedef enum STREAM_14_SYNCHRONIZATION {
9122STREAM_14_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9123STREAM_14_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9124} STREAM_14_SYNCHRONIZATION;
9125
9126/*
9127 * STREAM_15_SYNCHRONIZATION enum
9128 */
9129
9130typedef enum STREAM_15_SYNCHRONIZATION {
9131STREAM_15_SYNCHRONIZATION_STEAM_NOT_STOPPED_RESERVED = 0x00000000,
9132STREAM_15_SYNCHRONIZATION_STEAM_STOPPED_RESERVED = 0x00000001,
9133} STREAM_15_SYNCHRONIZATION;
9134
9135/*
9136 * CORB_READ_POINTER_RESET enum
9137 */
9138
9139typedef enum CORB_READ_POINTER_RESET {
9140CORB_READ_POINTER_RESET_CORB_DMA_IS_NOT_RESET = 0x00000000,
9141CORB_READ_POINTER_RESET_CORB_DMA_IS_RESET = 0x00000001,
9142} CORB_READ_POINTER_RESET;
9143
9144/*
9145 * AZ_CORB_SIZE enum
9146 */
9147
9148typedef enum AZ_CORB_SIZE {
9149AZ_CORB_SIZE_2ENTRIES_RESERVED = 0x00000000,
9150AZ_CORB_SIZE_16ENTRIES_RESERVED = 0x00000001,
9151AZ_CORB_SIZE_256ENTRIES = 0x00000002,
9152AZ_CORB_SIZE_RESERVED = 0x00000003,
9153} AZ_CORB_SIZE;
9154
9155/*
9156 * AZ_RIRB_WRITE_POINTER_RESET enum
9157 */
9158
9159typedef enum AZ_RIRB_WRITE_POINTER_RESET {
9160AZ_RIRB_WRITE_POINTER_NOT_RESET = 0x00000000,
9161AZ_RIRB_WRITE_POINTER_DO_RESET = 0x00000001,
9162} AZ_RIRB_WRITE_POINTER_RESET;
9163
9164/*
9165 * RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL enum
9166 */
9167
9168typedef enum RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL {
9169RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
9170RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
9171} RIRB_CONTROL_RESPONSE_OVERRUN_INTERRUPT_CONTROL;
9172
9173/*
9174 * RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL enum
9175 */
9176
9177typedef enum RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL {
9178RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_DISABLED = 0x00000000,
9179RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL_INTERRUPT_ENABLED = 0x00000001,
9180} RIRB_CONTROL_RESPONSE_INTERRUPT_CONTROL;
9181
9182/*
9183 * AZ_RIRB_SIZE enum
9184 */
9185
9186typedef enum AZ_RIRB_SIZE {
9187AZ_RIRB_SIZE_2ENTRIES_RESERVED = 0x00000000,
9188AZ_RIRB_SIZE_16ENTRIES_RESERVED = 0x00000001,
9189AZ_RIRB_SIZE_256ENTRIES = 0x00000002,
9190AZ_RIRB_SIZE_UNDEFINED = 0x00000003,
9191} AZ_RIRB_SIZE;
9192
9193/*
9194 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID enum
9195 */
9196
9197typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID {
9198IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_NO_IMMEDIATE_RESPONSE_VALID = 0x00000000,
9199IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID_IMMEDIATE_RESPONSE_VALID = 0x00000001,
9200} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_RESULT_VALID;
9201
9202/*
9203 * IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY enum
9204 */
9205
9206typedef enum IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY {
9207IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_NOT_BUSY = 0x00000000,
9208IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_IS_BUSY = 0x00000001,
9209} IMMEDIATE_COMMAND_STATUS_IMMEDIATE_COMMAND_BUSY;
9210
9211/*
9212 * DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE enum
9213 */
9214
9215typedef enum DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE {
9216DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_DISABLE = 0x00000000,
9217DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE_DMA_ENABLE = 0x00000001,
9218} DMA_POSITION_LOWER_BASE_ADDRESS_BUFFER_ENABLE;
9219
9220/*******************************************************
9221 * AZENDPOINT Enums
9222 *******************************************************/
9223
9224/*
9225 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
9226 */
9227
9228typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
9229AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
9230AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
9231} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
9232
9233/*
9234 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
9235 */
9236
9237typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
9238AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
9239AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
9240} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
9241
9242/*
9243 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
9244 */
9245
9246typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
9247AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
9248AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
9249AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
9250AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
9251AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
9252} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
9253
9254/*
9255 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
9256 */
9257
9258typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
9259AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
9260AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
9261AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
9262AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
9263AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
9264AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
9265AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
9266AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
9267} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
9268
9269/*
9270 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
9271 */
9272
9273typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
9274AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
9275AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
9276AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
9277AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
9278AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
9279AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
9280} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
9281
9282/*
9283 * AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
9284 */
9285
9286typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
9287AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
9288AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
9289AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
9290AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
9291AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
9292AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
9293AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
9294AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
9295AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
9296} AZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
9297
9298/*
9299 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L enum
9300 */
9301
9302typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L {
9303AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_NOT_SET = 0x00000000,
9304AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L_BIT7_IS_SET = 0x00000001,
9305} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_L;
9306
9307/*
9308 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO enum
9309 */
9310
9311typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO {
9312AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_NOT_SET = 0x00000000,
9313AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO_BIT_A_IS_SET = 0x00000001,
9314} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRO;
9315
9316/*
9317 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO enum
9318 */
9319
9320typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO {
9321AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_NOT_SET = 0x00000000,
9322AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO_BIT_B_IS_SET = 0x00000001,
9323} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_NON_AUDIO;
9324
9325/*
9326 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY enum
9327 */
9328
9329typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY {
9330AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_IS_SET = 0x00000000,
9331AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY_BIT_C_NOT_SET = 0x00000001,
9332} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_COPY;
9333
9334/*
9335 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE enum
9336 */
9337
9338typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE {
9339AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_NOT_SET = 0x00000000,
9340AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE_LSB_OF_D_IS_SET = 0x00000001,
9341} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_PRE;
9342
9343/*
9344 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG enum
9345 */
9346
9347typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG {
9348AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_NOT_ON = 0x00000000,
9349AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VALIDITY_CFG_ON = 0x00000001,
9350} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_VCFG;
9351
9352/*
9353 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V enum
9354 */
9355
9356typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V {
9357AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ZERO = 0x00000000,
9358AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V_BIT28_IS_ONE = 0x00000001,
9359} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_V;
9360
9361/*
9362 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
9363 */
9364
9365typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
9366AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
9367AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
9368} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
9369
9370/*
9371 * AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE enum
9372 */
9373
9374typedef enum AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE {
9375AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_NOT_ENABLE = 0x00000000,
9376AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE_SILENT_STREAM_ENABLE = 0x00000001,
9377} AZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3_KEEPALIVE;
9378
9379/*
9380 * AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE enum
9381 */
9382
9383typedef enum AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE {
9384AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_SHUT_OFF = 0x00000000,
9385AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE_PIN_DRIVEN = 0x00000001,
9386} AZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL_OUT_ENABLE;
9387
9388/*
9389 * AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
9390 */
9391
9392typedef enum AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
9393AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
9394AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
9395} AZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
9396
9397/*
9398 * AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT enum
9399 */
9400
9401typedef enum AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT {
9402AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_NO_INFO_OR_PERMITTED = 0x00000000,
9403AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_FORBIDDEN = 0x00000001,
9404} AZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO_DOWN_MIX_INHIBIT;
9405
9406/*
9407 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE enum
9408 */
9409
9410typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE {
9411AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_NOT_MUTED = 0x00000000,
9412AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTED = 0x00000001,
9413} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE_MULTICHANNEL01_MUTE;
9414
9415/*
9416 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE enum
9417 */
9418
9419typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE {
9420AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_NOT_MUTED = 0x00000000,
9421AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTED = 0x00000001,
9422} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE_MULTICHANNEL23_MUTE;
9423
9424/*
9425 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE enum
9426 */
9427
9428typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE {
9429AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_NOT_MUTED = 0x00000000,
9430AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTED = 0x00000001,
9431} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE_MULTICHANNEL45_MUTE;
9432
9433/*
9434 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE enum
9435 */
9436
9437typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE {
9438AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_NOT_MUTED = 0x00000000,
9439AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTED = 0x00000001,
9440} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE_MULTICHANNEL67_MUTE;
9441
9442/*
9443 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
9444 */
9445
9446typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
9447AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
9448AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
9449} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
9450
9451/*
9452 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
9453 */
9454
9455typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
9456AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
9457AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
9458} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
9459
9460/*
9461 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
9462 */
9463
9464typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
9465AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
9466AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
9467} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
9468
9469/*
9470 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
9471 */
9472
9473typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
9474AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
9475AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
9476} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
9477
9478/*
9479 * AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
9480 */
9481
9482typedef enum AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
9483AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
9484AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
9485} AZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
9486
9487/*
9488 * AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE enum
9489 */
9490
9491typedef enum AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE {
9492AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_0 = 0x00000000,
9493AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_1 = 0x00000001,
9494AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_2 = 0x00000002,
9495AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_3 = 0x00000003,
9496AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_4 = 0x00000004,
9497AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_5 = 0x00000005,
9498AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_6 = 0x00000006,
9499AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_7 = 0x00000007,
9500AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_8 = 0x00000008,
9501AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_9 = 0x00000009,
9502AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_10 = 0x0000000a,
9503AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_11 = 0x0000000b,
9504AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_12 = 0x0000000c,
9505AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_13 = 0x0000000d,
9506AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_14 = 0x0000000e,
9507AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE_15 = 0x0000000f,
9508} AZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_FORMAT_CODE;
9509
9510/*******************************************************
9511 * AZF0CONTROLLER Enums
9512 *******************************************************/
9513
9514/*
9515 * MEM_PWR_FORCE_CTRL enum
9516 */
9517
9518typedef enum MEM_PWR_FORCE_CTRL {
9519NO_FORCE_REQUEST = 0x00000000,
9520FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
9521FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
9522FORCE_SHUT_DOWN_REQUEST = 0x00000003,
9523} MEM_PWR_FORCE_CTRL;
9524
9525/*
9526 * MEM_PWR_FORCE_CTRL2 enum
9527 */
9528
9529typedef enum MEM_PWR_FORCE_CTRL2 {
9530NO_FORCE_REQ = 0x00000000,
9531FORCE_LIGHT_SLEEP_REQ = 0x00000001,
9532} MEM_PWR_FORCE_CTRL2;
9533
9534/*
9535 * MEM_PWR_DIS_CTRL enum
9536 */
9537
9538typedef enum MEM_PWR_DIS_CTRL {
9539ENABLE_MEM_PWR_CTRL = 0x00000000,
9540DISABLE_MEM_PWR_CTRL = 0x00000001,
9541} MEM_PWR_DIS_CTRL;
9542
9543/*
9544 * MEM_PWR_SEL_CTRL enum
9545 */
9546
9547typedef enum MEM_PWR_SEL_CTRL {
9548DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000,
9549DYNAMIC_DEEP_SLEEP_ENABLE = 0x00000001,
9550DYNAMIC_LIGHT_SLEEP_ENABLE = 0x00000002,
9551} MEM_PWR_SEL_CTRL;
9552
9553/*
9554 * MEM_PWR_SEL_CTRL2 enum
9555 */
9556
9557typedef enum MEM_PWR_SEL_CTRL2 {
9558DYNAMIC_DEEP_SLEEP_EN = 0x00000000,
9559DYNAMIC_LIGHT_SLEEP_EN = 0x00000001,
9560} MEM_PWR_SEL_CTRL2;
9561
9562/*
9563 * AZALIA_SOFT_RESET_REFCLK_SOFT_RESET enum
9564 */
9565
9566typedef enum AZALIA_SOFT_RESET_REFCLK_SOFT_RESET {
9567AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_NOT_RESET = 0x00000000,
9568AZALIA_SOFT_RESET_REFCLK_SOFT_RESET_RESET_REFCLK_LOGIC = 0x00000001,
9569} AZALIA_SOFT_RESET_REFCLK_SOFT_RESET;
9570
9571/*******************************************************
9572 * AZF0ROOT Enums
9573 *******************************************************/
9574
9575/*
9576 * CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY enum
9577 */
9578
9579typedef enum CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY {
9580CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_ALL = 0x00000000,
9581CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_6 = 0x00000001,
9582CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_5 = 0x00000002,
9583CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_4 = 0x00000003,
9584CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_3 = 0x00000004,
9585CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_2 = 0x00000005,
9586CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_1 = 0x00000006,
9587CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY_0 = 0x00000007,
9588} CC_RCU_DC_AUDIO_PORT_CONNECTIVITY_PORT_CONNECTIVITY;
9589
9590/*
9591 * CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY enum
9592 */
9593
9594typedef enum CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY {
9595CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_ALL = 0x00000000,
9596CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_6 = 0x00000001,
9597CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_5 = 0x00000002,
9598CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_4 = 0x00000003,
9599CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_3 = 0x00000004,
9600CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_2 = 0x00000005,
9601CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_1 = 0x00000006,
9602CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY_0 = 0x00000007,
9603} CC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_INPUT_PORT_CONNECTIVITY;
9604
9605/*******************************************************
9606 * AZINPUTENDPOINT Enums
9607 *******************************************************/
9608
9609/*
9610 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE enum
9611 */
9612
9613typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE {
9614AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_PCM = 0x00000000,
9615AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE_NOT_PCM = 0x00000001,
9616} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_STREAM_TYPE;
9617
9618/*
9619 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE enum
9620 */
9621
9622typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE {
9623AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
9624AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
9625} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_RATE;
9626
9627/*
9628 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE enum
9629 */
9630
9631typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE {
9632AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
9633AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
9634AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
9635AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
9636AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
9637} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_MULTIPLE;
9638
9639/*
9640 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR enum
9641 */
9642
9643typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR {
9644AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
9645AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
9646AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
9647AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
9648AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
9649AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
9650AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
9651AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
9652} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_SAMPLE_BASE_DIVISOR;
9653
9654/*
9655 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE enum
9656 */
9657
9658typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE {
9659AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
9660AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
9661AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
9662AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
9663AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
9664AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
9665} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_BITS_PER_SAMPLE;
9666
9667/*
9668 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS enum
9669 */
9670
9671typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS {
9672AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
9673AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
9674AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
9675AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
9676AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
9677AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
9678AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
9679AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
9680AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS_RESERVED = 0x00000008,
9681} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT_NUMBER_OF_CHANNELS;
9682
9683/*
9684 * AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN enum
9685 */
9686
9687typedef enum AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN {
9688AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_DISABLED = 0x00000000,
9689AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN_DIGITAL_TRANSMISSION_ENABLED = 0x00000001,
9690} AZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER_DIGEN;
9691
9692/*
9693 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE enum
9694 */
9695
9696typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE {
9697AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_SHUT_OFF = 0x00000000,
9698AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE_PIN_DRIVEN = 0x00000001,
9699} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL_IN_ENABLE;
9700
9701/*
9702 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE enum
9703 */
9704
9705typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE {
9706AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_DISABLED = 0x00000000,
9707AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLED = 0x00000001,
9708} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_ENABLE;
9709
9710/*
9711 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE enum
9712 */
9713
9714typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE {
9715AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_NOT_MUTED = 0x00000000,
9716AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTED = 0x00000001,
9717} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE_MULTICHANNEL0_MUTE;
9718
9719/*
9720 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE enum
9721 */
9722
9723typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE {
9724AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_NOT_MUTED = 0x00000000,
9725AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTED = 0x00000001,
9726} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE_MULTICHANNEL1_MUTE;
9727
9728/*
9729 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE enum
9730 */
9731
9732typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE {
9733AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_NOT_MUTED = 0x00000000,
9734AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTED = 0x00000001,
9735} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE_MULTICHANNEL2_MUTE;
9736
9737/*
9738 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE enum
9739 */
9740
9741typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE {
9742AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_NOT_MUTED = 0x00000000,
9743AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTED = 0x00000001,
9744} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE_MULTICHANNEL3_MUTE;
9745
9746/*
9747 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE enum
9748 */
9749
9750typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE {
9751AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_NOT_MUTED = 0x00000000,
9752AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTED = 0x00000001,
9753} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE_MULTICHANNEL4_MUTE;
9754
9755/*
9756 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE enum
9757 */
9758
9759typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE {
9760AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_NOT_MUTED = 0x00000000,
9761AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTED = 0x00000001,
9762} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE_MULTICHANNEL5_MUTE;
9763
9764/*
9765 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE enum
9766 */
9767
9768typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE {
9769AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_NOT_MUTED = 0x00000000,
9770AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTED = 0x00000001,
9771} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE_MULTICHANNEL6_MUTE;
9772
9773/*
9774 * AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE enum
9775 */
9776
9777typedef enum AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE {
9778AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_NOT_MUTED = 0x00000000,
9779AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTED = 0x00000001,
9780} AZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE_MULTICHANNEL7_MUTE;
9781
9782/*******************************************************
9783 * AZROOT Enums
9784 *******************************************************/
9785
9786/*
9787 * AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET enum
9788 */
9789
9790typedef enum AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET {
9791AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_NOT_RESET = 0x00000000,
9792AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_DO_RESET = 0x00000001,
9793} AZALIA_F2_CODEC_FUNCTION_CONTROL_RESET_CODEC_RESET;
9794
9795/*******************************************************
9796 * AZF0STREAM Enums
9797 *******************************************************/
9798
9799/*
9800 * AZ_LATENCY_COUNTER_CONTROL enum
9801 */
9802
9803typedef enum AZ_LATENCY_COUNTER_CONTROL {
9804AZ_LATENCY_COUNTER_NO_RESET = 0x00000000,
9805AZ_LATENCY_COUNTER_RESET_DONE = 0x00000001,
9806} AZ_LATENCY_COUNTER_CONTROL;
9807
9808/*******************************************************
9809 * AZSTREAM Enums
9810 *******************************************************/
9811
9812/*
9813 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR enum
9814 */
9815
9816typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR {
9817OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_NOT_SET = 0x00000000,
9818OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_STATUS_SET = 0x00000001,
9819} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR;
9820
9821/*
9822 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR enum
9823 */
9824
9825typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR {
9826OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_NOT_SET = 0x00000000,
9827OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_STATUS_SET = 0x00000001,
9828} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR;
9829
9830/*
9831 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS enum
9832 */
9833
9834typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS {
9835OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_NOT_SET = 0x00000000,
9836OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS_SET = 0x00000001,
9837} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BUFFER_COMPLETION_INTERRUPT_STATUS;
9838
9839/*
9840 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY enum
9841 */
9842
9843typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY {
9844OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_NO_TRAFFIC_PRIORITY = 0x00000000,
9845OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_YES_TRAFFIC_PRIORITY = 0x00000001,
9846} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_TRAFFIC_PRIORITY;
9847
9848/*
9849 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE enum
9850 */
9851
9852typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE {
9853OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_DISABLED = 0x00000000,
9854OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLED = 0x00000001,
9855} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_DESCRIPTOR_ERROR_INTERRUPT_ENABLE;
9856
9857/*
9858 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE enum
9859 */
9860
9861typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE {
9862OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_DISABLED = 0x00000000,
9863OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLED = 0x00000001,
9864} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_FIFO_ERROR_INTERRUPT_ENABLE;
9865
9866/*
9867 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE enum
9868 */
9869
9870typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE {
9871OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_DISABLED = 0x00000000,
9872OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE_INTERRUPT_ENABLED = 0x00000001,
9873} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_INTERRUPT_ON_COMPLETION_ENABLE;
9874
9875/*
9876 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN enum
9877 */
9878
9879typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN {
9880OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RUN = 0x00000000,
9881OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_DO_RUN = 0x00000001,
9882} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RUN;
9883
9884/*
9885 * OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET enum
9886 */
9887
9888typedef enum OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET {
9889OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_NOT_RESET = 0x00000000,
9890OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_IS_RESET = 0x00000001,
9891} OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_STREAM_RESET;
9892
9893/*
9894 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE enum
9895 */
9896
9897typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE {
9898OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_48KHZ = 0x00000000,
9899OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE_44P1KHZ = 0x00000001,
9900} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_RATE;
9901
9902/*
9903 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE enum
9904 */
9905
9906typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE {
9907OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY1 = 0x00000000,
9908OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY2 = 0x00000001,
9909OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY3_RESERVED = 0x00000002,
9910OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_BY4 = 0x00000003,
9911OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE_RESERVED = 0x00000004,
9912} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_MULTIPLE;
9913
9914/*
9915 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR enum
9916 */
9917
9918typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR {
9919OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY1 = 0x00000000,
9920OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY2_RESERVED = 0x00000001,
9921OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY3 = 0x00000002,
9922OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY4_RESERVED = 0x00000003,
9923OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY5_RESERVED = 0x00000004,
9924OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY6_RESERVED = 0x00000005,
9925OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY7_RESERVED = 0x00000006,
9926OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR_BY8_RESERVED = 0x00000007,
9927} OUTPUT_STREAM_DESCRIPTOR_FORMAT_SAMPLE_BASE_DIVISOR;
9928
9929/*
9930 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE enum
9931 */
9932
9933typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE {
9934OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_8_RESERVED = 0x00000000,
9935OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_16 = 0x00000001,
9936OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_20 = 0x00000002,
9937OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_24 = 0x00000003,
9938OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_32_RESERVED = 0x00000004,
9939OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE_RESERVED = 0x00000005,
9940} OUTPUT_STREAM_DESCRIPTOR_FORMAT_BITS_PER_SAMPLE;
9941
9942/*
9943 * OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS enum
9944 */
9945
9946typedef enum OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS {
9947OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_1 = 0x00000000,
9948OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_2 = 0x00000001,
9949OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_3 = 0x00000002,
9950OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_4 = 0x00000003,
9951OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_5 = 0x00000004,
9952OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_6 = 0x00000005,
9953OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_7 = 0x00000006,
9954OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_8 = 0x00000007,
9955OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_9_RESERVED = 0x00000008,
9956OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_10_RESERVED = 0x00000009,
9957OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_11_RESERVED = 0x0000000a,
9958OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_12_RESERVED = 0x0000000b,
9959OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_13_RESERVED = 0x0000000c,
9960OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_14_RESERVED = 0x0000000d,
9961OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_15_RESERVED = 0x0000000e,
9962OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS_16_RESERVED = 0x0000000f,
9963} OUTPUT_STREAM_DESCRIPTOR_FORMAT_NUMBER_OF_CHANNELS;
9964
9965/*******************************************************
9966 * AZF0ENDPOINT Enums
9967 *******************************************************/
9968
9969/*
9970 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
9971 */
9972
9973typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
9974AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
9975AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
9976AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
9977AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
9978AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
9979AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
9980AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
9981AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
9982AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
9983AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
9984} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
9985
9986/*
9987 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
9988 */
9989
9990typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
9991AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
9992AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
9993} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
9994
9995/*
9996 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
9997 */
9998
9999typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10000AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
10001AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
10002} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10003
10004/*
10005 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10006 */
10007
10008typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10009AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
10010AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
10011} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10012
10013/*
10014 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10015 */
10016
10017typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10018AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
10019AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
10020} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10021
10022/*
10023 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10024 */
10025
10026typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10027AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
10028AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
10029} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10030
10031/*
10032 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10033 */
10034
10035typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10036AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
10037AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
10038} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10039
10040/*
10041 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10042 */
10043
10044typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10045AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
10046AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
10047} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10048
10049/*
10050 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10051 */
10052
10053typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10054AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
10055AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_FORMAT_OVERRIDE = 0x00000001,
10056} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
10057
10058/*
10059 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10060 */
10061
10062typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10063AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
10064AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
10065} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10066
10067/*
10068 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10069 */
10070
10071typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10072AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
10073AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
10074} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10075
10076/*
10077 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10078 */
10079
10080typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10081AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
10082AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
10083} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10084
10085/*
10086 * AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10087 */
10088
10089typedef enum AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
10090AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
10091AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
10092} AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
10093
10094/*
10095 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10096 */
10097
10098typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10099AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
10100AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
10101AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
10102AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
10103AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
10104AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
10105AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
10106AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
10107AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED_RESERVED = 0x00000008,
10108AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
10109} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
10110
10111/*
10112 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10113 */
10114
10115typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10116AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
10117AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
10118} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
10119
10120/*
10121 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10122 */
10123
10124typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10125AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
10126AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
10127} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10128
10129/*
10130 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10131 */
10132
10133typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10134AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
10135AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
10136} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10137
10138/*
10139 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10140 */
10141
10142typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10143AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
10144AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
10145} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10146
10147/*
10148 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10149 */
10150
10151typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10152AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
10153AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
10154} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10155
10156/*
10157 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10158 */
10159
10160typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10161AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESSING_CAPABILITIES = 0x00000000,
10162AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
10163} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10164
10165/*
10166 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10167 */
10168
10169typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10170AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
10171AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
10172} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10173
10174/*
10175 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10176 */
10177
10178typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10179AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
10180AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
10181} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10182
10183/*
10184 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10185 */
10186
10187typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10188AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
10189AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
10190} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10191
10192/*
10193 * AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10194 */
10195
10196typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10197AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER_PRESENT = 0x00000000,
10198AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
10199} AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10200
10201/*
10202 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
10203 */
10204
10205typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
10206AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_EAPD_PIN = 0x00000000,
10207AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_EAPD_PIN = 0x00000001,
10208} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
10209
10210/*
10211 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
10212 */
10213
10214typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
10215AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_NOT_BALANCED = 0x00000000,
10216AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
10217} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
10218
10219/*
10220 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
10221 */
10222
10223typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
10224AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
10225AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
10226} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
10227
10228/*
10229 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
10230 */
10231
10232typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
10233AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
10234AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
10235} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
10236
10237/*
10238 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
10239 */
10240
10241typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
10242AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
10243AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
10244} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
10245
10246/*
10247 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
10248 */
10249
10250typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
10251AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_JACK_DETECTION_CAPABILITY = 0x00000000,
10252AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_DETECTION_CAPABILITY = 0x00000001,
10253} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
10254
10255/*
10256 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
10257 */
10258
10259typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
10260AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
10261AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
10262} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
10263
10264/*
10265 * AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
10266 */
10267
10268typedef enum AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
10269AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
10270AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
10271} AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
10272
10273/*
10274 * AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE enum
10275 */
10276
10277typedef enum AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE {
10278AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_PAIR_MODE = 0x00000000,
10279AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_SINGLE_MODE = 0x00000001,
10280} AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE_MULTICHANNEL_MODE;
10281
10282/*
10283 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10284 */
10285
10286typedef enum AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10287AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABLILITY = 0x00000000,
10288AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABLILITY = 0x00000001,
10289} AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
10290
10291/*******************************************************
10292 * AZF0INPUTENDPOINT Enums
10293 *******************************************************/
10294
10295/*
10296 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10297 */
10298
10299typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10300AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
10301AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
10302AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
10303AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
10304AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
10305AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
10306AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
10307AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
10308AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
10309AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
10310} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
10311
10312/*
10313 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10314 */
10315
10316typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10317AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP_CAPABILITY = 0x00000000,
10318AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP_CAPABILITY = 0x00000001,
10319} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
10320
10321/*
10322 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10323 */
10324
10325typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10326AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
10327AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
10328} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10329
10330/*
10331 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10332 */
10333
10334typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10335AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_ANALOG = 0x00000000,
10336AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CODEC_CONVERTER0_IS_DIGITAL = 0x00000001,
10337} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10338
10339/*
10340 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10341 */
10342
10343typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10344AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
10345AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
10346} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10347
10348/*
10349 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10350 */
10351
10352typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10353AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
10354AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
10355} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10356
10357/*
10358 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10359 */
10360
10361typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10362AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_NO_PROCESSING_CAPABILITIES = 0x00000000,
10363AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_CODEC_CONVERTER0_HAVE_PROCESSING_CAPABILITIES = 0x00000001,
10364} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10365
10366/*
10367 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10368 */
10369
10370typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10371AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NOT_SUPPORT_STRIPING = 0x00000000,
10372AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
10373} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10374
10375/*
10376 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE enum
10377 */
10378
10379typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE {
10380AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_FORMAT_OVERRIDE = 0x00000000,
10381AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_FORMAT_OVERRIDE = 0x00000001,
10382} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_FORMAT_OVERRIDE;
10383
10384/*
10385 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10386 */
10387
10388typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10389AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
10390AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER = 0x00000001,
10391} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10392
10393/*
10394 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10395 */
10396
10397typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10398AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
10399AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
10400} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10401
10402/*
10403 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10404 */
10405
10406typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10407AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
10408AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
10409} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10410
10411/*
10412 * AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES enum
10413 */
10414
10415typedef enum AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES {
10416AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_MONOPHONIC = 0x00000000,
10417AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES_STEREO = 0x00000001,
10418} AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AUDIO_CHANNEL_CAPABILITIES;
10419
10420/*
10421 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE enum
10422 */
10423
10424typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE {
10425AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_OUTPUT_CONVERTER_RESERVED = 0x00000000,
10426AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_INPUT_CONVERTER_RESERVED = 0x00000001,
10427AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_MIXER_RESERVED = 0x00000002,
10428AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_SELECTOR_RESERVED = 0x00000003,
10429AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_PIN_RESERVED = 0x00000004,
10430AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_POWER_WIDGET_RESERVED = 0x00000005,
10431AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VOLUME_KNOB_RESERVED = 0x00000006,
10432AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_BEEP_GENERATOR_RESERVED = 0x00000007,
10433AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_RESERVED = 0x00000008,
10434AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE_VENDOR_DEFINED_RESERVED = 0x00000009,
10435} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_TYPE;
10436
10437/*
10438 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP enum
10439 */
10440
10441typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP {
10442AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_LR_SWAP = 0x00000000,
10443AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_LR_SWAP = 0x00000001,
10444} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_LR_SWAP;
10445
10446/*
10447 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL enum
10448 */
10449
10450typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL {
10451AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_POWER_CONTROL_CAPABILITY = 0x00000000,
10452AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_POWER_CONTROL_CAPABILITY = 0x00000001,
10453} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_POWER_CONTROL;
10454
10455/*
10456 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL enum
10457 */
10458
10459typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL {
10460AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_ANALOG = 0x00000000,
10461AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_IS_DIGITAL = 0x00000001,
10462} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_DIGITAL;
10463
10464/*
10465 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST enum
10466 */
10467
10468typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST {
10469AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_CONNECTION_LIST = 0x00000000,
10470AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_CONNECTION_LIST = 0x00000001,
10471} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_CONNECTION_LIST;
10472
10473/*
10474 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY enum
10475 */
10476
10477typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY {
10478AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000000,
10479AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_UNSOLICITED_RESPONSE_CAPABILITY = 0x00000001,
10480} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_UNSOLICITED_RESPONSE_CAPABILITY;
10481
10482/*
10483 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET enum
10484 */
10485
10486typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET {
10487AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_NO_PROCESING_CAPABILITIES = 0x00000000,
10488AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET_HAVE_PROCESING_CAPABILITIES = 0x00000001,
10489} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_PROCESSING_WIDGET;
10490
10491/*
10492 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE enum
10493 */
10494
10495typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE {
10496AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_SUPPORT_STRIPING = 0x00000000,
10497AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_SUPPORT_STRIPING = 0x00000001,
10498} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_STRIPE;
10499
10500/*
10501 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE enum
10502 */
10503
10504typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE {
10505AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_AMPLIFIER_PARAMETER = 0x00000000,
10506AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_AMPLIFIER_PARAMETER_OVERRIDE = 0x00000001,
10507} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_AMPLIFIER_PARAMETER_OVERRIDE;
10508
10509/*
10510 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT enum
10511 */
10512
10513typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT {
10514AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_OUTPUT_AMPLIFIER = 0x00000000,
10515AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_OUTPUT_AMPLIFIER = 0x00000001,
10516} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_OUTPUT_AMPLIFIER_PRESENT;
10517
10518/*
10519 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT enum
10520 */
10521
10522typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT {
10523AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_NO_INPUT_AMPLIFIER = 0x00000000,
10524AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_HAVE_INPUT_AMPLIFIER = 0x00000001,
10525} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES_INPUT_AMPLIFIER_PRESENT;
10526
10527/*
10528 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP enum
10529 */
10530
10531typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP {
10532AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_NOT_ENABLED = 0x00000000,
10533AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP_ENABLED = 0x00000001,
10534} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_DP;
10535
10536/*
10537 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE enum
10538 */
10539
10540typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE {
10541AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_NO_EAPD_PIN = 0x00000000,
10542AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE_HAVE_EAPD_PIN = 0x00000001,
10543} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_EAPD_CAPABLE;
10544
10545/*
10546 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI enum
10547 */
10548
10549typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI {
10550AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_NOT_ENABLED = 0x00000000,
10551AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI_ENABLED = 0x00000001,
10552} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HDMI;
10553
10554/*
10555 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS enum
10556 */
10557
10558typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS {
10559AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_NOT_BALANCED = 0x00000000,
10560AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_I_O_PINS_ARE_BALANCED = 0x00000001,
10561} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_BALANCED_I_O_PINS;
10562
10563/*
10564 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE enum
10565 */
10566
10567typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE {
10568AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_INPUT_PIN = 0x00000000,
10569AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_INPUT_PIN = 0x00000001,
10570} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_INPUT_CAPABLE;
10571
10572/*
10573 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE enum
10574 */
10575
10576typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE {
10577AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_OUTPUT_PIN = 0x00000000,
10578AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_OUTPUT_PIN = 0x00000001,
10579} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_OUTPUT_CAPABLE;
10580
10581/*
10582 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE enum
10583 */
10584
10585typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE {
10586AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_HEADPHONE_DRIVE_CAPABILITY = 0x00000000,
10587AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_HEADPHONE_DRIVE_CAPABILITY = 0x00000001,
10588} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HEADPHONE_DRIVE_CAPABLE;
10589
10590/*
10591 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY enum
10592 */
10593
10594typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY {
10595AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000000,
10596AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_JACK_PRESENCE_DETECTION_CAPABILITY = 0x00000001,
10597} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_JACK_DETECTION_CAPABILITY;
10598
10599/*
10600 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED enum
10601 */
10602
10603typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED {
10604AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000000,
10605AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED_FOR_IMPEDANCE_MEASUREMENT = 0x00000001,
10606} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_TRIGGER_REQUIRED;
10607
10608/*
10609 * AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE enum
10610 */
10611
10612typedef enum AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE {
10613AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_NO_IMPEDANCE_SENSE_CAPABILITY = 0x00000000,
10614AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_HAVE_IMPEDANCE_SENSE_CAPABILITY = 0x00000001,
10615} AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES_IMPEDANCE_SENSE_CAPABLE;
10616
10617/*
10618 * AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE enum
10619 */
10620
10621typedef enum AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE {
10622AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_NO_HBR_CAPABILITY = 0x00000000,
10623AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HAVE_HBR_CAPABILITY = 0x00000001,
10624} AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR_HBR_CAPABLE;
10625
10626/*******************************************************
10627 * DSCC Enums
10628 *******************************************************/
10629
10630/*
10631 * DSCC_ICH_RESET_ENUM enum
10632 */
10633
10634typedef enum DSCC_ICH_RESET_ENUM {
10635DSCC_ICH_RESET_ENUM_SLICE0_ICH_RESET = 0x00000001,
10636DSCC_ICH_RESET_ENUM_SLICE1_ICH_RESET = 0x00000002,
10637DSCC_ICH_RESET_ENUM_SLICE2_ICH_RESET = 0x00000004,
10638DSCC_ICH_RESET_ENUM_SLICE3_ICH_RESET = 0x00000008,
10639} DSCC_ICH_RESET_ENUM;
10640
10641/*
10642 * DSCC_DSC_VERSION_MINOR_ENUM enum
10643 */
10644
10645typedef enum DSCC_DSC_VERSION_MINOR_ENUM {
10646DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_1_MINOR_VERSION = 0x00000001,
10647DSCC_DSC_VERSION_MINOR_ENUM_DSC_X_2_MINOR_VERSION = 0x00000002,
10648} DSCC_DSC_VERSION_MINOR_ENUM;
10649
10650/*
10651 * DSCC_DSC_VERSION_MAJOR_ENUM enum
10652 */
10653
10654typedef enum DSCC_DSC_VERSION_MAJOR_ENUM {
10655DSCC_DSC_VERSION_MAJOR_ENUM_DSC_1_X_MAJOR_VERSION = 0x00000001,
10656} DSCC_DSC_VERSION_MAJOR_ENUM;
10657
10658/*
10659 * DSCC_LINEBUF_DEPTH_ENUM enum
10660 */
10661
10662typedef enum DSCC_LINEBUF_DEPTH_ENUM {
10663DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_8_BIT = 0x00000008,
10664DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_9_BIT = 0x00000009,
10665DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_10_BIT = 0x0000000a,
10666DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_11_BIT = 0x0000000b,
10667DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_12_BIT = 0x0000000c,
10668DSCC_LINEBUF_DEPTH_ENUM_LINEBUF_DEPTH_13_BIT = 0x0000000d,
10669} DSCC_LINEBUF_DEPTH_ENUM;
10670
10671/*
10672 * DSCC_BITS_PER_COMPONENT_ENUM enum
10673 */
10674
10675typedef enum DSCC_BITS_PER_COMPONENT_ENUM {
10676DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
10677DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
10678DSCC_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
10679} DSCC_BITS_PER_COMPONENT_ENUM;
10680
10681/*
10682 * DSCC_ENABLE_ENUM enum
10683 */
10684
10685typedef enum DSCC_ENABLE_ENUM {
10686DSCC_ENABLE_ENUM_DISABLED = 0x00000000,
10687DSCC_ENABLE_ENUM_ENABLED = 0x00000001,
10688} DSCC_ENABLE_ENUM;
10689
10690/*
10691 * DSCC_MEM_PWR_FORCE_ENUM enum
10692 */
10693
10694typedef enum DSCC_MEM_PWR_FORCE_ENUM {
10695DSCC_MEM_PWR_FORCE_ENUM_NO_FORCE_REQUEST = 0x00000000,
10696DSCC_MEM_PWR_FORCE_ENUM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
10697DSCC_MEM_PWR_FORCE_ENUM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
10698DSCC_MEM_PWR_FORCE_ENUM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
10699} DSCC_MEM_PWR_FORCE_ENUM;
10700
10701/*
10702 * POWER_STATE_ENUM enum
10703 */
10704
10705typedef enum POWER_STATE_ENUM {
10706POWER_STATE_ENUM_ON = 0x00000000,
10707POWER_STATE_ENUM_LS = 0x00000001,
10708POWER_STATE_ENUM_DS = 0x00000002,
10709POWER_STATE_ENUM_SD = 0x00000003,
10710} POWER_STATE_ENUM;
10711
10712/*
10713 * DSCC_MEM_PWR_DIS_ENUM enum
10714 */
10715
10716typedef enum DSCC_MEM_PWR_DIS_ENUM {
10717DSCC_MEM_PWR_DIS_ENUM_REQUEST_EN = 0x00000000,
10718DSCC_MEM_PWR_DIS_ENUM_REQUEST_DIS = 0x00000001,
10719} DSCC_MEM_PWR_DIS_ENUM;
10720
10721/*******************************************************
10722 * DSCCIF Enums
10723 *******************************************************/
10724
10725/*
10726 * DSCCIF_ENABLE_ENUM enum
10727 */
10728
10729typedef enum DSCCIF_ENABLE_ENUM {
10730DSCCIF_ENABLE_ENUM_DISABLED = 0x00000000,
10731DSCCIF_ENABLE_ENUM_ENABLED = 0x00000001,
10732} DSCCIF_ENABLE_ENUM;
10733
10734/*
10735 * DSCCIF_INPUT_PIXEL_FORMAT_ENUM enum
10736 */
10737
10738typedef enum DSCCIF_INPUT_PIXEL_FORMAT_ENUM {
10739DSCCIF_INPUT_PIXEL_FORMAT_ENUM_RGB = 0x00000000,
10740DSCCIF_INPUT_PIXEL_FORMAT_ENUM_YCBCR_444 = 0x00000001,
10741DSCCIF_INPUT_PIXEL_FORMAT_ENUM_SIMPLE_YCBCR_422 = 0x00000002,
10742DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_422 = 0x00000003,
10743DSCCIF_INPUT_PIXEL_FORMAT_ENUM_NATIVE_YCBCR_420 = 0x00000004,
10744} DSCCIF_INPUT_PIXEL_FORMAT_ENUM;
10745
10746/*
10747 * DSCCIF_BITS_PER_COMPONENT_ENUM enum
10748 */
10749
10750typedef enum DSCCIF_BITS_PER_COMPONENT_ENUM {
10751DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_8_BIT = 0x00000008,
10752DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_10_BIT = 0x0000000a,
10753DSCCIF_BITS_PER_COMPONENT_ENUM_BITS_PER_COMPONENT_12_BIT = 0x0000000c,
10754} DSCCIF_BITS_PER_COMPONENT_ENUM;
10755
10756/*******************************************************
10757 * DSC_TOP Enums
10758 *******************************************************/
10759
10760/*
10761 * ENABLE_ENUM enum
10762 */
10763
10764typedef enum ENABLE_ENUM {
10765ENABLE_ENUM_DISABLED = 0x00000000,
10766ENABLE_ENUM_ENABLED = 0x00000001,
10767} ENABLE_ENUM;
10768
10769/*
10770 * CLOCK_GATING_DISABLE_ENUM enum
10771 */
10772
10773typedef enum CLOCK_GATING_DISABLE_ENUM {
10774CLOCK_GATING_DISABLE_ENUM_ENABLED = 0x00000000,
10775CLOCK_GATING_DISABLE_ENUM_DISABLED = 0x00000001,
10776} CLOCK_GATING_DISABLE_ENUM;
10777
10778/*
10779 * TEST_CLOCK_MUX_SELECT_ENUM enum
10780 */
10781
10782typedef enum TEST_CLOCK_MUX_SELECT_ENUM {
10783TEST_CLOCK_MUX_SELECT_DISPCLK_P = 0x00000000,
10784TEST_CLOCK_MUX_SELECT_DISPCLK_G = 0x00000001,
10785TEST_CLOCK_MUX_SELECT_DISPCLK_R = 0x00000002,
10786TEST_CLOCK_MUX_SELECT_DSCCLK_P = 0x00000003,
10787TEST_CLOCK_MUX_SELECT_DSCCLK_G = 0x00000004,
10788TEST_CLOCK_MUX_SELECT_DSCCLK_R = 0x00000005,
10789} TEST_CLOCK_MUX_SELECT_ENUM;
10790
10791/*******************************************************
10792 * CNV Enums
10793 *******************************************************/
10794
10795/*
10796 * WB_ENABLE_ENUM enum
10797 */
10798
10799typedef enum WB_ENABLE_ENUM {
10800WB_EN_DISABLE = 0x00000000,
10801WB_EN_ENABLE = 0x00000001,
10802} WB_ENABLE_ENUM;
10803
10804/*
10805 * WB_CLK_GATE_DIS_ENUM enum
10806 */
10807
10808typedef enum WB_CLK_GATE_DIS_ENUM {
10809WB_CLK_GATE_ENABLE = 0x00000000,
10810WB_CLK_GATE_DISABLE = 0x00000001,
10811} WB_CLK_GATE_DIS_ENUM;
10812
10813/*
10814 * WB_MEM_PWR_DIS_ENUM enum
10815 */
10816
10817typedef enum WB_MEM_PWR_DIS_ENUM {
10818WB_MEM_PWR_ENABLE = 0x00000000,
10819WB_MEM_PWR_DISABLE = 0x00000001,
10820} WB_MEM_PWR_DIS_ENUM;
10821
10822/*
10823 * WB_TEST_CLK_SEL_ENUM enum
10824 */
10825
10826typedef enum WB_TEST_CLK_SEL_ENUM {
10827WB_TEST_CLK_SEL_REG = 0x00000000,
10828WB_TEST_CLK_SEL_WB = 0x00000001,
10829WB_TEST_CLK_SEL_WBSCL = 0x00000002,
10830WB_TEST_CLK_SEL_PERM = 0x00000003,
10831} WB_TEST_CLK_SEL_ENUM;
10832
10833/*
10834 * WBSCL_LB_MEM_PWR_MODE_SEL_ENUM enum
10835 */
10836
10837typedef enum WBSCL_LB_MEM_PWR_MODE_SEL_ENUM {
10838WBSCL_LB_MEM_PWR_MODE_SEL_SD = 0x00000000,
10839WBSCL_LB_MEM_PWR_MODE_SEL_DS = 0x00000001,
10840WBSCL_LB_MEM_PWR_MODE_SEL_LS = 0x00000002,
10841WBSCL_LB_MEM_PWR_MODE_SEL_ON = 0x00000003,
10842} WBSCL_LB_MEM_PWR_MODE_SEL_ENUM;
10843
10844/*
10845 * WBSCL_LB_MEM_PWR_FORCE_ENUM enum
10846 */
10847
10848typedef enum WBSCL_LB_MEM_PWR_FORCE_ENUM {
10849WBSCL_LB_MEM_PWR_FORCE_NO = 0x00000000,
10850WBSCL_LB_MEM_PWR_FORCE_LS = 0x00000001,
10851WBSCL_LB_MEM_PWR_FORCE_DS = 0x00000002,
10852WBSCL_LB_MEM_PWR_FORCE_SD = 0x00000003,
10853} WBSCL_LB_MEM_PWR_FORCE_ENUM;
10854
10855/*
10856 * WBSCL_MEM_PWR_STATE_ENUM enum
10857 */
10858
10859typedef enum WBSCL_MEM_PWR_STATE_ENUM {
10860WBSCL_MEM_PWR_STATE_ON = 0x00000000,
10861WBSCL_MEM_PWR_STATE_LS = 0x00000001,
10862WBSCL_MEM_PWR_STATE_DS = 0x00000002,
10863WBSCL_MEM_PWR_STATE_SD = 0x00000003,
10864} WBSCL_MEM_PWR_STATE_ENUM;
10865
10866/*
10867 * WBSCL_LUT_MEM_PWR_STATE_ENUM enum
10868 */
10869
10870typedef enum WBSCL_LUT_MEM_PWR_STATE_ENUM {
10871WBSCL_LUT_MEM_PWR_STATE_ON = 0x00000000,
10872WBSCL_LUT_MEM_PWR_STATE_LS = 0x00000001,
10873WBSCL_LUT_MEM_PWR_STATE_RESERVED2 = 0x00000002,
10874WBSCL_LUT_MEM_PWR_STATE_RESERVED3 = 0x00000003,
10875} WBSCL_LUT_MEM_PWR_STATE_ENUM;
10876
10877/*
10878 * WB_RAM_PW_SAVE_MODE_ENUM enum
10879 */
10880
10881typedef enum WB_RAM_PW_SAVE_MODE_ENUM {
10882WB_RAM_PW_SAVE_MODE_LS = 0x00000000,
10883WB_RAM_PW_SAVE_MODE_SD = 0x00000001,
10884} WB_RAM_PW_SAVE_MODE_ENUM;
10885
10886/*
10887 * CNV_OUT_BPC_ENUM enum
10888 */
10889
10890typedef enum CNV_OUT_BPC_ENUM {
10891CNV_OUT_BPC_8BPC = 0x00000000,
10892CNV_OUT_BPC_10BPC = 0x00000001,
10893} CNV_OUT_BPC_ENUM;
10894
10895/*
10896 * CNV_FRAME_CAPTURE_RATE_ENUM enum
10897 */
10898
10899typedef enum CNV_FRAME_CAPTURE_RATE_ENUM {
10900CNV_FRAME_CAPTURE_RATE_0 = 0x00000000,
10901CNV_FRAME_CAPTURE_RATE_1 = 0x00000001,
10902CNV_FRAME_CAPTURE_RATE_2 = 0x00000002,
10903CNV_FRAME_CAPTURE_RATE_3 = 0x00000003,
10904} CNV_FRAME_CAPTURE_RATE_ENUM;
10905
10906/*
10907 * CNV_WINDOW_CROP_EN_ENUM enum
10908 */
10909
10910typedef enum CNV_WINDOW_CROP_EN_ENUM {
10911CNV_WINDOW_CROP_DISABLE = 0x00000000,
10912CNV_WINDOW_CROP_ENABLE = 0x00000001,
10913} CNV_WINDOW_CROP_EN_ENUM;
10914
10915/*
10916 * CNV_INTERLACED_MODE_ENUM enum
10917 */
10918
10919typedef enum CNV_INTERLACED_MODE_ENUM {
10920CNV_INTERLACED_MODE_PROGRESSIVE = 0x00000000,
10921CNV_INTERLACED_MODE_INTERLACED = 0x00000001,
10922} CNV_INTERLACED_MODE_ENUM;
10923
10924/*
10925 * CNV_EYE_SELECT enum
10926 */
10927
10928typedef enum CNV_EYE_SELECT {
10929STEREO_DISABLED = 0x00000000,
10930LEFT_EYE = 0x00000001,
10931RIGHT_EYE = 0x00000002,
10932BOTH_EYE = 0x00000003,
10933} CNV_EYE_SELECT;
10934
10935/*
10936 * CNV_STEREO_TYPE_ENUM enum
10937 */
10938
10939typedef enum CNV_STEREO_TYPE_ENUM {
10940CNV_STEREO_TYPE_RESERVED0 = 0x00000000,
10941CNV_STEREO_TYPE_RESERVED1 = 0x00000001,
10942CNV_STEREO_TYPE_RESERVED2 = 0x00000002,
10943CNV_STEREO_TYPE_FRAME_SEQUENTIAL = 0x00000003,
10944} CNV_STEREO_TYPE_ENUM;
10945
10946/*
10947 * CNV_STEREO_POLARITY_ENUM enum
10948 */
10949
10950typedef enum CNV_STEREO_POLARITY_ENUM {
10951CNV_STEREO_POLARITY_LEFT = 0x00000000,
10952CNV_STEREO_POLARITY_RIGHT = 0x00000001,
10953} CNV_STEREO_POLARITY_ENUM;
10954
10955/*
10956 * CNV_INTERLACED_FIELD_ORDER_ENUM enum
10957 */
10958
10959typedef enum CNV_INTERLACED_FIELD_ORDER_ENUM {
10960CNV_INTERLACED_FIELD_ORDER_TOP = 0x00000000,
10961CNV_INTERLACED_FIELD_ORDER_BOT = 0x00000001,
10962} CNV_INTERLACED_FIELD_ORDER_ENUM;
10963
10964/*
10965 * CNV_STEREO_SPLIT_ENUM enum
10966 */
10967
10968typedef enum CNV_STEREO_SPLIT_ENUM {
10969CNV_STEREO_SPLIT_DISABLE = 0x00000000,
10970CNV_STEREO_SPLIT_ENABLE = 0x00000001,
10971} CNV_STEREO_SPLIT_ENUM;
10972
10973/*
10974 * CNV_NEW_CONTENT_ENUM enum
10975 */
10976
10977typedef enum CNV_NEW_CONTENT_ENUM {
10978CNV_NEW_CONTENT_NEG = 0x00000000,
10979CNV_NEW_CONTENT_POS = 0x00000001,
10980} CNV_NEW_CONTENT_ENUM;
10981
10982/*
10983 * CNV_FRAME_CAPTURE_EN_ENUM enum
10984 */
10985
10986typedef enum CNV_FRAME_CAPTURE_EN_ENUM {
10987CNV_FRAME_CAPTURE_DISABLE = 0x00000000,
10988CNV_FRAME_CAPTURE_ENABLE = 0x00000001,
10989} CNV_FRAME_CAPTURE_EN_ENUM;
10990
10991/*
10992 * CNV_UPDATE_PENDING_ENUM enum
10993 */
10994
10995typedef enum CNV_UPDATE_PENDING_ENUM {
10996CNV_UPDATE_PENDING_NEG = 0x00000000,
10997CNV_UPDATE_PENDING_POS = 0x00000001,
10998} CNV_UPDATE_PENDING_ENUM;
10999
11000/*
11001 * CNV_UPDATE_LOCK_ENUM enum
11002 */
11003
11004typedef enum CNV_UPDATE_LOCK_ENUM {
11005CNV_UPDATE_UNLOCK = 0x00000000,
11006CNV_UPDATE_LOCK = 0x00000001,
11007} CNV_UPDATE_LOCK_ENUM;
11008
11009/*
11010 * CNV_CSC_BYPASS_ENUM enum
11011 */
11012
11013typedef enum CNV_CSC_BYPASS_ENUM {
11014CNV_CSC_BYPASS_NEG = 0x00000000,
11015CNV_CSC_BYPASS_POS = 0x00000001,
11016} CNV_CSC_BYPASS_ENUM;
11017
11018/*
11019 * CNV_TEST_CRC_EN_ENUM enum
11020 */
11021
11022typedef enum CNV_TEST_CRC_EN_ENUM {
11023CNV_TEST_CRC_DISABLE = 0x00000000,
11024CNV_TEST_CRC_ENABLE = 0x00000001,
11025} CNV_TEST_CRC_EN_ENUM;
11026
11027/*
11028 * CNV_TEST_CRC_CONT_EN_ENUM enum
11029 */
11030
11031typedef enum CNV_TEST_CRC_CONT_EN_ENUM {
11032CNV_TEST_CRC_CONT_DISABLE = 0x00000000,
11033CNV_TEST_CRC_CONT_ENABLE = 0x00000001,
11034} CNV_TEST_CRC_CONT_EN_ENUM;
11035
11036/*
11037 * WB_SOFT_RESET_ENUM enum
11038 */
11039
11040typedef enum WB_SOFT_RESET_ENUM {
11041WB_SOFT_RESET_NEG = 0x00000000,
11042WB_SOFT_RESET_POS = 0x00000001,
11043} WB_SOFT_RESET_ENUM;
11044
11045/*
11046 * DWB_GMC_WARM_UP_ENABLE_ENUM enum
11047 */
11048
11049typedef enum DWB_GMC_WARM_UP_ENABLE_ENUM {
11050DWB_GMC_WARM_UP_DISABLE = 0x00000000,
11051DWB_GMC_WARM_UP_ENABLE = 0x00000001,
11052} DWB_GMC_WARM_UP_ENABLE_ENUM;
11053
11054/*
11055 * DWB_MODE_WARMUP_ENUM enum
11056 */
11057
11058typedef enum DWB_MODE_WARMUP_ENUM {
11059DWB_MODE_WARMUP_420 = 0x00000000,
11060DWB_MODE_WARMUP_444 = 0x00000001,
11061} DWB_MODE_WARMUP_ENUM;
11062
11063/*
11064 * DWB_DATA_DEPTH_WARMUP_ENUM enum
11065 */
11066
11067typedef enum DWB_DATA_DEPTH_WARMUP_ENUM {
11068DWB_DATA_DEPTH_WARMUP_8BPC = 0x00000000,
11069DWB_DATA_DEPTH_WARMUP_10BPC = 0x00000001,
11070} DWB_DATA_DEPTH_WARMUP_ENUM;
11071
11072/*******************************************************
11073 * WBSCL Enums
11074 *******************************************************/
11075
11076/*
11077 * WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM enum
11078 */
11079
11080typedef enum WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM {
11081WBSCL_COEF_RAM_TAP_PAIR_IDX0 = 0x00000000,
11082WBSCL_COEF_RAM_TAP_PAIR_IDX1 = 0x00000001,
11083WBSCL_COEF_RAM_TAP_PAIR_IDX2 = 0x00000002,
11084WBSCL_COEF_RAM_TAP_PAIR_IDX3 = 0x00000003,
11085WBSCL_COEF_RAM_TAP_PAIR_IDX4 = 0x00000004,
11086WBSCL_COEF_RAM_TAP_PAIR_IDX5 = 0x00000005,
11087} WBSCL_COEF_RAM_TAP_PAIR_IDX_ENUM;
11088
11089/*
11090 * WBSCL_COEF_RAM_PHASE_ENUM enum
11091 */
11092
11093typedef enum WBSCL_COEF_RAM_PHASE_ENUM {
11094WBSCL_COEF_RAM_PHASE0 = 0x00000000,
11095WBSCL_COEF_RAM_PHASE1 = 0x00000001,
11096WBSCL_COEF_RAM_PHASE2 = 0x00000002,
11097WBSCL_COEF_RAM_PHASE3 = 0x00000003,
11098WBSCL_COEF_RAM_PHASE4 = 0x00000004,
11099WBSCL_COEF_RAM_PHASE5 = 0x00000005,
11100WBSCL_COEF_RAM_PHASE6 = 0x00000006,
11101WBSCL_COEF_RAM_PHASE7 = 0x00000007,
11102WBSCL_COEF_RAM_PHASE8 = 0x00000008,
11103} WBSCL_COEF_RAM_PHASE_ENUM;
11104
11105/*
11106 * WBSCL_COEF_RAM_FILTER_TYPE_ENUM enum
11107 */
11108
11109typedef enum WBSCL_COEF_RAM_FILTER_TYPE_ENUM {
11110WBSCL_COEF_RAM_FILTER_TYPE_VL = 0x00000000,
11111WBSCL_COEF_RAM_FILTER_TYPE_VC = 0x00000001,
11112WBSCL_COEF_RAM_FILTER_TYPE_HL = 0x00000002,
11113WBSCL_COEF_RAM_FILTER_TYPE_HC = 0x00000003,
11114} WBSCL_COEF_RAM_FILTER_TYPE_ENUM;
11115
11116/*
11117 * WBSCL_COEF_FILTER_TYPE_SEL enum
11118 */
11119
11120typedef enum WBSCL_COEF_FILTER_TYPE_SEL {
11121WBSCL_COEF_LUMA_VERT_FILTER = 0x00000000,
11122WBSCL_COEF_CHROMA_VERT_FILTER = 0x00000001,
11123WBSCL_COEF_LUMA_HORZ_FILTER = 0x00000002,
11124WBSCL_COEF_CHROMA_HORZ_FILTER = 0x00000003,
11125} WBSCL_COEF_FILTER_TYPE_SEL;
11126
11127/*
11128 * WBSCL_MODE_SEL enum
11129 */
11130
11131typedef enum WBSCL_MODE_SEL {
11132WBSCL_MODE_SCALING_444_BYPASS = 0x00000000,
11133WBSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001,
11134WBSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002,
11135WBSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003,
11136} WBSCL_MODE_SEL;
11137
11138/*
11139 * WBSCL_PIXEL_DEPTH enum
11140 */
11141
11142typedef enum WBSCL_PIXEL_DEPTH {
11143PIXEL_DEPTH_8BPC = 0x00000000,
11144PIXEL_DEPTH_10BPC = 0x00000001,
11145} WBSCL_PIXEL_DEPTH;
11146
11147/*
11148 * WBSCL_COEF_RAM_SEL_ENUM enum
11149 */
11150
11151typedef enum WBSCL_COEF_RAM_SEL_ENUM {
11152WBSCL_COEF_RAM_SEL_0 = 0x00000000,
11153WBSCL_COEF_RAM_SEL_1 = 0x00000001,
11154} WBSCL_COEF_RAM_SEL_ENUM;
11155
11156/*
11157 * WBSCL_COEF_RAM_RD_SEL_ENUM enum
11158 */
11159
11160typedef enum WBSCL_COEF_RAM_RD_SEL_ENUM {
11161WBSCL_COEF_RAM_RD_SEL_0 = 0x00000000,
11162WBSCL_COEF_RAM_RD_SEL_1 = 0x00000001,
11163} WBSCL_COEF_RAM_RD_SEL_ENUM;
11164
11165/*
11166 * WBSCL_COEF_RAM_TAP_COEF_EN_ENUM enum
11167 */
11168
11169typedef enum WBSCL_COEF_RAM_TAP_COEF_EN_ENUM {
11170WBSCL_COEF_RAM_TAP_COEF_DISABLE = 0x00000000,
11171WBSCL_COEF_RAM_TAP_COEF_ENABLE = 0x00000001,
11172} WBSCL_COEF_RAM_TAP_COEF_EN_ENUM;
11173
11174/*
11175 * WBSCL_NUM_OF_TAPS_ENUM enum
11176 */
11177
11178typedef enum WBSCL_NUM_OF_TAPS_ENUM {
11179WBSCL_NUM_OF_TAPS0 = 0x00000000,
11180WBSCL_NUM_OF_TAPS1 = 0x00000001,
11181WBSCL_NUM_OF_TAPS2 = 0x00000002,
11182WBSCL_NUM_OF_TAPS3 = 0x00000003,
11183WBSCL_NUM_OF_TAPS4 = 0x00000004,
11184WBSCL_NUM_OF_TAPS5 = 0x00000005,
11185WBSCL_NUM_OF_TAPS6 = 0x00000006,
11186WBSCL_NUM_OF_TAPS7 = 0x00000007,
11187WBSCL_NUM_OF_TAPS8 = 0x00000008,
11188WBSCL_NUM_OF_TAPS9 = 0x00000009,
11189WBSCL_NUM_OF_TAPS10 = 0x0000000a,
11190WBSCL_NUM_OF_TAPS11 = 0x0000000b,
11191} WBSCL_NUM_OF_TAPS_ENUM;
11192
11193/*
11194 * WBSCL_STATUS_ACK_ENUM enum
11195 */
11196
11197typedef enum WBSCL_STATUS_ACK_ENUM {
11198WBSCL_STATUS_ACK_NCLR = 0x00000000,
11199WBSCL_STATUS_ACK_CLR = 0x00000001,
11200} WBSCL_STATUS_ACK_ENUM;
11201
11202/*
11203 * WBSCL_STATUS_MASK_ENUM enum
11204 */
11205
11206typedef enum WBSCL_STATUS_MASK_ENUM {
11207WBSCL_STATUS_MASK_DISABLE = 0x00000000,
11208WBSCL_STATUS_MASK_ENABLE = 0x00000001,
11209} WBSCL_STATUS_MASK_ENUM;
11210
11211/*
11212 * WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM enum
11213 */
11214
11215typedef enum WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM {
11216WBSCL_DATA_OVERFLOW_INT_TYPE_REG = 0x00000000,
11217WBSCL_DATA_OVERFLOW_INT_TYPE_HW = 0x00000001,
11218} WBSCL_DATA_OVERFLOW_INT_TYPE_ENUM;
11219
11220/*
11221 * WBSCL_HOST_CONFLICT_INT_TYPE_ENUM enum
11222 */
11223
11224typedef enum WBSCL_HOST_CONFLICT_INT_TYPE_ENUM {
11225WBSCL_HOST_CONFLICT_INT_TYPE_REG = 0x00000000,
11226WBSCL_HOST_CONFLICT_INT_TYPE_HW = 0x00000001,
11227} WBSCL_HOST_CONFLICT_INT_TYPE_ENUM;
11228
11229/*
11230 * WBSCL_TEST_CRC_EN_ENUM enum
11231 */
11232
11233typedef enum WBSCL_TEST_CRC_EN_ENUM {
11234WBSCL_TEST_CRC_DISABLE = 0x00000000,
11235WBSCL_TEST_CRC_ENABLE = 0x00000001,
11236} WBSCL_TEST_CRC_EN_ENUM;
11237
11238/*
11239 * WBSCL_TEST_CRC_CONT_EN_ENUM enum
11240 */
11241
11242typedef enum WBSCL_TEST_CRC_CONT_EN_ENUM {
11243WBSCL_TEST_CRC_CONT_DISABLE = 0x00000000,
11244WBSCL_TEST_CRC_CONT_ENABLE = 0x00000001,
11245} WBSCL_TEST_CRC_CONT_EN_ENUM;
11246
11247/*
11248 * WBSCL_TEST_CRC_MASK_ENUM enum
11249 */
11250
11251typedef enum WBSCL_TEST_CRC_MASK_ENUM {
11252WBSCL_TEST_CRC_MASKED = 0x00000000,
11253WBSCL_TEST_CRC_UNMASKED = 0x00000001,
11254} WBSCL_TEST_CRC_MASK_ENUM;
11255
11256/*
11257 * WBSCL_BACKPRESSURE_CNT_EN_ENUM enum
11258 */
11259
11260typedef enum WBSCL_BACKPRESSURE_CNT_EN_ENUM {
11261WBSCL_BACKPRESSURE_CNT_DISABLE = 0x00000000,
11262WBSCL_BACKPRESSURE_CNT_ENABLE = 0x00000001,
11263} WBSCL_BACKPRESSURE_CNT_EN_ENUM;
11264
11265/*
11266 * WBSCL_OUTSIDE_PIX_STRATEGY_ENUM enum
11267 */
11268
11269typedef enum WBSCL_OUTSIDE_PIX_STRATEGY_ENUM {
11270WBSCL_OUTSIDE_PIX_STRATEGY_BLACK = 0x00000000,
11271WBSCL_OUTSIDE_PIX_STRATEGY_EDGE = 0x00000001,
11272} WBSCL_OUTSIDE_PIX_STRATEGY_ENUM;
11273
11274/*******************************************************
11275 * DPCSRX Enums
11276 *******************************************************/
11277
11278/*
11279 * DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL enum
11280 */
11281
11282typedef enum DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL {
11283DPCSRX_BPHY_PCS_RX0_CLK = 0x00000000,
11284DPCSRX_BPHY_PCS_RX1_CLK = 0x00000001,
11285DPCSRX_BPHY_PCS_RX2_CLK = 0x00000002,
11286DPCSRX_BPHY_PCS_RX3_CLK = 0x00000003,
11287} DPCSRX_RX_CLOCK_CNTL_DPCS_SYMCLK_RX_SEL;
11288
11289/*******************************************************
11290 * DPCSTX Enums
11291 *******************************************************/
11292
11293/*
11294 * DPCSTX_DVI_LINK_MODE enum
11295 */
11296
11297typedef enum DPCSTX_DVI_LINK_MODE {
11298DPCSTX_DVI_LINK_MODE_NORMAL = 0x00000000,
11299DPCSTX_DVI_LINK_MODE_DUAL_LINK_MASTER = 0x00000001,
11300DPCSTX_DVI_LINK_MODE_DUAL_LINK_SLAVER = 0x00000002,
11301} DPCSTX_DVI_LINK_MODE;
11302
11303/*******************************************************
11304 * RDPCSTX Enums
11305 *******************************************************/
11306
11307/*
11308 * RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET enum
11309 */
11310
11311typedef enum RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET {
11312RDPCS_CBUS_SOFT_RESET_DISABLE = 0x00000000,
11313RDPCS_CBUS_SOFT_RESET_ENABLE = 0x00000001,
11314} RDPCSTX_CNTL_RDPCS_CBUS_SOFT_RESET;
11315
11316/*
11317 * RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET enum
11318 */
11319
11320typedef enum RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET {
11321RDPCS_SRAM_SRAM_RESET_DISABLE = 0x00000000,
11322} RDPCSTX_CNTL_RDPCS_SRAM_SOFT_RESET;
11323
11324/*
11325 * RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN enum
11326 */
11327
11328typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN {
11329RDPCS_TX_FIFO_LANE_DISABLE = 0x00000000,
11330RDPCS_TX_FIFO_LANE_ENABLE = 0x00000001,
11331} RDPCSTX_CNTL_RDPCS_TX_FIFO_LANE_EN;
11332
11333/*
11334 * RDPCSTX_CNTL_RDPCS_TX_FIFO_EN enum
11335 */
11336
11337typedef enum RDPCSTX_CNTL_RDPCS_TX_FIFO_EN {
11338RDPCS_TX_FIFO_DISABLE = 0x00000000,
11339RDPCS_TX_FIFO_ENABLE = 0x00000001,
11340} RDPCSTX_CNTL_RDPCS_TX_FIFO_EN;
11341
11342/*
11343 * RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET enum
11344 */
11345
11346typedef enum RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET {
11347RDPCS_TX_SOFT_RESET_DISABLE = 0x00000000,
11348RDPCS_TX_SOFT_RESET_ENABLE = 0x00000001,
11349} RDPCSTX_CNTL_RDPCS_TX_SOFT_RESET;
11350
11351/*
11352 * RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN enum
11353 */
11354
11355typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN {
11356RDPCS_EXT_REFCLK_DISABLE = 0x00000000,
11357RDPCS_EXT_REFCLK_ENABLE = 0x00000001,
11358} RDPCSTX_CLOCK_CNTL_RDPCS_EXT_REFCLK_EN;
11359
11360/*
11361 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN enum
11362 */
11363
11364typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN {
11365RDPCS_EXT_REFCLK_EN_DISABLE = 0x00000000,
11366RDPCS_EXT_REFCLK_EN_ENABLE = 0x00000001,
11367} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_TX_EN;
11368
11369/*
11370 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS enum
11371 */
11372
11373typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS {
11374RDPCS_SYMCLK_DIV2_GATE_ENABLE = 0x00000000,
11375RDPCS_SYMCLK_DIV2_GATE_DISABLE = 0x00000001,
11376} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_GATE_DIS;
11377
11378/*
11379 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN enum
11380 */
11381
11382typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN {
11383RDPCS_SYMCLK_DIV2_DISABLE = 0x00000000,
11384RDPCS_SYMCLK_DIV2_ENABLE = 0x00000001,
11385} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_EN;
11386
11387/*
11388 * RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON enum
11389 */
11390
11391typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON {
11392RDPCS_SYMCLK_DIV2_CLOCK_OFF = 0x00000000,
11393RDPCS_SYMCLK_DIV2_CLOCK_ON = 0x00000001,
11394} RDPCSTX_CLOCK_CNTL_RDPCS_SYMCLK_DIV2_CLOCK_ON;
11395
11396/*
11397 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS enum
11398 */
11399
11400typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS {
11401RDPCS_SRAMCLK_GATE_ENABLE = 0x00000000,
11402RDPCS_SRAMCLK_GATE_DISABLE = 0x00000001,
11403} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_GATE_DIS;
11404
11405/*
11406 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN enum
11407 */
11408
11409typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN {
11410RDPCS_SRAMCLK_DISABLE = 0x00000000,
11411RDPCS_SRAMCLK_ENABLE = 0x00000001,
11412} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_EN;
11413
11414/*
11415 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS enum
11416 */
11417
11418typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS {
11419RDPCS_SRAMCLK_NOT_BYPASS = 0x00000000,
11420RDPCS_SRAMCLK_BYPASS = 0x00000001,
11421} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_BYPASS;
11422
11423/*
11424 * RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON enum
11425 */
11426
11427typedef enum RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON {
11428RDPCS_SYMCLK_SRAMCLK_CLOCK_OFF = 0x00000000,
11429RDPCS_SYMCLK_SRAMCLK_CLOCK_ON = 0x00000001,
11430} RDPCSTX_CLOCK_CNTL_RDPCS_SRAMCLK_CLOCK_ON;
11431
11432/*
11433 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE enum
11434 */
11435
11436typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE {
11437RDPCS_DPALT_DISABLE_TOGGLE_ENABLE = 0x00000000,
11438RDPCS_DPALT_DISABLE_TOGGLE_DISABLE = 0x00000001,
11439} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE;
11440
11441/*
11442 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE enum
11443 */
11444
11445typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE {
11446RDPCS_DPALT_4LANE_TOGGLE_2LANE = 0x00000000,
11447RDPCS_DPALT_4LANE_TOGGLE_4LANE = 0x00000001,
11448} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE;
11449
11450/*
11451 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK enum
11452 */
11453
11454typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK {
11455RDPCS_REG_FIFO_ERROR_MASK_DISABLE = 0x00000000,
11456RDPCS_REG_FIFO_ERROR_MASK_ENABLE = 0x00000001,
11457} RDPCSTX_INTERRUPT_CONTROL_RDPCS_REG_FIFO_ERROR_MASK;
11458
11459/*
11460 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK enum
11461 */
11462
11463typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK {
11464RDPCS_DPALT_DISABLE_TOGGLE_MASK_DISABLE = 0x00000000,
11465RDPCS_DPALT_DISABLE_TOGGLE_MASK_ENABLE = 0x00000001,
11466} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_DISABLE_TOGGLE_MASK;
11467
11468/*
11469 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK enum
11470 */
11471
11472typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK {
11473RDPCS_DPALT_4LANE_TOGGLE_MASK_DISABLE = 0x00000000,
11474RDPCS_DPALT_4LANE_TOGGLE_MASK_ENABLE = 0x00000001,
11475} RDPCSTX_INTERRUPT_CONTROL_RDPCS_DPALT_4LANE_TOGGLE_MASK;
11476
11477/*
11478 * RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK enum
11479 */
11480
11481typedef enum RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK {
11482RDPCS_TX_FIFO_ERROR_MASK_DISABLE = 0x00000000,
11483RDPCS_TX_FIFO_ERROR_MASK_ENABLE = 0x00000001,
11484} RDPCSTX_INTERRUPT_CONTROL_RDPCS_TX_FIFO_ERROR_MASK;
11485
11486/*
11487 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE enum
11488 */
11489
11490typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE {
11491RDPCS_MEM_PWR_NO_FORCE = 0x00000000,
11492RDPCS_MEM_PWR_LIGHT_SLEEP = 0x00000001,
11493RDPCS_MEM_PWR_DEEP_SLEEP = 0x00000002,
11494RDPCS_MEM_PWR_SHUT_DOWN = 0x00000003,
11495} RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_FORCE;
11496
11497/*
11498 * RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE enum
11499 */
11500
11501typedef enum RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE {
11502RDPCS_MEM_PWR_PWR_STATE_ON = 0x00000000,
11503RDPCS_MEM_PWR_PWR_STATE_LIGHT_SLEEP = 0x00000001,
11504RDPCS_MEM_PWR_PWR_STATE_DEEP_SLEEP = 0x00000002,
11505RDPCS_MEM_PWR_PWR_STATE_SHUT_DOWN = 0x00000003,
11506} RDPCS_TX_SRAM_CNTL_RDPCS_MEM_PWR_PWR_STATE;
11507
11508/*
11509 * RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF enum
11510 */
11511
11512typedef enum RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF {
11513RDPCS_MEM_POWER_CTRL_POFF_FOR_NO_PERIPHERY = 0x00000000,
11514RDPCS_MEM_POWER_CTRL_POFF_FOR_STANDARD = 0x00000001,
11515RDPCS_MEM_POWER_CTRL_POFF_FOR_RM3 = 0x00000002,
11516RDPCS_MEM_POWER_CTRL_POFF_FOR_SD = 0x00000003,
11517} RDPCSTX_MEM_POWER_CTRL2_RDPCS_MEM_POWER_CTRL_POFF;
11518
11519/*
11520 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE enum
11521 */
11522
11523typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE {
11524RDPCS_PHY_REF_RANGE_0 = 0x00000000,
11525RDPCS_PHY_REF_RANGE_1 = 0x00000001,
11526RDPCS_PHY_REF_RANGE_2 = 0x00000002,
11527RDPCS_PHY_REF_RANGE_3 = 0x00000003,
11528RDPCS_PHY_REF_RANGE_4 = 0x00000004,
11529RDPCS_PHY_REF_RANGE_5 = 0x00000005,
11530RDPCS_PHY_REF_RANGE_6 = 0x00000006,
11531RDPCS_PHY_REF_RANGE_7 = 0x00000007,
11532} RDPCSTX_PHY_CNTL0_RDPCS_PHY_REF_RANGE;
11533
11534/*
11535 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL enum
11536 */
11537
11538typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL {
11539RDPCS_PHY_CR_PARA_SEL_JTAG = 0x00000000,
11540RDPCS_PHY_CR_PARA_SEL_CR = 0x00000001,
11541} RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_PARA_SEL;
11542
11543/*
11544 * RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL enum
11545 */
11546
11547typedef enum RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL {
11548RDPCS_PHY_CR_MUX_SEL_FOR_USB = 0x00000000,
11549RDPCS_PHY_CR_MUX_SEL_FOR_DC = 0x00000001,
11550} RDPCSTX_PHY_CNTL0_RDPCS_PHY_CR_MUX_SEL;
11551
11552/*
11553 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE enum
11554 */
11555
11556typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE {
11557RDPCS_SRAM_INIT_NOT_DONE = 0x00000000,
11558RDPCS_SRAM_INIT_DONE = 0x00000001,
11559} RDPCSTX_PHY_CNTL0_RDPCS_SRAM_INIT_DONE;
11560
11561/*
11562 * RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE enum
11563 */
11564
11565typedef enum RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE {
11566RDPCS_SRAM_EXT_LD_NOT_DONE = 0x00000000,
11567RDPCS_SRAM_EXT_LD_DONE = 0x00000001,
11568} RDPCSTX_PHY_CNTL0_RDPCS_SRAM_EXT_LD_DONE;
11569
11570/*
11571 * RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL enum
11572 */
11573
11574typedef enum RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL {
11575RDPCS_PHY_DP_TX_TERM_CTRL_54 = 0x00000000,
11576RDPCS_PHY_DP_TX_TERM_CTRL_52 = 0x00000001,
11577RDPCS_PHY_DP_TX_TERM_CTRL_50 = 0x00000002,
11578RDPCS_PHY_DP_TX_TERM_CTRL_48 = 0x00000003,
11579RDPCS_PHY_DP_TX_TERM_CTRL_46 = 0x00000004,
11580RDPCS_PHY_DP_TX_TERM_CTRL_44 = 0x00000005,
11581RDPCS_PHY_DP_TX_TERM_CTRL_42 = 0x00000006,
11582RDPCS_PHY_DP_TX_TERM_CTRL_40 = 0x00000007,
11583} RDPCSTX_PHY_CNTL4_RDPCS_PHY_DP_TX_TERM_CTRL;
11584
11585/*
11586 * RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE enum
11587 */
11588
11589typedef enum RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE {
11590RRDPCS_PHY_DP_TX_PSTATE_POWER_UP = 0x00000000,
11591RRDPCS_PHY_DP_TX_PSTATE_HOLD = 0x00000001,
11592RRDPCS_PHY_DP_TX_PSTATE_HOLD_OFF = 0x00000002,
11593RRDPCS_PHY_DP_TX_PSTATE_POWER_DOWN = 0x00000003,
11594} RDPCSTX_PHY_CNTL_RRDPCS_PHY_DP_TX_PSTATE;
11595
11596/*
11597 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE enum
11598 */
11599
11600typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE {
11601RDPCS_PHY_DP_TX_RATE = 0x00000000,
11602RDPCS_PHY_DP_TX_RATE_DIV2 = 0x00000001,
11603RDPCS_PHY_DP_TX_RATE_DIV4 = 0x00000002,
11604} RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_RATE;
11605
11606/*
11607 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH enum
11608 */
11609
11610typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH {
11611RDPCS_PHY_DP_TX_WIDTH_8 = 0x00000000,
11612RDPCS_PHY_DP_TX_WIDTH_10 = 0x00000001,
11613RDPCS_PHY_DP_TX_WIDTH_16 = 0x00000002,
11614RDPCS_PHY_DP_TX_WIDTH_20 = 0x00000003,
11615} RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_WIDTH;
11616
11617/*
11618 * RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT enum
11619 */
11620
11621typedef enum RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT {
11622RDPCS_PHY_DP_TX_DETRX_RESULT_NO_DETECT = 0x00000000,
11623RDPCS_PHY_DP_TX_DETRX_RESULT_DETECT = 0x00000001,
11624} RDPCSTX_PHY_CNTL_RDPCS_PHY_DP_TX_DETRX_RESULT;
11625
11626/*
11627 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV enum
11628 */
11629
11630typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV {
11631RDPCS_PHY_DP_REF_CLK_MPLLB_DIV1 = 0x00000000,
11632RDPCS_PHY_DP_REF_CLK_MPLLB_DIV2 = 0x00000001,
11633RDPCS_PHY_DP_REF_CLK_MPLLB_DIV3 = 0x00000002,
11634RDPCS_PHY_DP_REF_CLK_MPLLB_DIV8 = 0x00000003,
11635RDPCS_PHY_DP_REF_CLK_MPLLB_DIV16 = 0x00000004,
11636} RDPCSTX_PHY_CNTL11_RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;
11637
11638/*
11639 * RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV enum
11640 */
11641
11642typedef enum RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV {
11643RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_0 = 0x00000000,
11644RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_1 = 0x00000001,
11645RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_2 = 0x00000002,
11646RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV_3 = 0x00000003,
11647} RDPCSTX_PHY_CNTL11_RDPCS_PHY_HDMI_MPLLB_HDMI_PIXEL_CLK_DIV;
11648
11649/*
11650 * RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV enum
11651 */
11652
11653typedef enum RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV {
11654RDPCS_PHY_DP_MPLLB_TX_CLK_DIV = 0x00000000,
11655RDPCS_PHY_DP_MPLLB_TX_CLK_DIV2 = 0x00000001,
11656RDPCS_PHY_DP_MPLLB_TX_CLK_DIV4 = 0x00000002,
11657RDPCS_PHY_DP_MPLLB_TX_CLK_DIV8 = 0x00000003,
11658RDPCS_PHY_DP_MPLLB_TX_CLK_DIV3 = 0x00000004,
11659RDPCS_PHY_DP_MPLLB_TX_CLK_DIV5 = 0x00000005,
11660RDPCS_PHY_DP_MPLLB_TX_CLK_DIV6 = 0x00000006,
11661RDPCS_PHY_DP_MPLLB_TX_CLK_DIV10 = 0x00000007,
11662} RDPCSTX_PHY_CNTL12_RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;
11663
11664/*
11665 * RDPCS_TEST_CLK_SEL enum
11666 */
11667
11668typedef enum RDPCS_TEST_CLK_SEL {
11669RDPCS_TEST_CLK_SEL_NONE = 0x00000000,
11670RDPCS_TEST_CLK_SEL_CFGCLK = 0x00000001,
11671RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS = 0x00000002,
11672RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS = 0x00000003,
11673RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_LDPCS_DIV4 = 0x00000004,
11674RDPCS_TEST_CLK_SEL_SYMCLK_DIV2_RDPCS_DIV4 = 0x00000005,
11675RDPCS_TEST_CLK_SEL_SRAMCLK = 0x00000006,
11676RDPCS_TEST_CLK_SEL_EXT_CR_CLK = 0x00000007,
11677RDPCS_TEST_CLK_SEL_DP_TX0_WORD_CLK = 0x00000008,
11678RDPCS_TEST_CLK_SEL_DP_TX1_WORD_CLK = 0x00000009,
11679RDPCS_TEST_CLK_SEL_DP_TX2_WORD_CLK = 0x0000000a,
11680RDPCS_TEST_CLK_SEL_DP_TX3_WORD_CLK = 0x0000000b,
11681RDPCS_TEST_CLK_SEL_DP_MPLLB_DIV_CLK = 0x0000000c,
11682RDPCS_TEST_CLK_SEL_HDMI_MPLLB_HDMI_PIXEL_CLK = 0x0000000d,
11683RDPCS_TEST_CLK_SEL_PHY_REF_DIG_CLK = 0x0000000e,
11684RDPCS_TEST_CLK_SEL_REF_DIG_FR_clk = 0x0000000f,
11685RDPCS_TEST_CLK_SEL_dtb_out0 = 0x00000010,
11686RDPCS_TEST_CLK_SEL_dtb_out1 = 0x00000011,
11687} RDPCS_TEST_CLK_SEL;
11688
11689/*******************************************************
11690 * CB Enums
11691 *******************************************************/
11692
11693/*
11694 * CBMode enum
11695 */
11696
11697typedef enum CBMode {
11698CB_DISABLE = 0x00000000,
11699CB_NORMAL = 0x00000001,
11700CB_ELIMINATE_FAST_CLEAR = 0x00000002,
11701CB_RESOLVE = 0x00000003,
11702CB_DECOMPRESS = 0x00000004,
11703CB_FMASK_DECOMPRESS = 0x00000005,
11704CB_DCC_DECOMPRESS = 0x00000006,
11705CB_RESERVED = 0x00000007,
11706} CBMode;
11707
11708/*
11709 * BlendOp enum
11710 */
11711
11712typedef enum BlendOp {
11713BLEND_ZERO = 0x00000000,
11714BLEND_ONE = 0x00000001,
11715BLEND_SRC_COLOR = 0x00000002,
11716BLEND_ONE_MINUS_SRC_COLOR = 0x00000003,
11717BLEND_SRC_ALPHA = 0x00000004,
11718BLEND_ONE_MINUS_SRC_ALPHA = 0x00000005,
11719BLEND_DST_ALPHA = 0x00000006,
11720BLEND_ONE_MINUS_DST_ALPHA = 0x00000007,
11721BLEND_DST_COLOR = 0x00000008,
11722BLEND_ONE_MINUS_DST_COLOR = 0x00000009,
11723BLEND_SRC_ALPHA_SATURATE = 0x0000000a,
11724BLEND_BOTH_SRC_ALPHA = 0x0000000b,
11725BLEND_BOTH_INV_SRC_ALPHA = 0x0000000c,
11726BLEND_CONSTANT_COLOR = 0x0000000d,
11727BLEND_ONE_MINUS_CONSTANT_COLOR = 0x0000000e,
11728BLEND_SRC1_COLOR = 0x0000000f,
11729BLEND_INV_SRC1_COLOR = 0x00000010,
11730BLEND_SRC1_ALPHA = 0x00000011,
11731BLEND_INV_SRC1_ALPHA = 0x00000012,
11732BLEND_CONSTANT_ALPHA = 0x00000013,
11733BLEND_ONE_MINUS_CONSTANT_ALPHA = 0x00000014,
11734} BlendOp;
11735
11736/*
11737 * CombFunc enum
11738 */
11739
11740typedef enum CombFunc {
11741COMB_DST_PLUS_SRC = 0x00000000,
11742COMB_SRC_MINUS_DST = 0x00000001,
11743COMB_MIN_DST_SRC = 0x00000002,
11744COMB_MAX_DST_SRC = 0x00000003,
11745COMB_DST_MINUS_SRC = 0x00000004,
11746} CombFunc;
11747
11748/*
11749 * BlendOpt enum
11750 */
11751
11752typedef enum BlendOpt {
11753FORCE_OPT_AUTO = 0x00000000,
11754FORCE_OPT_DISABLE = 0x00000001,
11755FORCE_OPT_ENABLE_IF_SRC_A_0 = 0x00000002,
11756FORCE_OPT_ENABLE_IF_SRC_RGB_0 = 0x00000003,
11757FORCE_OPT_ENABLE_IF_SRC_ARGB_0 = 0x00000004,
11758FORCE_OPT_ENABLE_IF_SRC_A_1 = 0x00000005,
11759FORCE_OPT_ENABLE_IF_SRC_RGB_1 = 0x00000006,
11760FORCE_OPT_ENABLE_IF_SRC_ARGB_1 = 0x00000007,
11761} BlendOpt;
11762
11763/*
11764 * CmaskCode enum
11765 */
11766
11767typedef enum CmaskCode {
11768CMASK_CLR00_F0 = 0x00000000,
11769CMASK_CLR00_F1 = 0x00000001,
11770CMASK_CLR00_F2 = 0x00000002,
11771CMASK_CLR00_FX = 0x00000003,
11772CMASK_CLR01_F0 = 0x00000004,
11773CMASK_CLR01_F1 = 0x00000005,
11774CMASK_CLR01_F2 = 0x00000006,
11775CMASK_CLR01_FX = 0x00000007,
11776CMASK_CLR10_F0 = 0x00000008,
11777CMASK_CLR10_F1 = 0x00000009,
11778CMASK_CLR10_F2 = 0x0000000a,
11779CMASK_CLR10_FX = 0x0000000b,
11780CMASK_CLR11_F0 = 0x0000000c,
11781CMASK_CLR11_F1 = 0x0000000d,
11782CMASK_CLR11_F2 = 0x0000000e,
11783CMASK_CLR11_FX = 0x0000000f,
11784} CmaskCode;
11785
11786/*
11787 * MemArbMode enum
11788 */
11789
11790typedef enum MemArbMode {
11791MEM_ARB_MODE_FIXED = 0x00000000,
11792MEM_ARB_MODE_AGE = 0x00000001,
11793MEM_ARB_MODE_WEIGHT = 0x00000002,
11794MEM_ARB_MODE_BOTH = 0x00000003,
11795} MemArbMode;
11796
11797/*
11798 * CBPerfOpFilterSel enum
11799 */
11800
11801typedef enum CBPerfOpFilterSel {
11802CB_PERF_OP_FILTER_SEL_WRITE_ONLY = 0x00000000,
11803CB_PERF_OP_FILTER_SEL_NEEDS_DESTINATION = 0x00000001,
11804CB_PERF_OP_FILTER_SEL_RESOLVE = 0x00000002,
11805CB_PERF_OP_FILTER_SEL_DECOMPRESS = 0x00000003,
11806CB_PERF_OP_FILTER_SEL_FMASK_DECOMPRESS = 0x00000004,
11807CB_PERF_OP_FILTER_SEL_ELIMINATE_FAST_CLEAR = 0x00000005,
11808} CBPerfOpFilterSel;
11809
11810/*
11811 * CBPerfClearFilterSel enum
11812 */
11813
11814typedef enum CBPerfClearFilterSel {
11815CB_PERF_CLEAR_FILTER_SEL_NONCLEAR = 0x00000000,
11816CB_PERF_CLEAR_FILTER_SEL_CLEAR = 0x00000001,
11817} CBPerfClearFilterSel;
11818
11819/*
11820 * CBPerfSel enum
11821 */
11822
11823typedef enum CBPerfSel {
11824CB_PERF_SEL_NONE = 0x00000000,
11825CB_PERF_SEL_BUSY = 0x00000001,
11826CB_PERF_SEL_CORE_SCLK_VLD = 0x00000002,
11827CB_PERF_SEL_REG_SCLK0_VLD = 0x00000003,
11828CB_PERF_SEL_REG_SCLK1_VLD = 0x00000004,
11829CB_PERF_SEL_DRAWN_QUAD = 0x00000005,
11830CB_PERF_SEL_DRAWN_PIXEL = 0x00000006,
11831CB_PERF_SEL_DRAWN_QUAD_FRAGMENT = 0x00000007,
11832CB_PERF_SEL_DRAWN_TILE = 0x00000008,
11833CB_PERF_SEL_DB_CB_TILE_VALID_READY = 0x00000009,
11834CB_PERF_SEL_DB_CB_TILE_VALID_READYB = 0x0000000a,
11835CB_PERF_SEL_DB_CB_TILE_VALIDB_READY = 0x0000000b,
11836CB_PERF_SEL_DB_CB_TILE_VALIDB_READYB = 0x0000000c,
11837CB_PERF_SEL_CM_FC_TILE_VALID_READY = 0x0000000d,
11838CB_PERF_SEL_CM_FC_TILE_VALID_READYB = 0x0000000e,
11839CB_PERF_SEL_CM_FC_TILE_VALIDB_READY = 0x0000000f,
11840CB_PERF_SEL_CM_FC_TILE_VALIDB_READYB = 0x00000010,
11841CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READY = 0x00000011,
11842CB_PERF_SEL_MERGE_TILE_ONLY_VALID_READYB = 0x00000012,
11843CB_PERF_SEL_DB_CB_LQUAD_VALID_READY = 0x00000013,
11844CB_PERF_SEL_DB_CB_LQUAD_VALID_READYB = 0x00000014,
11845CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READY = 0x00000015,
11846CB_PERF_SEL_DB_CB_LQUAD_VALIDB_READYB = 0x00000016,
11847CB_PERF_SEL_LQUAD_NO_TILE = 0x00000017,
11848CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_R = 0x00000018,
11849CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_AR = 0x00000019,
11850CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_GR = 0x0000001a,
11851CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32_ABGR = 0x0000001b,
11852CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_FP16_ABGR = 0x0000001c,
11853CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_SIGNED16_ABGR = 0x0000001d,
11854CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_UNSIGNED16_ABGR = 0x0000001e,
11855CB_PERF_SEL_QUAD_KILLED_BY_EXTRA_PIXEL_EXPORT = 0x0000001f,
11856CB_PERF_SEL_QUAD_KILLED_BY_COLOR_INVALID = 0x00000020,
11857CB_PERF_SEL_QUAD_KILLED_BY_NULL_TARGET_SHADER_MASK = 0x00000021,
11858CB_PERF_SEL_QUAD_KILLED_BY_NULL_SAMPLE_MASK = 0x00000022,
11859CB_PERF_SEL_QUAD_KILLED_BY_DISCARD_PIXEL = 0x00000023,
11860CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READY = 0x00000024,
11861CB_PERF_SEL_FC_CLEAR_QUAD_VALID_READYB = 0x00000025,
11862CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READY = 0x00000026,
11863CB_PERF_SEL_FC_CLEAR_QUAD_VALIDB_READYB = 0x00000027,
11864CB_PERF_SEL_FOP_IN_VALID_READY = 0x00000028,
11865CB_PERF_SEL_FOP_IN_VALID_READYB = 0x00000029,
11866CB_PERF_SEL_FOP_IN_VALIDB_READY = 0x0000002a,
11867CB_PERF_SEL_FOP_IN_VALIDB_READYB = 0x0000002b,
11868CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READY = 0x0000002c,
11869CB_PERF_SEL_FC_CC_QUADFRAG_VALID_READYB = 0x0000002d,
11870CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READY = 0x0000002e,
11871CB_PERF_SEL_FC_CC_QUADFRAG_VALIDB_READYB = 0x0000002f,
11872CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READY = 0x00000030,
11873CB_PERF_SEL_CC_IB_SR_FRAG_VALID_READYB = 0x00000031,
11874CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READY = 0x00000032,
11875CB_PERF_SEL_CC_IB_SR_FRAG_VALIDB_READYB = 0x00000033,
11876CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READY = 0x00000034,
11877CB_PERF_SEL_CC_IB_TB_FRAG_VALID_READYB = 0x00000035,
11878CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READY = 0x00000036,
11879CB_PERF_SEL_CC_IB_TB_FRAG_VALIDB_READYB = 0x00000037,
11880CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READY = 0x00000038,
11881CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALID_READYB = 0x00000039,
11882CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READY = 0x0000003a,
11883CB_PERF_SEL_CC_RB_BC_EVENFRAG_VALIDB_READYB = 0x0000003b,
11884CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READY = 0x0000003c,
11885CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALID_READYB = 0x0000003d,
11886CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READY = 0x0000003e,
11887CB_PERF_SEL_CC_RB_BC_ODDFRAG_VALIDB_READYB = 0x0000003f,
11888CB_PERF_SEL_CC_BC_CS_FRAG_VALID = 0x00000040,
11889CB_PERF_SEL_CM_CACHE_HIT = 0x00000041,
11890CB_PERF_SEL_CM_CACHE_TAG_MISS = 0x00000042,
11891CB_PERF_SEL_CM_CACHE_SECTOR_MISS = 0x00000043,
11892CB_PERF_SEL_CM_CACHE_REEVICTION_STALL = 0x00000044,
11893CB_PERF_SEL_CM_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000045,
11894CB_PERF_SEL_CM_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000046,
11895CB_PERF_SEL_CM_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000047,
11896CB_PERF_SEL_CM_CACHE_READ_OUTPUT_STALL = 0x00000048,
11897CB_PERF_SEL_CM_CACHE_WRITE_OUTPUT_STALL = 0x00000049,
11898CB_PERF_SEL_CM_CACHE_ACK_OUTPUT_STALL = 0x0000004a,
11899CB_PERF_SEL_CM_CACHE_STALL = 0x0000004b,
11900CB_PERF_SEL_CM_CACHE_FLUSH = 0x0000004c,
11901CB_PERF_SEL_CM_CACHE_TAGS_FLUSHED = 0x0000004d,
11902CB_PERF_SEL_CM_CACHE_SECTORS_FLUSHED = 0x0000004e,
11903CB_PERF_SEL_CM_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000004f,
11904CB_PERF_SEL_FC_CACHE_HIT = 0x00000050,
11905CB_PERF_SEL_FC_CACHE_TAG_MISS = 0x00000051,
11906CB_PERF_SEL_FC_CACHE_SECTOR_MISS = 0x00000052,
11907CB_PERF_SEL_FC_CACHE_REEVICTION_STALL = 0x00000053,
11908CB_PERF_SEL_FC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000054,
11909CB_PERF_SEL_FC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000055,
11910CB_PERF_SEL_FC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000056,
11911CB_PERF_SEL_FC_CACHE_READ_OUTPUT_STALL = 0x00000057,
11912CB_PERF_SEL_FC_CACHE_WRITE_OUTPUT_STALL = 0x00000058,
11913CB_PERF_SEL_FC_CACHE_ACK_OUTPUT_STALL = 0x00000059,
11914CB_PERF_SEL_FC_CACHE_STALL = 0x0000005a,
11915CB_PERF_SEL_FC_CACHE_FLUSH = 0x0000005b,
11916CB_PERF_SEL_FC_CACHE_TAGS_FLUSHED = 0x0000005c,
11917CB_PERF_SEL_FC_CACHE_SECTORS_FLUSHED = 0x0000005d,
11918CB_PERF_SEL_FC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000005e,
11919CB_PERF_SEL_CC_CACHE_HIT = 0x0000005f,
11920CB_PERF_SEL_CC_CACHE_TAG_MISS = 0x00000060,
11921CB_PERF_SEL_CC_CACHE_SECTOR_MISS = 0x00000061,
11922CB_PERF_SEL_CC_CACHE_REEVICTION_STALL = 0x00000062,
11923CB_PERF_SEL_CC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x00000063,
11924CB_PERF_SEL_CC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x00000064,
11925CB_PERF_SEL_CC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x00000065,
11926CB_PERF_SEL_CC_CACHE_READ_OUTPUT_STALL = 0x00000066,
11927CB_PERF_SEL_CC_CACHE_WRITE_OUTPUT_STALL = 0x00000067,
11928CB_PERF_SEL_CC_CACHE_ACK_OUTPUT_STALL = 0x00000068,
11929CB_PERF_SEL_CC_CACHE_STALL = 0x00000069,
11930CB_PERF_SEL_CC_CACHE_FLUSH = 0x0000006a,
11931CB_PERF_SEL_CC_CACHE_TAGS_FLUSHED = 0x0000006b,
11932CB_PERF_SEL_CC_CACHE_SECTORS_FLUSHED = 0x0000006c,
11933CB_PERF_SEL_CC_CACHE_DIRTY_SECTORS_FLUSHED = 0x0000006d,
11934CB_PERF_SEL_CC_CACHE_WA_TO_RMW_CONVERSION = 0x0000006e,
11935CB_PERF_SEL_CB_TAP_WRREQ_VALID_READY = 0x0000006f,
11936CB_PERF_SEL_CB_TAP_WRREQ_VALID_READYB = 0x00000070,
11937CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READY = 0x00000071,
11938CB_PERF_SEL_CB_TAP_WRREQ_VALIDB_READYB = 0x00000072,
11939CB_PERF_SEL_CM_MC_WRITE_REQUEST = 0x00000073,
11940CB_PERF_SEL_FC_MC_WRITE_REQUEST = 0x00000074,
11941CB_PERF_SEL_CC_MC_WRITE_REQUEST = 0x00000075,
11942CB_PERF_SEL_CM_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000076,
11943CB_PERF_SEL_FC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000077,
11944CB_PERF_SEL_CC_MC_WRITE_REQUESTS_IN_FLIGHT = 0x00000078,
11945CB_PERF_SEL_CB_TAP_RDREQ_VALID_READY = 0x00000079,
11946CB_PERF_SEL_CB_TAP_RDREQ_VALID_READYB = 0x0000007a,
11947CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READY = 0x0000007b,
11948CB_PERF_SEL_CB_TAP_RDREQ_VALIDB_READYB = 0x0000007c,
11949CB_PERF_SEL_CM_MC_READ_REQUEST = 0x0000007d,
11950CB_PERF_SEL_FC_MC_READ_REQUEST = 0x0000007e,
11951CB_PERF_SEL_CC_MC_READ_REQUEST = 0x0000007f,
11952CB_PERF_SEL_CM_MC_READ_REQUESTS_IN_FLIGHT = 0x00000080,
11953CB_PERF_SEL_FC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000081,
11954CB_PERF_SEL_CC_MC_READ_REQUESTS_IN_FLIGHT = 0x00000082,
11955CB_PERF_SEL_CM_TQ_FULL = 0x00000083,
11956CB_PERF_SEL_CM_TQ_FIFO_TILE_RESIDENCY_STALL = 0x00000084,
11957CB_PERF_SEL_CM_TQ_FIFO_STUTTER_STALL = 0x00000085,
11958CB_PERF_SEL_FC_QUAD_RDLAT_FIFO_FULL = 0x00000086,
11959CB_PERF_SEL_FC_TILE_RDLAT_FIFO_FULL = 0x00000087,
11960CB_PERF_SEL_FC_RDLAT_FIFO_QUAD_RESIDENCY_STALL = 0x00000088,
11961CB_PERF_SEL_FC_TILE_STUTTER_STALL = 0x00000089,
11962CB_PERF_SEL_FC_QUAD_STUTTER_STALL = 0x0000008a,
11963CB_PERF_SEL_FC_KEYID_STUTTER_STALL = 0x0000008b,
11964CB_PERF_SEL_FOP_FMASK_RAW_STALL = 0x0000008c,
11965CB_PERF_SEL_FOP_FMASK_BYPASS_STALL = 0x0000008d,
11966CB_PERF_SEL_CC_SF_FULL = 0x0000008e,
11967CB_PERF_SEL_CC_RB_FULL = 0x0000008f,
11968CB_PERF_SEL_CC_EVENFIFO_QUAD_RESIDENCY_STALL = 0x00000090,
11969CB_PERF_SEL_CC_ODDFIFO_QUAD_RESIDENCY_STALL = 0x00000091,
11970CB_PERF_SEL_CC_EVENFIFO_STUTTER_STALL = 0x00000092,
11971CB_PERF_SEL_CC_ODDFIFO_STUTTER_STALL = 0x00000093,
11972CB_PERF_SEL_BLENDER_RAW_HAZARD_STALL = 0x00000094,
11973CB_PERF_SEL_EVENT = 0x00000095,
11974CB_PERF_SEL_EVENT_CACHE_FLUSH_TS = 0x00000096,
11975CB_PERF_SEL_EVENT_CONTEXT_DONE = 0x00000097,
11976CB_PERF_SEL_EVENT_CACHE_FLUSH = 0x00000098,
11977CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000099,
11978CB_PERF_SEL_EVENT_CACHE_FLUSH_AND_INV_EVENT = 0x0000009a,
11979CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_DATA_TS = 0x0000009b,
11980CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_META = 0x0000009c,
11981CB_PERF_SEL_CC_SURFACE_SYNC = 0x0000009d,
11982CB_PERF_SEL_CMASK_READ_DATA_0xC = 0x0000009e,
11983CB_PERF_SEL_CMASK_READ_DATA_0xD = 0x0000009f,
11984CB_PERF_SEL_CMASK_READ_DATA_0xE = 0x000000a0,
11985CB_PERF_SEL_CMASK_READ_DATA_0xF = 0x000000a1,
11986CB_PERF_SEL_CMASK_WRITE_DATA_0xC = 0x000000a2,
11987CB_PERF_SEL_CMASK_WRITE_DATA_0xD = 0x000000a3,
11988CB_PERF_SEL_CMASK_WRITE_DATA_0xE = 0x000000a4,
11989CB_PERF_SEL_CMASK_WRITE_DATA_0xF = 0x000000a5,
11990CB_PERF_SEL_TWO_PROBE_QUAD_FRAGMENT = 0x000000a6,
11991CB_PERF_SEL_EXPORT_32_ABGR_QUAD_FRAGMENT = 0x000000a7,
11992CB_PERF_SEL_DUAL_SOURCE_COLOR_QUAD_FRAGMENT = 0x000000a8,
11993CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_BEFORE_UPDATE = 0x000000a9,
11994CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_BEFORE_UPDATE = 0x000000aa,
11995CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_BEFORE_UPDATE = 0x000000ab,
11996CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_BEFORE_UPDATE = 0x000000ac,
11997CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_BEFORE_UPDATE = 0x000000ad,
11998CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_BEFORE_UPDATE = 0x000000ae,
11999CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_BEFORE_UPDATE = 0x000000af,
12000CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_BEFORE_UPDATE = 0x000000b0,
12001CB_PERF_SEL_QUAD_HAS_1_FRAGMENT_AFTER_UPDATE = 0x000000b1,
12002CB_PERF_SEL_QUAD_HAS_2_FRAGMENTS_AFTER_UPDATE = 0x000000b2,
12003CB_PERF_SEL_QUAD_HAS_3_FRAGMENTS_AFTER_UPDATE = 0x000000b3,
12004CB_PERF_SEL_QUAD_HAS_4_FRAGMENTS_AFTER_UPDATE = 0x000000b4,
12005CB_PERF_SEL_QUAD_HAS_5_FRAGMENTS_AFTER_UPDATE = 0x000000b5,
12006CB_PERF_SEL_QUAD_HAS_6_FRAGMENTS_AFTER_UPDATE = 0x000000b6,
12007CB_PERF_SEL_QUAD_HAS_7_FRAGMENTS_AFTER_UPDATE = 0x000000b7,
12008CB_PERF_SEL_QUAD_HAS_8_FRAGMENTS_AFTER_UPDATE = 0x000000b8,
12009CB_PERF_SEL_QUAD_ADDED_1_FRAGMENT = 0x000000b9,
12010CB_PERF_SEL_QUAD_ADDED_2_FRAGMENTS = 0x000000ba,
12011CB_PERF_SEL_QUAD_ADDED_3_FRAGMENTS = 0x000000bb,
12012CB_PERF_SEL_QUAD_ADDED_4_FRAGMENTS = 0x000000bc,
12013CB_PERF_SEL_QUAD_ADDED_5_FRAGMENTS = 0x000000bd,
12014CB_PERF_SEL_QUAD_ADDED_6_FRAGMENTS = 0x000000be,
12015CB_PERF_SEL_QUAD_ADDED_7_FRAGMENTS = 0x000000bf,
12016CB_PERF_SEL_QUAD_REMOVED_1_FRAGMENT = 0x000000c0,
12017CB_PERF_SEL_QUAD_REMOVED_2_FRAGMENTS = 0x000000c1,
12018CB_PERF_SEL_QUAD_REMOVED_3_FRAGMENTS = 0x000000c2,
12019CB_PERF_SEL_QUAD_REMOVED_4_FRAGMENTS = 0x000000c3,
12020CB_PERF_SEL_QUAD_REMOVED_5_FRAGMENTS = 0x000000c4,
12021CB_PERF_SEL_QUAD_REMOVED_6_FRAGMENTS = 0x000000c5,
12022CB_PERF_SEL_QUAD_REMOVED_7_FRAGMENTS = 0x000000c6,
12023CB_PERF_SEL_QUAD_READS_FRAGMENT_0 = 0x000000c7,
12024CB_PERF_SEL_QUAD_READS_FRAGMENT_1 = 0x000000c8,
12025CB_PERF_SEL_QUAD_READS_FRAGMENT_2 = 0x000000c9,
12026CB_PERF_SEL_QUAD_READS_FRAGMENT_3 = 0x000000ca,
12027CB_PERF_SEL_QUAD_READS_FRAGMENT_4 = 0x000000cb,
12028CB_PERF_SEL_QUAD_READS_FRAGMENT_5 = 0x000000cc,
12029CB_PERF_SEL_QUAD_READS_FRAGMENT_6 = 0x000000cd,
12030CB_PERF_SEL_QUAD_READS_FRAGMENT_7 = 0x000000ce,
12031CB_PERF_SEL_QUAD_WRITES_FRAGMENT_0 = 0x000000cf,
12032CB_PERF_SEL_QUAD_WRITES_FRAGMENT_1 = 0x000000d0,
12033CB_PERF_SEL_QUAD_WRITES_FRAGMENT_2 = 0x000000d1,
12034CB_PERF_SEL_QUAD_WRITES_FRAGMENT_3 = 0x000000d2,
12035CB_PERF_SEL_QUAD_WRITES_FRAGMENT_4 = 0x000000d3,
12036CB_PERF_SEL_QUAD_WRITES_FRAGMENT_5 = 0x000000d4,
12037CB_PERF_SEL_QUAD_WRITES_FRAGMENT_6 = 0x000000d5,
12038CB_PERF_SEL_QUAD_WRITES_FRAGMENT_7 = 0x000000d6,
12039CB_PERF_SEL_QUAD_BLEND_OPT_DONT_READ_DST = 0x000000d7,
12040CB_PERF_SEL_QUAD_BLEND_OPT_BLEND_BYPASS = 0x000000d8,
12041CB_PERF_SEL_QUAD_BLEND_OPT_DISCARD_PIXELS = 0x000000d9,
12042CB_PERF_SEL_QUAD_DST_READ_COULD_HAVE_BEEN_OPTIMIZED = 0x000000da,
12043CB_PERF_SEL_QUAD_BLENDING_COULD_HAVE_BEEN_BYPASSED = 0x000000db,
12044CB_PERF_SEL_QUAD_COULD_HAVE_BEEN_DISCARDED = 0x000000dc,
12045CB_PERF_SEL_BLEND_OPT_PIXELS_RESULT_EQ_DEST = 0x000000dd,
12046CB_PERF_SEL_DRAWN_BUSY = 0x000000de,
12047CB_PERF_SEL_TILE_TO_CMR_REGION_BUSY = 0x000000df,
12048CB_PERF_SEL_CMR_TO_FCR_REGION_BUSY = 0x000000e0,
12049CB_PERF_SEL_FCR_TO_CCR_REGION_BUSY = 0x000000e1,
12050CB_PERF_SEL_CCR_TO_CCW_REGION_BUSY = 0x000000e2,
12051CB_PERF_SEL_FC_PF_SLOW_MODE_QUAD_EMPTY_HALF_DROPPED = 0x000000e3,
12052CB_PERF_SEL_FC_SEQUENCER_CLEAR = 0x000000e4,
12053CB_PERF_SEL_FC_SEQUENCER_ELIMINATE_FAST_CLEAR = 0x000000e5,
12054CB_PERF_SEL_FC_SEQUENCER_FMASK_DECOMPRESS = 0x000000e6,
12055CB_PERF_SEL_FC_SEQUENCER_FMASK_COMPRESSION_DISABLE = 0x000000e7,
12056CB_PERF_SEL_CC_CACHE_READS_SAVED_DUE_TO_DCC = 0x000000e8,
12057CB_PERF_SEL_FC_KEYID_RDLAT_FIFO_FULL = 0x000000e9,
12058CB_PERF_SEL_FC_DOC_IS_STALLED = 0x000000ea,
12059CB_PERF_SEL_FC_DOC_MRTS_NOT_COMBINED = 0x000000eb,
12060CB_PERF_SEL_FC_DOC_MRTS_COMBINED = 0x000000ec,
12061CB_PERF_SEL_FC_DOC_QTILE_CAM_MISS = 0x000000ed,
12062CB_PERF_SEL_FC_DOC_QTILE_CAM_HIT = 0x000000ee,
12063CB_PERF_SEL_FC_DOC_CLINE_CAM_MISS = 0x000000ef,
12064CB_PERF_SEL_FC_DOC_CLINE_CAM_HIT = 0x000000f0,
12065CB_PERF_SEL_FC_DOC_QUAD_PTR_FIFO_IS_FULL = 0x000000f1,
12066CB_PERF_SEL_FC_DOC_OVERWROTE_1_SECTOR = 0x000000f2,
12067CB_PERF_SEL_FC_DOC_OVERWROTE_2_SECTORS = 0x000000f3,
12068CB_PERF_SEL_FC_DOC_OVERWROTE_3_SECTORS = 0x000000f4,
12069CB_PERF_SEL_FC_DOC_OVERWROTE_4_SECTORS = 0x000000f5,
12070CB_PERF_SEL_FC_DOC_TOTAL_OVERWRITTEN_SECTORS = 0x000000f6,
12071CB_PERF_SEL_FC_DCC_CACHE_HIT = 0x000000f7,
12072CB_PERF_SEL_FC_DCC_CACHE_TAG_MISS = 0x000000f8,
12073CB_PERF_SEL_FC_DCC_CACHE_SECTOR_MISS = 0x000000f9,
12074CB_PERF_SEL_FC_DCC_CACHE_REEVICTION_STALL = 0x000000fa,
12075CB_PERF_SEL_FC_DCC_CACHE_EVICT_NONZERO_INFLIGHT_STALL = 0x000000fb,
12076CB_PERF_SEL_FC_DCC_CACHE_REPLACE_PENDING_EVICT_STALL = 0x000000fc,
12077CB_PERF_SEL_FC_DCC_CACHE_INFLIGHT_COUNTER_MAXIMUM_STALL = 0x000000fd,
12078CB_PERF_SEL_FC_DCC_CACHE_READ_OUTPUT_STALL = 0x000000fe,
12079CB_PERF_SEL_FC_DCC_CACHE_WRITE_OUTPUT_STALL = 0x000000ff,
12080CB_PERF_SEL_FC_DCC_CACHE_ACK_OUTPUT_STALL = 0x00000100,
12081CB_PERF_SEL_FC_DCC_CACHE_STALL = 0x00000101,
12082CB_PERF_SEL_FC_DCC_CACHE_FLUSH = 0x00000102,
12083CB_PERF_SEL_FC_DCC_CACHE_TAGS_FLUSHED = 0x00000103,
12084CB_PERF_SEL_FC_DCC_CACHE_SECTORS_FLUSHED = 0x00000104,
12085CB_PERF_SEL_FC_DCC_CACHE_DIRTY_SECTORS_FLUSHED = 0x00000105,
12086CB_PERF_SEL_CC_DCC_BEYOND_TILE_SPLIT = 0x00000106,
12087CB_PERF_SEL_FC_MC_DCC_WRITE_REQUEST = 0x00000107,
12088CB_PERF_SEL_FC_MC_DCC_WRITE_REQUESTS_IN_FLIGHT = 0x00000108,
12089CB_PERF_SEL_FC_MC_DCC_READ_REQUEST = 0x00000109,
12090CB_PERF_SEL_FC_MC_DCC_READ_REQUESTS_IN_FLIGHT = 0x0000010a,
12091CB_PERF_SEL_CC_DCC_RDREQ_STALL = 0x0000010b,
12092CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_IN = 0x0000010c,
12093CB_PERF_SEL_CC_DCC_DECOMPRESS_TIDS_OUT = 0x0000010d,
12094CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_IN = 0x0000010e,
12095CB_PERF_SEL_CC_DCC_COMPRESS_TIDS_OUT = 0x0000010f,
12096CB_PERF_SEL_FC_DCC_KEY_VALUE__CLEAR = 0x00000110,
12097CB_PERF_SEL_CC_DCC_KEY_VALUE__4_BLOCKS__2TO1 = 0x00000111,
12098CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO1__1BLOCK_2TO2 = 0x00000112,
12099CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000113,
12100CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__2BLOCKS_2TO1 = 0x00000114,
12101CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__3BLOCKS_2TO1 = 0x00000115,
12102CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__2BLOCKS_2TO2 = 0x00000116,
12103CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__2BLOCKS_2TO2__1BLOCK_2TO1 = 0x00000117,
12104CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000118,
12105CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000119,
12106CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__2BLOCKS_2TO1 = 0x0000011a,
12107CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__2BLOCKS_2TO1__1BLOCK_2TO2 = 0x0000011b,
12108CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__3BLOCKS_2TO2 = 0x0000011c,
12109CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__2BLOCKS_2TO2 = 0x0000011d,
12110CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x0000011e,
12111CB_PERF_SEL_CC_DCC_KEY_VALUE__3BLOCKS_2TO2__1BLOCK_2TO1 = 0x0000011f,
12112CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO1 = 0x00000120,
12113CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO2 = 0x00000121,
12114CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO3 = 0x00000122,
12115CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_4TO4 = 0x00000123,
12116CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO1 = 0x00000124,
12117CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO2 = 0x00000125,
12118CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO3 = 0x00000126,
12119CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_4TO4 = 0x00000127,
12120CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO1 = 0x00000128,
12121CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO2 = 0x00000129,
12122CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_4TO3 = 0x0000012a,
12123CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_4TO4 = 0x0000012b,
12124CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO1 = 0x0000012c,
12125CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO2 = 0x0000012d,
12126CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_4TO3 = 0x0000012e,
12127CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO1 = 0x0000012f,
12128CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO2 = 0x00000130,
12129CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO3 = 0x00000131,
12130CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO1__1BLOCK_4TO4 = 0x00000132,
12131CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO1 = 0x00000133,
12132CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO2 = 0x00000134,
12133CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO3 = 0x00000135,
12134CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_2TO2__1BLOCK_4TO4 = 0x00000136,
12135CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO1 = 0x00000137,
12136CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO2 = 0x00000138,
12137CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO3 = 0x00000139,
12138CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_2TO1__1BLOCK_4TO4 = 0x0000013a,
12139CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO1 = 0x0000013b,
12140CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO2 = 0x0000013c,
12141CB_PERF_SEL_CC_DCC_KEY_VALUE__2BLOCKS_2TO2__1BLOCK_4TO3 = 0x0000013d,
12142CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO1 = 0x0000013e,
12143CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO1 = 0x0000013f,
12144CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO1 = 0x00000140,
12145CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO1 = 0x00000141,
12146CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO1 = 0x00000142,
12147CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO1 = 0x00000143,
12148CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO1 = 0x00000144,
12149CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO4__1BLOCK_2TO1 = 0x00000145,
12150CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO1__1BLOCK_2TO2 = 0x00000146,
12151CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO2__1BLOCK_2TO2 = 0x00000147,
12152CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO3__1BLOCK_2TO2 = 0x00000148,
12153CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_4TO4__1BLOCK_2TO2 = 0x00000149,
12154CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO1__1BLOCK_2TO2 = 0x0000014a,
12155CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO2__1BLOCK_2TO2 = 0x0000014b,
12156CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_4TO3__1BLOCK_2TO2 = 0x0000014c,
12157CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO1 = 0x0000014d,
12158CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO1 = 0x0000014e,
12159CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO1 = 0x0000014f,
12160CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__2BLOCKS_2TO1 = 0x00000150,
12161CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__2BLOCKS_2TO2 = 0x00000151,
12162CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__2BLOCKS_2TO2 = 0x00000152,
12163CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__2BLOCKS_2TO2 = 0x00000153,
12164CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000154,
12165CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000155,
12166CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000156,
12167CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO1__1BLOCK_2TO2 = 0x00000157,
12168CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO1__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000158,
12169CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO2__1BLOCK_2TO2__1BLOCK_2TO1 = 0x00000159,
12170CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO3__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000015a,
12171CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_4TO4__1BLOCK_2TO2__1BLOCK_2TO1 = 0x0000015b,
12172CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO1 = 0x0000015c,
12173CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO2 = 0x0000015d,
12174CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO3 = 0x0000015e,
12175CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO4 = 0x0000015f,
12176CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO5 = 0x00000160,
12177CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__1BLOCK_6TO6 = 0x00000161,
12178CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV0 = 0x00000162,
12179CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO1__INV1 = 0x00000163,
12180CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO1 = 0x00000164,
12181CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO2 = 0x00000165,
12182CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO3 = 0x00000166,
12183CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO4 = 0x00000167,
12184CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__1BLOCK_6TO5 = 0x00000168,
12185CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV0 = 0x00000169,
12186CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_2TO2__INV1 = 0x0000016a,
12187CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO1 = 0x0000016b,
12188CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO1 = 0x0000016c,
12189CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO1 = 0x0000016d,
12190CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO1 = 0x0000016e,
12191CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO1 = 0x0000016f,
12192CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO6__1BLOCK_2TO1 = 0x00000170,
12193CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO1 = 0x00000171,
12194CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO1 = 0x00000172,
12195CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO1__1BLOCK_2TO2 = 0x00000173,
12196CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO2__1BLOCK_2TO2 = 0x00000174,
12197CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO3__1BLOCK_2TO2 = 0x00000175,
12198CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO4__1BLOCK_2TO2 = 0x00000176,
12199CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_6TO5__1BLOCK_2TO2 = 0x00000177,
12200CB_PERF_SEL_CC_DCC_KEY_VALUE__INV0__1BLOCK_2TO2 = 0x00000178,
12201CB_PERF_SEL_CC_DCC_KEY_VALUE__INV1__1BLOCK_2TO2 = 0x00000179,
12202CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO1 = 0x0000017a,
12203CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO2 = 0x0000017b,
12204CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO3 = 0x0000017c,
12205CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO4 = 0x0000017d,
12206CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO5 = 0x0000017e,
12207CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO6 = 0x0000017f,
12208CB_PERF_SEL_CC_DCC_KEY_VALUE__1BLOCK_8TO7 = 0x00000180,
12209CB_PERF_SEL_CC_DCC_KEY_VALUE__UNCOMPRESSED = 0x00000181,
12210CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_2TO1 = 0x00000182,
12211CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO1 = 0x00000183,
12212CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO2 = 0x00000184,
12213CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_4TO3 = 0x00000185,
12214CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO1 = 0x00000186,
12215CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO2 = 0x00000187,
12216CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO3 = 0x00000188,
12217CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO4 = 0x00000189,
12218CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_6TO5 = 0x0000018a,
12219CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO1 = 0x0000018b,
12220CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO2 = 0x0000018c,
12221CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO3 = 0x0000018d,
12222CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO4 = 0x0000018e,
12223CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO5 = 0x0000018f,
12224CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO6 = 0x00000190,
12225CB_PERF_SEL_CC_DCC_COMPRESS_RATIO_8TO7 = 0x00000191,
12226CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_BOTH = 0x00000192,
12227CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_LEFT = 0x00000193,
12228CB_PERF_SEL_RBP_EXPORT_8PIX_LIT_RIGHT = 0x00000194,
12229CB_PERF_SEL_RBP_SPLIT_MICROTILE = 0x00000195,
12230CB_PERF_SEL_RBP_SPLIT_AA_SAMPLE_MASK = 0x00000196,
12231CB_PERF_SEL_RBP_SPLIT_PARTIAL_TARGET_MASK = 0x00000197,
12232CB_PERF_SEL_RBP_SPLIT_LINEAR_ADDRESSING = 0x00000198,
12233CB_PERF_SEL_RBP_SPLIT_AA_NO_FMASK_COMPRESS = 0x00000199,
12234CB_PERF_SEL_RBP_INSERT_MISSING_LAST_QUAD = 0x0000019a,
12235CB_PERF_SEL_NACK_CM_READ = 0x0000019b,
12236CB_PERF_SEL_NACK_CM_WRITE = 0x0000019c,
12237CB_PERF_SEL_NACK_FC_READ = 0x0000019d,
12238CB_PERF_SEL_NACK_FC_WRITE = 0x0000019e,
12239CB_PERF_SEL_NACK_DC_READ = 0x0000019f,
12240CB_PERF_SEL_NACK_DC_WRITE = 0x000001a0,
12241CB_PERF_SEL_NACK_CC_READ = 0x000001a1,
12242CB_PERF_SEL_NACK_CC_WRITE = 0x000001a2,
12243CB_PERF_SEL_CM_MC_EARLY_WRITE_RETURN = 0x000001a3,
12244CB_PERF_SEL_FC_MC_EARLY_WRITE_RETURN = 0x000001a4,
12245CB_PERF_SEL_DC_MC_EARLY_WRITE_RETURN = 0x000001a5,
12246CB_PERF_SEL_CC_MC_EARLY_WRITE_RETURN = 0x000001a6,
12247CB_PERF_SEL_CM_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a7,
12248CB_PERF_SEL_FC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a8,
12249CB_PERF_SEL_DC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001a9,
12250CB_PERF_SEL_CC_MC_EARLY_WRITE_REQUESTS_IN_FLIGHT = 0x000001aa,
12251CB_PERF_SEL_CM_MC_WRITE_ACK64B = 0x000001ab,
12252CB_PERF_SEL_FC_MC_WRITE_ACK64B = 0x000001ac,
12253CB_PERF_SEL_DC_MC_WRITE_ACK64B = 0x000001ad,
12254CB_PERF_SEL_CC_MC_WRITE_ACK64B = 0x000001ae,
12255CB_PERF_SEL_EVENT_BOTTOM_OF_PIPE_TS = 0x000001af,
12256CB_PERF_SEL_EVENT_FLUSH_AND_INV_DB_DATA_TS = 0x000001b0,
12257CB_PERF_SEL_EVENT_FLUSH_AND_INV_CB_PIXEL_DATA = 0x000001b1,
12258CB_PERF_SEL_DB_CB_TILE_TILENOTEVENT = 0x000001b2,
12259CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_32BPP_8PIX = 0x000001b3,
12260CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_UNSIGNED_8PIX = 0x000001b4,
12261CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_SIGNED_8PIX = 0x000001b5,
12262CB_PERF_SEL_LQUAD_FORMAT_IS_EXPORT_16_16_FLOAT_8PIX = 0x000001b6,
12263CB_PERF_SEL_MERGE_PIXELS_WITH_BLEND_ENABLED = 0x000001b7,
12264CB_PERF_SEL_DB_CB_CONTEXT_DONE = 0x000001b8,
12265CB_PERF_SEL_DB_CB_EOP_DONE = 0x000001b9,
12266CB_PERF_SEL_CC_MC_WRITE_REQUEST_PARTIAL = 0x000001ba,
12267CB_PERF_SEL_CC_BB_BLEND_PIXEL_VLD = 0x000001bb,
12268} CBPerfSel;
12269
12270/*
12271 * CmaskAddr enum
12272 */
12273
12274typedef enum CmaskAddr {
12275CMASK_ADDR_TILED = 0x00000000,
12276CMASK_ADDR_LINEAR = 0x00000001,
12277CMASK_ADDR_COMPATIBLE = 0x00000002,
12278} CmaskAddr;
12279
12280/*
12281 * SourceFormat enum
12282 */
12283
12284typedef enum SourceFormat {
12285EXPORT_4C_32BPC = 0x00000000,
12286EXPORT_4C_16BPC = 0x00000001,
12287EXPORT_2C_32BPC_GR = 0x00000002,
12288EXPORT_2C_32BPC_AR = 0x00000003,
12289} SourceFormat;
12290
12291/*******************************************************
12292 * TC Enums
12293 *******************************************************/
12294
12295/*
12296 * TC_OP_MASKS enum
12297 */
12298
12299typedef enum TC_OP_MASKS {
12300TC_OP_MASK_FLUSH_DENROM = 0x00000008,
12301TC_OP_MASK_64 = 0x00000020,
12302TC_OP_MASK_NO_RTN = 0x00000040,
12303} TC_OP_MASKS;
12304
12305/*
12306 * TC_OP enum
12307 */
12308
12309typedef enum TC_OP {
12310TC_OP_READ = 0x00000000,
12311TC_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
12312TC_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
12313TC_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
12314TC_OP_RESERVED_FOP_RTN_32_0 = 0x00000004,
12315TC_OP_RESERVED_FOP_RTN_32_1 = 0x00000005,
12316TC_OP_RESERVED_FOP_RTN_32_2 = 0x00000006,
12317TC_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
12318TC_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
12319TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
12320TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
12321TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
12322TC_OP_PROBE_FILTER = 0x0000000c,
12323TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
12324TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
12325TC_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
12326TC_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
12327TC_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
12328TC_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
12329TC_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
12330TC_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
12331TC_OP_ATOMIC_AND_RTN_32 = 0x00000015,
12332TC_OP_ATOMIC_OR_RTN_32 = 0x00000016,
12333TC_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
12334TC_OP_ATOMIC_INC_RTN_32 = 0x00000018,
12335TC_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
12336TC_OP_WBINVL1_VOL = 0x0000001a,
12337TC_OP_WBINVL1_SD = 0x0000001b,
12338TC_OP_RESERVED_NON_FLOAT_RTN_32_0 = 0x0000001c,
12339TC_OP_RESERVED_NON_FLOAT_RTN_32_1 = 0x0000001d,
12340TC_OP_RESERVED_NON_FLOAT_RTN_32_2 = 0x0000001e,
12341TC_OP_RESERVED_NON_FLOAT_RTN_32_3 = 0x0000001f,
12342TC_OP_WRITE = 0x00000020,
12343TC_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
12344TC_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
12345TC_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
12346TC_OP_RESERVED_FOP_RTN_64_0 = 0x00000024,
12347TC_OP_RESERVED_FOP_RTN_64_1 = 0x00000025,
12348TC_OP_RESERVED_FOP_RTN_64_2 = 0x00000026,
12349TC_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
12350TC_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
12351TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
12352TC_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
12353TC_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
12354TC_OP_WBINVL2_SD = 0x0000002c,
12355TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_0 = 0x0000002d,
12356TC_OP_RESERVED_FOP_FLUSH_DENORM_RTN_64_1 = 0x0000002e,
12357TC_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
12358TC_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
12359TC_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
12360TC_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
12361TC_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
12362TC_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
12363TC_OP_ATOMIC_AND_RTN_64 = 0x00000035,
12364TC_OP_ATOMIC_OR_RTN_64 = 0x00000036,
12365TC_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
12366TC_OP_ATOMIC_INC_RTN_64 = 0x00000038,
12367TC_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
12368TC_OP_WBL2_NC = 0x0000003a,
12369TC_OP_WBL2_WC = 0x0000003b,
12370TC_OP_RESERVED_NON_FLOAT_RTN_64_1 = 0x0000003c,
12371TC_OP_RESERVED_NON_FLOAT_RTN_64_2 = 0x0000003d,
12372TC_OP_RESERVED_NON_FLOAT_RTN_64_3 = 0x0000003e,
12373TC_OP_RESERVED_NON_FLOAT_RTN_64_4 = 0x0000003f,
12374TC_OP_WBINVL1 = 0x00000040,
12375TC_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
12376TC_OP_ATOMIC_FMIN_32 = 0x00000042,
12377TC_OP_ATOMIC_FMAX_32 = 0x00000043,
12378TC_OP_RESERVED_FOP_32_0 = 0x00000044,
12379TC_OP_RESERVED_FOP_32_1 = 0x00000045,
12380TC_OP_RESERVED_FOP_32_2 = 0x00000046,
12381TC_OP_ATOMIC_SWAP_32 = 0x00000047,
12382TC_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
12383TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
12384TC_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
12385TC_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
12386TC_OP_INV_METADATA = 0x0000004c,
12387TC_OP_RESERVED_FOP_FLUSH_DENORM_32_1 = 0x0000004d,
12388TC_OP_RESERVED_FOP_FLUSH_DENORM_32_2 = 0x0000004e,
12389TC_OP_ATOMIC_ADD_32 = 0x0000004f,
12390TC_OP_ATOMIC_SUB_32 = 0x00000050,
12391TC_OP_ATOMIC_SMIN_32 = 0x00000051,
12392TC_OP_ATOMIC_UMIN_32 = 0x00000052,
12393TC_OP_ATOMIC_SMAX_32 = 0x00000053,
12394TC_OP_ATOMIC_UMAX_32 = 0x00000054,
12395TC_OP_ATOMIC_AND_32 = 0x00000055,
12396TC_OP_ATOMIC_OR_32 = 0x00000056,
12397TC_OP_ATOMIC_XOR_32 = 0x00000057,
12398TC_OP_ATOMIC_INC_32 = 0x00000058,
12399TC_OP_ATOMIC_DEC_32 = 0x00000059,
12400TC_OP_INVL2_NC = 0x0000005a,
12401TC_OP_NOP_RTN0 = 0x0000005b,
12402TC_OP_RESERVED_NON_FLOAT_32_1 = 0x0000005c,
12403TC_OP_RESERVED_NON_FLOAT_32_2 = 0x0000005d,
12404TC_OP_RESERVED_NON_FLOAT_32_3 = 0x0000005e,
12405TC_OP_RESERVED_NON_FLOAT_32_4 = 0x0000005f,
12406TC_OP_WBINVL2 = 0x00000060,
12407TC_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
12408TC_OP_ATOMIC_FMIN_64 = 0x00000062,
12409TC_OP_ATOMIC_FMAX_64 = 0x00000063,
12410TC_OP_RESERVED_FOP_64_0 = 0x00000064,
12411TC_OP_RESERVED_FOP_64_1 = 0x00000065,
12412TC_OP_RESERVED_FOP_64_2 = 0x00000066,
12413TC_OP_ATOMIC_SWAP_64 = 0x00000067,
12414TC_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
12415TC_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
12416TC_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
12417TC_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
12418TC_OP_RESERVED_FOP_FLUSH_DENORM_64_0 = 0x0000006c,
12419TC_OP_RESERVED_FOP_FLUSH_DENORM_64_1 = 0x0000006d,
12420TC_OP_RESERVED_FOP_FLUSH_DENORM_64_2 = 0x0000006e,
12421TC_OP_ATOMIC_ADD_64 = 0x0000006f,
12422TC_OP_ATOMIC_SUB_64 = 0x00000070,
12423TC_OP_ATOMIC_SMIN_64 = 0x00000071,
12424TC_OP_ATOMIC_UMIN_64 = 0x00000072,
12425TC_OP_ATOMIC_SMAX_64 = 0x00000073,
12426TC_OP_ATOMIC_UMAX_64 = 0x00000074,
12427TC_OP_ATOMIC_AND_64 = 0x00000075,
12428TC_OP_ATOMIC_OR_64 = 0x00000076,
12429TC_OP_ATOMIC_XOR_64 = 0x00000077,
12430TC_OP_ATOMIC_INC_64 = 0x00000078,
12431TC_OP_ATOMIC_DEC_64 = 0x00000079,
12432TC_OP_WBINVL2_NC = 0x0000007a,
12433TC_OP_NOP_ACK = 0x0000007b,
12434TC_OP_RESERVED_NON_FLOAT_64_1 = 0x0000007c,
12435TC_OP_RESERVED_NON_FLOAT_64_2 = 0x0000007d,
12436TC_OP_RESERVED_NON_FLOAT_64_3 = 0x0000007e,
12437TC_OP_RESERVED_NON_FLOAT_64_4 = 0x0000007f,
12438} TC_OP;
12439
12440/*
12441 * TC_NACKS enum
12442 */
12443
12444typedef enum TC_NACKS {
12445TC_NACK_NO_FAULT = 0x00000000,
12446TC_NACK_PAGE_FAULT = 0x00000001,
12447TC_NACK_PROTECTION_FAULT = 0x00000002,
12448TC_NACK_DATA_ERROR = 0x00000003,
12449} TC_NACKS;
12450
12451/*
12452 * TC_EA_CID enum
12453 */
12454
12455typedef enum TC_EA_CID {
12456TC_EA_CID_RT = 0x00000000,
12457TC_EA_CID_FMASK = 0x00000001,
12458TC_EA_CID_DCC = 0x00000002,
12459TC_EA_CID_TCPMETA = 0x00000003,
12460TC_EA_CID_Z = 0x00000004,
12461TC_EA_CID_STENCIL = 0x00000005,
12462TC_EA_CID_HTILE = 0x00000006,
12463TC_EA_CID_MISC = 0x00000007,
12464TC_EA_CID_TCP = 0x00000008,
12465TC_EA_CID_SQC = 0x00000009,
12466TC_EA_CID_CPF = 0x0000000a,
12467TC_EA_CID_CPG = 0x0000000b,
12468TC_EA_CID_IA = 0x0000000c,
12469TC_EA_CID_WD = 0x0000000d,
12470TC_EA_CID_PA = 0x0000000e,
12471TC_EA_CID_UTCL2_TPI = 0x0000000f,
12472} TC_EA_CID;
12473
12474/*******************************************************
12475 * GL2 Enums
12476 *******************************************************/
12477
12478/*
12479 * GL2_OP_MASKS enum
12480 */
12481
12482typedef enum GL2_OP_MASKS {
12483GL2_OP_MASK_FLUSH_DENROM = 0x00000008,
12484GL2_OP_MASK_64 = 0x00000020,
12485GL2_OP_MASK_NO_RTN = 0x00000040,
12486} GL2_OP_MASKS;
12487
12488/*
12489 * GL2_OP enum
12490 */
12491
12492typedef enum GL2_OP {
12493GL2_OP_READ = 0x00000000,
12494GL2_OP_ATOMIC_FCMPSWAP_RTN_32 = 0x00000001,
12495GL2_OP_ATOMIC_FMIN_RTN_32 = 0x00000002,
12496GL2_OP_ATOMIC_FMAX_RTN_32 = 0x00000003,
12497GL2_OP_ATOMIC_SWAP_RTN_32 = 0x00000007,
12498GL2_OP_ATOMIC_CMPSWAP_RTN_32 = 0x00000008,
12499GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_32 = 0x00000009,
12500GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_32 = 0x0000000a,
12501GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_32 = 0x0000000b,
12502GL2_OP_PROBE_FILTER = 0x0000000c,
12503GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_1 = 0x0000000d,
12504GL2_OP_RESERVED_FOP_FLUSH_DENORM_RTN_32_2 = 0x0000000e,
12505GL2_OP_ATOMIC_ADD_RTN_32 = 0x0000000f,
12506GL2_OP_ATOMIC_SUB_RTN_32 = 0x00000010,
12507GL2_OP_ATOMIC_SMIN_RTN_32 = 0x00000011,
12508GL2_OP_ATOMIC_UMIN_RTN_32 = 0x00000012,
12509GL2_OP_ATOMIC_SMAX_RTN_32 = 0x00000013,
12510GL2_OP_ATOMIC_UMAX_RTN_32 = 0x00000014,
12511GL2_OP_ATOMIC_AND_RTN_32 = 0x00000015,
12512GL2_OP_ATOMIC_OR_RTN_32 = 0x00000016,
12513GL2_OP_ATOMIC_XOR_RTN_32 = 0x00000017,
12514GL2_OP_ATOMIC_INC_RTN_32 = 0x00000018,
12515GL2_OP_ATOMIC_DEC_RTN_32 = 0x00000019,
12516GL2_OP_WRITE = 0x00000020,
12517GL2_OP_ATOMIC_FCMPSWAP_RTN_64 = 0x00000021,
12518GL2_OP_ATOMIC_FMIN_RTN_64 = 0x00000022,
12519GL2_OP_ATOMIC_FMAX_RTN_64 = 0x00000023,
12520GL2_OP_ATOMIC_SWAP_RTN_64 = 0x00000027,
12521GL2_OP_ATOMIC_CMPSWAP_RTN_64 = 0x00000028,
12522GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_RTN_64 = 0x00000029,
12523GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_RTN_64 = 0x0000002a,
12524GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_RTN_64 = 0x0000002b,
12525GL2_OP_ATOMIC_ADD_RTN_64 = 0x0000002f,
12526GL2_OP_ATOMIC_SUB_RTN_64 = 0x00000030,
12527GL2_OP_ATOMIC_SMIN_RTN_64 = 0x00000031,
12528GL2_OP_ATOMIC_UMIN_RTN_64 = 0x00000032,
12529GL2_OP_ATOMIC_SMAX_RTN_64 = 0x00000033,
12530GL2_OP_ATOMIC_UMAX_RTN_64 = 0x00000034,
12531GL2_OP_ATOMIC_AND_RTN_64 = 0x00000035,
12532GL2_OP_ATOMIC_OR_RTN_64 = 0x00000036,
12533GL2_OP_ATOMIC_XOR_RTN_64 = 0x00000037,
12534GL2_OP_ATOMIC_INC_RTN_64 = 0x00000038,
12535GL2_OP_ATOMIC_DEC_RTN_64 = 0x00000039,
12536GL2_OP_GL1_INV = 0x00000040,
12537GL2_OP_ATOMIC_FCMPSWAP_32 = 0x00000041,
12538GL2_OP_ATOMIC_FMIN_32 = 0x00000042,
12539GL2_OP_ATOMIC_FMAX_32 = 0x00000043,
12540GL2_OP_ATOMIC_SWAP_32 = 0x00000047,
12541GL2_OP_ATOMIC_CMPSWAP_32 = 0x00000048,
12542GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_32 = 0x00000049,
12543GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_32 = 0x0000004a,
12544GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_32 = 0x0000004b,
12545GL2_OP_ATOMIC_ADD_32 = 0x0000004f,
12546GL2_OP_ATOMIC_SUB_32 = 0x00000050,
12547GL2_OP_ATOMIC_SMIN_32 = 0x00000051,
12548GL2_OP_ATOMIC_UMIN_32 = 0x00000052,
12549GL2_OP_ATOMIC_SMAX_32 = 0x00000053,
12550GL2_OP_ATOMIC_UMAX_32 = 0x00000054,
12551GL2_OP_ATOMIC_AND_32 = 0x00000055,
12552GL2_OP_ATOMIC_OR_32 = 0x00000056,
12553GL2_OP_ATOMIC_XOR_32 = 0x00000057,
12554GL2_OP_ATOMIC_INC_32 = 0x00000058,
12555GL2_OP_ATOMIC_DEC_32 = 0x00000059,
12556GL2_OP_NOP_RTN0 = 0x0000005b,
12557GL2_OP_ATOMIC_FCMPSWAP_64 = 0x00000061,
12558GL2_OP_ATOMIC_FMIN_64 = 0x00000062,
12559GL2_OP_ATOMIC_FMAX_64 = 0x00000063,
12560GL2_OP_ATOMIC_SWAP_64 = 0x00000067,
12561GL2_OP_ATOMIC_CMPSWAP_64 = 0x00000068,
12562GL2_OP_ATOMIC_FCMPSWAP_FLUSH_DENORM_64 = 0x00000069,
12563GL2_OP_ATOMIC_FMIN_FLUSH_DENORM_64 = 0x0000006a,
12564GL2_OP_ATOMIC_FMAX_FLUSH_DENORM_64 = 0x0000006b,
12565GL2_OP_ATOMIC_ADD_64 = 0x0000006f,
12566GL2_OP_ATOMIC_SUB_64 = 0x00000070,
12567GL2_OP_ATOMIC_SMIN_64 = 0x00000071,
12568GL2_OP_ATOMIC_UMIN_64 = 0x00000072,
12569GL2_OP_ATOMIC_SMAX_64 = 0x00000073,
12570GL2_OP_ATOMIC_UMAX_64 = 0x00000074,
12571GL2_OP_ATOMIC_AND_64 = 0x00000075,
12572GL2_OP_ATOMIC_OR_64 = 0x00000076,
12573GL2_OP_ATOMIC_XOR_64 = 0x00000077,
12574GL2_OP_ATOMIC_INC_64 = 0x00000078,
12575GL2_OP_ATOMIC_DEC_64 = 0x00000079,
12576GL2_OP_NOP_ACK = 0x0000007b,
12577} GL2_OP;
12578
12579/*
12580 * GL2_NACKS enum
12581 */
12582
12583typedef enum GL2_NACKS {
12584GL2_NACK_NO_FAULT = 0x00000000,
12585GL2_NACK_PAGE_FAULT = 0x00000001,
12586GL2_NACK_PROTECTION_FAULT = 0x00000002,
12587GL2_NACK_DATA_ERROR = 0x00000003,
12588} GL2_NACKS;
12589
12590/*
12591 * GL2_EA_CID enum
12592 */
12593
12594typedef enum GL2_EA_CID {
12595GL2_EA_CID_CLIENT = 0x00000000,
12596GL2_EA_CID_SDMA = 0x00000001,
12597GL2_EA_CID_RLC = 0x00000002,
12598GL2_EA_CID_CP = 0x00000004,
12599GL2_EA_CID_CPDMA = 0x00000005,
12600GL2_EA_CID_UTCL2 = 0x00000006,
12601GL2_EA_CID_RT = 0x00000007,
12602GL2_EA_CID_FMASK = 0x00000008,
12603GL2_EA_CID_DCC = 0x00000009,
12604GL2_EA_CID_Z_STENCIL = 0x0000000a,
12605GL2_EA_CID_ZPCPSD = 0x0000000b,
12606GL2_EA_CID_HTILE = 0x0000000c,
12607GL2_EA_CID_TCPMETA = 0x0000000f,
12608} GL2_EA_CID;
12609
12610/*******************************************************
12611 * SPI Enums
12612 *******************************************************/
12613
12614/*
12615 * SPI_SAMPLE_CNTL enum
12616 */
12617
12618typedef enum SPI_SAMPLE_CNTL {
12619CENTROIDS_ONLY = 0x00000000,
12620CENTERS_ONLY = 0x00000001,
12621CENTROIDS_AND_CENTERS = 0x00000002,
12622UNDEF = 0x00000003,
12623} SPI_SAMPLE_CNTL;
12624
12625/*
12626 * SPI_FOG_MODE enum
12627 */
12628
12629typedef enum SPI_FOG_MODE {
12630SPI_FOG_NONE = 0x00000000,
12631SPI_FOG_EXP = 0x00000001,
12632SPI_FOG_EXP2 = 0x00000002,
12633SPI_FOG_LINEAR = 0x00000003,
12634} SPI_FOG_MODE;
12635
12636/*
12637 * SPI_PNT_SPRITE_OVERRIDE enum
12638 */
12639
12640typedef enum SPI_PNT_SPRITE_OVERRIDE {
12641SPI_PNT_SPRITE_SEL_0 = 0x00000000,
12642SPI_PNT_SPRITE_SEL_1 = 0x00000001,
12643SPI_PNT_SPRITE_SEL_S = 0x00000002,
12644SPI_PNT_SPRITE_SEL_T = 0x00000003,
12645SPI_PNT_SPRITE_SEL_NONE = 0x00000004,
12646} SPI_PNT_SPRITE_OVERRIDE;
12647
12648/*
12649 * SPI_PERFCNT_SEL enum
12650 */
12651
12652typedef enum SPI_PERFCNT_SEL {
12653SPI_PERF_VS_WINDOW_VALID = 0x00000000,
12654SPI_PERF_VS_BUSY = 0x00000001,
12655SPI_PERF_VS_FIRST_WAVE = 0x00000002,
12656SPI_PERF_VS_LAST_WAVE = 0x00000003,
12657SPI_PERF_VS_LSHS_DEALLOC = 0x00000004,
12658SPI_PERF_VS_PC_STALL = 0x00000005,
12659SPI_PERF_VS_POS0_STALL = 0x00000006,
12660SPI_PERF_VS_POS1_STALL = 0x00000007,
12661SPI_PERF_VS_CRAWLER_STALL = 0x00000008,
12662SPI_PERF_VS_EVENT_WAVE = 0x00000009,
12663SPI_PERF_VS_WAVE = 0x0000000a,
12664SPI_PERF_VS_PERS_UPD_FULL0 = 0x0000000b,
12665SPI_PERF_VS_PERS_UPD_FULL1 = 0x0000000c,
12666SPI_PERF_VS_LATE_ALLOC_FULL = 0x0000000d,
12667SPI_PERF_VS_FIRST_SUBGRP = 0x0000000e,
12668SPI_PERF_VS_LAST_SUBGRP = 0x0000000f,
12669SPI_PERF_VS_ALLOC_CNT = 0x00000010,
12670SPI_PERF_VS_PC_ALLOC_CNT = 0x00000011,
12671SPI_PERF_VS_LATE_ALLOC_ACCUM = 0x00000012,
12672SPI_PERF_GS_WINDOW_VALID = 0x00000013,
12673SPI_PERF_GS_BUSY = 0x00000014,
12674SPI_PERF_GS_CRAWLER_STALL = 0x00000015,
12675SPI_PERF_GS_EVENT_WAVE = 0x00000016,
12676SPI_PERF_GS_WAVE = 0x00000017,
12677SPI_PERF_GS_PERS_UPD_FULL0 = 0x00000018,
12678SPI_PERF_GS_PERS_UPD_FULL1 = 0x00000019,
12679SPI_PERF_GS_FIRST_SUBGRP = 0x0000001a,
12680SPI_PERF_GS_LAST_SUBGRP = 0x0000001b,
12681SPI_PERF_GS_HS_DEALLOC = 0x0000001c,
12682SPI_PERF_GS_NGG_SE_LATE_ALLOC_LIMIT = 0x0000001d,
12683SPI_PERF_GS_GRP_FIFO_FULL = 0x0000001e,
12684SPI_PERF_HS_WINDOW_VALID = 0x0000001f,
12685SPI_PERF_HS_BUSY = 0x00000020,
12686SPI_PERF_HS_CRAWLER_STALL = 0x00000021,
12687SPI_PERF_HS_FIRST_WAVE = 0x00000022,
12688SPI_PERF_HS_LAST_WAVE = 0x00000023,
12689SPI_PERF_HS_OFFCHIP_LDS_STALL = 0x00000024,
12690SPI_PERF_HS_EVENT_WAVE = 0x00000025,
12691SPI_PERF_HS_WAVE = 0x00000026,
12692SPI_PERF_HS_PERS_UPD_FULL0 = 0x00000027,
12693SPI_PERF_HS_PERS_UPD_FULL1 = 0x00000028,
12694SPI_PERF_CSG_WINDOW_VALID = 0x00000029,
12695SPI_PERF_CSG_BUSY = 0x0000002a,
12696SPI_PERF_CSG_NUM_THREADGROUPS = 0x0000002b,
12697SPI_PERF_CSG_CRAWLER_STALL = 0x0000002c,
12698SPI_PERF_CSG_EVENT_WAVE = 0x0000002d,
12699SPI_PERF_CSG_WAVE = 0x0000002e,
12700SPI_PERF_CSN_WINDOW_VALID = 0x0000002f,
12701SPI_PERF_CSN_BUSY = 0x00000030,
12702SPI_PERF_CSN_NUM_THREADGROUPS = 0x00000031,
12703SPI_PERF_CSN_CRAWLER_STALL = 0x00000032,
12704SPI_PERF_CSN_EVENT_WAVE = 0x00000033,
12705SPI_PERF_CSN_WAVE = 0x00000034,
12706SPI_PERF_PS0_WINDOW_VALID = 0x00000035,
12707SPI_PERF_PS1_WINDOW_VALID = 0x00000036,
12708SPI_PERF_PS2_WINDOW_VALID = 0x00000037,
12709SPI_PERF_PS3_WINDOW_VALID = 0x00000038,
12710SPI_PERF_PS0_BUSY = 0x00000039,
12711SPI_PERF_PS1_BUSY = 0x0000003a,
12712SPI_PERF_PS2_BUSY = 0x0000003b,
12713SPI_PERF_PS3_BUSY = 0x0000003c,
12714SPI_PERF_PS0_ACTIVE = 0x0000003d,
12715SPI_PERF_PS1_ACTIVE = 0x0000003e,
12716SPI_PERF_PS2_ACTIVE = 0x0000003f,
12717SPI_PERF_PS3_ACTIVE = 0x00000040,
12718SPI_PERF_PS0_DEALLOC_BIN0 = 0x00000041,
12719SPI_PERF_PS1_DEALLOC_BIN0 = 0x00000042,
12720SPI_PERF_PS2_DEALLOC_BIN0 = 0x00000043,
12721SPI_PERF_PS3_DEALLOC_BIN0 = 0x00000044,
12722SPI_PERF_PS0_FPOS_BIN1_STALL = 0x00000045,
12723SPI_PERF_PS1_FPOS_BIN1_STALL = 0x00000046,
12724SPI_PERF_PS2_FPOS_BIN1_STALL = 0x00000047,
12725SPI_PERF_PS3_FPOS_BIN1_STALL = 0x00000048,
12726SPI_PERF_PS0_EVENT_WAVE = 0x00000049,
12727SPI_PERF_PS1_EVENT_WAVE = 0x0000004a,
12728SPI_PERF_PS2_EVENT_WAVE = 0x0000004b,
12729SPI_PERF_PS3_EVENT_WAVE = 0x0000004c,
12730SPI_PERF_PS0_WAVE = 0x0000004d,
12731SPI_PERF_PS1_WAVE = 0x0000004e,
12732SPI_PERF_PS2_WAVE = 0x0000004f,
12733SPI_PERF_PS3_WAVE = 0x00000050,
12734SPI_PERF_PS0_OPT_WAVE = 0x00000051,
12735SPI_PERF_PS1_OPT_WAVE = 0x00000052,
12736SPI_PERF_PS2_OPT_WAVE = 0x00000053,
12737SPI_PERF_PS3_OPT_WAVE = 0x00000054,
12738SPI_PERF_PS0_PASS_BIN0 = 0x00000055,
12739SPI_PERF_PS1_PASS_BIN0 = 0x00000056,
12740SPI_PERF_PS2_PASS_BIN0 = 0x00000057,
12741SPI_PERF_PS3_PASS_BIN0 = 0x00000058,
12742SPI_PERF_PS0_PASS_BIN1 = 0x00000059,
12743SPI_PERF_PS1_PASS_BIN1 = 0x0000005a,
12744SPI_PERF_PS2_PASS_BIN1 = 0x0000005b,
12745SPI_PERF_PS3_PASS_BIN1 = 0x0000005c,
12746SPI_PERF_PS0_FPOS_BIN2 = 0x0000005d,
12747SPI_PERF_PS1_FPOS_BIN2 = 0x0000005e,
12748SPI_PERF_PS2_FPOS_BIN2 = 0x0000005f,
12749SPI_PERF_PS3_FPOS_BIN2 = 0x00000060,
12750SPI_PERF_PS0_PRIM_BIN0 = 0x00000061,
12751SPI_PERF_PS1_PRIM_BIN0 = 0x00000062,
12752SPI_PERF_PS2_PRIM_BIN0 = 0x00000063,
12753SPI_PERF_PS3_PRIM_BIN0 = 0x00000064,
12754SPI_PERF_PS0_PRIM_BIN1 = 0x00000065,
12755SPI_PERF_PS1_PRIM_BIN1 = 0x00000066,
12756SPI_PERF_PS2_PRIM_BIN1 = 0x00000067,
12757SPI_PERF_PS3_PRIM_BIN1 = 0x00000068,
12758SPI_PERF_PS0_CNF_BIN2 = 0x00000069,
12759SPI_PERF_PS1_CNF_BIN2 = 0x0000006a,
12760SPI_PERF_PS2_CNF_BIN2 = 0x0000006b,
12761SPI_PERF_PS3_CNF_BIN2 = 0x0000006c,
12762SPI_PERF_PS0_CNF_BIN3 = 0x0000006d,
12763SPI_PERF_PS1_CNF_BIN3 = 0x0000006e,
12764SPI_PERF_PS2_CNF_BIN3 = 0x0000006f,
12765SPI_PERF_PS3_CNF_BIN3 = 0x00000070,
12766SPI_PERF_PS0_CRAWLER_STALL = 0x00000071,
12767SPI_PERF_PS1_CRAWLER_STALL = 0x00000072,
12768SPI_PERF_PS2_CRAWLER_STALL = 0x00000073,
12769SPI_PERF_PS3_CRAWLER_STALL = 0x00000074,
12770SPI_PERF_PS0_LDS_RES_FULL = 0x00000075,
12771SPI_PERF_PS1_LDS_RES_FULL = 0x00000076,
12772SPI_PERF_PS2_LDS_RES_FULL = 0x00000077,
12773SPI_PERF_PS3_LDS_RES_FULL = 0x00000078,
12774SPI_PERF_PS_PERS_UPD_FULL0 = 0x00000079,
12775SPI_PERF_PS_PERS_UPD_FULL1 = 0x0000007a,
12776SPI_PERF_PS0_POPS_WAVE_SENT = 0x0000007b,
12777SPI_PERF_PS1_POPS_WAVE_SENT = 0x0000007c,
12778SPI_PERF_PS2_POPS_WAVE_SENT = 0x0000007d,
12779SPI_PERF_PS3_POPS_WAVE_SENT = 0x0000007e,
12780SPI_PERF_PS0_POPS_WAVE_EXIT = 0x0000007f,
12781SPI_PERF_PS1_POPS_WAVE_EXIT = 0x00000080,
12782SPI_PERF_PS2_POPS_WAVE_EXIT = 0x00000081,
12783SPI_PERF_PS3_POPS_WAVE_EXIT = 0x00000082,
12784SPI_PERF_LDS0_PC_VALID = 0x00000083,
12785SPI_PERF_LDS1_PC_VALID = 0x00000084,
12786SPI_PERF_RA_PIPE_REQ_BIN2 = 0x00000085,
12787SPI_PERF_RA_TASK_REQ_BIN3 = 0x00000086,
12788SPI_PERF_RA_WR_CTL_FULL = 0x00000087,
12789SPI_PERF_RA_REQ_NO_ALLOC = 0x00000088,
12790SPI_PERF_RA_REQ_NO_ALLOC_PS = 0x00000089,
12791SPI_PERF_RA_REQ_NO_ALLOC_VS = 0x0000008a,
12792SPI_PERF_RA_REQ_NO_ALLOC_GS = 0x0000008b,
12793SPI_PERF_RA_REQ_NO_ALLOC_HS = 0x0000008c,
12794SPI_PERF_RA_REQ_NO_ALLOC_CSG = 0x0000008d,
12795SPI_PERF_RA_REQ_NO_ALLOC_CSN = 0x0000008e,
12796SPI_PERF_RA_RES_STALL_PS = 0x0000008f,
12797SPI_PERF_RA_RES_STALL_VS = 0x00000090,
12798SPI_PERF_RA_RES_STALL_GS = 0x00000091,
12799SPI_PERF_RA_RES_STALL_HS = 0x00000092,
12800SPI_PERF_RA_RES_STALL_CSG = 0x00000093,
12801SPI_PERF_RA_RES_STALL_CSN = 0x00000094,
12802SPI_PERF_RA_TMP_STALL_PS = 0x00000095,
12803SPI_PERF_RA_TMP_STALL_VS = 0x00000096,
12804SPI_PERF_RA_TMP_STALL_GS = 0x00000097,
12805SPI_PERF_RA_TMP_STALL_HS = 0x00000098,
12806SPI_PERF_RA_TMP_STALL_CSG = 0x00000099,
12807SPI_PERF_RA_TMP_STALL_CSN = 0x0000009a,
12808SPI_PERF_RA_WAVE_SIMD_FULL_PS = 0x0000009b,
12809SPI_PERF_RA_WAVE_SIMD_FULL_VS = 0x0000009c,
12810SPI_PERF_RA_WAVE_SIMD_FULL_GS = 0x0000009d,
12811SPI_PERF_RA_WAVE_SIMD_FULL_HS = 0x0000009e,
12812SPI_PERF_RA_WAVE_SIMD_FULL_CSG = 0x0000009f,
12813SPI_PERF_RA_WAVE_SIMD_FULL_CSN = 0x000000a0,
12814SPI_PERF_RA_VGPR_SIMD_FULL_PS = 0x000000a1,
12815SPI_PERF_RA_VGPR_SIMD_FULL_VS = 0x000000a2,
12816SPI_PERF_RA_VGPR_SIMD_FULL_GS = 0x000000a3,
12817SPI_PERF_RA_VGPR_SIMD_FULL_HS = 0x000000a4,
12818SPI_PERF_RA_VGPR_SIMD_FULL_CSG = 0x000000a5,
12819SPI_PERF_RA_VGPR_SIMD_FULL_CSN = 0x000000a6,
12820SPI_PERF_RA_SGPR_SIMD_FULL_PS = 0x000000a7,
12821SPI_PERF_RA_SGPR_SIMD_FULL_VS = 0x000000a8,
12822SPI_PERF_RA_SGPR_SIMD_FULL_GS = 0x000000a9,
12823SPI_PERF_RA_SGPR_SIMD_FULL_HS = 0x000000aa,
12824SPI_PERF_RA_SGPR_SIMD_FULL_CSG = 0x000000ab,
12825SPI_PERF_RA_SGPR_SIMD_FULL_CSN = 0x000000ac,
12826SPI_PERF_RA_LDS_CU_FULL_PS = 0x000000ad,
12827SPI_PERF_RA_LDS_CU_FULL_LS = 0x000000ae,
12828SPI_PERF_RA_LDS_CU_FULL_ES = 0x000000af,
12829SPI_PERF_RA_LDS_CU_FULL_CSG = 0x000000b0,
12830SPI_PERF_RA_LDS_CU_FULL_CSN = 0x000000b1,
12831SPI_PERF_RA_BAR_CU_FULL_HS = 0x000000b2,
12832SPI_PERF_RA_BAR_CU_FULL_CSG = 0x000000b3,
12833SPI_PERF_RA_BAR_CU_FULL_CSN = 0x000000b4,
12834SPI_PERF_RA_BULKY_CU_FULL_CSG = 0x000000b5,
12835SPI_PERF_RA_BULKY_CU_FULL_CSN = 0x000000b6,
12836SPI_PERF_RA_TGLIM_CU_FULL_CSG = 0x000000b7,
12837SPI_PERF_RA_TGLIM_CU_FULL_CSN = 0x000000b8,
12838SPI_PERF_RA_WVLIM_STALL_PS = 0x000000b9,
12839SPI_PERF_RA_WVLIM_STALL_VS = 0x000000ba,
12840SPI_PERF_RA_WVLIM_STALL_GS = 0x000000bb,
12841SPI_PERF_RA_WVLIM_STALL_HS = 0x000000bc,
12842SPI_PERF_RA_WVLIM_STALL_CSG = 0x000000bd,
12843SPI_PERF_RA_WVLIM_STALL_CSN = 0x000000be,
12844SPI_PERF_RA_VS_LOCK = 0x000000bf,
12845SPI_PERF_RA_GS_LOCK = 0x000000c0,
12846SPI_PERF_RA_HS_LOCK = 0x000000c1,
12847SPI_PERF_RA_CSG_LOCK = 0x000000c2,
12848SPI_PERF_RA_CSN_LOCK = 0x000000c3,
12849SPI_PERF_RA_RSV_UPD = 0x000000c4,
12850SPI_PERF_EXP_ARB_COL_CNT = 0x000000c5,
12851SPI_PERF_EXP_ARB_PAR_CNT = 0x000000c6,
12852SPI_PERF_EXP_ARB_POS_CNT = 0x000000c7,
12853SPI_PERF_EXP_ARB_GDS_CNT = 0x000000c8,
12854SPI_PERF_NUM_PS_COL_R0_EXPORTS = 0x000000c9,
12855SPI_PERF_NUM_PS_COL_R1_EXPORTS = 0x000000ca,
12856SPI_PERF_NUM_VS_POS_R0_EXPORTS = 0x000000cb,
12857SPI_PERF_NUM_VS_POS_R1_EXPORTS = 0x000000cc,
12858SPI_PERF_NUM_VS_PARAM_R0_EXPORTS = 0x000000cd,
12859SPI_PERF_NUM_VS_PARAM_R1_EXPORTS = 0x000000ce,
12860SPI_PERF_NUM_VS_GDS_R0_EXPORTS = 0x000000cf,
12861SPI_PERF_NUM_VS_GDS_R1_EXPORTS = 0x000000d0,
12862SPI_PERF_NUM_EXPGRANT_EXPORTS = 0x000000d1,
12863SPI_PERF_CLKGATE_BUSY_STALL = 0x000000d2,
12864SPI_PERF_CLKGATE_ACTIVE_STALL = 0x000000d3,
12865SPI_PERF_CLKGATE_ALL_CLOCKS_ON = 0x000000d4,
12866SPI_PERF_CLKGATE_CGTT_DYN_ON = 0x000000d5,
12867SPI_PERF_CLKGATE_CGTT_REG_ON = 0x000000d6,
12868SPI_PERF_PIX_ALLOC_PEND_CNT = 0x000000d7,
12869SPI_PERF_PIX_ALLOC_SCB0_STALL = 0x000000d8,
12870SPI_PERF_PIX_ALLOC_SCB1_STALL = 0x000000d9,
12871SPI_PERF_PIX_ALLOC_SCB2_STALL = 0x000000da,
12872SPI_PERF_PIX_ALLOC_SCB3_STALL = 0x000000db,
12873SPI_PERF_PIX_ALLOC_DB0_STALL = 0x000000dc,
12874SPI_PERF_PIX_ALLOC_DB1_STALL = 0x000000dd,
12875SPI_PERF_PIX_ALLOC_DB2_STALL = 0x000000de,
12876SPI_PERF_PIX_ALLOC_DB3_STALL = 0x000000df,
12877SPI_PERF_PIX_ALLOC_DB4_STALL = 0x000000e0,
12878SPI_PERF_PIX_ALLOC_DB5_STALL = 0x000000e1,
12879SPI_PERF_PIX_ALLOC_DB6_STALL = 0x000000e2,
12880SPI_PERF_PIX_ALLOC_DB7_STALL = 0x000000e3,
12881SPI_PERF_PC_ALLOC_ACCUM = 0x000000e4,
12882SPI_PERF_GS_NGG_SE_HAS_BATON = 0x000000e5,
12883SPI_PERF_GS_NGG_SE_DOES_NOT_HAVE_BATON = 0x000000e6,
12884SPI_PERF_GS_NGG_SE_FORWARDED_BATON = 0x000000e7,
12885SPI_PERF_GS_NGG_SE_AT_SYNC_EVENT = 0x000000e8,
12886SPI_PERF_GS_NGG_SE_SG_ALLOC_PC_SPACE_CNT = 0x000000e9,
12887SPI_PERF_GS_NGG_SE_DEALLOC_PC_SPACE_CNT = 0x000000ea,
12888SPI_PERF_GS_NGG_PC_FULL = 0x000000eb,
12889SPI_PERF_GS_NGG_SE_SEND_GS_ALLOC = 0x000000ec,
12890SPI_PERF_GS_NGG_GS_ALLOC_FIFO_EMPTY = 0x000000ed,
12891SPI_PERF_GSC_VTX_BUSY = 0x000000ee,
12892SPI_PERF_GSC_VTX_INPUT_STARVED = 0x000000ef,
12893SPI_PERF_GSC_VTX_VSR_STALL = 0x000000f0,
12894SPI_PERF_GSC_VTX_VSR_FULL = 0x000000f1,
12895SPI_PERF_GSC_VTX_CAC_BUSY = 0x000000f2,
12896SPI_PERF_ESC_VTX_BUSY = 0x000000f3,
12897SPI_PERF_ESC_VTX_INPUT_STARVED = 0x000000f4,
12898SPI_PERF_ESC_VTX_VSR_STALL = 0x000000f5,
12899SPI_PERF_ESC_VTX_VSR_FULL = 0x000000f6,
12900SPI_PERF_ESC_VTX_CAC_BUSY = 0x000000f7,
12901SPI_PERF_SWC_PS_WR = 0x000000f8,
12902SPI_PERF_SWC_VS_WR = 0x000000f9,
12903SPI_PERF_SWC_GS_WR = 0x000000fa,
12904SPI_PERF_SWC_HS_WR = 0x000000fb,
12905SPI_PERF_SWC_CSG_WR = 0x000000fc,
12906SPI_PERF_SWC_CSC_WR = 0x000000fd,
12907SPI_PERF_VWC_PS_WR = 0x000000fe,
12908SPI_PERF_VWC_VS_WR = 0x000000ff,
12909SPI_PERF_VWC_GS_WR = 0x00000100,
12910SPI_PERF_VWC_HS_WR = 0x00000101,
12911SPI_PERF_VWC_CSG_WR = 0x00000102,
12912SPI_PERF_VWC_CSC_WR = 0x00000103,
12913SPI_PERF_ES_WINDOW_VALID = 0x00000104,
12914SPI_PERF_ES_BUSY = 0x00000105,
12915SPI_PERF_ES_CRAWLER_STALL = 0x00000106,
12916SPI_PERF_ES_FIRST_WAVE = 0x00000107,
12917SPI_PERF_ES_LAST_WAVE = 0x00000108,
12918SPI_PERF_ES_LSHS_DEALLOC = 0x00000109,
12919SPI_PERF_ES_EVENT_WAVE = 0x0000010a,
12920SPI_PERF_ES_WAVE = 0x0000010b,
12921SPI_PERF_ES_PERS_UPD_FULL0 = 0x0000010c,
12922SPI_PERF_ES_PERS_UPD_FULL1 = 0x0000010d,
12923SPI_PERF_ES_FIRST_SUBGRP = 0x0000010e,
12924SPI_PERF_ES_LAST_SUBGRP = 0x0000010f,
12925SPI_PERF_LS_WINDOW_VALID = 0x00000110,
12926SPI_PERF_LS_BUSY = 0x00000111,
12927SPI_PERF_LS_CRAWLER_STALL = 0x00000112,
12928SPI_PERF_LS_FIRST_WAVE = 0x00000113,
12929SPI_PERF_LS_LAST_WAVE = 0x00000114,
12930SPI_PERF_LS_OFFCHIP_LDS_STALL = 0x00000115,
12931SPI_PERF_LS_EVENT_WAVE = 0x00000116,
12932SPI_PERF_LS_WAVE = 0x00000117,
12933SPI_PERF_LS_PERS_UPD_FULL0 = 0x00000118,
12934SPI_PERF_LS_PERS_UPD_FULL1 = 0x00000119,
12935} SPI_PERFCNT_SEL;
12936
12937/*
12938 * SPI_SHADER_FORMAT enum
12939 */
12940
12941typedef enum SPI_SHADER_FORMAT {
12942SPI_SHADER_NONE = 0x00000000,
12943SPI_SHADER_1COMP = 0x00000001,
12944SPI_SHADER_2COMP = 0x00000002,
12945SPI_SHADER_4COMPRESS = 0x00000003,
12946SPI_SHADER_4COMP = 0x00000004,
12947} SPI_SHADER_FORMAT;
12948
12949/*
12950 * SPI_SHADER_EX_FORMAT enum
12951 */
12952
12953typedef enum SPI_SHADER_EX_FORMAT {
12954SPI_SHADER_ZERO = 0x00000000,
12955SPI_SHADER_32_R = 0x00000001,
12956SPI_SHADER_32_GR = 0x00000002,
12957SPI_SHADER_32_AR = 0x00000003,
12958SPI_SHADER_FP16_ABGR = 0x00000004,
12959SPI_SHADER_UNORM16_ABGR = 0x00000005,
12960SPI_SHADER_SNORM16_ABGR = 0x00000006,
12961SPI_SHADER_UINT16_ABGR = 0x00000007,
12962SPI_SHADER_SINT16_ABGR = 0x00000008,
12963SPI_SHADER_32_ABGR = 0x00000009,
12964} SPI_SHADER_EX_FORMAT;
12965
12966/*
12967 * CLKGATE_SM_MODE enum
12968 */
12969
12970typedef enum CLKGATE_SM_MODE {
12971ON_SEQ = 0x00000000,
12972OFF_SEQ = 0x00000001,
12973PROG_SEQ = 0x00000002,
12974READ_SEQ = 0x00000003,
12975SM_MODE_RESERVED = 0x00000004,
12976} CLKGATE_SM_MODE;
12977
12978/*
12979 * CLKGATE_BASE_MODE enum
12980 */
12981
12982typedef enum CLKGATE_BASE_MODE {
12983MULT_8 = 0x00000000,
12984MULT_16 = 0x00000001,
12985} CLKGATE_BASE_MODE;
12986
12987/*
12988 * SPI_LB_WAVES_SELECT enum
12989 */
12990
12991typedef enum SPI_LB_WAVES_SELECT {
12992HS_GS = 0x00000000,
12993VS_PS = 0x00000001,
12994CS_NA = 0x00000002,
12995SPI_LB_WAVES_RSVD = 0x00000003,
12996} SPI_LB_WAVES_SELECT;
12997
12998/*******************************************************
12999 * SQ Enums
13000 *******************************************************/
13001
13002/*
13003 * SQ_TEX_CLAMP enum
13004 */
13005
13006typedef enum SQ_TEX_CLAMP {
13007SQ_TEX_WRAP = 0x00000000,
13008SQ_TEX_MIRROR = 0x00000001,
13009SQ_TEX_CLAMP_LAST_TEXEL = 0x00000002,
13010SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 0x00000003,
13011SQ_TEX_CLAMP_HALF_BORDER = 0x00000004,
13012SQ_TEX_MIRROR_ONCE_HALF_BORDER = 0x00000005,
13013SQ_TEX_CLAMP_BORDER = 0x00000006,
13014SQ_TEX_MIRROR_ONCE_BORDER = 0x00000007,
13015} SQ_TEX_CLAMP;
13016
13017/*
13018 * SQ_TEX_XY_FILTER enum
13019 */
13020
13021typedef enum SQ_TEX_XY_FILTER {
13022SQ_TEX_XY_FILTER_POINT = 0x00000000,
13023SQ_TEX_XY_FILTER_BILINEAR = 0x00000001,
13024SQ_TEX_XY_FILTER_ANISO_POINT = 0x00000002,
13025SQ_TEX_XY_FILTER_ANISO_BILINEAR = 0x00000003,
13026} SQ_TEX_XY_FILTER;
13027
13028/*
13029 * SQ_TEX_Z_FILTER enum
13030 */
13031
13032typedef enum SQ_TEX_Z_FILTER {
13033SQ_TEX_Z_FILTER_NONE = 0x00000000,
13034SQ_TEX_Z_FILTER_POINT = 0x00000001,
13035SQ_TEX_Z_FILTER_LINEAR = 0x00000002,
13036} SQ_TEX_Z_FILTER;
13037
13038/*
13039 * SQ_TEX_MIP_FILTER enum
13040 */
13041
13042typedef enum SQ_TEX_MIP_FILTER {
13043SQ_TEX_MIP_FILTER_NONE = 0x00000000,
13044SQ_TEX_MIP_FILTER_POINT = 0x00000001,
13045SQ_TEX_MIP_FILTER_LINEAR = 0x00000002,
13046SQ_TEX_MIP_FILTER_POINT_ANISO_ADJ = 0x00000003,
13047} SQ_TEX_MIP_FILTER;
13048
13049/*
13050 * SQ_TEX_ANISO_RATIO enum
13051 */
13052
13053typedef enum SQ_TEX_ANISO_RATIO {
13054SQ_TEX_ANISO_RATIO_1 = 0x00000000,
13055SQ_TEX_ANISO_RATIO_2 = 0x00000001,
13056SQ_TEX_ANISO_RATIO_4 = 0x00000002,
13057SQ_TEX_ANISO_RATIO_8 = 0x00000003,
13058SQ_TEX_ANISO_RATIO_16 = 0x00000004,
13059} SQ_TEX_ANISO_RATIO;
13060
13061/*
13062 * SQ_TEX_DEPTH_COMPARE enum
13063 */
13064
13065typedef enum SQ_TEX_DEPTH_COMPARE {
13066SQ_TEX_DEPTH_COMPARE_NEVER = 0x00000000,
13067SQ_TEX_DEPTH_COMPARE_LESS = 0x00000001,
13068SQ_TEX_DEPTH_COMPARE_EQUAL = 0x00000002,
13069SQ_TEX_DEPTH_COMPARE_LESSEQUAL = 0x00000003,
13070SQ_TEX_DEPTH_COMPARE_GREATER = 0x00000004,
13071SQ_TEX_DEPTH_COMPARE_NOTEQUAL = 0x00000005,
13072SQ_TEX_DEPTH_COMPARE_GREATEREQUAL = 0x00000006,
13073SQ_TEX_DEPTH_COMPARE_ALWAYS = 0x00000007,
13074} SQ_TEX_DEPTH_COMPARE;
13075
13076/*
13077 * SQ_TEX_BORDER_COLOR enum
13078 */
13079
13080typedef enum SQ_TEX_BORDER_COLOR {
13081SQ_TEX_BORDER_COLOR_TRANS_BLACK = 0x00000000,
13082SQ_TEX_BORDER_COLOR_OPAQUE_BLACK = 0x00000001,
13083SQ_TEX_BORDER_COLOR_OPAQUE_WHITE = 0x00000002,
13084SQ_TEX_BORDER_COLOR_REGISTER = 0x00000003,
13085} SQ_TEX_BORDER_COLOR;
13086
13087/*
13088 * SQ_RSRC_BUF_TYPE enum
13089 */
13090
13091typedef enum SQ_RSRC_BUF_TYPE {
13092SQ_RSRC_BUF = 0x00000000,
13093SQ_RSRC_BUF_RSVD_1 = 0x00000001,
13094SQ_RSRC_BUF_RSVD_2 = 0x00000002,
13095SQ_RSRC_BUF_RSVD_3 = 0x00000003,
13096} SQ_RSRC_BUF_TYPE;
13097
13098/*
13099 * SQ_RSRC_IMG_TYPE enum
13100 */
13101
13102typedef enum SQ_RSRC_IMG_TYPE {
13103SQ_RSRC_IMG_RSVD_0 = 0x00000000,
13104SQ_RSRC_IMG_RSVD_1 = 0x00000001,
13105SQ_RSRC_IMG_RSVD_2 = 0x00000002,
13106SQ_RSRC_IMG_RSVD_3 = 0x00000003,
13107SQ_RSRC_IMG_RSVD_4 = 0x00000004,
13108SQ_RSRC_IMG_RSVD_5 = 0x00000005,
13109SQ_RSRC_IMG_RSVD_6 = 0x00000006,
13110SQ_RSRC_IMG_RSVD_7 = 0x00000007,
13111SQ_RSRC_IMG_1D = 0x00000008,
13112SQ_RSRC_IMG_2D = 0x00000009,
13113SQ_RSRC_IMG_3D = 0x0000000a,
13114SQ_RSRC_IMG_CUBE = 0x0000000b,
13115SQ_RSRC_IMG_1D_ARRAY = 0x0000000c,
13116SQ_RSRC_IMG_2D_ARRAY = 0x0000000d,
13117SQ_RSRC_IMG_2D_MSAA = 0x0000000e,
13118SQ_RSRC_IMG_2D_MSAA_ARRAY = 0x0000000f,
13119} SQ_RSRC_IMG_TYPE;
13120
13121/*
13122 * SQ_RSRC_FLAT_TYPE enum
13123 */
13124
13125typedef enum SQ_RSRC_FLAT_TYPE {
13126SQ_RSRC_FLAT_RSVD_0 = 0x00000000,
13127SQ_RSRC_FLAT = 0x00000001,
13128SQ_RSRC_FLAT_RSVD_2 = 0x00000002,
13129SQ_RSRC_FLAT_RSVD_3 = 0x00000003,
13130} SQ_RSRC_FLAT_TYPE;
13131
13132/*
13133 * SQ_IMG_FILTER_TYPE enum
13134 */
13135
13136typedef enum SQ_IMG_FILTER_TYPE {
13137SQ_IMG_FILTER_MODE_BLEND = 0x00000000,
13138SQ_IMG_FILTER_MODE_MIN = 0x00000001,
13139SQ_IMG_FILTER_MODE_MAX = 0x00000002,
13140} SQ_IMG_FILTER_TYPE;
13141
13142/*
13143 * SQ_SEL_XYZW01 enum
13144 */
13145
13146typedef enum SQ_SEL_XYZW01 {
13147SQ_SEL_0 = 0x00000000,
13148SQ_SEL_1 = 0x00000001,
13149SQ_SEL_N_BC_1 = 0x00000002,
13150SQ_SEL_RESERVED_1 = 0x00000003,
13151SQ_SEL_X = 0x00000004,
13152SQ_SEL_Y = 0x00000005,
13153SQ_SEL_Z = 0x00000006,
13154SQ_SEL_W = 0x00000007,
13155} SQ_SEL_XYZW01;
13156
13157/*
13158 * SQ_OOB_SELECT enum
13159 */
13160
13161typedef enum SQ_OOB_SELECT {
13162SQ_OOB_INDEX_AND_OFFSET = 0x00000000,
13163SQ_OOB_INDEX_ONLY = 0x00000001,
13164SQ_OOB_NUM_RECORDS_0 = 0x00000002,
13165SQ_OOB_COMPLETE = 0x00000003,
13166} SQ_OOB_SELECT;
13167
13168/*
13169 * SQ_WAVE_TYPE enum
13170 */
13171
13172typedef enum SQ_WAVE_TYPE {
13173SQ_WAVE_TYPE_PS = 0x00000000,
13174SQ_WAVE_TYPE_VS = 0x00000001,
13175SQ_WAVE_TYPE_GS = 0x00000002,
13176SQ_WAVE_TYPE_ES = 0x00000003,
13177SQ_WAVE_TYPE_HS = 0x00000004,
13178SQ_WAVE_TYPE_LS = 0x00000005,
13179SQ_WAVE_TYPE_CS = 0x00000006,
13180SQ_WAVE_TYPE_PS1 = 0x00000007,
13181SQ_WAVE_TYPE_PS2 = 0x00000008,
13182SQ_WAVE_TYPE_PS3 = 0x00000009,
13183} SQ_WAVE_TYPE;
13184
13185/*
13186 * SQ_PERF_SEL enum
13187 */
13188
13189typedef enum SQ_PERF_SEL {
13190SQ_PERF_SEL_NONE = 0x00000000,
13191SQ_PERF_SEL_ACCUM_PREV = 0x00000001,
13192SQ_PERF_SEL_CYCLES = 0x00000002,
13193SQ_PERF_SEL_BUSY_CYCLES = 0x00000003,
13194SQ_PERF_SEL_WAVES = 0x00000004,
13195SQ_PERF_SEL_WAVES_32 = 0x00000005,
13196SQ_PERF_SEL_WAVES_64 = 0x00000006,
13197SQ_PERF_SEL_LEVEL_WAVES = 0x00000007,
13198SQ_PERF_SEL_ITEMS = 0x00000008,
13199SQ_PERF_SEL_WAVE32_ITEMS = 0x00000009,
13200SQ_PERF_SEL_WAVE64_ITEMS = 0x0000000a,
13201SQ_PERF_SEL_QUADS = 0x0000000b,
13202SQ_PERF_SEL_EVENTS = 0x0000000c,
13203SQ_PERF_SEL_WAVES_EQ_64 = 0x0000000d,
13204SQ_PERF_SEL_WAVES_LT_64 = 0x0000000e,
13205SQ_PERF_SEL_WAVES_LT_48 = 0x0000000f,
13206SQ_PERF_SEL_WAVES_LT_32 = 0x00000010,
13207SQ_PERF_SEL_WAVES_LT_16 = 0x00000011,
13208SQ_PERF_SEL_WAVES_RESTORED = 0x00000012,
13209SQ_PERF_SEL_WAVES_SAVED = 0x00000013,
13210SQ_PERF_SEL_MSG = 0x00000014,
13211SQ_PERF_SEL_MSG_GSCNT = 0x00000015,
13212SQ_PERF_SEL_MSG_INTERRUPT = 0x00000016,
13213SQ_PERF_SEL_Reserved_1 = 0x00000017,
13214SQ_PERF_SEL_Reserved_2 = 0x00000018,
13215SQ_PERF_SEL_Reserved_3 = 0x00000019,
13216SQ_PERF_SEL_WAVE_CYCLES = 0x0000001a,
13217SQ_PERF_SEL_WAVE_READY = 0x0000001b,
13218SQ_PERF_SEL_WAIT_INST_ANY = 0x0000001c,
13219SQ_PERF_SEL_WAIT_INST_VALU = 0x0000001d,
13220SQ_PERF_SEL_WAIT_INST_SCA = 0x0000001e,
13221SQ_PERF_SEL_WAIT_INST_LDS = 0x0000001f,
13222SQ_PERF_SEL_WAIT_INST_TEX = 0x00000020,
13223SQ_PERF_SEL_WAIT_INST_FLAT = 0x00000021,
13224SQ_PERF_SEL_WAIT_INST_VMEM = 0x00000022,
13225SQ_PERF_SEL_WAIT_INST_EXP_GDS = 0x00000023,
13226SQ_PERF_SEL_WAIT_INST_BR_MSG = 0x00000024,
13227SQ_PERF_SEL_WAIT_ANY = 0x00000025,
13228SQ_PERF_SEL_WAIT_CNT_ANY = 0x00000026,
13229SQ_PERF_SEL_WAIT_CNT_VMVS = 0x00000027,
13230SQ_PERF_SEL_WAIT_CNT_LGKM = 0x00000028,
13231SQ_PERF_SEL_WAIT_CNT_EXP = 0x00000029,
13232SQ_PERF_SEL_WAIT_TTRACE = 0x0000002a,
13233SQ_PERF_SEL_WAIT_IFETCH = 0x0000002b,
13234SQ_PERF_SEL_WAIT_BARRIER = 0x0000002c,
13235SQ_PERF_SEL_WAIT_EXP_ALLOC = 0x0000002d,
13236SQ_PERF_SEL_WAIT_SLEEP = 0x0000002e,
13237SQ_PERF_SEL_WAIT_SLEEP_XNACK = 0x0000002f,
13238SQ_PERF_SEL_WAIT_OTHER = 0x00000030,
13239SQ_PERF_SEL_INSTS_ALL = 0x00000031,
13240SQ_PERF_SEL_INSTS_BRANCH = 0x00000032,
13241SQ_PERF_SEL_INSTS_CBRANCH_NOT_TAKEN = 0x00000033,
13242SQ_PERF_SEL_INSTS_CBRANCH_TAKEN = 0x00000034,
13243SQ_PERF_SEL_INSTS_CBRANCH_TAKEN_HIT_IS = 0x00000035,
13244SQ_PERF_SEL_INSTS_EXP_GDS = 0x00000036,
13245SQ_PERF_SEL_INSTS_GDS = 0x00000037,
13246SQ_PERF_SEL_INSTS_EXP = 0x00000038,
13247SQ_PERF_SEL_INSTS_FLAT = 0x00000039,
13248SQ_PERF_SEL_Reserved_4 = 0x0000003a,
13249SQ_PERF_SEL_INSTS_LDS = 0x0000003b,
13250SQ_PERF_SEL_INSTS_SALU = 0x0000003c,
13251SQ_PERF_SEL_INSTS_SMEM = 0x0000003d,
13252SQ_PERF_SEL_INSTS_SMEM_NORM = 0x0000003e,
13253SQ_PERF_SEL_INSTS_SENDMSG = 0x0000003f,
13254SQ_PERF_SEL_INSTS_VALU = 0x00000040,
13255SQ_PERF_SEL_Reserved_17 = 0x00000041,
13256SQ_PERF_SEL_INSTS_VALU_TRANS32 = 0x00000042,
13257SQ_PERF_SEL_INSTS_VALU_NO_COEXEC = 0x00000043,
13258SQ_PERF_SEL_INSTS_TEX = 0x00000044,
13259SQ_PERF_SEL_INSTS_TEX_LOAD = 0x00000045,
13260SQ_PERF_SEL_INSTS_TEX_STORE = 0x00000046,
13261SQ_PERF_SEL_INSTS_WAVE32 = 0x00000047,
13262SQ_PERF_SEL_INSTS_WAVE32_FLAT = 0x00000048,
13263SQ_PERF_SEL_Reserved_5 = 0x00000049,
13264SQ_PERF_SEL_INSTS_WAVE32_LDS = 0x0000004a,
13265SQ_PERF_SEL_INSTS_WAVE32_VALU = 0x0000004b,
13266SQ_PERF_SEL_Reserved_16 = 0x0000004c,
13267SQ_PERF_SEL_INSTS_WAVE32_VALU_TRANS32 = 0x0000004d,
13268SQ_PERF_SEL_INSTS_WAVE32_VALU_NO_COEXEC = 0x0000004e,
13269SQ_PERF_SEL_INSTS_WAVE32_TEX = 0x0000004f,
13270SQ_PERF_SEL_INSTS_WAVE32_TEX_LOAD = 0x00000050,
13271SQ_PERF_SEL_INSTS_WAVE32_TEX_STORE = 0x00000051,
13272SQ_PERF_SEL_ITEM_CYCLES_VALU = 0x00000052,
13273SQ_PERF_SEL_VALU_READWRITELANE_CYCLES = 0x00000053,
13274SQ_PERF_SEL_WAVE32_INSTS = 0x00000054,
13275SQ_PERF_SEL_WAVE64_INSTS = 0x00000055,
13276SQ_PERF_SEL_Reserved_18 = 0x00000056,
13277SQ_PERF_SEL_INSTS_VALU_EXEC_SKIPPED = 0x00000057,
13278SQ_PERF_SEL_WAVE64_HALF_SKIP = 0x00000058,
13279SQ_PERF_SEL_INSTS_TEX_REPLAY = 0x00000059,
13280SQ_PERF_SEL_INSTS_SMEM_REPLAY = 0x0000005a,
13281SQ_PERF_SEL_INSTS_SMEM_NORM_REPLAY = 0x0000005b,
13282SQ_PERF_SEL_INSTS_FLAT_REPLAY = 0x0000005c,
13283SQ_PERF_SEL_XNACK_ALL = 0x0000005d,
13284SQ_PERF_SEL_XNACK_FIRST = 0x0000005e,
13285SQ_PERF_SEL_INSTS_VALU_LDS_DIRECT_RD = 0x0000005f,
13286SQ_PERF_SEL_INSTS_VALU_VINTRP_OP = 0x00000060,
13287SQ_PERF_SEL_INST_LEVEL_EXP = 0x00000061,
13288SQ_PERF_SEL_INST_LEVEL_GDS = 0x00000062,
13289SQ_PERF_SEL_INST_LEVEL_LDS = 0x00000063,
13290SQ_PERF_SEL_INST_LEVEL_SMEM = 0x00000064,
13291SQ_PERF_SEL_INST_LEVEL_TEX_LOAD = 0x00000065,
13292SQ_PERF_SEL_INST_LEVEL_TEX_STORE = 0x00000066,
13293SQ_PERF_SEL_IFETCH_REQS = 0x00000067,
13294SQ_PERF_SEL_IFETCH_LEVEL = 0x00000068,
13295SQ_PERF_SEL_IFETCH_XNACK = 0x00000069,
13296SQ_PERF_SEL_Reserved_6 = 0x0000006a,
13297SQ_PERF_SEL_Reserved_7 = 0x0000006b,
13298SQ_PERF_SEL_LDS_DIRECT_CMD_FIFO_FULL_STALL = 0x0000006c,
13299SQ_PERF_SEL_VALU_SGATHER_STALL = 0x0000006d,
13300SQ_PERF_SEL_VALU_FWD_BUFFER_FULL_STALL = 0x0000006e,
13301SQ_PERF_SEL_VALU_SGPR_RD_FIFO_FULL_STALL = 0x0000006f,
13302SQ_PERF_SEL_VALU_SGATHER_FULL_STALL = 0x00000070,
13303SQ_PERF_SEL_SALU_SGATHER_STALL = 0x00000071,
13304SQ_PERF_SEL_SALU_SGPR_RD_FIFO_FULL_STALL = 0x00000072,
13305SQ_PERF_SEL_SALU_GATHER_FULL_STALL = 0x00000073,
13306SQ_PERF_SEL_SMEM_DCACHE_FIFO_FULL_STALL = 0x00000074,
13307SQ_PERF_SEL_INST_CYCLES_VALU = 0x00000075,
13308SQ_PERF_SEL_INST_CYCLES_VALU_TRANS32 = 0x00000076,
13309SQ_PERF_SEL_INST_CYCLES_VALU_NO_COEXEC = 0x00000077,
13310SQ_PERF_SEL_INST_CYCLES_VMEM = 0x00000078,
13311SQ_PERF_SEL_INST_CYCLES_VMEM_LOAD = 0x00000079,
13312SQ_PERF_SEL_INST_CYCLES_VMEM_STORE = 0x0000007a,
13313SQ_PERF_SEL_INST_CYCLES_LDS = 0x0000007b,
13314SQ_PERF_SEL_INST_CYCLES_TEX = 0x0000007c,
13315SQ_PERF_SEL_INST_CYCLES_FLAT = 0x0000007d,
13316SQ_PERF_SEL_INST_CYCLES_EXP_GDS = 0x0000007e,
13317SQ_PERF_SEL_VMEM_ARB_FIFO_FULL = 0x0000007f,
13318SQ_PERF_SEL_MSG_FIFO_FULL_STALL = 0x00000080,
13319SQ_PERF_SEL_EXP_REQ_FIFO_FULL = 0x00000081,
13320SQ_PERF_SEL_Reserved_8 = 0x00000082,
13321SQ_PERF_SEL_Reserved_9 = 0x00000083,
13322SQ_PERF_SEL_Reserved_10 = 0x00000084,
13323SQ_PERF_SEL_Reserved_11 = 0x00000085,
13324SQ_PERF_SEL_Reserved_12 = 0x00000086,
13325SQ_PERF_SEL_Reserved_13 = 0x00000087,
13326SQ_PERF_SEL_Reserved_14 = 0x00000088,
13327SQ_PERF_SEL_VMEM_BUS_ACTIVE = 0x00000089,
13328SQ_PERF_SEL_VMEM_BUS_STALL = 0x0000008a,
13329SQ_PERF_SEL_VMEM_BUS_STALL_TA_ADDR_FIFO_FULL = 0x0000008b,
13330SQ_PERF_SEL_VMEM_BUS_STALL_TA_CMD_FIFO_FULL = 0x0000008c,
13331SQ_PERF_SEL_VMEM_BUS_STALL_LDS_ADDR_FIFO_FULL = 0x0000008d,
13332SQ_PERF_SEL_VMEM_BUS_STALL_LDS_CMD_FIFO_FULL = 0x0000008e,
13333SQ_PERF_SEL_VMEM_STARVE_TA_ADDR_EMPTY = 0x0000008f,
13334SQ_PERF_SEL_VMEM_STARVE_LDS_ADDR_EMPTY = 0x00000090,
13335SQ_PERF_SEL_Reserved_15 = 0x00000091,
13336SQ_PERF_SEL_SALU_PIPE_STALL = 0x00000092,
13337SQ_PERF_SEL_SMEM_DCACHE_RETURN_CYCLES = 0x00000093,
13338SQ_PERF_SEL_SMEM_DCACHE_RETURN_STALL = 0x00000094,
13339SQ_PERF_SEL_MSG_BUS_BUSY = 0x00000095,
13340SQ_PERF_SEL_EXP_REQ_BUS_STALL = 0x00000096,
13341SQ_PERF_SEL_EXP_REQ0_BUS_BUSY = 0x00000097,
13342SQ_PERF_SEL_EXP_REQ1_BUS_BUSY = 0x00000098,
13343SQ_PERF_SEL_EXP_BUS0_BUSY = 0x00000099,
13344SQ_PERF_SEL_EXP_BUS1_BUSY = 0x0000009a,
13345SQ_PERF_SEL_INST_CACHE_REQS = 0x0000009b,
13346SQ_PERF_SEL_INST_CACHE_REQ_STALL = 0x0000009c,
13347SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VALU = 0x0000009d,
13348SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_SALU = 0x0000009e,
13349SQ_PERF_SEL_MIXED_SUBSEQUENT_ISSUES_VMEM = 0x0000009f,
13350SQ_PERF_SEL_USER0 = 0x000000a0,
13351SQ_PERF_SEL_USER1 = 0x000000a1,
13352SQ_PERF_SEL_USER2 = 0x000000a2,
13353SQ_PERF_SEL_USER3 = 0x000000a3,
13354SQ_PERF_SEL_USER4 = 0x000000a4,
13355SQ_PERF_SEL_USER5 = 0x000000a5,
13356SQ_PERF_SEL_USER6 = 0x000000a6,
13357SQ_PERF_SEL_USER7 = 0x000000a7,
13358SQ_PERF_SEL_USER8 = 0x000000a8,
13359SQ_PERF_SEL_USER9 = 0x000000a9,
13360SQ_PERF_SEL_USER10 = 0x000000aa,
13361SQ_PERF_SEL_USER11 = 0x000000ab,
13362SQ_PERF_SEL_USER12 = 0x000000ac,
13363SQ_PERF_SEL_USER13 = 0x000000ad,
13364SQ_PERF_SEL_USER14 = 0x000000ae,
13365SQ_PERF_SEL_USER15 = 0x000000af,
13366SQ_PERF_SEL_USER_LEVEL0 = 0x000000b0,
13367SQ_PERF_SEL_USER_LEVEL1 = 0x000000b1,
13368SQ_PERF_SEL_USER_LEVEL2 = 0x000000b2,
13369SQ_PERF_SEL_USER_LEVEL3 = 0x000000b3,
13370SQ_PERF_SEL_USER_LEVEL4 = 0x000000b4,
13371SQ_PERF_SEL_USER_LEVEL5 = 0x000000b5,
13372SQ_PERF_SEL_USER_LEVEL6 = 0x000000b6,
13373SQ_PERF_SEL_USER_LEVEL7 = 0x000000b7,
13374SQ_PERF_SEL_USER_LEVEL8 = 0x000000b8,
13375SQ_PERF_SEL_USER_LEVEL9 = 0x000000b9,
13376SQ_PERF_SEL_USER_LEVEL10 = 0x000000ba,
13377SQ_PERF_SEL_USER_LEVEL11 = 0x000000bb,
13378SQ_PERF_SEL_USER_LEVEL12 = 0x000000bc,
13379SQ_PERF_SEL_USER_LEVEL13 = 0x000000bd,
13380SQ_PERF_SEL_USER_LEVEL14 = 0x000000be,
13381SQ_PERF_SEL_USER_LEVEL15 = 0x000000bf,
13382SQ_PERF_SEL_VALU_RETURN_SDST = 0x000000c0,
13383SQ_PERF_SEL_VMEM_SECOND_TRY_USED = 0x000000c1,
13384SQ_PERF_SEL_VMEM_SECOND_TRY_STALL = 0x000000c2,
13385SQ_PERF_SEL_DUMMY_END = 0x000000c3,
13386SQ_PERF_SEL_DUMMY_LAST = 0x000000ff,
13387SQG_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x00000100,
13388SQG_PERF_SEL_UTCL0_PERMISSION_MISS = 0x00000101,
13389SQG_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x00000102,
13390SQG_PERF_SEL_UTCL0_REQUEST = 0x00000103,
13391SQG_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x00000104,
13392SQG_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x00000105,
13393SQG_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000106,
13394SQG_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000107,
13395SQG_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000108,
13396SQG_PERF_SEL_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x00000109,
13397SQG_PERF_SEL_UTCL0_HIT_FIFO_FULL = 0x0000010a,
13398SQG_PERF_SEL_UTCL0_UTCL1_REQ = 0x0000010b,
13399SQG_PERF_SEL_TLB_SHOOTDOWN = 0x0000010c,
13400SQG_PERF_SEL_TLB_SHOOTDOWN_CYCLES = 0x0000010d,
13401SQG_PERF_SEL_TTRACE_REQS = 0x0000010e,
13402SQG_PERF_SEL_TTRACE_INFLIGHT_REQS = 0x0000010f,
13403SQG_PERF_SEL_TTRACE_STALL = 0x00000110,
13404SQG_PERF_SEL_TTRACE_LOST_PACKETS = 0x00000111,
13405SQG_PERF_SEL_DUMMY_LAST = 0x00000112,
13406SQC_PERF_SEL_POWER_VALU = 0x00000113,
13407SQC_PERF_SEL_POWER_VALU0 = 0x00000114,
13408SQC_PERF_SEL_POWER_VALU1 = 0x00000115,
13409SQC_PERF_SEL_POWER_VALU2 = 0x00000116,
13410SQC_PERF_SEL_POWER_GPR_RD = 0x00000117,
13411SQC_PERF_SEL_POWER_GPR_WR = 0x00000118,
13412SQC_PERF_SEL_POWER_LDS_BUSY = 0x00000119,
13413SQC_PERF_SEL_POWER_ALU_BUSY = 0x0000011a,
13414SQC_PERF_SEL_POWER_TEX_BUSY = 0x0000011b,
13415SQC_PERF_SEL_PT_POWER_STALL = 0x0000011c,
13416SQC_PERF_SEL_LDS_BANK_CONFLICT = 0x0000011d,
13417SQC_PERF_SEL_LDS_ADDR_CONFLICT = 0x0000011e,
13418SQC_PERF_SEL_LDS_UNALIGNED_STALL = 0x0000011f,
13419SQC_PERF_SEL_LDS_MEM_VIOLATIONS = 0x00000120,
13420SQC_PERF_SEL_LDS_ATOMIC_RETURN = 0x00000121,
13421SQC_PERF_SEL_LDS_IDX_ACTIVE = 0x00000122,
13422SQC_PERF_SEL_LDS_DATA_FIFO_FULL = 0x00000123,
13423SQC_PERF_SEL_LDS_CMD_FIFO_FULL = 0x00000124,
13424SQC_PERF_SEL_LDS_ADDR_STALL = 0x00000125,
13425SQC_PERF_SEL_LDS_ADDR_ACTIVE = 0x00000126,
13426SQC_PERF_SEL_LDS_DIRECT_FIFO_FULL_STALL = 0x00000127,
13427SQC_PERF_SEL_LDS_PC_LDS_WRITE_STALL_TD = 0x00000128,
13428SQC_PERF_SEL_LDS_SPI_VGPR_WRITE_STALL_TD = 0x00000129,
13429SQC_PERF_SEL_LDS_LDS_VGPR_WRITE_STALL = 0x0000012a,
13430SQC_PERF_SEL_LDS_FP_ADD_CYCLES = 0x0000012b,
13431SQC_PERF_SEL_ICACHE_BUSY_CYCLES = 0x0000012c,
13432SQC_PERF_SEL_ICACHE_REQ = 0x0000012d,
13433SQC_PERF_SEL_ICACHE_HITS = 0x0000012e,
13434SQC_PERF_SEL_ICACHE_MISSES = 0x0000012f,
13435SQC_PERF_SEL_ICACHE_MISSES_DUPLICATE = 0x00000130,
13436SQC_PERF_SEL_ICACHE_INVAL_INST = 0x00000131,
13437SQC_PERF_SEL_ICACHE_INVAL_ASYNC = 0x00000132,
13438SQC_PERF_SEL_ICACHE_INFLIGHT_LEVEL = 0x00000133,
13439SQC_PERF_SEL_DCACHE_INFLIGHT_LEVEL = 0x00000134,
13440SQC_PERF_SEL_TC_INFLIGHT_LEVEL = 0x00000135,
13441SQC_PERF_SEL_ICACHE_TC_INFLIGHT_LEVEL = 0x00000136,
13442SQC_PERF_SEL_DCACHE_TC_INFLIGHT_LEVEL = 0x00000137,
13443SQC_PERF_SEL_ICACHE_INPUT_VALID_READY = 0x00000138,
13444SQC_PERF_SEL_ICACHE_INPUT_VALID_READYB = 0x00000139,
13445SQC_PERF_SEL_ICACHE_INPUT_VALIDB = 0x0000013a,
13446SQC_PERF_SEL_DCACHE_INPUT_VALID_READY = 0x0000013b,
13447SQC_PERF_SEL_DCACHE_INPUT_VALID_READYB = 0x0000013c,
13448SQC_PERF_SEL_DCACHE_INPUT_VALIDB = 0x0000013d,
13449SQC_PERF_SEL_TC_REQ = 0x0000013e,
13450SQC_PERF_SEL_TC_INST_REQ = 0x0000013f,
13451SQC_PERF_SEL_TC_DATA_READ_REQ = 0x00000140,
13452SQC_PERF_SEL_TC_DATA_WRITE_REQ = 0x00000141,
13453SQC_PERF_SEL_TC_DATA_ATOMIC_REQ = 0x00000142,
13454SQC_PERF_SEL_TC_STALL = 0x00000143,
13455SQC_PERF_SEL_TC_STARVE = 0x00000144,
13456SQC_PERF_SEL_ICACHE_INPUT_STALL_ARB_NO_GRANT = 0x00000145,
13457SQC_PERF_SEL_ICACHE_INPUT_STALL_BANK_READYB = 0x00000146,
13458SQC_PERF_SEL_ICACHE_CACHE_STALLED = 0x00000147,
13459SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x00000148,
13460SQC_PERF_SEL_ICACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000149,
13461SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT = 0x0000014a,
13462SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x0000014b,
13463SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x0000014c,
13464SQC_PERF_SEL_ICACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000014d,
13465SQC_PERF_SEL_ICACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000014e,
13466SQC_PERF_SEL_DCACHE_BUSY_CYCLES = 0x0000014f,
13467SQC_PERF_SEL_DCACHE_REQ = 0x00000150,
13468SQC_PERF_SEL_DCACHE_HITS = 0x00000151,
13469SQC_PERF_SEL_DCACHE_MISSES = 0x00000152,
13470SQC_PERF_SEL_DCACHE_MISSES_DUPLICATE = 0x00000153,
13471SQC_PERF_SEL_DCACHE_INVAL_INST = 0x00000154,
13472SQC_PERF_SEL_DCACHE_INVAL_ASYNC = 0x00000155,
13473SQC_PERF_SEL_DCACHE_HIT_LRU_READ = 0x00000156,
13474SQC_PERF_SEL_DCACHE_WC_LRU_WRITE = 0x00000157,
13475SQC_PERF_SEL_DCACHE_WT_EVICT_WRITE = 0x00000158,
13476SQC_PERF_SEL_DCACHE_ATOMIC = 0x00000159,
13477SQC_PERF_SEL_DCACHE_WB_INST = 0x0000015a,
13478SQC_PERF_SEL_DCACHE_WB_ASYNC = 0x0000015b,
13479SQC_PERF_SEL_DCACHE_INPUT_STALL_ARB_NO_GRANT = 0x0000015c,
13480SQC_PERF_SEL_DCACHE_INPUT_STALL_BANK_READYB = 0x0000015d,
13481SQC_PERF_SEL_DCACHE_CACHE_STALLED = 0x0000015e,
13482SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_NONZERO = 0x0000015f,
13483SQC_PERF_SEL_DCACHE_CACHE_STALL_INFLIGHT_MAX = 0x00000160,
13484SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT = 0x00000161,
13485SQC_PERF_SEL_DCACHE_CACHE_STALL_EVICT = 0x00000162,
13486SQC_PERF_SEL_DCACHE_CACHE_STALL_UNORDERED = 0x00000163,
13487SQC_PERF_SEL_DCACHE_CACHE_STALL_ALLOC_UNAVAILABLE = 0x00000164,
13488SQC_PERF_SEL_DCACHE_CACHE_STALL_FORCE_EVICT = 0x00000165,
13489SQC_PERF_SEL_DCACHE_CACHE_STALL_MULTI_FLUSH = 0x00000166,
13490SQC_PERF_SEL_DCACHE_CACHE_STALL_FLUSH_DONE = 0x00000167,
13491SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_MISS_FIFO = 0x00000168,
13492SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_HIT_FIFO = 0x00000169,
13493SQC_PERF_SEL_DCACHE_CACHE_STALL_OUTPUT_TC_IF = 0x0000016a,
13494SQC_PERF_SEL_DCACHE_STALL_OUTXBAR_ARB_NO_GRANT = 0x0000016b,
13495SQC_PERF_SEL_DCACHE_REQ_READ_1 = 0x0000016c,
13496SQC_PERF_SEL_DCACHE_REQ_READ_2 = 0x0000016d,
13497SQC_PERF_SEL_DCACHE_REQ_READ_4 = 0x0000016e,
13498SQC_PERF_SEL_DCACHE_REQ_READ_8 = 0x0000016f,
13499SQC_PERF_SEL_DCACHE_REQ_READ_16 = 0x00000170,
13500SQC_PERF_SEL_DCACHE_REQ_TIME = 0x00000171,
13501SQC_PERF_SEL_DCACHE_REQ_WRITE_1 = 0x00000172,
13502SQC_PERF_SEL_DCACHE_REQ_WRITE_2 = 0x00000173,
13503SQC_PERF_SEL_DCACHE_REQ_WRITE_4 = 0x00000174,
13504SQC_PERF_SEL_DCACHE_REQ_ATC_PROBE = 0x00000175,
13505SQC_PERF_SEL_SQ_DCACHE_REQS = 0x00000176,
13506SQC_PERF_SEL_DCACHE_FLAT_REQ = 0x00000177,
13507SQC_PERF_SEL_DCACHE_NONFLAT_REQ = 0x00000178,
13508SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_MISS = 0x00000179,
13509SQC_PERF_SEL_ICACHE_UTCL0_PERMISSION_MISS = 0x0000017a,
13510SQC_PERF_SEL_ICACHE_UTCL0_TRANSLATION_HIT = 0x0000017b,
13511SQC_PERF_SEL_ICACHE_UTCL0_REQUEST = 0x0000017c,
13512SQC_PERF_SEL_ICACHE_UTCL0_XNACK = 0x0000017d,
13513SQC_PERF_SEL_ICACHE_UTCL0_STALL_INFLIGHT_MAX = 0x0000017e,
13514SQC_PERF_SEL_ICACHE_UTCL0_STALL_LRU_INFLIGHT = 0x0000017f,
13515SQC_PERF_SEL_ICACHE_UTCL0_LFIFO_FULL = 0x00000180,
13516SQC_PERF_SEL_ICACHE_UTCL0_STALL_LFIFO_NOT_RES = 0x00000181,
13517SQC_PERF_SEL_ICACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x00000182,
13518SQC_PERF_SEL_ICACHE_UTCL0_UTCL1_INFLIGHT = 0x00000183,
13519SQC_PERF_SEL_ICACHE_UTCL0_STALL_MISSFIFO_FULL = 0x00000184,
13520SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_MISS = 0x00000185,
13521SQC_PERF_SEL_DCACHE_UTCL0_PERMISSION_MISS = 0x00000186,
13522SQC_PERF_SEL_DCACHE_UTCL0_TRANSLATION_HIT = 0x00000187,
13523SQC_PERF_SEL_DCACHE_UTCL0_REQUEST = 0x00000188,
13524SQC_PERF_SEL_DCACHE_UTCL0_XNACK = 0x00000189,
13525SQC_PERF_SEL_DCACHE_UTCL0_STALL_INFLIGHT_MAX = 0x0000018a,
13526SQC_PERF_SEL_DCACHE_UTCL0_STALL_LRU_INFLIGHT = 0x0000018b,
13527SQC_PERF_SEL_DCACHE_UTCL0_LFIFO_FULL = 0x0000018c,
13528SQC_PERF_SEL_DCACHE_UTCL0_STALL_LFIFO_NOT_RES = 0x0000018d,
13529SQC_PERF_SEL_DCACHE_UTCL0_STALL_UTCL1_REQ_OUT_OF_CREDITS = 0x0000018e,
13530SQC_PERF_SEL_DCACHE_UTCL0_UTCL1_INFLIGHT = 0x0000018f,
13531SQC_PERF_SEL_DCACHE_UTCL0_STALL_MISSFIFO_FULL = 0x00000190,
13532SQC_PERF_SEL_DCACHE_UTCL0_STALL_MULTI_MISS = 0x00000191,
13533SQC_PERF_SEL_DCACHE_UTCL0_HIT_FIFO_FULL = 0x00000192,
13534SQC_PERF_SEL_ICACHE_UTCL0_INFLIGHT_LEVEL = 0x00000193,
13535SQC_PERF_SEL_ICACHE_UTCL0_ALL_REQ = 0x00000194,
13536SQC_PERF_SEL_ICACHE_UTCL1_INFLIGHT_LEVEL = 0x00000195,
13537SQC_PERF_SEL_ICACHE_UTCL1_ALL_REQ = 0x00000196,
13538SQC_PERF_SEL_DCACHE_UTCL0_INFLIGHT_LEVEL = 0x00000197,
13539SQC_PERF_SEL_DCACHE_UTCL0_ALL_REQ = 0x00000198,
13540SQC_PERF_SEL_DCACHE_UTCL1_INFLIGHT_LEVEL = 0x00000199,
13541SQC_PERF_SEL_DCACHE_UTCL1_ALL_REQ = 0x0000019a,
13542SQC_PERF_SEL_ICACHE_GCR = 0x0000019b,
13543SQC_PERF_SEL_ICACHE_GCR_HITS = 0x0000019c,
13544SQC_PERF_SEL_DCACHE_GCR = 0x0000019d,
13545SQC_PERF_SEL_DCACHE_GCR_HITS = 0x0000019e,
13546SQC_PERF_SEL_ICACHE_GCR_INVALIDATE = 0x0000019f,
13547SQC_PERF_SEL_DCACHE_GCR_INVALIDATE = 0x000001a0,
13548SQC_PERF_SEL_DCACHE_GCR_WRITEBACK = 0x000001a1,
13549SQC_PERF_SEL_DUMMY_LAST = 0x000001a2,
13550SP_PERF_SEL_DUMMY_BEGIN = 0x000001c0,
13551SP_PERF_SEL_DUMMY_LAST = 0x000001ff,
13552} SQ_PERF_SEL;
13553
13554/*
13555 * SQ_CAC_POWER_SEL enum
13556 */
13557
13558typedef enum SQ_CAC_POWER_SEL {
13559SQ_CAC_POWER_VALU = 0x00000000,
13560SQ_CAC_POWER_VALU0 = 0x00000001,
13561SQ_CAC_POWER_VALU1 = 0x00000002,
13562SQ_CAC_POWER_VALU2 = 0x00000003,
13563SQ_CAC_POWER_GPR_RD = 0x00000004,
13564SQ_CAC_POWER_GPR_WR = 0x00000005,
13565SQ_CAC_POWER_LDS_BUSY = 0x00000006,
13566SQ_CAC_POWER_ALU_BUSY = 0x00000007,
13567SQ_CAC_POWER_TEX_BUSY = 0x00000008,
13568} SQ_CAC_POWER_SEL;
13569
13570/*
13571 * SQ_IND_CMD_CMD enum
13572 */
13573
13574typedef enum SQ_IND_CMD_CMD {
13575SQ_IND_CMD_CMD_NULL = 0x00000000,
13576SQ_IND_CMD_CMD_SETHALT = 0x00000001,
13577SQ_IND_CMD_CMD_SAVECTX = 0x00000002,
13578SQ_IND_CMD_CMD_KILL = 0x00000003,
13579SQ_IND_CMD_CMD_DEBUG = 0x00000004,
13580SQ_IND_CMD_CMD_TRAP = 0x00000005,
13581SQ_IND_CMD_CMD_SET_SPI_PRIO = 0x00000006,
13582SQ_IND_CMD_CMD_SETFATALHALT = 0x00000007,
13583SQ_IND_CMD_CMD_SINGLE_STEP = 0x00000008,
13584} SQ_IND_CMD_CMD;
13585
13586/*
13587 * SQ_IND_CMD_MODE enum
13588 */
13589
13590typedef enum SQ_IND_CMD_MODE {
13591SQ_IND_CMD_MODE_SINGLE = 0x00000000,
13592SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
13593SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
13594SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
13595SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
13596} SQ_IND_CMD_MODE;
13597
13598/*
13599 * SQ_EDC_INFO_SOURCE enum
13600 */
13601
13602typedef enum SQ_EDC_INFO_SOURCE {
13603SQ_EDC_INFO_SOURCE_INVALID = 0x00000000,
13604SQ_EDC_INFO_SOURCE_INST = 0x00000001,
13605SQ_EDC_INFO_SOURCE_SGPR = 0x00000002,
13606SQ_EDC_INFO_SOURCE_VGPR = 0x00000003,
13607SQ_EDC_INFO_SOURCE_LDS = 0x00000004,
13608SQ_EDC_INFO_SOURCE_GDS = 0x00000005,
13609SQ_EDC_INFO_SOURCE_TA = 0x00000006,
13610} SQ_EDC_INFO_SOURCE;
13611
13612/*
13613 * SQ_ROUND_MODE enum
13614 */
13615
13616typedef enum SQ_ROUND_MODE {
13617SQ_ROUND_NEAREST_EVEN = 0x00000000,
13618SQ_ROUND_PLUS_INFINITY = 0x00000001,
13619SQ_ROUND_MINUS_INFINITY = 0x00000002,
13620SQ_ROUND_TO_ZERO = 0x00000003,
13621} SQ_ROUND_MODE;
13622
13623/*
13624 * SQ_INTERRUPT_WORD_ENCODING enum
13625 */
13626
13627typedef enum SQ_INTERRUPT_WORD_ENCODING {
13628SQ_INTERRUPT_WORD_ENCODING_AUTO = 0x00000000,
13629SQ_INTERRUPT_WORD_ENCODING_INST = 0x00000001,
13630SQ_INTERRUPT_WORD_ENCODING_ERROR = 0x00000002,
13631} SQ_INTERRUPT_WORD_ENCODING;
13632
13633/*
13634 * SQ_IBUF_ST enum
13635 */
13636
13637typedef enum SQ_IBUF_ST {
13638SQ_IBUF_IB_IDLE = 0x00000000,
13639SQ_IBUF_IB_INI_WAIT_GNT = 0x00000001,
13640SQ_IBUF_IB_INI_WAIT_DRET = 0x00000002,
13641SQ_IBUF_IB_LE_4DW = 0x00000003,
13642SQ_IBUF_IB_WAIT_DRET = 0x00000004,
13643SQ_IBUF_IB_EMPTY_WAIT_DRET = 0x00000005,
13644SQ_IBUF_IB_DRET = 0x00000006,
13645SQ_IBUF_IB_EMPTY_WAIT_GNT = 0x00000007,
13646} SQ_IBUF_ST;
13647
13648/*
13649 * SQ_INST_STR_ST enum
13650 */
13651
13652typedef enum SQ_INST_STR_ST {
13653SQ_INST_STR_IB_WAVE_NORML = 0x00000000,
13654SQ_INST_STR_IB_WAVE2ID_NORMAL_INST_AV = 0x00000001,
13655SQ_INST_STR_IB_WAVE_INTERNAL_INST_AV = 0x00000002,
13656SQ_INST_STR_IB_WAVE_INST_SKIP_AV = 0x00000003,
13657SQ_INST_STR_IB_WAVE_SETVSKIP_ST0 = 0x00000004,
13658SQ_INST_STR_IB_WAVE_SETVSKIP_ST1 = 0x00000005,
13659SQ_INST_STR_IB_WAVE_NOP_SLEEP_WAIT = 0x00000006,
13660SQ_INST_STR_IB_WAVE_PC_FROM_SGPR_MSG_WAIT = 0x00000007,
13661} SQ_INST_STR_ST;
13662
13663/*
13664 * SQ_WAVE_IB_ECC_ST enum
13665 */
13666
13667typedef enum SQ_WAVE_IB_ECC_ST {
13668SQ_WAVE_IB_ECC_CLEAN = 0x00000000,
13669SQ_WAVE_IB_ECC_ERR_CONTINUE = 0x00000001,
13670SQ_WAVE_IB_ECC_ERR_HALT = 0x00000002,
13671SQ_WAVE_IB_ECC_WITH_ERR_MSG = 0x00000003,
13672} SQ_WAVE_IB_ECC_ST;
13673
13674/*
13675 * SH_MEM_ADDRESS_MODE enum
13676 */
13677
13678typedef enum SH_MEM_ADDRESS_MODE {
13679SH_MEM_ADDRESS_MODE_64 = 0x00000000,
13680SH_MEM_ADDRESS_MODE_32 = 0x00000001,
13681} SH_MEM_ADDRESS_MODE;
13682
13683/*
13684 * SH_MEM_RETRY_MODE enum
13685 */
13686
13687typedef enum SH_MEM_RETRY_MODE {
13688SH_MEM_RETRY_MODE_ALL = 0x00000000,
13689SH_MEM_RETRY_MODE_WRITEATOMIC = 0x00000001,
13690SH_MEM_RETRY_MODE_NONE = 0x00000002,
13691} SH_MEM_RETRY_MODE;
13692
13693/*
13694 * SH_MEM_ALIGNMENT_MODE enum
13695 */
13696
13697typedef enum SH_MEM_ALIGNMENT_MODE {
13698SH_MEM_ALIGNMENT_MODE_DWORD = 0x00000000,
13699SH_MEM_ALIGNMENT_MODE_DWORD_STRICT = 0x00000001,
13700SH_MEM_ALIGNMENT_MODE_STRICT = 0x00000002,
13701SH_MEM_ALIGNMENT_MODE_UNALIGNED = 0x00000003,
13702} SH_MEM_ALIGNMENT_MODE;
13703
13704/*
13705 * SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT enum
13706 */
13707
13708typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT {
13709SQ_TT_TOKEN_MASK_SQDEC_SHIFT = 0x00000000,
13710SQ_TT_TOKEN_MASK_SHDEC_SHIFT = 0x00000001,
13711SQ_TT_TOKEN_MASK_GFXUDEC_SHIFT = 0x00000002,
13712SQ_TT_TOKEN_MASK_COMP_SHIFT = 0x00000003,
13713SQ_TT_TOKEN_MASK_CONTEXT_SHIFT = 0x00000004,
13714SQ_TT_TOKEN_MASK_CONFIG_SHIFT = 0x00000005,
13715SQ_TT_TOKEN_MASK_OTHER_SHIFT = 0x00000006,
13716SQ_TT_TOKEN_MASK_READS_SHIFT = 0x00000007,
13717} SQ_TT_TOKEN_MASK_REG_INCLUDE_SHIFT;
13718
13719/*
13720 * SQ_TT_TOKEN_MASK_REG_INCLUDE enum
13721 */
13722
13723typedef enum SQ_TT_TOKEN_MASK_REG_INCLUDE {
13724SQ_TT_TOKEN_MASK_SQDEC_BIT = 0x00000001,
13725SQ_TT_TOKEN_MASK_SHDEC_BIT = 0x00000002,
13726SQ_TT_TOKEN_MASK_GFXUDEC_BIT = 0x00000004,
13727SQ_TT_TOKEN_MASK_COMP_BIT = 0x00000008,
13728SQ_TT_TOKEN_MASK_CONTEXT_BIT = 0x00000010,
13729SQ_TT_TOKEN_MASK_CONFIG_BIT = 0x00000020,
13730SQ_TT_TOKEN_MASK_OTHER_BIT = 0x00000040,
13731SQ_TT_TOKEN_MASK_READS_BIT = 0x00000080,
13732} SQ_TT_TOKEN_MASK_REG_INCLUDE;
13733
13734/*
13735 * SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT enum
13736 */
13737
13738typedef enum SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT {
13739SQ_TT_TOKEN_EXCLUDE_VMEMEXEC_SHIFT = 0x00000000,
13740SQ_TT_TOKEN_EXCLUDE_ALUEXEC_SHIFT = 0x00000001,
13741SQ_TT_TOKEN_EXCLUDE_VALUINST_SHIFT = 0x00000002,
13742SQ_TT_TOKEN_EXCLUDE_WAVERDY_SHIFT = 0x00000003,
13743SQ_TT_TOKEN_EXCLUDE_IMMED1_SHIFT = 0x00000004,
13744SQ_TT_TOKEN_EXCLUDE_IMMEDIATE_SHIFT = 0x00000005,
13745SQ_TT_TOKEN_EXCLUDE_REG_SHIFT = 0x00000006,
13746SQ_TT_TOKEN_EXCLUDE_EVENT_SHIFT = 0x00000007,
13747SQ_TT_TOKEN_EXCLUDE_INST_SHIFT = 0x00000008,
13748SQ_TT_TOKEN_EXCLUDE_UTILCTR_SHIFT = 0x00000009,
13749SQ_TT_TOKEN_EXCLUDE_WAVEALLOC_SHIFT = 0x0000000a,
13750SQ_TT_TOKEN_EXCLUDE_PERF_SHIFT = 0x0000000b,
13751} SQ_TT_TOKEN_MASK_TOKEN_EXCLUDE_SHIFT;
13752
13753/*
13754 * SQ_TT_TOKEN_MASK_INST_EXCLUDE enum
13755 */
13756
13757typedef enum SQ_TT_TOKEN_MASK_INST_EXCLUDE {
13758SQ_TT_INST_EXCLUDE_VMEM_OTHER_SIMD = 0x00000000,
13759SQ_TT_INST_EXCLUDE_EXPGNT234 = 0x00000001,
13760} SQ_TT_TOKEN_MASK_INST_EXCLUDE;
13761
13762/*
13763 * SQ_TT_MODE enum
13764 */
13765
13766typedef enum SQ_TT_MODE {
13767SQ_TT_MODE_OFF = 0x00000000,
13768SQ_TT_MODE_ON = 0x00000001,
13769SQ_TT_MODE_GLOBAL = 0x00000002,
13770SQ_TT_MODE_DETAIL = 0x00000003,
13771} SQ_TT_MODE;
13772
13773/*
13774 * SQ_TT_WTYPE_INCLUDE_SHIFT enum
13775 */
13776
13777typedef enum SQ_TT_WTYPE_INCLUDE_SHIFT {
13778SQ_TT_WTYPE_INCLUDE_PS_SHIFT = 0x00000000,
13779SQ_TT_WTYPE_INCLUDE_VS_SHIFT = 0x00000001,
13780SQ_TT_WTYPE_INCLUDE_GS_SHIFT = 0x00000002,
13781SQ_TT_WTYPE_INCLUDE_ES_SHIFT = 0x00000003,
13782SQ_TT_WTYPE_INCLUDE_HS_SHIFT = 0x00000004,
13783SQ_TT_WTYPE_INCLUDE_LS_SHIFT = 0x00000005,
13784SQ_TT_WTYPE_INCLUDE_CS_SHIFT = 0x00000006,
13785} SQ_TT_WTYPE_INCLUDE_SHIFT;
13786
13787/*
13788 * SQ_TT_WTYPE_INCLUDE enum
13789 */
13790
13791typedef enum SQ_TT_WTYPE_INCLUDE {
13792SQ_TT_WTYPE_INCLUDE_PS_BIT = 0x00000001,
13793SQ_TT_WTYPE_INCLUDE_VS_BIT = 0x00000002,
13794SQ_TT_WTYPE_INCLUDE_GS_BIT = 0x00000004,
13795SQ_TT_WTYPE_INCLUDE_ES_BIT = 0x00000008,
13796SQ_TT_WTYPE_INCLUDE_HS_BIT = 0x00000010,
13797SQ_TT_WTYPE_INCLUDE_LS_BIT = 0x00000020,
13798SQ_TT_WTYPE_INCLUDE_CS_BIT = 0x00000040,
13799} SQ_TT_WTYPE_INCLUDE;
13800
13801/*
13802 * SQ_TT_UTIL_TIMER enum
13803 */
13804
13805typedef enum SQ_TT_UTIL_TIMER {
13806SQ_TT_UTIL_TIMER_100_CLK = 0x00000000,
13807SQ_TT_UTIL_TIMER_250_CLK = 0x00000001,
13808} SQ_TT_UTIL_TIMER;
13809
13810/*
13811 * SQ_TT_WAVESTART_MODE enum
13812 */
13813
13814typedef enum SQ_TT_WAVESTART_MODE {
13815SQ_TT_WAVESTART_MODE_SHORT = 0x00000000,
13816SQ_TT_WAVESTART_MODE_ALLOC = 0x00000001,
13817SQ_TT_WAVESTART_MODE_PBB_ID = 0x00000002,
13818} SQ_TT_WAVESTART_MODE;
13819
13820/*
13821 * SQ_TT_RT_FREQ enum
13822 */
13823
13824typedef enum SQ_TT_RT_FREQ {
13825SQ_TT_RT_FREQ_NEVER = 0x00000000,
13826SQ_TT_RT_FREQ_1024_CLK = 0x00000001,
13827SQ_TT_RT_FREQ_4096_CLK = 0x00000002,
13828} SQ_TT_RT_FREQ;
13829
13830/*
13831 * SQ_WATCH_MODES enum
13832 */
13833
13834typedef enum SQ_WATCH_MODES {
13835SQ_WATCH_MODE_READ = 0x00000000,
13836SQ_WATCH_MODE_NONREAD = 0x00000001,
13837SQ_WATCH_MODE_ATOMIC = 0x00000002,
13838SQ_WATCH_MODE_ALL = 0x00000003,
13839} SQ_WATCH_MODES;
13840
13841/*
13842 * SQ_WAVE_SCHED_MODES enum
13843 */
13844
13845typedef enum SQ_WAVE_SCHED_MODES {
13846SQ_WAVE_SCHED_MODE_NORMAL = 0x00000000,
13847SQ_WAVE_SCHED_MODE_EXPERT = 0x00000001,
13848SQ_WAVE_SCHED_MODE_DISABLE_VA_VDST = 0x00000002,
13849} SQ_WAVE_SCHED_MODES;
13850
13851/*
13852 * SQ_WAVE_TYPE value
13853 */
13854
13855#define SQ_WAVE_TYPE_PS0 0x00000000
13856
13857/*
13858 * SQIND_PARTITIONS value
13859 */
13860
13861#define SQIND_GLOBAL_REGS_OFFSET 0x00000000
13862#define SQIND_GLOBAL_REGS_SIZE 0x00000008
13863#define SQIND_LOCAL_REGS_OFFSET 0x00000008
13864#define SQIND_LOCAL_REGS_SIZE 0x00000008
13865#define SQIND_WAVE_HWREGS_OFFSET 0x00000100
13866#define SQIND_WAVE_HWREGS_SIZE 0x00000100
13867#define SQIND_WAVE_SGPRS_OFFSET 0x00000200
13868#define SQIND_WAVE_SGPRS_SIZE 0x00000200
13869#define SQIND_WAVE_VGPRS_OFFSET 0x00000400
13870#define SQIND_WAVE_VGPRS_SIZE 0x00000400
13871
13872/*
13873 * SQ_GFXDEC value
13874 */
13875
13876#define SQ_GFXDEC_BEGIN 0x0000a000
13877#define SQ_GFXDEC_END 0x0000c000
13878#define SQ_GFXDEC_STATE_ID_SHIFT 0x0000000a
13879
13880/*
13881 * SQDEC value
13882 */
13883
13884#define SQDEC_BEGIN 0x00002300
13885#define SQDEC_END 0x000023ff
13886
13887/*
13888 * SQPERFSDEC value
13889 */
13890
13891#define SQPERFSDEC_BEGIN 0x0000d9c0
13892#define SQPERFSDEC_END 0x0000da40
13893
13894/*
13895 * SQPERFDDEC value
13896 */
13897
13898#define SQPERFDDEC_BEGIN 0x0000d1c0
13899#define SQPERFDDEC_END 0x0000d240
13900
13901/*
13902 * SQGFXUDEC value
13903 */
13904
13905#define SQGFXUDEC_BEGIN 0x0000c330
13906#define SQGFXUDEC_END 0x0000c380
13907
13908/*
13909 * SQPWRDEC value
13910 */
13911
13912#define SQPWRDEC_BEGIN 0x0000f08c
13913#define SQPWRDEC_END 0x0000f094
13914
13915/*
13916 * SQ_DISPATCHER value
13917 */
13918
13919#define SQ_DISPATCHER_GFX_MIN 0x00000010
13920#define SQ_DISPATCHER_GFX_CNT_PER_RING 0x00000008
13921
13922/*
13923 * SQ_MAX value
13924 */
13925
13926#define SQ_MAX_PGM_SGPRS 0x00000068
13927#define SQ_MAX_PGM_VGPRS 0x00000100
13928
13929/*
13930 * SQ_EXCP_BITS value
13931 */
13932
13933#define SQ_EX_MODE_EXCP_VALU_BASE 0x00000000
13934#define SQ_EX_MODE_EXCP_VALU_SIZE 0x00000007
13935#define SQ_EX_MODE_EXCP_INVALID 0x00000000
13936#define SQ_EX_MODE_EXCP_INPUT_DENORM 0x00000001
13937#define SQ_EX_MODE_EXCP_DIV0 0x00000002
13938#define SQ_EX_MODE_EXCP_OVERFLOW 0x00000003
13939#define SQ_EX_MODE_EXCP_UNDERFLOW 0x00000004
13940#define SQ_EX_MODE_EXCP_INEXACT 0x00000005
13941#define SQ_EX_MODE_EXCP_INT_DIV0 0x00000006
13942#define SQ_EX_MODE_EXCP_ADDR_WATCH0 0x00000007
13943#define SQ_EX_MODE_EXCP_MEM_VIOL 0x00000008
13944
13945/*
13946 * SQ_EXCP_HI_BITS value
13947 */
13948
13949#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH1 0x00000000
13950#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH2 0x00000001
13951#define SQ_EX_MODE_EXCP_HI_ADDR_WATCH3 0x00000002
13952
13953/*
13954 * HW_INSERTED_INST_ID value
13955 */
13956
13957#define INST_ID_PRIV_START 0x80000000
13958#define INST_ID_ECC_INTERRUPT_MSG 0xfffffff0
13959#define INST_ID_TTRACE_NEW_PC_MSG 0xfffffff1
13960#define INST_ID_HW_TRAP 0xfffffff2
13961#define INST_ID_KILL_SEQ 0xfffffff3
13962#define INST_ID_SPI_WREXEC 0xfffffff4
13963#define INST_ID_HOST_REG_TRAP_MSG 0xfffffffe
13964
13965/*
13966 * SIMM16_WAITCNT_PARTITIONS value
13967 */
13968
13969#define SIMM16_WAITCNT_VM_CNT_START 0x00000000
13970#define SIMM16_WAITCNT_VM_CNT_SIZE 0x00000004
13971#define SIMM16_WAITCNT_EXP_CNT_START 0x00000004
13972#define SIMM16_WAITCNT_EXP_CNT_SIZE 0x00000003
13973#define SIMM16_WAITCNT_LGKM_CNT_START 0x00000008
13974#define SIMM16_WAITCNT_LGKM_CNT_SIZE 0x00000004
13975#define SIMM16_WAITCNT_VM_CNT_HI_START 0x0000000e
13976#define SIMM16_WAITCNT_VM_CNT_HI_SIZE 0x00000002
13977#define SIMM16_WAITCNT_DEPCTR_SA_SDST_START 0x00000000
13978#define SIMM16_WAITCNT_DEPCTR_SA_SDST_SIZE 0x00000001
13979#define SIMM16_WAITCNT_DEPCTR_VA_VCC_START 0x00000001
13980#define SIMM16_WAITCNT_DEPCTR_VA_VCC_SIZE 0x00000001
13981#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_START 0x00000002
13982#define SIMM16_WAITCNT_DEPCTR_VM_VSRC_SIZE 0x00000003
13983#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_START 0x00000008
13984#define SIMM16_WAITCNT_DEPCTR_VA_SSRC_SIZE 0x00000001
13985#define SIMM16_WAITCNT_DEPCTR_VA_SDST_START 0x00000009
13986#define SIMM16_WAITCNT_DEPCTR_VA_SDST_SIZE 0x00000003
13987#define SIMM16_WAITCNT_DEPCTR_VA_VDST_START 0x0000000c
13988#define SIMM16_WAITCNT_DEPCTR_VA_VDST_SIZE 0x00000004
13989
13990/*
13991 * SQ_EDC_FUE_CNTL_BITS value
13992 */
13993
13994#define SQ_EDC_FUE_CNTL_SIMD0 0x00000000
13995#define SQ_EDC_FUE_CNTL_SIMD1 0x00000001
13996#define SQ_EDC_FUE_CNTL_SIMD2 0x00000002
13997#define SQ_EDC_FUE_CNTL_SIMD3 0x00000003
13998#define SQ_EDC_FUE_CNTL_SQ 0x00000004
13999#define SQ_EDC_FUE_CNTL_LDS 0x00000005
14000#define SQ_EDC_FUE_CNTL_TD 0x00000006
14001#define SQ_EDC_FUE_CNTL_TA 0x00000007
14002#define SQ_EDC_FUE_CNTL_TCP 0x00000008
14003
14004/*******************************************************
14005 * COMP Enums
14006 *******************************************************/
14007
14008/*
14009 * CSDATA_TYPE enum
14010 */
14011
14012typedef enum CSDATA_TYPE {
14013CSDATA_TYPE_TG = 0x00000000,
14014CSDATA_TYPE_STATE = 0x00000001,
14015CSDATA_TYPE_EVENT = 0x00000002,
14016CSDATA_TYPE_PRIVATE = 0x00000003,
14017} CSDATA_TYPE;
14018
14019/*
14020 * CSCNTL_TYPE enum
14021 */
14022
14023typedef enum CSCNTL_TYPE {
14024CSCNTL_TYPE_TG = 0x00000000,
14025CSCNTL_TYPE_STATE = 0x00000001,
14026CSCNTL_TYPE_EVENT = 0x00000002,
14027CSCNTL_TYPE_PRIVATE = 0x00000003,
14028} CSCNTL_TYPE;
14029
14030/*
14031 * CSDATA_TYPE_WIDTH value
14032 */
14033
14034#define CSDATA_TYPE_WIDTH 0x00000002
14035
14036/*
14037 * CSDATA_ADDR_WIDTH value
14038 */
14039
14040#define CSDATA_ADDR_WIDTH 0x00000007
14041
14042/*
14043 * CSDATA_DATA_WIDTH value
14044 */
14045
14046#define CSDATA_DATA_WIDTH 0x00000020
14047
14048/*
14049 * CSCNTL_TYPE_WIDTH value
14050 */
14051
14052#define CSCNTL_TYPE_WIDTH 0x00000002
14053
14054/*
14055 * CSCNTL_ADDR_WIDTH value
14056 */
14057
14058#define CSCNTL_ADDR_WIDTH 0x00000007
14059
14060/*
14061 * CSCNTL_DATA_WIDTH value
14062 */
14063
14064#define CSCNTL_DATA_WIDTH 0x00000020
14065
14066/*******************************************************
14067 * GE Enums
14068 *******************************************************/
14069
14070/*
14071 * VGT_OUT_PRIM_TYPE enum
14072 */
14073
14074typedef enum VGT_OUT_PRIM_TYPE {
14075VGT_OUT_POINT = 0x00000000,
14076VGT_OUT_LINE = 0x00000001,
14077VGT_OUT_TRI = 0x00000002,
14078VGT_OUT_RECT_V0 = 0x00000003,
14079VGT_OUT_RECT_V1 = 0x00000004,
14080VGT_OUT_RECT_V2 = 0x00000005,
14081VGT_OUT_RECT_V3 = 0x00000006,
14082VGT_OUT_2D_RECT = 0x00000007,
14083VGT_TE_QUAD = 0x00000008,
14084VGT_TE_PRIM_INDEX_LINE = 0x00000009,
14085VGT_TE_PRIM_INDEX_TRI = 0x0000000a,
14086VGT_TE_PRIM_INDEX_QUAD = 0x0000000b,
14087VGT_OUT_LINE_ADJ = 0x0000000c,
14088VGT_OUT_TRI_ADJ = 0x0000000d,
14089VGT_OUT_PATCH = 0x0000000e,
14090} VGT_OUT_PRIM_TYPE;
14091
14092/*
14093 * VGT_DI_PRIM_TYPE enum
14094 */
14095
14096typedef enum VGT_DI_PRIM_TYPE {
14097DI_PT_NONE = 0x00000000,
14098DI_PT_POINTLIST = 0x00000001,
14099DI_PT_LINELIST = 0x00000002,
14100DI_PT_LINESTRIP = 0x00000003,
14101DI_PT_TRILIST = 0x00000004,
14102DI_PT_TRIFAN = 0x00000005,
14103DI_PT_TRISTRIP = 0x00000006,
14104DI_PT_2D_RECTANGLE = 0x00000007,
14105DI_PT_UNUSED_1 = 0x00000008,
14106DI_PT_PATCH = 0x00000009,
14107DI_PT_LINELIST_ADJ = 0x0000000a,
14108DI_PT_LINESTRIP_ADJ = 0x0000000b,
14109DI_PT_TRILIST_ADJ = 0x0000000c,
14110DI_PT_TRISTRIP_ADJ = 0x0000000d,
14111DI_PT_UNUSED_3 = 0x0000000e,
14112DI_PT_UNUSED_4 = 0x0000000f,
14113DI_PT_TRI_WITH_WFLAGS = 0x00000010,
14114DI_PT_RECTLIST = 0x00000011,
14115DI_PT_LINELOOP = 0x00000012,
14116DI_PT_QUADLIST = 0x00000013,
14117DI_PT_QUADSTRIP = 0x00000014,
14118DI_PT_POLYGON = 0x00000015,
14119} VGT_DI_PRIM_TYPE;
14120
14121/*
14122 * VGT_DI_SOURCE_SELECT enum
14123 */
14124
14125typedef enum VGT_DI_SOURCE_SELECT {
14126DI_SRC_SEL_DMA = 0x00000000,
14127DI_SRC_SEL_IMMEDIATE = 0x00000001,
14128DI_SRC_SEL_AUTO_INDEX = 0x00000002,
14129DI_SRC_SEL_RESERVED = 0x00000003,
14130} VGT_DI_SOURCE_SELECT;
14131
14132/*
14133 * VGT_DI_MAJOR_MODE_SELECT enum
14134 */
14135
14136typedef enum VGT_DI_MAJOR_MODE_SELECT {
14137DI_MAJOR_MODE_0 = 0x00000000,
14138DI_MAJOR_MODE_1 = 0x00000001,
14139} VGT_DI_MAJOR_MODE_SELECT;
14140
14141/*
14142 * VGT_DI_INDEX_SIZE enum
14143 */
14144
14145typedef enum VGT_DI_INDEX_SIZE {
14146DI_INDEX_SIZE_16_BIT = 0x00000000,
14147DI_INDEX_SIZE_32_BIT = 0x00000001,
14148DI_INDEX_SIZE_8_BIT = 0x00000002,
14149} VGT_DI_INDEX_SIZE;
14150
14151/*
14152 * VGT_EVENT_TYPE enum
14153 */
14154
14155typedef enum VGT_EVENT_TYPE {
14156Reserved_0x00 = 0x00000000,
14157SAMPLE_STREAMOUTSTATS1 = 0x00000001,
14158SAMPLE_STREAMOUTSTATS2 = 0x00000002,
14159SAMPLE_STREAMOUTSTATS3 = 0x00000003,
14160CACHE_FLUSH_TS = 0x00000004,
14161CONTEXT_DONE = 0x00000005,
14162CACHE_FLUSH = 0x00000006,
14163CS_PARTIAL_FLUSH = 0x00000007,
14164VGT_STREAMOUT_SYNC = 0x00000008,
14165SET_FE_ID = 0x00000009,
14166VGT_STREAMOUT_RESET = 0x0000000a,
14167END_OF_PIPE_INCR_DE = 0x0000000b,
14168END_OF_PIPE_IB_END = 0x0000000c,
14169RST_PIX_CNT = 0x0000000d,
14170BREAK_BATCH = 0x0000000e,
14171VS_PARTIAL_FLUSH = 0x0000000f,
14172PS_PARTIAL_FLUSH = 0x00000010,
14173FLUSH_HS_OUTPUT = 0x00000011,
14174FLUSH_DFSM = 0x00000012,
14175RESET_TO_LOWEST_VGT = 0x00000013,
14176CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000014,
14177ZPASS_DONE = 0x00000015,
14178CACHE_FLUSH_AND_INV_EVENT = 0x00000016,
14179PERFCOUNTER_START = 0x00000017,
14180PERFCOUNTER_STOP = 0x00000018,
14181PIPELINESTAT_START = 0x00000019,
14182PIPELINESTAT_STOP = 0x0000001a,
14183PERFCOUNTER_SAMPLE = 0x0000001b,
14184FLUSH_ES_OUTPUT = 0x0000001c,
14185BIN_CONF_OVERRIDE_CHECK = 0x0000001d,
14186SAMPLE_PIPELINESTAT = 0x0000001e,
14187SO_VGTSTREAMOUT_FLUSH = 0x0000001f,
14188SAMPLE_STREAMOUTSTATS = 0x00000020,
14189RESET_VTX_CNT = 0x00000021,
14190BLOCK_CONTEXT_DONE = 0x00000022,
14191CS_CONTEXT_DONE = 0x00000023,
14192VGT_FLUSH = 0x00000024,
14193TGID_ROLLOVER = 0x00000025,
14194SQ_NON_EVENT = 0x00000026,
14195SC_SEND_DB_VPZ = 0x00000027,
14196BOTTOM_OF_PIPE_TS = 0x00000028,
14197FLUSH_SX_TS = 0x00000029,
14198DB_CACHE_FLUSH_AND_INV = 0x0000002a,
14199FLUSH_AND_INV_DB_DATA_TS = 0x0000002b,
14200FLUSH_AND_INV_DB_META = 0x0000002c,
14201FLUSH_AND_INV_CB_DATA_TS = 0x0000002d,
14202FLUSH_AND_INV_CB_META = 0x0000002e,
14203CS_DONE = 0x0000002f,
14204PS_DONE = 0x00000030,
14205FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000031,
14206SX_CB_RAT_ACK_REQUEST = 0x00000032,
14207THREAD_TRACE_START = 0x00000033,
14208THREAD_TRACE_STOP = 0x00000034,
14209THREAD_TRACE_MARKER = 0x00000035,
14210THREAD_TRACE_DRAW = 0x00000036,
14211THREAD_TRACE_FINISH = 0x00000037,
14212PIXEL_PIPE_STAT_CONTROL = 0x00000038,
14213PIXEL_PIPE_STAT_DUMP = 0x00000039,
14214PIXEL_PIPE_STAT_RESET = 0x0000003a,
14215CONTEXT_SUSPEND = 0x0000003b,
14216OFFCHIP_HS_DEALLOC = 0x0000003c,
14217ENABLE_NGG_PIPELINE = 0x0000003d,
14218ENABLE_LEGACY_PIPELINE = 0x0000003e,
14219DRAW_DONE = 0x0000003f,
14220} VGT_EVENT_TYPE;
14221
14222/*
14223 * VGT_DMA_SWAP_MODE enum
14224 */
14225
14226typedef enum VGT_DMA_SWAP_MODE {
14227VGT_DMA_SWAP_NONE = 0x00000000,
14228VGT_DMA_SWAP_16_BIT = 0x00000001,
14229VGT_DMA_SWAP_32_BIT = 0x00000002,
14230VGT_DMA_SWAP_WORD = 0x00000003,
14231} VGT_DMA_SWAP_MODE;
14232
14233/*
14234 * VGT_INDEX_TYPE_MODE enum
14235 */
14236
14237typedef enum VGT_INDEX_TYPE_MODE {
14238VGT_INDEX_16 = 0x00000000,
14239VGT_INDEX_32 = 0x00000001,
14240VGT_INDEX_8 = 0x00000002,
14241} VGT_INDEX_TYPE_MODE;
14242
14243/*
14244 * VGT_DMA_BUF_TYPE enum
14245 */
14246
14247typedef enum VGT_DMA_BUF_TYPE {
14248VGT_DMA_BUF_MEM = 0x00000000,
14249VGT_DMA_BUF_RING = 0x00000001,
14250VGT_DMA_BUF_SETUP = 0x00000002,
14251VGT_DMA_PTR_UPDATE = 0x00000003,
14252} VGT_DMA_BUF_TYPE;
14253
14254/*
14255 * VGT_OUTPATH_SELECT enum
14256 */
14257
14258typedef enum VGT_OUTPATH_SELECT {
14259VGT_OUTPATH_VTX_REUSE = 0x00000000,
14260VGT_OUTPATH_GS_BLOCK = 0x00000001,
14261VGT_OUTPATH_HS_BLOCK = 0x00000002,
14262VGT_OUTPATH_PRIM_GEN = 0x00000003,
14263VGT_OUTPATH_TE_PRIM_GEN = 0x00000004,
14264VGT_OUTPATH_TE_GS_BLOCK = 0x00000005,
14265VGT_OUTPATH_TE_OUTPUT = 0x00000006,
14266} VGT_OUTPATH_SELECT;
14267
14268/*
14269 * VGT_GRP_PRIM_TYPE enum
14270 */
14271
14272typedef enum VGT_GRP_PRIM_TYPE {
14273VGT_GRP_3D_POINT = 0x00000000,
14274VGT_GRP_3D_LINE = 0x00000001,
14275VGT_GRP_3D_TRI = 0x00000002,
14276VGT_GRP_3D_RECT = 0x00000003,
14277VGT_GRP_3D_QUAD = 0x00000004,
14278VGT_GRP_2D_COPY_RECT_V0 = 0x00000005,
14279VGT_GRP_2D_COPY_RECT_V1 = 0x00000006,
14280VGT_GRP_2D_COPY_RECT_V2 = 0x00000007,
14281VGT_GRP_2D_COPY_RECT_V3 = 0x00000008,
14282VGT_GRP_2D_FILL_RECT = 0x00000009,
14283VGT_GRP_2D_LINE = 0x0000000a,
14284VGT_GRP_2D_TRI = 0x0000000b,
14285VGT_GRP_PRIM_INDEX_LINE = 0x0000000c,
14286VGT_GRP_PRIM_INDEX_TRI = 0x0000000d,
14287VGT_GRP_PRIM_INDEX_QUAD = 0x0000000e,
14288VGT_GRP_3D_LINE_ADJ = 0x0000000f,
14289VGT_GRP_3D_TRI_ADJ = 0x00000010,
14290VGT_GRP_3D_PATCH = 0x00000011,
14291VGT_GRP_2D_RECT = 0x00000012,
14292} VGT_GRP_PRIM_TYPE;
14293
14294/*
14295 * VGT_GRP_PRIM_ORDER enum
14296 */
14297
14298typedef enum VGT_GRP_PRIM_ORDER {
14299VGT_GRP_LIST = 0x00000000,
14300VGT_GRP_STRIP = 0x00000001,
14301VGT_GRP_FAN = 0x00000002,
14302VGT_GRP_LOOP = 0x00000003,
14303VGT_GRP_POLYGON = 0x00000004,
14304} VGT_GRP_PRIM_ORDER;
14305
14306/*
14307 * VGT_GROUP_CONV_SEL enum
14308 */
14309
14310typedef enum VGT_GROUP_CONV_SEL {
14311VGT_GRP_INDEX_16 = 0x00000000,
14312VGT_GRP_INDEX_32 = 0x00000001,
14313VGT_GRP_UINT_16 = 0x00000002,
14314VGT_GRP_UINT_32 = 0x00000003,
14315VGT_GRP_SINT_16 = 0x00000004,
14316VGT_GRP_SINT_32 = 0x00000005,
14317VGT_GRP_FLOAT_32 = 0x00000006,
14318VGT_GRP_AUTO_PRIM = 0x00000007,
14319VGT_GRP_FIX_1_23_TO_FLOAT = 0x00000008,
14320} VGT_GROUP_CONV_SEL;
14321
14322/*
14323 * VGT_GS_MODE_TYPE enum
14324 */
14325
14326typedef enum VGT_GS_MODE_TYPE {
14327GS_OFF = 0x00000000,
14328GS_SCENARIO_A = 0x00000001,
14329GS_SCENARIO_B = 0x00000002,
14330GS_SCENARIO_G = 0x00000003,
14331GS_SCENARIO_C = 0x00000004,
14332SPRITE_EN = 0x00000005,
14333} VGT_GS_MODE_TYPE;
14334
14335/*
14336 * VGT_GS_CUT_MODE enum
14337 */
14338
14339typedef enum VGT_GS_CUT_MODE {
14340GS_CUT_1024 = 0x00000000,
14341GS_CUT_512 = 0x00000001,
14342GS_CUT_256 = 0x00000002,
14343GS_CUT_128 = 0x00000003,
14344} VGT_GS_CUT_MODE;
14345
14346/*
14347 * VGT_GS_OUTPRIM_TYPE enum
14348 */
14349
14350typedef enum VGT_GS_OUTPRIM_TYPE {
14351POINTLIST = 0x00000000,
14352LINESTRIP = 0x00000001,
14353TRISTRIP = 0x00000002,
14354RECTLIST = 0x00000003,
14355} VGT_GS_OUTPRIM_TYPE;
14356
14357/*
14358 * VGT_CACHE_INVALID_MODE enum
14359 */
14360
14361typedef enum VGT_CACHE_INVALID_MODE {
14362VC_ONLY = 0x00000000,
14363TC_ONLY = 0x00000001,
14364VC_AND_TC = 0x00000002,
14365} VGT_CACHE_INVALID_MODE;
14366
14367/*
14368 * VGT_TESS_TYPE enum
14369 */
14370
14371typedef enum VGT_TESS_TYPE {
14372TESS_ISOLINE = 0x00000000,
14373TESS_TRIANGLE = 0x00000001,
14374TESS_QUAD = 0x00000002,
14375} VGT_TESS_TYPE;
14376
14377/*
14378 * VGT_TESS_PARTITION enum
14379 */
14380
14381typedef enum VGT_TESS_PARTITION {
14382PART_INTEGER = 0x00000000,
14383PART_POW2 = 0x00000001,
14384PART_FRAC_ODD = 0x00000002,
14385PART_FRAC_EVEN = 0x00000003,
14386} VGT_TESS_PARTITION;
14387
14388/*
14389 * VGT_TESS_TOPOLOGY enum
14390 */
14391
14392typedef enum VGT_TESS_TOPOLOGY {
14393OUTPUT_POINT = 0x00000000,
14394OUTPUT_LINE = 0x00000001,
14395OUTPUT_TRIANGLE_CW = 0x00000002,
14396OUTPUT_TRIANGLE_CCW = 0x00000003,
14397} VGT_TESS_TOPOLOGY;
14398
14399/*
14400 * VGT_RDREQ_POLICY enum
14401 */
14402
14403typedef enum VGT_RDREQ_POLICY {
14404VGT_POLICY_LRU = 0x00000000,
14405VGT_POLICY_STREAM = 0x00000001,
14406VGT_POLICY_BYPASS = 0x00000002,
14407} VGT_RDREQ_POLICY;
14408
14409/*
14410 * VGT_DIST_MODE enum
14411 */
14412
14413typedef enum VGT_DIST_MODE {
14414NO_DIST = 0x00000000,
14415PATCHES = 0x00000001,
14416DONUTS = 0x00000002,
14417TRAPEZOIDS = 0x00000003,
14418} VGT_DIST_MODE;
14419
14420/*
14421 * VGT_DETECT_ONE enum
14422 */
14423
14424typedef enum VGT_DETECT_ONE {
14425PRE_CLAMP_TF1 = 0x00000000,
14426POST_CLAMP_TF1 = 0x00000001,
14427DISABLE_TF1 = 0x00000002,
14428} VGT_DETECT_ONE;
14429
14430/*
14431 * VGT_DETECT_ZERO enum
14432 */
14433
14434typedef enum VGT_DETECT_ZERO {
14435PRE_CLAMP_TF0 = 0x00000000,
14436POST_CLAMP_TF0 = 0x00000001,
14437DISABLE_TF0 = 0x00000002,
14438} VGT_DETECT_ZERO;
14439
14440/*
14441 * VGT_STAGES_LS_EN enum
14442 */
14443
14444typedef enum VGT_STAGES_LS_EN {
14445LS_STAGE_OFF = 0x00000000,
14446LS_STAGE_ON = 0x00000001,
14447CS_STAGE_ON = 0x00000002,
14448RESERVED_LS = 0x00000003,
14449} VGT_STAGES_LS_EN;
14450
14451/*
14452 * VGT_STAGES_HS_EN enum
14453 */
14454
14455typedef enum VGT_STAGES_HS_EN {
14456HS_STAGE_OFF = 0x00000000,
14457HS_STAGE_ON = 0x00000001,
14458} VGT_STAGES_HS_EN;
14459
14460/*
14461 * VGT_STAGES_ES_EN enum
14462 */
14463
14464typedef enum VGT_STAGES_ES_EN {
14465ES_STAGE_OFF = 0x00000000,
14466ES_STAGE_DS = 0x00000001,
14467ES_STAGE_REAL = 0x00000002,
14468RESERVED_ES = 0x00000003,
14469} VGT_STAGES_ES_EN;
14470
14471/*
14472 * VGT_STAGES_GS_EN enum
14473 */
14474
14475typedef enum VGT_STAGES_GS_EN {
14476GS_STAGE_OFF = 0x00000000,
14477GS_STAGE_ON = 0x00000001,
14478} VGT_STAGES_GS_EN;
14479
14480/*
14481 * VGT_STAGES_VS_EN enum
14482 */
14483
14484typedef enum VGT_STAGES_VS_EN {
14485VS_STAGE_REAL = 0x00000000,
14486VS_STAGE_DS = 0x00000001,
14487VS_STAGE_COPY_SHADER = 0x00000002,
14488RESERVED_VS = 0x00000003,
14489} VGT_STAGES_VS_EN;
14490
14491/*
14492 * GE_PERFCOUNT_SELECT enum
14493 */
14494
14495typedef enum GE_PERFCOUNT_SELECT {
14496ge_assembler_busy = 0x00000000,
14497ge_assembler_stalled = 0x00000001,
14498ge_cm_reading_stalled = 0x00000002,
14499ge_cm_stalled_by_gog = 0x00000003,
14500ge_cm_stalled_by_gsfetch_done = 0x00000004,
14501ge_dma_busy = 0x00000005,
14502ge_dma_lat_bin_0 = 0x00000006,
14503ge_dma_lat_bin_1 = 0x00000007,
14504ge_dma_lat_bin_2 = 0x00000008,
14505ge_dma_lat_bin_3 = 0x00000009,
14506ge_dma_lat_bin_4 = 0x0000000a,
14507ge_dma_lat_bin_5 = 0x0000000b,
14508ge_dma_lat_bin_6 = 0x0000000c,
14509ge_dma_lat_bin_7 = 0x0000000d,
14510ge_dma_return = 0x0000000e,
14511ge_dma_utcl1_consecutive_retry_event = 0x0000000f,
14512ge_dma_utcl1_request_event = 0x00000010,
14513ge_dma_utcl1_retry_event = 0x00000011,
14514ge_dma_utcl1_stall_event = 0x00000012,
14515ge_dma_utcl1_stall_utcl2_event = 0x00000013,
14516ge_dma_utcl1_translation_hit_event = 0x00000014,
14517ge_dma_utcl1_translation_miss_event = 0x00000015,
14518ge_dma_utcl2_stall_on_trans = 0x00000016,
14519ge_dma_utcl2_trans_ack = 0x00000017,
14520ge_dma_utcl2_trans_xnack = 0x00000018,
14521ge_ds_cache_hits = 0x00000019,
14522ge_ds_prims = 0x0000001a,
14523ge_es_done = 0x0000001b,
14524ge_es_done_latency = 0x0000001c,
14525ge_es_flush = 0x0000001d,
14526ge_es_ring_high_water_mark = 0x0000001e,
14527ge_es_thread_groups = 0x0000001f,
14528ge_esthread_stalled_es_rb_full = 0x00000020,
14529ge_esthread_stalled_spi_bp = 0x00000021,
14530ge_esvert_stalled_es_tbl = 0x00000022,
14531ge_esvert_stalled_gs_event = 0x00000023,
14532ge_esvert_stalled_gs_tbl = 0x00000024,
14533ge_esvert_stalled_gsprim = 0x00000025,
14534ge_gea_dma_starved = 0x00000026,
14535ge_gog_busy = 0x00000027,
14536ge_gog_out_indx_stalled = 0x00000028,
14537ge_gog_out_prim_stalled = 0x00000029,
14538ge_gog_vs_tbl_stalled = 0x0000002a,
14539ge_gs_cache_hits = 0x0000002b,
14540ge_gs_counters_avail_stalled = 0x0000002c,
14541ge_gs_done = 0x0000002d,
14542ge_gs_done_latency = 0x0000002e,
14543ge_gs_event_stall = 0x0000002f,
14544ge_gs_issue_rtr_stalled = 0x00000030,
14545ge_gs_rb_space_avail_stalled = 0x00000031,
14546ge_gs_ring_high_water_mark = 0x00000032,
14547ge_gsprim_stalled_es_tbl = 0x00000033,
14548ge_gsprim_stalled_esvert = 0x00000034,
14549ge_gsprim_stalled_gs_event = 0x00000035,
14550ge_gsprim_stalled_gs_tbl = 0x00000036,
14551ge_gsthread_stalled = 0x00000037,
14552ge_hs_done = 0x00000038,
14553ge_hs_done_latency = 0x00000039,
14554ge_hs_done_se0 = 0x0000003a,
14555ge_hs_done_se1 = 0x0000003b,
14556ge_hs_done_se2_reserved = 0x0000003c,
14557ge_hs_done_se3_reserved = 0x0000003d,
14558ge_hs_tfm_stall = 0x0000003e,
14559ge_hs_tgs_active_high_water_mark = 0x0000003f,
14560ge_hs_thread_groups = 0x00000040,
14561ge_inside_tf_bin_0 = 0x00000041,
14562ge_inside_tf_bin_1 = 0x00000042,
14563ge_inside_tf_bin_2 = 0x00000043,
14564ge_inside_tf_bin_3 = 0x00000044,
14565ge_inside_tf_bin_4 = 0x00000045,
14566ge_inside_tf_bin_5 = 0x00000046,
14567ge_inside_tf_bin_6 = 0x00000047,
14568ge_inside_tf_bin_7 = 0x00000048,
14569ge_inside_tf_bin_8 = 0x00000049,
14570ge_ls_done = 0x0000004a,
14571ge_ls_done_latency = 0x0000004b,
14572ge_null_patch = 0x0000004c,
14573ge_pa_clipp_eop = 0x0000004d,
14574ge_pa_clipp_is_event = 0x0000004e,
14575ge_pa_clipp_new_vtx_vect = 0x0000004f,
14576ge_pa_clipp_null_prim = 0x00000050,
14577ge_pa_clipp_send = 0x00000051,
14578ge_pa_clipp_send_not_event = 0x00000052,
14579ge_pa_clipp_stalled = 0x00000053,
14580ge_pa_clipp_starved_busy = 0x00000054,
14581ge_pa_clipp_starved_idle = 0x00000055,
14582ge_pa_clipp_valid_prim = 0x00000056,
14583ge_pa_clips_send = 0x00000057,
14584ge_pa_clips_stalled = 0x00000058,
14585ge_pa_clipv_send = 0x00000059,
14586ge_pa_clipv_stalled = 0x0000005a,
14587ge_rbiu_di_fifo_stalled = 0x0000005b,
14588ge_rbiu_di_fifo_starved = 0x0000005c,
14589ge_rbiu_dr_fifo_stalled = 0x0000005d,
14590ge_rbiu_dr_fifo_starved = 0x0000005e,
14591ge_reused_es_indices = 0x0000005f,
14592ge_reused_vs_indices = 0x00000060,
14593ge_sclk_core_vld = 0x00000061,
14594ge_sclk_gs_vld = 0x00000062,
14595ge_sclk_input_vld = 0x00000063,
14596ge_sclk_leg_gs_arb_vld = 0x00000064,
14597ge_sclk_ngg_vld = 0x00000065,
14598ge_sclk_reg_vld = 0x00000066,
14599ge_sclk_te11_vld = 0x00000067,
14600ge_sclk_vr_vld = 0x00000068,
14601ge_sclk_wd_te11_vld = 0x00000069,
14602ge_spi_esvert_eov = 0x0000006a,
14603ge_spi_esvert_stalled = 0x0000006b,
14604ge_spi_esvert_starved_busy = 0x0000006c,
14605ge_spi_esvert_valid = 0x0000006d,
14606ge_spi_eswave_is_event = 0x0000006e,
14607ge_spi_eswave_send = 0x0000006f,
14608ge_spi_gsprim_cont = 0x00000070,
14609ge_spi_gsprim_eov = 0x00000071,
14610ge_spi_gsprim_stalled = 0x00000072,
14611ge_spi_gsprim_starved_busy = 0x00000073,
14612ge_spi_gsprim_starved_idle = 0x00000074,
14613ge_spi_gsprim_valid = 0x00000075,
14614ge_spi_gssubgrp_is_event = 0x00000076,
14615ge_spi_gssubgrp_send = 0x00000077,
14616ge_spi_gswave_is_event = 0x00000078,
14617ge_spi_gswave_send = 0x00000079,
14618ge_spi_hsvert_eov = 0x0000007a,
14619ge_spi_hsvert_stalled = 0x0000007b,
14620ge_spi_hsvert_starved_busy = 0x0000007c,
14621ge_spi_hsvert_valid = 0x0000007d,
14622ge_spi_hswave_is_event = 0x0000007e,
14623ge_spi_hswave_send = 0x0000007f,
14624ge_spi_lsvert_eov = 0x00000080,
14625ge_spi_lsvert_stalled = 0x00000081,
14626ge_spi_lsvert_starved_busy = 0x00000082,
14627ge_spi_lsvert_starved_idle = 0x00000083,
14628ge_spi_lsvert_valid = 0x00000084,
14629ge_spi_lswave_is_event = 0x00000085,
14630ge_spi_lswave_send = 0x00000086,
14631ge_spi_vsvert_eov = 0x00000087,
14632ge_spi_vsvert_send = 0x00000088,
14633ge_spi_vsvert_stalled = 0x00000089,
14634ge_spi_vsvert_starved_busy = 0x0000008a,
14635ge_spi_vsvert_starved_idle = 0x0000008b,
14636ge_spi_vswave_is_event = 0x0000008c,
14637ge_spi_vswave_send = 0x0000008d,
14638ge_starved_on_hs_done = 0x0000008e,
14639ge_stat_busy = 0x0000008f,
14640ge_stat_combined_busy = 0x00000090,
14641ge_stat_no_dma_busy = 0x00000091,
14642ge_strmout_stalled = 0x00000092,
14643ge_te11_busy = 0x00000093,
14644ge_te11_starved = 0x00000094,
14645ge_tfreq_lat_bin_0 = 0x00000095,
14646ge_tfreq_lat_bin_1 = 0x00000096,
14647ge_tfreq_lat_bin_2 = 0x00000097,
14648ge_tfreq_lat_bin_3 = 0x00000098,
14649ge_tfreq_lat_bin_4 = 0x00000099,
14650ge_tfreq_lat_bin_5 = 0x0000009a,
14651ge_tfreq_lat_bin_6 = 0x0000009b,
14652ge_tfreq_lat_bin_7 = 0x0000009c,
14653ge_tfreq_utcl1_consecutive_retry_event = 0x0000009d,
14654ge_tfreq_utcl1_request_event = 0x0000009e,
14655ge_tfreq_utcl1_retry_event = 0x0000009f,
14656ge_tfreq_utcl1_stall_event = 0x000000a0,
14657ge_tfreq_utcl1_stall_utcl2_event = 0x000000a1,
14658ge_tfreq_utcl1_translation_hit_event = 0x000000a2,
14659ge_tfreq_utcl1_translation_miss_event = 0x000000a3,
14660ge_tfreq_utcl2_stall_on_trans = 0x000000a4,
14661ge_tfreq_utcl2_trans_ack = 0x000000a5,
14662ge_tfreq_utcl2_trans_xnack = 0x000000a6,
14663ge_vs_cache_hits = 0x000000a7,
14664ge_vs_done = 0x000000a8,
14665ge_vs_pc_stall = 0x000000a9,
14666ge_vs_table_high_water_mark = 0x000000aa,
14667ge_vs_thread_groups = 0x000000ab,
14668ge_vsvert_api_send = 0x000000ac,
14669ge_vsvert_ds_send = 0x000000ad,
14670ge_wait_for_es_done_stalled = 0x000000ae,
14671ge_waveid_stalled = 0x000000af,
14672} GE_PERFCOUNT_SELECT;
14673
14674/*
14675 * WD_IA_DRAW_TYPE enum
14676 */
14677
14678typedef enum WD_IA_DRAW_TYPE {
14679WD_IA_DRAW_TYPE_DI_MM0 = 0x00000000,
14680WD_IA_DRAW_TYPE_REG_XFER = 0x00000001,
14681WD_IA_DRAW_TYPE_EVENT_INIT = 0x00000002,
14682WD_IA_DRAW_TYPE_EVENT_ADDR = 0x00000003,
14683WD_IA_DRAW_TYPE_MIN_INDX = 0x00000004,
14684WD_IA_DRAW_TYPE_MAX_INDX = 0x00000005,
14685WD_IA_DRAW_TYPE_INDX_OFF = 0x00000006,
14686WD_IA_DRAW_TYPE_IMM_DATA = 0x00000007,
14687} WD_IA_DRAW_TYPE;
14688
14689/*
14690 * WD_IA_DRAW_REG_XFER enum
14691 */
14692
14693typedef enum WD_IA_DRAW_REG_XFER {
14694WD_IA_DRAW_REG_XFER_IA_MULTI_VGT_PARAM = 0x00000000,
14695WD_IA_DRAW_REG_XFER_VGT_MULTI_PRIM_IB_RESET_EN = 0x00000001,
14696WD_IA_DRAW_REG_XFER_VGT_INSTANCE_BASE_ID = 0x00000002,
14697WD_IA_DRAW_REG_XFER_GE_CNTL = 0x00000003,
14698} WD_IA_DRAW_REG_XFER;
14699
14700/*
14701 * WD_IA_DRAW_SOURCE enum
14702 */
14703
14704typedef enum WD_IA_DRAW_SOURCE {
14705WD_IA_DRAW_SOURCE_DMA = 0x00000000,
14706WD_IA_DRAW_SOURCE_IMMD = 0x00000001,
14707WD_IA_DRAW_SOURCE_AUTO = 0x00000002,
14708WD_IA_DRAW_SOURCE_OPAQ = 0x00000003,
14709} WD_IA_DRAW_SOURCE;
14710
14711/*
14712 * GS_THREADID_SIZE value
14713 */
14714
14715#define GSTHREADID_SIZE 0x00000002
14716
14717/*******************************************************
14718 * GB Enums
14719 *******************************************************/
14720
14721/*
14722 * GB_EDC_DED_MODE enum
14723 */
14724
14725typedef enum GB_EDC_DED_MODE {
14726GB_EDC_DED_MODE_LOG = 0x00000000,
14727GB_EDC_DED_MODE_HALT = 0x00000001,
14728GB_EDC_DED_MODE_INT_HALT = 0x00000002,
14729} GB_EDC_DED_MODE;
14730
14731/*******************************************************
14732 * GLX Enums
14733 *******************************************************/
14734
14735/*
14736 * CHA_PERF_SEL enum
14737 */
14738
14739typedef enum CHA_PERF_SEL {
14740CHA_PERF_SEL_BUSY = 0x00000000,
14741CHA_PERF_SEL_STALL_CHC0 = 0x00000001,
14742CHA_PERF_SEL_STALL_CHC1 = 0x00000002,
14743CHA_PERF_SEL_STALL_CHC2 = 0x00000003,
14744CHA_PERF_SEL_STALL_CHC3 = 0x00000004,
14745CHA_PERF_SEL_STALL_CHC4 = 0x00000005,
14746CHA_PERF_SEL_REQUEST_CHC0 = 0x00000006,
14747CHA_PERF_SEL_REQUEST_CHC1 = 0x00000007,
14748CHA_PERF_SEL_REQUEST_CHC2 = 0x00000008,
14749CHA_PERF_SEL_REQUEST_CHC3 = 0x00000009,
14750CHA_PERF_SEL_REQUEST_CHC4 = 0x0000000a,
14751CHA_PERF_SEL_REQUEST_CHC5 = 0x0000000b,
14752CHA_PERF_SEL_MEM_32B_WDS_CHC0 = 0x0000000c,
14753CHA_PERF_SEL_MEM_32B_WDS_CHC1 = 0x0000000d,
14754CHA_PERF_SEL_MEM_32B_WDS_CHC2 = 0x0000000e,
14755CHA_PERF_SEL_MEM_32B_WDS_CHC3 = 0x0000000f,
14756CHA_PERF_SEL_MEM_32B_WDS_CHC4 = 0x00000010,
14757CHA_PERF_SEL_IO_32B_WDS_CHC0 = 0x00000011,
14758CHA_PERF_SEL_IO_32B_WDS_CHC1 = 0x00000012,
14759CHA_PERF_SEL_IO_32B_WDS_CHC2 = 0x00000013,
14760CHA_PERF_SEL_IO_32B_WDS_CHC3 = 0x00000014,
14761CHA_PERF_SEL_IO_32B_WDS_CHC4 = 0x00000015,
14762CHA_PERF_SEL_MEM_BURST_COUNT_CHC0 = 0x00000016,
14763CHA_PERF_SEL_MEM_BURST_COUNT_CHC1 = 0x00000017,
14764CHA_PERF_SEL_MEM_BURST_COUNT_CHC2 = 0x00000018,
14765CHA_PERF_SEL_MEM_BURST_COUNT_CHC3 = 0x00000019,
14766CHA_PERF_SEL_MEM_BURST_COUNT_CHC4 = 0x0000001a,
14767CHA_PERF_SEL_IO_BURST_COUNT_CHC0 = 0x0000001b,
14768CHA_PERF_SEL_IO_BURST_COUNT_CHC1 = 0x0000001c,
14769CHA_PERF_SEL_IO_BURST_COUNT_CHC2 = 0x0000001d,
14770CHA_PERF_SEL_IO_BURST_COUNT_CHC3 = 0x0000001e,
14771CHA_PERF_SEL_IO_BURST_COUNT_CHC4 = 0x0000001f,
14772CHA_PERF_SEL_ARB_REQUESTS = 0x00000020,
14773CHA_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000021,
14774CHA_PERF_SEL_STALL_RET_CONFLICT_CHC0 = 0x00000022,
14775CHA_PERF_SEL_STALL_RET_CONFLICT_CHC1 = 0x00000023,
14776CHA_PERF_SEL_STALL_RET_CONFLICT_CHC2 = 0x00000024,
14777CHA_PERF_SEL_STALL_RET_CONFLICT_CHC3 = 0x00000025,
14778CHA_PERF_SEL_STALL_RET_CONFLICT_CHC4 = 0x00000026,
14779CHA_PERF_SEL_CYCLE = 0x00000027,
14780} CHA_PERF_SEL;
14781
14782/*
14783 * CHC_PERF_SEL enum
14784 */
14785
14786typedef enum CHC_PERF_SEL {
14787CHC_PERF_SEL_GATE_EN1 = 0x00000000,
14788CHC_PERF_SEL_GATE_EN2 = 0x00000001,
14789CHC_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002,
14790CHC_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 0x00000003,
14791CHC_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 0x00000004,
14792CHC_PERF_SEL_CYCLE = 0x00000005,
14793CHC_PERF_SEL_REQ = 0x00000006,
14794} CHC_PERF_SEL;
14795
14796/*
14797 * CHCG_PERF_SEL enum
14798 */
14799
14800typedef enum CHCG_PERF_SEL {
14801CHCG_PERF_SEL_GATE_EN1 = 0x00000000,
14802CHCG_PERF_SEL_GATE_EN2 = 0x00000001,
14803CHCG_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002,
14804CHCG_PERF_SEL_TA_CHC_ADDR_STARVE_CYCLES = 0x00000003,
14805CHCG_PERF_SEL_TA_CHC_DATA_STARVE_CYCLES = 0x00000004,
14806CHCG_PERF_SEL_CYCLE = 0x00000005,
14807CHCG_PERF_SEL_REQ = 0x00000006,
14808} CHCG_PERF_SEL;
14809
14810/*
14811 * GL1A_PERF_SEL enum
14812 */
14813
14814typedef enum GL1A_PERF_SEL {
14815GL1A_PERF_SEL_BUSY = 0x00000000,
14816GL1A_PERF_SEL_STALL_GL1C0 = 0x00000001,
14817GL1A_PERF_SEL_STALL_GL1C1 = 0x00000002,
14818GL1A_PERF_SEL_STALL_GL1C2 = 0x00000003,
14819GL1A_PERF_SEL_STALL_GL1C3 = 0x00000004,
14820GL1A_PERF_SEL_STALL_GL1C4 = 0x00000005,
14821GL1A_PERF_SEL_REQUEST_GL1C0 = 0x00000006,
14822GL1A_PERF_SEL_REQUEST_GL1C1 = 0x00000007,
14823GL1A_PERF_SEL_REQUEST_GL1C2 = 0x00000008,
14824GL1A_PERF_SEL_REQUEST_GL1C3 = 0x00000009,
14825GL1A_PERF_SEL_REQUEST_GL1C4 = 0x0000000a,
14826GL1A_PERF_SEL_MEM_32B_WDS_GL1C0 = 0x0000000b,
14827GL1A_PERF_SEL_MEM_32B_WDS_GL1C1 = 0x0000000c,
14828GL1A_PERF_SEL_MEM_32B_WDS_GL1C2 = 0x0000000d,
14829GL1A_PERF_SEL_MEM_32B_WDS_GL1C3 = 0x0000000e,
14830GL1A_PERF_SEL_MEM_32B_WDS_GL1C4 = 0x0000000f,
14831GL1A_PERF_SEL_IO_32B_WDS_GL1C0 = 0x00000010,
14832GL1A_PERF_SEL_IO_32B_WDS_GL1C1 = 0x00000011,
14833GL1A_PERF_SEL_IO_32B_WDS_GL1C2 = 0x00000012,
14834GL1A_PERF_SEL_IO_32B_WDS_GL1C3 = 0x00000013,
14835GL1A_PERF_SEL_IO_32B_WDS_GL1C4 = 0x00000014,
14836GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C0 = 0x00000015,
14837GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C1 = 0x00000016,
14838GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C2 = 0x00000017,
14839GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C3 = 0x00000018,
14840GL1A_PERF_SEL_MEM_BURST_COUNT_GL1C4 = 0x00000019,
14841GL1A_PERF_SEL_IO_BURST_COUNT_GL1C0 = 0x0000001a,
14842GL1A_PERF_SEL_IO_BURST_COUNT_GL1C1 = 0x0000001b,
14843GL1A_PERF_SEL_IO_BURST_COUNT_GL1C2 = 0x0000001c,
14844GL1A_PERF_SEL_IO_BURST_COUNT_GL1C3 = 0x0000001d,
14845GL1A_PERF_SEL_IO_BURST_COUNT_GL1C4 = 0x0000001e,
14846GL1A_PERF_SEL_ARB_REQUESTS = 0x0000001f,
14847GL1A_PERF_SEL_REQ_INFLIGHT_LEVEL = 0x00000020,
14848GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C0 = 0x00000021,
14849GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C1 = 0x00000022,
14850GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C2 = 0x00000023,
14851GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C3 = 0x00000024,
14852GL1A_PERF_SEL_STALL_RET_CONFLICT_GL1C4 = 0x00000025,
14853GL1A_PERF_SEL_CYCLE = 0x00000026,
14854} GL1A_PERF_SEL;
14855
14856/*
14857 * GL1C_PERF_SEL enum
14858 */
14859
14860typedef enum GL1C_PERF_SEL {
14861GL1C_PERF_SEL_GATE_EN1 = 0x00000000,
14862GL1C_PERF_SEL_GATE_EN2 = 0x00000001,
14863GL1C_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002,
14864GL1C_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 0x00000003,
14865GL1C_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 0x00000004,
14866GL1C_PERF_SEL_CYCLE = 0x00000005,
14867GL1C_PERF_SEL_REQ = 0x00000006,
14868} GL1C_PERF_SEL;
14869
14870/*
14871 * GL1CG_PERF_SEL enum
14872 */
14873
14874typedef enum GL1CG_PERF_SEL {
14875GL1CG_PERF_SEL_GATE_EN1 = 0x00000000,
14876GL1CG_PERF_SEL_GATE_EN2 = 0x00000001,
14877GL1CG_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002,
14878GL1CG_PERF_SEL_TA_GL1C_ADDR_STARVE_CYCLES = 0x00000003,
14879GL1CG_PERF_SEL_TA_GL1C_DATA_STARVE_CYCLES = 0x00000004,
14880GL1CG_PERF_SEL_CYCLE = 0x00000005,
14881GL1CG_PERF_SEL_REQ = 0x00000006,
14882} GL1CG_PERF_SEL;
14883
14884/*******************************************************
14885 * TP Enums
14886 *******************************************************/
14887
14888/*
14889 * TA_TC_REQ_MODES enum
14890 */
14891
14892typedef enum TA_TC_REQ_MODES {
14893TA_TC_REQ_MODE_BORDER = 0x00000000,
14894TA_TC_REQ_MODE_TEX2 = 0x00000001,
14895TA_TC_REQ_MODE_TEX1 = 0x00000002,
14896TA_TC_REQ_MODE_TEX0 = 0x00000003,
14897TA_TC_REQ_MODE_NORMAL = 0x00000004,
14898TA_TC_REQ_MODE_DWORD = 0x00000005,
14899TA_TC_REQ_MODE_BYTE = 0x00000006,
14900TA_TC_REQ_MODE_BYTE_NV = 0x00000007,
14901} TA_TC_REQ_MODES;
14902
14903/*
14904 * TA_TC_ADDR_MODES enum
14905 */
14906
14907typedef enum TA_TC_ADDR_MODES {
14908TA_TC_ADDR_MODE_DEFAULT = 0x00000000,
14909TA_TC_ADDR_MODE_COMP0 = 0x00000001,
14910TA_TC_ADDR_MODE_COMP1 = 0x00000002,
14911TA_TC_ADDR_MODE_COMP2 = 0x00000003,
14912TA_TC_ADDR_MODE_COMP3 = 0x00000004,
14913TA_TC_ADDR_MODE_UNALIGNED = 0x00000005,
14914TA_TC_ADDR_MODE_BORDER_COLOR = 0x00000006,
14915} TA_TC_ADDR_MODES;
14916
14917/*
14918 * TA_PERFCOUNT_SEL enum
14919 */
14920
14921typedef enum TA_PERFCOUNT_SEL {
14922TA_PERF_SEL_NULL = 0x00000000,
14923TA_PERF_SEL_sh_fifo_busy = 0x00000001,
14924TA_PERF_SEL_sh_fifo_cmd_busy = 0x00000002,
14925TA_PERF_SEL_sh_fifo_addr_busy = 0x00000003,
14926TA_PERF_SEL_sh_fifo_data_busy = 0x00000004,
14927TA_PERF_SEL_sh_fifo_data_sfifo_busy = 0x00000005,
14928TA_PERF_SEL_sh_fifo_data_tfifo_busy = 0x00000006,
14929TA_PERF_SEL_gradient_busy = 0x00000007,
14930TA_PERF_SEL_gradient_fifo_busy = 0x00000008,
14931TA_PERF_SEL_lod_busy = 0x00000009,
14932TA_PERF_SEL_lod_fifo_busy = 0x0000000a,
14933TA_PERF_SEL_addresser_busy = 0x0000000b,
14934TA_PERF_SEL_addresser_fifo_busy = 0x0000000c,
14935TA_PERF_SEL_aligner_busy = 0x0000000d,
14936TA_PERF_SEL_write_path_busy = 0x0000000e,
14937TA_PERF_SEL_ta_busy = 0x0000000f,
14938TA_PERF_SEL_sq_ta_cmd_cycles = 0x00000010,
14939TA_PERF_SEL_sp_ta_addr_cycles = 0x00000011,
14940TA_PERF_SEL_sp_ta_data_cycles = 0x00000012,
14941TA_PERF_SEL_ta_fa_data_state_cycles = 0x00000013,
14942TA_PERF_SEL_sh_fifo_addr_waiting_on_cmd_cycles = 0x00000014,
14943TA_PERF_SEL_sh_fifo_cmd_waiting_on_addr_cycles = 0x00000015,
14944TA_PERF_SEL_sh_fifo_addr_starved_while_busy_cycles = 0x00000016,
14945TA_PERF_SEL_sh_fifo_cmd_starved_while_busy_cycles = 0x00000017,
14946TA_PERF_SEL_sh_fifo_data_waiting_on_data_state_cycles = 0x00000018,
14947TA_PERF_SEL_sh_fifo_data_state_waiting_on_data_cycles = 0x00000019,
14948TA_PERF_SEL_sh_fifo_data_starved_while_busy_cycles = 0x0000001a,
14949TA_PERF_SEL_sh_fifo_data_state_starved_while_busy_cycles = 0x0000001b,
14950TA_PERF_SEL_ta_sh_fifo_starved = 0x0000001c,
14951TA_PERF_SEL_RESERVED_29 = 0x0000001d,
14952TA_PERF_SEL_sh_fifo_addr_cycles = 0x0000001e,
14953TA_PERF_SEL_sh_fifo_data_cycles = 0x0000001f,
14954TA_PERF_SEL_total_wavefronts = 0x00000020,
14955TA_PERF_SEL_gradient_cycles = 0x00000021,
14956TA_PERF_SEL_walker_cycles = 0x00000022,
14957TA_PERF_SEL_aligner_cycles = 0x00000023,
14958TA_PERF_SEL_image_wavefronts = 0x00000024,
14959TA_PERF_SEL_image_read_wavefronts = 0x00000025,
14960TA_PERF_SEL_image_write_wavefronts = 0x00000026,
14961TA_PERF_SEL_image_atomic_wavefronts = 0x00000027,
14962TA_PERF_SEL_image_total_cycles = 0x00000028,
14963TA_PERF_SEL_RESERVED_41 = 0x00000029,
14964TA_PERF_SEL_RESERVED_42 = 0x0000002a,
14965TA_PERF_SEL_RESERVED_43 = 0x0000002b,
14966TA_PERF_SEL_buffer_wavefronts = 0x0000002c,
14967TA_PERF_SEL_buffer_read_wavefronts = 0x0000002d,
14968TA_PERF_SEL_buffer_write_wavefronts = 0x0000002e,
14969TA_PERF_SEL_buffer_atomic_wavefronts = 0x0000002f,
14970TA_PERF_SEL_buffer_coalescable_wavefronts = 0x00000030,
14971TA_PERF_SEL_buffer_total_cycles = 0x00000031,
14972TA_PERF_SEL_buffer_coalescable_addr_multicycled_cycles = 0x00000032,
14973TA_PERF_SEL_buffer_coalescable_clamp_16kdword_multicycled_cycles = 0x00000033,
14974TA_PERF_SEL_buffer_coalesced_read_cycles = 0x00000034,
14975TA_PERF_SEL_buffer_coalesced_write_cycles = 0x00000035,
14976TA_PERF_SEL_addr_stalled_by_tc_cycles = 0x00000036,
14977TA_PERF_SEL_addr_stalled_by_td_cycles = 0x00000037,
14978TA_PERF_SEL_data_stalled_by_tc_cycles = 0x00000038,
14979TA_PERF_SEL_addresser_stalled_by_aligner_only_cycles = 0x00000039,
14980TA_PERF_SEL_addresser_stalled_cycles = 0x0000003a,
14981TA_PERF_SEL_aniso_stalled_by_addresser_only_cycles = 0x0000003b,
14982TA_PERF_SEL_aniso_stalled_cycles = 0x0000003c,
14983TA_PERF_SEL_deriv_stalled_by_aniso_only_cycles = 0x0000003d,
14984TA_PERF_SEL_deriv_stalled_cycles = 0x0000003e,
14985TA_PERF_SEL_aniso_gt1_cycle_quads = 0x0000003f,
14986TA_PERF_SEL_color_1_cycle_pixels = 0x00000040,
14987TA_PERF_SEL_color_2_cycle_pixels = 0x00000041,
14988TA_PERF_SEL_color_3_cycle_pixels = 0x00000042,
14989TA_PERF_SEL_color_4_cycle_pixels = 0x00000043,
14990TA_PERF_SEL_mip_1_cycle_pixels = 0x00000044,
14991TA_PERF_SEL_mip_2_cycle_pixels = 0x00000045,
14992TA_PERF_SEL_vol_1_cycle_pixels = 0x00000046,
14993TA_PERF_SEL_vol_2_cycle_pixels = 0x00000047,
14994TA_PERF_SEL_bilin_point_1_cycle_pixels = 0x00000048,
14995TA_PERF_SEL_mipmap_lod_0_samples = 0x00000049,
14996TA_PERF_SEL_mipmap_lod_1_samples = 0x0000004a,
14997TA_PERF_SEL_mipmap_lod_2_samples = 0x0000004b,
14998TA_PERF_SEL_mipmap_lod_3_samples = 0x0000004c,
14999TA_PERF_SEL_mipmap_lod_4_samples = 0x0000004d,
15000TA_PERF_SEL_mipmap_lod_5_samples = 0x0000004e,
15001TA_PERF_SEL_mipmap_lod_6_samples = 0x0000004f,
15002TA_PERF_SEL_mipmap_lod_7_samples = 0x00000050,
15003TA_PERF_SEL_mipmap_lod_8_samples = 0x00000051,
15004TA_PERF_SEL_mipmap_lod_9_samples = 0x00000052,
15005TA_PERF_SEL_mipmap_lod_10_samples = 0x00000053,
15006TA_PERF_SEL_mipmap_lod_11_samples = 0x00000054,
15007TA_PERF_SEL_mipmap_lod_12_samples = 0x00000055,
15008TA_PERF_SEL_mipmap_lod_13_samples = 0x00000056,
15009TA_PERF_SEL_mipmap_lod_14_samples = 0x00000057,
15010TA_PERF_SEL_mipmap_invalid_samples = 0x00000058,
15011TA_PERF_SEL_aniso_1_cycle_quads = 0x00000059,
15012TA_PERF_SEL_aniso_2_cycle_quads = 0x0000005a,
15013TA_PERF_SEL_aniso_4_cycle_quads = 0x0000005b,
15014TA_PERF_SEL_aniso_6_cycle_quads = 0x0000005c,
15015TA_PERF_SEL_aniso_8_cycle_quads = 0x0000005d,
15016TA_PERF_SEL_aniso_10_cycle_quads = 0x0000005e,
15017TA_PERF_SEL_aniso_12_cycle_quads = 0x0000005f,
15018TA_PERF_SEL_aniso_14_cycle_quads = 0x00000060,
15019TA_PERF_SEL_aniso_16_cycle_quads = 0x00000061,
15020TA_PERF_SEL_write_path_input_cycles = 0x00000062,
15021TA_PERF_SEL_write_path_output_cycles = 0x00000063,
15022TA_PERF_SEL_flat_wavefronts = 0x00000064,
15023TA_PERF_SEL_flat_read_wavefronts = 0x00000065,
15024TA_PERF_SEL_flat_write_wavefronts = 0x00000066,
15025TA_PERF_SEL_flat_atomic_wavefronts = 0x00000067,
15026TA_PERF_SEL_flat_coalesceable_wavefronts = 0x00000068,
15027TA_PERF_SEL_reg_sclk_vld = 0x00000069,
15028TA_PERF_SEL_local_cg_dyn_sclk_grp0_en = 0x0000006a,
15029TA_PERF_SEL_local_cg_dyn_sclk_grp1_en = 0x0000006b,
15030TA_PERF_SEL_local_cg_dyn_sclk_grp1_mems_en = 0x0000006c,
15031TA_PERF_SEL_local_cg_dyn_sclk_grp4_en = 0x0000006d,
15032TA_PERF_SEL_local_cg_dyn_sclk_grp5_en = 0x0000006e,
15033TA_PERF_SEL_xnack_on_phase0 = 0x0000006f,
15034TA_PERF_SEL_xnack_on_phase1 = 0x00000070,
15035TA_PERF_SEL_xnack_on_phase2 = 0x00000071,
15036TA_PERF_SEL_xnack_on_phase3 = 0x00000072,
15037TA_PERF_SEL_first_xnack_on_phase0 = 0x00000073,
15038TA_PERF_SEL_first_xnack_on_phase1 = 0x00000074,
15039TA_PERF_SEL_first_xnack_on_phase2 = 0x00000075,
15040TA_PERF_SEL_first_xnack_on_phase3 = 0x00000076,
15041} TA_PERFCOUNT_SEL;
15042
15043/*
15044 * TD_PERFCOUNT_SEL enum
15045 */
15046
15047typedef enum TD_PERFCOUNT_SEL {
15048TD_PERF_SEL_none = 0x00000000,
15049TD_PERF_SEL_td_busy = 0x00000001,
15050TD_PERF_SEL_input_busy = 0x00000002,
15051TD_PERF_SEL_sampler_lerp_busy = 0x00000003,
15052TD_PERF_SEL_sampler_out_busy = 0x00000004,
15053TD_PERF_SEL_nofilter_busy = 0x00000005,
15054TD_PERF_SEL_sampler_sclk_on_nofilter_sclk_off = 0x00000006,
15055TD_PERF_SEL_nofilter_sclk_on_sampler_sclk_off = 0x00000007,
15056TD_PERF_SEL_RESERVED_8 = 0x00000008,
15057TD_PERF_SEL_core_state_rams_read = 0x00000009,
15058TD_PERF_SEL_weight_data_rams_read = 0x0000000a,
15059TD_PERF_SEL_reference_data_rams_read = 0x0000000b,
15060TD_PERF_SEL_tc_td_data_fifo_full = 0x0000000c,
15061TD_PERF_SEL_tc_td_ram_fifo_full = 0x0000000d,
15062TD_PERF_SEL_input_state_fifo_full = 0x0000000e,
15063TD_PERF_SEL_ta_data_stall = 0x0000000f,
15064TD_PERF_SEL_tc_data_stall = 0x00000010,
15065TD_PERF_SEL_tc_ram_stall = 0x00000011,
15066TD_PERF_SEL_lds_stall = 0x00000012,
15067TD_PERF_SEL_sampler_pkr_full = 0x00000013,
15068TD_PERF_SEL_nofilter_pkr_full = 0x00000014,
15069TD_PERF_SEL_RESERVED_21 = 0x00000015,
15070TD_PERF_SEL_gather4_wavefront = 0x00000016,
15071TD_PERF_SEL_gather4h_wavefront = 0x00000017,
15072TD_PERF_SEL_gather4h_packed_wavefront = 0x00000018,
15073TD_PERF_SEL_gather8h_packed_wavefront = 0x00000019,
15074TD_PERF_SEL_sample_c_wavefront = 0x0000001a,
15075TD_PERF_SEL_load_wavefront = 0x0000001b,
15076TD_PERF_SEL_store_wavefront = 0x0000001c,
15077TD_PERF_SEL_ldfptr_wavefront = 0x0000001d,
15078TD_PERF_SEL_write_ack_wavefront = 0x0000001e,
15079TD_PERF_SEL_d16_en_wavefront = 0x0000001f,
15080TD_PERF_SEL_bypassLerp_wavefront = 0x00000020,
15081TD_PERF_SEL_min_max_filter_wavefront = 0x00000021,
15082TD_PERF_SEL_one_comp_wavefront = 0x00000022,
15083TD_PERF_SEL_two_comp_wavefront = 0x00000023,
15084TD_PERF_SEL_three_comp_wavefront = 0x00000024,
15085TD_PERF_SEL_four_comp_wavefront = 0x00000025,
15086TD_PERF_SEL_user_defined_border = 0x00000026,
15087TD_PERF_SEL_white_border = 0x00000027,
15088TD_PERF_SEL_opaque_black_border = 0x00000028,
15089TD_PERF_SEL_lod_warn_from_ta = 0x00000029,
15090TD_PERF_SEL_wavefront_dest_is_lds = 0x0000002a,
15091TD_PERF_SEL_td_cycling_of_nofilter_instr = 0x0000002b,
15092TD_PERF_SEL_tc_cycling_of_nofilter_instr = 0x0000002c,
15093TD_PERF_SEL_out_of_order_instr = 0x0000002d,
15094TD_PERF_SEL_total_num_instr = 0x0000002e,
15095TD_PERF_SEL_mixmode_instruction = 0x0000002f,
15096TD_PERF_SEL_mixmode_resource = 0x00000030,
15097TD_PERF_SEL_status_packet = 0x00000031,
15098TD_PERF_SEL_address_cmd_poison = 0x00000032,
15099TD_PERF_SEL_data_poison = 0x00000033,
15100TD_PERF_SEL_done_scoreboard_not_empty = 0x00000034,
15101TD_PERF_SEL_done_scoreboard_is_full = 0x00000035,
15102TD_PERF_SEL_done_scoreboard_bp_due_to_ooo = 0x00000036,
15103TD_PERF_SEL_done_scoreboard_bp_due_to_lds = 0x00000037,
15104TD_PERF_SEL_nofilter_formatters_turned_off = 0x00000038,
15105TD_PERF_SEL_nofilter_popcount_dmask_gt_num_comp_of_fmt = 0x00000039,
15106TD_PERF_SEL_nofilter_popcount_dmask_lt_num_comp_of_fmt = 0x0000003a,
15107} TD_PERFCOUNT_SEL;
15108
15109/*
15110 * TCP_PERFCOUNT_SELECT enum
15111 */
15112
15113typedef enum TCP_PERFCOUNT_SELECT {
15114TCP_PERF_SEL_GATE_EN1 = 0x00000000,
15115TCP_PERF_SEL_GATE_EN2 = 0x00000001,
15116TCP_PERF_SEL_CORE_REG_SCLK_VLD = 0x00000002,
15117TCP_PERF_SEL_TA_TCP_ADDR_STARVE_CYCLES = 0x00000003,
15118TCP_PERF_SEL_TA_TCP_DATA_STARVE_CYCLES = 0x00000004,
15119TCP_PERF_SEL_TCP_TA_ADDR_STALL_CYCLES = 0x00000005,
15120TCP_PERF_SEL_TCP_TA_DATA_STALL_CYCLES = 0x00000006,
15121TCP_PERF_SEL_TD_TCP_STALL_CYCLES = 0x00000007,
15122TCP_PERF_SEL_TCR_TCP_STALL_CYCLES = 0x00000008,
15123TCP_PERF_SEL_TCP_TCR_STARVE_CYCLES = 0x00000009,
15124TCP_PERF_SEL_LOD_STALL_CYCLES = 0x0000000a,
15125TCP_PERF_SEL_READ_TAGCONFLICT_STALL_CYCLES = 0x0000000b,
15126TCP_PERF_SEL_WRITE_TAGCONFLICT_STALL_CYCLES = 0x0000000c,
15127TCP_PERF_SEL_ATOMIC_TAGCONFLICT_STALL_CYCLES = 0x0000000d,
15128TCP_PERF_SEL_ALLOC_STALL_CYCLES = 0x0000000e,
15129TCP_PERF_SEL_UNORDERED_MTYPE_STALL = 0x0000000f,
15130TCP_PERF_SEL_LFIFO_STALL_CYCLES = 0x00000010,
15131TCP_PERF_SEL_RFIFO_STALL_CYCLES = 0x00000011,
15132TCP_PERF_SEL_TCR_RDRET_STALL = 0x00000012,
15133TCP_PERF_SEL_WRITE_CONFLICT_STALL = 0x00000013,
15134TCP_PERF_SEL_HOLE_READ_STALL = 0x00000014,
15135TCP_PERF_SEL_READCONFLICT_STALL_CYCLES = 0x00000015,
15136TCP_PERF_SEL_PENDING_STALL_CYCLES = 0x00000016,
15137TCP_PERF_SEL_READFIFO_STALL_CYCLES = 0x00000017,
15138TCP_PERF_SEL_POWER_STALL = 0x00000018,
15139TCP_PERF_SEL_UTCL0_SERIALIZATION_STALL = 0x00000019,
15140TCP_PERF_SEL_TC_TA_XNACK_STALL = 0x0000001a,
15141TCP_PERF_SEL_TA_TCP_STATE_READ = 0x0000001b,
15142TCP_PERF_SEL_TOTAL_ACCESSES = 0x0000001c,
15143TCP_PERF_SEL_TOTAL_READ = 0x0000001d,
15144TCP_PERF_SEL_TOTAL_NON_READ = 0x0000001e,
15145TCP_PERF_SEL_TOTAL_WRITE = 0x0000001f,
15146TCP_PERF_SEL_TOTAL_HIT_LRU_READ = 0x00000020,
15147TCP_PERF_SEL_TOTAL_MISS_LRU_READ = 0x00000021,
15148TCP_PERF_SEL_TOTAL_MISS_EVICT_READ = 0x00000022,
15149TCP_PERF_SEL_TOTAL_MISS_LRU_WRITE = 0x00000023,
15150TCP_PERF_SEL_TOTAL_MISS_EVICT_WRITE = 0x00000024,
15151TCP_PERF_SEL_TOTAL_ATOMIC_WITH_RET = 0x00000025,
15152TCP_PERF_SEL_TOTAL_ATOMIC_WITHOUT_RET = 0x00000026,
15153TCP_PERF_SEL_TOTAL_WBINVL1 = 0x00000027,
15154TCP_PERF_SEL_CP_TCP_INVALIDATE = 0x00000028,
15155TCP_PERF_SEL_TOTAL_WRITEBACK_INVALIDATES = 0x00000029,
15156TCP_PERF_SEL_SHOOTDOWN = 0x0000002a,
15157TCP_PERF_SEL_UTCL0_REQUEST = 0x0000002b,
15158TCP_PERF_SEL_UTCL0_TRANSLATION_MISS = 0x0000002c,
15159TCP_PERF_SEL_UTCL0_TRANSLATION_HIT = 0x0000002d,
15160TCP_PERF_SEL_UTCL0_PERMISSION_MISS = 0x0000002e,
15161TCP_PERF_SEL_UTCL0_STALL_INFLIGHT_MAX = 0x0000002f,
15162TCP_PERF_SEL_UTCL0_STALL_LRU_INFLIGHT = 0x00000030,
15163TCP_PERF_SEL_UTCL0_STALL_MULTI_MISS = 0x00000031,
15164TCP_PERF_SEL_UTCL0_LFIFO_FULL = 0x00000032,
15165TCP_PERF_SEL_UTCL0_STALL_LFIFO_NOT_RES = 0x00000033,
15166TCP_PERF_SEL_UTCL0_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000034,
15167TCP_PERF_SEL_CLIENT_UTCL0_INFLIGHT = 0x00000035,
15168TCP_PERF_SEL_UTCL0_UTCL2_INFLIGHT = 0x00000036,
15169TCP_PERF_SEL_UTCL0_STALL_MISSFIFO_FULL = 0x00000037,
15170TCP_PERF_SEL_TOTAL_CACHE_ACCESSES = 0x00000038,
15171TCP_PERF_SEL_TAGRAM0_REQ = 0x00000039,
15172TCP_PERF_SEL_TAGRAM1_REQ = 0x0000003a,
15173TCP_PERF_SEL_TAGRAM2_REQ = 0x0000003b,
15174TCP_PERF_SEL_TAGRAM3_REQ = 0x0000003c,
15175TCP_PERF_SEL_TCP_LATENCY = 0x0000003d,
15176TCP_PERF_SEL_TCC_READ_REQ_LATENCY = 0x0000003e,
15177TCP_PERF_SEL_TCC_WRITE_REQ_LATENCY = 0x0000003f,
15178TCP_PERF_SEL_TCC_WRITE_REQ_HOLE_LATENCY = 0x00000040,
15179TCP_PERF_SEL_TCC_READ_REQ = 0x00000041,
15180TCP_PERF_SEL_TCC_WRITE_REQ = 0x00000042,
15181TCP_PERF_SEL_TCC_ATOMIC_WITH_RET_REQ = 0x00000043,
15182TCP_PERF_SEL_TCC_ATOMIC_WITHOUT_RET_REQ = 0x00000044,
15183TCP_PERF_SEL_TCC_LRU_REQ = 0x00000045,
15184TCP_PERF_SEL_TCC_STREAM_REQ = 0x00000046,
15185TCP_PERF_SEL_TCC_NC_READ_REQ = 0x00000047,
15186TCP_PERF_SEL_TCC_NC_WRITE_REQ = 0x00000048,
15187TCP_PERF_SEL_TCC_NC_ATOMIC_REQ = 0x00000049,
15188TCP_PERF_SEL_TCC_UC_READ_REQ = 0x0000004a,
15189TCP_PERF_SEL_TCC_UC_WRITE_REQ = 0x0000004b,
15190TCP_PERF_SEL_TCC_UC_ATOMIC_REQ = 0x0000004c,
15191TCP_PERF_SEL_TCC_CC_READ_REQ = 0x0000004d,
15192TCP_PERF_SEL_TCC_CC_WRITE_REQ = 0x0000004e,
15193TCP_PERF_SEL_TCC_CC_ATOMIC_REQ = 0x0000004f,
15194TCP_PERF_SEL_TCC_DCC_REQ = 0x00000050,
15195TCP_PERF_SEL_GL1_REQ_ATOMIC_WITH_RET = 0x00000051,
15196TCP_PERF_SEL_GL1_REQ_ATOMIC_WITHOUT_RET = 0x00000052,
15197TCP_PERF_SEL_GL1_REQ_READ = 0x00000053,
15198TCP_PERF_SEL_GL1_REQ_READ_LATENCY = 0x00000054,
15199TCP_PERF_SEL_GL1_REQ_WRITE = 0x00000055,
15200TCP_PERF_SEL_GL1_REQ_WRITE_LATENCY = 0x00000056,
15201TCP_PERF_SEL_REQ_MISS_TAGRAM0 = 0x00000057,
15202TCP_PERF_SEL_REQ_MISS_TAGRAM1 = 0x00000058,
15203TCP_PERF_SEL_REQ_MISS_TAGRAM2 = 0x00000059,
15204TCP_PERF_SEL_REQ_MISS_TAGRAM3 = 0x0000005a,
15205TCP_PERF_SEL_TA_REQ = 0x0000005b,
15206TCP_PERF_SEL_TA_REQ_ATOMIC_WITH_RET = 0x0000005c,
15207TCP_PERF_SEL_TA_REQ_ATOMIC_WITHOUT_RET = 0x0000005d,
15208TCP_PERF_SEL_TA_REQ_READ = 0x0000005e,
15209TCP_PERF_SEL_TA_REQ_WRITE = 0x0000005f,
15210TCP_PERF_SEL_TA_REQ_STATE_READ = 0x00000060,
15211} TCP_PERFCOUNT_SELECT;
15212
15213/*
15214 * TCP_CACHE_POLICIES enum
15215 */
15216
15217typedef enum TCP_CACHE_POLICIES {
15218TCP_CACHE_POLICY_MISS_LRU = 0x00000000,
15219TCP_CACHE_POLICY_MISS_EVICT = 0x00000001,
15220TCP_CACHE_POLICY_HIT_LRU = 0x00000002,
15221TCP_CACHE_POLICY_HIT_EVICT = 0x00000003,
15222} TCP_CACHE_POLICIES;
15223
15224/*
15225 * TCP_CACHE_STORE_POLICIES enum
15226 */
15227
15228typedef enum TCP_CACHE_STORE_POLICIES {
15229TCP_CACHE_STORE_POLICY_WT_LRU = 0x00000000,
15230TCP_CACHE_STORE_POLICY_WT_EVICT = 0x00000001,
15231} TCP_CACHE_STORE_POLICIES;
15232
15233/*
15234 * TCP_WATCH_MODES enum
15235 */
15236
15237typedef enum TCP_WATCH_MODES {
15238TCP_WATCH_MODE_READ = 0x00000000,
15239TCP_WATCH_MODE_NONREAD = 0x00000001,
15240TCP_WATCH_MODE_ATOMIC = 0x00000002,
15241TCP_WATCH_MODE_ALL = 0x00000003,
15242} TCP_WATCH_MODES;
15243
15244/*
15245 * TCP_DSM_DATA_SEL enum
15246 */
15247
15248typedef enum TCP_DSM_DATA_SEL {
15249TCP_DSM_DISABLE = 0x00000000,
15250TCP_DSM_SEL0 = 0x00000001,
15251TCP_DSM_SEL1 = 0x00000002,
15252TCP_DSM_SEL_BOTH = 0x00000003,
15253} TCP_DSM_DATA_SEL;
15254
15255/*
15256 * TCP_DSM_SINGLE_WRITE enum
15257 */
15258
15259typedef enum TCP_DSM_SINGLE_WRITE {
15260TCP_DSM_SINGLE_WRITE_DIS = 0x00000000,
15261TCP_DSM_SINGLE_WRITE_EN = 0x00000001,
15262} TCP_DSM_SINGLE_WRITE;
15263
15264/*
15265 * TCP_DSM_INJECT_SEL enum
15266 */
15267
15268typedef enum TCP_DSM_INJECT_SEL {
15269TCP_DSM_INJECT_SEL0 = 0x00000000,
15270TCP_DSM_INJECT_SEL1 = 0x00000001,
15271TCP_DSM_INJECT_SEL2 = 0x00000002,
15272TCP_DSM_INJECT_SEL3 = 0x00000003,
15273} TCP_DSM_INJECT_SEL;
15274
15275/*
15276 * TCP_OPCODE_TYPE enum
15277 */
15278
15279typedef enum TCP_OPCODE_TYPE {
15280TCP_OPCODE_READ = 0x00000000,
15281TCP_OPCODE_WRITE = 0x00000001,
15282TCP_OPCODE_ATOMIC = 0x00000002,
15283TCP_OPCODE_WBINVL1 = 0x00000003,
15284TCP_OPCODE_ATOMIC_CMPSWAP = 0x00000004,
15285TCP_OPCODE_GATHERH = 0x00000005,
15286} TCP_OPCODE_TYPE;
15287
15288/*******************************************************
15289 * GL2C Enums
15290 *******************************************************/
15291
15292/*
15293 * GL2C_PERF_SEL enum
15294 */
15295
15296typedef enum GL2C_PERF_SEL {
15297GL2C_PERF_SEL_NONE = 0x00000000,
15298GL2C_PERF_SEL_CYCLE = 0x00000001,
15299GL2C_PERF_SEL_BUSY = 0x00000002,
15300GL2C_PERF_SEL_REQ = 0x00000003,
15301GL2C_PERF_SEL_VOL_REQ = 0x00000004,
15302GL2C_PERF_SEL_HIGH_PRIORITY_REQ = 0x00000005,
15303GL2C_PERF_SEL_READ = 0x00000006,
15304GL2C_PERF_SEL_WRITE = 0x00000007,
15305GL2C_PERF_SEL_ATOMIC = 0x00000008,
15306GL2C_PERF_SEL_NOP_ACK = 0x00000009,
15307GL2C_PERF_SEL_NOP_RTN0 = 0x0000000a,
15308GL2C_PERF_SEL_PROBE = 0x0000000b,
15309GL2C_PERF_SEL_PROBE_ALL = 0x0000000c,
15310GL2C_PERF_SEL_INTERNAL_PROBE = 0x0000000d,
15311GL2C_PERF_SEL_COMPRESSED_READ_REQ = 0x0000000e,
15312GL2C_PERF_SEL_METADATA_READ_REQ = 0x0000000f,
15313GL2C_PERF_SEL_CLIENT0_REQ = 0x00000010,
15314GL2C_PERF_SEL_CLIENT1_REQ = 0x00000011,
15315GL2C_PERF_SEL_CLIENT2_REQ = 0x00000012,
15316GL2C_PERF_SEL_CLIENT3_REQ = 0x00000013,
15317GL2C_PERF_SEL_CLIENT4_REQ = 0x00000014,
15318GL2C_PERF_SEL_CLIENT5_REQ = 0x00000015,
15319GL2C_PERF_SEL_CLIENT6_REQ = 0x00000016,
15320GL2C_PERF_SEL_CLIENT7_REQ = 0x00000017,
15321GL2C_PERF_SEL_C_RW_S_REQ = 0x00000018,
15322GL2C_PERF_SEL_C_RW_US_REQ = 0x00000019,
15323GL2C_PERF_SEL_C_RO_S_REQ = 0x0000001a,
15324GL2C_PERF_SEL_C_RO_US_REQ = 0x0000001b,
15325GL2C_PERF_SEL_UC_REQ = 0x0000001c,
15326GL2C_PERF_SEL_LRU_REQ = 0x0000001d,
15327GL2C_PERF_SEL_STREAM_REQ = 0x0000001e,
15328GL2C_PERF_SEL_BYPASS_REQ = 0x0000001f,
15329GL2C_PERF_SEL_NOA_REQ = 0x00000020,
15330GL2C_PERF_SEL_SHARED_REQ = 0x00000021,
15331GL2C_PERF_SEL_HIT = 0x00000022,
15332GL2C_PERF_SEL_MISS = 0x00000023,
15333GL2C_PERF_SEL_FULL_HIT = 0x00000024,
15334GL2C_PERF_SEL_PARTIAL_32B_HIT = 0x00000025,
15335GL2C_PERF_SEL_PARTIAL_64B_HIT = 0x00000026,
15336GL2C_PERF_SEL_PARTIAL_96B_HIT = 0x00000027,
15337GL2C_PERF_SEL_DEWRITE_ALLOCATE_HIT = 0x00000028,
15338GL2C_PERF_SEL_FULLY_WRITTEN_HIT = 0x00000029,
15339GL2C_PERF_SEL_UNCACHED_WRITE = 0x0000002a,
15340GL2C_PERF_SEL_WRITEBACK = 0x0000002b,
15341GL2C_PERF_SEL_NORMAL_WRITEBACK = 0x0000002c,
15342GL2C_PERF_SEL_EVICT = 0x0000002d,
15343GL2C_PERF_SEL_NORMAL_EVICT = 0x0000002e,
15344GL2C_PERF_SEL_PROBE_EVICT = 0x0000002f,
15345GL2C_PERF_SEL_REQ_TO_MISS_QUEUE = 0x00000030,
15346GL2C_PERF_SEL_HIT_PASS_MISS_IN_HI_PRIO = 0x00000031,
15347GL2C_PERF_SEL_HIT_PASS_MISS_IN_COMP = 0x00000032,
15348GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT0 = 0x00000033,
15349GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT1 = 0x00000034,
15350GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT2 = 0x00000035,
15351GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT3 = 0x00000036,
15352GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT4 = 0x00000037,
15353GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT5 = 0x00000038,
15354GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT6 = 0x00000039,
15355GL2C_PERF_SEL_HIT_PASS_MISS_IN_CLIENT7 = 0x0000003a,
15356GL2C_PERF_SEL_READ_32_REQ = 0x0000003b,
15357GL2C_PERF_SEL_READ_64_REQ = 0x0000003c,
15358GL2C_PERF_SEL_READ_128_REQ = 0x0000003d,
15359GL2C_PERF_SEL_WRITE_32_REQ = 0x0000003e,
15360GL2C_PERF_SEL_WRITE_64_REQ = 0x0000003f,
15361GL2C_PERF_SEL_COMPRESSED_READ_0_REQ = 0x00000040,
15362GL2C_PERF_SEL_COMPRESSED_READ_32_REQ = 0x00000041,
15363GL2C_PERF_SEL_COMPRESSED_READ_64_REQ = 0x00000042,
15364GL2C_PERF_SEL_COMPRESSED_READ_96_REQ = 0x00000043,
15365GL2C_PERF_SEL_COMPRESSED_READ_128_REQ = 0x00000044,
15366GL2C_PERF_SEL_MC_WRREQ = 0x00000045,
15367GL2C_PERF_SEL_EA_WRREQ_64B = 0x00000046,
15368GL2C_PERF_SEL_EA_WRREQ_PROBE_COMMAND = 0x00000047,
15369GL2C_PERF_SEL_EA_WR_UNCACHED_32B = 0x00000048,
15370GL2C_PERF_SEL_MC_WRREQ_STALL = 0x00000049,
15371GL2C_PERF_SEL_EA_WRREQ_IO_CREDIT_STALL = 0x0000004a,
15372GL2C_PERF_SEL_EA_WRREQ_GMI_CREDIT_STALL = 0x0000004b,
15373GL2C_PERF_SEL_EA_WRREQ_DRAM_CREDIT_STALL = 0x0000004c,
15374GL2C_PERF_SEL_TOO_MANY_EA_WRREQS_STALL = 0x0000004d,
15375GL2C_PERF_SEL_MC_WRREQ_LEVEL = 0x0000004e,
15376GL2C_PERF_SEL_EA_ATOMIC = 0x0000004f,
15377GL2C_PERF_SEL_EA_ATOMIC_LEVEL = 0x00000050,
15378GL2C_PERF_SEL_MC_RDREQ = 0x00000051,
15379GL2C_PERF_SEL_EA_RDREQ_SPLIT = 0x00000052,
15380GL2C_PERF_SEL_EA_RDREQ_32B = 0x00000053,
15381GL2C_PERF_SEL_EA_RDREQ_64B = 0x00000054,
15382GL2C_PERF_SEL_EA_RDREQ_96B = 0x00000055,
15383GL2C_PERF_SEL_EA_RDREQ_128B = 0x00000056,
15384GL2C_PERF_SEL_EA_RD_UNCACHED_32B = 0x00000057,
15385GL2C_PERF_SEL_EA_RD_MDC_32B = 0x00000058,
15386GL2C_PERF_SEL_EA_RD_COMPRESSED_32B = 0x00000059,
15387GL2C_PERF_SEL_EA_RDREQ_IO_CREDIT_STALL = 0x0000005a,
15388GL2C_PERF_SEL_EA_RDREQ_GMI_CREDIT_STALL = 0x0000005b,
15389GL2C_PERF_SEL_EA_RDREQ_DRAM_CREDIT_STALL = 0x0000005c,
15390GL2C_PERF_SEL_MC_RDREQ_LEVEL = 0x0000005d,
15391GL2C_PERF_SEL_EA_RDREQ_DRAM = 0x0000005e,
15392GL2C_PERF_SEL_EA_WRREQ_DRAM = 0x0000005f,
15393GL2C_PERF_SEL_EA_RDREQ_DRAM_32B = 0x00000060,
15394GL2C_PERF_SEL_EA_WRREQ_DRAM_32B = 0x00000061,
15395GL2C_PERF_SEL_ONION_READ = 0x00000062,
15396GL2C_PERF_SEL_ONION_WRITE = 0x00000063,
15397GL2C_PERF_SEL_IO_READ = 0x00000064,
15398GL2C_PERF_SEL_IO_WRITE = 0x00000065,
15399GL2C_PERF_SEL_GARLIC_READ = 0x00000066,
15400GL2C_PERF_SEL_GARLIC_WRITE = 0x00000067,
15401GL2C_PERF_SEL_LATENCY_FIFO_FULL = 0x00000068,
15402GL2C_PERF_SEL_SRC_FIFO_FULL = 0x00000069,
15403GL2C_PERF_SEL_TAG_STALL = 0x0000006a,
15404GL2C_PERF_SEL_TAG_WRITEBACK_FIFO_FULL_STALL = 0x0000006b,
15405GL2C_PERF_SEL_TAG_MISS_NOTHING_REPLACEABLE_STALL = 0x0000006c,
15406GL2C_PERF_SEL_TAG_UNCACHED_WRITE_ATOMIC_FIFO_FULL_STALL = 0x0000006d,
15407GL2C_PERF_SEL_TAG_NO_UNCACHED_WRITE_ATOMIC_ENTRIES_STALL = 0x0000006e,
15408GL2C_PERF_SEL_TAG_PROBE_STALL = 0x0000006f,
15409GL2C_PERF_SEL_TAG_PROBE_FILTER_STALL = 0x00000070,
15410GL2C_PERF_SEL_TAG_PROBE_FIFO_FULL_STALL = 0x00000071,
15411GL2C_PERF_SEL_TAG_READ_DST_STALL = 0x00000072,
15412GL2C_PERF_SEL_READ_RETURN_TIMEOUT = 0x00000073,
15413GL2C_PERF_SEL_WRITEBACK_READ_TIMEOUT = 0x00000074,
15414GL2C_PERF_SEL_READ_RETURN_FULL_BUBBLE = 0x00000075,
15415GL2C_PERF_SEL_BUBBLE = 0x00000076,
15416GL2C_PERF_SEL_IB_REQ = 0x00000077,
15417GL2C_PERF_SEL_IB_STALL = 0x00000078,
15418GL2C_PERF_SEL_IB_TAG_STALL = 0x00000079,
15419GL2C_PERF_SEL_IB_CM_STALL = 0x0000007a,
15420GL2C_PERF_SEL_RETURN_ACK = 0x0000007b,
15421GL2C_PERF_SEL_RETURN_DATA = 0x0000007c,
15422GL2C_PERF_SEL_EA_RDRET_NACK = 0x0000007d,
15423GL2C_PERF_SEL_EA_WRRET_NACK = 0x0000007e,
15424GL2C_PERF_SEL_GL2A_LEVEL = 0x0000007f,
15425GL2C_PERF_SEL_PROBE_FILTER_DISABLE_TRANSITION = 0x00000080,
15426GL2C_PERF_SEL_PROBE_FILTER_DISABLED = 0x00000081,
15427GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_START = 0x00000082,
15428GL2C_PERF_SEL_ALL_TC_OP_WB_OR_INV_VOL_START = 0x00000083,
15429GL2C_PERF_SEL_GCR_INV = 0x00000084,
15430GL2C_PERF_SEL_GCR_WB = 0x00000085,
15431GL2C_PERF_SEL_GCR_DISCARD = 0x00000086,
15432GL2C_PERF_SEL_GCR_RANGE = 0x00000087,
15433GL2C_PERF_SEL_GCR_ALL = 0x00000088,
15434GL2C_PERF_SEL_GCR_VOL = 0x00000089,
15435GL2C_PERF_SEL_GCR_UNSHARED = 0x0000008a,
15436GL2C_PERF_SEL_GCR_MDC_INV = 0x0000008b,
15437GL2C_PERF_SEL_GCR_GL2_INV_ALL = 0x0000008c,
15438GL2C_PERF_SEL_GCR_GL2_WB_ALL = 0x0000008d,
15439GL2C_PERF_SEL_GCR_MDC_INV_ALL = 0x0000008e,
15440GL2C_PERF_SEL_GCR_GL2_INV_RANGE = 0x0000008f,
15441GL2C_PERF_SEL_GCR_GL2_WB_RANGE = 0x00000090,
15442GL2C_PERF_SEL_GCR_GL2_WB_INV_RANGE = 0x00000091,
15443GL2C_PERF_SEL_GCR_MDC_INV_RANGE = 0x00000092,
15444GL2C_PERF_SEL_ALL_GCR_INV_EVICT = 0x00000093,
15445GL2C_PERF_SEL_ALL_GCR_INV_VOL_EVICT = 0x00000094,
15446GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_CYCLE = 0x00000095,
15447GL2C_PERF_SEL_ALL_GCR_WB_OR_INV_VOL_CYCLE = 0x00000096,
15448GL2C_PERF_SEL_ALL_GCR_WB_WRITEBACK = 0x00000097,
15449GL2C_PERF_SEL_GCR_INVL2_VOL_CYCLE = 0x00000098,
15450GL2C_PERF_SEL_GCR_INVL2_VOL_EVICT = 0x00000099,
15451GL2C_PERF_SEL_GCR_INVL2_VOL_START = 0x0000009a,
15452GL2C_PERF_SEL_GCR_WBL2_VOL_CYCLE = 0x0000009b,
15453GL2C_PERF_SEL_GCR_WBL2_VOL_EVICT = 0x0000009c,
15454GL2C_PERF_SEL_GCR_WBL2_VOL_START = 0x0000009d,
15455GL2C_PERF_SEL_GCR_WBINVL2_CYCLE = 0x0000009e,
15456GL2C_PERF_SEL_GCR_WBINVL2_EVICT = 0x0000009f,
15457GL2C_PERF_SEL_GCR_WBINVL2_START = 0x000000a0,
15458GL2C_PERF_SEL_MDC_INV_METADATA = 0x000000a1,
15459GL2C_PERF_SEL_MDC_REQ = 0x000000a2,
15460GL2C_PERF_SEL_MDC_LEVEL = 0x000000a3,
15461GL2C_PERF_SEL_MDC_TAG_HIT = 0x000000a4,
15462GL2C_PERF_SEL_MDC_SECTOR_HIT = 0x000000a5,
15463GL2C_PERF_SEL_MDC_SECTOR_MISS = 0x000000a6,
15464GL2C_PERF_SEL_MDC_TAG_STALL = 0x000000a7,
15465GL2C_PERF_SEL_MDC_TAG_REPLACEMENT_LINE_IN_USE_STALL = 0x000000a8,
15466GL2C_PERF_SEL_MDC_TAG_DESECTORIZATION_FIFO_FULL_STALL = 0x000000a9,
15467GL2C_PERF_SEL_MDC_TAG_WAITING_FOR_INVALIDATE_COMPLETION_STALL = 0x000000aa,
15468GL2C_PERF_SEL_CM_CHANNEL0_REQ = 0x000000ab,
15469GL2C_PERF_SEL_CM_CHANNEL1_REQ = 0x000000ac,
15470GL2C_PERF_SEL_CM_CHANNEL2_REQ = 0x000000ad,
15471GL2C_PERF_SEL_CM_CHANNEL3_REQ = 0x000000ae,
15472GL2C_PERF_SEL_CM_CHANNEL4_REQ = 0x000000af,
15473GL2C_PERF_SEL_CM_CHANNEL5_REQ = 0x000000b0,
15474GL2C_PERF_SEL_CM_CHANNEL6_REQ = 0x000000b1,
15475GL2C_PERF_SEL_CM_CHANNEL7_REQ = 0x000000b2,
15476GL2C_PERF_SEL_CM_CHANNEL8_REQ = 0x000000b3,
15477GL2C_PERF_SEL_CM_CHANNEL9_REQ = 0x000000b4,
15478GL2C_PERF_SEL_CM_CHANNEL10_REQ = 0x000000b5,
15479GL2C_PERF_SEL_CM_CHANNEL11_REQ = 0x000000b6,
15480GL2C_PERF_SEL_CM_CHANNEL12_REQ = 0x000000b7,
15481GL2C_PERF_SEL_CM_CHANNEL13_REQ = 0x000000b8,
15482GL2C_PERF_SEL_CM_CHANNEL14_REQ = 0x000000b9,
15483GL2C_PERF_SEL_CM_CHANNEL15_REQ = 0x000000ba,
15484GL2C_PERF_SEL_CM_CHANNEL16_REQ = 0x000000bb,
15485GL2C_PERF_SEL_CM_CHANNEL17_REQ = 0x000000bc,
15486GL2C_PERF_SEL_CM_CHANNEL18_REQ = 0x000000bd,
15487GL2C_PERF_SEL_CM_CHANNEL19_REQ = 0x000000be,
15488GL2C_PERF_SEL_CM_CHANNEL20_REQ = 0x000000bf,
15489GL2C_PERF_SEL_CM_CHANNEL21_REQ = 0x000000c0,
15490GL2C_PERF_SEL_CM_CHANNEL22_REQ = 0x000000c1,
15491GL2C_PERF_SEL_CM_CHANNEL23_REQ = 0x000000c2,
15492GL2C_PERF_SEL_CM_CHANNEL24_REQ = 0x000000c3,
15493GL2C_PERF_SEL_CM_CHANNEL25_REQ = 0x000000c4,
15494GL2C_PERF_SEL_CM_CHANNEL26_REQ = 0x000000c5,
15495GL2C_PERF_SEL_CM_CHANNEL27_REQ = 0x000000c6,
15496GL2C_PERF_SEL_CM_CHANNEL28_REQ = 0x000000c7,
15497GL2C_PERF_SEL_CM_CHANNEL29_REQ = 0x000000c8,
15498GL2C_PERF_SEL_CM_CHANNEL30_REQ = 0x000000c9,
15499GL2C_PERF_SEL_CM_CHANNEL31_REQ = 0x000000ca,
15500GL2C_PERF_SEL_CM_COMP_ATOMIC_COLOR_REQ = 0x000000cb,
15501GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH16_REQ = 0x000000cc,
15502GL2C_PERF_SEL_CM_COMP_ATOMIC_DEPTH32_REQ = 0x000000cd,
15503GL2C_PERF_SEL_CM_COMP_WRITE_COLOR_REQ = 0x000000ce,
15504GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH16_REQ = 0x000000cf,
15505GL2C_PERF_SEL_CM_COMP_WRITE_DEPTH32_REQ = 0x000000d0,
15506GL2C_PERF_SEL_CM_COMP_WRITE_STENCIL_REQ = 0x000000d1,
15507GL2C_PERF_SEL_CM_COMP_READ_REQ = 0x000000d2,
15508GL2C_PERF_SEL_CM_READ_BACK_REQ = 0x000000d3,
15509GL2C_PERF_SEL_CM_METADATA_WR_REQ = 0x000000d4,
15510GL2C_PERF_SEL_CM_WR_ACK_REQ = 0x000000d5,
15511GL2C_PERF_SEL_CM_NO_ACK_REQ = 0x000000d6,
15512GL2C_PERF_SEL_CM_NOOP_REQ = 0x000000d7,
15513GL2C_PERF_SEL_CM_COMP_COLOR_EN_REQ = 0x000000d8,
15514GL2C_PERF_SEL_CM_COMP_COLOR_DIS_REQ = 0x000000d9,
15515GL2C_PERF_SEL_CM_COMP_STENCIL_REQ = 0x000000da,
15516GL2C_PERF_SEL_CM_COMP_DEPTH16_REQ = 0x000000db,
15517GL2C_PERF_SEL_CM_COMP_DEPTH32_REQ = 0x000000dc,
15518GL2C_PERF_SEL_CM_COLOR_32B_WR_REQ = 0x000000dd,
15519GL2C_PERF_SEL_CM_COLOR_64B_WR_REQ = 0x000000de,
15520GL2C_PERF_SEL_CM_FULL_WRITE_REQ = 0x000000df,
15521GL2C_PERF_SEL_CM_RVF_FULL = 0x000000e0,
15522GL2C_PERF_SEL_CM_SDR_FULL = 0x000000e1,
15523GL2C_PERF_SEL_CM_MERGE_BUF_FULL = 0x000000e2,
15524GL2C_PERF_SEL_CM_DCC_STALL = 0x000000e3,
15525} GL2C_PERF_SEL;
15526
15527/*
15528 * GL2A_PERF_SEL enum
15529 */
15530
15531typedef enum GL2A_PERF_SEL {
15532GL2A_PERF_SEL_NONE = 0x00000000,
15533GL2A_PERF_SEL_CYCLE = 0x00000001,
15534GL2A_PERF_SEL_BUSY = 0x00000002,
15535GL2A_PERF_SEL_REQ_GL2C0 = 0x00000003,
15536GL2A_PERF_SEL_REQ_GL2C1 = 0x00000004,
15537GL2A_PERF_SEL_REQ_GL2C2 = 0x00000005,
15538GL2A_PERF_SEL_REQ_GL2C3 = 0x00000006,
15539GL2A_PERF_SEL_REQ_GL2C4 = 0x00000007,
15540GL2A_PERF_SEL_REQ_GL2C5 = 0x00000008,
15541GL2A_PERF_SEL_REQ_GL2C6 = 0x00000009,
15542GL2A_PERF_SEL_REQ_GL2C7 = 0x0000000a,
15543GL2A_PERF_SEL_REQ_HI_PRIO_GL2C0 = 0x0000000b,
15544GL2A_PERF_SEL_REQ_HI_PRIO_GL2C1 = 0x0000000c,
15545GL2A_PERF_SEL_REQ_HI_PRIO_GL2C2 = 0x0000000d,
15546GL2A_PERF_SEL_REQ_HI_PRIO_GL2C3 = 0x0000000e,
15547GL2A_PERF_SEL_REQ_HI_PRIO_GL2C4 = 0x0000000f,
15548GL2A_PERF_SEL_REQ_HI_PRIO_GL2C5 = 0x00000010,
15549GL2A_PERF_SEL_REQ_HI_PRIO_GL2C6 = 0x00000011,
15550GL2A_PERF_SEL_REQ_HI_PRIO_GL2C7 = 0x00000012,
15551GL2A_PERF_SEL_REQ_BURST_GL2C0 = 0x00000013,
15552GL2A_PERF_SEL_REQ_BURST_GL2C1 = 0x00000014,
15553GL2A_PERF_SEL_REQ_BURST_GL2C2 = 0x00000015,
15554GL2A_PERF_SEL_REQ_BURST_GL2C3 = 0x00000016,
15555GL2A_PERF_SEL_REQ_BURST_GL2C4 = 0x00000017,
15556GL2A_PERF_SEL_REQ_BURST_GL2C5 = 0x00000018,
15557GL2A_PERF_SEL_REQ_BURST_GL2C6 = 0x00000019,
15558GL2A_PERF_SEL_REQ_BURST_GL2C7 = 0x0000001a,
15559GL2A_PERF_SEL_REQ_STALL_GL2C0 = 0x0000001b,
15560GL2A_PERF_SEL_REQ_STALL_GL2C1 = 0x0000001c,
15561GL2A_PERF_SEL_REQ_STALL_GL2C2 = 0x0000001d,
15562GL2A_PERF_SEL_REQ_STALL_GL2C3 = 0x0000001e,
15563GL2A_PERF_SEL_REQ_STALL_GL2C4 = 0x0000001f,
15564GL2A_PERF_SEL_REQ_STALL_GL2C5 = 0x00000020,
15565GL2A_PERF_SEL_REQ_STALL_GL2C6 = 0x00000021,
15566GL2A_PERF_SEL_REQ_STALL_GL2C7 = 0x00000022,
15567GL2A_PERF_SEL_RTN_STALL_GL2C0 = 0x00000023,
15568GL2A_PERF_SEL_RTN_STALL_GL2C1 = 0x00000024,
15569GL2A_PERF_SEL_RTN_STALL_GL2C2 = 0x00000025,
15570GL2A_PERF_SEL_RTN_STALL_GL2C3 = 0x00000026,
15571GL2A_PERF_SEL_RTN_STALL_GL2C4 = 0x00000027,
15572GL2A_PERF_SEL_RTN_STALL_GL2C5 = 0x00000028,
15573GL2A_PERF_SEL_RTN_STALL_GL2C6 = 0x00000029,
15574GL2A_PERF_SEL_RTN_STALL_GL2C7 = 0x0000002a,
15575GL2A_PERF_SEL_RTN_CLIENT0 = 0x0000002b,
15576GL2A_PERF_SEL_RTN_CLIENT1 = 0x0000002c,
15577GL2A_PERF_SEL_RTN_CLIENT2 = 0x0000002d,
15578GL2A_PERF_SEL_RTN_CLIENT3 = 0x0000002e,
15579GL2A_PERF_SEL_RTN_CLIENT4 = 0x0000002f,
15580GL2A_PERF_SEL_RTN_CLIENT5 = 0x00000030,
15581GL2A_PERF_SEL_RTN_CLIENT6 = 0x00000031,
15582GL2A_PERF_SEL_RTN_CLIENT7 = 0x00000032,
15583GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT0 = 0x00000033,
15584GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT1 = 0x00000034,
15585GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT2 = 0x00000035,
15586GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT3 = 0x00000036,
15587GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT4 = 0x00000037,
15588GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT5 = 0x00000038,
15589GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT6 = 0x00000039,
15590GL2A_PERF_SEL_RTN_ARB_COLLISION_CLIENT7 = 0x0000003a,
15591} GL2A_PERF_SEL;
15592
15593/*******************************************************
15594 * GRBM Enums
15595 *******************************************************/
15596
15597/*
15598 * GRBM_PERF_SEL enum
15599 */
15600
15601typedef enum GRBM_PERF_SEL {
15602GRBM_PERF_SEL_COUNT = 0x00000000,
15603GRBM_PERF_SEL_USER_DEFINED = 0x00000001,
15604GRBM_PERF_SEL_GUI_ACTIVE = 0x00000002,
15605GRBM_PERF_SEL_CP_BUSY = 0x00000003,
15606GRBM_PERF_SEL_CP_COHER_BUSY = 0x00000004,
15607GRBM_PERF_SEL_CP_DMA_BUSY = 0x00000005,
15608GRBM_PERF_SEL_CB_BUSY = 0x00000006,
15609GRBM_PERF_SEL_DB_BUSY = 0x00000007,
15610GRBM_PERF_SEL_PA_BUSY = 0x00000008,
15611GRBM_PERF_SEL_SC_BUSY = 0x00000009,
15612GRBM_PERF_SEL_RESERVED_6 = 0x0000000a,
15613GRBM_PERF_SEL_SPI_BUSY = 0x0000000b,
15614GRBM_PERF_SEL_SX_BUSY = 0x0000000c,
15615GRBM_PERF_SEL_TA_BUSY = 0x0000000d,
15616GRBM_PERF_SEL_CB_CLEAN = 0x0000000e,
15617GRBM_PERF_SEL_DB_CLEAN = 0x0000000f,
15618GRBM_PERF_SEL_RESERVED_5 = 0x00000010,
15619GRBM_PERF_SEL_RESERVED_9 = 0x00000011,
15620GRBM_PERF_SEL_RESERVED_4 = 0x00000012,
15621GRBM_PERF_SEL_RESERVED_3 = 0x00000013,
15622GRBM_PERF_SEL_RESERVED_2 = 0x00000014,
15623GRBM_PERF_SEL_RESERVED_1 = 0x00000015,
15624GRBM_PERF_SEL_RESERVED_0 = 0x00000016,
15625GRBM_PERF_SEL_RESERVED_8 = 0x00000017,
15626GRBM_PERF_SEL_RESERVED_7 = 0x00000018,
15627GRBM_PERF_SEL_GDS_BUSY = 0x00000019,
15628GRBM_PERF_SEL_BCI_BUSY = 0x0000001a,
15629GRBM_PERF_SEL_RLC_BUSY = 0x0000001b,
15630GRBM_PERF_SEL_TCP_BUSY = 0x0000001c,
15631GRBM_PERF_SEL_CPG_BUSY = 0x0000001d,
15632GRBM_PERF_SEL_CPC_BUSY = 0x0000001e,
15633GRBM_PERF_SEL_CPF_BUSY = 0x0000001f,
15634GRBM_PERF_SEL_GE_BUSY = 0x00000020,
15635GRBM_PERF_SEL_GE_NO_DMA_BUSY = 0x00000021,
15636GRBM_PERF_SEL_UTCL2_BUSY = 0x00000022,
15637GRBM_PERF_SEL_EA_BUSY = 0x00000023,
15638GRBM_PERF_SEL_RMI_BUSY = 0x00000024,
15639GRBM_PERF_SEL_CPAXI_BUSY = 0x00000025,
15640GRBM_PERF_SEL_UTCL1_BUSY = 0x00000027,
15641GRBM_PERF_SEL_GL2CC_BUSY = 0x00000028,
15642GRBM_PERF_SEL_SDMA_BUSY = 0x00000029,
15643GRBM_PERF_SEL_CH_BUSY = 0x0000002a,
15644GRBM_PERF_SEL_PH_BUSY = 0x0000002b,
15645GRBM_PERF_SEL_PMM_BUSY = 0x0000002c,
15646GRBM_PERF_SEL_GUS_BUSY = 0x0000002d,
15647GRBM_PERF_SEL_GL1CC_BUSY = 0x0000002e,
15648} GRBM_PERF_SEL;
15649
15650/*
15651 * GRBM_SE0_PERF_SEL enum
15652 */
15653
15654typedef enum GRBM_SE0_PERF_SEL {
15655GRBM_SE0_PERF_SEL_COUNT = 0x00000000,
15656GRBM_SE0_PERF_SEL_USER_DEFINED = 0x00000001,
15657GRBM_SE0_PERF_SEL_CB_BUSY = 0x00000002,
15658GRBM_SE0_PERF_SEL_DB_BUSY = 0x00000003,
15659GRBM_SE0_PERF_SEL_SC_BUSY = 0x00000004,
15660GRBM_SE0_PERF_SEL_RESERVED_1 = 0x00000005,
15661GRBM_SE0_PERF_SEL_SPI_BUSY = 0x00000006,
15662GRBM_SE0_PERF_SEL_SX_BUSY = 0x00000007,
15663GRBM_SE0_PERF_SEL_TA_BUSY = 0x00000008,
15664GRBM_SE0_PERF_SEL_CB_CLEAN = 0x00000009,
15665GRBM_SE0_PERF_SEL_DB_CLEAN = 0x0000000a,
15666GRBM_SE0_PERF_SEL_RESERVED_0 = 0x0000000b,
15667GRBM_SE0_PERF_SEL_PA_BUSY = 0x0000000c,
15668GRBM_SE0_PERF_SEL_RESERVED_2 = 0x0000000d,
15669GRBM_SE0_PERF_SEL_BCI_BUSY = 0x0000000e,
15670GRBM_SE0_PERF_SEL_RMI_BUSY = 0x0000000f,
15671GRBM_SE0_PERF_SEL_UTCL1_BUSY = 0x00000010,
15672GRBM_SE0_PERF_SEL_TCP_BUSY = 0x00000011,
15673GRBM_SE0_PERF_SEL_GL1CC_BUSY = 0x00000012,
15674} GRBM_SE0_PERF_SEL;
15675
15676/*
15677 * GRBM_SE1_PERF_SEL enum
15678 */
15679
15680typedef enum GRBM_SE1_PERF_SEL {
15681GRBM_SE1_PERF_SEL_COUNT = 0x00000000,
15682GRBM_SE1_PERF_SEL_USER_DEFINED = 0x00000001,
15683GRBM_SE1_PERF_SEL_CB_BUSY = 0x00000002,
15684GRBM_SE1_PERF_SEL_DB_BUSY = 0x00000003,
15685GRBM_SE1_PERF_SEL_SC_BUSY = 0x00000004,
15686GRBM_SE1_PERF_SEL_RESERVED_1 = 0x00000005,
15687GRBM_SE1_PERF_SEL_SPI_BUSY = 0x00000006,
15688GRBM_SE1_PERF_SEL_SX_BUSY = 0x00000007,
15689GRBM_SE1_PERF_SEL_TA_BUSY = 0x00000008,
15690GRBM_SE1_PERF_SEL_CB_CLEAN = 0x00000009,
15691GRBM_SE1_PERF_SEL_DB_CLEAN = 0x0000000a,
15692GRBM_SE1_PERF_SEL_RESERVED_0 = 0x0000000b,
15693GRBM_SE1_PERF_SEL_PA_BUSY = 0x0000000c,
15694GRBM_SE1_PERF_SEL_RESERVED_2 = 0x0000000d,
15695GRBM_SE1_PERF_SEL_BCI_BUSY = 0x0000000e,
15696GRBM_SE1_PERF_SEL_RMI_BUSY = 0x0000000f,
15697GRBM_SE1_PERF_SEL_UTCL1_BUSY = 0x00000010,
15698GRBM_SE1_PERF_SEL_TCP_BUSY = 0x00000011,
15699GRBM_SE1_PERF_SEL_GL1CC_BUSY = 0x00000012,
15700} GRBM_SE1_PERF_SEL;
15701
15702/*
15703 * GRBM_SE2_PERF_SEL enum
15704 */
15705
15706typedef enum GRBM_SE2_PERF_SEL {
15707GRBM_SE2_PERF_SEL_COUNT = 0x00000000,
15708GRBM_SE2_PERF_SEL_USER_DEFINED = 0x00000001,
15709GRBM_SE2_PERF_SEL_CB_BUSY = 0x00000002,
15710GRBM_SE2_PERF_SEL_DB_BUSY = 0x00000003,
15711GRBM_SE2_PERF_SEL_SC_BUSY = 0x00000004,
15712GRBM_SE2_PERF_SEL_RESERVED_1 = 0x00000005,
15713GRBM_SE2_PERF_SEL_SPI_BUSY = 0x00000006,
15714GRBM_SE2_PERF_SEL_SX_BUSY = 0x00000007,
15715GRBM_SE2_PERF_SEL_TA_BUSY = 0x00000008,
15716GRBM_SE2_PERF_SEL_CB_CLEAN = 0x00000009,
15717GRBM_SE2_PERF_SEL_DB_CLEAN = 0x0000000a,
15718GRBM_SE2_PERF_SEL_RESERVED_0 = 0x0000000b,
15719GRBM_SE2_PERF_SEL_PA_BUSY = 0x0000000c,
15720GRBM_SE2_PERF_SEL_RESERVED_2 = 0x0000000d,
15721GRBM_SE2_PERF_SEL_BCI_BUSY = 0x0000000e,
15722GRBM_SE2_PERF_SEL_RMI_BUSY = 0x0000000f,
15723GRBM_SE2_PERF_SEL_UTCL1_BUSY = 0x00000010,
15724GRBM_SE2_PERF_SEL_TCP_BUSY = 0x00000011,
15725GRBM_SE2_PERF_SEL_GL1CC_BUSY = 0x00000012,
15726} GRBM_SE2_PERF_SEL;
15727
15728/*
15729 * GRBM_SE3_PERF_SEL enum
15730 */
15731
15732typedef enum GRBM_SE3_PERF_SEL {
15733GRBM_SE3_PERF_SEL_COUNT = 0x00000000,
15734GRBM_SE3_PERF_SEL_USER_DEFINED = 0x00000001,
15735GRBM_SE3_PERF_SEL_CB_BUSY = 0x00000002,
15736GRBM_SE3_PERF_SEL_DB_BUSY = 0x00000003,
15737GRBM_SE3_PERF_SEL_SC_BUSY = 0x00000004,
15738GRBM_SE3_PERF_SEL_RESERVED_1 = 0x00000005,
15739GRBM_SE3_PERF_SEL_SPI_BUSY = 0x00000006,
15740GRBM_SE3_PERF_SEL_SX_BUSY = 0x00000007,
15741GRBM_SE3_PERF_SEL_TA_BUSY = 0x00000008,
15742GRBM_SE3_PERF_SEL_CB_CLEAN = 0x00000009,
15743GRBM_SE3_PERF_SEL_DB_CLEAN = 0x0000000a,
15744GRBM_SE3_PERF_SEL_RESERVED_0 = 0x0000000b,
15745GRBM_SE3_PERF_SEL_PA_BUSY = 0x0000000c,
15746GRBM_SE3_PERF_SEL_RESERVED_2 = 0x0000000d,
15747GRBM_SE3_PERF_SEL_BCI_BUSY = 0x0000000e,
15748GRBM_SE3_PERF_SEL_RMI_BUSY = 0x0000000f,
15749GRBM_SE3_PERF_SEL_UTCL1_BUSY = 0x00000010,
15750GRBM_SE3_PERF_SEL_TCP_BUSY = 0x00000011,
15751GRBM_SE3_PERF_SEL_GL1CC_BUSY = 0x00000012,
15752} GRBM_SE3_PERF_SEL;
15753
15754/*******************************************************
15755 * CP Enums
15756 *******************************************************/
15757
15758/*
15759 * CP_RING_ID enum
15760 */
15761
15762typedef enum CP_RING_ID {
15763RINGID0 = 0x00000000,
15764RINGID1 = 0x00000001,
15765RINGID2 = 0x00000002,
15766RINGID3 = 0x00000003,
15767} CP_RING_ID;
15768
15769/*
15770 * CP_PIPE_ID enum
15771 */
15772
15773typedef enum CP_PIPE_ID {
15774PIPE_ID0 = 0x00000000,
15775PIPE_ID1 = 0x00000001,
15776PIPE_ID2 = 0x00000002,
15777PIPE_ID3 = 0x00000003,
15778} CP_PIPE_ID;
15779
15780/*
15781 * CP_ME_ID enum
15782 */
15783
15784typedef enum CP_ME_ID {
15785ME_ID0 = 0x00000000,
15786ME_ID1 = 0x00000001,
15787ME_ID2 = 0x00000002,
15788ME_ID3 = 0x00000003,
15789} CP_ME_ID;
15790
15791/*
15792 * SPM_PERFMON_STATE enum
15793 */
15794
15795typedef enum SPM_PERFMON_STATE {
15796STRM_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
15797STRM_PERFMON_STATE_START_COUNTING = 0x00000001,
15798STRM_PERFMON_STATE_STOP_COUNTING = 0x00000002,
15799STRM_PERFMON_STATE_RESERVED_3 = 0x00000003,
15800STRM_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
15801STRM_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
15802} SPM_PERFMON_STATE;
15803
15804/*
15805 * CP_PERFMON_STATE enum
15806 */
15807
15808typedef enum CP_PERFMON_STATE {
15809CP_PERFMON_STATE_DISABLE_AND_RESET = 0x00000000,
15810CP_PERFMON_STATE_START_COUNTING = 0x00000001,
15811CP_PERFMON_STATE_STOP_COUNTING = 0x00000002,
15812CP_PERFMON_STATE_RESERVED_3 = 0x00000003,
15813CP_PERFMON_STATE_DISABLE_AND_RESET_PHANTOM = 0x00000004,
15814CP_PERFMON_STATE_COUNT_AND_DUMP_PHANTOM = 0x00000005,
15815} CP_PERFMON_STATE;
15816
15817/*
15818 * CP_PERFMON_ENABLE_MODE enum
15819 */
15820
15821typedef enum CP_PERFMON_ENABLE_MODE {
15822CP_PERFMON_ENABLE_MODE_ALWAYS_COUNT = 0x00000000,
15823CP_PERFMON_ENABLE_MODE_RESERVED_1 = 0x00000001,
15824CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_TRUE = 0x00000002,
15825CP_PERFMON_ENABLE_MODE_COUNT_CONTEXT_FALSE = 0x00000003,
15826} CP_PERFMON_ENABLE_MODE;
15827
15828/*
15829 * CPG_PERFCOUNT_SEL enum
15830 */
15831
15832typedef enum CPG_PERFCOUNT_SEL {
15833CPG_PERF_SEL_ALWAYS_COUNT = 0x00000000,
15834CPG_PERF_SEL_RBIU_FIFO_FULL = 0x00000001,
15835CPG_PERF_SEL_CSF_RTS_BUT_MIU_NOT_RTR = 0x00000002,
15836CPG_PERF_SEL_CSF_ST_BASE_SIZE_FIFO_FULL = 0x00000003,
15837CPG_PERF_SEL_CP_GRBM_DWORDS_SENT = 0x00000004,
15838CPG_PERF_SEL_ME_PARSER_BUSY = 0x00000005,
15839CPG_PERF_SEL_COUNT_TYPE0_PACKETS = 0x00000006,
15840CPG_PERF_SEL_COUNT_TYPE3_PACKETS = 0x00000007,
15841CPG_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x00000008,
15842CPG_PERF_SEL_CP_GRBM_OUT_OF_CREDITS = 0x00000009,
15843CPG_PERF_SEL_CP_PFP_GRBM_OUT_OF_CREDITS = 0x0000000a,
15844CPG_PERF_SEL_CP_GDS_GRBM_OUT_OF_CREDITS = 0x0000000b,
15845CPG_PERF_SEL_RCIU_STALLED_ON_ME_READ = 0x0000000c,
15846CPG_PERF_SEL_RCIU_STALLED_ON_DMA_READ = 0x0000000d,
15847CPG_PERF_SEL_SSU_STALLED_ON_ACTIVE_CNTX = 0x0000000e,
15848CPG_PERF_SEL_SSU_STALLED_ON_CLEAN_SIGNALS = 0x0000000f,
15849CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_PULSE = 0x00000010,
15850CPG_PERF_SEL_QU_STALLED_ON_EOP_DONE_WR_CONFIRM = 0x00000011,
15851CPG_PERF_SEL_PFP_STALLED_ON_CSF_READY = 0x00000012,
15852CPG_PERF_SEL_PFP_STALLED_ON_MEQ_READY = 0x00000013,
15853CPG_PERF_SEL_PFP_STALLED_ON_RCIU_READY = 0x00000014,
15854CPG_PERF_SEL_PFP_STALLED_FOR_DATA_FROM_ROQ = 0x00000015,
15855CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_PFP = 0x00000016,
15856CPG_PERF_SEL_ME_STALLED_FOR_DATA_FROM_STQ = 0x00000017,
15857CPG_PERF_SEL_ME_STALLED_ON_NO_AVAIL_GFX_CNTX = 0x00000018,
15858CPG_PERF_SEL_ME_STALLED_WRITING_TO_RCIU = 0x00000019,
15859CPG_PERF_SEL_ME_STALLED_WRITING_CONSTANTS = 0x0000001a,
15860CPG_PERF_SEL_ME_STALLED_ON_PARTIAL_FLUSH = 0x0000001b,
15861CPG_PERF_SEL_ME_WAIT_ON_CE_COUNTER = 0x0000001c,
15862CPG_PERF_SEL_ME_WAIT_ON_AVAIL_BUFFER = 0x0000001d,
15863CPG_PERF_SEL_SEMAPHORE_BUSY_POLLING_FOR_PASS = 0x0000001e,
15864CPG_PERF_SEL_LOAD_STALLED_ON_SET_COHERENCY = 0x0000001f,
15865CPG_PERF_SEL_DYNAMIC_CLK_VALID = 0x00000020,
15866CPG_PERF_SEL_REGISTER_CLK_VALID = 0x00000021,
15867CPG_PERF_SEL_GUS_WRITE_REQUEST_SENT = 0x00000022,
15868CPG_PERF_SEL_GUS_READ_REQUEST_SENT = 0x00000023,
15869CPG_PERF_SEL_CE_STALL_RAM_DUMP = 0x00000024,
15870CPG_PERF_SEL_CE_STALL_RAM_WRITE = 0x00000025,
15871CPG_PERF_SEL_CE_STALL_ON_INC_FIFO = 0x00000026,
15872CPG_PERF_SEL_CE_STALL_ON_WR_RAM_FIFO = 0x00000027,
15873CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_MIU = 0x00000028,
15874CPG_PERF_SEL_CE_STALL_ON_DATA_FROM_ROQ = 0x00000029,
15875CPG_PERF_SEL_CE_STALL_ON_CE_BUFFER_FLAG = 0x0000002a,
15876CPG_PERF_SEL_CE_STALL_ON_DE_COUNTER = 0x0000002b,
15877CPG_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x0000002c,
15878CPG_PERF_SEL_TCIU_STALL_WAIT_ON_TAGS = 0x0000002d,
15879CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x0000002e,
15880CPG_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x0000002f,
15881CPG_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000030,
15882CPG_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000031,
15883CPG_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000032,
15884CPG_PERF_SEL_CPG_STAT_BUSY = 0x00000033,
15885CPG_PERF_SEL_CPG_STAT_IDLE = 0x00000034,
15886CPG_PERF_SEL_CPG_STAT_STALL = 0x00000035,
15887CPG_PERF_SEL_CPG_TCIU_BUSY = 0x00000036,
15888CPG_PERF_SEL_CPG_TCIU_IDLE = 0x00000037,
15889CPF_PERF_SEL_CPG_TCIU_STALL = 0x00000038,
15890CPG_PERF_SEL_CPG_UTCL2IU_BUSY = 0x00000039,
15891CPG_PERF_SEL_CPG_UTCL2IU_IDLE = 0x0000003a,
15892CPG_PERF_SEL_CPG_UTCL2IU_STALL = 0x0000003b,
15893CPG_PERF_SEL_CPG_GCRIU_BUSY = 0x0000003c,
15894CPG_PERF_SEL_CPG_GCRIU_IDLE = 0x0000003d,
15895CPG_PERF_SEL_CPG_GCRIU_STALL = 0x0000003e,
15896CPG_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x0000003f,
15897CPG_PERF_SEL_ALL_GFX_PIPES_BUSY = 0x00000040,
15898CPG_PERF_SEL_CPG_UTCL2IU_XACK = 0x00000041,
15899CPG_PERF_SEL_CPG_UTCL2IU_XNACK = 0x00000042,
15900CPG_PERF_SEL_PFP_STALLED_ON_MEQ_DDID_READY = 0x00000043,
15901CPG_PERF_SEL_PFP_INSTR_CACHE_HIT = 0x00000044,
15902CPG_PERF_SEL_PFP_INSTR_CACHE_MISS = 0x00000045,
15903CPG_PERF_SEL_CE_INSTR_CACHE_HIT = 0x00000046,
15904CPG_PERF_SEL_CE_INSTR_CACHE_MISS = 0x00000047,
15905CPG_PERF_SEL_ME_INSTR_CACHE_HIT = 0x00000048,
15906CPG_PERF_SEL_ME_INSTR_CACHE_MISS = 0x00000049,
15907CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB1 = 0x0000004a,
15908CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB1 = 0x0000004b,
15909CPG_PERF_SEL_PFP_PACKET_FILTER_HIT_IB2 = 0x0000004c,
15910CPG_PERF_SEL_PFP_PACKET_FILTER_MISS_IB2 = 0x0000004d,
15911} CPG_PERFCOUNT_SEL;
15912
15913/*
15914 * CPF_PERFCOUNT_SEL enum
15915 */
15916
15917typedef enum CPF_PERFCOUNT_SEL {
15918CPF_PERF_SEL_ALWAYS_COUNT = 0x00000000,
15919CPF_PERF_SEL_MIU_STALLED_WAITING_RDREQ_FREE = 0x00000001,
15920CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_FREE = 0x00000002,
15921CPF_PERF_SEL_TCIU_STALLED_WAITING_ON_TAGS = 0x00000003,
15922CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_RING = 0x00000004,
15923CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB1 = 0x00000005,
15924CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_IB2 = 0x00000006,
15925CPF_PERF_SEL_CSF_BUSY_FOR_FECTHINC_STATE = 0x00000007,
15926CPF_PERF_SEL_MIU_BUSY_FOR_OUTSTANDING_TAGS = 0x00000008,
15927CPF_PERF_SEL_CSF_RTS_MIU_NOT_RTR = 0x00000009,
15928CPF_PERF_SEL_CSF_STATE_FIFO_NOT_RTR = 0x0000000a,
15929CPF_PERF_SEL_CSF_FETCHING_CMD_BUFFERS = 0x0000000b,
15930CPF_PERF_SEL_GRBM_DWORDS_SENT = 0x0000000c,
15931CPF_PERF_SEL_DYNAMIC_CLOCK_VALID = 0x0000000d,
15932CPF_PERF_SEL_REGISTER_CLOCK_VALID = 0x0000000e,
15933CPF_PERF_SEL_GUS_WRITE_REQUEST_SEND = 0x0000000f,
15934CPF_PERF_SEL_GUS_READ_REQUEST_SEND = 0x00000010,
15935CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000011,
15936CPF_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000012,
15937CPF_PERF_SEL_GFX_UTCL1_STALL_ON_TRANSLATION = 0x00000013,
15938CPF_PERF_SEL_CMP_UTCL1_STALL_ON_TRANSLATION = 0x00000014,
15939CPF_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000015,
15940CPF_PERF_SEL_TCIU_WRITE_REQUEST_SENT = 0x00000016,
15941CPF_PERF_SEL_TCIU_READ_REQUEST_SENT = 0x00000017,
15942CPF_PERF_SEL_CPF_STAT_BUSY = 0x00000018,
15943CPF_PERF_SEL_CPF_STAT_IDLE = 0x00000019,
15944CPF_PERF_SEL_CPF_STAT_STALL = 0x0000001a,
15945CPF_PERF_SEL_CPF_TCIU_BUSY = 0x0000001b,
15946CPF_PERF_SEL_CPF_TCIU_IDLE = 0x0000001c,
15947CPF_PERF_SEL_CPF_TCIU_STALL = 0x0000001d,
15948CPF_PERF_SEL_CPF_UTCL2IU_BUSY = 0x0000001e,
15949CPF_PERF_SEL_CPF_UTCL2IU_IDLE = 0x0000001f,
15950CPF_PERF_SEL_CPF_UTCL2IU_STALL = 0x00000020,
15951CPF_PERF_SEL_CPF_GCRIU_BUSY = 0x00000021,
15952CPF_PERF_SEL_CPF_GCRIU_IDLE = 0x00000022,
15953CPF_PERF_SEL_CPF_GCRIU_STALL = 0x00000023,
15954CPF_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000024,
15955CPF_PERF_SEL_CSF_BUSY_FOR_FETCHING_DB = 0x00000025,
15956CPF_PERF_SEL_CPF_UTCL2IU_XACK = 0x00000026,
15957CPF_PERF_SEL_CPF_UTCL2IU_XNACK = 0x00000027,
15958} CPF_PERFCOUNT_SEL;
15959
15960/*
15961 * CPC_PERFCOUNT_SEL enum
15962 */
15963
15964typedef enum CPC_PERFCOUNT_SEL {
15965CPC_PERF_SEL_ALWAYS_COUNT = 0x00000000,
15966CPC_PERF_SEL_RCIU_STALL_WAIT_ON_FREE = 0x00000001,
15967CPC_PERF_SEL_RCIU_STALL_PRIV_VIOLATION = 0x00000002,
15968CPC_PERF_SEL_MIU_STALL_ON_RDREQ_FREE = 0x00000003,
15969CPC_PERF_SEL_MIU_STALL_ON_WRREQ_FREE = 0x00000004,
15970CPC_PERF_SEL_TCIU_STALL_WAIT_ON_FREE = 0x00000005,
15971CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY = 0x00000006,
15972CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READY_PERF = 0x00000007,
15973CPC_PERF_SEL_ME1_STALL_WAIT_ON_RCIU_READ = 0x00000008,
15974CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_READ = 0x00000009,
15975CPC_PERF_SEL_ME1_STALL_WAIT_ON_GUS_WRITE = 0x0000000a,
15976CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ = 0x0000000b,
15977CPC_PERF_SEL_ME1_STALL_ON_DATA_FROM_ROQ_PERF = 0x0000000c,
15978CPC_PERF_SEL_ME1_BUSY_FOR_PACKET_DECODE = 0x0000000d,
15979CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY = 0x0000000e,
15980CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READY_PERF = 0x0000000f,
15981CPC_PERF_SEL_ME2_STALL_WAIT_ON_RCIU_READ = 0x00000010,
15982CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_READ = 0x00000011,
15983CPC_PERF_SEL_ME2_STALL_WAIT_ON_GUS_WRITE = 0x00000012,
15984CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ = 0x00000013,
15985CPC_PERF_SEL_ME2_STALL_ON_DATA_FROM_ROQ_PERF = 0x00000014,
15986CPC_PERF_SEL_ME2_BUSY_FOR_PACKET_DECODE = 0x00000015,
15987CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_FREE = 0x00000016,
15988CPC_PERF_SEL_UTCL2IU_STALL_WAIT_ON_TAGS = 0x00000017,
15989CPC_PERF_SEL_UTCL1_STALL_ON_TRANSLATION = 0x00000018,
15990CPC_PERF_SEL_CPC_STAT_BUSY = 0x00000019,
15991CPC_PERF_SEL_CPC_STAT_IDLE = 0x0000001a,
15992CPC_PERF_SEL_CPC_STAT_STALL = 0x0000001b,
15993CPC_PERF_SEL_CPC_TCIU_BUSY = 0x0000001c,
15994CPC_PERF_SEL_CPC_TCIU_IDLE = 0x0000001d,
15995CPC_PERF_SEL_CPC_UTCL2IU_BUSY = 0x0000001e,
15996CPC_PERF_SEL_CPC_UTCL2IU_IDLE = 0x0000001f,
15997CPC_PERF_SEL_CPC_UTCL2IU_STALL = 0x00000020,
15998CPC_PERF_SEL_ME1_DC0_SPI_BUSY = 0x00000021,
15999CPC_PERF_SEL_ME2_DC1_SPI_BUSY = 0x00000022,
16000CPC_PERF_SEL_CPC_GCRIU_BUSY = 0x00000023,
16001CPC_PERF_SEL_CPC_GCRIU_IDLE = 0x00000024,
16002CPC_PERF_SEL_CPC_GCRIU_STALL = 0x00000025,
16003CPC_PERF_SEL_GCRIU_STALL_WAIT_ON_FREE = 0x00000026,
16004CPC_PERF_SEL_ME1_STALL_WAIT_ON_TCIU_READ = 0x00000027,
16005CPC_PERF_SEL_ME2_STALL_WAIT_ON_TCIU_READ = 0x00000028,
16006CPC_PERF_SEL_CPC_UTCL2IU_XACK = 0x00000029,
16007CPC_PERF_SEL_CPC_UTCL2IU_XNACK = 0x0000002a,
16008CPC_PERF_SEL_MEC_INSTR_CACHE_HIT = 0x0000002b,
16009CPC_PERF_SEL_MEC_INSTR_CACHE_MISS = 0x0000002c,
16010} CPC_PERFCOUNT_SEL;
16011
16012/*
16013 * CP_ALPHA_TAG_RAM_SEL enum
16014 */
16015
16016typedef enum CP_ALPHA_TAG_RAM_SEL {
16017CPG_TAG_RAM = 0x00000000,
16018CPC_TAG_RAM = 0x00000001,
16019CPF_TAG_RAM = 0x00000002,
16020RSV_TAG_RAM = 0x00000003,
16021} CP_ALPHA_TAG_RAM_SEL;
16022
16023/*
16024 * CPF_PERFCOUNTWINDOW_SEL enum
16025 */
16026
16027typedef enum CPF_PERFCOUNTWINDOW_SEL {
16028CPF_PERFWINDOW_SEL_CSF = 0x00000000,
16029CPF_PERFWINDOW_SEL_HQD1 = 0x00000001,
16030CPF_PERFWINDOW_SEL_HQD2 = 0x00000002,
16031CPF_PERFWINDOW_SEL_RDMA = 0x00000003,
16032CPF_PERFWINDOW_SEL_RWPP = 0x00000004,
16033} CPF_PERFCOUNTWINDOW_SEL;
16034
16035/*
16036 * CPG_PERFCOUNTWINDOW_SEL enum
16037 */
16038
16039typedef enum CPG_PERFCOUNTWINDOW_SEL {
16040CPG_PERFWINDOW_SEL_PFP = 0x00000000,
16041CPG_PERFWINDOW_SEL_ME = 0x00000001,
16042CPG_PERFWINDOW_SEL_CE = 0x00000002,
16043CPG_PERFWINDOW_SEL_MES = 0x00000003,
16044CPG_PERFWINDOW_SEL_MEC1 = 0x00000004,
16045CPG_PERFWINDOW_SEL_MEC2 = 0x00000005,
16046CPG_PERFWINDOW_SEL_DFY = 0x00000006,
16047CPG_PERFWINDOW_SEL_DMA = 0x00000007,
16048CPG_PERFWINDOW_SEL_SHADOW = 0x00000008,
16049CPG_PERFWINDOW_SEL_RB = 0x00000009,
16050CPG_PERFWINDOW_SEL_CEDMA = 0x0000000a,
16051CPG_PERFWINDOW_SEL_PRT_HDR_RPTR = 0x0000000b,
16052CPG_PERFWINDOW_SEL_PRT_SMP_RPTR = 0x0000000c,
16053CPG_PERFWINDOW_SEL_PQ1 = 0x0000000d,
16054CPG_PERFWINDOW_SEL_PQ2 = 0x0000000e,
16055CPG_PERFWINDOW_SEL_PQ3 = 0x0000000f,
16056CPG_PERFWINDOW_SEL_MEMWR = 0x00000010,
16057CPG_PERFWINDOW_SEL_MEMRD = 0x00000011,
16058CPG_PERFWINDOW_SEL_VGT0 = 0x00000012,
16059CPG_PERFWINDOW_SEL_VGT1 = 0x00000013,
16060CPG_PERFWINDOW_SEL_APPEND = 0x00000014,
16061CPG_PERFWINDOW_SEL_QURD = 0x00000015,
16062CPG_PERFWINDOW_SEL_DDID = 0x00000016,
16063CPG_PERFWINDOW_SEL_SR = 0x00000017,
16064CPG_PERFWINDOW_SEL_QU_EOP = 0x00000018,
16065CPG_PERFWINDOW_SEL_QU_STRM = 0x00000019,
16066CPG_PERFWINDOW_SEL_QU_PIPE = 0x0000001a,
16067CPG_PERFWINDOW_SEL_RESERVED1 = 0x0000001b,
16068CPG_PERFWINDOW_SEL_CPC_IC = 0x0000001c,
16069CPG_PERFWINDOW_SEL_RESERVED2 = 0x0000001d,
16070CPG_PERFWINDOW_SEL_CPG_IC = 0x0000001e,
16071} CPG_PERFCOUNTWINDOW_SEL;
16072
16073/*
16074 * CPF_LATENCY_STATS_SEL enum
16075 */
16076
16077typedef enum CPF_LATENCY_STATS_SEL {
16078CPF_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
16079CPF_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
16080CPF_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
16081CPF_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
16082CPF_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
16083CPF_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
16084CPF_LATENCY_STATS_SEL_READ_MAX = 0x00000006,
16085CPF_LATENCY_STATS_SEL_READ_MIN = 0x00000007,
16086CPF_LATENCY_STATS_SEL_READ_LAST = 0x00000008,
16087CPF_LATENCY_STATS_SEL_INVAL_MAX = 0x00000009,
16088CPF_LATENCY_STATS_SEL_INVAL_MIN = 0x0000000a,
16089CPF_LATENCY_STATS_SEL_INVAL_LAST = 0x0000000b,
16090} CPF_LATENCY_STATS_SEL;
16091
16092/*
16093 * CPG_LATENCY_STATS_SEL enum
16094 */
16095
16096typedef enum CPG_LATENCY_STATS_SEL {
16097CPG_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
16098CPG_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
16099CPG_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
16100CPG_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
16101CPG_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
16102CPG_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
16103CPG_LATENCY_STATS_SEL_WRITE_MAX = 0x00000006,
16104CPG_LATENCY_STATS_SEL_WRITE_MIN = 0x00000007,
16105CPG_LATENCY_STATS_SEL_WRITE_LAST = 0x00000008,
16106CPG_LATENCY_STATS_SEL_READ_MAX = 0x00000009,
16107CPG_LATENCY_STATS_SEL_READ_MIN = 0x0000000a,
16108CPG_LATENCY_STATS_SEL_READ_LAST = 0x0000000b,
16109CPG_LATENCY_STATS_SEL_ATOMIC_MAX = 0x0000000c,
16110CPG_LATENCY_STATS_SEL_ATOMIC_MIN = 0x0000000d,
16111CPG_LATENCY_STATS_SEL_ATOMIC_LAST = 0x0000000e,
16112CPG_LATENCY_STATS_SEL_INVAL_MAX = 0x0000000f,
16113CPG_LATENCY_STATS_SEL_INVAL_MIN = 0x00000010,
16114CPG_LATENCY_STATS_SEL_INVAL_LAST = 0x00000011,
16115} CPG_LATENCY_STATS_SEL;
16116
16117/*
16118 * CPC_LATENCY_STATS_SEL enum
16119 */
16120
16121typedef enum CPC_LATENCY_STATS_SEL {
16122CPC_LATENCY_STATS_SEL_XACK_MAX = 0x00000000,
16123CPC_LATENCY_STATS_SEL_XACK_MIN = 0x00000001,
16124CPC_LATENCY_STATS_SEL_XACK_LAST = 0x00000002,
16125CPC_LATENCY_STATS_SEL_XNACK_MAX = 0x00000003,
16126CPC_LATENCY_STATS_SEL_XNACK_MIN = 0x00000004,
16127CPC_LATENCY_STATS_SEL_XNACK_LAST = 0x00000005,
16128CPC_LATENCY_STATS_SEL_INVAL_MAX = 0x00000006,
16129CPC_LATENCY_STATS_SEL_INVAL_MIN = 0x00000007,
16130CPC_LATENCY_STATS_SEL_INVAL_LAST = 0x00000008,
16131} CPC_LATENCY_STATS_SEL;
16132
16133/*
16134 * CP_DDID_CNTL_MODE enum
16135 */
16136
16137typedef enum CP_DDID_CNTL_MODE {
16138STALL = 0x00000000,
16139OVERRUN = 0x00000001,
16140} CP_DDID_CNTL_MODE;
16141
16142/*
16143 * CP_DDID_CNTL_SIZE enum
16144 */
16145
16146typedef enum CP_DDID_CNTL_SIZE {
16147SIZE_8K = 0x00000000,
16148SIZE_16K = 0x00000001,
16149} CP_DDID_CNTL_SIZE;
16150
16151/*
16152 * CP_DDID_CNTL_VMID_SEL enum
16153 */
16154
16155typedef enum CP_DDID_CNTL_VMID_SEL {
16156DDID_VMID_PIPE = 0x00000000,
16157DDID_VMID_CNTL = 0x00000001,
16158} CP_DDID_CNTL_VMID_SEL;
16159
16160/*
16161 * SEM_RESPONSE value
16162 */
16163
16164#define SEM_ECC_ERROR 0x00000000
16165#define SEM_TRANS_ERROR 0x00000001
16166#define SEM_RESP_FAILED 0x00000002
16167#define SEM_RESP_PASSED 0x00000003
16168
16169/*
16170 * IQ_RETRY_TYPE value
16171 */
16172
16173#define IQ_QUEUE_SLEEP 0x00000000
16174#define IQ_OFFLOAD_RETRY 0x00000001
16175#define IQ_SCH_WAVE_MSG 0x00000002
16176#define IQ_SEM_REARM 0x00000003
16177#define IQ_DEQUEUE_RETRY 0x00000004
16178
16179/*
16180 * IQ_INTR_TYPE value
16181 */
16182
16183#define IQ_INTR_TYPE_PQ 0x00000000
16184#define IQ_INTR_TYPE_IB 0x00000001
16185#define IQ_INTR_TYPE_MQD 0x00000002
16186
16187/*
16188 * VMID_SIZE value
16189 */
16190
16191#define VMID_SZ 0x00000004
16192
16193/*
16194 * CONFIG_SPACE value
16195 */
16196
16197#define CONFIG_SPACE_START 0x00002000
16198#define CONFIG_SPACE_END 0x00009fff
16199
16200/*
16201 * CONFIG_SPACE1 value
16202 */
16203
16204#define CONFIG_SPACE1_START 0x00002000
16205#define CONFIG_SPACE1_END 0x00002bff
16206
16207/*
16208 * CONFIG_SPACE2 value
16209 */
16210
16211#define CONFIG_SPACE2_START 0x00003000
16212#define CONFIG_SPACE2_END 0x00009fff
16213
16214/*
16215 * UCONFIG_SPACE value
16216 */
16217
16218#define UCONFIG_SPACE_START 0x0000c000
16219#define UCONFIG_SPACE_END 0x0000ffff
16220
16221/*
16222 * PERSISTENT_SPACE value
16223 */
16224
16225#define PERSISTENT_SPACE_START 0x00002c00
16226#define PERSISTENT_SPACE_END 0x00002fff
16227
16228/*
16229 * CONTEXT_SPACE value
16230 */
16231
16232#define CONTEXT_SPACE_START 0x0000a000
16233#define CONTEXT_SPACE_END 0x0000bfff
16234
16235/*******************************************************
16236 * SX Enums
16237 *******************************************************/
16238
16239/*
16240 * SX_BLEND_OPT enum
16241 */
16242
16243typedef enum SX_BLEND_OPT {
16244BLEND_OPT_PRESERVE_NONE_IGNORE_ALL = 0x00000000,
16245BLEND_OPT_PRESERVE_ALL_IGNORE_NONE = 0x00000001,
16246BLEND_OPT_PRESERVE_C1_IGNORE_C0 = 0x00000002,
16247BLEND_OPT_PRESERVE_C0_IGNORE_C1 = 0x00000003,
16248BLEND_OPT_PRESERVE_A1_IGNORE_A0 = 0x00000004,
16249BLEND_OPT_PRESERVE_A0_IGNORE_A1 = 0x00000005,
16250BLEND_OPT_PRESERVE_NONE_IGNORE_A0 = 0x00000006,
16251BLEND_OPT_PRESERVE_NONE_IGNORE_NONE = 0x00000007,
16252} SX_BLEND_OPT;
16253
16254/*
16255 * SX_OPT_COMB_FCN enum
16256 */
16257
16258typedef enum SX_OPT_COMB_FCN {
16259OPT_COMB_NONE = 0x00000000,
16260OPT_COMB_ADD = 0x00000001,
16261OPT_COMB_SUBTRACT = 0x00000002,
16262OPT_COMB_MIN = 0x00000003,
16263OPT_COMB_MAX = 0x00000004,
16264OPT_COMB_REVSUBTRACT = 0x00000005,
16265OPT_COMB_BLEND_DISABLED = 0x00000006,
16266OPT_COMB_SAFE_ADD = 0x00000007,
16267} SX_OPT_COMB_FCN;
16268
16269/*
16270 * SX_DOWNCONVERT_FORMAT enum
16271 */
16272
16273typedef enum SX_DOWNCONVERT_FORMAT {
16274SX_RT_EXPORT_NO_CONVERSION = 0x00000000,
16275SX_RT_EXPORT_32_R = 0x00000001,
16276SX_RT_EXPORT_32_A = 0x00000002,
16277SX_RT_EXPORT_10_11_11 = 0x00000003,
16278SX_RT_EXPORT_2_10_10_10 = 0x00000004,
16279SX_RT_EXPORT_8_8_8_8 = 0x00000005,
16280SX_RT_EXPORT_5_6_5 = 0x00000006,
16281SX_RT_EXPORT_1_5_5_5 = 0x00000007,
16282SX_RT_EXPORT_4_4_4_4 = 0x00000008,
16283SX_RT_EXPORT_16_16_GR = 0x00000009,
16284SX_RT_EXPORT_16_16_AR = 0x0000000a,
16285} SX_DOWNCONVERT_FORMAT;
16286
16287/*
16288 * SX_PERFCOUNTER_VALS enum
16289 */
16290
16291typedef enum SX_PERFCOUNTER_VALS {
16292SX_PERF_SEL_PA_IDLE_CYCLES = 0x00000000,
16293SX_PERF_SEL_PA_REQ = 0x00000001,
16294SX_PERF_SEL_PA_POS = 0x00000002,
16295SX_PERF_SEL_CLOCK = 0x00000003,
16296SX_PERF_SEL_GATE_EN1 = 0x00000004,
16297SX_PERF_SEL_GATE_EN2 = 0x00000005,
16298SX_PERF_SEL_GATE_EN3 = 0x00000006,
16299SX_PERF_SEL_GATE_EN4 = 0x00000007,
16300SX_PERF_SEL_SH_POS_STARVE = 0x00000008,
16301SX_PERF_SEL_SH_COLOR_STARVE = 0x00000009,
16302SX_PERF_SEL_SH_POS_STALL = 0x0000000a,
16303SX_PERF_SEL_SH_COLOR_STALL = 0x0000000b,
16304SX_PERF_SEL_DB0_PIXELS = 0x0000000c,
16305SX_PERF_SEL_DB0_HALF_QUADS = 0x0000000d,
16306SX_PERF_SEL_DB0_PIXEL_STALL = 0x0000000e,
16307SX_PERF_SEL_DB0_PIXEL_IDLE = 0x0000000f,
16308SX_PERF_SEL_DB0_PRED_PIXELS = 0x00000010,
16309SX_PERF_SEL_DB1_PIXELS = 0x00000011,
16310SX_PERF_SEL_DB1_HALF_QUADS = 0x00000012,
16311SX_PERF_SEL_DB1_PIXEL_STALL = 0x00000013,
16312SX_PERF_SEL_DB1_PIXEL_IDLE = 0x00000014,
16313SX_PERF_SEL_DB1_PRED_PIXELS = 0x00000015,
16314SX_PERF_SEL_DB2_PIXELS = 0x00000016,
16315SX_PERF_SEL_DB2_HALF_QUADS = 0x00000017,
16316SX_PERF_SEL_DB2_PIXEL_STALL = 0x00000018,
16317SX_PERF_SEL_DB2_PIXEL_IDLE = 0x00000019,
16318SX_PERF_SEL_DB2_PRED_PIXELS = 0x0000001a,
16319SX_PERF_SEL_DB3_PIXELS = 0x0000001b,
16320SX_PERF_SEL_DB3_HALF_QUADS = 0x0000001c,
16321SX_PERF_SEL_DB3_PIXEL_STALL = 0x0000001d,
16322SX_PERF_SEL_DB3_PIXEL_IDLE = 0x0000001e,
16323SX_PERF_SEL_DB3_PRED_PIXELS = 0x0000001f,
16324SX_PERF_SEL_COL_BUSY = 0x00000020,
16325SX_PERF_SEL_POS_BUSY = 0x00000021,
16326SX_PERF_SEL_DB0_A2M_DISCARD_QUADS = 0x00000022,
16327SX_PERF_SEL_DB0_MRT0_BLEND_BYPASS = 0x00000023,
16328SX_PERF_SEL_DB0_MRT0_DONT_RD_DEST = 0x00000024,
16329SX_PERF_SEL_DB0_MRT0_DISCARD_SRC = 0x00000025,
16330SX_PERF_SEL_DB0_MRT0_SINGLE_QUADS = 0x00000026,
16331SX_PERF_SEL_DB0_MRT0_DOUBLE_QUADS = 0x00000027,
16332SX_PERF_SEL_DB0_MRT1_BLEND_BYPASS = 0x00000028,
16333SX_PERF_SEL_DB0_MRT1_DONT_RD_DEST = 0x00000029,
16334SX_PERF_SEL_DB0_MRT1_DISCARD_SRC = 0x0000002a,
16335SX_PERF_SEL_DB0_MRT1_SINGLE_QUADS = 0x0000002b,
16336SX_PERF_SEL_DB0_MRT1_DOUBLE_QUADS = 0x0000002c,
16337SX_PERF_SEL_DB0_MRT2_BLEND_BYPASS = 0x0000002d,
16338SX_PERF_SEL_DB0_MRT2_DONT_RD_DEST = 0x0000002e,
16339SX_PERF_SEL_DB0_MRT2_DISCARD_SRC = 0x0000002f,
16340SX_PERF_SEL_DB0_MRT2_SINGLE_QUADS = 0x00000030,
16341SX_PERF_SEL_DB0_MRT2_DOUBLE_QUADS = 0x00000031,
16342SX_PERF_SEL_DB0_MRT3_BLEND_BYPASS = 0x00000032,
16343SX_PERF_SEL_DB0_MRT3_DONT_RD_DEST = 0x00000033,
16344SX_PERF_SEL_DB0_MRT3_DISCARD_SRC = 0x00000034,
16345SX_PERF_SEL_DB0_MRT3_SINGLE_QUADS = 0x00000035,
16346SX_PERF_SEL_DB0_MRT3_DOUBLE_QUADS = 0x00000036,
16347SX_PERF_SEL_DB0_MRT4_BLEND_BYPASS = 0x00000037,
16348SX_PERF_SEL_DB0_MRT4_DONT_RD_DEST = 0x00000038,
16349SX_PERF_SEL_DB0_MRT4_DISCARD_SRC = 0x00000039,
16350SX_PERF_SEL_DB0_MRT4_SINGLE_QUADS = 0x0000003a,
16351SX_PERF_SEL_DB0_MRT4_DOUBLE_QUADS = 0x0000003b,
16352SX_PERF_SEL_DB0_MRT5_BLEND_BYPASS = 0x0000003c,
16353SX_PERF_SEL_DB0_MRT5_DONT_RD_DEST = 0x0000003d,
16354SX_PERF_SEL_DB0_MRT5_DISCARD_SRC = 0x0000003e,
16355SX_PERF_SEL_DB0_MRT5_SINGLE_QUADS = 0x0000003f,
16356SX_PERF_SEL_DB0_MRT5_DOUBLE_QUADS = 0x00000040,
16357SX_PERF_SEL_DB0_MRT6_BLEND_BYPASS = 0x00000041,
16358SX_PERF_SEL_DB0_MRT6_DONT_RD_DEST = 0x00000042,
16359SX_PERF_SEL_DB0_MRT6_DISCARD_SRC = 0x00000043,
16360SX_PERF_SEL_DB0_MRT6_SINGLE_QUADS = 0x00000044,
16361SX_PERF_SEL_DB0_MRT6_DOUBLE_QUADS = 0x00000045,
16362SX_PERF_SEL_DB0_MRT7_BLEND_BYPASS = 0x00000046,
16363SX_PERF_SEL_DB0_MRT7_DONT_RD_DEST = 0x00000047,
16364SX_PERF_SEL_DB0_MRT7_DISCARD_SRC = 0x00000048,
16365SX_PERF_SEL_DB0_MRT7_SINGLE_QUADS = 0x00000049,
16366SX_PERF_SEL_DB0_MRT7_DOUBLE_QUADS = 0x0000004a,
16367SX_PERF_SEL_DB1_A2M_DISCARD_QUADS = 0x0000004b,
16368SX_PERF_SEL_DB1_MRT0_BLEND_BYPASS = 0x0000004c,
16369SX_PERF_SEL_DB1_MRT0_DONT_RD_DEST = 0x0000004d,
16370SX_PERF_SEL_DB1_MRT0_DISCARD_SRC = 0x0000004e,
16371SX_PERF_SEL_DB1_MRT0_SINGLE_QUADS = 0x0000004f,
16372SX_PERF_SEL_DB1_MRT0_DOUBLE_QUADS = 0x00000050,
16373SX_PERF_SEL_DB1_MRT1_BLEND_BYPASS = 0x00000051,
16374SX_PERF_SEL_DB1_MRT1_DONT_RD_DEST = 0x00000052,
16375SX_PERF_SEL_DB1_MRT1_DISCARD_SRC = 0x00000053,
16376SX_PERF_SEL_DB1_MRT1_SINGLE_QUADS = 0x00000054,
16377SX_PERF_SEL_DB1_MRT1_DOUBLE_QUADS = 0x00000055,
16378SX_PERF_SEL_DB1_MRT2_BLEND_BYPASS = 0x00000056,
16379SX_PERF_SEL_DB1_MRT2_DONT_RD_DEST = 0x00000057,
16380SX_PERF_SEL_DB1_MRT2_DISCARD_SRC = 0x00000058,
16381SX_PERF_SEL_DB1_MRT2_SINGLE_QUADS = 0x00000059,
16382SX_PERF_SEL_DB1_MRT2_DOUBLE_QUADS = 0x0000005a,
16383SX_PERF_SEL_DB1_MRT3_BLEND_BYPASS = 0x0000005b,
16384SX_PERF_SEL_DB1_MRT3_DONT_RD_DEST = 0x0000005c,
16385SX_PERF_SEL_DB1_MRT3_DISCARD_SRC = 0x0000005d,
16386SX_PERF_SEL_DB1_MRT3_SINGLE_QUADS = 0x0000005e,
16387SX_PERF_SEL_DB1_MRT3_DOUBLE_QUADS = 0x0000005f,
16388SX_PERF_SEL_DB1_MRT4_BLEND_BYPASS = 0x00000060,
16389SX_PERF_SEL_DB1_MRT4_DONT_RD_DEST = 0x00000061,
16390SX_PERF_SEL_DB1_MRT4_DISCARD_SRC = 0x00000062,
16391SX_PERF_SEL_DB1_MRT4_SINGLE_QUADS = 0x00000063,
16392SX_PERF_SEL_DB1_MRT4_DOUBLE_QUADS = 0x00000064,
16393SX_PERF_SEL_DB1_MRT5_BLEND_BYPASS = 0x00000065,
16394SX_PERF_SEL_DB1_MRT5_DONT_RD_DEST = 0x00000066,
16395SX_PERF_SEL_DB1_MRT5_DISCARD_SRC = 0x00000067,
16396SX_PERF_SEL_DB1_MRT5_SINGLE_QUADS = 0x00000068,
16397SX_PERF_SEL_DB1_MRT5_DOUBLE_QUADS = 0x00000069,
16398SX_PERF_SEL_DB1_MRT6_BLEND_BYPASS = 0x0000006a,
16399SX_PERF_SEL_DB1_MRT6_DONT_RD_DEST = 0x0000006b,
16400SX_PERF_SEL_DB1_MRT6_DISCARD_SRC = 0x0000006c,
16401SX_PERF_SEL_DB1_MRT6_SINGLE_QUADS = 0x0000006d,
16402SX_PERF_SEL_DB1_MRT6_DOUBLE_QUADS = 0x0000006e,
16403SX_PERF_SEL_DB1_MRT7_BLEND_BYPASS = 0x0000006f,
16404SX_PERF_SEL_DB1_MRT7_DONT_RD_DEST = 0x00000070,
16405SX_PERF_SEL_DB1_MRT7_DISCARD_SRC = 0x00000071,
16406SX_PERF_SEL_DB1_MRT7_SINGLE_QUADS = 0x00000072,
16407SX_PERF_SEL_DB1_MRT7_DOUBLE_QUADS = 0x00000073,
16408SX_PERF_SEL_DB2_A2M_DISCARD_QUADS = 0x00000074,
16409SX_PERF_SEL_DB2_MRT0_BLEND_BYPASS = 0x00000075,
16410SX_PERF_SEL_DB2_MRT0_DONT_RD_DEST = 0x00000076,
16411SX_PERF_SEL_DB2_MRT0_DISCARD_SRC = 0x00000077,
16412SX_PERF_SEL_DB2_MRT0_SINGLE_QUADS = 0x00000078,
16413SX_PERF_SEL_DB2_MRT0_DOUBLE_QUADS = 0x00000079,
16414SX_PERF_SEL_DB2_MRT1_BLEND_BYPASS = 0x0000007a,
16415SX_PERF_SEL_DB2_MRT1_DONT_RD_DEST = 0x0000007b,
16416SX_PERF_SEL_DB2_MRT1_DISCARD_SRC = 0x0000007c,
16417SX_PERF_SEL_DB2_MRT1_SINGLE_QUADS = 0x0000007d,
16418SX_PERF_SEL_DB2_MRT1_DOUBLE_QUADS = 0x0000007e,
16419SX_PERF_SEL_DB2_MRT2_BLEND_BYPASS = 0x0000007f,
16420SX_PERF_SEL_DB2_MRT2_DONT_RD_DEST = 0x00000080,
16421SX_PERF_SEL_DB2_MRT2_DISCARD_SRC = 0x00000081,
16422SX_PERF_SEL_DB2_MRT2_SINGLE_QUADS = 0x00000082,
16423SX_PERF_SEL_DB2_MRT2_DOUBLE_QUADS = 0x00000083,
16424SX_PERF_SEL_DB2_MRT3_BLEND_BYPASS = 0x00000084,
16425SX_PERF_SEL_DB2_MRT3_DONT_RD_DEST = 0x00000085,
16426SX_PERF_SEL_DB2_MRT3_DISCARD_SRC = 0x00000086,
16427SX_PERF_SEL_DB2_MRT3_SINGLE_QUADS = 0x00000087,
16428SX_PERF_SEL_DB2_MRT3_DOUBLE_QUADS = 0x00000088,
16429SX_PERF_SEL_DB2_MRT4_BLEND_BYPASS = 0x00000089,
16430SX_PERF_SEL_DB2_MRT4_DONT_RD_DEST = 0x0000008a,
16431SX_PERF_SEL_DB2_MRT4_DISCARD_SRC = 0x0000008b,
16432SX_PERF_SEL_DB2_MRT4_SINGLE_QUADS = 0x0000008c,
16433SX_PERF_SEL_DB2_MRT4_DOUBLE_QUADS = 0x0000008d,
16434SX_PERF_SEL_DB2_MRT5_BLEND_BYPASS = 0x0000008e,
16435SX_PERF_SEL_DB2_MRT5_DONT_RD_DEST = 0x0000008f,
16436SX_PERF_SEL_DB2_MRT5_DISCARD_SRC = 0x00000090,
16437SX_PERF_SEL_DB2_MRT5_SINGLE_QUADS = 0x00000091,
16438SX_PERF_SEL_DB2_MRT5_DOUBLE_QUADS = 0x00000092,
16439SX_PERF_SEL_DB2_MRT6_BLEND_BYPASS = 0x00000093,
16440SX_PERF_SEL_DB2_MRT6_DONT_RD_DEST = 0x00000094,
16441SX_PERF_SEL_DB2_MRT6_DISCARD_SRC = 0x00000095,
16442SX_PERF_SEL_DB2_MRT6_SINGLE_QUADS = 0x00000096,
16443SX_PERF_SEL_DB2_MRT6_DOUBLE_QUADS = 0x00000097,
16444SX_PERF_SEL_DB2_MRT7_BLEND_BYPASS = 0x00000098,
16445SX_PERF_SEL_DB2_MRT7_DONT_RD_DEST = 0x00000099,
16446SX_PERF_SEL_DB2_MRT7_DISCARD_SRC = 0x0000009a,
16447SX_PERF_SEL_DB2_MRT7_SINGLE_QUADS = 0x0000009b,
16448SX_PERF_SEL_DB2_MRT7_DOUBLE_QUADS = 0x0000009c,
16449SX_PERF_SEL_DB3_A2M_DISCARD_QUADS = 0x0000009d,
16450SX_PERF_SEL_DB3_MRT0_BLEND_BYPASS = 0x0000009e,
16451SX_PERF_SEL_DB3_MRT0_DONT_RD_DEST = 0x0000009f,
16452SX_PERF_SEL_DB3_MRT0_DISCARD_SRC = 0x000000a0,
16453SX_PERF_SEL_DB3_MRT0_SINGLE_QUADS = 0x000000a1,
16454SX_PERF_SEL_DB3_MRT0_DOUBLE_QUADS = 0x000000a2,
16455SX_PERF_SEL_DB3_MRT1_BLEND_BYPASS = 0x000000a3,
16456SX_PERF_SEL_DB3_MRT1_DONT_RD_DEST = 0x000000a4,
16457SX_PERF_SEL_DB3_MRT1_DISCARD_SRC = 0x000000a5,
16458SX_PERF_SEL_DB3_MRT1_SINGLE_QUADS = 0x000000a6,
16459SX_PERF_SEL_DB3_MRT1_DOUBLE_QUADS = 0x000000a7,
16460SX_PERF_SEL_DB3_MRT2_BLEND_BYPASS = 0x000000a8,
16461SX_PERF_SEL_DB3_MRT2_DONT_RD_DEST = 0x000000a9,
16462SX_PERF_SEL_DB3_MRT2_DISCARD_SRC = 0x000000aa,
16463SX_PERF_SEL_DB3_MRT2_SINGLE_QUADS = 0x000000ab,
16464SX_PERF_SEL_DB3_MRT2_DOUBLE_QUADS = 0x000000ac,
16465SX_PERF_SEL_DB3_MRT3_BLEND_BYPASS = 0x000000ad,
16466SX_PERF_SEL_DB3_MRT3_DONT_RD_DEST = 0x000000ae,
16467SX_PERF_SEL_DB3_MRT3_DISCARD_SRC = 0x000000af,
16468SX_PERF_SEL_DB3_MRT3_SINGLE_QUADS = 0x000000b0,
16469SX_PERF_SEL_DB3_MRT3_DOUBLE_QUADS = 0x000000b1,
16470SX_PERF_SEL_DB3_MRT4_BLEND_BYPASS = 0x000000b2,
16471SX_PERF_SEL_DB3_MRT4_DONT_RD_DEST = 0x000000b3,
16472SX_PERF_SEL_DB3_MRT4_DISCARD_SRC = 0x000000b4,
16473SX_PERF_SEL_DB3_MRT4_SINGLE_QUADS = 0x000000b5,
16474SX_PERF_SEL_DB3_MRT4_DOUBLE_QUADS = 0x000000b6,
16475SX_PERF_SEL_DB3_MRT5_BLEND_BYPASS = 0x000000b7,
16476SX_PERF_SEL_DB3_MRT5_DONT_RD_DEST = 0x000000b8,
16477SX_PERF_SEL_DB3_MRT5_DISCARD_SRC = 0x000000b9,
16478SX_PERF_SEL_DB3_MRT5_SINGLE_QUADS = 0x000000ba,
16479SX_PERF_SEL_DB3_MRT5_DOUBLE_QUADS = 0x000000bb,
16480SX_PERF_SEL_DB3_MRT6_BLEND_BYPASS = 0x000000bc,
16481SX_PERF_SEL_DB3_MRT6_DONT_RD_DEST = 0x000000bd,
16482SX_PERF_SEL_DB3_MRT6_DISCARD_SRC = 0x000000be,
16483SX_PERF_SEL_DB3_MRT6_SINGLE_QUADS = 0x000000bf,
16484SX_PERF_SEL_DB3_MRT6_DOUBLE_QUADS = 0x000000c0,
16485SX_PERF_SEL_DB3_MRT7_BLEND_BYPASS = 0x000000c1,
16486SX_PERF_SEL_DB3_MRT7_DONT_RD_DEST = 0x000000c2,
16487SX_PERF_SEL_DB3_MRT7_DISCARD_SRC = 0x000000c3,
16488SX_PERF_SEL_DB3_MRT7_SINGLE_QUADS = 0x000000c4,
16489SX_PERF_SEL_DB3_MRT7_DOUBLE_QUADS = 0x000000c5,
16490SX_PERF_SEL_PA_REQ_LATENCY = 0x000000c6,
16491SX_PERF_SEL_POS_SCBD_STALL = 0x000000c7,
16492SX_PERF_SEL_COL_SCBD_STALL = 0x000000c8,
16493SX_PERF_SEL_CLOCK_DROP_STALL = 0x000000c9,
16494SX_PERF_SEL_GATE_EN5 = 0x000000ca,
16495SX_PERF_SEL_GATE_EN6 = 0x000000cb,
16496SX_PERF_SEL_DB0_SIZE = 0x000000cc,
16497SX_PERF_SEL_DB1_SIZE = 0x000000cd,
16498SX_PERF_SEL_DB2_SIZE = 0x000000ce,
16499SX_PERF_SEL_DB3_SIZE = 0x000000cf,
16500SX_PERF_SEL_SPLITMODE = 0x000000d0,
16501SX_PERF_SEL_COL_SCBD0_STALL = 0x000000d1,
16502SX_PERF_SEL_COL_SCBD1_STALL = 0x000000d2,
16503SX_PERF_SEL_IDX_STALL_CYCLES = 0x000000d3,
16504SX_PERF_SEL_IDX_IDLE_CYCLES = 0x000000d4,
16505SX_PERF_SEL_IDX_REQ = 0x000000d5,
16506SX_PERF_SEL_IDX_RET = 0x000000d6,
16507SX_PERF_SEL_IDX_REQ_LATENCY = 0x000000d7,
16508SX_PERF_SEL_IDX_SCBD_STALL = 0x000000d8,
16509SX_PERF_SEL_GATE_EN7 = 0x000000d9,
16510SX_PERF_SEL_GATE_EN8 = 0x000000da,
16511SX_PERF_SEL_SH_IDX_STARVE = 0x000000db,
16512SX_PERF_SEL_IDX_BUSY = 0x000000dc,
16513} SX_PERFCOUNTER_VALS;
16514
16515/*******************************************************
16516 * DB Enums
16517 *******************************************************/
16518
16519/*
16520 * ForceControl enum
16521 */
16522
16523typedef enum ForceControl {
16524FORCE_OFF = 0x00000000,
16525FORCE_ENABLE = 0x00000001,
16526FORCE_DISABLE = 0x00000002,
16527FORCE_RESERVED = 0x00000003,
16528} ForceControl;
16529
16530/*
16531 * ZSamplePosition enum
16532 */
16533
16534typedef enum ZSamplePosition {
16535Z_SAMPLE_CENTER = 0x00000000,
16536Z_SAMPLE_CENTROID = 0x00000001,
16537} ZSamplePosition;
16538
16539/*
16540 * ZOrder enum
16541 */
16542
16543typedef enum ZOrder {
16544LATE_Z = 0x00000000,
16545EARLY_Z_THEN_LATE_Z = 0x00000001,
16546RE_Z = 0x00000002,
16547EARLY_Z_THEN_RE_Z = 0x00000003,
16548} ZOrder;
16549
16550/*
16551 * ZpassControl enum
16552 */
16553
16554typedef enum ZpassControl {
16555ZPASS_DISABLE = 0x00000000,
16556ZPASS_SAMPLES = 0x00000001,
16557ZPASS_PIXELS = 0x00000002,
16558} ZpassControl;
16559
16560/*
16561 * ZModeForce enum
16562 */
16563
16564typedef enum ZModeForce {
16565NO_FORCE = 0x00000000,
16566FORCE_EARLY_Z = 0x00000001,
16567FORCE_LATE_Z = 0x00000002,
16568FORCE_RE_Z = 0x00000003,
16569} ZModeForce;
16570
16571/*
16572 * ZLimitSumm enum
16573 */
16574
16575typedef enum ZLimitSumm {
16576FORCE_SUMM_OFF = 0x00000000,
16577FORCE_SUMM_MINZ = 0x00000001,
16578FORCE_SUMM_MAXZ = 0x00000002,
16579FORCE_SUMM_BOTH = 0x00000003,
16580} ZLimitSumm;
16581
16582/*
16583 * CompareFrag enum
16584 */
16585
16586typedef enum CompareFrag {
16587FRAG_NEVER = 0x00000000,
16588FRAG_LESS = 0x00000001,
16589FRAG_EQUAL = 0x00000002,
16590FRAG_LEQUAL = 0x00000003,
16591FRAG_GREATER = 0x00000004,
16592FRAG_NOTEQUAL = 0x00000005,
16593FRAG_GEQUAL = 0x00000006,
16594FRAG_ALWAYS = 0x00000007,
16595} CompareFrag;
16596
16597/*
16598 * StencilOp enum
16599 */
16600
16601typedef enum StencilOp {
16602STENCIL_KEEP = 0x00000000,
16603STENCIL_ZERO = 0x00000001,
16604STENCIL_ONES = 0x00000002,
16605STENCIL_REPLACE_TEST = 0x00000003,
16606STENCIL_REPLACE_OP = 0x00000004,
16607STENCIL_ADD_CLAMP = 0x00000005,
16608STENCIL_SUB_CLAMP = 0x00000006,
16609STENCIL_INVERT = 0x00000007,
16610STENCIL_ADD_WRAP = 0x00000008,
16611STENCIL_SUB_WRAP = 0x00000009,
16612STENCIL_AND = 0x0000000a,
16613STENCIL_OR = 0x0000000b,
16614STENCIL_XOR = 0x0000000c,
16615STENCIL_NAND = 0x0000000d,
16616STENCIL_NOR = 0x0000000e,
16617STENCIL_XNOR = 0x0000000f,
16618} StencilOp;
16619
16620/*
16621 * ConservativeZExport enum
16622 */
16623
16624typedef enum ConservativeZExport {
16625EXPORT_ANY_Z = 0x00000000,
16626EXPORT_LESS_THAN_Z = 0x00000001,
16627EXPORT_GREATER_THAN_Z = 0x00000002,
16628EXPORT_RESERVED = 0x00000003,
16629} ConservativeZExport;
16630
16631/*
16632 * DbPSLControl enum
16633 */
16634
16635typedef enum DbPSLControl {
16636PSLC_AUTO = 0x00000000,
16637PSLC_ON_HANG_ONLY = 0x00000001,
16638PSLC_ASAP = 0x00000002,
16639PSLC_COUNTDOWN = 0x00000003,
16640} DbPSLControl;
16641
16642/*
16643 * DbPRTFaultBehavior enum
16644 */
16645
16646typedef enum DbPRTFaultBehavior {
16647FAULT_ZERO = 0x00000000,
16648FAULT_ONE = 0x00000001,
16649FAULT_FAIL = 0x00000002,
16650FAULT_PASS = 0x00000003,
16651} DbPRTFaultBehavior;
16652
16653/*
16654 * PerfCounter_Vals enum
16655 */
16656
16657typedef enum PerfCounter_Vals {
16658DB_PERF_SEL_SC_DB_tile_sends = 0x00000000,
16659DB_PERF_SEL_SC_DB_tile_busy = 0x00000001,
16660DB_PERF_SEL_SC_DB_tile_stalls = 0x00000002,
16661DB_PERF_SEL_SC_DB_tile_events = 0x00000003,
16662DB_PERF_SEL_SC_DB_tile_tiles = 0x00000004,
16663DB_PERF_SEL_SC_DB_tile_covered = 0x00000005,
16664DB_PERF_SEL_hiz_tc_read_starved = 0x00000006,
16665DB_PERF_SEL_hiz_tc_write_stall = 0x00000007,
16666DB_PERF_SEL_hiz_tile_culled = 0x00000008,
16667DB_PERF_SEL_his_tile_culled = 0x00000009,
16668DB_PERF_SEL_DB_SC_tile_sends = 0x0000000a,
16669DB_PERF_SEL_DB_SC_tile_busy = 0x0000000b,
16670DB_PERF_SEL_DB_SC_tile_stalls = 0x0000000c,
16671DB_PERF_SEL_DB_SC_tile_df_stalls = 0x0000000d,
16672DB_PERF_SEL_DB_SC_tile_tiles = 0x0000000e,
16673DB_PERF_SEL_DB_SC_tile_culled = 0x0000000f,
16674DB_PERF_SEL_DB_SC_tile_hier_kill = 0x00000010,
16675DB_PERF_SEL_DB_SC_tile_fast_ops = 0x00000011,
16676DB_PERF_SEL_DB_SC_tile_no_ops = 0x00000012,
16677DB_PERF_SEL_DB_SC_tile_tile_rate = 0x00000013,
16678DB_PERF_SEL_DB_SC_tile_ssaa_kill = 0x00000014,
16679DB_PERF_SEL_DB_SC_tile_fast_z_ops = 0x00000015,
16680DB_PERF_SEL_DB_SC_tile_fast_stencil_ops = 0x00000016,
16681DB_PERF_SEL_SC_DB_quad_sends = 0x00000017,
16682DB_PERF_SEL_SC_DB_quad_busy = 0x00000018,
16683DB_PERF_SEL_SC_DB_quad_squads = 0x00000019,
16684DB_PERF_SEL_SC_DB_quad_tiles = 0x0000001a,
16685DB_PERF_SEL_SC_DB_quad_pixels = 0x0000001b,
16686DB_PERF_SEL_SC_DB_quad_killed_tiles = 0x0000001c,
16687DB_PERF_SEL_DB_SC_quad_sends = 0x0000001d,
16688DB_PERF_SEL_DB_SC_quad_busy = 0x0000001e,
16689DB_PERF_SEL_DB_SC_quad_stalls = 0x0000001f,
16690DB_PERF_SEL_DB_SC_quad_tiles = 0x00000020,
16691DB_PERF_SEL_DB_SC_quad_lit_quad = 0x00000021,
16692DB_PERF_SEL_DB_CB_tile_sends = 0x00000022,
16693DB_PERF_SEL_DB_CB_tile_busy = 0x00000023,
16694DB_PERF_SEL_DB_CB_tile_stalls = 0x00000024,
16695DB_PERF_SEL_SX_DB_quad_sends = 0x00000025,
16696DB_PERF_SEL_SX_DB_quad_busy = 0x00000026,
16697DB_PERF_SEL_SX_DB_quad_stalls = 0x00000027,
16698DB_PERF_SEL_SX_DB_quad_quads = 0x00000028,
16699DB_PERF_SEL_SX_DB_quad_pixels = 0x00000029,
16700DB_PERF_SEL_SX_DB_quad_exports = 0x0000002a,
16701DB_PERF_SEL_SH_quads_outstanding_sum = 0x0000002b,
16702DB_PERF_SEL_DB_CB_lquad_sends = 0x0000002c,
16703DB_PERF_SEL_DB_CB_lquad_busy = 0x0000002d,
16704DB_PERF_SEL_DB_CB_lquad_stalls = 0x0000002e,
16705DB_PERF_SEL_DB_CB_lquad_quads = 0x0000002f,
16706DB_PERF_SEL_tile_rd_sends = 0x00000030,
16707DB_PERF_SEL_mi_tile_rd_outstanding_sum = 0x00000031,
16708DB_PERF_SEL_quad_rd_sends = 0x00000032,
16709DB_PERF_SEL_quad_rd_busy = 0x00000033,
16710DB_PERF_SEL_quad_rd_mi_stall = 0x00000034,
16711DB_PERF_SEL_quad_rd_rw_collision = 0x00000035,
16712DB_PERF_SEL_quad_rd_tag_stall = 0x00000036,
16713DB_PERF_SEL_quad_rd_32byte_reqs = 0x00000037,
16714DB_PERF_SEL_quad_rd_panic = 0x00000038,
16715DB_PERF_SEL_mi_quad_rd_outstanding_sum = 0x00000039,
16716DB_PERF_SEL_quad_rdret_sends = 0x0000003a,
16717DB_PERF_SEL_quad_rdret_busy = 0x0000003b,
16718DB_PERF_SEL_tile_wr_sends = 0x0000003c,
16719DB_PERF_SEL_tile_wr_acks = 0x0000003d,
16720DB_PERF_SEL_mi_tile_wr_outstanding_sum = 0x0000003e,
16721DB_PERF_SEL_quad_wr_sends = 0x0000003f,
16722DB_PERF_SEL_quad_wr_busy = 0x00000040,
16723DB_PERF_SEL_quad_wr_mi_stall = 0x00000041,
16724DB_PERF_SEL_quad_wr_coherency_stall = 0x00000042,
16725DB_PERF_SEL_quad_wr_acks = 0x00000043,
16726DB_PERF_SEL_mi_quad_wr_outstanding_sum = 0x00000044,
16727DB_PERF_SEL_Tile_Cache_misses = 0x00000045,
16728DB_PERF_SEL_Tile_Cache_hits = 0x00000046,
16729DB_PERF_SEL_Tile_Cache_flushes = 0x00000047,
16730DB_PERF_SEL_Tile_Cache_surface_stall = 0x00000048,
16731DB_PERF_SEL_Tile_Cache_starves = 0x00000049,
16732DB_PERF_SEL_Tile_Cache_mem_return_starve = 0x0000004a,
16733DB_PERF_SEL_tcp_dispatcher_reads = 0x0000004b,
16734DB_PERF_SEL_tcp_prefetcher_reads = 0x0000004c,
16735DB_PERF_SEL_tcp_preloader_reads = 0x0000004d,
16736DB_PERF_SEL_tcp_dispatcher_flushes = 0x0000004e,
16737DB_PERF_SEL_tcp_prefetcher_flushes = 0x0000004f,
16738DB_PERF_SEL_tcp_preloader_flushes = 0x00000050,
16739DB_PERF_SEL_Depth_Tile_Cache_sends = 0x00000051,
16740DB_PERF_SEL_Depth_Tile_Cache_busy = 0x00000052,
16741DB_PERF_SEL_Depth_Tile_Cache_starves = 0x00000053,
16742DB_PERF_SEL_Depth_Tile_Cache_dtile_locked = 0x00000054,
16743DB_PERF_SEL_Depth_Tile_Cache_alloc_stall = 0x00000055,
16744DB_PERF_SEL_Depth_Tile_Cache_misses = 0x00000056,
16745DB_PERF_SEL_Depth_Tile_Cache_hits = 0x00000057,
16746DB_PERF_SEL_Depth_Tile_Cache_flushes = 0x00000058,
16747DB_PERF_SEL_Depth_Tile_Cache_noop_tile = 0x00000059,
16748DB_PERF_SEL_Depth_Tile_Cache_detailed_noop = 0x0000005a,
16749DB_PERF_SEL_Depth_Tile_Cache_event = 0x0000005b,
16750DB_PERF_SEL_Depth_Tile_Cache_tile_frees = 0x0000005c,
16751DB_PERF_SEL_Depth_Tile_Cache_data_frees = 0x0000005d,
16752DB_PERF_SEL_Depth_Tile_Cache_mem_return_starve = 0x0000005e,
16753DB_PERF_SEL_Stencil_Cache_misses = 0x0000005f,
16754DB_PERF_SEL_Stencil_Cache_hits = 0x00000060,
16755DB_PERF_SEL_Stencil_Cache_flushes = 0x00000061,
16756DB_PERF_SEL_Stencil_Cache_starves = 0x00000062,
16757DB_PERF_SEL_Stencil_Cache_frees = 0x00000063,
16758DB_PERF_SEL_Z_Cache_separate_Z_misses = 0x00000064,
16759DB_PERF_SEL_Z_Cache_separate_Z_hits = 0x00000065,
16760DB_PERF_SEL_Z_Cache_separate_Z_flushes = 0x00000066,
16761DB_PERF_SEL_Z_Cache_separate_Z_starves = 0x00000067,
16762DB_PERF_SEL_Z_Cache_pmask_misses = 0x00000068,
16763DB_PERF_SEL_Z_Cache_pmask_hits = 0x00000069,
16764DB_PERF_SEL_Z_Cache_pmask_flushes = 0x0000006a,
16765DB_PERF_SEL_Z_Cache_pmask_starves = 0x0000006b,
16766DB_PERF_SEL_Z_Cache_frees = 0x0000006c,
16767DB_PERF_SEL_Plane_Cache_misses = 0x0000006d,
16768DB_PERF_SEL_Plane_Cache_hits = 0x0000006e,
16769DB_PERF_SEL_Plane_Cache_flushes = 0x0000006f,
16770DB_PERF_SEL_Plane_Cache_starves = 0x00000070,
16771DB_PERF_SEL_Plane_Cache_frees = 0x00000071,
16772DB_PERF_SEL_flush_expanded_stencil = 0x00000072,
16773DB_PERF_SEL_flush_compressed_stencil = 0x00000073,
16774DB_PERF_SEL_flush_single_stencil = 0x00000074,
16775DB_PERF_SEL_planes_flushed = 0x00000075,
16776DB_PERF_SEL_flush_1plane = 0x00000076,
16777DB_PERF_SEL_flush_2plane = 0x00000077,
16778DB_PERF_SEL_flush_3plane = 0x00000078,
16779DB_PERF_SEL_flush_4plane = 0x00000079,
16780DB_PERF_SEL_flush_5plane = 0x0000007a,
16781DB_PERF_SEL_flush_6plane = 0x0000007b,
16782DB_PERF_SEL_flush_7plane = 0x0000007c,
16783DB_PERF_SEL_flush_8plane = 0x0000007d,
16784DB_PERF_SEL_flush_9plane = 0x0000007e,
16785DB_PERF_SEL_flush_10plane = 0x0000007f,
16786DB_PERF_SEL_flush_11plane = 0x00000080,
16787DB_PERF_SEL_flush_12plane = 0x00000081,
16788DB_PERF_SEL_flush_13plane = 0x00000082,
16789DB_PERF_SEL_flush_14plane = 0x00000083,
16790DB_PERF_SEL_flush_15plane = 0x00000084,
16791DB_PERF_SEL_flush_16plane = 0x00000085,
16792DB_PERF_SEL_flush_expanded_z = 0x00000086,
16793DB_PERF_SEL_earlyZ_waiting_for_postZ_done = 0x00000087,
16794DB_PERF_SEL_reZ_waiting_for_postZ_done = 0x00000088,
16795DB_PERF_SEL_dk_tile_sends = 0x00000089,
16796DB_PERF_SEL_dk_tile_busy = 0x0000008a,
16797DB_PERF_SEL_dk_tile_quad_starves = 0x0000008b,
16798DB_PERF_SEL_dk_tile_stalls = 0x0000008c,
16799DB_PERF_SEL_dk_squad_sends = 0x0000008d,
16800DB_PERF_SEL_dk_squad_busy = 0x0000008e,
16801DB_PERF_SEL_dk_squad_stalls = 0x0000008f,
16802DB_PERF_SEL_Op_Pipe_Busy = 0x00000090,
16803DB_PERF_SEL_Op_Pipe_MC_Read_stall = 0x00000091,
16804DB_PERF_SEL_qc_busy = 0x00000092,
16805DB_PERF_SEL_qc_xfc = 0x00000093,
16806DB_PERF_SEL_qc_conflicts = 0x00000094,
16807DB_PERF_SEL_qc_full_stall = 0x00000095,
16808DB_PERF_SEL_qc_in_preZ_tile_stalls_postZ = 0x00000096,
16809DB_PERF_SEL_qc_in_postZ_tile_stalls_preZ = 0x00000097,
16810DB_PERF_SEL_tsc_insert_summarize_stall = 0x00000098,
16811DB_PERF_SEL_tl_busy = 0x00000099,
16812DB_PERF_SEL_tl_dtc_read_starved = 0x0000009a,
16813DB_PERF_SEL_tl_z_fetch_stall = 0x0000009b,
16814DB_PERF_SEL_tl_stencil_stall = 0x0000009c,
16815DB_PERF_SEL_tl_z_decompress_stall = 0x0000009d,
16816DB_PERF_SEL_tl_stencil_locked_stall = 0x0000009e,
16817DB_PERF_SEL_tl_events = 0x0000009f,
16818DB_PERF_SEL_tl_summarize_squads = 0x000000a0,
16819DB_PERF_SEL_tl_flush_expand_squads = 0x000000a1,
16820DB_PERF_SEL_tl_expand_squads = 0x000000a2,
16821DB_PERF_SEL_tl_preZ_squads = 0x000000a3,
16822DB_PERF_SEL_tl_postZ_squads = 0x000000a4,
16823DB_PERF_SEL_tl_preZ_noop_squads = 0x000000a5,
16824DB_PERF_SEL_tl_postZ_noop_squads = 0x000000a6,
16825DB_PERF_SEL_tl_tile_ops = 0x000000a7,
16826DB_PERF_SEL_tl_in_xfc = 0x000000a8,
16827DB_PERF_SEL_tl_in_single_stencil_expand_stall = 0x000000a9,
16828DB_PERF_SEL_tl_in_fast_z_stall = 0x000000aa,
16829DB_PERF_SEL_tl_out_xfc = 0x000000ab,
16830DB_PERF_SEL_tl_out_squads = 0x000000ac,
16831DB_PERF_SEL_zf_plane_multicycle = 0x000000ad,
16832DB_PERF_SEL_PostZ_Samples_passing_Z = 0x000000ae,
16833DB_PERF_SEL_PostZ_Samples_failing_Z = 0x000000af,
16834DB_PERF_SEL_PostZ_Samples_failing_S = 0x000000b0,
16835DB_PERF_SEL_PreZ_Samples_passing_Z = 0x000000b1,
16836DB_PERF_SEL_PreZ_Samples_failing_Z = 0x000000b2,
16837DB_PERF_SEL_PreZ_Samples_failing_S = 0x000000b3,
16838DB_PERF_SEL_ts_tc_update_stall = 0x000000b4,
16839DB_PERF_SEL_sc_kick_start = 0x000000b5,
16840DB_PERF_SEL_sc_kick_end = 0x000000b6,
16841DB_PERF_SEL_clock_reg_active = 0x000000b7,
16842DB_PERF_SEL_clock_main_active = 0x000000b8,
16843DB_PERF_SEL_clock_mem_export_active = 0x000000b9,
16844DB_PERF_SEL_esr_ps_out_busy = 0x000000ba,
16845DB_PERF_SEL_esr_ps_lqf_busy = 0x000000bb,
16846DB_PERF_SEL_esr_ps_lqf_stall = 0x000000bc,
16847DB_PERF_SEL_etr_out_send = 0x000000bd,
16848DB_PERF_SEL_etr_out_busy = 0x000000be,
16849DB_PERF_SEL_etr_out_ltile_probe_fifo_full_stall = 0x000000bf,
16850DB_PERF_SEL_etr_out_cb_tile_stall = 0x000000c0,
16851DB_PERF_SEL_etr_out_esr_stall = 0x000000c1,
16852DB_PERF_SEL_esr_ps_sqq_busy = 0x000000c2,
16853DB_PERF_SEL_esr_ps_sqq_stall = 0x000000c3,
16854DB_PERF_SEL_esr_eot_fwd_busy = 0x000000c4,
16855DB_PERF_SEL_esr_eot_fwd_holding_squad = 0x000000c5,
16856DB_PERF_SEL_esr_eot_fwd_forward = 0x000000c6,
16857DB_PERF_SEL_esr_sqq_zi_busy = 0x000000c7,
16858DB_PERF_SEL_esr_sqq_zi_stall = 0x000000c8,
16859DB_PERF_SEL_postzl_sq_pt_busy = 0x000000c9,
16860DB_PERF_SEL_postzl_sq_pt_stall = 0x000000ca,
16861DB_PERF_SEL_postzl_se_busy = 0x000000cb,
16862DB_PERF_SEL_postzl_se_stall = 0x000000cc,
16863DB_PERF_SEL_postzl_partial_launch = 0x000000cd,
16864DB_PERF_SEL_postzl_full_launch = 0x000000ce,
16865DB_PERF_SEL_postzl_partial_waiting = 0x000000cf,
16866DB_PERF_SEL_postzl_tile_mem_stall = 0x000000d0,
16867DB_PERF_SEL_postzl_tile_init_stall = 0x000000d1,
16868DB_PERF_SEL_prezl_tile_mem_stall = 0x000000d2,
16869DB_PERF_SEL_prezl_tile_init_stall = 0x000000d3,
16870DB_PERF_SEL_dtt_sm_clash_stall = 0x000000d4,
16871DB_PERF_SEL_dtt_sm_slot_stall = 0x000000d5,
16872DB_PERF_SEL_dtt_sm_miss_stall = 0x000000d6,
16873DB_PERF_SEL_mi_rdreq_busy = 0x000000d7,
16874DB_PERF_SEL_mi_rdreq_stall = 0x000000d8,
16875DB_PERF_SEL_mi_wrreq_busy = 0x000000d9,
16876DB_PERF_SEL_mi_wrreq_stall = 0x000000da,
16877DB_PERF_SEL_recomp_tile_to_1zplane_no_fastop = 0x000000db,
16878DB_PERF_SEL_dkg_tile_rate_tile = 0x000000dc,
16879DB_PERF_SEL_prezl_src_in_sends = 0x000000dd,
16880DB_PERF_SEL_prezl_src_in_stall = 0x000000de,
16881DB_PERF_SEL_prezl_src_in_squads = 0x000000df,
16882DB_PERF_SEL_prezl_src_in_squads_unrolled = 0x000000e0,
16883DB_PERF_SEL_prezl_src_in_tile_rate = 0x000000e1,
16884DB_PERF_SEL_prezl_src_in_tile_rate_unrolled = 0x000000e2,
16885DB_PERF_SEL_prezl_src_out_stall = 0x000000e3,
16886DB_PERF_SEL_postzl_src_in_sends = 0x000000e4,
16887DB_PERF_SEL_postzl_src_in_stall = 0x000000e5,
16888DB_PERF_SEL_postzl_src_in_squads = 0x000000e6,
16889DB_PERF_SEL_postzl_src_in_squads_unrolled = 0x000000e7,
16890DB_PERF_SEL_postzl_src_in_tile_rate = 0x000000e8,
16891DB_PERF_SEL_postzl_src_in_tile_rate_unrolled = 0x000000e9,
16892DB_PERF_SEL_postzl_src_out_stall = 0x000000ea,
16893DB_PERF_SEL_esr_ps_src_in_sends = 0x000000eb,
16894DB_PERF_SEL_esr_ps_src_in_stall = 0x000000ec,
16895DB_PERF_SEL_esr_ps_src_in_squads = 0x000000ed,
16896DB_PERF_SEL_esr_ps_src_in_squads_unrolled = 0x000000ee,
16897DB_PERF_SEL_esr_ps_src_in_tile_rate = 0x000000ef,
16898DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled = 0x000000f0,
16899DB_PERF_SEL_esr_ps_src_in_tile_rate_unrolled_to_pixel_rate = 0x000000f1,
16900DB_PERF_SEL_esr_ps_src_out_stall = 0x000000f2,
16901DB_PERF_SEL_depth_bounds_tile_culled = 0x000000f3,
16902DB_PERF_SEL_PreZ_Samples_failing_DB = 0x000000f4,
16903DB_PERF_SEL_PostZ_Samples_failing_DB = 0x000000f5,
16904DB_PERF_SEL_flush_compressed = 0x000000f6,
16905DB_PERF_SEL_flush_plane_le4 = 0x000000f7,
16906DB_PERF_SEL_tiles_z_fully_summarized = 0x000000f8,
16907DB_PERF_SEL_tiles_stencil_fully_summarized = 0x000000f9,
16908DB_PERF_SEL_tiles_z_clear_on_expclear = 0x000000fa,
16909DB_PERF_SEL_tiles_s_clear_on_expclear = 0x000000fb,
16910DB_PERF_SEL_tiles_decomp_on_expclear = 0x000000fc,
16911DB_PERF_SEL_tiles_compressed_to_decompressed = 0x000000fd,
16912DB_PERF_SEL_Op_Pipe_Prez_Busy = 0x000000fe,
16913DB_PERF_SEL_Op_Pipe_Postz_Busy = 0x000000ff,
16914DB_PERF_SEL_di_dt_stall = 0x00000100,
16915DB_PERF_SEL_DB_SC_quad_lit_quad_pre_invoke = 0x00000101,
16916DB_PERF_SEL_DB_SC_s_tile_rate = 0x00000102,
16917DB_PERF_SEL_DB_SC_c_tile_rate = 0x00000103,
16918DB_PERF_SEL_DB_SC_z_tile_rate = 0x00000104,
16919Spare_261 = 0x00000105,
16920DB_PERF_SEL_DB_CB_lquad_export_quads = 0x00000106,
16921DB_PERF_SEL_DB_CB_lquad_double_format = 0x00000107,
16922DB_PERF_SEL_DB_CB_lquad_fast_format = 0x00000108,
16923DB_PERF_SEL_DB_CB_lquad_slow_format = 0x00000109,
16924DB_PERF_SEL_CB_DB_rdreq_sends = 0x0000010a,
16925DB_PERF_SEL_CB_DB_rdreq_prt_sends = 0x0000010b,
16926DB_PERF_SEL_CB_DB_wrreq_sends = 0x0000010c,
16927DB_PERF_SEL_CB_DB_wrreq_prt_sends = 0x0000010d,
16928DB_PERF_SEL_DB_CB_rdret_ack = 0x0000010e,
16929DB_PERF_SEL_DB_CB_rdret_nack = 0x0000010f,
16930DB_PERF_SEL_DB_CB_wrret_ack = 0x00000110,
16931DB_PERF_SEL_DB_CB_wrret_nack = 0x00000111,
16932DB_PERF_SEL_DFSM_Stall_opmode_change = 0x00000112,
16933DB_PERF_SEL_DFSM_Stall_cam_fifo = 0x00000113,
16934DB_PERF_SEL_DFSM_Stall_bypass_fifo = 0x00000114,
16935DB_PERF_SEL_DFSM_Stall_retained_tile_fifo = 0x00000115,
16936DB_PERF_SEL_DFSM_Stall_control_fifo = 0x00000116,
16937DB_PERF_SEL_DFSM_Stall_overflow_counter = 0x00000117,
16938DB_PERF_SEL_DFSM_Stall_pops_stall_overflow = 0x00000118,
16939DB_PERF_SEL_DFSM_Stall_pops_stall_self_flush = 0x00000119,
16940DB_PERF_SEL_DFSM_Stall_middle_output = 0x0000011a,
16941DB_PERF_SEL_DFSM_Stall_stalling_general = 0x0000011b,
16942Spare_285 = 0x0000011c,
16943Spare_286 = 0x0000011d,
16944DB_PERF_SEL_DFSM_prez_killed_squad = 0x0000011e,
16945DB_PERF_SEL_DFSM_squads_in = 0x0000011f,
16946DB_PERF_SEL_DFSM_full_cleared_squads_out = 0x00000120,
16947DB_PERF_SEL_DFSM_quads_in = 0x00000121,
16948DB_PERF_SEL_DFSM_fully_cleared_quads_out = 0x00000122,
16949DB_PERF_SEL_DFSM_lit_pixels_in = 0x00000123,
16950DB_PERF_SEL_DFSM_fully_cleared_pixels_out = 0x00000124,
16951DB_PERF_SEL_DFSM_lit_samples_in = 0x00000125,
16952DB_PERF_SEL_DFSM_lit_samples_out = 0x00000126,
16953DB_PERF_SEL_DFSM_evicted_tiles_above_watermark = 0x00000127,
16954DB_PERF_SEL_DFSM_cant_accept_squads_but_not_stalled_by_downstream = 0x00000128,
16955DB_PERF_SEL_DFSM_stalled_by_downstream = 0x00000129,
16956DB_PERF_SEL_DFSM_evicted_squads_above_watermark = 0x0000012a,
16957DB_PERF_SEL_DFSM_collisions_due_to_POPS_overflow = 0x0000012b,
16958DB_PERF_SEL_DFSM_collisions_detected_within_POPS_FIFO = 0x0000012c,
16959DB_PERF_SEL_DFSM_evicted_squads_due_to_prim_watermark = 0x0000012d,
16960DB_PERF_SEL_MI_tile_req_wrack_counter_stall = 0x0000012e,
16961DB_PERF_SEL_MI_quad_req_wrack_counter_stall = 0x0000012f,
16962DB_PERF_SEL_MI_zpc_req_wrack_counter_stall = 0x00000130,
16963DB_PERF_SEL_MI_psd_req_wrack_counter_stall = 0x00000131,
16964DB_PERF_SEL_unmapped_z_tile_culled = 0x00000132,
16965DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_DB_DATA_TS = 0x00000133,
16966DB_PERF_SEL_DB_CB_tile_is_event_FLUSH_AND_INV_CB_PIXEL_DATA = 0x00000134,
16967DB_PERF_SEL_DB_CB_tile_is_event_BOTTOM_OF_PIPE_TS = 0x00000135,
16968DB_PERF_SEL_DB_CB_tile_waiting_for_perfcounter_stop_event = 0x00000136,
16969DB_PERF_SEL_DB_CB_lquad_fmt_32bpp_8pix = 0x00000137,
16970DB_PERF_SEL_DB_CB_lquad_fmt_16_16_unsigned_8pix = 0x00000138,
16971DB_PERF_SEL_DB_CB_lquad_fmt_16_16_signed_8pix = 0x00000139,
16972DB_PERF_SEL_DB_CB_lquad_fmt_16_16_float_8pix = 0x0000013a,
16973DB_PERF_SEL_DB_CB_lquad_num_pixels_need_blending = 0x0000013b,
16974DB_PERF_SEL_DB_CB_context_dones = 0x0000013c,
16975DB_PERF_SEL_DB_CB_eop_dones = 0x0000013d,
16976DB_PERF_SEL_SX_DB_quad_all_pixels_killed = 0x0000013e,
16977DB_PERF_SEL_SX_DB_quad_all_pixels_enabled = 0x0000013f,
16978DB_PERF_SEL_SX_DB_quad_need_blending_and_dst_read = 0x00000140,
16979DB_PERF_SEL_SC_DB_tile_backface = 0x00000141,
16980DB_PERF_SEL_SC_DB_quad_quads = 0x00000142,
16981DB_PERF_SEL_DB_SC_quad_quads_with_1_pixel = 0x00000143,
16982DB_PERF_SEL_DB_SC_quad_quads_with_2_pixels = 0x00000144,
16983DB_PERF_SEL_DB_SC_quad_quads_with_3_pixels = 0x00000145,
16984DB_PERF_SEL_DB_SC_quad_quads_with_4_pixels = 0x00000146,
16985DB_PERF_SEL_DFSM_Flush_flushabit = 0x00000147,
16986DB_PERF_SEL_DFSM_Flush_flushabit_camcoord_fifo = 0x00000148,
16987DB_PERF_SEL_DFSM_Flush_flushabit_passthrough = 0x00000149,
16988DB_PERF_SEL_DFSM_Flush_flushabit_forceflush = 0x0000014a,
16989DB_PERF_SEL_DFSM_Flush_flushabit_nearlyfull = 0x0000014b,
16990DB_PERF_SEL_DFSM_Flush_flushabit_primitivesinflightwatermark = 0x0000014c,
16991DB_PERF_SEL_DFSM_Flush_flushabit_punch_stalling = 0x0000014d,
16992DB_PERF_SEL_DFSM_Flush_flushabit_retainedtilefifo_watermark = 0x0000014e,
16993DB_PERF_SEL_DFSM_Flush_flushabit_tilesinflightwatermark = 0x0000014f,
16994DB_PERF_SEL_DFSM_Flush_flushall = 0x00000150,
16995DB_PERF_SEL_DFSM_Flush_flushall_dfsmflush = 0x00000151,
16996DB_PERF_SEL_DFSM_Flush_flushall_opmodechange = 0x00000152,
16997DB_PERF_SEL_DFSM_Flush_flushall_sampleratechange = 0x00000153,
16998DB_PERF_SEL_DFSM_Flush_flushall_watchdog = 0x00000154,
16999DB_PERF_SEL_DB_SC_quad_double_quad = 0x00000155,
17000DB_PERF_SEL_SX_DB_quad_export_quads = 0x00000156,
17001DB_PERF_SEL_SX_DB_quad_double_format = 0x00000157,
17002DB_PERF_SEL_SX_DB_quad_fast_format = 0x00000158,
17003DB_PERF_SEL_SX_DB_quad_slow_format = 0x00000159,
17004} PerfCounter_Vals;
17005
17006/*
17007 * RingCounterControl enum
17008 */
17009
17010typedef enum RingCounterControl {
17011COUNTER_RING_SPLIT = 0x00000000,
17012COUNTER_RING_0 = 0x00000001,
17013COUNTER_RING_1 = 0x00000002,
17014} RingCounterControl;
17015
17016/*
17017 * DbMemArbWatermarks enum
17018 */
17019
17020typedef enum DbMemArbWatermarks {
17021TRANSFERRED_64_BYTES = 0x00000000,
17022TRANSFERRED_128_BYTES = 0x00000001,
17023TRANSFERRED_256_BYTES = 0x00000002,
17024TRANSFERRED_512_BYTES = 0x00000003,
17025TRANSFERRED_1024_BYTES = 0x00000004,
17026TRANSFERRED_2048_BYTES = 0x00000005,
17027TRANSFERRED_4096_BYTES = 0x00000006,
17028TRANSFERRED_8192_BYTES = 0x00000007,
17029} DbMemArbWatermarks;
17030
17031/*
17032 * DFSMFlushEvents enum
17033 */
17034
17035typedef enum DFSMFlushEvents {
17036DB_FLUSH_AND_INV_DB_DATA_TS = 0x00000000,
17037DB_FLUSH_AND_INV_DB_META = 0x00000001,
17038DB_CACHE_FLUSH = 0x00000002,
17039DB_CACHE_FLUSH_TS = 0x00000003,
17040DB_CACHE_FLUSH_AND_INV_EVENT = 0x00000004,
17041DB_CACHE_FLUSH_AND_INV_TS_EVENT = 0x00000005,
17042DB_VPORT_CHANGED_EVENT = 0x00000006,
17043DB_CONTEXT_DONE_EVENT = 0x00000007,
17044DB_BREAK_BATCH_EVENT = 0x00000008,
17045DB_PSINVOKE_CHANGE_EVENT = 0x00000009,
17046DB_CONTEXT_SUSPEND_EVENT = 0x0000000a,
17047} DFSMFlushEvents;
17048
17049/*
17050 * PixelPipeCounterId enum
17051 */
17052
17053typedef enum PixelPipeCounterId {
17054PIXEL_PIPE_OCCLUSION_COUNT_0 = 0x00000000,
17055PIXEL_PIPE_OCCLUSION_COUNT_1 = 0x00000001,
17056PIXEL_PIPE_OCCLUSION_COUNT_2 = 0x00000002,
17057PIXEL_PIPE_OCCLUSION_COUNT_3 = 0x00000003,
17058PIXEL_PIPE_SCREEN_MIN_EXTENTS_0 = 0x00000004,
17059PIXEL_PIPE_SCREEN_MAX_EXTENTS_0 = 0x00000005,
17060PIXEL_PIPE_SCREEN_MIN_EXTENTS_1 = 0x00000006,
17061PIXEL_PIPE_SCREEN_MAX_EXTENTS_1 = 0x00000007,
17062} PixelPipeCounterId;
17063
17064/*
17065 * PixelPipeStride enum
17066 */
17067
17068typedef enum PixelPipeStride {
17069PIXEL_PIPE_STRIDE_32_BITS = 0x00000000,
17070PIXEL_PIPE_STRIDE_64_BITS = 0x00000001,
17071PIXEL_PIPE_STRIDE_128_BITS = 0x00000002,
17072PIXEL_PIPE_STRIDE_256_BITS = 0x00000003,
17073} PixelPipeStride;
17074
17075/*
17076 * FullTileWaveBreak enum
17077 */
17078
17079typedef enum FullTileWaveBreak {
17080FULL_TILE_WAVE_BREAK_NBC_ONLY = 0x00000000,
17081FULL_TILE_WAVE_BREAK_BOTH = 0x00000001,
17082FULL_TILE_WAVE_BREAK_NONE = 0x00000002,
17083FULL_TILE_WAVE_BREAK_BC_ONLY = 0x00000003,
17084} FullTileWaveBreak;
17085
17086/*******************************************************
17087 * TA Enums
17088 *******************************************************/
17089
17090/*
17091 * TEX_BORDER_COLOR_TYPE enum
17092 */
17093
17094typedef enum TEX_BORDER_COLOR_TYPE {
17095TEX_BorderColor_TransparentBlack = 0x00000000,
17096TEX_BorderColor_OpaqueBlack = 0x00000001,
17097TEX_BorderColor_OpaqueWhite = 0x00000002,
17098TEX_BorderColor_Register = 0x00000003,
17099} TEX_BORDER_COLOR_TYPE;
17100
17101/*
17102 * TEX_BC_SWIZZLE enum
17103 */
17104
17105typedef enum TEX_BC_SWIZZLE {
17106TEX_BC_Swizzle_XYZW = 0x00000000,
17107TEX_BC_Swizzle_XWYZ = 0x00000001,
17108TEX_BC_Swizzle_WZYX = 0x00000002,
17109TEX_BC_Swizzle_WXYZ = 0x00000003,
17110TEX_BC_Swizzle_ZYXW = 0x00000004,
17111TEX_BC_Swizzle_YXWZ = 0x00000005,
17112} TEX_BC_SWIZZLE;
17113
17114/*
17115 * TEX_CHROMA_KEY enum
17116 */
17117
17118typedef enum TEX_CHROMA_KEY {
17119TEX_ChromaKey_Disabled = 0x00000000,
17120TEX_ChromaKey_Kill = 0x00000001,
17121TEX_ChromaKey_Blend = 0x00000002,
17122TEX_ChromaKey_RESERVED_3 = 0x00000003,
17123} TEX_CHROMA_KEY;
17124
17125/*
17126 * TEX_CLAMP enum
17127 */
17128
17129typedef enum TEX_CLAMP {
17130TEX_Clamp_Repeat = 0x00000000,
17131TEX_Clamp_Mirror = 0x00000001,
17132TEX_Clamp_ClampToLast = 0x00000002,
17133TEX_Clamp_MirrorOnceToLast = 0x00000003,
17134TEX_Clamp_ClampHalfToBorder = 0x00000004,
17135TEX_Clamp_MirrorOnceHalfToBorder = 0x00000005,
17136TEX_Clamp_ClampToBorder = 0x00000006,
17137TEX_Clamp_MirrorOnceToBorder = 0x00000007,
17138} TEX_CLAMP;
17139
17140/*
17141 * TEX_COORD_TYPE enum
17142 */
17143
17144typedef enum TEX_COORD_TYPE {
17145TEX_CoordType_Unnormalized = 0x00000000,
17146TEX_CoordType_Normalized = 0x00000001,
17147} TEX_COORD_TYPE;
17148
17149/*
17150 * TEX_DEPTH_COMPARE_FUNCTION enum
17151 */
17152
17153typedef enum TEX_DEPTH_COMPARE_FUNCTION {
17154TEX_DepthCompareFunction_Never = 0x00000000,
17155TEX_DepthCompareFunction_Less = 0x00000001,
17156TEX_DepthCompareFunction_Equal = 0x00000002,
17157TEX_DepthCompareFunction_LessEqual = 0x00000003,
17158TEX_DepthCompareFunction_Greater = 0x00000004,
17159TEX_DepthCompareFunction_NotEqual = 0x00000005,
17160TEX_DepthCompareFunction_GreaterEqual = 0x00000006,
17161TEX_DepthCompareFunction_Always = 0x00000007,
17162} TEX_DEPTH_COMPARE_FUNCTION;
17163
17164/*
17165 * TEX_DIM enum
17166 */
17167
17168typedef enum TEX_DIM {
17169TEX_Dim_1D = 0x00000000,
17170TEX_Dim_2D = 0x00000001,
17171TEX_Dim_3D = 0x00000002,
17172TEX_Dim_CubeMap = 0x00000003,
17173TEX_Dim_1DArray = 0x00000004,
17174TEX_Dim_2DArray = 0x00000005,
17175TEX_Dim_2D_MSAA = 0x00000006,
17176TEX_Dim_2DArray_MSAA = 0x00000007,
17177} TEX_DIM;
17178
17179/*
17180 * TEX_FORMAT_COMP enum
17181 */
17182
17183typedef enum TEX_FORMAT_COMP {
17184TEX_FormatComp_Unsigned = 0x00000000,
17185TEX_FormatComp_Signed = 0x00000001,
17186TEX_FormatComp_UnsignedBiased = 0x00000002,
17187TEX_FormatComp_RESERVED_3 = 0x00000003,
17188} TEX_FORMAT_COMP;
17189
17190/*
17191 * TEX_MAX_ANISO_RATIO enum
17192 */
17193
17194typedef enum TEX_MAX_ANISO_RATIO {
17195TEX_MaxAnisoRatio_1to1 = 0x00000000,
17196TEX_MaxAnisoRatio_2to1 = 0x00000001,
17197TEX_MaxAnisoRatio_4to1 = 0x00000002,
17198TEX_MaxAnisoRatio_8to1 = 0x00000003,
17199TEX_MaxAnisoRatio_16to1 = 0x00000004,
17200TEX_MaxAnisoRatio_RESERVED_5 = 0x00000005,
17201TEX_MaxAnisoRatio_RESERVED_6 = 0x00000006,
17202TEX_MaxAnisoRatio_RESERVED_7 = 0x00000007,
17203} TEX_MAX_ANISO_RATIO;
17204
17205/*
17206 * TEX_MIP_FILTER enum
17207 */
17208
17209typedef enum TEX_MIP_FILTER {
17210TEX_MipFilter_None = 0x00000000,
17211TEX_MipFilter_Point = 0x00000001,
17212TEX_MipFilter_Linear = 0x00000002,
17213TEX_MipFilter_Point_Aniso_Adj = 0x00000003,
17214} TEX_MIP_FILTER;
17215
17216/*
17217 * TEX_REQUEST_SIZE enum
17218 */
17219
17220typedef enum TEX_REQUEST_SIZE {
17221TEX_RequestSize_32B = 0x00000000,
17222TEX_RequestSize_64B = 0x00000001,
17223TEX_RequestSize_128B = 0x00000002,
17224TEX_RequestSize_2X64B = 0x00000003,
17225} TEX_REQUEST_SIZE;
17226
17227/*
17228 * TEX_SAMPLER_TYPE enum
17229 */
17230
17231typedef enum TEX_SAMPLER_TYPE {
17232TEX_SamplerType_Invalid = 0x00000000,
17233TEX_SamplerType_Valid = 0x00000001,
17234} TEX_SAMPLER_TYPE;
17235
17236/*
17237 * TEX_XY_FILTER enum
17238 */
17239
17240typedef enum TEX_XY_FILTER {
17241TEX_XYFilter_Point = 0x00000000,
17242TEX_XYFilter_Linear = 0x00000001,
17243TEX_XYFilter_AnisoPoint = 0x00000002,
17244TEX_XYFilter_AnisoLinear = 0x00000003,
17245} TEX_XY_FILTER;
17246
17247/*
17248 * TEX_Z_FILTER enum
17249 */
17250
17251typedef enum TEX_Z_FILTER {
17252TEX_ZFilter_None = 0x00000000,
17253TEX_ZFilter_Point = 0x00000001,
17254TEX_ZFilter_Linear = 0x00000002,
17255TEX_ZFilter_RESERVED_3 = 0x00000003,
17256} TEX_Z_FILTER;
17257
17258/*
17259 * VTX_CLAMP enum
17260 */
17261
17262typedef enum VTX_CLAMP {
17263VTX_Clamp_ClampToZero = 0x00000000,
17264VTX_Clamp_ClampToNAN = 0x00000001,
17265} VTX_CLAMP;
17266
17267/*
17268 * VTX_FETCH_TYPE enum
17269 */
17270
17271typedef enum VTX_FETCH_TYPE {
17272VTX_FetchType_VertexData = 0x00000000,
17273VTX_FetchType_InstanceData = 0x00000001,
17274VTX_FetchType_NoIndexOffset = 0x00000002,
17275VTX_FetchType_RESERVED_3 = 0x00000003,
17276} VTX_FETCH_TYPE;
17277
17278/*
17279 * VTX_FORMAT_COMP_ALL enum
17280 */
17281
17282typedef enum VTX_FORMAT_COMP_ALL {
17283VTX_FormatCompAll_Unsigned = 0x00000000,
17284VTX_FormatCompAll_Signed = 0x00000001,
17285} VTX_FORMAT_COMP_ALL;
17286
17287/*
17288 * VTX_MEM_REQUEST_SIZE enum
17289 */
17290
17291typedef enum VTX_MEM_REQUEST_SIZE {
17292VTX_MemRequestSize_32B = 0x00000000,
17293VTX_MemRequestSize_64B = 0x00000001,
17294} VTX_MEM_REQUEST_SIZE;
17295
17296/*
17297 * TVX_DATA_FORMAT enum
17298 */
17299
17300typedef enum TVX_DATA_FORMAT {
17301TVX_FMT_INVALID = 0x00000000,
17302TVX_FMT_8 = 0x00000001,
17303TVX_FMT_4_4 = 0x00000002,
17304TVX_FMT_3_3_2 = 0x00000003,
17305TVX_FMT_RESERVED_4 = 0x00000004,
17306TVX_FMT_16 = 0x00000005,
17307TVX_FMT_16_FLOAT = 0x00000006,
17308TVX_FMT_8_8 = 0x00000007,
17309TVX_FMT_5_6_5 = 0x00000008,
17310TVX_FMT_6_5_5 = 0x00000009,
17311TVX_FMT_1_5_5_5 = 0x0000000a,
17312TVX_FMT_4_4_4_4 = 0x0000000b,
17313TVX_FMT_5_5_5_1 = 0x0000000c,
17314TVX_FMT_32 = 0x0000000d,
17315TVX_FMT_32_FLOAT = 0x0000000e,
17316TVX_FMT_16_16 = 0x0000000f,
17317TVX_FMT_16_16_FLOAT = 0x00000010,
17318TVX_FMT_8_24 = 0x00000011,
17319TVX_FMT_8_24_FLOAT = 0x00000012,
17320TVX_FMT_24_8 = 0x00000013,
17321TVX_FMT_24_8_FLOAT = 0x00000014,
17322TVX_FMT_10_11_11 = 0x00000015,
17323TVX_FMT_10_11_11_FLOAT = 0x00000016,
17324TVX_FMT_11_11_10 = 0x00000017,
17325TVX_FMT_11_11_10_FLOAT = 0x00000018,
17326TVX_FMT_2_10_10_10 = 0x00000019,
17327TVX_FMT_8_8_8_8 = 0x0000001a,
17328TVX_FMT_10_10_10_2 = 0x0000001b,
17329TVX_FMT_X24_8_32_FLOAT = 0x0000001c,
17330TVX_FMT_32_32 = 0x0000001d,
17331TVX_FMT_32_32_FLOAT = 0x0000001e,
17332TVX_FMT_16_16_16_16 = 0x0000001f,
17333TVX_FMT_16_16_16_16_FLOAT = 0x00000020,
17334TVX_FMT_RESERVED_33 = 0x00000021,
17335TVX_FMT_32_32_32_32 = 0x00000022,
17336TVX_FMT_32_32_32_32_FLOAT = 0x00000023,
17337TVX_FMT_RESERVED_36 = 0x00000024,
17338TVX_FMT_1 = 0x00000025,
17339TVX_FMT_1_REVERSED = 0x00000026,
17340TVX_FMT_GB_GR = 0x00000027,
17341TVX_FMT_BG_RG = 0x00000028,
17342TVX_FMT_32_AS_8 = 0x00000029,
17343TVX_FMT_32_AS_8_8 = 0x0000002a,
17344TVX_FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
17345TVX_FMT_8_8_8 = 0x0000002c,
17346TVX_FMT_16_16_16 = 0x0000002d,
17347TVX_FMT_16_16_16_FLOAT = 0x0000002e,
17348TVX_FMT_32_32_32 = 0x0000002f,
17349TVX_FMT_32_32_32_FLOAT = 0x00000030,
17350TVX_FMT_BC1 = 0x00000031,
17351TVX_FMT_BC2 = 0x00000032,
17352TVX_FMT_BC3 = 0x00000033,
17353TVX_FMT_BC4 = 0x00000034,
17354TVX_FMT_BC5 = 0x00000035,
17355TVX_FMT_APC0 = 0x00000036,
17356TVX_FMT_APC1 = 0x00000037,
17357TVX_FMT_APC2 = 0x00000038,
17358TVX_FMT_APC3 = 0x00000039,
17359TVX_FMT_APC4 = 0x0000003a,
17360TVX_FMT_APC5 = 0x0000003b,
17361TVX_FMT_APC6 = 0x0000003c,
17362TVX_FMT_APC7 = 0x0000003d,
17363TVX_FMT_CTX1 = 0x0000003e,
17364TVX_FMT_RESERVED_63 = 0x0000003f,
17365} TVX_DATA_FORMAT;
17366
17367/*
17368 * TVX_DST_SEL enum
17369 */
17370
17371typedef enum TVX_DST_SEL {
17372TVX_DstSel_X = 0x00000000,
17373TVX_DstSel_Y = 0x00000001,
17374TVX_DstSel_Z = 0x00000002,
17375TVX_DstSel_W = 0x00000003,
17376TVX_DstSel_0f = 0x00000004,
17377TVX_DstSel_1f = 0x00000005,
17378TVX_DstSel_RESERVED_6 = 0x00000006,
17379TVX_DstSel_Mask = 0x00000007,
17380} TVX_DST_SEL;
17381
17382/*
17383 * TVX_ENDIAN_SWAP enum
17384 */
17385
17386typedef enum TVX_ENDIAN_SWAP {
17387TVX_EndianSwap_None = 0x00000000,
17388TVX_EndianSwap_8in16 = 0x00000001,
17389TVX_EndianSwap_8in32 = 0x00000002,
17390TVX_EndianSwap_8in64 = 0x00000003,
17391} TVX_ENDIAN_SWAP;
17392
17393/*
17394 * TVX_INST enum
17395 */
17396
17397typedef enum TVX_INST {
17398TVX_Inst_NormalVertexFetch = 0x00000000,
17399TVX_Inst_SemanticVertexFetch = 0x00000001,
17400TVX_Inst_RESERVED_2 = 0x00000002,
17401TVX_Inst_LD = 0x00000003,
17402TVX_Inst_GetTextureResInfo = 0x00000004,
17403TVX_Inst_GetNumberOfSamples = 0x00000005,
17404TVX_Inst_GetLOD = 0x00000006,
17405TVX_Inst_GetGradientsH = 0x00000007,
17406TVX_Inst_GetGradientsV = 0x00000008,
17407TVX_Inst_SetTextureOffsets = 0x00000009,
17408TVX_Inst_KeepGradients = 0x0000000a,
17409TVX_Inst_SetGradientsH = 0x0000000b,
17410TVX_Inst_SetGradientsV = 0x0000000c,
17411TVX_Inst_Pass = 0x0000000d,
17412TVX_Inst_GetBufferResInfo = 0x0000000e,
17413TVX_Inst_RESERVED_15 = 0x0000000f,
17414TVX_Inst_Sample = 0x00000010,
17415TVX_Inst_Sample_L = 0x00000011,
17416TVX_Inst_Sample_LB = 0x00000012,
17417TVX_Inst_Sample_LZ = 0x00000013,
17418TVX_Inst_Sample_G = 0x00000014,
17419TVX_Inst_Gather4 = 0x00000015,
17420TVX_Inst_Sample_G_LB = 0x00000016,
17421TVX_Inst_Gather4_O = 0x00000017,
17422TVX_Inst_Sample_C = 0x00000018,
17423TVX_Inst_Sample_C_L = 0x00000019,
17424TVX_Inst_Sample_C_LB = 0x0000001a,
17425TVX_Inst_Sample_C_LZ = 0x0000001b,
17426TVX_Inst_Sample_C_G = 0x0000001c,
17427TVX_Inst_Gather4_C = 0x0000001d,
17428TVX_Inst_Sample_C_G_LB = 0x0000001e,
17429TVX_Inst_Gather4_C_O = 0x0000001f,
17430} TVX_INST;
17431
17432/*
17433 * TVX_NUM_FORMAT_ALL enum
17434 */
17435
17436typedef enum TVX_NUM_FORMAT_ALL {
17437TVX_NumFormatAll_Norm = 0x00000000,
17438TVX_NumFormatAll_Int = 0x00000001,
17439TVX_NumFormatAll_Scaled = 0x00000002,
17440TVX_NumFormatAll_RESERVED_3 = 0x00000003,
17441} TVX_NUM_FORMAT_ALL;
17442
17443/*
17444 * TVX_SRC_SEL enum
17445 */
17446
17447typedef enum TVX_SRC_SEL {
17448TVX_SrcSel_X = 0x00000000,
17449TVX_SrcSel_Y = 0x00000001,
17450TVX_SrcSel_Z = 0x00000002,
17451TVX_SrcSel_W = 0x00000003,
17452TVX_SrcSel_0f = 0x00000004,
17453TVX_SrcSel_1f = 0x00000005,
17454} TVX_SRC_SEL;
17455
17456/*
17457 * TVX_SRF_MODE_ALL enum
17458 */
17459
17460typedef enum TVX_SRF_MODE_ALL {
17461TVX_SRFModeAll_ZCMO = 0x00000000,
17462TVX_SRFModeAll_NZ = 0x00000001,
17463} TVX_SRF_MODE_ALL;
17464
17465/*
17466 * TVX_TYPE enum
17467 */
17468
17469typedef enum TVX_TYPE {
17470TVX_Type_InvalidTextureResource = 0x00000000,
17471TVX_Type_InvalidVertexBuffer = 0x00000001,
17472TVX_Type_ValidTextureResource = 0x00000002,
17473TVX_Type_ValidVertexBuffer = 0x00000003,
17474} TVX_TYPE;
17475
17476/*******************************************************
17477 * PA Enums
17478 *******************************************************/
17479
17480/*
17481 * PH_PERFCNT_SEL enum
17482 */
17483
17484typedef enum PH_PERFCNT_SEL {
17485PH_SC0_SRPS_WINDOW_VALID = 0x00000000,
17486PH_SC0_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000001,
17487PH_SC0_ARB_XFC_ONLY_PRIM_CYCLES = 0x00000002,
17488PH_SC0_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x00000003,
17489PH_SC0_ARB_STALLED_FROM_BELOW = 0x00000004,
17490PH_SC0_ARB_STARVED_FROM_ABOVE = 0x00000005,
17491PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x00000006,
17492PH_SC0_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x00000007,
17493PH_SC0_ARB_BUSY = 0x00000008,
17494PH_SC0_ARB_PA_BUSY_SOP = 0x00000009,
17495PH_SC0_ARB_EOP_POP_SYNC_POP = 0x0000000a,
17496PH_SC0_ARB_EVENT_SYNC_POP = 0x0000000b,
17497PH_SC0_PS_ENG_MULTICYCLE_BUBBLE = 0x0000000c,
17498PH_SC0_EOP_SYNC_WINDOW = 0x0000000d,
17499PH_SC0_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x0000000e,
17500PH_SC0_BUSY_CNT_NOT_ZERO = 0x0000000f,
17501PH_SC0_SEND = 0x00000010,
17502PH_SC0_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000011,
17503PH_SC0_CREDIT_AT_MAX = 0x00000012,
17504PH_SC0_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000013,
17505PH_SC0_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000014,
17506PH_SC0_GFX_PIPE_PRIM_PROVOKED_TRANSITION = 0x00000015,
17507PH_SC0_GFX_PIPE0_TO_1_TRANSITION = 0x00000016,
17508PH_SC0_GFX_PIPE1_TO_0_TRANSITION = 0x00000017,
17509PH_SC0_PA0_DATA_FIFO_RD = 0x00000018,
17510PH_SC0_PA0_DATA_FIFO_WE = 0x00000019,
17511PH_SC0_PA0_FIFO_EMPTY = 0x0000001a,
17512PH_SC0_PA0_FIFO_FULL = 0x0000001b,
17513PH_SC0_PA0_NULL_WE = 0x0000001c,
17514PH_SC0_PA0_EVENT_WE = 0x0000001d,
17515PH_SC0_PA0_FPOV_WE = 0x0000001e,
17516PH_SC0_PA0_LPOV_WE = 0x0000001f,
17517PH_SC0_PA0_EOP_WE = 0x00000020,
17518PH_SC0_PA0_DATA_FIFO_EOP_RD = 0x00000021,
17519PH_SC0_PA0_EOPG_WE = 0x00000022,
17520PH_SC0_PA0_DEALLOC_4_0_RD = 0x00000023,
17521PH_SC0_PA1_DATA_FIFO_RD = 0x00000024,
17522PH_SC0_PA1_DATA_FIFO_WE = 0x00000025,
17523PH_SC0_PA1_FIFO_EMPTY = 0x00000026,
17524PH_SC0_PA1_FIFO_FULL = 0x00000027,
17525PH_SC0_PA1_NULL_WE = 0x00000028,
17526PH_SC0_PA1_EVENT_WE = 0x00000029,
17527PH_SC0_PA1_FPOV_WE = 0x0000002a,
17528PH_SC0_PA1_LPOV_WE = 0x0000002b,
17529PH_SC0_PA1_EOP_WE = 0x0000002c,
17530PH_SC0_PA1_DATA_FIFO_EOP_RD = 0x0000002d,
17531PH_SC0_PA1_EOPG_WE = 0x0000002e,
17532PH_SC0_PA1_DEALLOC_4_0_RD = 0x0000002f,
17533PH_SC0_PA2_DATA_FIFO_RD = 0x00000030,
17534PH_SC0_PA2_DATA_FIFO_WE = 0x00000031,
17535PH_SC0_PA2_FIFO_EMPTY = 0x00000032,
17536PH_SC0_PA2_FIFO_FULL = 0x00000033,
17537PH_SC0_PA2_NULL_WE = 0x00000034,
17538PH_SC0_PA2_EVENT_WE = 0x00000035,
17539PH_SC0_PA2_FPOV_WE = 0x00000036,
17540PH_SC0_PA2_LPOV_WE = 0x00000037,
17541PH_SC0_PA2_EOP_WE = 0x00000038,
17542PH_SC0_PA2_DATA_FIFO_EOP_RD = 0x00000039,
17543PH_SC0_PA2_EOPG_WE = 0x0000003a,
17544PH_SC0_PA2_DEALLOC_4_0_RD = 0x0000003b,
17545PH_SC0_PA3_DATA_FIFO_RD = 0x0000003c,
17546PH_SC0_PA3_DATA_FIFO_WE = 0x0000003d,
17547PH_SC0_PA3_FIFO_EMPTY = 0x0000003e,
17548PH_SC0_PA3_FIFO_FULL = 0x0000003f,
17549PH_SC0_PA3_NULL_WE = 0x00000040,
17550PH_SC0_PA3_EVENT_WE = 0x00000041,
17551PH_SC0_PA3_FPOV_WE = 0x00000042,
17552PH_SC0_PA3_LPOV_WE = 0x00000043,
17553PH_SC0_PA3_EOP_WE = 0x00000044,
17554PH_SC0_PA3_DATA_FIFO_EOP_RD = 0x00000045,
17555PH_SC0_PA3_EOPG_WE = 0x00000046,
17556PH_SC0_PA3_DEALLOC_4_0_RD = 0x00000047,
17557PH_SC0_PA4_DATA_FIFO_RD = 0x00000048,
17558PH_SC0_PA4_DATA_FIFO_WE = 0x00000049,
17559PH_SC0_PA4_FIFO_EMPTY = 0x0000004a,
17560PH_SC0_PA4_FIFO_FULL = 0x0000004b,
17561PH_SC0_PA4_NULL_WE = 0x0000004c,
17562PH_SC0_PA4_EVENT_WE = 0x0000004d,
17563PH_SC0_PA4_FPOV_WE = 0x0000004e,
17564PH_SC0_PA4_LPOV_WE = 0x0000004f,
17565PH_SC0_PA4_EOP_WE = 0x00000050,
17566PH_SC0_PA4_DATA_FIFO_EOP_RD = 0x00000051,
17567PH_SC0_PA4_EOPG_WE = 0x00000052,
17568PH_SC0_PA4_DEALLOC_4_0_RD = 0x00000053,
17569PH_SC0_PA5_DATA_FIFO_RD = 0x00000054,
17570PH_SC0_PA5_DATA_FIFO_WE = 0x00000055,
17571PH_SC0_PA5_FIFO_EMPTY = 0x00000056,
17572PH_SC0_PA5_FIFO_FULL = 0x00000057,
17573PH_SC0_PA5_NULL_WE = 0x00000058,
17574PH_SC0_PA5_EVENT_WE = 0x00000059,
17575PH_SC0_PA5_FPOV_WE = 0x0000005a,
17576PH_SC0_PA5_LPOV_WE = 0x0000005b,
17577PH_SC0_PA5_EOP_WE = 0x0000005c,
17578PH_SC0_PA5_DATA_FIFO_EOP_RD = 0x0000005d,
17579PH_SC0_PA5_EOPG_WE = 0x0000005e,
17580PH_SC0_PA5_DEALLOC_4_0_RD = 0x0000005f,
17581PH_SC0_PA6_DATA_FIFO_RD = 0x00000060,
17582PH_SC0_PA6_DATA_FIFO_WE = 0x00000061,
17583PH_SC0_PA6_FIFO_EMPTY = 0x00000062,
17584PH_SC0_PA6_FIFO_FULL = 0x00000063,
17585PH_SC0_PA6_NULL_WE = 0x00000064,
17586PH_SC0_PA6_EVENT_WE = 0x00000065,
17587PH_SC0_PA6_FPOV_WE = 0x00000066,
17588PH_SC0_PA6_LPOV_WE = 0x00000067,
17589PH_SC0_PA6_EOP_WE = 0x00000068,
17590PH_SC0_PA6_DATA_FIFO_EOP_RD = 0x00000069,
17591PH_SC0_PA6_EOPG_WE = 0x0000006a,
17592PH_SC0_PA6_DEALLOC_4_0_RD = 0x0000006b,
17593PH_SC0_PA7_DATA_FIFO_RD = 0x0000006c,
17594PH_SC0_PA7_DATA_FIFO_WE = 0x0000006d,
17595PH_SC0_PA7_FIFO_EMPTY = 0x0000006e,
17596PH_SC0_PA7_FIFO_FULL = 0x0000006f,
17597PH_SC0_PA7_NULL_WE = 0x00000070,
17598PH_SC0_PA7_EVENT_WE = 0x00000071,
17599PH_SC0_PA7_FPOV_WE = 0x00000072,
17600PH_SC0_PA7_LPOV_WE = 0x00000073,
17601PH_SC0_PA7_EOP_WE = 0x00000074,
17602PH_SC0_PA7_DATA_FIFO_EOP_RD = 0x00000075,
17603PH_SC0_PA7_EOPG_WE = 0x00000076,
17604PH_SC0_PA7_DEALLOC_4_0_RD = 0x00000077,
17605PH_SC1_SRPS_WINDOW_VALID = 0x00000078,
17606PH_SC1_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000079,
17607PH_SC1_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000007a,
17608PH_SC1_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000007b,
17609PH_SC1_ARB_STALLED_FROM_BELOW = 0x0000007c,
17610PH_SC1_ARB_STARVED_FROM_ABOVE = 0x0000007d,
17611PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000007e,
17612PH_SC1_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000007f,
17613PH_SC1_ARB_BUSY = 0x00000080,
17614PH_SC1_ARB_PA_BUSY_SOP = 0x00000081,
17615PH_SC1_ARB_EOP_POP_SYNC_POP = 0x00000082,
17616PH_SC1_ARB_EVENT_SYNC_POP = 0x00000083,
17617PH_SC1_PS_ENG_MULTICYCLE_BUBBLE = 0x00000084,
17618PH_SC1_EOP_SYNC_WINDOW = 0x00000085,
17619PH_SC1_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000086,
17620PH_SC1_BUSY_CNT_NOT_ZERO = 0x00000087,
17621PH_SC1_SEND = 0x00000088,
17622PH_SC1_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000089,
17623PH_SC1_CREDIT_AT_MAX = 0x0000008a,
17624PH_SC1_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000008b,
17625PH_SC1_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000008c,
17626PH_SC1_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000008d,
17627PH_SC1_GFX_PIPE0_TO_1_TRANSITION = 0x0000008e,
17628PH_SC1_GFX_PIPE1_TO_0_TRANSITION = 0x0000008f,
17629PH_SC1_PA0_DATA_FIFO_RD = 0x00000090,
17630PH_SC1_PA0_DATA_FIFO_WE = 0x00000091,
17631PH_SC1_PA0_FIFO_EMPTY = 0x00000092,
17632PH_SC1_PA0_FIFO_FULL = 0x00000093,
17633PH_SC1_PA0_NULL_WE = 0x00000094,
17634PH_SC1_PA0_EVENT_WE = 0x00000095,
17635PH_SC1_PA0_FPOV_WE = 0x00000096,
17636PH_SC1_PA0_LPOV_WE = 0x00000097,
17637PH_SC1_PA0_EOP_WE = 0x00000098,
17638PH_SC1_PA0_DATA_FIFO_EOP_RD = 0x00000099,
17639PH_SC1_PA0_EOPG_WE = 0x0000009a,
17640PH_SC1_PA0_DEALLOC_4_0_RD = 0x0000009b,
17641PH_SC1_PA1_DATA_FIFO_RD = 0x0000009c,
17642PH_SC1_PA1_DATA_FIFO_WE = 0x0000009d,
17643PH_SC1_PA1_FIFO_EMPTY = 0x0000009e,
17644PH_SC1_PA1_FIFO_FULL = 0x0000009f,
17645PH_SC1_PA1_NULL_WE = 0x000000a0,
17646PH_SC1_PA1_EVENT_WE = 0x000000a1,
17647PH_SC1_PA1_FPOV_WE = 0x000000a2,
17648PH_SC1_PA1_LPOV_WE = 0x000000a3,
17649PH_SC1_PA1_EOP_WE = 0x000000a4,
17650PH_SC1_PA1_DATA_FIFO_EOP_RD = 0x000000a5,
17651PH_SC1_PA1_EOPG_WE = 0x000000a6,
17652PH_SC1_PA1_DEALLOC_4_0_RD = 0x000000a7,
17653PH_SC1_PA2_DATA_FIFO_RD = 0x000000a8,
17654PH_SC1_PA2_DATA_FIFO_WE = 0x000000a9,
17655PH_SC1_PA2_FIFO_EMPTY = 0x000000aa,
17656PH_SC1_PA2_FIFO_FULL = 0x000000ab,
17657PH_SC1_PA2_NULL_WE = 0x000000ac,
17658PH_SC1_PA2_EVENT_WE = 0x000000ad,
17659PH_SC1_PA2_FPOV_WE = 0x000000ae,
17660PH_SC1_PA2_LPOV_WE = 0x000000af,
17661PH_SC1_PA2_EOP_WE = 0x000000b0,
17662PH_SC1_PA2_DATA_FIFO_EOP_RD = 0x000000b1,
17663PH_SC1_PA2_EOPG_WE = 0x000000b2,
17664PH_SC1_PA2_DEALLOC_4_0_RD = 0x000000b3,
17665PH_SC1_PA3_DATA_FIFO_RD = 0x000000b4,
17666PH_SC1_PA3_DATA_FIFO_WE = 0x000000b5,
17667PH_SC1_PA3_FIFO_EMPTY = 0x000000b6,
17668PH_SC1_PA3_FIFO_FULL = 0x000000b7,
17669PH_SC1_PA3_NULL_WE = 0x000000b8,
17670PH_SC1_PA3_EVENT_WE = 0x000000b9,
17671PH_SC1_PA3_FPOV_WE = 0x000000ba,
17672PH_SC1_PA3_LPOV_WE = 0x000000bb,
17673PH_SC1_PA3_EOP_WE = 0x000000bc,
17674PH_SC1_PA3_DATA_FIFO_EOP_RD = 0x000000bd,
17675PH_SC1_PA3_EOPG_WE = 0x000000be,
17676PH_SC1_PA3_DEALLOC_4_0_RD = 0x000000bf,
17677PH_SC1_PA4_DATA_FIFO_RD = 0x000000c0,
17678PH_SC1_PA4_DATA_FIFO_WE = 0x000000c1,
17679PH_SC1_PA4_FIFO_EMPTY = 0x000000c2,
17680PH_SC1_PA4_FIFO_FULL = 0x000000c3,
17681PH_SC1_PA4_NULL_WE = 0x000000c4,
17682PH_SC1_PA4_EVENT_WE = 0x000000c5,
17683PH_SC1_PA4_FPOV_WE = 0x000000c6,
17684PH_SC1_PA4_LPOV_WE = 0x000000c7,
17685PH_SC1_PA4_EOP_WE = 0x000000c8,
17686PH_SC1_PA4_DATA_FIFO_EOP_RD = 0x000000c9,
17687PH_SC1_PA4_EOPG_WE = 0x000000ca,
17688PH_SC1_PA4_DEALLOC_4_0_RD = 0x000000cb,
17689PH_SC1_PA5_DATA_FIFO_RD = 0x000000cc,
17690PH_SC1_PA5_DATA_FIFO_WE = 0x000000cd,
17691PH_SC1_PA5_FIFO_EMPTY = 0x000000ce,
17692PH_SC1_PA5_FIFO_FULL = 0x000000cf,
17693PH_SC1_PA5_NULL_WE = 0x000000d0,
17694PH_SC1_PA5_EVENT_WE = 0x000000d1,
17695PH_SC1_PA5_FPOV_WE = 0x000000d2,
17696PH_SC1_PA5_LPOV_WE = 0x000000d3,
17697PH_SC1_PA5_EOP_WE = 0x000000d4,
17698PH_SC1_PA5_DATA_FIFO_EOP_RD = 0x000000d5,
17699PH_SC1_PA5_EOPG_WE = 0x000000d6,
17700PH_SC1_PA5_DEALLOC_4_0_RD = 0x000000d7,
17701PH_SC1_PA6_DATA_FIFO_RD = 0x000000d8,
17702PH_SC1_PA6_DATA_FIFO_WE = 0x000000d9,
17703PH_SC1_PA6_FIFO_EMPTY = 0x000000da,
17704PH_SC1_PA6_FIFO_FULL = 0x000000db,
17705PH_SC1_PA6_NULL_WE = 0x000000dc,
17706PH_SC1_PA6_EVENT_WE = 0x000000dd,
17707PH_SC1_PA6_FPOV_WE = 0x000000de,
17708PH_SC1_PA6_LPOV_WE = 0x000000df,
17709PH_SC1_PA6_EOP_WE = 0x000000e0,
17710PH_SC1_PA6_DATA_FIFO_EOP_RD = 0x000000e1,
17711PH_SC1_PA6_EOPG_WE = 0x000000e2,
17712PH_SC1_PA6_DEALLOC_4_0_RD = 0x000000e3,
17713PH_SC1_PA7_DATA_FIFO_RD = 0x000000e4,
17714PH_SC1_PA7_DATA_FIFO_WE = 0x000000e5,
17715PH_SC1_PA7_FIFO_EMPTY = 0x000000e6,
17716PH_SC1_PA7_FIFO_FULL = 0x000000e7,
17717PH_SC1_PA7_NULL_WE = 0x000000e8,
17718PH_SC1_PA7_EVENT_WE = 0x000000e9,
17719PH_SC1_PA7_FPOV_WE = 0x000000ea,
17720PH_SC1_PA7_LPOV_WE = 0x000000eb,
17721PH_SC1_PA7_EOP_WE = 0x000000ec,
17722PH_SC1_PA7_DATA_FIFO_EOP_RD = 0x000000ed,
17723PH_SC1_PA7_EOPG_WE = 0x000000ee,
17724PH_SC1_PA7_DEALLOC_4_0_RD = 0x000000ef,
17725PH_SC2_SRPS_WINDOW_VALID = 0x000000f0,
17726PH_SC2_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000000f1,
17727PH_SC2_ARB_XFC_ONLY_PRIM_CYCLES = 0x000000f2,
17728PH_SC2_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000000f3,
17729PH_SC2_ARB_STALLED_FROM_BELOW = 0x000000f4,
17730PH_SC2_ARB_STARVED_FROM_ABOVE = 0x000000f5,
17731PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000000f6,
17732PH_SC2_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000000f7,
17733PH_SC2_ARB_BUSY = 0x000000f8,
17734PH_SC2_ARB_PA_BUSY_SOP = 0x000000f9,
17735PH_SC2_ARB_EOP_POP_SYNC_POP = 0x000000fa,
17736PH_SC2_ARB_EVENT_SYNC_POP = 0x000000fb,
17737PH_SC2_PS_ENG_MULTICYCLE_BUBBLE = 0x000000fc,
17738PH_SC2_EOP_SYNC_WINDOW = 0x000000fd,
17739PH_SC2_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000000fe,
17740PH_SC2_BUSY_CNT_NOT_ZERO = 0x000000ff,
17741PH_SC2_SEND = 0x00000100,
17742PH_SC2_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000101,
17743PH_SC2_CREDIT_AT_MAX = 0x00000102,
17744PH_SC2_CREDIT_AT_MAX_NO_PENDING_SEND = 0x00000103,
17745PH_SC2_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x00000104,
17746PH_SC2_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x00000105,
17747PH_SC2_GFX_PIPE0_TO_1_TRANSITION = 0x00000106,
17748PH_SC2_GFX_PIPE1_TO_0_TRANSITION = 0x00000107,
17749PH_SC2_PA0_DATA_FIFO_RD = 0x00000108,
17750PH_SC2_PA0_DATA_FIFO_WE = 0x00000109,
17751PH_SC2_PA0_FIFO_EMPTY = 0x0000010a,
17752PH_SC2_PA0_FIFO_FULL = 0x0000010b,
17753PH_SC2_PA0_NULL_WE = 0x0000010c,
17754PH_SC2_PA0_EVENT_WE = 0x0000010d,
17755PH_SC2_PA0_FPOV_WE = 0x0000010e,
17756PH_SC2_PA0_LPOV_WE = 0x0000010f,
17757PH_SC2_PA0_EOP_WE = 0x00000110,
17758PH_SC2_PA0_DATA_FIFO_EOP_RD = 0x00000111,
17759PH_SC2_PA0_EOPG_WE = 0x00000112,
17760PH_SC2_PA0_DEALLOC_4_0_RD = 0x00000113,
17761PH_SC2_PA1_DATA_FIFO_RD = 0x00000114,
17762PH_SC2_PA1_DATA_FIFO_WE = 0x00000115,
17763PH_SC2_PA1_FIFO_EMPTY = 0x00000116,
17764PH_SC2_PA1_FIFO_FULL = 0x00000117,
17765PH_SC2_PA1_NULL_WE = 0x00000118,
17766PH_SC2_PA1_EVENT_WE = 0x00000119,
17767PH_SC2_PA1_FPOV_WE = 0x0000011a,
17768PH_SC2_PA1_LPOV_WE = 0x0000011b,
17769PH_SC2_PA1_EOP_WE = 0x0000011c,
17770PH_SC2_PA1_DATA_FIFO_EOP_RD = 0x0000011d,
17771PH_SC2_PA1_EOPG_WE = 0x0000011e,
17772PH_SC2_PA1_DEALLOC_4_0_RD = 0x0000011f,
17773PH_SC2_PA2_DATA_FIFO_RD = 0x00000120,
17774PH_SC2_PA2_DATA_FIFO_WE = 0x00000121,
17775PH_SC2_PA2_FIFO_EMPTY = 0x00000122,
17776PH_SC2_PA2_FIFO_FULL = 0x00000123,
17777PH_SC2_PA2_NULL_WE = 0x00000124,
17778PH_SC2_PA2_EVENT_WE = 0x00000125,
17779PH_SC2_PA2_FPOV_WE = 0x00000126,
17780PH_SC2_PA2_LPOV_WE = 0x00000127,
17781PH_SC2_PA2_EOP_WE = 0x00000128,
17782PH_SC2_PA2_DATA_FIFO_EOP_RD = 0x00000129,
17783PH_SC2_PA2_EOPG_WE = 0x0000012a,
17784PH_SC2_PA2_DEALLOC_4_0_RD = 0x0000012b,
17785PH_SC2_PA3_DATA_FIFO_RD = 0x0000012c,
17786PH_SC2_PA3_DATA_FIFO_WE = 0x0000012d,
17787PH_SC2_PA3_FIFO_EMPTY = 0x0000012e,
17788PH_SC2_PA3_FIFO_FULL = 0x0000012f,
17789PH_SC2_PA3_NULL_WE = 0x00000130,
17790PH_SC2_PA3_EVENT_WE = 0x00000131,
17791PH_SC2_PA3_FPOV_WE = 0x00000132,
17792PH_SC2_PA3_LPOV_WE = 0x00000133,
17793PH_SC2_PA3_EOP_WE = 0x00000134,
17794PH_SC2_PA3_DATA_FIFO_EOP_RD = 0x00000135,
17795PH_SC2_PA3_EOPG_WE = 0x00000136,
17796PH_SC2_PA3_DEALLOC_4_0_RD = 0x00000137,
17797PH_SC2_PA4_DATA_FIFO_RD = 0x00000138,
17798PH_SC2_PA4_DATA_FIFO_WE = 0x00000139,
17799PH_SC2_PA4_FIFO_EMPTY = 0x0000013a,
17800PH_SC2_PA4_FIFO_FULL = 0x0000013b,
17801PH_SC2_PA4_NULL_WE = 0x0000013c,
17802PH_SC2_PA4_EVENT_WE = 0x0000013d,
17803PH_SC2_PA4_FPOV_WE = 0x0000013e,
17804PH_SC2_PA4_LPOV_WE = 0x0000013f,
17805PH_SC2_PA4_EOP_WE = 0x00000140,
17806PH_SC2_PA4_DATA_FIFO_EOP_RD = 0x00000141,
17807PH_SC2_PA4_EOPG_WE = 0x00000142,
17808PH_SC2_PA4_DEALLOC_4_0_RD = 0x00000143,
17809PH_SC2_PA5_DATA_FIFO_RD = 0x00000144,
17810PH_SC2_PA5_DATA_FIFO_WE = 0x00000145,
17811PH_SC2_PA5_FIFO_EMPTY = 0x00000146,
17812PH_SC2_PA5_FIFO_FULL = 0x00000147,
17813PH_SC2_PA5_NULL_WE = 0x00000148,
17814PH_SC2_PA5_EVENT_WE = 0x00000149,
17815PH_SC2_PA5_FPOV_WE = 0x0000014a,
17816PH_SC2_PA5_LPOV_WE = 0x0000014b,
17817PH_SC2_PA5_EOP_WE = 0x0000014c,
17818PH_SC2_PA5_DATA_FIFO_EOP_RD = 0x0000014d,
17819PH_SC2_PA5_EOPG_WE = 0x0000014e,
17820PH_SC2_PA5_DEALLOC_4_0_RD = 0x0000014f,
17821PH_SC2_PA6_DATA_FIFO_RD = 0x00000150,
17822PH_SC2_PA6_DATA_FIFO_WE = 0x00000151,
17823PH_SC2_PA6_FIFO_EMPTY = 0x00000152,
17824PH_SC2_PA6_FIFO_FULL = 0x00000153,
17825PH_SC2_PA6_NULL_WE = 0x00000154,
17826PH_SC2_PA6_EVENT_WE = 0x00000155,
17827PH_SC2_PA6_FPOV_WE = 0x00000156,
17828PH_SC2_PA6_LPOV_WE = 0x00000157,
17829PH_SC2_PA6_EOP_WE = 0x00000158,
17830PH_SC2_PA6_DATA_FIFO_EOP_RD = 0x00000159,
17831PH_SC2_PA6_EOPG_WE = 0x0000015a,
17832PH_SC2_PA6_DEALLOC_4_0_RD = 0x0000015b,
17833PH_SC2_PA7_DATA_FIFO_RD = 0x0000015c,
17834PH_SC2_PA7_DATA_FIFO_WE = 0x0000015d,
17835PH_SC2_PA7_FIFO_EMPTY = 0x0000015e,
17836PH_SC2_PA7_FIFO_FULL = 0x0000015f,
17837PH_SC2_PA7_NULL_WE = 0x00000160,
17838PH_SC2_PA7_EVENT_WE = 0x00000161,
17839PH_SC2_PA7_FPOV_WE = 0x00000162,
17840PH_SC2_PA7_LPOV_WE = 0x00000163,
17841PH_SC2_PA7_EOP_WE = 0x00000164,
17842PH_SC2_PA7_DATA_FIFO_EOP_RD = 0x00000165,
17843PH_SC2_PA7_EOPG_WE = 0x00000166,
17844PH_SC2_PA7_DEALLOC_4_0_RD = 0x00000167,
17845PH_SC3_SRPS_WINDOW_VALID = 0x00000168,
17846PH_SC3_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000169,
17847PH_SC3_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000016a,
17848PH_SC3_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000016b,
17849PH_SC3_ARB_STALLED_FROM_BELOW = 0x0000016c,
17850PH_SC3_ARB_STARVED_FROM_ABOVE = 0x0000016d,
17851PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000016e,
17852PH_SC3_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000016f,
17853PH_SC3_ARB_BUSY = 0x00000170,
17854PH_SC3_ARB_PA_BUSY_SOP = 0x00000171,
17855PH_SC3_ARB_EOP_POP_SYNC_POP = 0x00000172,
17856PH_SC3_ARB_EVENT_SYNC_POP = 0x00000173,
17857PH_SC3_PS_ENG_MULTICYCLE_BUBBLE = 0x00000174,
17858PH_SC3_EOP_SYNC_WINDOW = 0x00000175,
17859PH_SC3_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000176,
17860PH_SC3_BUSY_CNT_NOT_ZERO = 0x00000177,
17861PH_SC3_SEND = 0x00000178,
17862PH_SC3_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000179,
17863PH_SC3_CREDIT_AT_MAX = 0x0000017a,
17864PH_SC3_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000017b,
17865PH_SC3_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000017c,
17866PH_SC3_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000017d,
17867PH_SC3_GFX_PIPE0_TO_1_TRANSITION = 0x0000017e,
17868PH_SC3_GFX_PIPE1_TO_0_TRANSITION = 0x0000017f,
17869PH_SC3_PA0_DATA_FIFO_RD = 0x00000180,
17870PH_SC3_PA0_DATA_FIFO_WE = 0x00000181,
17871PH_SC3_PA0_FIFO_EMPTY = 0x00000182,
17872PH_SC3_PA0_FIFO_FULL = 0x00000183,
17873PH_SC3_PA0_NULL_WE = 0x00000184,
17874PH_SC3_PA0_EVENT_WE = 0x00000185,
17875PH_SC3_PA0_FPOV_WE = 0x00000186,
17876PH_SC3_PA0_LPOV_WE = 0x00000187,
17877PH_SC3_PA0_EOP_WE = 0x00000188,
17878PH_SC3_PA0_DATA_FIFO_EOP_RD = 0x00000189,
17879PH_SC3_PA0_EOPG_WE = 0x0000018a,
17880PH_SC3_PA0_DEALLOC_4_0_RD = 0x0000018b,
17881PH_SC3_PA1_DATA_FIFO_RD = 0x0000018c,
17882PH_SC3_PA1_DATA_FIFO_WE = 0x0000018d,
17883PH_SC3_PA1_FIFO_EMPTY = 0x0000018e,
17884PH_SC3_PA1_FIFO_FULL = 0x0000018f,
17885PH_SC3_PA1_NULL_WE = 0x00000190,
17886PH_SC3_PA1_EVENT_WE = 0x00000191,
17887PH_SC3_PA1_FPOV_WE = 0x00000192,
17888PH_SC3_PA1_LPOV_WE = 0x00000193,
17889PH_SC3_PA1_EOP_WE = 0x00000194,
17890PH_SC3_PA1_DATA_FIFO_EOP_RD = 0x00000195,
17891PH_SC3_PA1_EOPG_WE = 0x00000196,
17892PH_SC3_PA1_DEALLOC_4_0_RD = 0x00000197,
17893PH_SC3_PA2_DATA_FIFO_RD = 0x00000198,
17894PH_SC3_PA2_DATA_FIFO_WE = 0x00000199,
17895PH_SC3_PA2_FIFO_EMPTY = 0x0000019a,
17896PH_SC3_PA2_FIFO_FULL = 0x0000019b,
17897PH_SC3_PA2_NULL_WE = 0x0000019c,
17898PH_SC3_PA2_EVENT_WE = 0x0000019d,
17899PH_SC3_PA2_FPOV_WE = 0x0000019e,
17900PH_SC3_PA2_LPOV_WE = 0x0000019f,
17901PH_SC3_PA2_EOP_WE = 0x000001a0,
17902PH_SC3_PA2_DATA_FIFO_EOP_RD = 0x000001a1,
17903PH_SC3_PA2_EOPG_WE = 0x000001a2,
17904PH_SC3_PA2_DEALLOC_4_0_RD = 0x000001a3,
17905PH_SC3_PA3_DATA_FIFO_RD = 0x000001a4,
17906PH_SC3_PA3_DATA_FIFO_WE = 0x000001a5,
17907PH_SC3_PA3_FIFO_EMPTY = 0x000001a6,
17908PH_SC3_PA3_FIFO_FULL = 0x000001a7,
17909PH_SC3_PA3_NULL_WE = 0x000001a8,
17910PH_SC3_PA3_EVENT_WE = 0x000001a9,
17911PH_SC3_PA3_FPOV_WE = 0x000001aa,
17912PH_SC3_PA3_LPOV_WE = 0x000001ab,
17913PH_SC3_PA3_EOP_WE = 0x000001ac,
17914PH_SC3_PA3_DATA_FIFO_EOP_RD = 0x000001ad,
17915PH_SC3_PA3_EOPG_WE = 0x000001ae,
17916PH_SC3_PA3_DEALLOC_4_0_RD = 0x000001af,
17917PH_SC3_PA4_DATA_FIFO_RD = 0x000001b0,
17918PH_SC3_PA4_DATA_FIFO_WE = 0x000001b1,
17919PH_SC3_PA4_FIFO_EMPTY = 0x000001b2,
17920PH_SC3_PA4_FIFO_FULL = 0x000001b3,
17921PH_SC3_PA4_NULL_WE = 0x000001b4,
17922PH_SC3_PA4_EVENT_WE = 0x000001b5,
17923PH_SC3_PA4_FPOV_WE = 0x000001b6,
17924PH_SC3_PA4_LPOV_WE = 0x000001b7,
17925PH_SC3_PA4_EOP_WE = 0x000001b8,
17926PH_SC3_PA4_DATA_FIFO_EOP_RD = 0x000001b9,
17927PH_SC3_PA4_EOPG_WE = 0x000001ba,
17928PH_SC3_PA4_DEALLOC_4_0_RD = 0x000001bb,
17929PH_SC3_PA5_DATA_FIFO_RD = 0x000001bc,
17930PH_SC3_PA5_DATA_FIFO_WE = 0x000001bd,
17931PH_SC3_PA5_FIFO_EMPTY = 0x000001be,
17932PH_SC3_PA5_FIFO_FULL = 0x000001bf,
17933PH_SC3_PA5_NULL_WE = 0x000001c0,
17934PH_SC3_PA5_EVENT_WE = 0x000001c1,
17935PH_SC3_PA5_FPOV_WE = 0x000001c2,
17936PH_SC3_PA5_LPOV_WE = 0x000001c3,
17937PH_SC3_PA5_EOP_WE = 0x000001c4,
17938PH_SC3_PA5_DATA_FIFO_EOP_RD = 0x000001c5,
17939PH_SC3_PA5_EOPG_WE = 0x000001c6,
17940PH_SC3_PA5_DEALLOC_4_0_RD = 0x000001c7,
17941PH_SC3_PA6_DATA_FIFO_RD = 0x000001c8,
17942PH_SC3_PA6_DATA_FIFO_WE = 0x000001c9,
17943PH_SC3_PA6_FIFO_EMPTY = 0x000001ca,
17944PH_SC3_PA6_FIFO_FULL = 0x000001cb,
17945PH_SC3_PA6_NULL_WE = 0x000001cc,
17946PH_SC3_PA6_EVENT_WE = 0x000001cd,
17947PH_SC3_PA6_FPOV_WE = 0x000001ce,
17948PH_SC3_PA6_LPOV_WE = 0x000001cf,
17949PH_SC3_PA6_EOP_WE = 0x000001d0,
17950PH_SC3_PA6_DATA_FIFO_EOP_RD = 0x000001d1,
17951PH_SC3_PA6_EOPG_WE = 0x000001d2,
17952PH_SC3_PA6_DEALLOC_4_0_RD = 0x000001d3,
17953PH_SC3_PA7_DATA_FIFO_RD = 0x000001d4,
17954PH_SC3_PA7_DATA_FIFO_WE = 0x000001d5,
17955PH_SC3_PA7_FIFO_EMPTY = 0x000001d6,
17956PH_SC3_PA7_FIFO_FULL = 0x000001d7,
17957PH_SC3_PA7_NULL_WE = 0x000001d8,
17958PH_SC3_PA7_EVENT_WE = 0x000001d9,
17959PH_SC3_PA7_FPOV_WE = 0x000001da,
17960PH_SC3_PA7_LPOV_WE = 0x000001db,
17961PH_SC3_PA7_EOP_WE = 0x000001dc,
17962PH_SC3_PA7_DATA_FIFO_EOP_RD = 0x000001dd,
17963PH_SC3_PA7_EOPG_WE = 0x000001de,
17964PH_SC3_PA7_DEALLOC_4_0_RD = 0x000001df,
17965PH_SC4_SRPS_WINDOW_VALID = 0x000001e0,
17966PH_SC4_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000001e1,
17967PH_SC4_ARB_XFC_ONLY_PRIM_CYCLES = 0x000001e2,
17968PH_SC4_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000001e3,
17969PH_SC4_ARB_STALLED_FROM_BELOW = 0x000001e4,
17970PH_SC4_ARB_STARVED_FROM_ABOVE = 0x000001e5,
17971PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000001e6,
17972PH_SC4_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000001e7,
17973PH_SC4_ARB_BUSY = 0x000001e8,
17974PH_SC4_ARB_PA_BUSY_SOP = 0x000001e9,
17975PH_SC4_ARB_EOP_POP_SYNC_POP = 0x000001ea,
17976PH_SC4_ARB_EVENT_SYNC_POP = 0x000001eb,
17977PH_SC4_PS_ENG_MULTICYCLE_BUBBLE = 0x000001ec,
17978PH_SC4_EOP_SYNC_WINDOW = 0x000001ed,
17979PH_SC4_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000001ee,
17980PH_SC4_BUSY_CNT_NOT_ZERO = 0x000001ef,
17981PH_SC4_SEND = 0x000001f0,
17982PH_SC4_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001f1,
17983PH_SC4_CREDIT_AT_MAX = 0x000001f2,
17984PH_SC4_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001f3,
17985PH_SC4_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000001f4,
17986PH_SC4_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000001f5,
17987PH_SC4_GFX_PIPE0_TO_1_TRANSITION = 0x000001f6,
17988PH_SC4_GFX_PIPE1_TO_0_TRANSITION = 0x000001f7,
17989PH_SC4_PA0_DATA_FIFO_RD = 0x000001f8,
17990PH_SC4_PA0_DATA_FIFO_WE = 0x000001f9,
17991PH_SC4_PA0_FIFO_EMPTY = 0x000001fa,
17992PH_SC4_PA0_FIFO_FULL = 0x000001fb,
17993PH_SC4_PA0_NULL_WE = 0x000001fc,
17994PH_SC4_PA0_EVENT_WE = 0x000001fd,
17995PH_SC4_PA0_FPOV_WE = 0x000001fe,
17996PH_SC4_PA0_LPOV_WE = 0x000001ff,
17997PH_SC4_PA0_EOP_WE = 0x00000200,
17998PH_SC4_PA0_DATA_FIFO_EOP_RD = 0x00000201,
17999PH_SC4_PA0_EOPG_WE = 0x00000202,
18000PH_SC4_PA0_DEALLOC_4_0_RD = 0x00000203,
18001PH_SC4_PA1_DATA_FIFO_RD = 0x00000204,
18002PH_SC4_PA1_DATA_FIFO_WE = 0x00000205,
18003PH_SC4_PA1_FIFO_EMPTY = 0x00000206,
18004PH_SC4_PA1_FIFO_FULL = 0x00000207,
18005PH_SC4_PA1_NULL_WE = 0x00000208,
18006PH_SC4_PA1_EVENT_WE = 0x00000209,
18007PH_SC4_PA1_FPOV_WE = 0x0000020a,
18008PH_SC4_PA1_LPOV_WE = 0x0000020b,
18009PH_SC4_PA1_EOP_WE = 0x0000020c,
18010PH_SC4_PA1_DATA_FIFO_EOP_RD = 0x0000020d,
18011PH_SC4_PA1_EOPG_WE = 0x0000020e,
18012PH_SC4_PA1_DEALLOC_4_0_RD = 0x0000020f,
18013PH_SC4_PA2_DATA_FIFO_RD = 0x00000210,
18014PH_SC4_PA2_DATA_FIFO_WE = 0x00000211,
18015PH_SC4_PA2_FIFO_EMPTY = 0x00000212,
18016PH_SC4_PA2_FIFO_FULL = 0x00000213,
18017PH_SC4_PA2_NULL_WE = 0x00000214,
18018PH_SC4_PA2_EVENT_WE = 0x00000215,
18019PH_SC4_PA2_FPOV_WE = 0x00000216,
18020PH_SC4_PA2_LPOV_WE = 0x00000217,
18021PH_SC4_PA2_EOP_WE = 0x00000218,
18022PH_SC4_PA2_DATA_FIFO_EOP_RD = 0x00000219,
18023PH_SC4_PA2_EOPG_WE = 0x0000021a,
18024PH_SC4_PA2_DEALLOC_4_0_RD = 0x0000021b,
18025PH_SC4_PA3_DATA_FIFO_RD = 0x0000021c,
18026PH_SC4_PA3_DATA_FIFO_WE = 0x0000021d,
18027PH_SC4_PA3_FIFO_EMPTY = 0x0000021e,
18028PH_SC4_PA3_FIFO_FULL = 0x0000021f,
18029PH_SC4_PA3_NULL_WE = 0x00000220,
18030PH_SC4_PA3_EVENT_WE = 0x00000221,
18031PH_SC4_PA3_FPOV_WE = 0x00000222,
18032PH_SC4_PA3_LPOV_WE = 0x00000223,
18033PH_SC4_PA3_EOP_WE = 0x00000224,
18034PH_SC4_PA3_DATA_FIFO_EOP_RD = 0x00000225,
18035PH_SC4_PA3_EOPG_WE = 0x00000226,
18036PH_SC4_PA3_DEALLOC_4_0_RD = 0x00000227,
18037PH_SC4_PA4_DATA_FIFO_RD = 0x00000228,
18038PH_SC4_PA4_DATA_FIFO_WE = 0x00000229,
18039PH_SC4_PA4_FIFO_EMPTY = 0x0000022a,
18040PH_SC4_PA4_FIFO_FULL = 0x0000022b,
18041PH_SC4_PA4_NULL_WE = 0x0000022c,
18042PH_SC4_PA4_EVENT_WE = 0x0000022d,
18043PH_SC4_PA4_FPOV_WE = 0x0000022e,
18044PH_SC4_PA4_LPOV_WE = 0x0000022f,
18045PH_SC4_PA4_EOP_WE = 0x00000230,
18046PH_SC4_PA4_DATA_FIFO_EOP_RD = 0x00000231,
18047PH_SC4_PA4_EOPG_WE = 0x00000232,
18048PH_SC4_PA4_DEALLOC_4_0_RD = 0x00000233,
18049PH_SC4_PA5_DATA_FIFO_RD = 0x00000234,
18050PH_SC4_PA5_DATA_FIFO_WE = 0x00000235,
18051PH_SC4_PA5_FIFO_EMPTY = 0x00000236,
18052PH_SC4_PA5_FIFO_FULL = 0x00000237,
18053PH_SC4_PA5_NULL_WE = 0x00000238,
18054PH_SC4_PA5_EVENT_WE = 0x00000239,
18055PH_SC4_PA5_FPOV_WE = 0x0000023a,
18056PH_SC4_PA5_LPOV_WE = 0x0000023b,
18057PH_SC4_PA5_EOP_WE = 0x0000023c,
18058PH_SC4_PA5_DATA_FIFO_EOP_RD = 0x0000023d,
18059PH_SC4_PA5_EOPG_WE = 0x0000023e,
18060PH_SC4_PA5_DEALLOC_4_0_RD = 0x0000023f,
18061PH_SC4_PA6_DATA_FIFO_RD = 0x00000240,
18062PH_SC4_PA6_DATA_FIFO_WE = 0x00000241,
18063PH_SC4_PA6_FIFO_EMPTY = 0x00000242,
18064PH_SC4_PA6_FIFO_FULL = 0x00000243,
18065PH_SC4_PA6_NULL_WE = 0x00000244,
18066PH_SC4_PA6_EVENT_WE = 0x00000245,
18067PH_SC4_PA6_FPOV_WE = 0x00000246,
18068PH_SC4_PA6_LPOV_WE = 0x00000247,
18069PH_SC4_PA6_EOP_WE = 0x00000248,
18070PH_SC4_PA6_DATA_FIFO_EOP_RD = 0x00000249,
18071PH_SC4_PA6_EOPG_WE = 0x0000024a,
18072PH_SC4_PA6_DEALLOC_4_0_RD = 0x0000024b,
18073PH_SC4_PA7_DATA_FIFO_RD = 0x0000024c,
18074PH_SC4_PA7_DATA_FIFO_WE = 0x0000024d,
18075PH_SC4_PA7_FIFO_EMPTY = 0x0000024e,
18076PH_SC4_PA7_FIFO_FULL = 0x0000024f,
18077PH_SC4_PA7_NULL_WE = 0x00000250,
18078PH_SC4_PA7_EVENT_WE = 0x00000251,
18079PH_SC4_PA7_FPOV_WE = 0x00000252,
18080PH_SC4_PA7_LPOV_WE = 0x00000253,
18081PH_SC4_PA7_EOP_WE = 0x00000254,
18082PH_SC4_PA7_DATA_FIFO_EOP_RD = 0x00000255,
18083PH_SC4_PA7_EOPG_WE = 0x00000256,
18084PH_SC4_PA7_DEALLOC_4_0_RD = 0x00000257,
18085PH_SC5_SRPS_WINDOW_VALID = 0x00000258,
18086PH_SC5_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000259,
18087PH_SC5_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000025a,
18088PH_SC5_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000025b,
18089PH_SC5_ARB_STALLED_FROM_BELOW = 0x0000025c,
18090PH_SC5_ARB_STARVED_FROM_ABOVE = 0x0000025d,
18091PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000025e,
18092PH_SC5_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000025f,
18093PH_SC5_ARB_BUSY = 0x00000260,
18094PH_SC5_ARB_PA_BUSY_SOP = 0x00000261,
18095PH_SC5_ARB_EOP_POP_SYNC_POP = 0x00000262,
18096PH_SC5_ARB_EVENT_SYNC_POP = 0x00000263,
18097PH_SC5_PS_ENG_MULTICYCLE_BUBBLE = 0x00000264,
18098PH_SC5_EOP_SYNC_WINDOW = 0x00000265,
18099PH_SC5_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000266,
18100PH_SC5_BUSY_CNT_NOT_ZERO = 0x00000267,
18101PH_SC5_SEND = 0x00000268,
18102PH_SC5_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000269,
18103PH_SC5_CREDIT_AT_MAX = 0x0000026a,
18104PH_SC5_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000026b,
18105PH_SC5_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000026c,
18106PH_SC5_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000026d,
18107PH_SC5_GFX_PIPE0_TO_1_TRANSITION = 0x0000026e,
18108PH_SC5_GFX_PIPE1_TO_0_TRANSITION = 0x0000026f,
18109PH_SC5_PA0_DATA_FIFO_RD = 0x00000270,
18110PH_SC5_PA0_DATA_FIFO_WE = 0x00000271,
18111PH_SC5_PA0_FIFO_EMPTY = 0x00000272,
18112PH_SC5_PA0_FIFO_FULL = 0x00000273,
18113PH_SC5_PA0_NULL_WE = 0x00000274,
18114PH_SC5_PA0_EVENT_WE = 0x00000275,
18115PH_SC5_PA0_FPOV_WE = 0x00000276,
18116PH_SC5_PA0_LPOV_WE = 0x00000277,
18117PH_SC5_PA0_EOP_WE = 0x00000278,
18118PH_SC5_PA0_DATA_FIFO_EOP_RD = 0x00000279,
18119PH_SC5_PA0_EOPG_WE = 0x0000027a,
18120PH_SC5_PA0_DEALLOC_4_0_RD = 0x0000027b,
18121PH_SC5_PA1_DATA_FIFO_RD = 0x0000027c,
18122PH_SC5_PA1_DATA_FIFO_WE = 0x0000027d,
18123PH_SC5_PA1_FIFO_EMPTY = 0x0000027e,
18124PH_SC5_PA1_FIFO_FULL = 0x0000027f,
18125PH_SC5_PA1_NULL_WE = 0x00000280,
18126PH_SC5_PA1_EVENT_WE = 0x00000281,
18127PH_SC5_PA1_FPOV_WE = 0x00000282,
18128PH_SC5_PA1_LPOV_WE = 0x00000283,
18129PH_SC5_PA1_EOP_WE = 0x00000284,
18130PH_SC5_PA1_DATA_FIFO_EOP_RD = 0x00000285,
18131PH_SC5_PA1_EOPG_WE = 0x00000286,
18132PH_SC5_PA1_DEALLOC_4_0_RD = 0x00000287,
18133PH_SC5_PA2_DATA_FIFO_RD = 0x00000288,
18134PH_SC5_PA2_DATA_FIFO_WE = 0x00000289,
18135PH_SC5_PA2_FIFO_EMPTY = 0x0000028a,
18136PH_SC5_PA2_FIFO_FULL = 0x0000028b,
18137PH_SC5_PA2_NULL_WE = 0x0000028c,
18138PH_SC5_PA2_EVENT_WE = 0x0000028d,
18139PH_SC5_PA2_FPOV_WE = 0x0000028e,
18140PH_SC5_PA2_LPOV_WE = 0x0000028f,
18141PH_SC5_PA2_EOP_WE = 0x00000290,
18142PH_SC5_PA2_DATA_FIFO_EOP_RD = 0x00000291,
18143PH_SC5_PA2_EOPG_WE = 0x00000292,
18144PH_SC5_PA2_DEALLOC_4_0_RD = 0x00000293,
18145PH_SC5_PA3_DATA_FIFO_RD = 0x00000294,
18146PH_SC5_PA3_DATA_FIFO_WE = 0x00000295,
18147PH_SC5_PA3_FIFO_EMPTY = 0x00000296,
18148PH_SC5_PA3_FIFO_FULL = 0x00000297,
18149PH_SC5_PA3_NULL_WE = 0x00000298,
18150PH_SC5_PA3_EVENT_WE = 0x00000299,
18151PH_SC5_PA3_FPOV_WE = 0x0000029a,
18152PH_SC5_PA3_LPOV_WE = 0x0000029b,
18153PH_SC5_PA3_EOP_WE = 0x0000029c,
18154PH_SC5_PA3_DATA_FIFO_EOP_RD = 0x0000029d,
18155PH_SC5_PA3_EOPG_WE = 0x0000029e,
18156PH_SC5_PA3_DEALLOC_4_0_RD = 0x0000029f,
18157PH_SC5_PA4_DATA_FIFO_RD = 0x000002a0,
18158PH_SC5_PA4_DATA_FIFO_WE = 0x000002a1,
18159PH_SC5_PA4_FIFO_EMPTY = 0x000002a2,
18160PH_SC5_PA4_FIFO_FULL = 0x000002a3,
18161PH_SC5_PA4_NULL_WE = 0x000002a4,
18162PH_SC5_PA4_EVENT_WE = 0x000002a5,
18163PH_SC5_PA4_FPOV_WE = 0x000002a6,
18164PH_SC5_PA4_LPOV_WE = 0x000002a7,
18165PH_SC5_PA4_EOP_WE = 0x000002a8,
18166PH_SC5_PA4_DATA_FIFO_EOP_RD = 0x000002a9,
18167PH_SC5_PA4_EOPG_WE = 0x000002aa,
18168PH_SC5_PA4_DEALLOC_4_0_RD = 0x000002ab,
18169PH_SC5_PA5_DATA_FIFO_RD = 0x000002ac,
18170PH_SC5_PA5_DATA_FIFO_WE = 0x000002ad,
18171PH_SC5_PA5_FIFO_EMPTY = 0x000002ae,
18172PH_SC5_PA5_FIFO_FULL = 0x000002af,
18173PH_SC5_PA5_NULL_WE = 0x000002b0,
18174PH_SC5_PA5_EVENT_WE = 0x000002b1,
18175PH_SC5_PA5_FPOV_WE = 0x000002b2,
18176PH_SC5_PA5_LPOV_WE = 0x000002b3,
18177PH_SC5_PA5_EOP_WE = 0x000002b4,
18178PH_SC5_PA5_DATA_FIFO_EOP_RD = 0x000002b5,
18179PH_SC5_PA5_EOPG_WE = 0x000002b6,
18180PH_SC5_PA5_DEALLOC_4_0_RD = 0x000002b7,
18181PH_SC5_PA6_DATA_FIFO_RD = 0x000002b8,
18182PH_SC5_PA6_DATA_FIFO_WE = 0x000002b9,
18183PH_SC5_PA6_FIFO_EMPTY = 0x000002ba,
18184PH_SC5_PA6_FIFO_FULL = 0x000002bb,
18185PH_SC5_PA6_NULL_WE = 0x000002bc,
18186PH_SC5_PA6_EVENT_WE = 0x000002bd,
18187PH_SC5_PA6_FPOV_WE = 0x000002be,
18188PH_SC5_PA6_LPOV_WE = 0x000002bf,
18189PH_SC5_PA6_EOP_WE = 0x000002c0,
18190PH_SC5_PA6_DATA_FIFO_EOP_RD = 0x000002c1,
18191PH_SC5_PA6_EOPG_WE = 0x000002c2,
18192PH_SC5_PA6_DEALLOC_4_0_RD = 0x000002c3,
18193PH_SC5_PA7_DATA_FIFO_RD = 0x000002c4,
18194PH_SC5_PA7_DATA_FIFO_WE = 0x000002c5,
18195PH_SC5_PA7_FIFO_EMPTY = 0x000002c6,
18196PH_SC5_PA7_FIFO_FULL = 0x000002c7,
18197PH_SC5_PA7_NULL_WE = 0x000002c8,
18198PH_SC5_PA7_EVENT_WE = 0x000002c9,
18199PH_SC5_PA7_FPOV_WE = 0x000002ca,
18200PH_SC5_PA7_LPOV_WE = 0x000002cb,
18201PH_SC5_PA7_EOP_WE = 0x000002cc,
18202PH_SC5_PA7_DATA_FIFO_EOP_RD = 0x000002cd,
18203PH_SC5_PA7_EOPG_WE = 0x000002ce,
18204PH_SC5_PA7_DEALLOC_4_0_RD = 0x000002cf,
18205PH_SC6_SRPS_WINDOW_VALID = 0x000002d0,
18206PH_SC6_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x000002d1,
18207PH_SC6_ARB_XFC_ONLY_PRIM_CYCLES = 0x000002d2,
18208PH_SC6_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x000002d3,
18209PH_SC6_ARB_STALLED_FROM_BELOW = 0x000002d4,
18210PH_SC6_ARB_STARVED_FROM_ABOVE = 0x000002d5,
18211PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x000002d6,
18212PH_SC6_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x000002d7,
18213PH_SC6_ARB_BUSY = 0x000002d8,
18214PH_SC6_ARB_PA_BUSY_SOP = 0x000002d9,
18215PH_SC6_ARB_EOP_POP_SYNC_POP = 0x000002da,
18216PH_SC6_ARB_EVENT_SYNC_POP = 0x000002db,
18217PH_SC6_PS_ENG_MULTICYCLE_BUBBLE = 0x000002dc,
18218PH_SC6_EOP_SYNC_WINDOW = 0x000002dd,
18219PH_SC6_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x000002de,
18220PH_SC6_BUSY_CNT_NOT_ZERO = 0x000002df,
18221PH_SC6_SEND = 0x000002e0,
18222PH_SC6_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000002e1,
18223PH_SC6_CREDIT_AT_MAX = 0x000002e2,
18224PH_SC6_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000002e3,
18225PH_SC6_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x000002e4,
18226PH_SC6_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x000002e5,
18227PH_SC6_GFX_PIPE0_TO_1_TRANSITION = 0x000002e6,
18228PH_SC6_GFX_PIPE1_TO_0_TRANSITION = 0x000002e7,
18229PH_SC6_PA0_DATA_FIFO_RD = 0x000002e8,
18230PH_SC6_PA0_DATA_FIFO_WE = 0x000002e9,
18231PH_SC6_PA0_FIFO_EMPTY = 0x000002ea,
18232PH_SC6_PA0_FIFO_FULL = 0x000002eb,
18233PH_SC6_PA0_NULL_WE = 0x000002ec,
18234PH_SC6_PA0_EVENT_WE = 0x000002ed,
18235PH_SC6_PA0_FPOV_WE = 0x000002ee,
18236PH_SC6_PA0_LPOV_WE = 0x000002ef,
18237PH_SC6_PA0_EOP_WE = 0x000002f0,
18238PH_SC6_PA0_DATA_FIFO_EOP_RD = 0x000002f1,
18239PH_SC6_PA0_EOPG_WE = 0x000002f2,
18240PH_SC6_PA0_DEALLOC_4_0_RD = 0x000002f3,
18241PH_SC6_PA1_DATA_FIFO_RD = 0x000002f4,
18242PH_SC6_PA1_DATA_FIFO_WE = 0x000002f5,
18243PH_SC6_PA1_FIFO_EMPTY = 0x000002f6,
18244PH_SC6_PA1_FIFO_FULL = 0x000002f7,
18245PH_SC6_PA1_NULL_WE = 0x000002f8,
18246PH_SC6_PA1_EVENT_WE = 0x000002f9,
18247PH_SC6_PA1_FPOV_WE = 0x000002fa,
18248PH_SC6_PA1_LPOV_WE = 0x000002fb,
18249PH_SC6_PA1_EOP_WE = 0x000002fc,
18250PH_SC6_PA1_DATA_FIFO_EOP_RD = 0x000002fd,
18251PH_SC6_PA1_EOPG_WE = 0x000002fe,
18252PH_SC6_PA1_DEALLOC_4_0_RD = 0x000002ff,
18253PH_SC6_PA2_DATA_FIFO_RD = 0x00000300,
18254PH_SC6_PA2_DATA_FIFO_WE = 0x00000301,
18255PH_SC6_PA2_FIFO_EMPTY = 0x00000302,
18256PH_SC6_PA2_FIFO_FULL = 0x00000303,
18257PH_SC6_PA2_NULL_WE = 0x00000304,
18258PH_SC6_PA2_EVENT_WE = 0x00000305,
18259PH_SC6_PA2_FPOV_WE = 0x00000306,
18260PH_SC6_PA2_LPOV_WE = 0x00000307,
18261PH_SC6_PA2_EOP_WE = 0x00000308,
18262PH_SC6_PA2_DATA_FIFO_EOP_RD = 0x00000309,
18263PH_SC6_PA2_EOPG_WE = 0x0000030a,
18264PH_SC6_PA2_DEALLOC_4_0_RD = 0x0000030b,
18265PH_SC6_PA3_DATA_FIFO_RD = 0x0000030c,
18266PH_SC6_PA3_DATA_FIFO_WE = 0x0000030d,
18267PH_SC6_PA3_FIFO_EMPTY = 0x0000030e,
18268PH_SC6_PA3_FIFO_FULL = 0x0000030f,
18269PH_SC6_PA3_NULL_WE = 0x00000310,
18270PH_SC6_PA3_EVENT_WE = 0x00000311,
18271PH_SC6_PA3_FPOV_WE = 0x00000312,
18272PH_SC6_PA3_LPOV_WE = 0x00000313,
18273PH_SC6_PA3_EOP_WE = 0x00000314,
18274PH_SC6_PA3_DATA_FIFO_EOP_RD = 0x00000315,
18275PH_SC6_PA3_EOPG_WE = 0x00000316,
18276PH_SC6_PA3_DEALLOC_4_0_RD = 0x00000317,
18277PH_SC6_PA4_DATA_FIFO_RD = 0x00000318,
18278PH_SC6_PA4_DATA_FIFO_WE = 0x00000319,
18279PH_SC6_PA4_FIFO_EMPTY = 0x0000031a,
18280PH_SC6_PA4_FIFO_FULL = 0x0000031b,
18281PH_SC6_PA4_NULL_WE = 0x0000031c,
18282PH_SC6_PA4_EVENT_WE = 0x0000031d,
18283PH_SC6_PA4_FPOV_WE = 0x0000031e,
18284PH_SC6_PA4_LPOV_WE = 0x0000031f,
18285PH_SC6_PA4_EOP_WE = 0x00000320,
18286PH_SC6_PA4_DATA_FIFO_EOP_RD = 0x00000321,
18287PH_SC6_PA4_EOPG_WE = 0x00000322,
18288PH_SC6_PA4_DEALLOC_4_0_RD = 0x00000323,
18289PH_SC6_PA5_DATA_FIFO_RD = 0x00000324,
18290PH_SC6_PA5_DATA_FIFO_WE = 0x00000325,
18291PH_SC6_PA5_FIFO_EMPTY = 0x00000326,
18292PH_SC6_PA5_FIFO_FULL = 0x00000327,
18293PH_SC6_PA5_NULL_WE = 0x00000328,
18294PH_SC6_PA5_EVENT_WE = 0x00000329,
18295PH_SC6_PA5_FPOV_WE = 0x0000032a,
18296PH_SC6_PA5_LPOV_WE = 0x0000032b,
18297PH_SC6_PA5_EOP_WE = 0x0000032c,
18298PH_SC6_PA5_DATA_FIFO_EOP_RD = 0x0000032d,
18299PH_SC6_PA5_EOPG_WE = 0x0000032e,
18300PH_SC6_PA5_DEALLOC_4_0_RD = 0x0000032f,
18301PH_SC6_PA6_DATA_FIFO_RD = 0x00000330,
18302PH_SC6_PA6_DATA_FIFO_WE = 0x00000331,
18303PH_SC6_PA6_FIFO_EMPTY = 0x00000332,
18304PH_SC6_PA6_FIFO_FULL = 0x00000333,
18305PH_SC6_PA6_NULL_WE = 0x00000334,
18306PH_SC6_PA6_EVENT_WE = 0x00000335,
18307PH_SC6_PA6_FPOV_WE = 0x00000336,
18308PH_SC6_PA6_LPOV_WE = 0x00000337,
18309PH_SC6_PA6_EOP_WE = 0x00000338,
18310PH_SC6_PA6_DATA_FIFO_EOP_RD = 0x00000339,
18311PH_SC6_PA6_EOPG_WE = 0x0000033a,
18312PH_SC6_PA6_DEALLOC_4_0_RD = 0x0000033b,
18313PH_SC6_PA7_DATA_FIFO_RD = 0x0000033c,
18314PH_SC6_PA7_DATA_FIFO_WE = 0x0000033d,
18315PH_SC6_PA7_FIFO_EMPTY = 0x0000033e,
18316PH_SC6_PA7_FIFO_FULL = 0x0000033f,
18317PH_SC6_PA7_NULL_WE = 0x00000340,
18318PH_SC6_PA7_EVENT_WE = 0x00000341,
18319PH_SC6_PA7_FPOV_WE = 0x00000342,
18320PH_SC6_PA7_LPOV_WE = 0x00000343,
18321PH_SC6_PA7_EOP_WE = 0x00000344,
18322PH_SC6_PA7_DATA_FIFO_EOP_RD = 0x00000345,
18323PH_SC6_PA7_EOPG_WE = 0x00000346,
18324PH_SC6_PA7_DEALLOC_4_0_RD = 0x00000347,
18325PH_SC7_SRPS_WINDOW_VALID = 0x00000348,
18326PH_SC7_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000349,
18327PH_SC7_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000034a,
18328PH_SC7_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000034b,
18329PH_SC7_ARB_STALLED_FROM_BELOW = 0x0000034c,
18330PH_SC7_ARB_STARVED_FROM_ABOVE = 0x0000034d,
18331PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_NOT_EMPTY = 0x0000034e,
18332PH_SC7_ARB_STARVED_FROM_ABOVE_WITH_UNSELECTED_FIFO_FULL = 0x0000034f,
18333PH_SC7_ARB_BUSY = 0x00000350,
18334PH_SC7_ARB_PA_BUSY_SOP = 0x00000351,
18335PH_SC7_ARB_EOP_POP_SYNC_POP = 0x00000352,
18336PH_SC7_ARB_EVENT_SYNC_POP = 0x00000353,
18337PH_SC7_PS_ENG_MULTICYCLE_BUBBLE = 0x00000354,
18338PH_SC7_EOP_SYNC_WINDOW = 0x00000355,
18339PH_SC7_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000356,
18340PH_SC7_BUSY_CNT_NOT_ZERO = 0x00000357,
18341PH_SC7_SEND = 0x00000358,
18342PH_SC7_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x00000359,
18343PH_SC7_CREDIT_AT_MAX = 0x0000035a,
18344PH_SC7_CREDIT_AT_MAX_NO_PENDING_SEND = 0x0000035b,
18345PH_SC7_GFX_PIPE_EVENT_PROVOKED_TRANSITION = 0x0000035c,
18346PH_SC7_GFX_PIPE_EOP_PRIM_PROVOKED_TRANSITION = 0x0000035d,
18347PH_SC7_GFX_PIPE0_TO_1_TRANSITION = 0x0000035e,
18348PH_SC7_GFX_PIPE1_TO_0_TRANSITION = 0x0000035f,
18349PH_SC7_PA0_DATA_FIFO_RD = 0x00000360,
18350PH_SC7_PA0_DATA_FIFO_WE = 0x00000361,
18351PH_SC7_PA0_FIFO_EMPTY = 0x00000362,
18352PH_SC7_PA0_FIFO_FULL = 0x00000363,
18353PH_SC7_PA0_NULL_WE = 0x00000364,
18354PH_SC7_PA0_EVENT_WE = 0x00000365,
18355PH_SC7_PA0_FPOV_WE = 0x00000366,
18356PH_SC7_PA0_LPOV_WE = 0x00000367,
18357PH_SC7_PA0_EOP_WE = 0x00000368,
18358PH_SC7_PA0_DATA_FIFO_EOP_RD = 0x00000369,
18359PH_SC7_PA0_EOPG_WE = 0x0000036a,
18360PH_SC7_PA0_DEALLOC_4_0_RD = 0x0000036b,
18361PH_SC7_PA1_DATA_FIFO_RD = 0x0000036c,
18362PH_SC7_PA1_DATA_FIFO_WE = 0x0000036d,
18363PH_SC7_PA1_FIFO_EMPTY = 0x0000036e,
18364PH_SC7_PA1_FIFO_FULL = 0x0000036f,
18365PH_SC7_PA1_NULL_WE = 0x00000370,
18366PH_SC7_PA1_EVENT_WE = 0x00000371,
18367PH_SC7_PA1_FPOV_WE = 0x00000372,
18368PH_SC7_PA1_LPOV_WE = 0x00000373,
18369PH_SC7_PA1_EOP_WE = 0x00000374,
18370PH_SC7_PA1_DATA_FIFO_EOP_RD = 0x00000375,
18371PH_SC7_PA1_EOPG_WE = 0x00000376,
18372PH_SC7_PA1_DEALLOC_4_0_RD = 0x00000377,
18373PH_SC7_PA2_DATA_FIFO_RD = 0x00000378,
18374PH_SC7_PA2_DATA_FIFO_WE = 0x00000379,
18375PH_SC7_PA2_FIFO_EMPTY = 0x0000037a,
18376PH_SC7_PA2_FIFO_FULL = 0x0000037b,
18377PH_SC7_PA2_NULL_WE = 0x0000037c,
18378PH_SC7_PA2_EVENT_WE = 0x0000037d,
18379PH_SC7_PA2_FPOV_WE = 0x0000037e,
18380PH_SC7_PA2_LPOV_WE = 0x0000037f,
18381PH_SC7_PA2_EOP_WE = 0x00000380,
18382PH_SC7_PA2_DATA_FIFO_EOP_RD = 0x00000381,
18383PH_SC7_PA2_EOPG_WE = 0x00000382,
18384PH_SC7_PA2_DEALLOC_4_0_RD = 0x00000383,
18385PH_SC7_PA3_DATA_FIFO_RD = 0x00000384,
18386PH_SC7_PA3_DATA_FIFO_WE = 0x00000385,
18387PH_SC7_PA3_FIFO_EMPTY = 0x00000386,
18388PH_SC7_PA3_FIFO_FULL = 0x00000387,
18389PH_SC7_PA3_NULL_WE = 0x00000388,
18390PH_SC7_PA3_EVENT_WE = 0x00000389,
18391PH_SC7_PA3_FPOV_WE = 0x0000038a,
18392PH_SC7_PA3_LPOV_WE = 0x0000038b,
18393PH_SC7_PA3_EOP_WE = 0x0000038c,
18394PH_SC7_PA3_DATA_FIFO_EOP_RD = 0x0000038d,
18395PH_SC7_PA3_EOPG_WE = 0x0000038e,
18396PH_SC7_PA3_DEALLOC_4_0_RD = 0x0000038f,
18397PH_SC7_PA4_DATA_FIFO_RD = 0x00000390,
18398PH_SC7_PA4_DATA_FIFO_WE = 0x00000391,
18399PH_SC7_PA4_FIFO_EMPTY = 0x00000392,
18400PH_SC7_PA4_FIFO_FULL = 0x00000393,
18401PH_SC7_PA4_NULL_WE = 0x00000394,
18402PH_SC7_PA4_EVENT_WE = 0x00000395,
18403PH_SC7_PA4_FPOV_WE = 0x00000396,
18404PH_SC7_PA4_LPOV_WE = 0x00000397,
18405PH_SC7_PA4_EOP_WE = 0x00000398,
18406PH_SC7_PA4_DATA_FIFO_EOP_RD = 0x00000399,
18407PH_SC7_PA4_EOPG_WE = 0x0000039a,
18408PH_SC7_PA4_DEALLOC_4_0_RD = 0x0000039b,
18409PH_SC7_PA5_DATA_FIFO_RD = 0x0000039c,
18410PH_SC7_PA5_DATA_FIFO_WE = 0x0000039d,
18411PH_SC7_PA5_FIFO_EMPTY = 0x0000039e,
18412PH_SC7_PA5_FIFO_FULL = 0x0000039f,
18413PH_SC7_PA5_NULL_WE = 0x000003a0,
18414PH_SC7_PA5_EVENT_WE = 0x000003a1,
18415PH_SC7_PA5_FPOV_WE = 0x000003a2,
18416PH_SC7_PA5_LPOV_WE = 0x000003a3,
18417PH_SC7_PA5_EOP_WE = 0x000003a4,
18418PH_SC7_PA5_DATA_FIFO_EOP_RD = 0x000003a5,
18419PH_SC7_PA5_EOPG_WE = 0x000003a6,
18420PH_SC7_PA5_DEALLOC_4_0_RD = 0x000003a7,
18421PH_SC7_PA6_DATA_FIFO_RD = 0x000003a8,
18422PH_SC7_PA6_DATA_FIFO_WE = 0x000003a9,
18423PH_SC7_PA6_FIFO_EMPTY = 0x000003aa,
18424PH_SC7_PA6_FIFO_FULL = 0x000003ab,
18425PH_SC7_PA6_NULL_WE = 0x000003ac,
18426PH_SC7_PA6_EVENT_WE = 0x000003ad,
18427PH_SC7_PA6_FPOV_WE = 0x000003ae,
18428PH_SC7_PA6_LPOV_WE = 0x000003af,
18429PH_SC7_PA6_EOP_WE = 0x000003b0,
18430PH_SC7_PA6_DATA_FIFO_EOP_RD = 0x000003b1,
18431PH_SC7_PA6_EOPG_WE = 0x000003b2,
18432PH_SC7_PA6_DEALLOC_4_0_RD = 0x000003b3,
18433PH_SC7_PA7_DATA_FIFO_RD = 0x000003b4,
18434PH_SC7_PA7_DATA_FIFO_WE = 0x000003b5,
18435PH_SC7_PA7_FIFO_EMPTY = 0x000003b6,
18436PH_SC7_PA7_FIFO_FULL = 0x000003b7,
18437PH_SC7_PA7_NULL_WE = 0x000003b8,
18438PH_SC7_PA7_EVENT_WE = 0x000003b9,
18439PH_SC7_PA7_FPOV_WE = 0x000003ba,
18440PH_SC7_PA7_LPOV_WE = 0x000003bb,
18441PH_SC7_PA7_EOP_WE = 0x000003bc,
18442PH_SC7_PA7_DATA_FIFO_EOP_RD = 0x000003bd,
18443PH_SC7_PA7_EOPG_WE = 0x000003be,
18444PH_SC7_PA7_DEALLOC_4_0_RD = 0x000003bf,
18445} PH_PERFCNT_SEL;
18446
18447/*
18448 * SU_PERFCNT_SEL enum
18449 */
18450
18451typedef enum SU_PERFCNT_SEL {
18452PERF_PAPC_PASX_REQ = 0x00000000,
18453PERF_PAPC_PASX_DISABLE_PIPE = 0x00000001,
18454PERF_PAPC_PASX_FIRST_VECTOR = 0x00000002,
18455PERF_PAPC_PASX_SECOND_VECTOR = 0x00000003,
18456PERF_PAPC_PASX_FIRST_DEAD = 0x00000004,
18457PERF_PAPC_PASX_SECOND_DEAD = 0x00000005,
18458PERF_PAPC_PASX_VTX_KILL_DISCARD = 0x00000006,
18459PERF_PAPC_PASX_VTX_NAN_DISCARD = 0x00000007,
18460PERF_PAPC_PA_INPUT_PRIM = 0x00000008,
18461PERF_PAPC_PA_INPUT_NULL_PRIM = 0x00000009,
18462PERF_PAPC_PA_INPUT_EVENT_FLAG = 0x0000000a,
18463PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 0x0000000b,
18464PERF_PAPC_PA_INPUT_END_OF_PACKET = 0x0000000c,
18465PERF_PAPC_PA_INPUT_EXTENDED_EVENT = 0x0000000d,
18466PERF_PAPC_CLPR_CULL_PRIM = 0x0000000e,
18467PERF_PAPC_CLPR_VVUCP_CULL_PRIM = 0x0000000f,
18468PERF_PAPC_CLPR_VV_CULL_PRIM = 0x00000010,
18469PERF_PAPC_CLPR_UCP_CULL_PRIM = 0x00000011,
18470PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 0x00000012,
18471PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 0x00000013,
18472PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 0x00000014,
18473PERF_PAPC_CLPR_VVUCP_CLIP_PRIM = 0x00000015,
18474PERF_PAPC_CLPR_VV_CLIP_PRIM = 0x00000016,
18475PERF_PAPC_CLPR_UCP_CLIP_PRIM = 0x00000017,
18476PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 0x00000018,
18477PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 0x00000019,
18478PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 0x0000001a,
18479PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 0x0000001b,
18480PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 0x0000001c,
18481PERF_PAPC_CLPR_CLIP_PLANE_CNT_5_8 = 0x0000001d,
18482PERF_PAPC_CLPR_CLIP_PLANE_CNT_9_12 = 0x0000001e,
18483PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 0x0000001f,
18484PERF_PAPC_CLPR_CLIP_PLANE_FAR = 0x00000020,
18485PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 0x00000021,
18486PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 0x00000022,
18487PERF_PAPC_CLPR_CLIP_PLANE_TOP = 0x00000023,
18488PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 0x00000024,
18489PERF_PAPC_CLPR_GSC_KILL_CULL_PRIM = 0x00000025,
18490PERF_PAPC_CLPR_RASTER_KILL_CULL_PRIM = 0x00000026,
18491PERF_PAPC_CLSM_NULL_PRIM = 0x00000027,
18492PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 0x00000028,
18493PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 0x00000029,
18494PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 0x0000002a,
18495PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 0x0000002b,
18496PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 0x0000002c,
18497PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 0x0000002d,
18498PERF_PAPC_CLSM_OUT_PRIM_CNT_5_8 = 0x0000002e,
18499PERF_PAPC_CLSM_OUT_PRIM_CNT_9_13 = 0x0000002f,
18500PERF_PAPC_CLIPGA_VTE_KILL_PRIM = 0x00000030,
18501PERF_PAPC_SU_INPUT_PRIM = 0x00000031,
18502PERF_PAPC_SU_INPUT_CLIP_PRIM = 0x00000032,
18503PERF_PAPC_SU_INPUT_NULL_PRIM = 0x00000033,
18504PERF_PAPC_SU_INPUT_PRIM_DUAL = 0x00000034,
18505PERF_PAPC_SU_INPUT_CLIP_PRIM_DUAL = 0x00000035,
18506PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 0x00000036,
18507PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 0x00000037,
18508PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 0x00000038,
18509PERF_PAPC_SU_POLYMODE_FACE_CULL = 0x00000039,
18510PERF_PAPC_SU_POLYMODE_BACK_CULL = 0x0000003a,
18511PERF_PAPC_SU_POLYMODE_FRONT_CULL = 0x0000003b,
18512PERF_PAPC_SU_POLYMODE_INVALID_FILL = 0x0000003c,
18513PERF_PAPC_SU_OUTPUT_PRIM = 0x0000003d,
18514PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 0x0000003e,
18515PERF_PAPC_SU_OUTPUT_NULL_PRIM = 0x0000003f,
18516PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 0x00000040,
18517PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 0x00000041,
18518PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 0x00000042,
18519PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 0x00000043,
18520PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 0x00000044,
18521PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 0x00000045,
18522PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 0x00000046,
18523PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 0x00000047,
18524PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 0x00000048,
18525PERF_PAPC_SU_OUTPUT_PRIM_DUAL = 0x00000049,
18526PERF_PAPC_SU_OUTPUT_CLIP_PRIM_DUAL = 0x0000004a,
18527PERF_PAPC_SU_OUTPUT_POLYMODE_DUAL = 0x0000004b,
18528PERF_PAPC_SU_OUTPUT_CLIP_POLYMODE_DUAL = 0x0000004c,
18529PERF_PAPC_PASX_REQ_IDLE = 0x0000004d,
18530PERF_PAPC_PASX_REQ_BUSY = 0x0000004e,
18531PERF_PAPC_PASX_REQ_STALLED = 0x0000004f,
18532PERF_PAPC_PASX_REC_IDLE = 0x00000050,
18533PERF_PAPC_PASX_REC_BUSY = 0x00000051,
18534PERF_PAPC_PASX_REC_STARVED_SX = 0x00000052,
18535PERF_PAPC_PASX_REC_STALLED = 0x00000053,
18536PERF_PAPC_PASX_REC_STALLED_POS_MEM = 0x00000054,
18537PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 0x00000055,
18538PERF_PAPC_CCGSM_IDLE = 0x00000056,
18539PERF_PAPC_CCGSM_BUSY = 0x00000057,
18540PERF_PAPC_CCGSM_STALLED = 0x00000058,
18541PERF_PAPC_CLPRIM_IDLE = 0x00000059,
18542PERF_PAPC_CLPRIM_BUSY = 0x0000005a,
18543PERF_PAPC_CLPRIM_STALLED = 0x0000005b,
18544PERF_PAPC_CLPRIM_STARVED_CCGSM = 0x0000005c,
18545PERF_PAPC_CLIPSM_IDLE = 0x0000005d,
18546PERF_PAPC_CLIPSM_BUSY = 0x0000005e,
18547PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 0x0000005f,
18548PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 0x00000060,
18549PERF_PAPC_CLIPSM_WAIT_CLIPGA = 0x00000061,
18550PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 0x00000062,
18551PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 0x00000063,
18552PERF_PAPC_CLIPGA_IDLE = 0x00000064,
18553PERF_PAPC_CLIPGA_BUSY = 0x00000065,
18554PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 0x00000066,
18555PERF_PAPC_CLIPGA_STALLED = 0x00000067,
18556PERF_PAPC_CLIP_IDLE = 0x00000068,
18557PERF_PAPC_CLIP_BUSY = 0x00000069,
18558PERF_PAPC_SU_IDLE = 0x0000006a,
18559PERF_PAPC_SU_BUSY = 0x0000006b,
18560PERF_PAPC_SU_STARVED_CLIP = 0x0000006c,
18561PERF_PAPC_SU_STALLED_SC = 0x0000006d,
18562PERF_PAPC_CL_DYN_SCLK_VLD = 0x0000006e,
18563PERF_PAPC_SU_DYN_SCLK_VLD = 0x0000006f,
18564PERF_PAPC_PA_REG_SCLK_VLD = 0x00000070,
18565PERF_PAPC_SU_MULTI_GPU_PRIM_FILTER_CULL = 0x00000071,
18566PERF_PAPC_PASX_SE0_REQ = 0x00000072,
18567PERF_PAPC_PASX_SE1_REQ = 0x00000073,
18568PERF_PAPC_PASX_SE0_FIRST_VECTOR = 0x00000074,
18569PERF_PAPC_PASX_SE0_SECOND_VECTOR = 0x00000075,
18570PERF_PAPC_PASX_SE1_FIRST_VECTOR = 0x00000076,
18571PERF_PAPC_PASX_SE1_SECOND_VECTOR = 0x00000077,
18572PERF_PAPC_SU_SE0_PRIM_FILTER_CULL = 0x00000078,
18573PERF_PAPC_SU_SE1_PRIM_FILTER_CULL = 0x00000079,
18574PERF_PAPC_SU_SE01_PRIM_FILTER_CULL = 0x0000007a,
18575PERF_PAPC_SU_SE0_OUTPUT_PRIM = 0x0000007b,
18576PERF_PAPC_SU_SE1_OUTPUT_PRIM = 0x0000007c,
18577PERF_PAPC_SU_SE01_OUTPUT_PRIM = 0x0000007d,
18578PERF_PAPC_SU_SE0_OUTPUT_NULL_PRIM = 0x0000007e,
18579PERF_PAPC_SU_SE1_OUTPUT_NULL_PRIM = 0x0000007f,
18580PERF_PAPC_SU_SE01_OUTPUT_NULL_PRIM = 0x00000080,
18581PERF_PAPC_SU_SE0_OUTPUT_FIRST_PRIM_SLOT = 0x00000081,
18582PERF_PAPC_SU_SE1_OUTPUT_FIRST_PRIM_SLOT = 0x00000082,
18583PERF_PAPC_SU_SE0_STALLED_SC = 0x00000083,
18584PERF_PAPC_SU_SE1_STALLED_SC = 0x00000084,
18585PERF_PAPC_SU_SE01_STALLED_SC = 0x00000085,
18586PERF_PAPC_CLSM_CLIPPING_PRIM = 0x00000086,
18587PERF_PAPC_SU_CULLED_PRIM = 0x00000087,
18588PERF_PAPC_SU_OUTPUT_EOPG = 0x00000088,
18589PERF_PAPC_SU_SE2_PRIM_FILTER_CULL = 0x00000089,
18590PERF_PAPC_SU_SE3_PRIM_FILTER_CULL = 0x0000008a,
18591PERF_PAPC_SU_SE2_OUTPUT_PRIM = 0x0000008b,
18592PERF_PAPC_SU_SE3_OUTPUT_PRIM = 0x0000008c,
18593PERF_PAPC_SU_SE2_OUTPUT_NULL_PRIM = 0x0000008d,
18594PERF_PAPC_SU_SE3_OUTPUT_NULL_PRIM = 0x0000008e,
18595PERF_PAPC_SU_SE0_OUTPUT_END_OF_PACKET = 0x0000008f,
18596PERF_PAPC_SU_SE1_OUTPUT_END_OF_PACKET = 0x00000090,
18597PERF_PAPC_SU_SE2_OUTPUT_END_OF_PACKET = 0x00000091,
18598PERF_PAPC_SU_SE3_OUTPUT_END_OF_PACKET = 0x00000092,
18599PERF_PAPC_SU_SE0_OUTPUT_EOPG = 0x00000093,
18600PERF_PAPC_SU_SE1_OUTPUT_EOPG = 0x00000094,
18601PERF_PAPC_SU_SE2_OUTPUT_EOPG = 0x00000095,
18602PERF_PAPC_SU_SE3_OUTPUT_EOPG = 0x00000096,
18603PERF_PAPC_SU_SE2_STALLED_SC = 0x00000097,
18604PERF_PAPC_SU_SE3_STALLED_SC = 0x00000098,
18605PERF_SU_SMALL_PRIM_FILTER_CULL_CNT = 0x00000099,
18606PERF_SMALL_PRIM_CULL_PRIM_1X1 = 0x0000009a,
18607PERF_SMALL_PRIM_CULL_PRIM_2X1 = 0x0000009b,
18608PERF_SMALL_PRIM_CULL_PRIM_1X2 = 0x0000009c,
18609PERF_SMALL_PRIM_CULL_PRIM_2X2 = 0x0000009d,
18610PERF_SMALL_PRIM_CULL_PRIM_3X1 = 0x0000009e,
18611PERF_SMALL_PRIM_CULL_PRIM_1X3 = 0x0000009f,
18612PERF_SMALL_PRIM_CULL_PRIM_3X2 = 0x000000a0,
18613PERF_SMALL_PRIM_CULL_PRIM_2X3 = 0x000000a1,
18614PERF_SMALL_PRIM_CULL_PRIM_NX1 = 0x000000a2,
18615PERF_SMALL_PRIM_CULL_PRIM_1XN = 0x000000a3,
18616PERF_SMALL_PRIM_CULL_PRIM_NX2 = 0x000000a4,
18617PERF_SMALL_PRIM_CULL_PRIM_2XN = 0x000000a5,
18618PERF_SMALL_PRIM_CULL_PRIM_FULL_RES_EVENT = 0x000000a6,
18619PERF_SMALL_PRIM_CULL_PRIM_HALF_RES_EVENT = 0x000000a7,
18620PERF_SMALL_PRIM_CULL_PRIM_QUARTER_RES_EVENT = 0x000000a8,
18621PERF_SC0_QUALIFIED_SEND_BUSY_EVENT = 0x000000a9,
18622PERF_SC0_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000aa,
18623PERF_SC1_QUALIFIED_SEND_BUSY_EVENT = 0x000000ab,
18624PERF_SC1_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ac,
18625PERF_SC2_QUALIFIED_SEND_BUSY_EVENT = 0x000000ad,
18626PERF_SC2_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000ae,
18627PERF_SC3_QUALIFIED_SEND_BUSY_EVENT = 0x000000af,
18628PERF_SC3_QUALIFIED_SEND_NOT_BUSY_EVENT = 0x000000b0,
18629PERF_UTC_SIDEBAND_DRIVER_WAITING_ON_UTCL1 = 0x000000b1,
18630PERF_UTC_SIDEBAND_DRIVER_STALLING_CLIENT = 0x000000b2,
18631PERF_UTC_SIDEBAND_DRIVER_BUSY = 0x000000b3,
18632PERF_UTC_INDEX_DRIVER_WAITING_ON_UTCL1 = 0x000000b4,
18633PERF_UTC_INDEX_DRIVER_STALLING_CLIENT = 0x000000b5,
18634PERF_UTC_INDEX_DRIVER_BUSY = 0x000000b6,
18635PERF_UTC_POSITION_DRIVER_WAITING_ON_UTCL1 = 0x000000b7,
18636PERF_UTC_POSITION_DRIVER_STALLING_CLIENT = 0x000000b8,
18637PERF_UTC_POSITION_DRIVER_BUSY = 0x000000b9,
18638PERF_UTC_SIDEBAND_RECEIVER_STALLING_UTCL1 = 0x000000ba,
18639PERF_UTC_SIDEBAND_RECEIVER_STALLED_BY_ARBITER = 0x000000bb,
18640PERF_UTC_SIDEBAND_RECEIVER_BUSY = 0x000000bc,
18641PERF_UTC_INDEX_RECEIVER_STALLING_UTCL1 = 0x000000bd,
18642PERF_UTC_INDEX_RECEIVER_STALLED_BY_ARBITER = 0x000000be,
18643PERF_UTC_INDEX_RECEIVER_BUSY = 0x000000bf,
18644PERF_UTC_POSITION_RECEIVER_STALLING_UTCL1 = 0x000000c0,
18645PERF_UTC_POSITION_RECEIVER_STALLED_BY_ARBITER = 0x000000c1,
18646PERF_UTC_POSITION_RECEIVER_BUSY = 0x000000c2,
18647PERF_TC_ARBITER_WAITING_FOR_TC_INTERFACE = 0x000000c3,
18648PERF_TCIF_STALLING_CLIENT_NO_CREDITS = 0x000000c4,
18649PERF_TCIF_BUSY = 0x000000c5,
18650PERF_TCIF_SIDEBAND_RDREQ = 0x000000c6,
18651PERF_TCIF_INDEX_RDREQ = 0x000000c7,
18652PERF_TCIF_POSITION_RDREQ = 0x000000c8,
18653PERF_SIDEBAND_WAITING_ON_UTCL1 = 0x000000c9,
18654PERF_SIDEBAND_WAITING_ON_FULL_SIDEBAND_MEMORY = 0x000000ca,
18655PERF_WRITING_TO_SIDEBAND_MEMORY = 0x000000cb,
18656PERF_SIDEBAND_EXPECTING_1_POSSIBLE_VALID_DWORD = 0x000000cc,
18657PERF_SIDEBAND_EXPECTING_2_TO_15_POSSIBLE_VALID_DWORD = 0x000000cd,
18658PERF_SIDEBAND_EXPECTING_16_POSSIBLE_VALID_DWORD = 0x000000ce,
18659PERF_SIDEBAND_WAITING_ON_RETURNED_DATA = 0x000000cf,
18660PERF_SIDEBAND_POP_BIT_FIFO_FULL = 0x000000d0,
18661PERF_SIDEBAND_FIFO_VMID_FIFO_FULL = 0x000000d1,
18662PERF_SIDEBAND_INVALID_REFETCH = 0x000000d2,
18663PERF_SIDEBAND_QUALIFIED_BUSY = 0x000000d3,
18664PERF_SIDEBAND_QUALIFIED_STARVED = 0x000000d4,
18665PERF_SIDEBAND_0_VALID_DWORDS_RECEIVED_ = 0x000000d5,
18666PERF_SIDEBAND_1_TO_7_VALID_DWORDS_RECEIVED_ = 0x000000d6,
18667PERF_SIDEBAND_8_TO_15_VALID_DWORDS_RECEIVED_ = 0x000000d7,
18668PERF_SIDEBAND_16_VALID_DWORDS_RECEIVED_ = 0x000000d8,
18669PERF_INDEX_REQUEST_WAITING_ON_TOKENS = 0x000000d9,
18670PERF_INDEX_REQUEST_WAITING_ON_FULL_RECEIVE_FIFO = 0x000000da,
18671PERF_INDEX_REQUEST_QUALIFIED_BUSY = 0x000000db,
18672PERF_INDEX_REQUEST_QUALIFIED_STARVED = 0x000000dc,
18673PERF_INDEX_RECEIVE_WAITING_ON_RETURNED_CACHELINE = 0x000000dd,
18674PERF_INDEX_RECEIVE_WAITING_ON_PRIM_INDICES_FIFO = 0x000000de,
18675PERF_INDEX_RECEIVE_PRIM_INDICES_FIFO_WRITE = 0x000000df,
18676PERF_INDEX_RECEIVE_QUALIFIED_BUSY = 0x000000e0,
18677PERF_INDEX_RECEIVE_QUALIFIED_STARVED = 0x000000e1,
18678PERF_INDEX_RECEIVE_0_VALID_DWORDS_THIS_CACHELINE = 0x000000e2,
18679PERF_INDEX_RECEIVE_1_VALID_DWORDS_THIS_CACHELINE = 0x000000e3,
18680PERF_INDEX_RECEIVE_2_VALID_DWORDS_THIS_CACHELINE = 0x000000e4,
18681PERF_INDEX_RECEIVE_3_VALID_DWORDS_THIS_CACHELINE = 0x000000e5,
18682PERF_INDEX_RECEIVE_4_VALID_DWORDS_THIS_CACHELINE = 0x000000e6,
18683PERF_INDEX_RECEIVE_5_VALID_DWORDS_THIS_CACHELINE = 0x000000e7,
18684PERF_INDEX_RECEIVE_6_VALID_DWORDS_THIS_CACHELINE = 0x000000e8,
18685PERF_INDEX_RECEIVE_7_VALID_DWORDS_THIS_CACHELINE = 0x000000e9,
18686PERF_INDEX_RECEIVE_8_VALID_DWORDS_THIS_CACHELINE = 0x000000ea,
18687PERF_INDEX_RECEIVE_9_VALID_DWORDS_THIS_CACHELINE = 0x000000eb,
18688PERF_INDEX_RECEIVE_10_VALID_DWORDS_THIS_CACHELINE = 0x000000ec,
18689PERF_INDEX_RECEIVE_11_VALID_DWORDS_THIS_CACHELINE = 0x000000ed,
18690PERF_INDEX_RECEIVE_12_VALID_DWORDS_THIS_CACHELINE = 0x000000ee,
18691PERF_INDEX_RECEIVE_13_VALID_DWORDS_THIS_CACHELINE = 0x000000ef,
18692PERF_INDEX_RECEIVE_14_VALID_DWORDS_THIS_CACHELINE = 0x000000f0,
18693PERF_INDEX_RECEIVE_15_VALID_DWORDS_THIS_CACHELINE = 0x000000f1,
18694PERF_INDEX_RECEIVE_16_VALID_DWORDS_THIS_CACHELINE = 0x000000f2,
18695PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x000000f3,
18696PERF_POS_REQ_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x000000f4,
18697PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_V_FIFO = 0x000000f5,
18698PERF_POS_REQ_STALLED_BY_FULL_POSREQ_TO_POSRTN_S_FIFO = 0x000000f6,
18699PERF_POS_REQ_STALLED_BY_FULL_PA_TO_WD_DEALLOC_INDEX_FIFO = 0x000000f7,
18700PERF_POS_REQ_STALLED_BY_NO_TOKENS = 0x000000f8,
18701PERF_POS_REQ_STARVED_BY_NO_PRIM = 0x000000f9,
18702PERF_POS_REQ_STALLED_BY_UTCL1 = 0x000000fa,
18703PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x000000fb,
18704PERF_POS_REQ_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x000000fc,
18705PERF_POS_REQ_QUALIFIED_BUSY = 0x000000fd,
18706PERF_POS_REQ_QUALIFIED_STARVED = 0x000000fe,
18707PERF_POS_REQ_REUSE_0_NEW_VERTS_THIS_PRIM = 0x000000ff,
18708PERF_POS_REQ_REUSE_1_NEW_VERTS_THIS_PRIM = 0x00000100,
18709PERF_POS_REQ_REUSE_2_NEW_VERTS_THIS_PRIM = 0x00000101,
18710PERF_POS_REQ_REUSE_3_NEW_VERTS_THIS_PRIM = 0x00000102,
18711PERF_POS_RET_FULL_FETCH_TO_SXIF_FIFO = 0x00000103,
18712PERF_POS_RET_FULL_PA_TO_WD_DEALLOC_POSITION_FIFO = 0x00000104,
18713PERF_POS_RET_WAITING_ON_RETURNED_CACHELINE = 0x00000105,
18714PERF_POS_RET_FETCH_TO_SXIF_FIFO_WRITE = 0x00000106,
18715PERF_POS_RET_QUALIFIED_BUSY = 0x00000107,
18716PERF_POS_RET_QUALIFIED_STARVED = 0x00000108,
18717PERF_POS_RET_1_CACHELINE_POSITION_USED = 0x00000109,
18718PERF_POS_RET_2_CACHELINE_POSITION_USED = 0x0000010a,
18719PERF_POS_RET_3_CACHELINE_POSITION_USED = 0x0000010b,
18720PERF_POS_RET_4_CACHELINE_POSITION_USED = 0x0000010c,
18721PERF_TC_INDEX_LATENCY_BIN0 = 0x0000010d,
18722PERF_TC_INDEX_LATENCY_BIN1 = 0x0000010e,
18723PERF_TC_INDEX_LATENCY_BIN2 = 0x0000010f,
18724PERF_TC_INDEX_LATENCY_BIN3 = 0x00000110,
18725PERF_TC_INDEX_LATENCY_BIN4 = 0x00000111,
18726PERF_TC_INDEX_LATENCY_BIN5 = 0x00000112,
18727PERF_TC_INDEX_LATENCY_BIN6 = 0x00000113,
18728PERF_TC_INDEX_LATENCY_BIN7 = 0x00000114,
18729PERF_TC_INDEX_LATENCY_BIN8 = 0x00000115,
18730PERF_TC_INDEX_LATENCY_BIN9 = 0x00000116,
18731PERF_TC_INDEX_LATENCY_BIN10 = 0x00000117,
18732PERF_TC_INDEX_LATENCY_BIN11 = 0x00000118,
18733PERF_TC_INDEX_LATENCY_BIN12 = 0x00000119,
18734PERF_TC_INDEX_LATENCY_BIN13 = 0x0000011a,
18735PERF_TC_INDEX_LATENCY_BIN14 = 0x0000011b,
18736PERF_TC_INDEX_LATENCY_BIN15 = 0x0000011c,
18737PERF_TC_POSITION_LATENCY_BIN0 = 0x0000011d,
18738PERF_TC_POSITION_LATENCY_BIN1 = 0x0000011e,
18739PERF_TC_POSITION_LATENCY_BIN2 = 0x0000011f,
18740PERF_TC_POSITION_LATENCY_BIN3 = 0x00000120,
18741PERF_TC_POSITION_LATENCY_BIN4 = 0x00000121,
18742PERF_TC_POSITION_LATENCY_BIN5 = 0x00000122,
18743PERF_TC_POSITION_LATENCY_BIN6 = 0x00000123,
18744PERF_TC_POSITION_LATENCY_BIN7 = 0x00000124,
18745PERF_TC_POSITION_LATENCY_BIN8 = 0x00000125,
18746PERF_TC_POSITION_LATENCY_BIN9 = 0x00000126,
18747PERF_TC_POSITION_LATENCY_BIN10 = 0x00000127,
18748PERF_TC_POSITION_LATENCY_BIN11 = 0x00000128,
18749PERF_TC_POSITION_LATENCY_BIN12 = 0x00000129,
18750PERF_TC_POSITION_LATENCY_BIN13 = 0x0000012a,
18751PERF_TC_POSITION_LATENCY_BIN14 = 0x0000012b,
18752PERF_TC_POSITION_LATENCY_BIN15 = 0x0000012c,
18753PERF_TC_STREAM0_DATA_AVAILABLE = 0x0000012d,
18754PERF_TC_STREAM1_DATA_AVAILABLE = 0x0000012e,
18755PERF_TC_STREAM2_DATA_AVAILABLE = 0x0000012f,
18756PERF_PAWD_DEALLOC_FIFO_IS_FULL = 0x00000130,
18757PERF_PAWD_DEALLOC_WAITING_TO_BE_READ = 0x00000131,
18758PERF_SHOOTDOWN_WAIT_ON_UTCL1 = 0x00000132,
18759PERF_SHOOTDOWN_WAIT_ON_UTC_SIDEBAND = 0x00000133,
18760PERF_SHOOTDOWN_WAIT_ON_UTC_INDEX = 0x00000134,
18761PERF_SHOOTDOWN_WAIT_ON_UTC_POSITION = 0x00000135,
18762PERF_SHOOTDOWN_WAIT_ALL_CLEAN = 0x00000136,
18763PERF_SHOOTDOWN_WAIT_DEASSERT = 0x00000137,
18764PERF_UTCL1_TRANSLATION_MISS_CLIENT0 = 0x00000138,
18765PERF_UTCL1_TRANSLATION_MISS_CLIENT1 = 0x00000139,
18766PERF_UTCL1_TRANSLATION_MISS_CLIENT2 = 0x0000013a,
18767PERF_UTCL1_PERMISSION_MISS_CLIENT0 = 0x0000013b,
18768PERF_UTCL1_PERMISSION_MISS_CLIENT1 = 0x0000013c,
18769PERF_UTCL1_PERMISSION_MISS_CLIENT2 = 0x0000013d,
18770PERF_UTCL1_TRANSLATION_HIT_CLIENT0 = 0x0000013e,
18771PERF_UTCL1_TRANSLATION_HIT_CLIENT1 = 0x0000013f,
18772PERF_UTCL1_TRANSLATION_HIT_CLIENT2 = 0x00000140,
18773PERF_UTCL1_REQUEST_CLIENT0 = 0x00000141,
18774PERF_UTCL1_REQUEST_CLIENT1 = 0x00000142,
18775PERF_UTCL1_REQUEST_CLIENT2 = 0x00000143,
18776PERF_UTCL1_STALL_MISSFIFO_FULL = 0x00000144,
18777PERF_UTCL1_STALL_INFLIGHT_MAX = 0x00000145,
18778PERF_UTCL1_STALL_LRU_INFLIGHT = 0x00000146,
18779PERF_UTCL1_STALL_MULTI_MISS = 0x00000147,
18780PERF_UTCL1_LFIFO_FULL = 0x00000148,
18781PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT0 = 0x00000149,
18782PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT1 = 0x0000014a,
18783PERF_UTCL1_STALL_LFIFO_NOT_RES_CLIENT2 = 0x0000014b,
18784PERF_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x0000014c,
18785PERF_UTCL1_UTCL2_REQ = 0x0000014d,
18786PERF_UTCL1_UTCL2_RET = 0x0000014e,
18787PERF_UTCL1_UTCL2_INFLIGHT = 0x0000014f,
18788PERF_CLIENT_UTCL1_INFLIGHT = 0x00000150,
18789PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x00000151,
18790PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x00000152,
18791PERF_PA_SE0_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x00000153,
18792PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x00000154,
18793PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x00000155,
18794PERF_PA_SE1_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x00000156,
18795PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x00000157,
18796PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x00000158,
18797PERF_PA_SE2_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x00000159,
18798PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_NOT_ASSERTED = 0x0000015a,
18799PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_NO_SEND = 0x0000015b,
18800PERF_PA_SE3_OUTPUT_QUALIFIED_CLKEN_ASSERTED_WITH_SEND = 0x0000015c,
18801PERF_PA_VERTEX_FIFO_FULL = 0x0000015d,
18802PERF_PA_PRIMIC_TO_CLPRIM_FIFO_FULL = 0x0000015e,
18803PERF_PA_FETCH_TO_PRIMIC_P_FIFO_FULL = 0x0000015f,
18804PERF_PA_FETCH_TO_SXIF_FIFO_FULL = 0x00000160,
18805ENGG_CSB_MACHINE_IS_STARVED = 0x00000163,
18806ENGG_CSB_MACHINE_STALLED_BY_CSB_MEMORY = 0x00000164,
18807ENGG_CSB_MACHINE_STALLED_BY_SPI = 0x00000165,
18808ENGG_CSB_GE_INPUT_FIFO_FULL = 0x00000166,
18809ENGG_CSB_SPI_INPUT_FIFO_FULL = 0x00000167,
18810ENGG_CSB_OBJECTID_INPUT_FIFO_FULL = 0x00000168,
18811ENGG_CSB_PRIM_COUNT_EQ0 = 0x00000169,
18812ENGG_CSB_GE_SENDING_SUBGROUP = 0x0000016a,
18813ENGG_CSB_DELAY_BIN00 = 0x0000016b,
18814ENGG_CSB_DELAY_BIN01 = 0x0000016c,
18815ENGG_CSB_DELAY_BIN02 = 0x0000016d,
18816ENGG_CSB_DELAY_BIN03 = 0x0000016e,
18817ENGG_CSB_DELAY_BIN04 = 0x0000016f,
18818ENGG_CSB_DELAY_BIN05 = 0x00000170,
18819ENGG_CSB_DELAY_BIN06 = 0x00000171,
18820ENGG_CSB_DELAY_BIN07 = 0x00000172,
18821ENGG_CSB_DELAY_BIN08 = 0x00000173,
18822ENGG_CSB_DELAY_BIN09 = 0x00000174,
18823ENGG_CSB_DELAY_BIN10 = 0x00000175,
18824ENGG_CSB_DELAY_BIN11 = 0x00000176,
18825ENGG_CSB_DELAY_BIN12 = 0x00000177,
18826ENGG_CSB_DELAY_BIN13 = 0x00000178,
18827ENGG_CSB_DELAY_BIN14 = 0x00000179,
18828ENGG_CSB_DELAY_BIN15 = 0x0000017a,
18829ENGG_CSB_SPI_DELAY_BIN00 = 0x0000017b,
18830ENGG_CSB_SPI_DELAY_BIN01 = 0x0000017c,
18831ENGG_CSB_SPI_DELAY_BIN02 = 0x0000017d,
18832ENGG_CSB_SPI_DELAY_BIN03 = 0x0000017e,
18833ENGG_CSB_SPI_DELAY_BIN04 = 0x0000017f,
18834ENGG_CSB_SPI_DELAY_BIN05 = 0x00000180,
18835ENGG_CSB_SPI_DELAY_BIN06 = 0x00000181,
18836ENGG_CSB_SPI_DELAY_BIN07 = 0x00000182,
18837ENGG_CSB_SPI_DELAY_BIN08 = 0x00000183,
18838ENGG_CSB_SPI_DELAY_BIN09 = 0x00000184,
18839ENGG_CSB_SPI_DELAY_BIN10 = 0x00000185,
18840ENGG_CSB_SPI_DELAY_BIN11 = 0x00000186,
18841ENGG_CSB_SPI_DELAY_BIN12 = 0x00000187,
18842ENGG_CSB_SPI_DELAY_BIN13 = 0x00000188,
18843ENGG_CSB_SPI_DELAY_BIN14 = 0x00000189,
18844ENGG_CSB_SPI_DELAY_BIN15 = 0x0000018a,
18845ENGG_INDEX_REQ_STARVED = 0x0000018b,
18846ENGG_INDEX_REQ_IDLE_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x0000018c,
18847ENGG_INDEX_REQ_BUSY_AND_STALLED_BY_REQ2RTN_FIFO_FULL = 0x0000018d,
18848ENGG_INDEX_REQ_STALLED_BY_SX_CREDITS = 0x0000018e,
18849ENGG_INDEX_RET_REQ2RTN_FIFO_FULL = 0x0000018f,
18850ENGG_INDEX_RET_REQ2RTN_FIFO_EMPTY = 0x00000190,
18851ENGG_INDEX_RET_SX_RECEIVE_FIFO_FULL = 0x00000191,
18852ENGG_INDEX_RET_SXRX_STARVED_BY_CSB = 0x00000192,
18853ENGG_INDEX_RET_SXRX_STARVED_BY_PRIMS = 0x00000193,
18854ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_CSB_FIFO = 0x00000194,
18855ENGG_INDEX_RET_SXRX_STALLED_BY_PRIM_INDICES_FIFO = 0x00000195,
18856ENGG_INDEX_RET_SXRX_READING_EVENT = 0x00000196,
18857ENGG_INDEX_RET_SXRX_READING_NULL_SUBGROUP = 0x00000197,
18858ENGG_INDEX_RET_SXRX_READING_SUBGROUP_PRIMCOUNT_EQ0 = 0x00000198,
18859ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_NOPL = 0x00000199,
18860ENGG_INDEX_RET_SXRX_READING_QDWORD_0_VALID_PRIMS_PL = 0x0000019a,
18861ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_NOPL = 0x0000019b,
18862ENGG_INDEX_RET_SXRX_READING_QDWORD_1_VALID_PRIMS_PL = 0x0000019c,
18863ENGG_INDEX_RET_SXRX_READING_QDWORD_2_VALID_PRIMS = 0x0000019d,
18864ENGG_INDEX_RET_SXRX_READING_QDWORD_3_VALID_PRIMS = 0x0000019e,
18865ENGG_INDEX_RET_SXRX_READING_QDWORD_4_VALID_PRIMS = 0x0000019f,
18866ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_P_FIFO = 0x000001a0,
18867ENGG_INDEX_PRIM_IF_STALLED_BY_FULL_FETCH_TO_PRIMIC_S_FIFO = 0x000001a1,
18868ENGG_INDEX_PRIM_IF_STARVED_BY_NO_PRIM = 0x000001a2,
18869ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_WRITE = 0x000001a3,
18870ENGG_INDEX_PRIM_IF_FETCH_TO_PRIMIC_P_FIFO_NO_WRITE = 0x000001a4,
18871ENGG_INDEX_PRIM_IF_QUALIFIED_BUSY = 0x000001a5,
18872ENGG_INDEX_PRIM_IF_QUALIFIED_STARVED = 0x000001a6,
18873ENGG_INDEX_PRIM_IF_REUSE_0_NEW_VERTS_THIS_PRIM = 0x000001a7,
18874ENGG_INDEX_PRIM_IF_REUSE_1_NEW_VERTS_THIS_PRIM = 0x000001a8,
18875ENGG_INDEX_PRIM_IF_REUSE_2_NEW_VERTS_THIS_PRIM = 0x000001a9,
18876ENGG_INDEX_PRIM_IF_REUSE_3_NEW_VERTS_THIS_PRIM = 0x000001aa,
18877ENGG_POS_REQ_STARVED = 0x000001ab,
18878ENGG_POS_REQ_STALLED_BY_FULL_CLIPV_FIFO = 0x000001ac,
18879} SU_PERFCNT_SEL;
18880
18881/*
18882 * SC_PERFCNT_SEL enum
18883 */
18884
18885typedef enum SC_PERFCNT_SEL {
18886SC_SRPS_WINDOW_VALID = 0x00000000,
18887SC_PSSW_WINDOW_VALID = 0x00000001,
18888SC_TPQZ_WINDOW_VALID = 0x00000002,
18889SC_QZQP_WINDOW_VALID = 0x00000003,
18890SC_TRPK_WINDOW_VALID = 0x00000004,
18891SC_SRPS_WINDOW_VALID_BUSY = 0x00000005,
18892SC_PSSW_WINDOW_VALID_BUSY = 0x00000006,
18893SC_TPQZ_WINDOW_VALID_BUSY = 0x00000007,
18894SC_QZQP_WINDOW_VALID_BUSY = 0x00000008,
18895SC_TRPK_WINDOW_VALID_BUSY = 0x00000009,
18896SC_STARVED_BY_PA = 0x0000000a,
18897SC_STALLED_BY_PRIMFIFO = 0x0000000b,
18898SC_STALLED_BY_DB_TILE = 0x0000000c,
18899SC_STARVED_BY_DB_TILE = 0x0000000d,
18900SC_STALLED_BY_TILEORDERFIFO = 0x0000000e,
18901SC_STALLED_BY_TILEFIFO = 0x0000000f,
18902SC_STALLED_BY_DB_QUAD = 0x00000010,
18903SC_STARVED_BY_DB_QUAD = 0x00000011,
18904SC_STALLED_BY_QUADFIFO = 0x00000012,
18905SC_STALLED_BY_BCI = 0x00000013,
18906SC_STALLED_BY_SPI = 0x00000014,
18907SC_SCISSOR_DISCARD = 0x00000015,
18908SC_BB_DISCARD = 0x00000016,
18909SC_SUPERTILE_COUNT = 0x00000017,
18910SC_SUPERTILE_PER_PRIM_H0 = 0x00000018,
18911SC_SUPERTILE_PER_PRIM_H1 = 0x00000019,
18912SC_SUPERTILE_PER_PRIM_H2 = 0x0000001a,
18913SC_SUPERTILE_PER_PRIM_H3 = 0x0000001b,
18914SC_SUPERTILE_PER_PRIM_H4 = 0x0000001c,
18915SC_SUPERTILE_PER_PRIM_H5 = 0x0000001d,
18916SC_SUPERTILE_PER_PRIM_H6 = 0x0000001e,
18917SC_SUPERTILE_PER_PRIM_H7 = 0x0000001f,
18918SC_SUPERTILE_PER_PRIM_H8 = 0x00000020,
18919SC_SUPERTILE_PER_PRIM_H9 = 0x00000021,
18920SC_SUPERTILE_PER_PRIM_H10 = 0x00000022,
18921SC_SUPERTILE_PER_PRIM_H11 = 0x00000023,
18922SC_SUPERTILE_PER_PRIM_H12 = 0x00000024,
18923SC_SUPERTILE_PER_PRIM_H13 = 0x00000025,
18924SC_SUPERTILE_PER_PRIM_H14 = 0x00000026,
18925SC_SUPERTILE_PER_PRIM_H15 = 0x00000027,
18926SC_SUPERTILE_PER_PRIM_H16 = 0x00000028,
18927SC_TILE_PER_PRIM_H0 = 0x00000029,
18928SC_TILE_PER_PRIM_H1 = 0x0000002a,
18929SC_TILE_PER_PRIM_H2 = 0x0000002b,
18930SC_TILE_PER_PRIM_H3 = 0x0000002c,
18931SC_TILE_PER_PRIM_H4 = 0x0000002d,
18932SC_TILE_PER_PRIM_H5 = 0x0000002e,
18933SC_TILE_PER_PRIM_H6 = 0x0000002f,
18934SC_TILE_PER_PRIM_H7 = 0x00000030,
18935SC_TILE_PER_PRIM_H8 = 0x00000031,
18936SC_TILE_PER_PRIM_H9 = 0x00000032,
18937SC_TILE_PER_PRIM_H10 = 0x00000033,
18938SC_TILE_PER_PRIM_H11 = 0x00000034,
18939SC_TILE_PER_PRIM_H12 = 0x00000035,
18940SC_TILE_PER_PRIM_H13 = 0x00000036,
18941SC_TILE_PER_PRIM_H14 = 0x00000037,
18942SC_TILE_PER_PRIM_H15 = 0x00000038,
18943SC_TILE_PER_PRIM_H16 = 0x00000039,
18944SC_TILE_PER_SUPERTILE_H0 = 0x0000003a,
18945SC_TILE_PER_SUPERTILE_H1 = 0x0000003b,
18946SC_TILE_PER_SUPERTILE_H2 = 0x0000003c,
18947SC_TILE_PER_SUPERTILE_H3 = 0x0000003d,
18948SC_TILE_PER_SUPERTILE_H4 = 0x0000003e,
18949SC_TILE_PER_SUPERTILE_H5 = 0x0000003f,
18950SC_TILE_PER_SUPERTILE_H6 = 0x00000040,
18951SC_TILE_PER_SUPERTILE_H7 = 0x00000041,
18952SC_TILE_PER_SUPERTILE_H8 = 0x00000042,
18953SC_TILE_PER_SUPERTILE_H9 = 0x00000043,
18954SC_TILE_PER_SUPERTILE_H10 = 0x00000044,
18955SC_TILE_PER_SUPERTILE_H11 = 0x00000045,
18956SC_TILE_PER_SUPERTILE_H12 = 0x00000046,
18957SC_TILE_PER_SUPERTILE_H13 = 0x00000047,
18958SC_TILE_PER_SUPERTILE_H14 = 0x00000048,
18959SC_TILE_PER_SUPERTILE_H15 = 0x00000049,
18960SC_TILE_PER_SUPERTILE_H16 = 0x0000004a,
18961SC_TILE_PICKED_H1 = 0x0000004b,
18962SC_TILE_PICKED_H2 = 0x0000004c,
18963SC_TILE_PICKED_H3 = 0x0000004d,
18964SC_TILE_PICKED_H4 = 0x0000004e,
18965SC_QZ0_TILE_COUNT = 0x0000004f,
18966SC_QZ1_TILE_COUNT = 0x00000050,
18967SC_QZ2_TILE_COUNT = 0x00000051,
18968SC_QZ3_TILE_COUNT = 0x00000052,
18969SC_QZ0_TILE_COVERED_COUNT = 0x00000053,
18970SC_QZ1_TILE_COVERED_COUNT = 0x00000054,
18971SC_QZ2_TILE_COVERED_COUNT = 0x00000055,
18972SC_QZ3_TILE_COVERED_COUNT = 0x00000056,
18973SC_QZ0_TILE_NOT_COVERED_COUNT = 0x00000057,
18974SC_QZ1_TILE_NOT_COVERED_COUNT = 0x00000058,
18975SC_QZ2_TILE_NOT_COVERED_COUNT = 0x00000059,
18976SC_QZ3_TILE_NOT_COVERED_COUNT = 0x0000005a,
18977SC_QZ0_QUAD_PER_TILE_H0 = 0x0000005b,
18978SC_QZ0_QUAD_PER_TILE_H1 = 0x0000005c,
18979SC_QZ0_QUAD_PER_TILE_H2 = 0x0000005d,
18980SC_QZ0_QUAD_PER_TILE_H3 = 0x0000005e,
18981SC_QZ0_QUAD_PER_TILE_H4 = 0x0000005f,
18982SC_QZ0_QUAD_PER_TILE_H5 = 0x00000060,
18983SC_QZ0_QUAD_PER_TILE_H6 = 0x00000061,
18984SC_QZ0_QUAD_PER_TILE_H7 = 0x00000062,
18985SC_QZ0_QUAD_PER_TILE_H8 = 0x00000063,
18986SC_QZ0_QUAD_PER_TILE_H9 = 0x00000064,
18987SC_QZ0_QUAD_PER_TILE_H10 = 0x00000065,
18988SC_QZ0_QUAD_PER_TILE_H11 = 0x00000066,
18989SC_QZ0_QUAD_PER_TILE_H12 = 0x00000067,
18990SC_QZ0_QUAD_PER_TILE_H13 = 0x00000068,
18991SC_QZ0_QUAD_PER_TILE_H14 = 0x00000069,
18992SC_QZ0_QUAD_PER_TILE_H15 = 0x0000006a,
18993SC_QZ0_QUAD_PER_TILE_H16 = 0x0000006b,
18994SC_QZ1_QUAD_PER_TILE_H0 = 0x0000006c,
18995SC_QZ1_QUAD_PER_TILE_H1 = 0x0000006d,
18996SC_QZ1_QUAD_PER_TILE_H2 = 0x0000006e,
18997SC_QZ1_QUAD_PER_TILE_H3 = 0x0000006f,
18998SC_QZ1_QUAD_PER_TILE_H4 = 0x00000070,
18999SC_QZ1_QUAD_PER_TILE_H5 = 0x00000071,
19000SC_QZ1_QUAD_PER_TILE_H6 = 0x00000072,
19001SC_QZ1_QUAD_PER_TILE_H7 = 0x00000073,
19002SC_QZ1_QUAD_PER_TILE_H8 = 0x00000074,
19003SC_QZ1_QUAD_PER_TILE_H9 = 0x00000075,
19004SC_QZ1_QUAD_PER_TILE_H10 = 0x00000076,
19005SC_QZ1_QUAD_PER_TILE_H11 = 0x00000077,
19006SC_QZ1_QUAD_PER_TILE_H12 = 0x00000078,
19007SC_QZ1_QUAD_PER_TILE_H13 = 0x00000079,
19008SC_QZ1_QUAD_PER_TILE_H14 = 0x0000007a,
19009SC_QZ1_QUAD_PER_TILE_H15 = 0x0000007b,
19010SC_QZ1_QUAD_PER_TILE_H16 = 0x0000007c,
19011SC_QZ2_QUAD_PER_TILE_H0 = 0x0000007d,
19012SC_QZ2_QUAD_PER_TILE_H1 = 0x0000007e,
19013SC_QZ2_QUAD_PER_TILE_H2 = 0x0000007f,
19014SC_QZ2_QUAD_PER_TILE_H3 = 0x00000080,
19015SC_QZ2_QUAD_PER_TILE_H4 = 0x00000081,
19016SC_QZ2_QUAD_PER_TILE_H5 = 0x00000082,
19017SC_QZ2_QUAD_PER_TILE_H6 = 0x00000083,
19018SC_QZ2_QUAD_PER_TILE_H7 = 0x00000084,
19019SC_QZ2_QUAD_PER_TILE_H8 = 0x00000085,
19020SC_QZ2_QUAD_PER_TILE_H9 = 0x00000086,
19021SC_QZ2_QUAD_PER_TILE_H10 = 0x00000087,
19022SC_QZ2_QUAD_PER_TILE_H11 = 0x00000088,
19023SC_QZ2_QUAD_PER_TILE_H12 = 0x00000089,
19024SC_QZ2_QUAD_PER_TILE_H13 = 0x0000008a,
19025SC_QZ2_QUAD_PER_TILE_H14 = 0x0000008b,
19026SC_QZ2_QUAD_PER_TILE_H15 = 0x0000008c,
19027SC_QZ2_QUAD_PER_TILE_H16 = 0x0000008d,
19028SC_QZ3_QUAD_PER_TILE_H0 = 0x0000008e,
19029SC_QZ3_QUAD_PER_TILE_H1 = 0x0000008f,
19030SC_QZ3_QUAD_PER_TILE_H2 = 0x00000090,
19031SC_QZ3_QUAD_PER_TILE_H3 = 0x00000091,
19032SC_QZ3_QUAD_PER_TILE_H4 = 0x00000092,
19033SC_QZ3_QUAD_PER_TILE_H5 = 0x00000093,
19034SC_QZ3_QUAD_PER_TILE_H6 = 0x00000094,
19035SC_QZ3_QUAD_PER_TILE_H7 = 0x00000095,
19036SC_QZ3_QUAD_PER_TILE_H8 = 0x00000096,
19037SC_QZ3_QUAD_PER_TILE_H9 = 0x00000097,
19038SC_QZ3_QUAD_PER_TILE_H10 = 0x00000098,
19039SC_QZ3_QUAD_PER_TILE_H11 = 0x00000099,
19040SC_QZ3_QUAD_PER_TILE_H12 = 0x0000009a,
19041SC_QZ3_QUAD_PER_TILE_H13 = 0x0000009b,
19042SC_QZ3_QUAD_PER_TILE_H14 = 0x0000009c,
19043SC_QZ3_QUAD_PER_TILE_H15 = 0x0000009d,
19044SC_QZ3_QUAD_PER_TILE_H16 = 0x0000009e,
19045SC_QZ0_QUAD_COUNT = 0x0000009f,
19046SC_QZ1_QUAD_COUNT = 0x000000a0,
19047SC_QZ2_QUAD_COUNT = 0x000000a1,
19048SC_QZ3_QUAD_COUNT = 0x000000a2,
19049SC_P0_HIZ_TILE_COUNT = 0x000000a3,
19050SC_P1_HIZ_TILE_COUNT = 0x000000a4,
19051SC_P2_HIZ_TILE_COUNT = 0x000000a5,
19052SC_P3_HIZ_TILE_COUNT = 0x000000a6,
19053SC_P0_HIZ_QUAD_PER_TILE_H0 = 0x000000a7,
19054SC_P0_HIZ_QUAD_PER_TILE_H1 = 0x000000a8,
19055SC_P0_HIZ_QUAD_PER_TILE_H2 = 0x000000a9,
19056SC_P0_HIZ_QUAD_PER_TILE_H3 = 0x000000aa,
19057SC_P0_HIZ_QUAD_PER_TILE_H4 = 0x000000ab,
19058SC_P0_HIZ_QUAD_PER_TILE_H5 = 0x000000ac,
19059SC_P0_HIZ_QUAD_PER_TILE_H6 = 0x000000ad,
19060SC_P0_HIZ_QUAD_PER_TILE_H7 = 0x000000ae,
19061SC_P0_HIZ_QUAD_PER_TILE_H8 = 0x000000af,
19062SC_P0_HIZ_QUAD_PER_TILE_H9 = 0x000000b0,
19063SC_P0_HIZ_QUAD_PER_TILE_H10 = 0x000000b1,
19064SC_P0_HIZ_QUAD_PER_TILE_H11 = 0x000000b2,
19065SC_P0_HIZ_QUAD_PER_TILE_H12 = 0x000000b3,
19066SC_P0_HIZ_QUAD_PER_TILE_H13 = 0x000000b4,
19067SC_P0_HIZ_QUAD_PER_TILE_H14 = 0x000000b5,
19068SC_P0_HIZ_QUAD_PER_TILE_H15 = 0x000000b6,
19069SC_P0_HIZ_QUAD_PER_TILE_H16 = 0x000000b7,
19070SC_P1_HIZ_QUAD_PER_TILE_H0 = 0x000000b8,
19071SC_P1_HIZ_QUAD_PER_TILE_H1 = 0x000000b9,
19072SC_P1_HIZ_QUAD_PER_TILE_H2 = 0x000000ba,
19073SC_P1_HIZ_QUAD_PER_TILE_H3 = 0x000000bb,
19074SC_P1_HIZ_QUAD_PER_TILE_H4 = 0x000000bc,
19075SC_P1_HIZ_QUAD_PER_TILE_H5 = 0x000000bd,
19076SC_P1_HIZ_QUAD_PER_TILE_H6 = 0x000000be,
19077SC_P1_HIZ_QUAD_PER_TILE_H7 = 0x000000bf,
19078SC_P1_HIZ_QUAD_PER_TILE_H8 = 0x000000c0,
19079SC_P1_HIZ_QUAD_PER_TILE_H9 = 0x000000c1,
19080SC_P1_HIZ_QUAD_PER_TILE_H10 = 0x000000c2,
19081SC_P1_HIZ_QUAD_PER_TILE_H11 = 0x000000c3,
19082SC_P1_HIZ_QUAD_PER_TILE_H12 = 0x000000c4,
19083SC_P1_HIZ_QUAD_PER_TILE_H13 = 0x000000c5,
19084SC_P1_HIZ_QUAD_PER_TILE_H14 = 0x000000c6,
19085SC_P1_HIZ_QUAD_PER_TILE_H15 = 0x000000c7,
19086SC_P1_HIZ_QUAD_PER_TILE_H16 = 0x000000c8,
19087SC_P2_HIZ_QUAD_PER_TILE_H0 = 0x000000c9,
19088SC_P2_HIZ_QUAD_PER_TILE_H1 = 0x000000ca,
19089SC_P2_HIZ_QUAD_PER_TILE_H2 = 0x000000cb,
19090SC_P2_HIZ_QUAD_PER_TILE_H3 = 0x000000cc,
19091SC_P2_HIZ_QUAD_PER_TILE_H4 = 0x000000cd,
19092SC_P2_HIZ_QUAD_PER_TILE_H5 = 0x000000ce,
19093SC_P2_HIZ_QUAD_PER_TILE_H6 = 0x000000cf,
19094SC_P2_HIZ_QUAD_PER_TILE_H7 = 0x000000d0,
19095SC_P2_HIZ_QUAD_PER_TILE_H8 = 0x000000d1,
19096SC_P2_HIZ_QUAD_PER_TILE_H9 = 0x000000d2,
19097SC_P2_HIZ_QUAD_PER_TILE_H10 = 0x000000d3,
19098SC_P2_HIZ_QUAD_PER_TILE_H11 = 0x000000d4,
19099SC_P2_HIZ_QUAD_PER_TILE_H12 = 0x000000d5,
19100SC_P2_HIZ_QUAD_PER_TILE_H13 = 0x000000d6,
19101SC_P2_HIZ_QUAD_PER_TILE_H14 = 0x000000d7,
19102SC_P2_HIZ_QUAD_PER_TILE_H15 = 0x000000d8,
19103SC_P2_HIZ_QUAD_PER_TILE_H16 = 0x000000d9,
19104SC_P3_HIZ_QUAD_PER_TILE_H0 = 0x000000da,
19105SC_P3_HIZ_QUAD_PER_TILE_H1 = 0x000000db,
19106SC_P3_HIZ_QUAD_PER_TILE_H2 = 0x000000dc,
19107SC_P3_HIZ_QUAD_PER_TILE_H3 = 0x000000dd,
19108SC_P3_HIZ_QUAD_PER_TILE_H4 = 0x000000de,
19109SC_P3_HIZ_QUAD_PER_TILE_H5 = 0x000000df,
19110SC_P3_HIZ_QUAD_PER_TILE_H6 = 0x000000e0,
19111SC_P3_HIZ_QUAD_PER_TILE_H7 = 0x000000e1,
19112SC_P3_HIZ_QUAD_PER_TILE_H8 = 0x000000e2,
19113SC_P3_HIZ_QUAD_PER_TILE_H9 = 0x000000e3,
19114SC_P3_HIZ_QUAD_PER_TILE_H10 = 0x000000e4,
19115SC_P3_HIZ_QUAD_PER_TILE_H11 = 0x000000e5,
19116SC_P3_HIZ_QUAD_PER_TILE_H12 = 0x000000e6,
19117SC_P3_HIZ_QUAD_PER_TILE_H13 = 0x000000e7,
19118SC_P3_HIZ_QUAD_PER_TILE_H14 = 0x000000e8,
19119SC_P3_HIZ_QUAD_PER_TILE_H15 = 0x000000e9,
19120SC_P3_HIZ_QUAD_PER_TILE_H16 = 0x000000ea,
19121SC_P0_HIZ_QUAD_COUNT = 0x000000eb,
19122SC_P1_HIZ_QUAD_COUNT = 0x000000ec,
19123SC_P2_HIZ_QUAD_COUNT = 0x000000ed,
19124SC_P3_HIZ_QUAD_COUNT = 0x000000ee,
19125SC_P0_DETAIL_QUAD_COUNT = 0x000000ef,
19126SC_P1_DETAIL_QUAD_COUNT = 0x000000f0,
19127SC_P2_DETAIL_QUAD_COUNT = 0x000000f1,
19128SC_P3_DETAIL_QUAD_COUNT = 0x000000f2,
19129SC_P0_DETAIL_QUAD_WITH_1_PIX = 0x000000f3,
19130SC_P0_DETAIL_QUAD_WITH_2_PIX = 0x000000f4,
19131SC_P0_DETAIL_QUAD_WITH_3_PIX = 0x000000f5,
19132SC_P0_DETAIL_QUAD_WITH_4_PIX = 0x000000f6,
19133SC_P1_DETAIL_QUAD_WITH_1_PIX = 0x000000f7,
19134SC_P1_DETAIL_QUAD_WITH_2_PIX = 0x000000f8,
19135SC_P1_DETAIL_QUAD_WITH_3_PIX = 0x000000f9,
19136SC_P1_DETAIL_QUAD_WITH_4_PIX = 0x000000fa,
19137SC_P2_DETAIL_QUAD_WITH_1_PIX = 0x000000fb,
19138SC_P2_DETAIL_QUAD_WITH_2_PIX = 0x000000fc,
19139SC_P2_DETAIL_QUAD_WITH_3_PIX = 0x000000fd,
19140SC_P2_DETAIL_QUAD_WITH_4_PIX = 0x000000fe,
19141SC_P3_DETAIL_QUAD_WITH_1_PIX = 0x000000ff,
19142SC_P3_DETAIL_QUAD_WITH_2_PIX = 0x00000100,
19143SC_P3_DETAIL_QUAD_WITH_3_PIX = 0x00000101,
19144SC_P3_DETAIL_QUAD_WITH_4_PIX = 0x00000102,
19145SC_EARLYZ_QUAD_COUNT = 0x00000103,
19146SC_EARLYZ_QUAD_WITH_1_PIX = 0x00000104,
19147SC_EARLYZ_QUAD_WITH_2_PIX = 0x00000105,
19148SC_EARLYZ_QUAD_WITH_3_PIX = 0x00000106,
19149SC_EARLYZ_QUAD_WITH_4_PIX = 0x00000107,
19150SC_PKR_QUAD_PER_ROW_H1 = 0x00000108,
19151SC_PKR_QUAD_PER_ROW_H2 = 0x00000109,
19152SC_PKR_4X2_QUAD_SPLIT = 0x0000010a,
19153SC_PKR_4X2_FILL_QUAD = 0x0000010b,
19154SC_PKR_END_OF_VECTOR = 0x0000010c,
19155SC_PKR_CONTROL_XFER = 0x0000010d,
19156SC_PKR_DBHANG_FORCE_EOV = 0x0000010e,
19157SC_REG_SCLK_BUSY = 0x0000010f,
19158SC_GRP0_DYN_SCLK_BUSY = 0x00000110,
19159SC_GRP1_DYN_SCLK_BUSY = 0x00000111,
19160SC_GRP2_DYN_SCLK_BUSY = 0x00000112,
19161SC_GRP3_DYN_SCLK_BUSY = 0x00000113,
19162SC_GRP4_DYN_SCLK_BUSY = 0x00000114,
19163SC_PA0_SC_DATA_FIFO_RD = 0x00000115,
19164SC_PA0_SC_DATA_FIFO_WE = 0x00000116,
19165SC_PA1_SC_DATA_FIFO_RD = 0x00000117,
19166SC_PA1_SC_DATA_FIFO_WE = 0x00000118,
19167SC_PS_ARB_XFC_ALL_EVENT_OR_PRIM_CYCLES = 0x00000119,
19168SC_PS_ARB_XFC_ONLY_PRIM_CYCLES = 0x0000011a,
19169SC_PS_ARB_XFC_ONLY_ONE_INC_PER_PRIM = 0x0000011b,
19170SC_PS_ARB_STALLED_FROM_BELOW = 0x0000011c,
19171SC_PS_ARB_STARVED_FROM_ABOVE = 0x0000011d,
19172SC_PS_ARB_SC_BUSY = 0x0000011e,
19173SC_PS_ARB_PA_SC_BUSY = 0x0000011f,
19174SC_PA2_SC_DATA_FIFO_RD = 0x00000120,
19175SC_PA2_SC_DATA_FIFO_WE = 0x00000121,
19176SC_PA3_SC_DATA_FIFO_RD = 0x00000122,
19177SC_PA3_SC_DATA_FIFO_WE = 0x00000123,
19178SC_PA_SC_DEALLOC_0_0_WE = 0x00000124,
19179SC_PA_SC_DEALLOC_0_1_WE = 0x00000125,
19180SC_PA_SC_DEALLOC_1_0_WE = 0x00000126,
19181SC_PA_SC_DEALLOC_1_1_WE = 0x00000127,
19182SC_PA_SC_DEALLOC_2_0_WE = 0x00000128,
19183SC_PA_SC_DEALLOC_2_1_WE = 0x00000129,
19184SC_PA_SC_DEALLOC_3_0_WE = 0x0000012a,
19185SC_PA_SC_DEALLOC_3_1_WE = 0x0000012b,
19186SC_PA0_SC_EOP_WE = 0x0000012c,
19187SC_PA0_SC_EOPG_WE = 0x0000012d,
19188SC_PA0_SC_EVENT_WE = 0x0000012e,
19189SC_PA1_SC_EOP_WE = 0x0000012f,
19190SC_PA1_SC_EOPG_WE = 0x00000130,
19191SC_PA1_SC_EVENT_WE = 0x00000131,
19192SC_PA2_SC_EOP_WE = 0x00000132,
19193SC_PA2_SC_EOPG_WE = 0x00000133,
19194SC_PA2_SC_EVENT_WE = 0x00000134,
19195SC_PA3_SC_EOP_WE = 0x00000135,
19196SC_PA3_SC_EOPG_WE = 0x00000136,
19197SC_PA3_SC_EVENT_WE = 0x00000137,
19198SC_PS_ARB_OOO_THRESHOLD_SWITCH_TO_DESIRED_FIFO = 0x00000138,
19199SC_PS_ARB_OOO_FIFO_EMPTY_SWITCH = 0x00000139,
19200SC_PS_ARB_NULL_PRIM_BUBBLE_POP = 0x0000013a,
19201SC_PS_ARB_EOP_POP_SYNC_POP = 0x0000013b,
19202SC_PS_ARB_EVENT_SYNC_POP = 0x0000013c,
19203SC_SC_PS_ENG_MULTICYCLE_BUBBLE = 0x0000013d,
19204SC_PA0_SC_FPOV_WE = 0x0000013e,
19205SC_PA1_SC_FPOV_WE = 0x0000013f,
19206SC_PA2_SC_FPOV_WE = 0x00000140,
19207SC_PA3_SC_FPOV_WE = 0x00000141,
19208SC_PA0_SC_LPOV_WE = 0x00000142,
19209SC_PA1_SC_LPOV_WE = 0x00000143,
19210SC_PA2_SC_LPOV_WE = 0x00000144,
19211SC_PA3_SC_LPOV_WE = 0x00000145,
19212SC_SC_SPI_DEALLOC_0_0 = 0x00000146,
19213SC_SC_SPI_DEALLOC_0_1 = 0x00000147,
19214SC_SC_SPI_DEALLOC_0_2 = 0x00000148,
19215SC_SC_SPI_DEALLOC_1_0 = 0x00000149,
19216SC_SC_SPI_DEALLOC_1_1 = 0x0000014a,
19217SC_SC_SPI_DEALLOC_1_2 = 0x0000014b,
19218SC_SC_SPI_DEALLOC_2_0 = 0x0000014c,
19219SC_SC_SPI_DEALLOC_2_1 = 0x0000014d,
19220SC_SC_SPI_DEALLOC_2_2 = 0x0000014e,
19221SC_SC_SPI_DEALLOC_3_0 = 0x0000014f,
19222SC_SC_SPI_DEALLOC_3_1 = 0x00000150,
19223SC_SC_SPI_DEALLOC_3_2 = 0x00000151,
19224SC_SC_SPI_FPOV_0 = 0x00000152,
19225SC_SC_SPI_FPOV_1 = 0x00000153,
19226SC_SC_SPI_FPOV_2 = 0x00000154,
19227SC_SC_SPI_FPOV_3 = 0x00000155,
19228SC_SC_SPI_EVENT = 0x00000156,
19229SC_PS_TS_EVENT_FIFO_PUSH = 0x00000157,
19230SC_PS_TS_EVENT_FIFO_POP = 0x00000158,
19231SC_PS_CTX_DONE_FIFO_PUSH = 0x00000159,
19232SC_PS_CTX_DONE_FIFO_POP = 0x0000015a,
19233SC_MULTICYCLE_BUBBLE_FREEZE = 0x0000015b,
19234SC_EOP_SYNC_WINDOW = 0x0000015c,
19235SC_PA0_SC_NULL_WE = 0x0000015d,
19236SC_PA0_SC_NULL_DEALLOC_WE = 0x0000015e,
19237SC_PA0_SC_DATA_FIFO_EOPG_RD = 0x0000015f,
19238SC_PA0_SC_DATA_FIFO_EOP_RD = 0x00000160,
19239SC_PA0_SC_DEALLOC_0_RD = 0x00000161,
19240SC_PA0_SC_DEALLOC_1_RD = 0x00000162,
19241SC_PA1_SC_DATA_FIFO_EOPG_RD = 0x00000163,
19242SC_PA1_SC_DATA_FIFO_EOP_RD = 0x00000164,
19243SC_PA1_SC_DEALLOC_0_RD = 0x00000165,
19244SC_PA1_SC_DEALLOC_1_RD = 0x00000166,
19245SC_PA1_SC_NULL_WE = 0x00000167,
19246SC_PA1_SC_NULL_DEALLOC_WE = 0x00000168,
19247SC_PA2_SC_DATA_FIFO_EOPG_RD = 0x00000169,
19248SC_PA2_SC_DATA_FIFO_EOP_RD = 0x0000016a,
19249SC_PA2_SC_DEALLOC_0_RD = 0x0000016b,
19250SC_PA2_SC_DEALLOC_1_RD = 0x0000016c,
19251SC_PA2_SC_NULL_WE = 0x0000016d,
19252SC_PA2_SC_NULL_DEALLOC_WE = 0x0000016e,
19253SC_PA3_SC_DATA_FIFO_EOPG_RD = 0x0000016f,
19254SC_PA3_SC_DATA_FIFO_EOP_RD = 0x00000170,
19255SC_PA3_SC_DEALLOC_0_RD = 0x00000171,
19256SC_PA3_SC_DEALLOC_1_RD = 0x00000172,
19257SC_PA3_SC_NULL_WE = 0x00000173,
19258SC_PA3_SC_NULL_DEALLOC_WE = 0x00000174,
19259SC_PS_PA0_SC_FIFO_EMPTY = 0x00000175,
19260SC_PS_PA0_SC_FIFO_FULL = 0x00000176,
19261SC_RESERVED_0 = 0x00000177,
19262SC_PS_PA1_SC_FIFO_EMPTY = 0x00000178,
19263SC_PS_PA1_SC_FIFO_FULL = 0x00000179,
19264SC_RESERVED_1 = 0x0000017a,
19265SC_PS_PA2_SC_FIFO_EMPTY = 0x0000017b,
19266SC_PS_PA2_SC_FIFO_FULL = 0x0000017c,
19267SC_RESERVED_2 = 0x0000017d,
19268SC_PS_PA3_SC_FIFO_EMPTY = 0x0000017e,
19269SC_PS_PA3_SC_FIFO_FULL = 0x0000017f,
19270SC_RESERVED_3 = 0x00000180,
19271SC_BUSY_PROCESSING_MULTICYCLE_PRIM = 0x00000181,
19272SC_BUSY_CNT_NOT_ZERO = 0x00000182,
19273SC_BM_BUSY = 0x00000183,
19274SC_BACKEND_BUSY = 0x00000184,
19275SC_SCF_SCB_INTERFACE_BUSY = 0x00000185,
19276SC_SCB_BUSY = 0x00000186,
19277SC_STARVED_BY_PA_WITH_UNSELECTED_PA_NOT_EMPTY = 0x00000187,
19278SC_STARVED_BY_PA_WITH_UNSELECTED_PA_FULL = 0x00000188,
19279SC_PBB_BIN_HIST_NUM_PRIMS = 0x00000189,
19280SC_PBB_BATCH_HIST_NUM_PRIMS = 0x0000018a,
19281SC_PBB_BIN_HIST_NUM_CONTEXTS = 0x0000018b,
19282SC_PBB_BATCH_HIST_NUM_CONTEXTS = 0x0000018c,
19283SC_PBB_BIN_HIST_NUM_PERSISTENT_STATES = 0x0000018d,
19284SC_PBB_BATCH_HIST_NUM_PERSISTENT_STATES = 0x0000018e,
19285SC_PBB_BATCH_HIST_NUM_PS_WAVE_BREAKS = 0x0000018f,
19286SC_PBB_BATCH_HIST_NUM_TRIV_REJECTED_PRIMS = 0x00000190,
19287SC_PBB_BATCH_HIST_NUM_ROWS_PER_PRIM = 0x00000191,
19288SC_PBB_BATCH_HIST_NUM_COLUMNS_PER_ROW = 0x00000192,
19289SC_PBB_BUSY = 0x00000193,
19290SC_PBB_BUSY_AND_NO_SENDS = 0x00000194,
19291SC_PBB_STALLS_PA_DUE_TO_NO_TILES = 0x00000195,
19292SC_PBB_NUM_BINS = 0x00000196,
19293SC_PBB_END_OF_BIN = 0x00000197,
19294SC_PBB_END_OF_BATCH = 0x00000198,
19295SC_PBB_PRIMBIN_PROCESSED = 0x00000199,
19296SC_PBB_PRIM_ADDED_TO_BATCH = 0x0000019a,
19297SC_PBB_NONBINNED_PRIM = 0x0000019b,
19298SC_PBB_TOTAL_REAL_PRIMS_OUT_OF_PBB = 0x0000019c,
19299SC_PBB_TOTAL_NULL_PRIMS_OUT_OF_PBB = 0x0000019d,
19300SC_PBB_IDLE_CLK_DUE_TO_ROW_TO_COLUMN_TRANSITION = 0x0000019e,
19301SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_ROW = 0x0000019f,
19302SC_PBB_IDLE_CLK_DUE_TO_FALSE_POSITIVE_ON_COLUMN = 0x000001a0,
19303SC_PBB_BATCH_BREAK_DUE_TO_PERSISTENT_STATE = 0x000001a1,
19304SC_PBB_BATCH_BREAK_DUE_TO_CONTEXT_STATE = 0x000001a2,
19305SC_PBB_BATCH_BREAK_DUE_TO_PRIM = 0x000001a3,
19306SC_PBB_BATCH_BREAK_DUE_TO_PC_STORAGE = 0x000001a4,
19307SC_PBB_BATCH_BREAK_DUE_TO_EVENT = 0x000001a5,
19308SC_PBB_BATCH_BREAK_DUE_TO_FPOV_LIMIT = 0x000001a6,
19309SC_POPS_INTRA_WAVE_OVERLAPS = 0x000001a7,
19310SC_POPS_FORCE_EOV = 0x000001a8,
19311SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_WAVES_SINCE_OVLP_SET_TO_MAX = 0x000001a9,
19312SC_PKR_QUAD_OVLP_NOT_FOUND_IN_WAVE_TABLE_AND_NO_CHANGE_TO_WAVES_SINCE_OVLP = 0x000001aa,
19313SC_PKR_QUAD_OVLP_FOUND_IN_WAVE_TABLE = 0x000001ab,
19314SC_FULL_FULL_QUAD = 0x000001ac,
19315SC_FULL_HALF_QUAD = 0x000001ad,
19316SC_FULL_QTR_QUAD = 0x000001ae,
19317SC_HALF_FULL_QUAD = 0x000001af,
19318SC_HALF_HALF_QUAD = 0x000001b0,
19319SC_HALF_QTR_QUAD = 0x000001b1,
19320SC_QTR_FULL_QUAD = 0x000001b2,
19321SC_QTR_HALF_QUAD = 0x000001b3,
19322SC_QTR_QTR_QUAD = 0x000001b4,
19323SC_GRP5_DYN_SCLK_BUSY = 0x000001b5,
19324SC_GRP6_DYN_SCLK_BUSY = 0x000001b6,
19325SC_GRP7_DYN_SCLK_BUSY = 0x000001b7,
19326SC_GRP8_DYN_SCLK_BUSY = 0x000001b8,
19327SC_GRP9_DYN_SCLK_BUSY = 0x000001b9,
19328SC_PS_TO_BE_SCLK_GATE_STALL = 0x000001ba,
19329SC_PA_TO_PBB_SCLK_GATE_STALL_STALL = 0x000001bb,
19330SC_PK_BUSY = 0x000001bc,
19331SC_PK_MAX_DEALLOC_FORCE_EOV = 0x000001bd,
19332SC_PK_DEALLOC_WAVE_BREAK = 0x000001be,
19333SC_SPI_SEND = 0x000001bf,
19334SC_SPI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c0,
19335SC_SPI_CREDIT_AT_MAX = 0x000001c1,
19336SC_SPI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c2,
19337SC_BCI_SEND = 0x000001c3,
19338SC_BCI_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001c4,
19339SC_BCI_CREDIT_AT_MAX = 0x000001c5,
19340SC_BCI_CREDIT_AT_MAX_NO_PENDING_SEND = 0x000001c6,
19341SC_SPIBC_FULL_FREEZE = 0x000001c7,
19342SC_PW_BM_PASS_EMPTY_PRIM = 0x000001c8,
19343SC_SUPERTILE_COUNT_EXCLUDE_PASS_EMPTY_PRIM = 0x000001c9,
19344SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H0 = 0x000001ca,
19345SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H1 = 0x000001cb,
19346SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H2 = 0x000001cc,
19347SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H3 = 0x000001cd,
19348SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H4 = 0x000001ce,
19349SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H5 = 0x000001cf,
19350SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H6 = 0x000001d0,
19351SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H7 = 0x000001d1,
19352SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H8 = 0x000001d2,
19353SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H9 = 0x000001d3,
19354SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H10 = 0x000001d4,
19355SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H11 = 0x000001d5,
19356SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H12 = 0x000001d6,
19357SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H13 = 0x000001d7,
19358SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H14 = 0x000001d8,
19359SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H15 = 0x000001d9,
19360SC_SUPERTILE_PER_PRIM_EXCLUDE_PASS_EMPTY_PRIM_H16 = 0x000001da,
19361SC_DB0_TILE_INTERFACE_BUSY = 0x000001db,
19362SC_DB0_TILE_INTERFACE_SEND = 0x000001dc,
19363SC_DB0_TILE_INTERFACE_SEND_EVENT = 0x000001dd,
19364SC_DB0_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001de,
19365SC_DB0_TILE_INTERFACE_SEND_SOP = 0x000001df,
19366SC_DB0_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e0,
19367SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e1,
19368SC_DB0_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001e2,
19369SC_DB1_TILE_INTERFACE_BUSY = 0x000001e3,
19370SC_DB1_TILE_INTERFACE_SEND = 0x000001e4,
19371SC_DB1_TILE_INTERFACE_SEND_EVENT = 0x000001e5,
19372SC_DB1_TILE_INTERFACE_SEND_SOP_ONLY_EVENT = 0x000001e6,
19373SC_DB1_TILE_INTERFACE_SEND_SOP = 0x000001e7,
19374SC_DB1_TILE_INTERFACE_CREDIT_AT_ZERO_WITH_PENDING_SEND = 0x000001e8,
19375SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX = 0x000001e9,
19376SC_DB1_TILE_INTERFACE_CREDIT_AT_MAX_WITH_NO_PENDING_SEND = 0x000001ea,
19377SC_BACKEND_PRIM_FIFO_FULL = 0x000001eb,
19378SC_PBB_BATCH_BREAK_DUE_TO_TIMEOUT_COUNTER = 0x000001ec,
19379SC_PBB_BATCH_BREAK_DUE_TO_NONBINNED_BATCH = 0x000001ed,
19380SC_PBB_BATCH_BREAK_DUE_TO_DEBUG_DATA_PER_DRAW_DISPATCH = 0x000001ee,
19381SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_PERSISTENT = 0x000001ef,
19382SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_CONTEXT = 0x000001f0,
19383SC_PBB_BATCH_BREAK_DUE_TO_OVERRIDE_REGISTER_FPOV = 0x000001f1,
19384SC_PBB_BATCH_BREAK_DUE_TO_NEW_SC_MODE = 0x000001f2,
19385SC_PBB_BATCH_BREAK_DUE_TO_BINNING_MODE_CHANGE = 0x000001f3,
19386SC_PBB_BATCH_BREAK_DUE_TO_PIPELINE_EVENT_COUNT = 0x000001f4,
19387} SC_PERFCNT_SEL;
19388
19389/*
19390 * SePairXsel enum
19391 */
19392
19393typedef enum SePairXsel {
19394RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE = 0x00000000,
19395RASTER_CONFIG_SE_PAIR_XSEL_16_WIDE_TILE = 0x00000001,
19396RASTER_CONFIG_SE_PAIR_XSEL_32_WIDE_TILE = 0x00000002,
19397RASTER_CONFIG_SE_PAIR_XSEL_64_WIDE_TILE = 0x00000003,
19398} SePairXsel;
19399
19400/*
19401 * SePairYsel enum
19402 */
19403
19404typedef enum SePairYsel {
19405RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE = 0x00000000,
19406RASTER_CONFIG_SE_PAIR_YSEL_16_WIDE_TILE = 0x00000001,
19407RASTER_CONFIG_SE_PAIR_YSEL_32_WIDE_TILE = 0x00000002,
19408RASTER_CONFIG_SE_PAIR_YSEL_64_WIDE_TILE = 0x00000003,
19409} SePairYsel;
19410
19411/*
19412 * SePairMap enum
19413 */
19414
19415typedef enum SePairMap {
19416RASTER_CONFIG_SE_PAIR_MAP_0 = 0x00000000,
19417RASTER_CONFIG_SE_PAIR_MAP_1 = 0x00000001,
19418RASTER_CONFIG_SE_PAIR_MAP_2 = 0x00000002,
19419RASTER_CONFIG_SE_PAIR_MAP_3 = 0x00000003,
19420} SePairMap;
19421
19422/*
19423 * SeXsel enum
19424 */
19425
19426typedef enum SeXsel {
19427RASTER_CONFIG_SE_XSEL_8_WIDE_TILE = 0x00000000,
19428RASTER_CONFIG_SE_XSEL_16_WIDE_TILE = 0x00000001,
19429RASTER_CONFIG_SE_XSEL_32_WIDE_TILE = 0x00000002,
19430RASTER_CONFIG_SE_XSEL_64_WIDE_TILE = 0x00000003,
19431} SeXsel;
19432
19433/*
19434 * SeYsel enum
19435 */
19436
19437typedef enum SeYsel {
19438RASTER_CONFIG_SE_YSEL_8_WIDE_TILE = 0x00000000,
19439RASTER_CONFIG_SE_YSEL_16_WIDE_TILE = 0x00000001,
19440RASTER_CONFIG_SE_YSEL_32_WIDE_TILE = 0x00000002,
19441RASTER_CONFIG_SE_YSEL_64_WIDE_TILE = 0x00000003,
19442} SeYsel;
19443
19444/*
19445 * SeMap enum
19446 */
19447
19448typedef enum SeMap {
19449RASTER_CONFIG_SE_MAP_0 = 0x00000000,
19450RASTER_CONFIG_SE_MAP_1 = 0x00000001,
19451RASTER_CONFIG_SE_MAP_2 = 0x00000002,
19452RASTER_CONFIG_SE_MAP_3 = 0x00000003,
19453} SeMap;
19454
19455/*
19456 * ScXsel enum
19457 */
19458
19459typedef enum ScXsel {
19460RASTER_CONFIG_SC_XSEL_8_WIDE_TILE = 0x00000000,
19461RASTER_CONFIG_SC_XSEL_16_WIDE_TILE = 0x00000001,
19462RASTER_CONFIG_SC_XSEL_32_WIDE_TILE = 0x00000002,
19463RASTER_CONFIG_SC_XSEL_64_WIDE_TILE = 0x00000003,
19464} ScXsel;
19465
19466/*
19467 * ScYsel enum
19468 */
19469
19470typedef enum ScYsel {
19471RASTER_CONFIG_SC_YSEL_8_WIDE_TILE = 0x00000000,
19472RASTER_CONFIG_SC_YSEL_16_WIDE_TILE = 0x00000001,
19473RASTER_CONFIG_SC_YSEL_32_WIDE_TILE = 0x00000002,
19474RASTER_CONFIG_SC_YSEL_64_WIDE_TILE = 0x00000003,
19475} ScYsel;
19476
19477/*
19478 * ScMap enum
19479 */
19480
19481typedef enum ScMap {
19482RASTER_CONFIG_SC_MAP_0 = 0x00000000,
19483RASTER_CONFIG_SC_MAP_1 = 0x00000001,
19484RASTER_CONFIG_SC_MAP_2 = 0x00000002,
19485RASTER_CONFIG_SC_MAP_3 = 0x00000003,
19486} ScMap;
19487
19488/*
19489 * PkrXsel2 enum
19490 */
19491
19492typedef enum PkrXsel2 {
19493RASTER_CONFIG_PKR_XSEL2_0 = 0x00000000,
19494RASTER_CONFIG_PKR_XSEL2_1 = 0x00000001,
19495RASTER_CONFIG_PKR_XSEL2_2 = 0x00000002,
19496RASTER_CONFIG_PKR_XSEL2_3 = 0x00000003,
19497} PkrXsel2;
19498
19499/*
19500 * PkrXsel enum
19501 */
19502
19503typedef enum PkrXsel {
19504RASTER_CONFIG_PKR_XSEL_0 = 0x00000000,
19505RASTER_CONFIG_PKR_XSEL_1 = 0x00000001,
19506RASTER_CONFIG_PKR_XSEL_2 = 0x00000002,
19507RASTER_CONFIG_PKR_XSEL_3 = 0x00000003,
19508} PkrXsel;
19509
19510/*
19511 * PkrYsel enum
19512 */
19513
19514typedef enum PkrYsel {
19515RASTER_CONFIG_PKR_YSEL_0 = 0x00000000,
19516RASTER_CONFIG_PKR_YSEL_1 = 0x00000001,
19517RASTER_CONFIG_PKR_YSEL_2 = 0x00000002,
19518RASTER_CONFIG_PKR_YSEL_3 = 0x00000003,
19519} PkrYsel;
19520
19521/*
19522 * PkrMap enum
19523 */
19524
19525typedef enum PkrMap {
19526RASTER_CONFIG_PKR_MAP_0 = 0x00000000,
19527RASTER_CONFIG_PKR_MAP_1 = 0x00000001,
19528RASTER_CONFIG_PKR_MAP_2 = 0x00000002,
19529RASTER_CONFIG_PKR_MAP_3 = 0x00000003,
19530} PkrMap;
19531
19532/*
19533 * RbXsel enum
19534 */
19535
19536typedef enum RbXsel {
19537RASTER_CONFIG_RB_XSEL_0 = 0x00000000,
19538RASTER_CONFIG_RB_XSEL_1 = 0x00000001,
19539} RbXsel;
19540
19541/*
19542 * RbYsel enum
19543 */
19544
19545typedef enum RbYsel {
19546RASTER_CONFIG_RB_YSEL_0 = 0x00000000,
19547RASTER_CONFIG_RB_YSEL_1 = 0x00000001,
19548} RbYsel;
19549
19550/*
19551 * RbXsel2 enum
19552 */
19553
19554typedef enum RbXsel2 {
19555RASTER_CONFIG_RB_XSEL2_0 = 0x00000000,
19556RASTER_CONFIG_RB_XSEL2_1 = 0x00000001,
19557RASTER_CONFIG_RB_XSEL2_2 = 0x00000002,
19558RASTER_CONFIG_RB_XSEL2_3 = 0x00000003,
19559} RbXsel2;
19560
19561/*
19562 * RbMap enum
19563 */
19564
19565typedef enum RbMap {
19566RASTER_CONFIG_RB_MAP_0 = 0x00000000,
19567RASTER_CONFIG_RB_MAP_1 = 0x00000001,
19568RASTER_CONFIG_RB_MAP_2 = 0x00000002,
19569RASTER_CONFIG_RB_MAP_3 = 0x00000003,
19570} RbMap;
19571
19572/*
19573 * BinningMode enum
19574 */
19575
19576typedef enum BinningMode {
19577BINNING_ALLOWED = 0x00000000,
19578FORCE_BINNING_ON = 0x00000001,
19579DISABLE_BINNING_USE_NEW_SC = 0x00000002,
19580DISABLE_BINNING_USE_LEGACY_SC = 0x00000003,
19581} BinningMode;
19582
19583/*
19584 * BinSizeExtend enum
19585 */
19586
19587typedef enum BinSizeExtend {
19588BIN_SIZE_32_PIXELS = 0x00000000,
19589BIN_SIZE_64_PIXELS = 0x00000001,
19590BIN_SIZE_128_PIXELS = 0x00000002,
19591BIN_SIZE_256_PIXELS = 0x00000003,
19592BIN_SIZE_512_PIXELS = 0x00000004,
19593} BinSizeExtend;
19594
19595/*
19596 * BinMapMode enum
19597 */
19598
19599typedef enum BinMapMode {
19600BIN_MAP_MODE_NONE = 0x00000000,
19601BIN_MAP_MODE_RTA_INDEX = 0x00000001,
19602BIN_MAP_MODE_POPS = 0x00000002,
19603} BinMapMode;
19604
19605/*
19606 * BinEventCntl enum
19607 */
19608
19609typedef enum BinEventCntl {
19610BINNER_BREAK_BATCH = 0x00000000,
19611BINNER_PIPELINE = 0x00000001,
19612BINNER_DROP = 0x00000002,
19613BINNER_DROP_ASSERT = 0x00000003,
19614} BinEventCntl;
19615
19616/*
19617 * CovToShaderSel enum
19618 */
19619
19620typedef enum CovToShaderSel {
19621INPUT_COVERAGE = 0x00000000,
19622INPUT_INNER_COVERAGE = 0x00000001,
19623INPUT_DEPTH_COVERAGE = 0x00000002,
19624RAW = 0x00000003,
19625} CovToShaderSel;
19626
19627/*
19628 * ScUncertaintyRegionMode enum
19629 */
19630
19631typedef enum ScUncertaintyRegionMode {
19632SC_HALF_LSB = 0x00000000,
19633SC_LSB_ONE_SIDED = 0x00000001,
19634SC_LSB_TWO_SIDED = 0x00000002,
19635} ScUncertaintyRegionMode;
19636
19637/*******************************************************
19638 * RMI Enums
19639 *******************************************************/
19640
19641/*
19642 * RMIPerfSel enum
19643 */
19644
19645typedef enum RMIPerfSel {
19646RMI_PERF_SEL_NONE = 0x00000000,
19647RMI_PERF_SEL_BUSY = 0x00000001,
19648RMI_PERF_SEL_REG_CLK_VLD = 0x00000002,
19649RMI_PERF_SEL_DYN_CLK_CMN_VLD = 0x00000003,
19650RMI_PERF_SEL_DYN_CLK_RB_VLD = 0x00000004,
19651RMI_PERF_SEL_DYN_CLK_PERF_VLD = 0x00000005,
19652RMI_PERF_SEL_PERF_WINDOW = 0x00000006,
19653RMI_PERF_SEL_EVENT_SEND = 0x00000007,
19654RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID0 = 0x00000008,
19655RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID1 = 0x00000009,
19656RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID2 = 0x0000000a,
19657RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID3 = 0x0000000b,
19658RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID4 = 0x0000000c,
19659RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID5 = 0x0000000d,
19660RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID6 = 0x0000000e,
19661RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID7 = 0x0000000f,
19662RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID8 = 0x00000010,
19663RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID9 = 0x00000011,
19664RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID10 = 0x00000012,
19665RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID11 = 0x00000013,
19666RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID12 = 0x00000014,
19667RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID13 = 0x00000015,
19668RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID14 = 0x00000016,
19669RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID15 = 0x00000017,
19670RMI_PERF_SEL_RMI_INVALIDATION_ATC_REQ_VMID_ALL = 0x00000018,
19671RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID0 = 0x00000019,
19672RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID1 = 0x0000001a,
19673RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID2 = 0x0000001b,
19674RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID3 = 0x0000001c,
19675RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID4 = 0x0000001d,
19676RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID5 = 0x0000001e,
19677RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID6 = 0x0000001f,
19678RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID7 = 0x00000020,
19679RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID8 = 0x00000021,
19680RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID9 = 0x00000022,
19681RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID10 = 0x00000023,
19682RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID11 = 0x00000024,
19683RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID12 = 0x00000025,
19684RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID13 = 0x00000026,
19685RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID14 = 0x00000027,
19686RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID15 = 0x00000028,
19687RMI_PERF_SEL_RMI_INVALIDATION_REQ_START_FINISH_VMID_ALL = 0x00000029,
19688RMI_PERF_SEL_UTCL1_TRANSLATION_MISS = 0x0000002a,
19689RMI_PERF_SEL_UTCL1_PERMISSION_MISS = 0x0000002b,
19690RMI_PERF_SEL_UTCL1_TRANSLATION_HIT = 0x0000002c,
19691RMI_PERF_SEL_UTCL1_REQUEST = 0x0000002d,
19692RMI_PERF_SEL_UTCL1_STALL_INFLIGHT_MAX = 0x0000002e,
19693RMI_PERF_SEL_UTCL1_STALL_LRU_INFLIGHT = 0x0000002f,
19694RMI_PERF_SEL_UTCL1_LFIFO_FULL = 0x00000030,
19695RMI_PERF_SEL_UTCL1_STALL_LFIFO_NOT_RES = 0x00000031,
19696RMI_PERF_SEL_UTCL1_STALL_UTCL2_REQ_OUT_OF_CREDITS = 0x00000032,
19697RMI_PERF_SEL_UTCL1_STALL_MISSFIFO_FULL = 0x00000033,
19698RMI_PERF_SEL_UTCL1_HIT_FIFO_FULL = 0x00000034,
19699RMI_PERF_SEL_UTCL1_STALL_MULTI_MISS = 0x00000035,
19700RMI_PERF_SEL_RB_RMI_WRREQ_ALL_CID = 0x00000036,
19701RMI_PERF_SEL_RB_RMI_WRREQ_TO_WRRET_BUSY = 0x00000037,
19702RMI_PERF_SEL_RB_RMI_WRREQ_CID0 = 0x00000038,
19703RMI_PERF_SEL_RB_RMI_WRREQ_CID1 = 0x00000039,
19704RMI_PERF_SEL_RB_RMI_WRREQ_CID2 = 0x0000003a,
19705RMI_PERF_SEL_RB_RMI_WRREQ_CID3 = 0x0000003b,
19706RMI_PERF_SEL_RB_RMI_WRREQ_CID4 = 0x0000003c,
19707RMI_PERF_SEL_RB_RMI_WRREQ_CID5 = 0x0000003d,
19708RMI_PERF_SEL_RB_RMI_WRREQ_CID6 = 0x0000003e,
19709RMI_PERF_SEL_RB_RMI_WRREQ_CID7 = 0x0000003f,
19710RMI_PERF_SEL_RB_RMI_32BWRREQ_INFLIGHT_ALL_ORONE_CID = 0x00000040,
19711RMI_PERF_SEL_RB_RMI_WRREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000041,
19712RMI_PERF_SEL_RB_RMI_WRREQ_BURST_ALL_ORONE_CID = 0x00000042,
19713RMI_PERF_SEL_RB_RMI_WRREQ_RESIDENCY = 0x00000043,
19714RMI_PERF_SEL_RMI_RB_WRRET_VALID_ALL_CID = 0x00000044,
19715RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID0 = 0x00000045,
19716RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID1 = 0x00000046,
19717RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID2 = 0x00000047,
19718RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID3 = 0x00000048,
19719RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID4 = 0x00000049,
19720RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID5 = 0x0000004a,
19721RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID6 = 0x0000004b,
19722RMI_PERF_SEL_RMI_RB_WRRET_VALID_CID7 = 0x0000004c,
19723RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK0 = 0x0000004d,
19724RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK1 = 0x0000004e,
19725RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK2 = 0x0000004f,
19726RMI_PERF_SEL_RMI_RB_WRRET_VALID_NACK3 = 0x00000050,
19727RMI_PERF_SEL_RB_RMI_32BRDREQ_ALL_CID = 0x00000051,
19728RMI_PERF_SEL_RB_RMI_RDREQ_ALL_CID = 0x00000052,
19729RMI_PERF_SEL_RB_RMI_RDREQ_TO_RDRET_BUSY = 0x00000053,
19730RMI_PERF_SEL_RB_RMI_32BRDREQ_CID0 = 0x00000054,
19731RMI_PERF_SEL_RB_RMI_32BRDREQ_CID1 = 0x00000055,
19732RMI_PERF_SEL_RB_RMI_32BRDREQ_CID2 = 0x00000056,
19733RMI_PERF_SEL_RB_RMI_32BRDREQ_CID3 = 0x00000057,
19734RMI_PERF_SEL_RB_RMI_32BRDREQ_CID4 = 0x00000058,
19735RMI_PERF_SEL_RB_RMI_32BRDREQ_CID5 = 0x00000059,
19736RMI_PERF_SEL_RB_RMI_32BRDREQ_CID6 = 0x0000005a,
19737RMI_PERF_SEL_RB_RMI_32BRDREQ_CID7 = 0x0000005b,
19738RMI_PERF_SEL_RB_RMI_RDREQ_CID0 = 0x0000005c,
19739RMI_PERF_SEL_RB_RMI_RDREQ_CID1 = 0x0000005d,
19740RMI_PERF_SEL_RB_RMI_RDREQ_CID2 = 0x0000005e,
19741RMI_PERF_SEL_RB_RMI_RDREQ_CID3 = 0x0000005f,
19742RMI_PERF_SEL_RB_RMI_RDREQ_CID4 = 0x00000060,
19743RMI_PERF_SEL_RB_RMI_RDREQ_CID5 = 0x00000061,
19744RMI_PERF_SEL_RB_RMI_RDREQ_CID6 = 0x00000062,
19745RMI_PERF_SEL_RB_RMI_RDREQ_CID7 = 0x00000063,
19746RMI_PERF_SEL_RB_RMI_32BRDREQ_INFLIGHT_ALL_ORONE_CID = 0x00000064,
19747RMI_PERF_SEL_RB_RMI_RDREQ_BURST_LENGTH_ALL_ORONE_CID = 0x00000065,
19748RMI_PERF_SEL_RB_RMI_RDREQ_BURST_ALL_ORONE_CID = 0x00000066,
19749RMI_PERF_SEL_RB_RMI_RDREQ_RESIDENCY = 0x00000067,
19750RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_ALL_CID = 0x00000068,
19751RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID0 = 0x00000069,
19752RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID1 = 0x0000006a,
19753RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID2 = 0x0000006b,
19754RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID3 = 0x0000006c,
19755RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID4 = 0x0000006d,
19756RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID5 = 0x0000006e,
19757RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID6 = 0x0000006f,
19758RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_CID7 = 0x00000070,
19759RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK0 = 0x00000071,
19760RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK1 = 0x00000072,
19761RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK2 = 0x00000073,
19762RMI_PERF_SEL_RMI_RB_32BRDRET_VALID_NACK3 = 0x00000074,
19763RMI_PERF_SEL_RB_RMI_WR_FIFO_MAX = 0x00000075,
19764RMI_PERF_SEL_RB_RMI_WR_FIFO_EMPTY = 0x00000076,
19765RMI_PERF_SEL_RB_RMI_WR_IDLE = 0x00000077,
19766RMI_PERF_SEL_RB_RMI_WR_STARVE = 0x00000078,
19767RMI_PERF_SEL_RB_RMI_WR_STALL = 0x00000079,
19768RMI_PERF_SEL_RB_RMI_WR_BUSY = 0x0000007a,
19769RMI_PERF_SEL_RB_RMI_WR_INTF_BUSY = 0x0000007b,
19770RMI_PERF_SEL_RB_RMI_RD_FIFO_MAX = 0x0000007c,
19771RMI_PERF_SEL_RB_RMI_RD_FIFO_EMPTY = 0x0000007d,
19772RMI_PERF_SEL_RB_RMI_RD_IDLE = 0x0000007e,
19773RMI_PERF_SEL_RB_RMI_RD_STARVE = 0x0000007f,
19774RMI_PERF_SEL_RB_RMI_RD_STALL = 0x00000080,
19775RMI_PERF_SEL_RB_RMI_RD_BUSY = 0x00000081,
19776RMI_PERF_SEL_RB_RMI_RD_INTF_BUSY = 0x00000082,
19777RMI_PERF_SEL_RMI_TC_64BWRREQ_ALL_ORONE_CID = 0x00000083,
19778RMI_PERF_SEL_RMI_TC_64BRDREQ_ALL_ORONE_CID = 0x00000084,
19779RMI_PERF_SEL_RMI_TC_WRREQ_ALL_CID = 0x00000085,
19780RMI_PERF_SEL_RMI_TC_REQ_BUSY = 0x00000086,
19781RMI_PERF_SEL_RMI_TC_WRREQ_CID0 = 0x00000087,
19782RMI_PERF_SEL_RMI_TC_WRREQ_CID1 = 0x00000088,
19783RMI_PERF_SEL_RMI_TC_WRREQ_CID2 = 0x00000089,
19784RMI_PERF_SEL_RMI_TC_WRREQ_CID3 = 0x0000008a,
19785RMI_PERF_SEL_RMI_TC_WRREQ_CID4 = 0x0000008b,
19786RMI_PERF_SEL_RMI_TC_WRREQ_CID5 = 0x0000008c,
19787RMI_PERF_SEL_RMI_TC_WRREQ_CID6 = 0x0000008d,
19788RMI_PERF_SEL_RMI_TC_WRREQ_CID7 = 0x0000008e,
19789RMI_PERF_SEL_RMI_TC_WRREQ_INFLIGHT_ALL_CID = 0x0000008f,
19790RMI_PERF_SEL_TC_RMI_WRRET_VALID_ALL_CID = 0x00000090,
19791RMI_PERF_SEL_RMI_TC_RDREQ_ALL_CID = 0x00000091,
19792RMI_PERF_SEL_RMI_TC_RDREQ_CID0 = 0x00000092,
19793RMI_PERF_SEL_RMI_TC_RDREQ_CID1 = 0x00000093,
19794RMI_PERF_SEL_RMI_TC_RDREQ_CID2 = 0x00000094,
19795RMI_PERF_SEL_RMI_TC_RDREQ_CID3 = 0x00000095,
19796RMI_PERF_SEL_RMI_TC_RDREQ_CID4 = 0x00000096,
19797RMI_PERF_SEL_RMI_TC_RDREQ_CID5 = 0x00000097,
19798RMI_PERF_SEL_RMI_TC_RDREQ_CID6 = 0x00000098,
19799RMI_PERF_SEL_RMI_TC_RDREQ_CID7 = 0x00000099,
19800RMI_PERF_SEL_RMI_TC_STALL_RDREQ = 0x0000009a,
19801RMI_PERF_SEL_RMI_TC_STALL_WRREQ = 0x0000009b,
19802RMI_PERF_SEL_RMI_TC_STALL_ALLREQ = 0x0000009c,
19803RMI_PERF_SEL_RMI_TC_CREDIT_FULL_NO_PENDING_SEND = 0x0000009d,
19804RMI_PERF_SEL_RMI_TC_CREDIT_ZERO_PENDING_SEND = 0x0000009e,
19805RMI_PERF_SEL_RMI_TC_RDREQ_INFLIGHT_ALL_CID = 0x0000009f,
19806RMI_PERF_SEL_TC_RMI_RDRET_VALID_ALL_CID = 0x000000a0,
19807RMI_PERF_SEL_UTCL1_BUSY = 0x000000a1,
19808RMI_PERF_SEL_RMI_UTC_REQ = 0x000000a2,
19809RMI_PERF_SEL_RMI_UTC_BUSY = 0x000000a3,
19810RMI_PERF_SEL_UTCL1_UTCL2_REQ = 0x000000a4,
19811RMI_PERF_SEL_LEVEL_ADD_UTCL1_TO_UTCL2 = 0x000000a5,
19812RMI_PERF_SEL_PROBE_UTCL1_XNACK_RETRY = 0x000000a6,
19813RMI_PERF_SEL_PROBE_UTCL1_ALL_FAULT = 0x000000a7,
19814RMI_PERF_SEL_PROBE_UTCL1_PRT_FAULT = 0x000000a8,
19815RMI_PERF_SEL_PROBE_UTCL1_VMID_BYPASS = 0x000000a9,
19816RMI_PERF_SEL_PROBE_UTCL1_XNACK_NORETRY_FAULT = 0x000000aa,
19817RMI_PERF_SEL_XNACK_FIFO_NUM_USED = 0x000000ab,
19818RMI_PERF_SEL_LAT_FIFO_NUM_USED = 0x000000ac,
19819RMI_PERF_SEL_LAT_FIFO_BLOCKING_REQ = 0x000000ad,
19820RMI_PERF_SEL_LAT_FIFO_NONBLOCKING_REQ = 0x000000ae,
19821RMI_PERF_SEL_XNACK_FIFO_FULL = 0x000000af,
19822RMI_PERF_SEL_XNACK_FIFO_BUSY = 0x000000b0,
19823RMI_PERF_SEL_LAT_FIFO_FULL = 0x000000b1,
19824RMI_PERF_SEL_SKID_FIFO_DEPTH = 0x000000b2,
19825RMI_PERF_SEL_TCIW_INFLIGHT_COUNT = 0x000000b3,
19826RMI_PERF_SEL_PRT_FIFO_NUM_USED = 0x000000b4,
19827RMI_PERF_SEL_PRT_FIFO_REQ = 0x000000b5,
19828RMI_PERF_SEL_PRT_FIFO_BUSY = 0x000000b6,
19829RMI_PERF_SEL_TCIW_REQ = 0x000000b7,
19830RMI_PERF_SEL_TCIW_BUSY = 0x000000b8,
19831RMI_PERF_SEL_SKID_FIFO_REQ = 0x000000b9,
19832RMI_PERF_SEL_SKID_FIFO_BUSY = 0x000000ba,
19833RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK0 = 0x000000bb,
19834RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK1 = 0x000000bc,
19835RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK2 = 0x000000bd,
19836RMI_PERF_SEL_DEMUX_TCIW_RESIDENCY_NACK3 = 0x000000be,
19837RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTR = 0x000000bf,
19838RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTR = 0x000000c0,
19839RMI_PERF_SEL_XBAR_PROBEGEN_RTS_RTRB = 0x000000c1,
19840RMI_PERF_SEL_XBAR_PROBEGEN_RTSB_RTRB = 0x000000c2,
19841RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTR = 0x000000c3,
19842RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTR = 0x000000c4,
19843RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTS_RTRB = 0x000000c5,
19844RMI_PERF_SEL_DEMUX_TCIW_FORMATTER_RTSB_RTRB = 0x000000c6,
19845RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTR = 0x000000c7,
19846RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTR = 0x000000c8,
19847RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTS_RTRB = 0x000000c9,
19848RMI_PERF_SEL_WRREQCONSUMER_XBAR_WRREQ_RTSB_RTRB = 0x000000ca,
19849RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTR = 0x000000cb,
19850RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTR = 0x000000cc,
19851RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTS_RTRB = 0x000000cd,
19852RMI_PERF_SEL_RDREQCONSUMER_XBAR_RDREQ_RTSB_RTRB = 0x000000ce,
19853RMI_PERF_SEL_POP_DEMUX_RTS_RTR = 0x000000cf,
19854RMI_PERF_SEL_POP_DEMUX_RTSB_RTR = 0x000000d0,
19855RMI_PERF_SEL_POP_DEMUX_RTS_RTRB = 0x000000d1,
19856RMI_PERF_SEL_POP_DEMUX_RTSB_RTRB = 0x000000d2,
19857RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTR = 0x000000d3,
19858RMI_PERF_SEL_LEVEL_ADD_RMI_TO_UTC = 0x000000d4,
19859RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTR = 0x000000d5,
19860RMI_PERF_SEL_PROBEGEN_UTC_RTS_RTRB = 0x000000d6,
19861RMI_PERF_SEL_PROBEGEN_UTC_RTSB_RTRB = 0x000000d7,
19862RMI_PERF_SEL_UTC_POP_RTS_RTR = 0x000000d8,
19863RMI_PERF_SEL_UTC_POP_RTSB_RTR = 0x000000d9,
19864RMI_PERF_SEL_UTC_POP_RTS_RTRB = 0x000000da,
19865RMI_PERF_SEL_UTC_POP_RTSB_RTRB = 0x000000db,
19866RMI_PERF_SEL_POP_XNACK_RTS_RTR = 0x000000dc,
19867RMI_PERF_SEL_POP_XNACK_RTSB_RTR = 0x000000dd,
19868RMI_PERF_SEL_POP_XNACK_RTS_RTRB = 0x000000de,
19869RMI_PERF_SEL_POP_XNACK_RTSB_RTRB = 0x000000df,
19870RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTR = 0x000000e0,
19871RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTR = 0x000000e1,
19872RMI_PERF_SEL_XNACK_PROBEGEN_RTS_RTRB = 0x000000e2,
19873RMI_PERF_SEL_XNACK_PROBEGEN_RTSB_RTRB = 0x000000e3,
19874RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTR = 0x000000e4,
19875RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTR = 0x000000e5,
19876RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTS_RTRB = 0x000000e6,
19877RMI_PERF_SEL_PRTFIFO_RTNFORMATTER_RTSB_RTRB = 0x000000e7,
19878RMI_PERF_SEL_SKID_FIFO_IN_RTS = 0x000000e8,
19879RMI_PERF_SEL_SKID_FIFO_IN_RTSB = 0x000000e9,
19880RMI_PERF_SEL_SKID_FIFO_OUT_RTS = 0x000000ea,
19881RMI_PERF_SEL_SKID_FIFO_OUT_RTSB = 0x000000eb,
19882RMI_PERF_SEL_XBAR_PROBEGEN_READ_RTS_RTR = 0x000000ec,
19883RMI_PERF_SEL_XBAR_PROBEGEN_WRITE_RTS_RTR = 0x000000ed,
19884RMI_PERF_SEL_XBAR_PROBEGEN_IN0_RTS_RTR = 0x000000ee,
19885RMI_PERF_SEL_XBAR_PROBEGEN_IN1_RTS_RTR = 0x000000ef,
19886RMI_PERF_SEL_XBAR_PROBEGEN_CB_RTS_RTR = 0x000000f0,
19887RMI_PERF_SEL_XBAR_PROBEGEN_DB_RTS_RTR = 0x000000f1,
19888RMI_PERF_SEL_REORDER_FIFO_REQ = 0x000000f2,
19889RMI_PERF_SEL_REORDER_FIFO_BUSY = 0x000000f3,
19890RMI_PERF_SEL_RMI_RB_EARLY_WRACK_ALL_CID = 0x000000f4,
19891RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID0 = 0x000000f5,
19892RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID1 = 0x000000f6,
19893RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID2 = 0x000000f7,
19894RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID3 = 0x000000f8,
19895RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID4 = 0x000000f9,
19896RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID5 = 0x000000fa,
19897RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID6 = 0x000000fb,
19898RMI_PERF_SEL_RMI_RB_EARLY_WRACK_CID7 = 0x000000fc,
19899RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK0 = 0x000000fd,
19900RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK1 = 0x000000fe,
19901RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK2 = 0x000000ff,
19902RMI_PERF_SEL_RMI_RB_EARLY_WRACK_NACK3 = 0x00000100,
19903} RMIPerfSel;
19904
19905/*******************************************************
19906 * PMM Enums
19907 *******************************************************/
19908
19909/*
19910 * GCRPerfSel enum
19911 */
19912
19913typedef enum GCRPerfSel {
19914GCR_PERF_SEL_NONE = 0x00000000,
19915GCR_PERF_SEL_SDMA0_ALL_REQ = 0x00000001,
19916GCR_PERF_SEL_SDMA0_GL2_RANGE_REQ = 0x00000002,
19917GCR_PERF_SEL_SDMA0_GL2_RANGE_LT16K_REQ = 0x00000003,
19918GCR_PERF_SEL_SDMA0_GL2_RANGE_16K_REQ = 0x00000004,
19919GCR_PERF_SEL_SDMA0_GL2_RANGE_GT16K_REQ = 0x00000005,
19920GCR_PERF_SEL_SDMA0_GL2_ALL_REQ = 0x00000006,
19921GCR_PERF_SEL_SDMA0_GL1_RANGE_REQ = 0x00000007,
19922GCR_PERF_SEL_SDMA0_GL1_RANGE_LT16K_REQ = 0x00000008,
19923GCR_PERF_SEL_SDMA0_GL1_RANGE_16K_REQ = 0x00000009,
19924GCR_PERF_SEL_SDMA0_GL1_RANGE_GT16K_REQ = 0x0000000a,
19925GCR_PERF_SEL_SDMA0_GL1_ALL_REQ = 0x0000000b,
19926GCR_PERF_SEL_SDMA0_METADATA_REQ = 0x0000000c,
19927GCR_PERF_SEL_SDMA0_SQC_DATA_REQ = 0x0000000d,
19928GCR_PERF_SEL_SDMA0_SQC_INST_REQ = 0x0000000e,
19929GCR_PERF_SEL_SDMA0_TCP_REQ = 0x0000000f,
19930GCR_PERF_SEL_SDMA0_TCP_TLB_SHOOTDOWN_REQ = 0x00000010,
19931GCR_PERF_SEL_SDMA1_ALL_REQ = 0x00000011,
19932GCR_PERF_SEL_SDMA1_GL2_RANGE_REQ = 0x00000012,
19933GCR_PERF_SEL_SDMA1_GL2_RANGE_LT16K_REQ = 0x00000013,
19934GCR_PERF_SEL_SDMA1_GL2_RANGE_16K_REQ = 0x00000014,
19935GCR_PERF_SEL_SDMA1_GL2_RANGE_GT16K_REQ = 0x00000015,
19936GCR_PERF_SEL_SDMA1_GL2_ALL_REQ = 0x00000016,
19937GCR_PERF_SEL_SDMA1_GL1_RANGE_REQ = 0x00000017,
19938GCR_PERF_SEL_SDMA1_GL1_RANGE_LT16K_REQ = 0x00000018,
19939GCR_PERF_SEL_SDMA1_GL1_RANGE_16K_REQ = 0x00000019,
19940GCR_PERF_SEL_SDMA1_GL1_RANGE_GT16K_REQ = 0x0000001a,
19941GCR_PERF_SEL_SDMA1_GL1_ALL_REQ = 0x0000001b,
19942GCR_PERF_SEL_SDMA1_METADATA_REQ = 0x0000001c,
19943GCR_PERF_SEL_SDMA1_SQC_DATA_REQ = 0x0000001d,
19944GCR_PERF_SEL_SDMA1_SQC_INST_REQ = 0x0000001e,
19945GCR_PERF_SEL_SDMA1_TCP_REQ = 0x0000001f,
19946GCR_PERF_SEL_SDMA1_TCP_TLB_SHOOTDOWN_REQ = 0x00000020,
19947GCR_PERF_SEL_CPG_ALL_REQ = 0x00000021,
19948GCR_PERF_SEL_CPG_GL2_RANGE_REQ = 0x00000022,
19949GCR_PERF_SEL_CPG_GL2_RANGE_LT16K_REQ = 0x00000023,
19950GCR_PERF_SEL_CPG_GL2_RANGE_16K_REQ = 0x00000024,
19951GCR_PERF_SEL_CPG_GL2_RANGE_GT16K_REQ = 0x00000025,
19952GCR_PERF_SEL_CPG_GL2_ALL_REQ = 0x00000026,
19953GCR_PERF_SEL_CPG_GL1_RANGE_REQ = 0x00000027,
19954GCR_PERF_SEL_CPG_GL1_RANGE_LT16K_REQ = 0x00000028,
19955GCR_PERF_SEL_CPG_GL1_RANGE_16K_REQ = 0x00000029,
19956GCR_PERF_SEL_CPG_GL1_RANGE_GT16K_REQ = 0x0000002a,
19957GCR_PERF_SEL_CPG_GL1_ALL_REQ = 0x0000002b,
19958GCR_PERF_SEL_CPG_METADATA_REQ = 0x0000002c,
19959GCR_PERF_SEL_CPG_SQC_DATA_REQ = 0x0000002d,
19960GCR_PERF_SEL_CPG_SQC_INST_REQ = 0x0000002e,
19961GCR_PERF_SEL_CPG_TCP_REQ = 0x0000002f,
19962GCR_PERF_SEL_CPG_TCP_TLB_SHOOTDOWN_REQ = 0x00000030,
19963GCR_PERF_SEL_CPC_ALL_REQ = 0x00000031,
19964GCR_PERF_SEL_CPC_GL2_RANGE_REQ = 0x00000032,
19965GCR_PERF_SEL_CPC_GL2_RANGE_LT16K_REQ = 0x00000033,
19966GCR_PERF_SEL_CPC_GL2_RANGE_16K_REQ = 0x00000034,
19967GCR_PERF_SEL_CPC_GL2_RANGE_GT16K_REQ = 0x00000035,
19968GCR_PERF_SEL_CPC_GL2_ALL_REQ = 0x00000036,
19969GCR_PERF_SEL_CPC_GL1_RANGE_REQ = 0x00000037,
19970GCR_PERF_SEL_CPC_GL1_RANGE_LT16K_REQ = 0x00000038,
19971GCR_PERF_SEL_CPC_GL1_RANGE_16K_REQ = 0x00000039,
19972GCR_PERF_SEL_CPC_GL1_RANGE_GT16K_REQ = 0x0000003a,
19973GCR_PERF_SEL_CPC_GL1_ALL_REQ = 0x0000003b,
19974GCR_PERF_SEL_CPC_METADATA_REQ = 0x0000003c,
19975GCR_PERF_SEL_CPC_SQC_DATA_REQ = 0x0000003d,
19976GCR_PERF_SEL_CPC_SQC_INST_REQ = 0x0000003e,
19977GCR_PERF_SEL_CPC_TCP_REQ = 0x0000003f,
19978GCR_PERF_SEL_CPC_TCP_TLB_SHOOTDOWN_REQ = 0x00000040,
19979GCR_PERF_SEL_CPF_ALL_REQ = 0x00000041,
19980GCR_PERF_SEL_CPF_GL2_RANGE_REQ = 0x00000042,
19981GCR_PERF_SEL_CPF_GL2_RANGE_LT16K_REQ = 0x00000043,
19982GCR_PERF_SEL_CPF_GL2_RANGE_16K_REQ = 0x00000044,
19983GCR_PERF_SEL_CPF_GL2_RANGE_GT16K_REQ = 0x00000045,
19984GCR_PERF_SEL_CPF_GL2_ALL_REQ = 0x00000046,
19985GCR_PERF_SEL_CPF_GL1_RANGE_REQ = 0x00000047,
19986GCR_PERF_SEL_CPF_GL1_RANGE_LT16K_REQ = 0x00000048,
19987GCR_PERF_SEL_CPF_GL1_RANGE_16K_REQ = 0x00000049,
19988GCR_PERF_SEL_CPF_GL1_RANGE_GT16K_REQ = 0x0000004a,
19989GCR_PERF_SEL_CPF_GL1_ALL_REQ = 0x0000004b,
19990GCR_PERF_SEL_CPF_METADATA_REQ = 0x0000004c,
19991GCR_PERF_SEL_CPF_SQC_DATA_REQ = 0x0000004d,
19992GCR_PERF_SEL_CPF_SQC_INST_REQ = 0x0000004e,
19993GCR_PERF_SEL_CPF_TCP_REQ = 0x0000004f,
19994GCR_PERF_SEL_CPF_TCP_TLB_SHOOTDOWN_REQ = 0x00000050,
19995GCR_PERF_SEL_VIRT_REQ = 0x00000051,
19996GCR_PERF_SEL_PHY_REQ = 0x00000052,
19997GCR_PERF_SEL_TLB_SHOOTDOWN_HEAVY_REQ = 0x00000053,
19998GCR_PERF_SEL_TLB_SHOOTDOWN_LIGHT_REQ = 0x00000054,
19999GCR_PERF_SEL_ALL_REQ = 0x00000055,
20000GCR_PERF_SEL_CLK_FOR_PHY_OUTSTANDING_REQ = 0x00000056,
20001GCR_PERF_SEL_CLK_FOR_VIRT_OUTSTANDING_REQ = 0x00000057,
20002GCR_PERF_SEL_CLK_FOR_ALL_OUTSTANDING_REQ = 0x00000058,
20003GCR_PERF_SEL_UTCL2_REQ = 0x00000059,
20004GCR_PERF_SEL_UTCL2_RET = 0x0000005a,
20005GCR_PERF_SEL_UTCL2_OUT_OF_CREDIT_EVENT = 0x0000005b,
20006GCR_PERF_SEL_UTCL2_INFLIGHT_REQ = 0x0000005c,
20007GCR_PERF_SEL_UTCL2_FILTERED_RET = 0x0000005d,
20008} GCRPerfSel;
20009
20010/*******************************************************
20011 * UTCL1 Enums
20012 *******************************************************/
20013
20014/*
20015 * UTCL1PerfSel enum
20016 */
20017
20018typedef enum UTCL1PerfSel {
20019UTCL1_PERF_SEL_NONE = 0x00000000,
20020UTCL1_PERF_SEL_REQS = 0x00000001,
20021UTCL1_PERF_SEL_HITS = 0x00000002,
20022UTCL1_PERF_SEL_MISSES = 0x00000003,
20023UTCL1_PERF_SEL_BYPASS_REQS = 0x00000004,
20024UTCL1_PERF_SEL_HIT_INV_FILTER_REQS = 0x00000005,
20025UTCL1_PERF_SEL_NUM_SMALLK_PAGES = 0x00000006,
20026UTCL1_PERF_SEL_NUM_BIGK_PAGES = 0x00000007,
20027UTCL1_PERF_SEL_TOTAL_UTCL2_REQS = 0x00000008,
20028UTCL1_PERF_SEL_OUTSTANDING_UTCL2_REQS_ACCUM = 0x00000009,
20029UTCL1_PERF_SEL_STALL_ON_UTCL2_CREDITS = 0x0000000a,
20030UTCL1_PERF_SEL_STALL_MH_OFIFO_FULL = 0x0000000b,
20031UTCL1_PERF_SEL_STALL_MH_CAM_FULL = 0x0000000c,
20032UTCL1_PERF_SEL_NONRANGE_INV_REQS = 0x0000000d,
20033UTCL1_PERF_SEL_RANGE_INV_REQS = 0x0000000e,
20034} UTCL1PerfSel;
20035
20036/*******************************************************
20037 * SDMA Enums
20038 *******************************************************/
20039
20040/*
20041 * SDMA_PERF_SEL enum
20042 */
20043
20044typedef enum SDMA_PERF_SEL {
20045SDMA_PERF_SEL_CYCLE = 0x00000000,
20046SDMA_PERF_SEL_IDLE = 0x00000001,
20047SDMA_PERF_SEL_REG_IDLE = 0x00000002,
20048SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
20049SDMA_PERF_SEL_RB_FULL = 0x00000004,
20050SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
20051SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
20052SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
20053SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
20054SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
20055SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
20056SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
20057SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
20058SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
20059SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
20060SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
20061SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
20062SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
20063SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
20064SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
20065SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
20066SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
20067SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
20068SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
20069SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
20070SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
20071SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
20072SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
20073SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
20074SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
20075SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
20076SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
20077SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
20078SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
20079SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
20080SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
20081SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
20082SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
20083SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
20084SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
20085SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
20086SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
20087SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
20088SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
20089SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
20090SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
20091SDMA_PERF_SEL_GFX_SELECT = 0x00000035,
20092SDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
20093SDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
20094SDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
20095SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
20096SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
20097SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
20098SDMA_PERF_SEL_DOORBELL = 0x0000003c,
20099SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
20100SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
20101SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
20102SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
20103SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041,
20104SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042,
20105SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
20106SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044,
20107SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
20108SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
20109SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047,
20110SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048,
20111SDMA_PERF_SEL_UTCL2_FREE = 0x00000049,
20112SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a,
20113SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b,
20114SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c,
20115SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d,
20116SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e,
20117SDMA_PERF_SEL_GPUVM_INVREQ_HIGH = 0x0000004f,
20118SDMA_PERF_SEL_GPUVM_INVREQ_LOW = 0x00000050,
20119SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051,
20120SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052,
20121SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053,
20122SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054,
20123SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055,
20124SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056,
20125SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057,
20126SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058,
20127SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
20128SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
20129SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
20130SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
20131SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d,
20132SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e,
20133SDMA_PERF_SEL_TLBI_SEND = 0x0000005f,
20134SDMA_PERF_SEL_TLBI_RTN = 0x00000060,
20135SDMA_PERF_SEL_GCR_SEND = 0x00000061,
20136SDMA_PERF_SEL_GCR_RTN = 0x00000062,
20137SDMA_PERF_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063,
20138SDMA_PERF_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064,
20139} SDMA_PERF_SEL;
20140
20141/*******************************************************
20142 * ADDRLIB Enums
20143 *******************************************************/
20144
20145/*
20146 * NUM_PIPES_BC_ENUM enum
20147 */
20148
20149typedef enum NUM_PIPES_BC_ENUM {
20150ADDR_NUM_PIPES_BC_P8 = 0x00000000,
20151ADDR_NUM_PIPES_BC_P16 = 0x00000001,
20152} NUM_PIPES_BC_ENUM;
20153
20154/*
20155 * NUM_BANKS_BC_ENUM enum
20156 */
20157
20158typedef enum NUM_BANKS_BC_ENUM {
20159ADDR_NUM_BANKS_BC_BANKS_1 = 0x00000000,
20160ADDR_NUM_BANKS_BC_BANKS_2 = 0x00000001,
20161ADDR_NUM_BANKS_BC_BANKS_4 = 0x00000002,
20162ADDR_NUM_BANKS_BC_BANKS_8 = 0x00000003,
20163ADDR_NUM_BANKS_BC_BANKS_16 = 0x00000004,
20164} NUM_BANKS_BC_ENUM;
20165
20166/*
20167 * SWIZZLE_TYPE_ENUM enum
20168 */
20169
20170typedef enum SWIZZLE_TYPE_ENUM {
20171SW_Z = 0x00000000,
20172SW_S = 0x00000001,
20173SW_D = 0x00000002,
20174SW_R = 0x00000003,
20175SW_L = 0x00000004,
20176} SWIZZLE_TYPE_ENUM;
20177
20178/*
20179 * TC_MICRO_TILE_MODE enum
20180 */
20181
20182typedef enum TC_MICRO_TILE_MODE {
20183MICRO_TILE_MODE_LINEAR = 0x00000000,
20184MICRO_TILE_MODE_RENDER_TARGET = 0x00000001,
20185MICRO_TILE_MODE_STD_2D = 0x00000002,
20186MICRO_TILE_MODE_STD_3D = 0x00000003,
20187MICRO_TILE_MODE_DISPLAY_2D = 0x00000004,
20188MICRO_TILE_MODE_DISPLAY_3D = 0x00000005,
20189MICRO_TILE_MODE_Z = 0x00000006,
20190} TC_MICRO_TILE_MODE;
20191
20192/*
20193 * SWIZZLE_MODE_ENUM enum
20194 */
20195
20196typedef enum SWIZZLE_MODE_ENUM {
20197SW_LINEAR = 0x00000000,
20198SW_256B_S = 0x00000001,
20199SW_256B_D = 0x00000002,
20200SW_256B_R = 0x00000003,
20201SW_4KB_Z = 0x00000004,
20202SW_4KB_S = 0x00000005,
20203SW_4KB_D = 0x00000006,
20204SW_4KB_R = 0x00000007,
20205SW_64KB_Z = 0x00000008,
20206SW_64KB_S = 0x00000009,
20207SW_64KB_D = 0x0000000a,
20208SW_64KB_R = 0x0000000b,
20209SW_VAR_Z = 0x0000000c,
20210SW_VAR_S = 0x0000000d,
20211SW_VAR_D = 0x0000000e,
20212SW_VAR_R = 0x0000000f,
20213SW_64KB_Z_T = 0x00000010,
20214SW_64KB_S_T = 0x00000011,
20215SW_64KB_D_T = 0x00000012,
20216SW_64KB_R_T = 0x00000013,
20217SW_4KB_Z_X = 0x00000014,
20218SW_4KB_S_X = 0x00000015,
20219SW_4KB_D_X = 0x00000016,
20220SW_4KB_R_X = 0x00000017,
20221SW_64KB_Z_X = 0x00000018,
20222SW_64KB_S_X = 0x00000019,
20223SW_64KB_D_X = 0x0000001a,
20224SW_64KB_R_X = 0x0000001b,
20225SW_VAR_Z_X = 0x0000001c,
20226SW_VAR_S_X = 0x0000001d,
20227SW_VAR_D_X = 0x0000001e,
20228SW_VAR_R_X = 0x0000001f,
20229} SWIZZLE_MODE_ENUM;
20230
20231/*
20232 * SurfaceEndian enum
20233 */
20234
20235typedef enum SurfaceEndian {
20236ENDIAN_NONE = 0x00000000,
20237ENDIAN_8IN16 = 0x00000001,
20238ENDIAN_8IN32 = 0x00000002,
20239ENDIAN_8IN64 = 0x00000003,
20240} SurfaceEndian;
20241
20242/*
20243 * ArrayMode enum
20244 */
20245
20246typedef enum ArrayMode {
20247ARRAY_LINEAR_GENERAL = 0x00000000,
20248ARRAY_LINEAR_ALIGNED = 0x00000001,
20249ARRAY_1D_TILED_THIN1 = 0x00000002,
20250ARRAY_1D_TILED_THICK = 0x00000003,
20251ARRAY_2D_TILED_THIN1 = 0x00000004,
20252ARRAY_PRT_TILED_THIN1 = 0x00000005,
20253ARRAY_PRT_2D_TILED_THIN1 = 0x00000006,
20254ARRAY_2D_TILED_THICK = 0x00000007,
20255ARRAY_2D_TILED_XTHICK = 0x00000008,
20256ARRAY_PRT_TILED_THICK = 0x00000009,
20257ARRAY_PRT_2D_TILED_THICK = 0x0000000a,
20258ARRAY_PRT_3D_TILED_THIN1 = 0x0000000b,
20259ARRAY_3D_TILED_THIN1 = 0x0000000c,
20260ARRAY_3D_TILED_THICK = 0x0000000d,
20261ARRAY_3D_TILED_XTHICK = 0x0000000e,
20262ARRAY_PRT_3D_TILED_THICK = 0x0000000f,
20263} ArrayMode;
20264
20265/*
20266 * NumPipes enum
20267 */
20268
20269typedef enum NumPipes {
20270ADDR_CONFIG_1_PIPE = 0x00000000,
20271ADDR_CONFIG_2_PIPE = 0x00000001,
20272ADDR_CONFIG_4_PIPE = 0x00000002,
20273ADDR_CONFIG_8_PIPE = 0x00000003,
20274ADDR_CONFIG_16_PIPE = 0x00000004,
20275ADDR_CONFIG_32_PIPE = 0x00000005,
20276ADDR_CONFIG_64_PIPE = 0x00000006,
20277} NumPipes;
20278
20279/*
20280 * NumBanksConfig enum
20281 */
20282
20283typedef enum NumBanksConfig {
20284ADDR_CONFIG_1_BANK = 0x00000000,
20285ADDR_CONFIG_2_BANK = 0x00000001,
20286ADDR_CONFIG_4_BANK = 0x00000002,
20287ADDR_CONFIG_8_BANK = 0x00000003,
20288ADDR_CONFIG_16_BANK = 0x00000004,
20289} NumBanksConfig;
20290
20291/*
20292 * PipeInterleaveSize enum
20293 */
20294
20295typedef enum PipeInterleaveSize {
20296ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000,
20297ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001,
20298ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002,
20299ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003,
20300} PipeInterleaveSize;
20301
20302/*
20303 * BankInterleaveSize enum
20304 */
20305
20306typedef enum BankInterleaveSize {
20307ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000,
20308ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001,
20309ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002,
20310ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003,
20311} BankInterleaveSize;
20312
20313/*
20314 * NumShaderEngines enum
20315 */
20316
20317typedef enum NumShaderEngines {
20318ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000,
20319ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001,
20320ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002,
20321ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003,
20322} NumShaderEngines;
20323
20324/*
20325 * NumRbPerShaderEngine enum
20326 */
20327
20328typedef enum NumRbPerShaderEngine {
20329ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000,
20330ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001,
20331ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002,
20332} NumRbPerShaderEngine;
20333
20334/*
20335 * NumGPUs enum
20336 */
20337
20338typedef enum NumGPUs {
20339ADDR_CONFIG_1_GPU = 0x00000000,
20340ADDR_CONFIG_2_GPU = 0x00000001,
20341ADDR_CONFIG_4_GPU = 0x00000002,
20342ADDR_CONFIG_8_GPU = 0x00000003,
20343} NumGPUs;
20344
20345/*
20346 * NumMaxCompressedFragments enum
20347 */
20348
20349typedef enum NumMaxCompressedFragments {
20350ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000,
20351ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001,
20352ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002,
20353ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003,
20354} NumMaxCompressedFragments;
20355
20356/*
20357 * ShaderEngineTileSize enum
20358 */
20359
20360typedef enum ShaderEngineTileSize {
20361ADDR_CONFIG_SE_TILE_16 = 0x00000000,
20362ADDR_CONFIG_SE_TILE_32 = 0x00000001,
20363} ShaderEngineTileSize;
20364
20365/*
20366 * MultiGPUTileSize enum
20367 */
20368
20369typedef enum MultiGPUTileSize {
20370ADDR_CONFIG_GPU_TILE_16 = 0x00000000,
20371ADDR_CONFIG_GPU_TILE_32 = 0x00000001,
20372ADDR_CONFIG_GPU_TILE_64 = 0x00000002,
20373ADDR_CONFIG_GPU_TILE_128 = 0x00000003,
20374} MultiGPUTileSize;
20375
20376/*
20377 * RowSize enum
20378 */
20379
20380typedef enum RowSize {
20381ADDR_CONFIG_1KB_ROW = 0x00000000,
20382ADDR_CONFIG_2KB_ROW = 0x00000001,
20383ADDR_CONFIG_4KB_ROW = 0x00000002,
20384} RowSize;
20385
20386/*
20387 * NumLowerPipes enum
20388 */
20389
20390typedef enum NumLowerPipes {
20391ADDR_CONFIG_1_LOWER_PIPES = 0x00000000,
20392ADDR_CONFIG_2_LOWER_PIPES = 0x00000001,
20393} NumLowerPipes;
20394
20395/*
20396 * ColorTransform enum
20397 */
20398
20399typedef enum ColorTransform {
20400DCC_CT_AUTO = 0x00000000,
20401DCC_CT_NONE = 0x00000001,
20402ABGR_TO_A_BG_G_RB = 0x00000002,
20403BGRA_TO_BG_G_RB_A = 0x00000003,
20404} ColorTransform;
20405
20406/*
20407 * CompareRef enum
20408 */
20409
20410typedef enum CompareRef {
20411REF_NEVER = 0x00000000,
20412REF_LESS = 0x00000001,
20413REF_EQUAL = 0x00000002,
20414REF_LEQUAL = 0x00000003,
20415REF_GREATER = 0x00000004,
20416REF_NOTEQUAL = 0x00000005,
20417REF_GEQUAL = 0x00000006,
20418REF_ALWAYS = 0x00000007,
20419} CompareRef;
20420
20421/*
20422 * ReadSize enum
20423 */
20424
20425typedef enum ReadSize {
20426READ_256_BITS = 0x00000000,
20427READ_512_BITS = 0x00000001,
20428} ReadSize;
20429
20430/*
20431 * DepthFormat enum
20432 */
20433
20434typedef enum DepthFormat {
20435DEPTH_INVALID = 0x00000000,
20436DEPTH_16 = 0x00000001,
20437DEPTH_X8_24 = 0x00000002,
20438DEPTH_8_24 = 0x00000003,
20439DEPTH_X8_24_FLOAT = 0x00000004,
20440DEPTH_8_24_FLOAT = 0x00000005,
20441DEPTH_32_FLOAT = 0x00000006,
20442DEPTH_X24_8_32_FLOAT = 0x00000007,
20443} DepthFormat;
20444
20445/*
20446 * ZFormat enum
20447 */
20448
20449typedef enum ZFormat {
20450Z_INVALID = 0x00000000,
20451Z_16 = 0x00000001,
20452Z_24 = 0x00000002,
20453Z_32_FLOAT = 0x00000003,
20454} ZFormat;
20455
20456/*
20457 * StencilFormat enum
20458 */
20459
20460typedef enum StencilFormat {
20461STENCIL_INVALID = 0x00000000,
20462STENCIL_8 = 0x00000001,
20463} StencilFormat;
20464
20465/*
20466 * CmaskMode enum
20467 */
20468
20469typedef enum CmaskMode {
20470CMASK_CLEAR_NONE = 0x00000000,
20471CMASK_CLEAR_ONE = 0x00000001,
20472CMASK_CLEAR_ALL = 0x00000002,
20473CMASK_ANY_EXPANDED = 0x00000003,
20474CMASK_ALPHA0_FRAG1 = 0x00000004,
20475CMASK_ALPHA0_FRAG2 = 0x00000005,
20476CMASK_ALPHA0_FRAG4 = 0x00000006,
20477CMASK_ALPHA0_FRAGS = 0x00000007,
20478CMASK_ALPHA1_FRAG1 = 0x00000008,
20479CMASK_ALPHA1_FRAG2 = 0x00000009,
20480CMASK_ALPHA1_FRAG4 = 0x0000000a,
20481CMASK_ALPHA1_FRAGS = 0x0000000b,
20482CMASK_ALPHAX_FRAG1 = 0x0000000c,
20483CMASK_ALPHAX_FRAG2 = 0x0000000d,
20484CMASK_ALPHAX_FRAG4 = 0x0000000e,
20485CMASK_ALPHAX_FRAGS = 0x0000000f,
20486} CmaskMode;
20487
20488/*
20489 * QuadExportFormat enum
20490 */
20491
20492typedef enum QuadExportFormat {
20493EXPORT_UNUSED = 0x00000000,
20494EXPORT_32_R = 0x00000001,
20495EXPORT_32_GR = 0x00000002,
20496EXPORT_32_AR = 0x00000003,
20497EXPORT_FP16_ABGR = 0x00000004,
20498EXPORT_UNSIGNED16_ABGR = 0x00000005,
20499EXPORT_SIGNED16_ABGR = 0x00000006,
20500EXPORT_32_ABGR = 0x00000007,
20501EXPORT_32BPP_8PIX = 0x00000008,
20502EXPORT_16_16_UNSIGNED_8PIX = 0x00000009,
20503EXPORT_16_16_SIGNED_8PIX = 0x0000000a,
20504EXPORT_16_16_FLOAT_8PIX = 0x0000000b,
20505} QuadExportFormat;
20506
20507/*
20508 * QuadExportFormatOld enum
20509 */
20510
20511typedef enum QuadExportFormatOld {
20512EXPORT_4P_32BPC_ABGR = 0x00000000,
20513EXPORT_4P_16BPC_ABGR = 0x00000001,
20514EXPORT_4P_32BPC_GR = 0x00000002,
20515EXPORT_4P_32BPC_AR = 0x00000003,
20516EXPORT_2P_32BPC_ABGR = 0x00000004,
20517EXPORT_8P_32BPC_R = 0x00000005,
20518} QuadExportFormatOld;
20519
20520/*
20521 * ColorFormat enum
20522 */
20523
20524typedef enum ColorFormat {
20525COLOR_INVALID = 0x00000000,
20526COLOR_8 = 0x00000001,
20527COLOR_16 = 0x00000002,
20528COLOR_8_8 = 0x00000003,
20529COLOR_32 = 0x00000004,
20530COLOR_16_16 = 0x00000005,
20531COLOR_10_11_11 = 0x00000006,
20532COLOR_11_11_10 = 0x00000007,
20533COLOR_10_10_10_2 = 0x00000008,
20534COLOR_2_10_10_10 = 0x00000009,
20535COLOR_8_8_8_8 = 0x0000000a,
20536COLOR_32_32 = 0x0000000b,
20537COLOR_16_16_16_16 = 0x0000000c,
20538COLOR_RESERVED_13 = 0x0000000d,
20539COLOR_32_32_32_32 = 0x0000000e,
20540COLOR_RESERVED_15 = 0x0000000f,
20541COLOR_5_6_5 = 0x00000010,
20542COLOR_1_5_5_5 = 0x00000011,
20543COLOR_5_5_5_1 = 0x00000012,
20544COLOR_4_4_4_4 = 0x00000013,
20545COLOR_8_24 = 0x00000014,
20546COLOR_24_8 = 0x00000015,
20547COLOR_X24_8_32_FLOAT = 0x00000016,
20548COLOR_RESERVED_23 = 0x00000017,
20549COLOR_RESERVED_24 = 0x00000018,
20550COLOR_RESERVED_25 = 0x00000019,
20551COLOR_RESERVED_26 = 0x0000001a,
20552COLOR_RESERVED_27 = 0x0000001b,
20553COLOR_RESERVED_28 = 0x0000001c,
20554COLOR_RESERVED_29 = 0x0000001d,
20555COLOR_RESERVED_30 = 0x0000001e,
20556COLOR_2_10_10_10_6E4 = 0x0000001f,
20557} ColorFormat;
20558
20559/*
20560 * SurfaceFormat enum
20561 */
20562
20563typedef enum SurfaceFormat {
20564FMT_INVALID = 0x00000000,
20565FMT_8 = 0x00000001,
20566FMT_16 = 0x00000002,
20567FMT_8_8 = 0x00000003,
20568FMT_32 = 0x00000004,
20569FMT_16_16 = 0x00000005,
20570FMT_10_11_11 = 0x00000006,
20571FMT_11_11_10 = 0x00000007,
20572FMT_10_10_10_2 = 0x00000008,
20573FMT_2_10_10_10 = 0x00000009,
20574FMT_8_8_8_8 = 0x0000000a,
20575FMT_32_32 = 0x0000000b,
20576FMT_16_16_16_16 = 0x0000000c,
20577FMT_32_32_32 = 0x0000000d,
20578FMT_32_32_32_32 = 0x0000000e,
20579FMT_RESERVED_4 = 0x0000000f,
20580FMT_5_6_5 = 0x00000010,
20581FMT_1_5_5_5 = 0x00000011,
20582FMT_5_5_5_1 = 0x00000012,
20583FMT_4_4_4_4 = 0x00000013,
20584FMT_8_24 = 0x00000014,
20585FMT_24_8 = 0x00000015,
20586FMT_X24_8_32_FLOAT = 0x00000016,
20587FMT_RESERVED_33 = 0x00000017,
20588FMT_11_11_10_FLOAT = 0x00000018,
20589FMT_16_FLOAT = 0x00000019,
20590FMT_32_FLOAT = 0x0000001a,
20591FMT_16_16_FLOAT = 0x0000001b,
20592FMT_8_24_FLOAT = 0x0000001c,
20593FMT_24_8_FLOAT = 0x0000001d,
20594FMT_32_32_FLOAT = 0x0000001e,
20595FMT_10_11_11_FLOAT = 0x0000001f,
20596FMT_16_16_16_16_FLOAT = 0x00000020,
20597FMT_3_3_2 = 0x00000021,
20598FMT_6_5_5 = 0x00000022,
20599FMT_32_32_32_32_FLOAT = 0x00000023,
20600FMT_RESERVED_36 = 0x00000024,
20601FMT_1 = 0x00000025,
20602FMT_1_REVERSED = 0x00000026,
20603FMT_GB_GR = 0x00000027,
20604FMT_BG_RG = 0x00000028,
20605FMT_32_AS_8 = 0x00000029,
20606FMT_32_AS_8_8 = 0x0000002a,
20607FMT_5_9_9_9_SHAREDEXP = 0x0000002b,
20608FMT_8_8_8 = 0x0000002c,
20609FMT_16_16_16 = 0x0000002d,
20610FMT_16_16_16_FLOAT = 0x0000002e,
20611FMT_4_4 = 0x0000002f,
20612FMT_32_32_32_FLOAT = 0x00000030,
20613FMT_BC1 = 0x00000031,
20614FMT_BC2 = 0x00000032,
20615FMT_BC3 = 0x00000033,
20616FMT_BC4 = 0x00000034,
20617FMT_BC5 = 0x00000035,
20618FMT_BC6 = 0x00000036,
20619FMT_BC7 = 0x00000037,
20620FMT_32_AS_32_32_32_32 = 0x00000038,
20621FMT_APC3 = 0x00000039,
20622FMT_APC4 = 0x0000003a,
20623FMT_APC5 = 0x0000003b,
20624FMT_APC6 = 0x0000003c,
20625FMT_APC7 = 0x0000003d,
20626FMT_CTX1 = 0x0000003e,
20627FMT_RESERVED_63 = 0x0000003f,
20628} SurfaceFormat;
20629
20630/*
20631 * IMG_NUM_FORMAT_FMASK enum
20632 */
20633
20634typedef enum IMG_NUM_FORMAT_FMASK {
20635IMG_NUM_FORMAT_FMASK_8_2_1 = 0x00000000,
20636IMG_NUM_FORMAT_FMASK_8_4_1 = 0x00000001,
20637IMG_NUM_FORMAT_FMASK_8_8_1 = 0x00000002,
20638IMG_NUM_FORMAT_FMASK_8_2_2 = 0x00000003,
20639IMG_NUM_FORMAT_FMASK_8_4_2 = 0x00000004,
20640IMG_NUM_FORMAT_FMASK_8_4_4 = 0x00000005,
20641IMG_NUM_FORMAT_FMASK_16_16_1 = 0x00000006,
20642IMG_NUM_FORMAT_FMASK_16_8_2 = 0x00000007,
20643IMG_NUM_FORMAT_FMASK_32_16_2 = 0x00000008,
20644IMG_NUM_FORMAT_FMASK_32_8_4 = 0x00000009,
20645IMG_NUM_FORMAT_FMASK_32_8_8 = 0x0000000a,
20646IMG_NUM_FORMAT_FMASK_64_16_4 = 0x0000000b,
20647IMG_NUM_FORMAT_FMASK_64_16_8 = 0x0000000c,
20648IMG_NUM_FORMAT_FMASK_RESERVED_13 = 0x0000000d,
20649IMG_NUM_FORMAT_FMASK_RESERVED_14 = 0x0000000e,
20650IMG_NUM_FORMAT_FMASK_RESERVED_15 = 0x0000000f,
20651} IMG_NUM_FORMAT_FMASK;
20652
20653/*
20654 * IMG_NUM_FORMAT_N_IN_16 enum
20655 */
20656
20657typedef enum IMG_NUM_FORMAT_N_IN_16 {
20658IMG_NUM_FORMAT_N_IN_16_RESERVED_0 = 0x00000000,
20659IMG_NUM_FORMAT_N_IN_16_UNORM_10 = 0x00000001,
20660IMG_NUM_FORMAT_N_IN_16_UNORM_9 = 0x00000002,
20661IMG_NUM_FORMAT_N_IN_16_RESERVED_3 = 0x00000003,
20662IMG_NUM_FORMAT_N_IN_16_UINT_10 = 0x00000004,
20663IMG_NUM_FORMAT_N_IN_16_UINT_9 = 0x00000005,
20664IMG_NUM_FORMAT_N_IN_16_RESERVED_6 = 0x00000006,
20665IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_10 = 0x00000007,
20666IMG_NUM_FORMAT_N_IN_16_UNORM_UINT_9 = 0x00000008,
20667IMG_NUM_FORMAT_N_IN_16_RESERVED_9 = 0x00000009,
20668IMG_NUM_FORMAT_N_IN_16_RESERVED_10 = 0x0000000a,
20669IMG_NUM_FORMAT_N_IN_16_RESERVED_11 = 0x0000000b,
20670IMG_NUM_FORMAT_N_IN_16_RESERVED_12 = 0x0000000c,
20671IMG_NUM_FORMAT_N_IN_16_RESERVED_13 = 0x0000000d,
20672IMG_NUM_FORMAT_N_IN_16_RESERVED_14 = 0x0000000e,
20673IMG_NUM_FORMAT_N_IN_16_RESERVED_15 = 0x0000000f,
20674} IMG_NUM_FORMAT_N_IN_16;
20675
20676/*
20677 * TileType enum
20678 */
20679
20680typedef enum TileType {
20681ARRAY_COLOR_TILE = 0x00000000,
20682ARRAY_DEPTH_TILE = 0x00000001,
20683} TileType;
20684
20685/*
20686 * NonDispTilingOrder enum
20687 */
20688
20689typedef enum NonDispTilingOrder {
20690ADDR_SURF_MICRO_TILING_DISPLAY = 0x00000000,
20691ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x00000001,
20692} NonDispTilingOrder;
20693
20694/*
20695 * MicroTileMode enum
20696 */
20697
20698typedef enum MicroTileMode {
20699ADDR_SURF_DISPLAY_MICRO_TILING = 0x00000000,
20700ADDR_SURF_THIN_MICRO_TILING = 0x00000001,
20701ADDR_SURF_DEPTH_MICRO_TILING = 0x00000002,
20702ADDR_SURF_ROTATED_MICRO_TILING = 0x00000003,
20703ADDR_SURF_THICK_MICRO_TILING = 0x00000004,
20704} MicroTileMode;
20705
20706/*
20707 * TileSplit enum
20708 */
20709
20710typedef enum TileSplit {
20711ADDR_SURF_TILE_SPLIT_64B = 0x00000000,
20712ADDR_SURF_TILE_SPLIT_128B = 0x00000001,
20713ADDR_SURF_TILE_SPLIT_256B = 0x00000002,
20714ADDR_SURF_TILE_SPLIT_512B = 0x00000003,
20715ADDR_SURF_TILE_SPLIT_1KB = 0x00000004,
20716ADDR_SURF_TILE_SPLIT_2KB = 0x00000005,
20717ADDR_SURF_TILE_SPLIT_4KB = 0x00000006,
20718} TileSplit;
20719
20720/*
20721 * SampleSplit enum
20722 */
20723
20724typedef enum SampleSplit {
20725ADDR_SURF_SAMPLE_SPLIT_1 = 0x00000000,
20726ADDR_SURF_SAMPLE_SPLIT_2 = 0x00000001,
20727ADDR_SURF_SAMPLE_SPLIT_4 = 0x00000002,
20728ADDR_SURF_SAMPLE_SPLIT_8 = 0x00000003,
20729} SampleSplit;
20730
20731/*
20732 * PipeConfig enum
20733 */
20734
20735typedef enum PipeConfig {
20736ADDR_SURF_P2 = 0x00000000,
20737ADDR_SURF_P2_RESERVED0 = 0x00000001,
20738ADDR_SURF_P2_RESERVED1 = 0x00000002,
20739ADDR_SURF_P2_RESERVED2 = 0x00000003,
20740ADDR_SURF_P4_8x16 = 0x00000004,
20741ADDR_SURF_P4_16x16 = 0x00000005,
20742ADDR_SURF_P4_16x32 = 0x00000006,
20743ADDR_SURF_P4_32x32 = 0x00000007,
20744ADDR_SURF_P8_16x16_8x16 = 0x00000008,
20745ADDR_SURF_P8_16x32_8x16 = 0x00000009,
20746ADDR_SURF_P8_32x32_8x16 = 0x0000000a,
20747ADDR_SURF_P8_16x32_16x16 = 0x0000000b,
20748ADDR_SURF_P8_32x32_16x16 = 0x0000000c,
20749ADDR_SURF_P8_32x32_16x32 = 0x0000000d,
20750ADDR_SURF_P8_32x64_32x32 = 0x0000000e,
20751ADDR_SURF_P8_RESERVED0 = 0x0000000f,
20752ADDR_SURF_P16_32x32_8x16 = 0x00000010,
20753ADDR_SURF_P16_32x32_16x16 = 0x00000011,
20754ADDR_SURF_P16 = 0x00000012,
20755} PipeConfig;
20756
20757/*
20758 * SeEnable enum
20759 */
20760
20761typedef enum SeEnable {
20762ADDR_CONFIG_DISABLE_SE = 0x00000000,
20763ADDR_CONFIG_ENABLE_SE = 0x00000001,
20764} SeEnable;
20765
20766/*
20767 * NumBanks enum
20768 */
20769
20770typedef enum NumBanks {
20771ADDR_SURF_2_BANK = 0x00000000,
20772ADDR_SURF_4_BANK = 0x00000001,
20773ADDR_SURF_8_BANK = 0x00000002,
20774ADDR_SURF_16_BANK = 0x00000003,
20775} NumBanks;
20776
20777/*
20778 * BankWidth enum
20779 */
20780
20781typedef enum BankWidth {
20782ADDR_SURF_BANK_WIDTH_1 = 0x00000000,
20783ADDR_SURF_BANK_WIDTH_2 = 0x00000001,
20784ADDR_SURF_BANK_WIDTH_4 = 0x00000002,
20785ADDR_SURF_BANK_WIDTH_8 = 0x00000003,
20786} BankWidth;
20787
20788/*
20789 * BankHeight enum
20790 */
20791
20792typedef enum BankHeight {
20793ADDR_SURF_BANK_HEIGHT_1 = 0x00000000,
20794ADDR_SURF_BANK_HEIGHT_2 = 0x00000001,
20795ADDR_SURF_BANK_HEIGHT_4 = 0x00000002,
20796ADDR_SURF_BANK_HEIGHT_8 = 0x00000003,
20797} BankHeight;
20798
20799/*
20800 * BankWidthHeight enum
20801 */
20802
20803typedef enum BankWidthHeight {
20804ADDR_SURF_BANK_WH_1 = 0x00000000,
20805ADDR_SURF_BANK_WH_2 = 0x00000001,
20806ADDR_SURF_BANK_WH_4 = 0x00000002,
20807ADDR_SURF_BANK_WH_8 = 0x00000003,
20808} BankWidthHeight;
20809
20810/*
20811 * MacroTileAspect enum
20812 */
20813
20814typedef enum MacroTileAspect {
20815ADDR_SURF_MACRO_ASPECT_1 = 0x00000000,
20816ADDR_SURF_MACRO_ASPECT_2 = 0x00000001,
20817ADDR_SURF_MACRO_ASPECT_4 = 0x00000002,
20818ADDR_SURF_MACRO_ASPECT_8 = 0x00000003,
20819} MacroTileAspect;
20820
20821/*
20822 * PipeTiling enum
20823 */
20824
20825typedef enum PipeTiling {
20826CONFIG_1_PIPE = 0x00000000,
20827CONFIG_2_PIPE = 0x00000001,
20828CONFIG_4_PIPE = 0x00000002,
20829CONFIG_8_PIPE = 0x00000003,
20830} PipeTiling;
20831
20832/*
20833 * BankTiling enum
20834 */
20835
20836typedef enum BankTiling {
20837CONFIG_4_BANK = 0x00000000,
20838CONFIG_8_BANK = 0x00000001,
20839} BankTiling;
20840
20841/*
20842 * GroupInterleave enum
20843 */
20844
20845typedef enum GroupInterleave {
20846CONFIG_256B_GROUP = 0x00000000,
20847CONFIG_512B_GROUP = 0x00000001,
20848} GroupInterleave;
20849
20850/*
20851 * RowTiling enum
20852 */
20853
20854typedef enum RowTiling {
20855CONFIG_1KB_ROW = 0x00000000,
20856CONFIG_2KB_ROW = 0x00000001,
20857CONFIG_4KB_ROW = 0x00000002,
20858CONFIG_8KB_ROW = 0x00000003,
20859CONFIG_1KB_ROW_OPT = 0x00000004,
20860CONFIG_2KB_ROW_OPT = 0x00000005,
20861CONFIG_4KB_ROW_OPT = 0x00000006,
20862CONFIG_8KB_ROW_OPT = 0x00000007,
20863} RowTiling;
20864
20865/*
20866 * BankSwapBytes enum
20867 */
20868
20869typedef enum BankSwapBytes {
20870CONFIG_128B_SWAPS = 0x00000000,
20871CONFIG_256B_SWAPS = 0x00000001,
20872CONFIG_512B_SWAPS = 0x00000002,
20873CONFIG_1KB_SWAPS = 0x00000003,
20874} BankSwapBytes;
20875
20876/*
20877 * SampleSplitBytes enum
20878 */
20879
20880typedef enum SampleSplitBytes {
20881CONFIG_1KB_SPLIT = 0x00000000,
20882CONFIG_2KB_SPLIT = 0x00000001,
20883CONFIG_4KB_SPLIT = 0x00000002,
20884CONFIG_8KB_SPLIT = 0x00000003,
20885} SampleSplitBytes;
20886
20887/*
20888 * SurfaceNumber enum
20889 */
20890
20891typedef enum SurfaceNumber {
20892NUMBER_UNORM = 0x00000000,
20893NUMBER_SNORM = 0x00000001,
20894NUMBER_USCALED = 0x00000002,
20895NUMBER_SSCALED = 0x00000003,
20896NUMBER_UINT = 0x00000004,
20897NUMBER_SINT = 0x00000005,
20898NUMBER_SRGB = 0x00000006,
20899NUMBER_FLOAT = 0x00000007,
20900} SurfaceNumber;
20901
20902/*
20903 * SurfaceSwap enum
20904 */
20905
20906typedef enum SurfaceSwap {
20907SWAP_STD = 0x00000000,
20908SWAP_ALT = 0x00000001,
20909SWAP_STD_REV = 0x00000002,
20910SWAP_ALT_REV = 0x00000003,
20911} SurfaceSwap;
20912
20913/*
20914 * RoundMode enum
20915 */
20916
20917typedef enum RoundMode {
20918ROUND_BY_HALF = 0x00000000,
20919ROUND_TRUNCATE = 0x00000001,
20920} RoundMode;
20921
20922/*
20923 * BUF_FMT enum
20924 */
20925
20926typedef enum BUF_FMT {
20927BUF_FMT_INVALID = 0x00000000,
20928BUF_FMT_8_UNORM = 0x00000001,
20929BUF_FMT_8_SNORM = 0x00000002,
20930BUF_FMT_8_USCALED = 0x00000003,
20931BUF_FMT_8_SSCALED = 0x00000004,
20932BUF_FMT_8_UINT = 0x00000005,
20933BUF_FMT_8_SINT = 0x00000006,
20934BUF_FMT_16_UNORM = 0x00000007,
20935BUF_FMT_16_SNORM = 0x00000008,
20936BUF_FMT_16_USCALED = 0x00000009,
20937BUF_FMT_16_SSCALED = 0x0000000a,
20938BUF_FMT_16_UINT = 0x0000000b,
20939BUF_FMT_16_SINT = 0x0000000c,
20940BUF_FMT_16_FLOAT = 0x0000000d,
20941BUF_FMT_8_8_UNORM = 0x0000000e,
20942BUF_FMT_8_8_SNORM = 0x0000000f,
20943BUF_FMT_8_8_USCALED = 0x00000010,
20944BUF_FMT_8_8_SSCALED = 0x00000011,
20945BUF_FMT_8_8_UINT = 0x00000012,
20946BUF_FMT_8_8_SINT = 0x00000013,
20947BUF_FMT_32_UINT = 0x00000014,
20948BUF_FMT_32_SINT = 0x00000015,
20949BUF_FMT_32_FLOAT = 0x00000016,
20950BUF_FMT_16_16_UNORM = 0x00000017,
20951BUF_FMT_16_16_SNORM = 0x00000018,
20952BUF_FMT_16_16_USCALED = 0x00000019,
20953BUF_FMT_16_16_SSCALED = 0x0000001a,
20954BUF_FMT_16_16_UINT = 0x0000001b,
20955BUF_FMT_16_16_SINT = 0x0000001c,
20956BUF_FMT_16_16_FLOAT = 0x0000001d,
20957BUF_FMT_10_11_11_UNORM = 0x0000001e,
20958BUF_FMT_10_11_11_SNORM = 0x0000001f,
20959BUF_FMT_10_11_11_USCALED = 0x00000020,
20960BUF_FMT_10_11_11_SSCALED = 0x00000021,
20961BUF_FMT_10_11_11_UINT = 0x00000022,
20962BUF_FMT_10_11_11_SINT = 0x00000023,
20963BUF_FMT_10_11_11_FLOAT = 0x00000024,
20964BUF_FMT_11_11_10_UNORM = 0x00000025,
20965BUF_FMT_11_11_10_SNORM = 0x00000026,
20966BUF_FMT_11_11_10_USCALED = 0x00000027,
20967BUF_FMT_11_11_10_SSCALED = 0x00000028,
20968BUF_FMT_11_11_10_UINT = 0x00000029,
20969BUF_FMT_11_11_10_SINT = 0x0000002a,
20970BUF_FMT_11_11_10_FLOAT = 0x0000002b,
20971BUF_FMT_10_10_10_2_UNORM = 0x0000002c,
20972BUF_FMT_10_10_10_2_SNORM = 0x0000002d,
20973BUF_FMT_10_10_10_2_USCALED = 0x0000002e,
20974BUF_FMT_10_10_10_2_SSCALED = 0x0000002f,
20975BUF_FMT_10_10_10_2_UINT = 0x00000030,
20976BUF_FMT_10_10_10_2_SINT = 0x00000031,
20977BUF_FMT_2_10_10_10_UNORM = 0x00000032,
20978BUF_FMT_2_10_10_10_SNORM = 0x00000033,
20979BUF_FMT_2_10_10_10_USCALED = 0x00000034,
20980BUF_FMT_2_10_10_10_SSCALED = 0x00000035,
20981BUF_FMT_2_10_10_10_UINT = 0x00000036,
20982BUF_FMT_2_10_10_10_SINT = 0x00000037,
20983BUF_FMT_8_8_8_8_UNORM = 0x00000038,
20984BUF_FMT_8_8_8_8_SNORM = 0x00000039,
20985BUF_FMT_8_8_8_8_USCALED = 0x0000003a,
20986BUF_FMT_8_8_8_8_SSCALED = 0x0000003b,
20987BUF_FMT_8_8_8_8_UINT = 0x0000003c,
20988BUF_FMT_8_8_8_8_SINT = 0x0000003d,
20989BUF_FMT_32_32_UINT = 0x0000003e,
20990BUF_FMT_32_32_SINT = 0x0000003f,
20991BUF_FMT_32_32_FLOAT = 0x00000040,
20992BUF_FMT_16_16_16_16_UNORM = 0x00000041,
20993BUF_FMT_16_16_16_16_SNORM = 0x00000042,
20994BUF_FMT_16_16_16_16_USCALED = 0x00000043,
20995BUF_FMT_16_16_16_16_SSCALED = 0x00000044,
20996BUF_FMT_16_16_16_16_UINT = 0x00000045,
20997BUF_FMT_16_16_16_16_SINT = 0x00000046,
20998BUF_FMT_16_16_16_16_FLOAT = 0x00000047,
20999BUF_FMT_32_32_32_UINT = 0x00000048,
21000BUF_FMT_32_32_32_SINT = 0x00000049,
21001BUF_FMT_32_32_32_FLOAT = 0x0000004a,
21002BUF_FMT_32_32_32_32_UINT = 0x0000004b,
21003BUF_FMT_32_32_32_32_SINT = 0x0000004c,
21004BUF_FMT_32_32_32_32_FLOAT = 0x0000004d,
21005BUF_FMT_RESERVED_78 = 0x0000004e,
21006BUF_FMT_RESERVED_79 = 0x0000004f,
21007BUF_FMT_RESERVED_80 = 0x00000050,
21008BUF_FMT_RESERVED_81 = 0x00000051,
21009BUF_FMT_RESERVED_82 = 0x00000052,
21010BUF_FMT_RESERVED_83 = 0x00000053,
21011BUF_FMT_RESERVED_84 = 0x00000054,
21012BUF_FMT_RESERVED_85 = 0x00000055,
21013BUF_FMT_RESERVED_86 = 0x00000056,
21014BUF_FMT_RESERVED_87 = 0x00000057,
21015BUF_FMT_RESERVED_88 = 0x00000058,
21016BUF_FMT_RESERVED_89 = 0x00000059,
21017BUF_FMT_RESERVED_90 = 0x0000005a,
21018BUF_FMT_RESERVED_91 = 0x0000005b,
21019BUF_FMT_RESERVED_92 = 0x0000005c,
21020BUF_FMT_RESERVED_93 = 0x0000005d,
21021BUF_FMT_RESERVED_94 = 0x0000005e,
21022BUF_FMT_RESERVED_95 = 0x0000005f,
21023BUF_FMT_RESERVED_96 = 0x00000060,
21024BUF_FMT_RESERVED_97 = 0x00000061,
21025BUF_FMT_RESERVED_98 = 0x00000062,
21026BUF_FMT_RESERVED_99 = 0x00000063,
21027BUF_FMT_RESERVED_100 = 0x00000064,
21028BUF_FMT_RESERVED_101 = 0x00000065,
21029BUF_FMT_RESERVED_102 = 0x00000066,
21030BUF_FMT_RESERVED_103 = 0x00000067,
21031BUF_FMT_RESERVED_104 = 0x00000068,
21032BUF_FMT_RESERVED_105 = 0x00000069,
21033BUF_FMT_RESERVED_106 = 0x0000006a,
21034BUF_FMT_RESERVED_107 = 0x0000006b,
21035BUF_FMT_RESERVED_108 = 0x0000006c,
21036BUF_FMT_RESERVED_109 = 0x0000006d,
21037BUF_FMT_RESERVED_110 = 0x0000006e,
21038BUF_FMT_RESERVED_111 = 0x0000006f,
21039BUF_FMT_RESERVED_112 = 0x00000070,
21040BUF_FMT_RESERVED_113 = 0x00000071,
21041BUF_FMT_RESERVED_114 = 0x00000072,
21042BUF_FMT_RESERVED_115 = 0x00000073,
21043BUF_FMT_RESERVED_116 = 0x00000074,
21044BUF_FMT_RESERVED_117 = 0x00000075,
21045BUF_FMT_RESERVED_118 = 0x00000076,
21046BUF_FMT_RESERVED_119 = 0x00000077,
21047BUF_FMT_RESERVED_120 = 0x00000078,
21048BUF_FMT_RESERVED_121 = 0x00000079,
21049BUF_FMT_RESERVED_122 = 0x0000007a,
21050BUF_FMT_RESERVED_123 = 0x0000007b,
21051BUF_FMT_RESERVED_124 = 0x0000007c,
21052BUF_FMT_RESERVED_125 = 0x0000007d,
21053BUF_FMT_RESERVED_126 = 0x0000007e,
21054BUF_FMT_RESERVED_127 = 0x0000007f,
21055} BUF_FMT;
21056
21057/*
21058 * IMG_FMT enum
21059 */
21060
21061typedef enum IMG_FMT {
21062IMG_FMT_INVALID = 0x00000000,
21063IMG_FMT_8_UNORM = 0x00000001,
21064IMG_FMT_8_SNORM = 0x00000002,
21065IMG_FMT_8_USCALED = 0x00000003,
21066IMG_FMT_8_SSCALED = 0x00000004,
21067IMG_FMT_8_UINT = 0x00000005,
21068IMG_FMT_8_SINT = 0x00000006,
21069IMG_FMT_16_UNORM = 0x00000007,
21070IMG_FMT_16_SNORM = 0x00000008,
21071IMG_FMT_16_USCALED = 0x00000009,
21072IMG_FMT_16_SSCALED = 0x0000000a,
21073IMG_FMT_16_UINT = 0x0000000b,
21074IMG_FMT_16_SINT = 0x0000000c,
21075IMG_FMT_16_FLOAT = 0x0000000d,
21076IMG_FMT_8_8_UNORM = 0x0000000e,
21077IMG_FMT_8_8_SNORM = 0x0000000f,
21078IMG_FMT_8_8_USCALED = 0x00000010,
21079IMG_FMT_8_8_SSCALED = 0x00000011,
21080IMG_FMT_8_8_UINT = 0x00000012,
21081IMG_FMT_8_8_SINT = 0x00000013,
21082IMG_FMT_32_UINT = 0x00000014,
21083IMG_FMT_32_SINT = 0x00000015,
21084IMG_FMT_32_FLOAT = 0x00000016,
21085IMG_FMT_16_16_UNORM = 0x00000017,
21086IMG_FMT_16_16_SNORM = 0x00000018,
21087IMG_FMT_16_16_USCALED = 0x00000019,
21088IMG_FMT_16_16_SSCALED = 0x0000001a,
21089IMG_FMT_16_16_UINT = 0x0000001b,
21090IMG_FMT_16_16_SINT = 0x0000001c,
21091IMG_FMT_16_16_FLOAT = 0x0000001d,
21092IMG_FMT_10_11_11_UNORM = 0x0000001e,
21093IMG_FMT_10_11_11_SNORM = 0x0000001f,
21094IMG_FMT_10_11_11_USCALED = 0x00000020,
21095IMG_FMT_10_11_11_SSCALED = 0x00000021,
21096IMG_FMT_10_11_11_UINT = 0x00000022,
21097IMG_FMT_10_11_11_SINT = 0x00000023,
21098IMG_FMT_10_11_11_FLOAT = 0x00000024,
21099IMG_FMT_11_11_10_UNORM = 0x00000025,
21100IMG_FMT_11_11_10_SNORM = 0x00000026,
21101IMG_FMT_11_11_10_USCALED = 0x00000027,
21102IMG_FMT_11_11_10_SSCALED = 0x00000028,
21103IMG_FMT_11_11_10_UINT = 0x00000029,
21104IMG_FMT_11_11_10_SINT = 0x0000002a,
21105IMG_FMT_11_11_10_FLOAT = 0x0000002b,
21106IMG_FMT_10_10_10_2_UNORM = 0x0000002c,
21107IMG_FMT_10_10_10_2_SNORM = 0x0000002d,
21108IMG_FMT_10_10_10_2_USCALED = 0x0000002e,
21109IMG_FMT_10_10_10_2_SSCALED = 0x0000002f,
21110IMG_FMT_10_10_10_2_UINT = 0x00000030,
21111IMG_FMT_10_10_10_2_SINT = 0x00000031,
21112IMG_FMT_2_10_10_10_UNORM = 0x00000032,
21113IMG_FMT_2_10_10_10_SNORM = 0x00000033,
21114IMG_FMT_2_10_10_10_USCALED = 0x00000034,
21115IMG_FMT_2_10_10_10_SSCALED = 0x00000035,
21116IMG_FMT_2_10_10_10_UINT = 0x00000036,
21117IMG_FMT_2_10_10_10_SINT = 0x00000037,
21118IMG_FMT_8_8_8_8_UNORM = 0x00000038,
21119IMG_FMT_8_8_8_8_SNORM = 0x00000039,
21120IMG_FMT_8_8_8_8_USCALED = 0x0000003a,
21121IMG_FMT_8_8_8_8_SSCALED = 0x0000003b,
21122IMG_FMT_8_8_8_8_UINT = 0x0000003c,
21123IMG_FMT_8_8_8_8_SINT = 0x0000003d,
21124IMG_FMT_32_32_UINT = 0x0000003e,
21125IMG_FMT_32_32_SINT = 0x0000003f,
21126IMG_FMT_32_32_FLOAT = 0x00000040,
21127IMG_FMT_16_16_16_16_UNORM = 0x00000041,
21128IMG_FMT_16_16_16_16_SNORM = 0x00000042,
21129IMG_FMT_16_16_16_16_USCALED = 0x00000043,
21130IMG_FMT_16_16_16_16_SSCALED = 0x00000044,
21131IMG_FMT_16_16_16_16_UINT = 0x00000045,
21132IMG_FMT_16_16_16_16_SINT = 0x00000046,
21133IMG_FMT_16_16_16_16_FLOAT = 0x00000047,
21134IMG_FMT_32_32_32_UINT = 0x00000048,
21135IMG_FMT_32_32_32_SINT = 0x00000049,
21136IMG_FMT_32_32_32_FLOAT = 0x0000004a,
21137IMG_FMT_32_32_32_32_UINT = 0x0000004b,
21138IMG_FMT_32_32_32_32_SINT = 0x0000004c,
21139IMG_FMT_32_32_32_32_FLOAT = 0x0000004d,
21140IMG_FMT_RESERVED_78 = 0x0000004e,
21141IMG_FMT_RESERVED_79 = 0x0000004f,
21142IMG_FMT_RESERVED_80 = 0x00000050,
21143IMG_FMT_RESERVED_81 = 0x00000051,
21144IMG_FMT_RESERVED_82 = 0x00000052,
21145IMG_FMT_RESERVED_83 = 0x00000053,
21146IMG_FMT_RESERVED_84 = 0x00000054,
21147IMG_FMT_RESERVED_85 = 0x00000055,
21148IMG_FMT_RESERVED_86 = 0x00000056,
21149IMG_FMT_RESERVED_87 = 0x00000057,
21150IMG_FMT_RESERVED_88 = 0x00000058,
21151IMG_FMT_RESERVED_89 = 0x00000059,
21152IMG_FMT_RESERVED_90 = 0x0000005a,
21153IMG_FMT_RESERVED_91 = 0x0000005b,
21154IMG_FMT_RESERVED_92 = 0x0000005c,
21155IMG_FMT_RESERVED_93 = 0x0000005d,
21156IMG_FMT_RESERVED_94 = 0x0000005e,
21157IMG_FMT_RESERVED_95 = 0x0000005f,
21158IMG_FMT_RESERVED_96 = 0x00000060,
21159IMG_FMT_RESERVED_97 = 0x00000061,
21160IMG_FMT_RESERVED_98 = 0x00000062,
21161IMG_FMT_RESERVED_99 = 0x00000063,
21162IMG_FMT_RESERVED_100 = 0x00000064,
21163IMG_FMT_RESERVED_101 = 0x00000065,
21164IMG_FMT_RESERVED_102 = 0x00000066,
21165IMG_FMT_RESERVED_103 = 0x00000067,
21166IMG_FMT_RESERVED_104 = 0x00000068,
21167IMG_FMT_RESERVED_105 = 0x00000069,
21168IMG_FMT_RESERVED_106 = 0x0000006a,
21169IMG_FMT_RESERVED_107 = 0x0000006b,
21170IMG_FMT_RESERVED_108 = 0x0000006c,
21171IMG_FMT_RESERVED_109 = 0x0000006d,
21172IMG_FMT_RESERVED_110 = 0x0000006e,
21173IMG_FMT_RESERVED_111 = 0x0000006f,
21174IMG_FMT_RESERVED_112 = 0x00000070,
21175IMG_FMT_RESERVED_113 = 0x00000071,
21176IMG_FMT_RESERVED_114 = 0x00000072,
21177IMG_FMT_RESERVED_115 = 0x00000073,
21178IMG_FMT_RESERVED_116 = 0x00000074,
21179IMG_FMT_RESERVED_117 = 0x00000075,
21180IMG_FMT_RESERVED_118 = 0x00000076,
21181IMG_FMT_RESERVED_119 = 0x00000077,
21182IMG_FMT_RESERVED_120 = 0x00000078,
21183IMG_FMT_RESERVED_121 = 0x00000079,
21184IMG_FMT_RESERVED_122 = 0x0000007a,
21185IMG_FMT_RESERVED_123 = 0x0000007b,
21186IMG_FMT_RESERVED_124 = 0x0000007c,
21187IMG_FMT_RESERVED_125 = 0x0000007d,
21188IMG_FMT_RESERVED_126 = 0x0000007e,
21189IMG_FMT_RESERVED_127 = 0x0000007f,
21190IMG_FMT_8_SRGB = 0x00000080,
21191IMG_FMT_8_8_SRGB = 0x00000081,
21192IMG_FMT_8_8_8_8_SRGB = 0x00000082,
21193IMG_FMT_6E4_FLOAT = 0x00000083,
21194IMG_FMT_5_9_9_9_FLOAT = 0x00000084,
21195IMG_FMT_5_6_5_UNORM = 0x00000085,
21196IMG_FMT_1_5_5_5_UNORM = 0x00000086,
21197IMG_FMT_5_5_5_1_UNORM = 0x00000087,
21198IMG_FMT_4_4_4_4_UNORM = 0x00000088,
21199IMG_FMT_4_4_UNORM = 0x00000089,
21200IMG_FMT_1_UNORM = 0x0000008a,
21201IMG_FMT_1_REVERSED_UNORM = 0x0000008b,
21202IMG_FMT_32_FLOAT_CLAMP = 0x0000008c,
21203IMG_FMT_8_24_UNORM = 0x0000008d,
21204IMG_FMT_8_24_UINT = 0x0000008e,
21205IMG_FMT_24_8_UNORM = 0x0000008f,
21206IMG_FMT_24_8_UINT = 0x00000090,
21207IMG_FMT_X24_8_32_UINT = 0x00000091,
21208IMG_FMT_X24_8_32_FLOAT = 0x00000092,
21209IMG_FMT_GB_GR_UNORM = 0x00000093,
21210IMG_FMT_GB_GR_SNORM = 0x00000094,
21211IMG_FMT_GB_GR_UINT = 0x00000095,
21212IMG_FMT_GB_GR_SRGB = 0x00000096,
21213IMG_FMT_BG_RG_UNORM = 0x00000097,
21214IMG_FMT_BG_RG_SNORM = 0x00000098,
21215IMG_FMT_BG_RG_UINT = 0x00000099,
21216IMG_FMT_BG_RG_SRGB = 0x0000009a,
21217IMG_FMT_RESERVED_155 = 0x0000009b,
21218IMG_FMT_FMASK8_S2_F1 = 0x0000009c,
21219IMG_FMT_FMASK8_S4_F1 = 0x0000009d,
21220IMG_FMT_FMASK8_S8_F1 = 0x0000009e,
21221IMG_FMT_FMASK8_S2_F2 = 0x0000009f,
21222IMG_FMT_FMASK8_S4_F2 = 0x000000a0,
21223IMG_FMT_FMASK8_S4_F4 = 0x000000a1,
21224IMG_FMT_FMASK16_S16_F1 = 0x000000a2,
21225IMG_FMT_FMASK16_S8_F2 = 0x000000a3,
21226IMG_FMT_FMASK32_S16_F2 = 0x000000a4,
21227IMG_FMT_FMASK32_S8_F4 = 0x000000a5,
21228IMG_FMT_FMASK32_S8_F8 = 0x000000a6,
21229IMG_FMT_FMASK64_S16_F4 = 0x000000a7,
21230IMG_FMT_FMASK64_S16_F8 = 0x000000a8,
21231IMG_FMT_BC1_UNORM = 0x000000a9,
21232IMG_FMT_BC1_SRGB = 0x000000aa,
21233IMG_FMT_BC2_UNORM = 0x000000ab,
21234IMG_FMT_BC2_SRGB = 0x000000ac,
21235IMG_FMT_BC3_UNORM = 0x000000ad,
21236IMG_FMT_BC3_SRGB = 0x000000ae,
21237IMG_FMT_BC4_UNORM = 0x000000af,
21238IMG_FMT_BC4_SNORM = 0x000000b0,
21239IMG_FMT_BC5_UNORM = 0x000000b1,
21240IMG_FMT_BC5_SNORM = 0x000000b2,
21241IMG_FMT_BC6_UFLOAT = 0x000000b3,
21242IMG_FMT_BC6_SFLOAT = 0x000000b4,
21243IMG_FMT_BC7_UNORM = 0x000000b5,
21244IMG_FMT_BC7_SRGB = 0x000000b6,
21245IMG_FMT_MM_8_UNORM = 0x00000109,
21246IMG_FMT_MM_8_UINT = 0x0000010a,
21247IMG_FMT_MM_8_8_UNORM = 0x0000010b,
21248IMG_FMT_MM_8_8_UINT = 0x0000010c,
21249IMG_FMT_MM_8_8_8_8_UNORM = 0x0000010d,
21250IMG_FMT_MM_8_8_8_8_UINT = 0x0000010e,
21251IMG_FMT_MM_VYUY8_UNORM = 0x0000010f,
21252IMG_FMT_MM_VYUY8_UINT = 0x00000110,
21253IMG_FMT_MM_10_11_11_UNORM = 0x00000111,
21254IMG_FMT_MM_10_11_11_UINT = 0x00000112,
21255IMG_FMT_MM_2_10_10_10_UNORM = 0x00000113,
21256IMG_FMT_MM_2_10_10_10_UINT = 0x00000114,
21257IMG_FMT_MM_16_16_16_16_UNORM = 0x00000115,
21258IMG_FMT_MM_16_16_16_16_UINT = 0x00000116,
21259IMG_FMT_MM_10_IN_16_UNORM = 0x00000117,
21260IMG_FMT_MM_10_IN_16_UINT = 0x00000118,
21261IMG_FMT_MM_10_IN_16_16_UNORM = 0x00000119,
21262IMG_FMT_MM_10_IN_16_16_UINT = 0x0000011a,
21263IMG_FMT_MM_10_IN_16_16_16_16_UNORM = 0x0000011b,
21264IMG_FMT_MM_10_IN_16_16_16_16_UINT = 0x0000011c,
21265IMG_FMT_RESERVED_285 = 0x0000011d,
21266IMG_FMT_RESERVED_286 = 0x0000011e,
21267IMG_FMT_RESERVED_287 = 0x0000011f,
21268IMG_FMT_RESERVED_288 = 0x00000120,
21269IMG_FMT_RESERVED_289 = 0x00000121,
21270IMG_FMT_RESERVED_290 = 0x00000122,
21271IMG_FMT_RESERVED_291 = 0x00000123,
21272IMG_FMT_RESERVED_292 = 0x00000124,
21273IMG_FMT_RESERVED_293 = 0x00000125,
21274IMG_FMT_RESERVED_294 = 0x00000126,
21275IMG_FMT_RESERVED_295 = 0x00000127,
21276IMG_FMT_RESERVED_296 = 0x00000128,
21277IMG_FMT_RESERVED_297 = 0x00000129,
21278IMG_FMT_RESERVED_298 = 0x0000012a,
21279IMG_FMT_RESERVED_299 = 0x0000012b,
21280IMG_FMT_RESERVED_300 = 0x0000012c,
21281IMG_FMT_RESERVED_301 = 0x0000012d,
21282IMG_FMT_RESERVED_302 = 0x0000012e,
21283IMG_FMT_RESERVED_303 = 0x0000012f,
21284IMG_FMT_RESERVED_304 = 0x00000130,
21285IMG_FMT_RESERVED_305 = 0x00000131,
21286IMG_FMT_RESERVED_306 = 0x00000132,
21287IMG_FMT_RESERVED_307 = 0x00000133,
21288IMG_FMT_RESERVED_308 = 0x00000134,
21289IMG_FMT_RESERVED_309 = 0x00000135,
21290IMG_FMT_RESERVED_310 = 0x00000136,
21291IMG_FMT_RESERVED_311 = 0x00000137,
21292IMG_FMT_RESERVED_312 = 0x00000138,
21293IMG_FMT_RESERVED_313 = 0x00000139,
21294IMG_FMT_RESERVED_314 = 0x0000013a,
21295IMG_FMT_RESERVED_315 = 0x0000013b,
21296IMG_FMT_RESERVED_316 = 0x0000013c,
21297IMG_FMT_RESERVED_317 = 0x0000013d,
21298IMG_FMT_RESERVED_318 = 0x0000013e,
21299IMG_FMT_RESERVED_319 = 0x0000013f,
21300IMG_FMT_RESERVED_320 = 0x00000140,
21301IMG_FMT_RESERVED_321 = 0x00000141,
21302IMG_FMT_RESERVED_322 = 0x00000142,
21303IMG_FMT_RESERVED_323 = 0x00000143,
21304IMG_FMT_RESERVED_324 = 0x00000144,
21305IMG_FMT_RESERVED_325 = 0x00000145,
21306IMG_FMT_RESERVED_326 = 0x00000146,
21307IMG_FMT_RESERVED_327 = 0x00000147,
21308IMG_FMT_RESERVED_328 = 0x00000148,
21309IMG_FMT_RESERVED_329 = 0x00000149,
21310IMG_FMT_RESERVED_330 = 0x0000014a,
21311IMG_FMT_RESERVED_331 = 0x0000014b,
21312IMG_FMT_RESERVED_332 = 0x0000014c,
21313IMG_FMT_RESERVED_333 = 0x0000014d,
21314IMG_FMT_RESERVED_334 = 0x0000014e,
21315IMG_FMT_RESERVED_335 = 0x0000014f,
21316IMG_FMT_RESERVED_336 = 0x00000150,
21317IMG_FMT_RESERVED_337 = 0x00000151,
21318IMG_FMT_RESERVED_338 = 0x00000152,
21319IMG_FMT_RESERVED_339 = 0x00000153,
21320IMG_FMT_RESERVED_340 = 0x00000154,
21321IMG_FMT_RESERVED_341 = 0x00000155,
21322IMG_FMT_RESERVED_342 = 0x00000156,
21323IMG_FMT_RESERVED_343 = 0x00000157,
21324IMG_FMT_RESERVED_344 = 0x00000158,
21325IMG_FMT_RESERVED_345 = 0x00000159,
21326IMG_FMT_RESERVED_346 = 0x0000015a,
21327IMG_FMT_RESERVED_347 = 0x0000015b,
21328IMG_FMT_RESERVED_348 = 0x0000015c,
21329IMG_FMT_RESERVED_349 = 0x0000015d,
21330IMG_FMT_RESERVED_350 = 0x0000015e,
21331IMG_FMT_RESERVED_351 = 0x0000015f,
21332IMG_FMT_RESERVED_352 = 0x00000160,
21333IMG_FMT_RESERVED_353 = 0x00000161,
21334IMG_FMT_RESERVED_354 = 0x00000162,
21335IMG_FMT_RESERVED_355 = 0x00000163,
21336IMG_FMT_RESERVED_356 = 0x00000164,
21337IMG_FMT_RESERVED_357 = 0x00000165,
21338IMG_FMT_RESERVED_358 = 0x00000166,
21339IMG_FMT_RESERVED_359 = 0x00000167,
21340IMG_FMT_RESERVED_360 = 0x00000168,
21341IMG_FMT_RESERVED_361 = 0x00000169,
21342IMG_FMT_RESERVED_362 = 0x0000016a,
21343IMG_FMT_RESERVED_363 = 0x0000016b,
21344IMG_FMT_RESERVED_364 = 0x0000016c,
21345IMG_FMT_RESERVED_365 = 0x0000016d,
21346IMG_FMT_RESERVED_366 = 0x0000016e,
21347IMG_FMT_RESERVED_367 = 0x0000016f,
21348IMG_FMT_RESERVED_368 = 0x00000170,
21349IMG_FMT_RESERVED_369 = 0x00000171,
21350IMG_FMT_RESERVED_370 = 0x00000172,
21351IMG_FMT_RESERVED_371 = 0x00000173,
21352IMG_FMT_RESERVED_372 = 0x00000174,
21353IMG_FMT_RESERVED_373 = 0x00000175,
21354IMG_FMT_RESERVED_374 = 0x00000176,
21355IMG_FMT_RESERVED_375 = 0x00000177,
21356IMG_FMT_RESERVED_376 = 0x00000178,
21357IMG_FMT_RESERVED_377 = 0x00000179,
21358IMG_FMT_RESERVED_378 = 0x0000017a,
21359IMG_FMT_RESERVED_379 = 0x0000017b,
21360IMG_FMT_RESERVED_380 = 0x0000017c,
21361IMG_FMT_RESERVED_381 = 0x0000017d,
21362IMG_FMT_RESERVED_382 = 0x0000017e,
21363IMG_FMT_RESERVED_383 = 0x0000017f,
21364IMG_FMT_RESERVED_384 = 0x00000180,
21365IMG_FMT_RESERVED_385 = 0x00000181,
21366IMG_FMT_RESERVED_386 = 0x00000182,
21367IMG_FMT_RESERVED_387 = 0x00000183,
21368IMG_FMT_RESERVED_388 = 0x00000184,
21369IMG_FMT_RESERVED_389 = 0x00000185,
21370IMG_FMT_RESERVED_390 = 0x00000186,
21371IMG_FMT_RESERVED_391 = 0x00000187,
21372IMG_FMT_RESERVED_392 = 0x00000188,
21373IMG_FMT_RESERVED_393 = 0x00000189,
21374IMG_FMT_RESERVED_394 = 0x0000018a,
21375IMG_FMT_RESERVED_395 = 0x0000018b,
21376IMG_FMT_RESERVED_396 = 0x0000018c,
21377IMG_FMT_RESERVED_397 = 0x0000018d,
21378IMG_FMT_RESERVED_398 = 0x0000018e,
21379IMG_FMT_RESERVED_399 = 0x0000018f,
21380IMG_FMT_RESERVED_400 = 0x00000190,
21381IMG_FMT_RESERVED_401 = 0x00000191,
21382IMG_FMT_RESERVED_402 = 0x00000192,
21383IMG_FMT_RESERVED_403 = 0x00000193,
21384IMG_FMT_RESERVED_404 = 0x00000194,
21385IMG_FMT_RESERVED_405 = 0x00000195,
21386IMG_FMT_RESERVED_406 = 0x00000196,
21387IMG_FMT_RESERVED_407 = 0x00000197,
21388IMG_FMT_RESERVED_408 = 0x00000198,
21389IMG_FMT_RESERVED_409 = 0x00000199,
21390IMG_FMT_RESERVED_410 = 0x0000019a,
21391IMG_FMT_RESERVED_411 = 0x0000019b,
21392IMG_FMT_RESERVED_412 = 0x0000019c,
21393IMG_FMT_RESERVED_413 = 0x0000019d,
21394IMG_FMT_RESERVED_414 = 0x0000019e,
21395IMG_FMT_RESERVED_415 = 0x0000019f,
21396IMG_FMT_RESERVED_416 = 0x000001a0,
21397IMG_FMT_RESERVED_417 = 0x000001a1,
21398IMG_FMT_RESERVED_418 = 0x000001a2,
21399IMG_FMT_RESERVED_419 = 0x000001a3,
21400IMG_FMT_RESERVED_420 = 0x000001a4,
21401IMG_FMT_RESERVED_421 = 0x000001a5,
21402IMG_FMT_RESERVED_422 = 0x000001a6,
21403IMG_FMT_RESERVED_423 = 0x000001a7,
21404IMG_FMT_RESERVED_424 = 0x000001a8,
21405IMG_FMT_RESERVED_425 = 0x000001a9,
21406IMG_FMT_RESERVED_426 = 0x000001aa,
21407IMG_FMT_RESERVED_427 = 0x000001ab,
21408IMG_FMT_RESERVED_428 = 0x000001ac,
21409IMG_FMT_RESERVED_429 = 0x000001ad,
21410IMG_FMT_RESERVED_430 = 0x000001ae,
21411IMG_FMT_RESERVED_431 = 0x000001af,
21412IMG_FMT_RESERVED_432 = 0x000001b0,
21413IMG_FMT_RESERVED_433 = 0x000001b1,
21414IMG_FMT_RESERVED_434 = 0x000001b2,
21415IMG_FMT_RESERVED_435 = 0x000001b3,
21416IMG_FMT_RESERVED_436 = 0x000001b4,
21417IMG_FMT_RESERVED_437 = 0x000001b5,
21418IMG_FMT_RESERVED_438 = 0x000001b6,
21419IMG_FMT_RESERVED_439 = 0x000001b7,
21420IMG_FMT_RESERVED_440 = 0x000001b8,
21421IMG_FMT_RESERVED_441 = 0x000001b9,
21422IMG_FMT_RESERVED_442 = 0x000001ba,
21423IMG_FMT_RESERVED_443 = 0x000001bb,
21424IMG_FMT_RESERVED_444 = 0x000001bc,
21425IMG_FMT_RESERVED_445 = 0x000001bd,
21426IMG_FMT_RESERVED_446 = 0x000001be,
21427IMG_FMT_RESERVED_447 = 0x000001bf,
21428IMG_FMT_RESERVED_448 = 0x000001c0,
21429IMG_FMT_RESERVED_449 = 0x000001c1,
21430IMG_FMT_RESERVED_450 = 0x000001c2,
21431IMG_FMT_RESERVED_451 = 0x000001c3,
21432IMG_FMT_RESERVED_452 = 0x000001c4,
21433IMG_FMT_RESERVED_453 = 0x000001c5,
21434IMG_FMT_RESERVED_454 = 0x000001c6,
21435IMG_FMT_RESERVED_455 = 0x000001c7,
21436IMG_FMT_RESERVED_456 = 0x000001c8,
21437IMG_FMT_RESERVED_457 = 0x000001c9,
21438IMG_FMT_RESERVED_458 = 0x000001ca,
21439IMG_FMT_RESERVED_459 = 0x000001cb,
21440IMG_FMT_RESERVED_460 = 0x000001cc,
21441IMG_FMT_RESERVED_461 = 0x000001cd,
21442IMG_FMT_RESERVED_462 = 0x000001ce,
21443IMG_FMT_RESERVED_463 = 0x000001cf,
21444IMG_FMT_RESERVED_464 = 0x000001d0,
21445IMG_FMT_RESERVED_465 = 0x000001d1,
21446IMG_FMT_RESERVED_466 = 0x000001d2,
21447IMG_FMT_RESERVED_467 = 0x000001d3,
21448IMG_FMT_RESERVED_468 = 0x000001d4,
21449IMG_FMT_RESERVED_469 = 0x000001d5,
21450IMG_FMT_RESERVED_470 = 0x000001d6,
21451IMG_FMT_RESERVED_471 = 0x000001d7,
21452IMG_FMT_RESERVED_472 = 0x000001d8,
21453IMG_FMT_RESERVED_473 = 0x000001d9,
21454IMG_FMT_RESERVED_474 = 0x000001da,
21455IMG_FMT_RESERVED_475 = 0x000001db,
21456IMG_FMT_RESERVED_476 = 0x000001dc,
21457IMG_FMT_RESERVED_477 = 0x000001dd,
21458IMG_FMT_RESERVED_478 = 0x000001de,
21459IMG_FMT_RESERVED_479 = 0x000001df,
21460IMG_FMT_RESERVED_480 = 0x000001e0,
21461IMG_FMT_RESERVED_481 = 0x000001e1,
21462IMG_FMT_RESERVED_482 = 0x000001e2,
21463IMG_FMT_RESERVED_483 = 0x000001e3,
21464IMG_FMT_RESERVED_484 = 0x000001e4,
21465IMG_FMT_RESERVED_485 = 0x000001e5,
21466IMG_FMT_RESERVED_486 = 0x000001e6,
21467IMG_FMT_RESERVED_487 = 0x000001e7,
21468IMG_FMT_RESERVED_488 = 0x000001e8,
21469IMG_FMT_RESERVED_489 = 0x000001e9,
21470IMG_FMT_RESERVED_490 = 0x000001ea,
21471IMG_FMT_RESERVED_491 = 0x000001eb,
21472IMG_FMT_RESERVED_492 = 0x000001ec,
21473IMG_FMT_RESERVED_493 = 0x000001ed,
21474IMG_FMT_RESERVED_494 = 0x000001ee,
21475IMG_FMT_RESERVED_495 = 0x000001ef,
21476IMG_FMT_RESERVED_496 = 0x000001f0,
21477IMG_FMT_RESERVED_497 = 0x000001f1,
21478IMG_FMT_RESERVED_498 = 0x000001f2,
21479IMG_FMT_RESERVED_499 = 0x000001f3,
21480IMG_FMT_RESERVED_500 = 0x000001f4,
21481IMG_FMT_RESERVED_501 = 0x000001f5,
21482IMG_FMT_RESERVED_502 = 0x000001f6,
21483IMG_FMT_RESERVED_503 = 0x000001f7,
21484IMG_FMT_RESERVED_504 = 0x000001f8,
21485IMG_FMT_RESERVED_505 = 0x000001f9,
21486IMG_FMT_RESERVED_506 = 0x000001fa,
21487IMG_FMT_RESERVED_507 = 0x000001fb,
21488IMG_FMT_RESERVED_508 = 0x000001fc,
21489IMG_FMT_RESERVED_509 = 0x000001fd,
21490IMG_FMT_RESERVED_510 = 0x000001fe,
21491IMG_FMT_RESERVED_511 = 0x000001ff,
21492} IMG_FMT;
21493
21494/*
21495 * BUF_DATA_FORMAT enum
21496 */
21497
21498typedef enum BUF_DATA_FORMAT {
21499BUF_DATA_FORMAT_INVALID = 0x00000000,
21500BUF_DATA_FORMAT_8 = 0x00000001,
21501BUF_DATA_FORMAT_16 = 0x00000002,
21502BUF_DATA_FORMAT_8_8 = 0x00000003,
21503BUF_DATA_FORMAT_32 = 0x00000004,
21504BUF_DATA_FORMAT_16_16 = 0x00000005,
21505BUF_DATA_FORMAT_10_11_11 = 0x00000006,
21506BUF_DATA_FORMAT_11_11_10 = 0x00000007,
21507BUF_DATA_FORMAT_10_10_10_2 = 0x00000008,
21508BUF_DATA_FORMAT_2_10_10_10 = 0x00000009,
21509BUF_DATA_FORMAT_8_8_8_8 = 0x0000000a,
21510BUF_DATA_FORMAT_32_32 = 0x0000000b,
21511BUF_DATA_FORMAT_16_16_16_16 = 0x0000000c,
21512BUF_DATA_FORMAT_32_32_32 = 0x0000000d,
21513BUF_DATA_FORMAT_32_32_32_32 = 0x0000000e,
21514BUF_DATA_FORMAT_RESERVED_15 = 0x0000000f,
21515} BUF_DATA_FORMAT;
21516
21517/*
21518 * IMG_DATA_FORMAT enum
21519 */
21520
21521typedef enum IMG_DATA_FORMAT {
21522IMG_DATA_FORMAT_INVALID = 0x00000000,
21523IMG_DATA_FORMAT_8 = 0x00000001,
21524IMG_DATA_FORMAT_16 = 0x00000002,
21525IMG_DATA_FORMAT_8_8 = 0x00000003,
21526IMG_DATA_FORMAT_32 = 0x00000004,
21527IMG_DATA_FORMAT_16_16 = 0x00000005,
21528IMG_DATA_FORMAT_10_11_11 = 0x00000006,
21529IMG_DATA_FORMAT_11_11_10 = 0x00000007,
21530IMG_DATA_FORMAT_10_10_10_2 = 0x00000008,
21531IMG_DATA_FORMAT_2_10_10_10 = 0x00000009,
21532IMG_DATA_FORMAT_8_8_8_8 = 0x0000000a,
21533IMG_DATA_FORMAT_32_32 = 0x0000000b,
21534IMG_DATA_FORMAT_16_16_16_16 = 0x0000000c,
21535IMG_DATA_FORMAT_32_32_32 = 0x0000000d,
21536IMG_DATA_FORMAT_32_32_32_32 = 0x0000000e,
21537IMG_DATA_FORMAT_RESERVED_15 = 0x0000000f,
21538IMG_DATA_FORMAT_5_6_5 = 0x00000010,
21539IMG_DATA_FORMAT_1_5_5_5 = 0x00000011,
21540IMG_DATA_FORMAT_5_5_5_1 = 0x00000012,
21541IMG_DATA_FORMAT_4_4_4_4 = 0x00000013,
21542IMG_DATA_FORMAT_8_24 = 0x00000014,
21543IMG_DATA_FORMAT_24_8 = 0x00000015,
21544IMG_DATA_FORMAT_X24_8_32 = 0x00000016,
21545IMG_DATA_FORMAT_RESERVED_23 = 0x00000017,
21546IMG_DATA_FORMAT_RESERVED_24 = 0x00000018,
21547IMG_DATA_FORMAT_RESERVED_25 = 0x00000019,
21548IMG_DATA_FORMAT_RESERVED_26 = 0x0000001a,
21549IMG_DATA_FORMAT_RESERVED_27 = 0x0000001b,
21550IMG_DATA_FORMAT_RESERVED_28 = 0x0000001c,
21551IMG_DATA_FORMAT_RESERVED_29 = 0x0000001d,
21552IMG_DATA_FORMAT_RESERVED_30 = 0x0000001e,
21553IMG_DATA_FORMAT_6E4 = 0x0000001f,
21554IMG_DATA_FORMAT_GB_GR = 0x00000020,
21555IMG_DATA_FORMAT_BG_RG = 0x00000021,
21556IMG_DATA_FORMAT_5_9_9_9 = 0x00000022,
21557IMG_DATA_FORMAT_BC1 = 0x00000023,
21558IMG_DATA_FORMAT_BC2 = 0x00000024,
21559IMG_DATA_FORMAT_BC3 = 0x00000025,
21560IMG_DATA_FORMAT_BC4 = 0x00000026,
21561IMG_DATA_FORMAT_BC5 = 0x00000027,
21562IMG_DATA_FORMAT_BC6 = 0x00000028,
21563IMG_DATA_FORMAT_BC7 = 0x00000029,
21564IMG_DATA_FORMAT_RESERVED_42 = 0x0000002a,
21565IMG_DATA_FORMAT_RESERVED_43 = 0x0000002b,
21566IMG_DATA_FORMAT_FMASK8_S2_F1 = 0x0000002c,
21567IMG_DATA_FORMAT_FMASK8_S4_F1 = 0x0000002d,
21568IMG_DATA_FORMAT_FMASK8_S8_F1 = 0x0000002e,
21569IMG_DATA_FORMAT_FMASK8_S2_F2 = 0x0000002f,
21570IMG_DATA_FORMAT_FMASK8_S4_F2 = 0x00000030,
21571IMG_DATA_FORMAT_FMASK8_S4_F4 = 0x00000031,
21572IMG_DATA_FORMAT_FMASK16_S16_F1 = 0x00000032,
21573IMG_DATA_FORMAT_FMASK16_S8_F2 = 0x00000033,
21574IMG_DATA_FORMAT_FMASK32_S16_F2 = 0x00000034,
21575IMG_DATA_FORMAT_FMASK32_S8_F4 = 0x00000035,
21576IMG_DATA_FORMAT_FMASK32_S8_F8 = 0x00000036,
21577IMG_DATA_FORMAT_FMASK64_S16_F4 = 0x00000037,
21578IMG_DATA_FORMAT_FMASK64_S16_F8 = 0x00000038,
21579IMG_DATA_FORMAT_4_4 = 0x00000039,
21580IMG_DATA_FORMAT_6_5_5 = 0x0000003a,
21581IMG_DATA_FORMAT_1 = 0x0000003b,
21582IMG_DATA_FORMAT_1_REVERSED = 0x0000003c,
21583IMG_DATA_FORMAT_RESERVED_61 = 0x0000003d,
21584IMG_DATA_FORMAT_RESERVED_62 = 0x0000003e,
21585IMG_DATA_FORMAT_32_AS_32_32_32_32 = 0x0000003f,
21586IMG_DATA_FORMAT_RESERVED_75 = 0x0000004b,
21587IMG_DATA_FORMAT_MM_8 = 0x0000004c,
21588IMG_DATA_FORMAT_MM_8_8 = 0x0000004d,
21589IMG_DATA_FORMAT_MM_8_8_8_8 = 0x0000004e,
21590IMG_DATA_FORMAT_MM_VYUY8 = 0x0000004f,
21591IMG_DATA_FORMAT_MM_10_11_11 = 0x00000050,
21592IMG_DATA_FORMAT_MM_2_10_10_10 = 0x00000051,
21593IMG_DATA_FORMAT_MM_16_16_16_16 = 0x00000052,
21594IMG_DATA_FORMAT_MM_10_IN_16 = 0x00000053,
21595IMG_DATA_FORMAT_MM_10_IN_16_16 = 0x00000054,
21596IMG_DATA_FORMAT_MM_10_IN_16_16_16_16 = 0x00000055,
21597IMG_DATA_FORMAT_RESERVED_86 = 0x00000056,
21598IMG_DATA_FORMAT_RESERVED_87 = 0x00000057,
21599IMG_DATA_FORMAT_RESERVED_88 = 0x00000058,
21600IMG_DATA_FORMAT_RESERVED_89 = 0x00000059,
21601IMG_DATA_FORMAT_RESERVED_90 = 0x0000005a,
21602IMG_DATA_FORMAT_RESERVED_91 = 0x0000005b,
21603IMG_DATA_FORMAT_RESERVED_92 = 0x0000005c,
21604IMG_DATA_FORMAT_RESERVED_93 = 0x0000005d,
21605IMG_DATA_FORMAT_RESERVED_94 = 0x0000005e,
21606IMG_DATA_FORMAT_RESERVED_95 = 0x0000005f,
21607IMG_DATA_FORMAT_RESERVED_96 = 0x00000060,
21608IMG_DATA_FORMAT_RESERVED_97 = 0x00000061,
21609IMG_DATA_FORMAT_RESERVED_98 = 0x00000062,
21610IMG_DATA_FORMAT_RESERVED_99 = 0x00000063,
21611IMG_DATA_FORMAT_RESERVED_100 = 0x00000064,
21612IMG_DATA_FORMAT_RESERVED_101 = 0x00000065,
21613IMG_DATA_FORMAT_RESERVED_102 = 0x00000066,
21614IMG_DATA_FORMAT_RESERVED_103 = 0x00000067,
21615IMG_DATA_FORMAT_RESERVED_104 = 0x00000068,
21616IMG_DATA_FORMAT_RESERVED_105 = 0x00000069,
21617IMG_DATA_FORMAT_RESERVED_106 = 0x0000006a,
21618IMG_DATA_FORMAT_RESERVED_107 = 0x0000006b,
21619IMG_DATA_FORMAT_RESERVED_108 = 0x0000006c,
21620IMG_DATA_FORMAT_RESERVED_109 = 0x0000006d,
21621IMG_DATA_FORMAT_RESERVED_110 = 0x0000006e,
21622IMG_DATA_FORMAT_RESERVED_111 = 0x0000006f,
21623IMG_DATA_FORMAT_RESERVED_112 = 0x00000070,
21624IMG_DATA_FORMAT_RESERVED_113 = 0x00000071,
21625IMG_DATA_FORMAT_RESERVED_114 = 0x00000072,
21626IMG_DATA_FORMAT_RESERVED_115 = 0x00000073,
21627IMG_DATA_FORMAT_RESERVED_116 = 0x00000074,
21628IMG_DATA_FORMAT_RESERVED_117 = 0x00000075,
21629IMG_DATA_FORMAT_RESERVED_118 = 0x00000076,
21630IMG_DATA_FORMAT_RESERVED_119 = 0x00000077,
21631IMG_DATA_FORMAT_RESERVED_120 = 0x00000078,
21632IMG_DATA_FORMAT_RESERVED_121 = 0x00000079,
21633IMG_DATA_FORMAT_RESERVED_122 = 0x0000007a,
21634IMG_DATA_FORMAT_RESERVED_123 = 0x0000007b,
21635IMG_DATA_FORMAT_RESERVED_124 = 0x0000007c,
21636IMG_DATA_FORMAT_RESERVED_125 = 0x0000007d,
21637IMG_DATA_FORMAT_RESERVED_126 = 0x0000007e,
21638IMG_DATA_FORMAT_RESERVED_127 = 0x0000007f,
21639} IMG_DATA_FORMAT;
21640
21641/*
21642 * BUF_NUM_FORMAT enum
21643 */
21644
21645typedef enum BUF_NUM_FORMAT {
21646BUF_NUM_FORMAT_UNORM = 0x00000000,
21647BUF_NUM_FORMAT_SNORM = 0x00000001,
21648BUF_NUM_FORMAT_USCALED = 0x00000002,
21649BUF_NUM_FORMAT_SSCALED = 0x00000003,
21650BUF_NUM_FORMAT_UINT = 0x00000004,
21651BUF_NUM_FORMAT_SINT = 0x00000005,
21652BUF_NUM_FORMAT_SNORM_NZ = 0x00000006,
21653BUF_NUM_FORMAT_FLOAT = 0x00000007,
21654} BUF_NUM_FORMAT;
21655
21656/*
21657 * IMG_NUM_FORMAT enum
21658 */
21659
21660typedef enum IMG_NUM_FORMAT {
21661IMG_NUM_FORMAT_UNORM = 0x00000000,
21662IMG_NUM_FORMAT_SNORM = 0x00000001,
21663IMG_NUM_FORMAT_USCALED = 0x00000002,
21664IMG_NUM_FORMAT_SSCALED = 0x00000003,
21665IMG_NUM_FORMAT_UINT = 0x00000004,
21666IMG_NUM_FORMAT_SINT = 0x00000005,
21667IMG_NUM_FORMAT_SNORM_NZ = 0x00000006,
21668IMG_NUM_FORMAT_FLOAT = 0x00000007,
21669IMG_NUM_FORMAT_RESERVED_8 = 0x00000008,
21670IMG_NUM_FORMAT_SRGB = 0x00000009,
21671IMG_NUM_FORMAT_UBNORM = 0x0000000a,
21672IMG_NUM_FORMAT_UBNORM_NZ = 0x0000000b,
21673IMG_NUM_FORMAT_UBINT = 0x0000000c,
21674IMG_NUM_FORMAT_UBSCALED = 0x0000000d,
21675IMG_NUM_FORMAT_RESERVED_14 = 0x0000000e,
21676IMG_NUM_FORMAT_RESERVED_15 = 0x0000000f,
21677} IMG_NUM_FORMAT;
21678
21679/*******************************************************
21680 * IH Enums
21681 *******************************************************/
21682
21683/*
21684 * IH_PERF_SEL enum
21685 */
21686
21687typedef enum IH_PERF_SEL {
21688IH_PERF_SEL_CYCLE = 0x00000000,
21689IH_PERF_SEL_IDLE = 0x00000001,
21690IH_PERF_SEL_INPUT_IDLE = 0x00000002,
21691IH_PERF_SEL_BUFFER_IDLE = 0x00000003,
21692IH_PERF_SEL_RB0_FULL = 0x00000004,
21693IH_PERF_SEL_RB0_OVERFLOW = 0x00000005,
21694IH_PERF_SEL_RB0_WPTR_WRITEBACK = 0x00000006,
21695IH_PERF_SEL_RB0_WPTR_WRAP = 0x00000007,
21696IH_PERF_SEL_RB0_RPTR_WRAP = 0x00000008,
21697IH_PERF_SEL_MC_WR_IDLE = 0x00000009,
21698IH_PERF_SEL_MC_WR_COUNT = 0x0000000a,
21699IH_PERF_SEL_MC_WR_STALL = 0x0000000b,
21700IH_PERF_SEL_MC_WR_CLEAN_PENDING = 0x0000000c,
21701IH_PERF_SEL_MC_WR_CLEAN_STALL = 0x0000000d,
21702IH_PERF_SEL_BIF_LINE0_RISING = 0x0000000e,
21703IH_PERF_SEL_BIF_LINE0_FALLING = 0x0000000f,
21704IH_PERF_SEL_RB1_FULL = 0x00000010,
21705IH_PERF_SEL_RB1_OVERFLOW = 0x00000011,
21706IH_PERF_SEL_COOKIE_REC_ERROR = 0x00000012,
21707IH_PERF_SEL_RB1_WPTR_WRAP = 0x00000013,
21708IH_PERF_SEL_RB1_RPTR_WRAP = 0x00000014,
21709IH_PERF_SEL_RB2_FULL = 0x00000015,
21710IH_PERF_SEL_RB2_OVERFLOW = 0x00000016,
21711IH_PERF_SEL_CLIENT_CREDIT_ERROR = 0x00000017,
21712IH_PERF_SEL_RB2_WPTR_WRAP = 0x00000018,
21713IH_PERF_SEL_RB2_RPTR_WRAP = 0x00000019,
21714IH_PERF_SEL_STORM_CLIENT_INT_DROP = 0x0000001a,
21715IH_PERF_SEL_SELF_IV_VALID = 0x0000001b,
21716IH_PERF_SEL_BUFFER_FIFO_FULL = 0x0000001c,
21717IH_PERF_SEL_RB0_FULL_VF0 = 0x0000001d,
21718IH_PERF_SEL_RB0_FULL_VF1 = 0x0000001e,
21719IH_PERF_SEL_RB0_FULL_VF2 = 0x0000001f,
21720IH_PERF_SEL_RB0_FULL_VF3 = 0x00000020,
21721IH_PERF_SEL_RB0_FULL_VF4 = 0x00000021,
21722IH_PERF_SEL_RB0_FULL_VF5 = 0x00000022,
21723IH_PERF_SEL_RB0_FULL_VF6 = 0x00000023,
21724IH_PERF_SEL_RB0_FULL_VF7 = 0x00000024,
21725IH_PERF_SEL_RB0_FULL_VF8 = 0x00000025,
21726IH_PERF_SEL_RB0_FULL_VF9 = 0x00000026,
21727IH_PERF_SEL_RB0_FULL_VF10 = 0x00000027,
21728IH_PERF_SEL_RB0_FULL_VF11 = 0x00000028,
21729IH_PERF_SEL_RB0_FULL_VF12 = 0x00000029,
21730IH_PERF_SEL_RB0_FULL_VF13 = 0x0000002a,
21731IH_PERF_SEL_RB0_FULL_VF14 = 0x0000002b,
21732IH_PERF_SEL_RB0_FULL_VF15 = 0x0000002c,
21733IH_PERF_SEL_RB0_FULL_VF16 = 0x0000002d,
21734IH_PERF_SEL_RB0_FULL_VF17 = 0x0000002e,
21735IH_PERF_SEL_RB0_FULL_VF18 = 0x0000002f,
21736IH_PERF_SEL_RB0_FULL_VF19 = 0x00000030,
21737IH_PERF_SEL_RB0_FULL_VF20 = 0x00000031,
21738IH_PERF_SEL_RB0_FULL_VF21 = 0x00000032,
21739IH_PERF_SEL_RB0_FULL_VF22 = 0x00000033,
21740IH_PERF_SEL_RB0_FULL_VF23 = 0x00000034,
21741IH_PERF_SEL_RB0_FULL_VF24 = 0x00000035,
21742IH_PERF_SEL_RB0_FULL_VF25 = 0x00000036,
21743IH_PERF_SEL_RB0_FULL_VF26 = 0x00000037,
21744IH_PERF_SEL_RB0_FULL_VF27 = 0x00000038,
21745IH_PERF_SEL_RB0_FULL_VF28 = 0x00000039,
21746IH_PERF_SEL_RB0_FULL_VF29 = 0x0000003a,
21747IH_PERF_SEL_RB0_FULL_VF30 = 0x0000003b,
21748IH_PERF_SEL_RB0_OVERFLOW_VF0 = 0x0000003c,
21749IH_PERF_SEL_RB0_OVERFLOW_VF1 = 0x0000003d,
21750IH_PERF_SEL_RB0_OVERFLOW_VF2 = 0x0000003e,
21751IH_PERF_SEL_RB0_OVERFLOW_VF3 = 0x0000003f,
21752IH_PERF_SEL_RB0_OVERFLOW_VF4 = 0x00000040,
21753IH_PERF_SEL_RB0_OVERFLOW_VF5 = 0x00000041,
21754IH_PERF_SEL_RB0_OVERFLOW_VF6 = 0x00000042,
21755IH_PERF_SEL_RB0_OVERFLOW_VF7 = 0x00000043,
21756IH_PERF_SEL_RB0_OVERFLOW_VF8 = 0x00000044,
21757IH_PERF_SEL_RB0_OVERFLOW_VF9 = 0x00000045,
21758IH_PERF_SEL_RB0_OVERFLOW_VF10 = 0x00000046,
21759IH_PERF_SEL_RB0_OVERFLOW_VF11 = 0x00000047,
21760IH_PERF_SEL_RB0_OVERFLOW_VF12 = 0x00000048,
21761IH_PERF_SEL_RB0_OVERFLOW_VF13 = 0x00000049,
21762IH_PERF_SEL_RB0_OVERFLOW_VF14 = 0x0000004a,
21763IH_PERF_SEL_RB0_OVERFLOW_VF15 = 0x0000004b,
21764IH_PERF_SEL_RB0_OVERFLOW_VF16 = 0x0000004c,
21765IH_PERF_SEL_RB0_OVERFLOW_VF17 = 0x0000004d,
21766IH_PERF_SEL_RB0_OVERFLOW_VF18 = 0x0000004e,
21767IH_PERF_SEL_RB0_OVERFLOW_VF19 = 0x0000004f,
21768IH_PERF_SEL_RB0_OVERFLOW_VF20 = 0x00000050,
21769IH_PERF_SEL_RB0_OVERFLOW_VF21 = 0x00000051,
21770IH_PERF_SEL_RB0_OVERFLOW_VF22 = 0x00000052,
21771IH_PERF_SEL_RB0_OVERFLOW_VF23 = 0x00000053,
21772IH_PERF_SEL_RB0_OVERFLOW_VF24 = 0x00000054,
21773IH_PERF_SEL_RB0_OVERFLOW_VF25 = 0x00000055,
21774IH_PERF_SEL_RB0_OVERFLOW_VF26 = 0x00000056,
21775IH_PERF_SEL_RB0_OVERFLOW_VF27 = 0x00000057,
21776IH_PERF_SEL_RB0_OVERFLOW_VF28 = 0x00000058,
21777IH_PERF_SEL_RB0_OVERFLOW_VF29 = 0x00000059,
21778IH_PERF_SEL_RB0_OVERFLOW_VF30 = 0x0000005a,
21779IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF0 = 0x0000005b,
21780IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF1 = 0x0000005c,
21781IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF2 = 0x0000005d,
21782IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF3 = 0x0000005e,
21783IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF4 = 0x0000005f,
21784IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF5 = 0x00000060,
21785IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF6 = 0x00000061,
21786IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF7 = 0x00000062,
21787IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF8 = 0x00000063,
21788IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF9 = 0x00000064,
21789IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF10 = 0x00000065,
21790IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF11 = 0x00000066,
21791IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF12 = 0x00000067,
21792IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF13 = 0x00000068,
21793IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF14 = 0x00000069,
21794IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF15 = 0x0000006a,
21795IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF16 = 0x0000006b,
21796IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF17 = 0x0000006c,
21797IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF18 = 0x0000006d,
21798IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF19 = 0x0000006e,
21799IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF20 = 0x0000006f,
21800IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF21 = 0x00000070,
21801IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF22 = 0x00000071,
21802IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF23 = 0x00000072,
21803IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF24 = 0x00000073,
21804IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF25 = 0x00000074,
21805IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF26 = 0x00000075,
21806IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF27 = 0x00000076,
21807IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF28 = 0x00000077,
21808IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF29 = 0x00000078,
21809IH_PERF_SEL_RB0_WPTR_WRITEBACK_VF30 = 0x00000079,
21810IH_PERF_SEL_RB0_WPTR_WRAP_VF0 = 0x0000007a,
21811IH_PERF_SEL_RB0_WPTR_WRAP_VF1 = 0x0000007b,
21812IH_PERF_SEL_RB0_WPTR_WRAP_VF2 = 0x0000007c,
21813IH_PERF_SEL_RB0_WPTR_WRAP_VF3 = 0x0000007d,
21814IH_PERF_SEL_RB0_WPTR_WRAP_VF4 = 0x0000007e,
21815IH_PERF_SEL_RB0_WPTR_WRAP_VF5 = 0x0000007f,
21816IH_PERF_SEL_RB0_WPTR_WRAP_VF6 = 0x00000080,
21817IH_PERF_SEL_RB0_WPTR_WRAP_VF7 = 0x00000081,
21818IH_PERF_SEL_RB0_WPTR_WRAP_VF8 = 0x00000082,
21819IH_PERF_SEL_RB0_WPTR_WRAP_VF9 = 0x00000083,
21820IH_PERF_SEL_RB0_WPTR_WRAP_VF10 = 0x00000084,
21821IH_PERF_SEL_RB0_WPTR_WRAP_VF11 = 0x00000085,
21822IH_PERF_SEL_RB0_WPTR_WRAP_VF12 = 0x00000086,
21823IH_PERF_SEL_RB0_WPTR_WRAP_VF13 = 0x00000087,
21824IH_PERF_SEL_RB0_WPTR_WRAP_VF14 = 0x00000088,
21825IH_PERF_SEL_RB0_WPTR_WRAP_VF15 = 0x00000089,
21826IH_PERF_SEL_RB0_WPTR_WRAP_VF16 = 0x0000008a,
21827IH_PERF_SEL_RB0_WPTR_WRAP_VF17 = 0x0000008b,
21828IH_PERF_SEL_RB0_WPTR_WRAP_VF18 = 0x0000008c,
21829IH_PERF_SEL_RB0_WPTR_WRAP_VF19 = 0x0000008d,
21830IH_PERF_SEL_RB0_WPTR_WRAP_VF20 = 0x0000008e,
21831IH_PERF_SEL_RB0_WPTR_WRAP_VF21 = 0x0000008f,
21832IH_PERF_SEL_RB0_WPTR_WRAP_VF22 = 0x00000090,
21833IH_PERF_SEL_RB0_WPTR_WRAP_VF23 = 0x00000091,
21834IH_PERF_SEL_RB0_WPTR_WRAP_VF24 = 0x00000092,
21835IH_PERF_SEL_RB0_WPTR_WRAP_VF25 = 0x00000093,
21836IH_PERF_SEL_RB0_WPTR_WRAP_VF26 = 0x00000094,
21837IH_PERF_SEL_RB0_WPTR_WRAP_VF27 = 0x00000095,
21838IH_PERF_SEL_RB0_WPTR_WRAP_VF28 = 0x00000096,
21839IH_PERF_SEL_RB0_WPTR_WRAP_VF29 = 0x00000097,
21840IH_PERF_SEL_RB0_WPTR_WRAP_VF30 = 0x00000098,
21841IH_PERF_SEL_RB0_RPTR_WRAP_VF0 = 0x00000099,
21842IH_PERF_SEL_RB0_RPTR_WRAP_VF1 = 0x0000009a,
21843IH_PERF_SEL_RB0_RPTR_WRAP_VF2 = 0x0000009b,
21844IH_PERF_SEL_RB0_RPTR_WRAP_VF3 = 0x0000009c,
21845IH_PERF_SEL_RB0_RPTR_WRAP_VF4 = 0x0000009d,
21846IH_PERF_SEL_RB0_RPTR_WRAP_VF5 = 0x0000009e,
21847IH_PERF_SEL_RB0_RPTR_WRAP_VF6 = 0x0000009f,
21848IH_PERF_SEL_RB0_RPTR_WRAP_VF7 = 0x000000a0,
21849IH_PERF_SEL_RB0_RPTR_WRAP_VF8 = 0x000000a1,
21850IH_PERF_SEL_RB0_RPTR_WRAP_VF9 = 0x000000a2,
21851IH_PERF_SEL_RB0_RPTR_WRAP_VF10 = 0x000000a3,
21852IH_PERF_SEL_RB0_RPTR_WRAP_VF11 = 0x000000a4,
21853IH_PERF_SEL_RB0_RPTR_WRAP_VF12 = 0x000000a5,
21854IH_PERF_SEL_RB0_RPTR_WRAP_VF13 = 0x000000a6,
21855IH_PERF_SEL_RB0_RPTR_WRAP_VF14 = 0x000000a7,
21856IH_PERF_SEL_RB0_RPTR_WRAP_VF15 = 0x000000a8,
21857IH_PERF_SEL_RB0_RPTR_WRAP_VF16 = 0x000000a9,
21858IH_PERF_SEL_RB0_RPTR_WRAP_VF17 = 0x000000aa,
21859IH_PERF_SEL_RB0_RPTR_WRAP_VF18 = 0x000000ab,
21860IH_PERF_SEL_RB0_RPTR_WRAP_VF19 = 0x000000ac,
21861IH_PERF_SEL_RB0_RPTR_WRAP_VF20 = 0x000000ad,
21862IH_PERF_SEL_RB0_RPTR_WRAP_VF21 = 0x000000ae,
21863IH_PERF_SEL_RB0_RPTR_WRAP_VF22 = 0x000000af,
21864IH_PERF_SEL_RB0_RPTR_WRAP_VF23 = 0x000000b0,
21865IH_PERF_SEL_RB0_RPTR_WRAP_VF24 = 0x000000b1,
21866IH_PERF_SEL_RB0_RPTR_WRAP_VF25 = 0x000000b2,
21867IH_PERF_SEL_RB0_RPTR_WRAP_VF26 = 0x000000b3,
21868IH_PERF_SEL_RB0_RPTR_WRAP_VF27 = 0x000000b4,
21869IH_PERF_SEL_RB0_RPTR_WRAP_VF28 = 0x000000b5,
21870IH_PERF_SEL_RB0_RPTR_WRAP_VF29 = 0x000000b6,
21871IH_PERF_SEL_RB0_RPTR_WRAP_VF30 = 0x000000b7,
21872IH_PERF_SEL_BIF_LINE0_RISING_VF0 = 0x000000b8,
21873IH_PERF_SEL_BIF_LINE0_RISING_VF1 = 0x000000b9,
21874IH_PERF_SEL_BIF_LINE0_RISING_VF2 = 0x000000ba,
21875IH_PERF_SEL_BIF_LINE0_RISING_VF3 = 0x000000bb,
21876IH_PERF_SEL_BIF_LINE0_RISING_VF4 = 0x000000bc,
21877IH_PERF_SEL_BIF_LINE0_RISING_VF5 = 0x000000bd,
21878IH_PERF_SEL_BIF_LINE0_RISING_VF6 = 0x000000be,
21879IH_PERF_SEL_BIF_LINE0_RISING_VF7 = 0x000000bf,
21880IH_PERF_SEL_BIF_LINE0_RISING_VF8 = 0x000000c0,
21881IH_PERF_SEL_BIF_LINE0_RISING_VF9 = 0x000000c1,
21882IH_PERF_SEL_BIF_LINE0_RISING_VF10 = 0x000000c2,
21883IH_PERF_SEL_BIF_LINE0_RISING_VF11 = 0x000000c3,
21884IH_PERF_SEL_BIF_LINE0_RISING_VF12 = 0x000000c4,
21885IH_PERF_SEL_BIF_LINE0_RISING_VF13 = 0x000000c5,
21886IH_PERF_SEL_BIF_LINE0_RISING_VF14 = 0x000000c6,
21887IH_PERF_SEL_BIF_LINE0_RISING_VF15 = 0x000000c7,
21888IH_PERF_SEL_BIF_LINE0_RISING_VF16 = 0x000000c8,
21889IH_PERF_SEL_BIF_LINE0_RISING_VF17 = 0x000000c9,
21890IH_PERF_SEL_BIF_LINE0_RISING_VF18 = 0x000000ca,
21891IH_PERF_SEL_BIF_LINE0_RISING_VF19 = 0x000000cb,
21892IH_PERF_SEL_BIF_LINE0_RISING_VF20 = 0x000000cc,
21893IH_PERF_SEL_BIF_LINE0_RISING_VF21 = 0x000000cd,
21894IH_PERF_SEL_BIF_LINE0_RISING_VF22 = 0x000000ce,
21895IH_PERF_SEL_BIF_LINE0_RISING_VF23 = 0x000000cf,
21896IH_PERF_SEL_BIF_LINE0_RISING_VF24 = 0x000000d0,
21897IH_PERF_SEL_BIF_LINE0_RISING_VF25 = 0x000000d1,
21898IH_PERF_SEL_BIF_LINE0_RISING_VF26 = 0x000000d2,
21899IH_PERF_SEL_BIF_LINE0_RISING_VF27 = 0x000000d3,
21900IH_PERF_SEL_BIF_LINE0_RISING_VF28 = 0x000000d4,
21901IH_PERF_SEL_BIF_LINE0_RISING_VF29 = 0x000000d5,
21902IH_PERF_SEL_BIF_LINE0_RISING_VF30 = 0x000000d6,
21903IH_PERF_SEL_BIF_LINE0_FALLING_VF0 = 0x000000d7,
21904IH_PERF_SEL_BIF_LINE0_FALLING_VF1 = 0x000000d8,
21905IH_PERF_SEL_BIF_LINE0_FALLING_VF2 = 0x000000d9,
21906IH_PERF_SEL_BIF_LINE0_FALLING_VF3 = 0x000000da,
21907IH_PERF_SEL_BIF_LINE0_FALLING_VF4 = 0x000000db,
21908IH_PERF_SEL_BIF_LINE0_FALLING_VF5 = 0x000000dc,
21909IH_PERF_SEL_BIF_LINE0_FALLING_VF6 = 0x000000dd,
21910IH_PERF_SEL_BIF_LINE0_FALLING_VF7 = 0x000000de,
21911IH_PERF_SEL_BIF_LINE0_FALLING_VF8 = 0x000000df,
21912IH_PERF_SEL_BIF_LINE0_FALLING_VF9 = 0x000000e0,
21913IH_PERF_SEL_BIF_LINE0_FALLING_VF10 = 0x000000e1,
21914IH_PERF_SEL_BIF_LINE0_FALLING_VF11 = 0x000000e2,
21915IH_PERF_SEL_BIF_LINE0_FALLING_VF12 = 0x000000e3,
21916IH_PERF_SEL_BIF_LINE0_FALLING_VF13 = 0x000000e4,
21917IH_PERF_SEL_BIF_LINE0_FALLING_VF14 = 0x000000e5,
21918IH_PERF_SEL_BIF_LINE0_FALLING_VF15 = 0x000000e6,
21919IH_PERF_SEL_BIF_LINE0_FALLING_VF16 = 0x000000e7,
21920IH_PERF_SEL_BIF_LINE0_FALLING_VF17 = 0x000000e8,
21921IH_PERF_SEL_BIF_LINE0_FALLING_VF18 = 0x000000e9,
21922IH_PERF_SEL_BIF_LINE0_FALLING_VF19 = 0x000000ea,
21923IH_PERF_SEL_BIF_LINE0_FALLING_VF20 = 0x000000eb,
21924IH_PERF_SEL_BIF_LINE0_FALLING_VF21 = 0x000000ec,
21925IH_PERF_SEL_BIF_LINE0_FALLING_VF22 = 0x000000ed,
21926IH_PERF_SEL_BIF_LINE0_FALLING_VF23 = 0x000000ee,
21927IH_PERF_SEL_BIF_LINE0_FALLING_VF24 = 0x000000ef,
21928IH_PERF_SEL_BIF_LINE0_FALLING_VF25 = 0x000000f0,
21929IH_PERF_SEL_BIF_LINE0_FALLING_VF26 = 0x000000f1,
21930IH_PERF_SEL_BIF_LINE0_FALLING_VF27 = 0x000000f2,
21931IH_PERF_SEL_BIF_LINE0_FALLING_VF28 = 0x000000f3,
21932IH_PERF_SEL_BIF_LINE0_FALLING_VF29 = 0x000000f4,
21933IH_PERF_SEL_BIF_LINE0_FALLING_VF30 = 0x000000f5,
21934IH_PERF_SEL_CLIENT0_INT = 0x000000f6,
21935IH_PERF_SEL_CLIENT1_INT = 0x000000f7,
21936IH_PERF_SEL_CLIENT2_INT = 0x000000f8,
21937IH_PERF_SEL_CLIENT3_INT = 0x000000f9,
21938IH_PERF_SEL_CLIENT4_INT = 0x000000fa,
21939IH_PERF_SEL_CLIENT5_INT = 0x000000fb,
21940IH_PERF_SEL_CLIENT6_INT = 0x000000fc,
21941IH_PERF_SEL_CLIENT7_INT = 0x000000fd,
21942IH_PERF_SEL_CLIENT8_INT = 0x000000fe,
21943IH_PERF_SEL_CLIENT9_INT = 0x000000ff,
21944IH_PERF_SEL_CLIENT10_INT = 0x00000100,
21945IH_PERF_SEL_CLIENT11_INT = 0x00000101,
21946IH_PERF_SEL_CLIENT12_INT = 0x00000102,
21947IH_PERF_SEL_CLIENT13_INT = 0x00000103,
21948IH_PERF_SEL_CLIENT14_INT = 0x00000104,
21949IH_PERF_SEL_CLIENT15_INT = 0x00000105,
21950IH_PERF_SEL_CLIENT16_INT = 0x00000106,
21951IH_PERF_SEL_CLIENT17_INT = 0x00000107,
21952IH_PERF_SEL_CLIENT18_INT = 0x00000108,
21953IH_PERF_SEL_CLIENT19_INT = 0x00000109,
21954IH_PERF_SEL_CLIENT20_INT = 0x0000010a,
21955IH_PERF_SEL_CLIENT21_INT = 0x0000010b,
21956IH_PERF_SEL_CLIENT22_INT = 0x0000010c,
21957IH_PERF_SEL_CLIENT23_INT = 0x0000010d,
21958IH_PERF_SEL_CLIENT24_INT = 0x0000010e,
21959IH_PERF_SEL_CLIENT25_INT = 0x0000010f,
21960IH_PERF_SEL_CLIENT26_INT = 0x00000110,
21961IH_PERF_SEL_CLIENT27_INT = 0x00000111,
21962IH_PERF_SEL_CLIENT28_INT = 0x00000112,
21963IH_PERF_SEL_CLIENT29_INT = 0x00000113,
21964IH_PERF_SEL_CLIENT30_INT = 0x00000114,
21965IH_PERF_SEL_CLIENT31_INT = 0x00000115,
21966IH_PERF_SEL_RB1_FULL_VF0 = 0x00000116,
21967IH_PERF_SEL_RB1_FULL_VF1 = 0x00000117,
21968IH_PERF_SEL_RB1_FULL_VF2 = 0x00000118,
21969IH_PERF_SEL_RB1_FULL_VF3 = 0x00000119,
21970IH_PERF_SEL_RB1_FULL_VF4 = 0x0000011a,
21971IH_PERF_SEL_RB1_FULL_VF5 = 0x0000011b,
21972IH_PERF_SEL_RB1_FULL_VF6 = 0x0000011c,
21973IH_PERF_SEL_RB1_FULL_VF7 = 0x0000011d,
21974IH_PERF_SEL_RB1_FULL_VF8 = 0x0000011e,
21975IH_PERF_SEL_RB1_FULL_VF9 = 0x0000011f,
21976IH_PERF_SEL_RB1_FULL_VF10 = 0x00000120,
21977IH_PERF_SEL_RB1_FULL_VF11 = 0x00000121,
21978IH_PERF_SEL_RB1_FULL_VF12 = 0x00000122,
21979IH_PERF_SEL_RB1_FULL_VF13 = 0x00000123,
21980IH_PERF_SEL_RB1_FULL_VF14 = 0x00000124,
21981IH_PERF_SEL_RB1_FULL_VF15 = 0x00000125,
21982IH_PERF_SEL_RB1_FULL_VF16 = 0x00000126,
21983IH_PERF_SEL_RB1_FULL_VF17 = 0x00000127,
21984IH_PERF_SEL_RB1_FULL_VF18 = 0x00000128,
21985IH_PERF_SEL_RB1_FULL_VF19 = 0x00000129,
21986IH_PERF_SEL_RB1_FULL_VF20 = 0x0000012a,
21987IH_PERF_SEL_RB1_FULL_VF21 = 0x0000012b,
21988IH_PERF_SEL_RB1_FULL_VF22 = 0x0000012c,
21989IH_PERF_SEL_RB1_FULL_VF23 = 0x0000012d,
21990IH_PERF_SEL_RB1_FULL_VF24 = 0x0000012e,
21991IH_PERF_SEL_RB1_FULL_VF25 = 0x0000012f,
21992IH_PERF_SEL_RB1_FULL_VF26 = 0x00000130,
21993IH_PERF_SEL_RB1_FULL_VF27 = 0x00000131,
21994IH_PERF_SEL_RB1_FULL_VF28 = 0x00000132,
21995IH_PERF_SEL_RB1_FULL_VF29 = 0x00000133,
21996IH_PERF_SEL_RB1_FULL_VF30 = 0x00000134,
21997IH_PERF_SEL_RB1_OVERFLOW_VF0 = 0x00000135,
21998IH_PERF_SEL_RB1_OVERFLOW_VF1 = 0x00000136,
21999IH_PERF_SEL_RB1_OVERFLOW_VF2 = 0x00000137,
22000IH_PERF_SEL_RB1_OVERFLOW_VF3 = 0x00000138,
22001IH_PERF_SEL_RB1_OVERFLOW_VF4 = 0x00000139,
22002IH_PERF_SEL_RB1_OVERFLOW_VF5 = 0x0000013a,
22003IH_PERF_SEL_RB1_OVERFLOW_VF6 = 0x0000013b,
22004IH_PERF_SEL_RB1_OVERFLOW_VF7 = 0x0000013c,
22005IH_PERF_SEL_RB1_OVERFLOW_VF8 = 0x0000013d,
22006IH_PERF_SEL_RB1_OVERFLOW_VF9 = 0x0000013e,
22007IH_PERF_SEL_RB1_OVERFLOW_VF10 = 0x0000013f,
22008IH_PERF_SEL_RB1_OVERFLOW_VF11 = 0x00000140,
22009IH_PERF_SEL_RB1_OVERFLOW_VF12 = 0x00000141,
22010IH_PERF_SEL_RB1_OVERFLOW_VF13 = 0x00000142,
22011IH_PERF_SEL_RB1_OVERFLOW_VF14 = 0x00000143,
22012IH_PERF_SEL_RB1_OVERFLOW_VF15 = 0x00000144,
22013IH_PERF_SEL_RB1_OVERFLOW_VF16 = 0x00000145,
22014IH_PERF_SEL_RB1_OVERFLOW_VF17 = 0x00000146,
22015IH_PERF_SEL_RB1_OVERFLOW_VF18 = 0x00000147,
22016IH_PERF_SEL_RB1_OVERFLOW_VF19 = 0x00000148,
22017IH_PERF_SEL_RB1_OVERFLOW_VF20 = 0x00000149,
22018IH_PERF_SEL_RB1_OVERFLOW_VF21 = 0x0000014a,
22019IH_PERF_SEL_RB1_OVERFLOW_VF22 = 0x0000014b,
22020IH_PERF_SEL_RB1_OVERFLOW_VF23 = 0x0000014c,
22021IH_PERF_SEL_RB1_OVERFLOW_VF24 = 0x0000014d,
22022IH_PERF_SEL_RB1_OVERFLOW_VF25 = 0x0000014e,
22023IH_PERF_SEL_RB1_OVERFLOW_VF26 = 0x0000014f,
22024IH_PERF_SEL_RB1_OVERFLOW_VF27 = 0x00000150,
22025IH_PERF_SEL_RB1_OVERFLOW_VF28 = 0x00000151,
22026IH_PERF_SEL_RB1_OVERFLOW_VF29 = 0x00000152,
22027IH_PERF_SEL_RB1_OVERFLOW_VF30 = 0x00000153,
22028IH_PERF_SEL_RB1_WPTR_WRAP_VF0 = 0x00000154,
22029IH_PERF_SEL_RB1_WPTR_WRAP_VF1 = 0x00000155,
22030IH_PERF_SEL_RB1_WPTR_WRAP_VF2 = 0x00000156,
22031IH_PERF_SEL_RB1_WPTR_WRAP_VF3 = 0x00000157,
22032IH_PERF_SEL_RB1_WPTR_WRAP_VF4 = 0x00000158,
22033IH_PERF_SEL_RB1_WPTR_WRAP_VF5 = 0x00000159,
22034IH_PERF_SEL_RB1_WPTR_WRAP_VF6 = 0x0000015a,
22035IH_PERF_SEL_RB1_WPTR_WRAP_VF7 = 0x0000015b,
22036IH_PERF_SEL_RB1_WPTR_WRAP_VF8 = 0x0000015c,
22037IH_PERF_SEL_RB1_WPTR_WRAP_VF9 = 0x0000015d,
22038IH_PERF_SEL_RB1_WPTR_WRAP_VF10 = 0x0000015e,
22039IH_PERF_SEL_RB1_WPTR_WRAP_VF11 = 0x0000015f,
22040IH_PERF_SEL_RB1_WPTR_WRAP_VF12 = 0x00000160,
22041IH_PERF_SEL_RB1_WPTR_WRAP_VF13 = 0x00000161,
22042IH_PERF_SEL_RB1_WPTR_WRAP_VF14 = 0x00000162,
22043IH_PERF_SEL_RB1_WPTR_WRAP_VF15 = 0x00000163,
22044IH_PERF_SEL_RB1_WPTR_WRAP_VF16 = 0x00000164,
22045IH_PERF_SEL_RB1_WPTR_WRAP_VF17 = 0x00000165,
22046IH_PERF_SEL_RB1_WPTR_WRAP_VF18 = 0x00000166,
22047IH_PERF_SEL_RB1_WPTR_WRAP_VF19 = 0x00000167,
22048IH_PERF_SEL_RB1_WPTR_WRAP_VF20 = 0x00000168,
22049IH_PERF_SEL_RB1_WPTR_WRAP_VF21 = 0x00000169,
22050IH_PERF_SEL_RB1_WPTR_WRAP_VF22 = 0x0000016a,
22051IH_PERF_SEL_RB1_WPTR_WRAP_VF23 = 0x0000016b,
22052IH_PERF_SEL_RB1_WPTR_WRAP_VF24 = 0x0000016c,
22053IH_PERF_SEL_RB1_WPTR_WRAP_VF25 = 0x0000016d,
22054IH_PERF_SEL_RB1_WPTR_WRAP_VF26 = 0x0000016e,
22055IH_PERF_SEL_RB1_WPTR_WRAP_VF27 = 0x0000016f,
22056IH_PERF_SEL_RB1_WPTR_WRAP_VF28 = 0x00000170,
22057IH_PERF_SEL_RB1_WPTR_WRAP_VF29 = 0x00000171,
22058IH_PERF_SEL_RB1_WPTR_WRAP_VF30 = 0x00000172,
22059IH_PERF_SEL_RB1_RPTR_WRAP_VF0 = 0x00000173,
22060IH_PERF_SEL_RB1_RPTR_WRAP_VF1 = 0x00000174,
22061IH_PERF_SEL_RB1_RPTR_WRAP_VF2 = 0x00000175,
22062IH_PERF_SEL_RB1_RPTR_WRAP_VF3 = 0x00000176,
22063IH_PERF_SEL_RB1_RPTR_WRAP_VF4 = 0x00000177,
22064IH_PERF_SEL_RB1_RPTR_WRAP_VF5 = 0x00000178,
22065IH_PERF_SEL_RB1_RPTR_WRAP_VF6 = 0x00000179,
22066IH_PERF_SEL_RB1_RPTR_WRAP_VF7 = 0x0000017a,
22067IH_PERF_SEL_RB1_RPTR_WRAP_VF8 = 0x0000017b,
22068IH_PERF_SEL_RB1_RPTR_WRAP_VF9 = 0x0000017c,
22069IH_PERF_SEL_RB1_RPTR_WRAP_VF10 = 0x0000017d,
22070IH_PERF_SEL_RB1_RPTR_WRAP_VF11 = 0x0000017e,
22071IH_PERF_SEL_RB1_RPTR_WRAP_VF12 = 0x0000017f,
22072IH_PERF_SEL_RB1_RPTR_WRAP_VF13 = 0x00000180,
22073IH_PERF_SEL_RB1_RPTR_WRAP_VF14 = 0x00000181,
22074IH_PERF_SEL_RB1_RPTR_WRAP_VF15 = 0x00000182,
22075IH_PERF_SEL_RB1_RPTR_WRAP_VF16 = 0x00000183,
22076IH_PERF_SEL_RB1_RPTR_WRAP_VF17 = 0x00000184,
22077IH_PERF_SEL_RB1_RPTR_WRAP_VF18 = 0x00000185,
22078IH_PERF_SEL_RB1_RPTR_WRAP_VF19 = 0x00000186,
22079IH_PERF_SEL_RB1_RPTR_WRAP_VF20 = 0x00000187,
22080IH_PERF_SEL_RB1_RPTR_WRAP_VF21 = 0x00000188,
22081IH_PERF_SEL_RB1_RPTR_WRAP_VF22 = 0x00000189,
22082IH_PERF_SEL_RB1_RPTR_WRAP_VF23 = 0x0000018a,
22083IH_PERF_SEL_RB1_RPTR_WRAP_VF24 = 0x0000018b,
22084IH_PERF_SEL_RB1_RPTR_WRAP_VF25 = 0x0000018c,
22085IH_PERF_SEL_RB1_RPTR_WRAP_VF26 = 0x0000018d,
22086IH_PERF_SEL_RB1_RPTR_WRAP_VF27 = 0x0000018e,
22087IH_PERF_SEL_RB1_RPTR_WRAP_VF28 = 0x0000018f,
22088IH_PERF_SEL_RB1_RPTR_WRAP_VF29 = 0x00000190,
22089IH_PERF_SEL_RB1_RPTR_WRAP_VF30 = 0x00000191,
22090IH_PERF_SEL_RB2_FULL_VF0 = 0x00000192,
22091IH_PERF_SEL_RB2_FULL_VF1 = 0x00000193,
22092IH_PERF_SEL_RB2_FULL_VF2 = 0x00000194,
22093IH_PERF_SEL_RB2_FULL_VF3 = 0x00000195,
22094IH_PERF_SEL_RB2_FULL_VF4 = 0x00000196,
22095IH_PERF_SEL_RB2_FULL_VF5 = 0x00000197,
22096IH_PERF_SEL_RB2_FULL_VF6 = 0x00000198,
22097IH_PERF_SEL_RB2_FULL_VF7 = 0x00000199,
22098IH_PERF_SEL_RB2_FULL_VF8 = 0x0000019a,
22099IH_PERF_SEL_RB2_FULL_VF9 = 0x0000019b,
22100IH_PERF_SEL_RB2_FULL_VF10 = 0x0000019c,
22101IH_PERF_SEL_RB2_FULL_VF11 = 0x0000019d,
22102IH_PERF_SEL_RB2_FULL_VF12 = 0x0000019e,
22103IH_PERF_SEL_RB2_FULL_VF13 = 0x0000019f,
22104IH_PERF_SEL_RB2_FULL_VF14 = 0x000001a0,
22105IH_PERF_SEL_RB2_FULL_VF15 = 0x000001a1,
22106IH_PERF_SEL_RB2_FULL_VF16 = 0x000001a2,
22107IH_PERF_SEL_RB2_FULL_VF17 = 0x000001a3,
22108IH_PERF_SEL_RB2_FULL_VF18 = 0x000001a4,
22109IH_PERF_SEL_RB2_FULL_VF19 = 0x000001a5,
22110IH_PERF_SEL_RB2_FULL_VF20 = 0x000001a6,
22111IH_PERF_SEL_RB2_FULL_VF21 = 0x000001a7,
22112IH_PERF_SEL_RB2_FULL_VF22 = 0x000001a8,
22113IH_PERF_SEL_RB2_FULL_VF23 = 0x000001a9,
22114IH_PERF_SEL_RB2_FULL_VF24 = 0x000001aa,
22115IH_PERF_SEL_RB2_FULL_VF25 = 0x000001ab,
22116IH_PERF_SEL_RB2_FULL_VF26 = 0x000001ac,
22117IH_PERF_SEL_RB2_FULL_VF27 = 0x000001ad,
22118IH_PERF_SEL_RB2_FULL_VF28 = 0x000001ae,
22119IH_PERF_SEL_RB2_FULL_VF29 = 0x000001af,
22120IH_PERF_SEL_RB2_FULL_VF30 = 0x000001b0,
22121IH_PERF_SEL_RB2_OVERFLOW_VF0 = 0x000001b1,
22122IH_PERF_SEL_RB2_OVERFLOW_VF1 = 0x000001b2,
22123IH_PERF_SEL_RB2_OVERFLOW_VF2 = 0x000001b3,
22124IH_PERF_SEL_RB2_OVERFLOW_VF3 = 0x000001b4,
22125IH_PERF_SEL_RB2_OVERFLOW_VF4 = 0x000001b5,
22126IH_PERF_SEL_RB2_OVERFLOW_VF5 = 0x000001b6,
22127IH_PERF_SEL_RB2_OVERFLOW_VF6 = 0x000001b7,
22128IH_PERF_SEL_RB2_OVERFLOW_VF7 = 0x000001b8,
22129IH_PERF_SEL_RB2_OVERFLOW_VF8 = 0x000001b9,
22130IH_PERF_SEL_RB2_OVERFLOW_VF9 = 0x000001ba,
22131IH_PERF_SEL_RB2_OVERFLOW_VF10 = 0x000001bb,
22132IH_PERF_SEL_RB2_OVERFLOW_VF11 = 0x000001bc,
22133IH_PERF_SEL_RB2_OVERFLOW_VF12 = 0x000001bd,
22134IH_PERF_SEL_RB2_OVERFLOW_VF13 = 0x000001be,
22135IH_PERF_SEL_RB2_OVERFLOW_VF14 = 0x000001bf,
22136IH_PERF_SEL_RB2_OVERFLOW_VF15 = 0x000001c0,
22137IH_PERF_SEL_RB2_OVERFLOW_VF16 = 0x000001c1,
22138IH_PERF_SEL_RB2_OVERFLOW_VF17 = 0x000001c2,
22139IH_PERF_SEL_RB2_OVERFLOW_VF18 = 0x000001c3,
22140IH_PERF_SEL_RB2_OVERFLOW_VF19 = 0x000001c4,
22141IH_PERF_SEL_RB2_OVERFLOW_VF20 = 0x000001c5,
22142IH_PERF_SEL_RB2_OVERFLOW_VF21 = 0x000001c6,
22143IH_PERF_SEL_RB2_OVERFLOW_VF22 = 0x000001c7,
22144IH_PERF_SEL_RB2_OVERFLOW_VF23 = 0x000001c8,
22145IH_PERF_SEL_RB2_OVERFLOW_VF24 = 0x000001c9,
22146IH_PERF_SEL_RB2_OVERFLOW_VF25 = 0x000001ca,
22147IH_PERF_SEL_RB2_OVERFLOW_VF26 = 0x000001cb,
22148IH_PERF_SEL_RB2_OVERFLOW_VF27 = 0x000001cc,
22149IH_PERF_SEL_RB2_OVERFLOW_VF28 = 0x000001cd,
22150IH_PERF_SEL_RB2_OVERFLOW_VF29 = 0x000001ce,
22151IH_PERF_SEL_RB2_OVERFLOW_VF30 = 0x000001cf,
22152IH_PERF_SEL_RB2_WPTR_WRAP_VF0 = 0x000001d0,
22153IH_PERF_SEL_RB2_WPTR_WRAP_VF1 = 0x000001d1,
22154IH_PERF_SEL_RB2_WPTR_WRAP_VF2 = 0x000001d2,
22155IH_PERF_SEL_RB2_WPTR_WRAP_VF3 = 0x000001d3,
22156IH_PERF_SEL_RB2_WPTR_WRAP_VF4 = 0x000001d4,
22157IH_PERF_SEL_RB2_WPTR_WRAP_VF5 = 0x000001d5,
22158IH_PERF_SEL_RB2_WPTR_WRAP_VF6 = 0x000001d6,
22159IH_PERF_SEL_RB2_WPTR_WRAP_VF7 = 0x000001d7,
22160IH_PERF_SEL_RB2_WPTR_WRAP_VF8 = 0x000001d8,
22161IH_PERF_SEL_RB2_WPTR_WRAP_VF9 = 0x000001d9,
22162IH_PERF_SEL_RB2_WPTR_WRAP_VF10 = 0x000001da,
22163IH_PERF_SEL_RB2_WPTR_WRAP_VF11 = 0x000001db,
22164IH_PERF_SEL_RB2_WPTR_WRAP_VF12 = 0x000001dc,
22165IH_PERF_SEL_RB2_WPTR_WRAP_VF13 = 0x000001dd,
22166IH_PERF_SEL_RB2_WPTR_WRAP_VF14 = 0x000001de,
22167IH_PERF_SEL_RB2_WPTR_WRAP_VF15 = 0x000001df,
22168IH_PERF_SEL_RB2_WPTR_WRAP_VF16 = 0x000001e0,
22169IH_PERF_SEL_RB2_WPTR_WRAP_VF17 = 0x000001e1,
22170IH_PERF_SEL_RB2_WPTR_WRAP_VF18 = 0x000001e2,
22171IH_PERF_SEL_RB2_WPTR_WRAP_VF19 = 0x000001e3,
22172IH_PERF_SEL_RB2_WPTR_WRAP_VF20 = 0x000001e4,
22173IH_PERF_SEL_RB2_WPTR_WRAP_VF21 = 0x000001e5,
22174IH_PERF_SEL_RB2_WPTR_WRAP_VF22 = 0x000001e6,
22175IH_PERF_SEL_RB2_WPTR_WRAP_VF23 = 0x000001e7,
22176IH_PERF_SEL_RB2_WPTR_WRAP_VF24 = 0x000001e8,
22177IH_PERF_SEL_RB2_WPTR_WRAP_VF25 = 0x000001e9,
22178IH_PERF_SEL_RB2_WPTR_WRAP_VF26 = 0x000001ea,
22179IH_PERF_SEL_RB2_WPTR_WRAP_VF27 = 0x000001eb,
22180IH_PERF_SEL_RB2_WPTR_WRAP_VF28 = 0x000001ec,
22181IH_PERF_SEL_RB2_WPTR_WRAP_VF29 = 0x000001ed,
22182IH_PERF_SEL_RB2_WPTR_WRAP_VF30 = 0x000001ee,
22183IH_PERF_SEL_RB2_RPTR_WRAP_VF0 = 0x000001ef,
22184IH_PERF_SEL_RB2_RPTR_WRAP_VF1 = 0x000001f0,
22185IH_PERF_SEL_RB2_RPTR_WRAP_VF2 = 0x000001f1,
22186IH_PERF_SEL_RB2_RPTR_WRAP_VF3 = 0x000001f2,
22187IH_PERF_SEL_RB2_RPTR_WRAP_VF4 = 0x000001f3,
22188IH_PERF_SEL_RB2_RPTR_WRAP_VF5 = 0x000001f4,
22189IH_PERF_SEL_RB2_RPTR_WRAP_VF6 = 0x000001f5,
22190IH_PERF_SEL_RB2_RPTR_WRAP_VF7 = 0x000001f6,
22191IH_PERF_SEL_RB2_RPTR_WRAP_VF8 = 0x000001f7,
22192IH_PERF_SEL_RB2_RPTR_WRAP_VF9 = 0x000001f8,
22193IH_PERF_SEL_RB2_RPTR_WRAP_VF10 = 0x000001f9,
22194IH_PERF_SEL_RB2_RPTR_WRAP_VF11 = 0x000001fa,
22195IH_PERF_SEL_RB2_RPTR_WRAP_VF12 = 0x000001fb,
22196IH_PERF_SEL_RB2_RPTR_WRAP_VF13 = 0x000001fc,
22197IH_PERF_SEL_RB2_RPTR_WRAP_VF14 = 0x000001fd,
22198IH_PERF_SEL_RB2_RPTR_WRAP_VF15 = 0x000001fe,
22199IH_PERF_SEL_RB2_RPTR_WRAP_VF16 = 0x000001ff,
22200IH_PERF_SEL_RB2_RPTR_WRAP_VF17 = 0x00000200,
22201IH_PERF_SEL_RB2_RPTR_WRAP_VF18 = 0x00000201,
22202IH_PERF_SEL_RB2_RPTR_WRAP_VF19 = 0x00000202,
22203IH_PERF_SEL_RB2_RPTR_WRAP_VF20 = 0x00000203,
22204IH_PERF_SEL_RB2_RPTR_WRAP_VF21 = 0x00000204,
22205IH_PERF_SEL_RB2_RPTR_WRAP_VF22 = 0x00000205,
22206IH_PERF_SEL_RB2_RPTR_WRAP_VF23 = 0x00000206,
22207IH_PERF_SEL_RB2_RPTR_WRAP_VF24 = 0x00000207,
22208IH_PERF_SEL_RB2_RPTR_WRAP_VF25 = 0x00000208,
22209IH_PERF_SEL_RB2_RPTR_WRAP_VF26 = 0x00000209,
22210IH_PERF_SEL_RB2_RPTR_WRAP_VF27 = 0x0000020a,
22211IH_PERF_SEL_RB2_RPTR_WRAP_VF28 = 0x0000020b,
22212IH_PERF_SEL_RB2_RPTR_WRAP_VF29 = 0x0000020c,
22213IH_PERF_SEL_RB2_RPTR_WRAP_VF30 = 0x0000020d,
22214IH_PERF_SEL_RB0_FULL_DRAIN_DROP = 0x0000020e,
22215IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF0 = 0x0000020f,
22216IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF1 = 0x00000210,
22217IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF2 = 0x00000211,
22218IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF3 = 0x00000212,
22219IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF4 = 0x00000213,
22220IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF5 = 0x00000214,
22221IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF6 = 0x00000215,
22222IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF7 = 0x00000216,
22223IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF8 = 0x00000217,
22224IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF9 = 0x00000218,
22225IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF10 = 0x00000219,
22226IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF11 = 0x0000021a,
22227IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF12 = 0x0000021b,
22228IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF13 = 0x0000021c,
22229IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF14 = 0x0000021d,
22230IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF15 = 0x0000021e,
22231IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF16 = 0x0000021f,
22232IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF17 = 0x00000220,
22233IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF18 = 0x00000221,
22234IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF19 = 0x00000222,
22235IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF20 = 0x00000223,
22236IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF21 = 0x00000224,
22237IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF22 = 0x00000225,
22238IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF23 = 0x00000226,
22239IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF24 = 0x00000227,
22240IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF25 = 0x00000228,
22241IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF26 = 0x00000229,
22242IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF27 = 0x0000022a,
22243IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF28 = 0x0000022b,
22244IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF29 = 0x0000022c,
22245IH_PERF_SEL_RB0_FULL_DRAIN_DROP_VF30 = 0x0000022d,
22246IH_PERF_SEL_RB1_FULL_DRAIN_DROP = 0x0000022e,
22247IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF0 = 0x0000022f,
22248IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF1 = 0x00000230,
22249IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF2 = 0x00000231,
22250IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF3 = 0x00000232,
22251IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF4 = 0x00000233,
22252IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF5 = 0x00000234,
22253IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF6 = 0x00000235,
22254IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF7 = 0x00000236,
22255IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF8 = 0x00000237,
22256IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF9 = 0x00000238,
22257IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF10 = 0x00000239,
22258IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF11 = 0x0000023a,
22259IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF12 = 0x0000023b,
22260IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF13 = 0x0000023c,
22261IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF14 = 0x0000023d,
22262IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF15 = 0x0000023e,
22263IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF16 = 0x0000023f,
22264IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF17 = 0x00000240,
22265IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF18 = 0x00000241,
22266IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF19 = 0x00000242,
22267IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF20 = 0x00000243,
22268IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF21 = 0x00000244,
22269IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF22 = 0x00000245,
22270IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF23 = 0x00000246,
22271IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF24 = 0x00000247,
22272IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF25 = 0x00000248,
22273IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF26 = 0x00000249,
22274IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF27 = 0x0000024a,
22275IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF28 = 0x0000024b,
22276IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF29 = 0x0000024c,
22277IH_PERF_SEL_RB1_FULL_DRAIN_DROP_VF30 = 0x0000024d,
22278IH_PERF_SEL_RB2_FULL_DRAIN_DROP = 0x0000024e,
22279IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF0 = 0x0000024f,
22280IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF1 = 0x00000250,
22281IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF2 = 0x00000251,
22282IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF3 = 0x00000252,
22283IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF4 = 0x00000253,
22284IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF5 = 0x00000254,
22285IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF6 = 0x00000255,
22286IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF7 = 0x00000256,
22287IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF8 = 0x00000257,
22288IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF9 = 0x00000258,
22289IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF10 = 0x00000259,
22290IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF11 = 0x0000025a,
22291IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF12 = 0x0000025b,
22292IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF13 = 0x0000025c,
22293IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF14 = 0x0000025d,
22294IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF15 = 0x0000025e,
22295IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF16 = 0x0000025f,
22296IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF17 = 0x00000260,
22297IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF18 = 0x00000261,
22298IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF19 = 0x00000262,
22299IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF20 = 0x00000263,
22300IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF21 = 0x00000264,
22301IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF22 = 0x00000265,
22302IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF23 = 0x00000266,
22303IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF24 = 0x00000267,
22304IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF25 = 0x00000268,
22305IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF26 = 0x00000269,
22306IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF27 = 0x0000026a,
22307IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF28 = 0x0000026b,
22308IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF29 = 0x0000026c,
22309IH_PERF_SEL_RB2_FULL_DRAIN_DROP_VF30 = 0x0000026d,
22310IH_PERF_SEL_RB0_LOAD_RPTR = 0x0000026e,
22311IH_PERF_SEL_RB0_LOAD_RPTR_VF0 = 0x0000026f,
22312IH_PERF_SEL_RB0_LOAD_RPTR_VF1 = 0x00000270,
22313IH_PERF_SEL_RB0_LOAD_RPTR_VF2 = 0x00000271,
22314IH_PERF_SEL_RB0_LOAD_RPTR_VF3 = 0x00000272,
22315IH_PERF_SEL_RB0_LOAD_RPTR_VF4 = 0x00000273,
22316IH_PERF_SEL_RB0_LOAD_RPTR_VF5 = 0x00000274,
22317IH_PERF_SEL_RB0_LOAD_RPTR_VF6 = 0x00000275,
22318IH_PERF_SEL_RB0_LOAD_RPTR_VF7 = 0x00000276,
22319IH_PERF_SEL_RB0_LOAD_RPTR_VF8 = 0x00000277,
22320IH_PERF_SEL_RB0_LOAD_RPTR_VF9 = 0x00000278,
22321IH_PERF_SEL_RB0_LOAD_RPTR_VF10 = 0x00000279,
22322IH_PERF_SEL_RB0_LOAD_RPTR_VF11 = 0x0000027a,
22323IH_PERF_SEL_RB0_LOAD_RPTR_VF12 = 0x0000027b,
22324IH_PERF_SEL_RB0_LOAD_RPTR_VF13 = 0x0000027c,
22325IH_PERF_SEL_RB0_LOAD_RPTR_VF14 = 0x0000027d,
22326IH_PERF_SEL_RB0_LOAD_RPTR_VF15 = 0x0000027e,
22327IH_PERF_SEL_RB0_LOAD_RPTR_VF16 = 0x0000027f,
22328IH_PERF_SEL_RB0_LOAD_RPTR_VF17 = 0x00000280,
22329IH_PERF_SEL_RB0_LOAD_RPTR_VF18 = 0x00000281,
22330IH_PERF_SEL_RB0_LOAD_RPTR_VF19 = 0x00000282,
22331IH_PERF_SEL_RB0_LOAD_RPTR_VF20 = 0x00000283,
22332IH_PERF_SEL_RB0_LOAD_RPTR_VF21 = 0x00000284,
22333IH_PERF_SEL_RB0_LOAD_RPTR_VF22 = 0x00000285,
22334IH_PERF_SEL_RB0_LOAD_RPTR_VF23 = 0x00000286,
22335IH_PERF_SEL_RB0_LOAD_RPTR_VF24 = 0x00000287,
22336IH_PERF_SEL_RB0_LOAD_RPTR_VF25 = 0x00000288,
22337IH_PERF_SEL_RB0_LOAD_RPTR_VF26 = 0x00000289,
22338IH_PERF_SEL_RB0_LOAD_RPTR_VF27 = 0x0000028a,
22339IH_PERF_SEL_RB0_LOAD_RPTR_VF28 = 0x0000028b,
22340IH_PERF_SEL_RB0_LOAD_RPTR_VF29 = 0x0000028c,
22341IH_PERF_SEL_RB0_LOAD_RPTR_VF30 = 0x0000028d,
22342IH_PERF_SEL_RB1_LOAD_RPTR = 0x0000028e,
22343IH_PERF_SEL_RB1_LOAD_RPTR_VF0 = 0x0000028f,
22344IH_PERF_SEL_RB1_LOAD_RPTR_VF1 = 0x00000290,
22345IH_PERF_SEL_RB1_LOAD_RPTR_VF2 = 0x00000291,
22346IH_PERF_SEL_RB1_LOAD_RPTR_VF3 = 0x00000292,
22347IH_PERF_SEL_RB1_LOAD_RPTR_VF4 = 0x00000293,
22348IH_PERF_SEL_RB1_LOAD_RPTR_VF5 = 0x00000294,
22349IH_PERF_SEL_RB1_LOAD_RPTR_VF6 = 0x00000295,
22350IH_PERF_SEL_RB1_LOAD_RPTR_VF7 = 0x00000296,
22351IH_PERF_SEL_RB1_LOAD_RPTR_VF8 = 0x00000297,
22352IH_PERF_SEL_RB1_LOAD_RPTR_VF9 = 0x00000298,
22353IH_PERF_SEL_RB1_LOAD_RPTR_VF10 = 0x00000299,
22354IH_PERF_SEL_RB1_LOAD_RPTR_VF11 = 0x0000029a,
22355IH_PERF_SEL_RB1_LOAD_RPTR_VF12 = 0x0000029b,
22356IH_PERF_SEL_RB1_LOAD_RPTR_VF13 = 0x0000029c,
22357IH_PERF_SEL_RB1_LOAD_RPTR_VF14 = 0x0000029d,
22358IH_PERF_SEL_RB1_LOAD_RPTR_VF15 = 0x0000029e,
22359IH_PERF_SEL_RB1_LOAD_RPTR_VF16 = 0x0000029f,
22360IH_PERF_SEL_RB1_LOAD_RPTR_VF17 = 0x000002a0,
22361IH_PERF_SEL_RB1_LOAD_RPTR_VF18 = 0x000002a1,
22362IH_PERF_SEL_RB1_LOAD_RPTR_VF19 = 0x000002a2,
22363IH_PERF_SEL_RB1_LOAD_RPTR_VF20 = 0x000002a3,
22364IH_PERF_SEL_RB1_LOAD_RPTR_VF21 = 0x000002a4,
22365IH_PERF_SEL_RB1_LOAD_RPTR_VF22 = 0x000002a5,
22366IH_PERF_SEL_RB1_LOAD_RPTR_VF23 = 0x000002a6,
22367IH_PERF_SEL_RB1_LOAD_RPTR_VF24 = 0x000002a7,
22368IH_PERF_SEL_RB1_LOAD_RPTR_VF25 = 0x000002a8,
22369IH_PERF_SEL_RB1_LOAD_RPTR_VF26 = 0x000002a9,
22370IH_PERF_SEL_RB1_LOAD_RPTR_VF27 = 0x000002aa,
22371IH_PERF_SEL_RB1_LOAD_RPTR_VF28 = 0x000002ab,
22372IH_PERF_SEL_RB1_LOAD_RPTR_VF29 = 0x000002ac,
22373IH_PERF_SEL_RB1_LOAD_RPTR_VF30 = 0x000002ad,
22374IH_PERF_SEL_RB2_LOAD_RPTR = 0x000002ae,
22375IH_PERF_SEL_RB2_LOAD_RPTR_VF0 = 0x000002af,
22376IH_PERF_SEL_RB2_LOAD_RPTR_VF1 = 0x000002b0,
22377IH_PERF_SEL_RB2_LOAD_RPTR_VF2 = 0x000002b1,
22378IH_PERF_SEL_RB2_LOAD_RPTR_VF3 = 0x000002b2,
22379IH_PERF_SEL_RB2_LOAD_RPTR_VF4 = 0x000002b3,
22380IH_PERF_SEL_RB2_LOAD_RPTR_VF5 = 0x000002b4,
22381IH_PERF_SEL_RB2_LOAD_RPTR_VF6 = 0x000002b5,
22382IH_PERF_SEL_RB2_LOAD_RPTR_VF7 = 0x000002b6,
22383IH_PERF_SEL_RB2_LOAD_RPTR_VF8 = 0x000002b7,
22384IH_PERF_SEL_RB2_LOAD_RPTR_VF9 = 0x000002b8,
22385IH_PERF_SEL_RB2_LOAD_RPTR_VF10 = 0x000002b9,
22386IH_PERF_SEL_RB2_LOAD_RPTR_VF11 = 0x000002ba,
22387IH_PERF_SEL_RB2_LOAD_RPTR_VF12 = 0x000002bb,
22388IH_PERF_SEL_RB2_LOAD_RPTR_VF13 = 0x000002bc,
22389IH_PERF_SEL_RB2_LOAD_RPTR_VF14 = 0x000002bd,
22390IH_PERF_SEL_RB2_LOAD_RPTR_VF15 = 0x000002be,
22391IH_PERF_SEL_RB2_LOAD_RPTR_VF16 = 0x000002bf,
22392IH_PERF_SEL_RB2_LOAD_RPTR_VF17 = 0x000002c0,
22393IH_PERF_SEL_RB2_LOAD_RPTR_VF18 = 0x000002c1,
22394IH_PERF_SEL_RB2_LOAD_RPTR_VF19 = 0x000002c2,
22395IH_PERF_SEL_RB2_LOAD_RPTR_VF20 = 0x000002c3,
22396IH_PERF_SEL_RB2_LOAD_RPTR_VF21 = 0x000002c4,
22397IH_PERF_SEL_RB2_LOAD_RPTR_VF22 = 0x000002c5,
22398IH_PERF_SEL_RB2_LOAD_RPTR_VF23 = 0x000002c6,
22399IH_PERF_SEL_RB2_LOAD_RPTR_VF24 = 0x000002c7,
22400IH_PERF_SEL_RB2_LOAD_RPTR_VF25 = 0x000002c8,
22401IH_PERF_SEL_RB2_LOAD_RPTR_VF26 = 0x000002c9,
22402IH_PERF_SEL_RB2_LOAD_RPTR_VF27 = 0x000002ca,
22403IH_PERF_SEL_RB2_LOAD_RPTR_VF28 = 0x000002cb,
22404IH_PERF_SEL_RB2_LOAD_RPTR_VF29 = 0x000002cc,
22405IH_PERF_SEL_RB2_LOAD_RPTR_VF30 = 0x000002cd,
22406} IH_PERF_SEL;
22407
22408/*
22409 * IH_CLIENT_TYPE enum
22410 */
22411
22412typedef enum IH_CLIENT_TYPE {
22413IH_GFX_VMID_CLIENT = 0x00000000,
22414IH_MM_VMID_CLIENT = 0x00000001,
22415IH_MULTI_VMID_CLIENT = 0x00000002,
22416IH_CLIENT_TYPE_RESERVED = 0x00000003,
22417} IH_CLIENT_TYPE;
22418
22419/*
22420 * IH_RING_ID enum
22421 */
22422
22423typedef enum IH_RING_ID {
22424IH_RING_ID_INTERRUPT = 0x00000000,
22425IH_RING_ID_REQUEST = 0x00000001,
22426IH_RING_ID_TRANSLATION = 0x00000002,
22427IH_RING_ID_RESERVED = 0x00000003,
22428} IH_RING_ID;
22429
22430/*
22431 * IH_VF_RB_SELECT enum
22432 */
22433
22434typedef enum IH_VF_RB_SELECT {
22435IH_VF_RB_SELECT_CLIENT_FCN_ID = 0x00000000,
22436IH_VF_RB_SELECT_IH_FCN_ID = 0x00000001,
22437IH_VF_RB_SELECT_PF = 0x00000002,
22438IH_VF_RB_SELECT_RESERVED = 0x00000003,
22439} IH_VF_RB_SELECT;
22440
22441/*
22442 * IH_INTERFACE_TYPE enum
22443 */
22444
22445typedef enum IH_INTERFACE_TYPE {
22446IH_LEGACY_INTERFACE = 0x00000000,
22447IH_REGISTER_WRITE_INTERFACE = 0x00000001,
22448} IH_INTERFACE_TYPE;
22449
22450/*******************************************************
22451 * SEM Enums
22452 *******************************************************/
22453
22454/*
22455 * SEM_PERF_SEL enum
22456 */
22457
22458typedef enum SEM_PERF_SEL {
22459SEM_PERF_SEL_CYCLE = 0x00000000,
22460SEM_PERF_SEL_IDLE = 0x00000001,
22461SEM_PERF_SEL_SDMA0_REQ_SIGNAL = 0x00000002,
22462SEM_PERF_SEL_SDMA1_REQ_SIGNAL = 0x00000003,
22463SEM_PERF_SEL_UVD_REQ_SIGNAL = 0x00000004,
22464SEM_PERF_SEL_VCE0_REQ_SIGNAL = 0x00000005,
22465SEM_PERF_SEL_ACP_REQ_SIGNAL = 0x00000006,
22466SEM_PERF_SEL_ISP_REQ_SIGNAL = 0x00000007,
22467SEM_PERF_SEL_VCE1_REQ_SIGNAL = 0x00000008,
22468SEM_PERF_SEL_VP8_REQ_SIGNAL = 0x00000009,
22469SEM_PERF_SEL_CPG_E0_REQ_SIGNAL = 0x0000000a,
22470SEM_PERF_SEL_CPG_E1_REQ_SIGNAL = 0x0000000b,
22471SEM_PERF_SEL_CPC1_IMME_E0_REQ_SIGNAL = 0x0000000c,
22472SEM_PERF_SEL_CPC1_IMME_E1_REQ_SIGNAL = 0x0000000d,
22473SEM_PERF_SEL_CPC1_IMME_E2_REQ_SIGNAL = 0x0000000e,
22474SEM_PERF_SEL_CPC1_IMME_E3_REQ_SIGNAL = 0x0000000f,
22475SEM_PERF_SEL_CPC2_IMME_E0_REQ_SIGNAL = 0x00000010,
22476SEM_PERF_SEL_CPC2_IMME_E1_REQ_SIGNAL = 0x00000011,
22477SEM_PERF_SEL_CPC2_IMME_E2_REQ_SIGNAL = 0x00000012,
22478SEM_PERF_SEL_CPC2_IMME_E3_REQ_SIGNAL = 0x00000013,
22479SEM_PERF_SEL_SDMA0_REQ_WAIT = 0x00000014,
22480SEM_PERF_SEL_SDMA1_REQ_WAIT = 0x00000015,
22481SEM_PERF_SEL_UVD_REQ_WAIT = 0x00000016,
22482SEM_PERF_SEL_VCE0_REQ_WAIT = 0x00000017,
22483SEM_PERF_SEL_ACP_REQ_WAIT = 0x00000018,
22484SEM_PERF_SEL_ISP_REQ_WAIT = 0x00000019,
22485SEM_PERF_SEL_VCE1_REQ_WAIT = 0x0000001a,
22486SEM_PERF_SEL_VP8_REQ_WAIT = 0x0000001b,
22487SEM_PERF_SEL_CPG_E0_REQ_WAIT = 0x0000001c,
22488SEM_PERF_SEL_CPG_E1_REQ_WAIT = 0x0000001d,
22489SEM_PERF_SEL_CPC1_IMME_E0_REQ_WAIT = 0x0000001e,
22490SEM_PERF_SEL_CPC1_IMME_E1_REQ_WAIT = 0x0000001f,
22491SEM_PERF_SEL_CPC1_IMME_E2_REQ_WAIT = 0x00000020,
22492SEM_PERF_SEL_CPC1_IMME_E3_REQ_WAIT = 0x00000021,
22493SEM_PERF_SEL_CPC2_IMME_E0_REQ_WAIT = 0x00000022,
22494SEM_PERF_SEL_CPC2_IMME_E1_REQ_WAIT = 0x00000023,
22495SEM_PERF_SEL_CPC2_IMME_E2_REQ_WAIT = 0x00000024,
22496SEM_PERF_SEL_CPC2_IMME_E3_REQ_WAIT = 0x00000025,
22497SEM_PERF_SEL_CPC1_OFFL_E0_REQ_WAIT = 0x00000026,
22498SEM_PERF_SEL_CPC1_OFFL_E1_REQ_WAIT = 0x00000027,
22499SEM_PERF_SEL_CPC1_OFFL_E2_REQ_WAIT = 0x00000028,
22500SEM_PERF_SEL_CPC1_OFFL_E3_REQ_WAIT = 0x00000029,
22501SEM_PERF_SEL_CPC1_OFFL_E4_REQ_WAIT = 0x0000002a,
22502SEM_PERF_SEL_CPC1_OFFL_E5_REQ_WAIT = 0x0000002b,
22503SEM_PERF_SEL_CPC1_OFFL_E6_REQ_WAIT = 0x0000002c,
22504SEM_PERF_SEL_CPC1_OFFL_E7_REQ_WAIT = 0x0000002d,
22505SEM_PERF_SEL_CPC1_OFFL_E8_REQ_WAIT = 0x0000002e,
22506SEM_PERF_SEL_CPC1_OFFL_E9_REQ_WAIT = 0x0000002f,
22507SEM_PERF_SEL_CPC1_OFFL_E10_REQ_WAIT = 0x00000030,
22508SEM_PERF_SEL_CPC1_OFFL_E11_REQ_WAIT = 0x00000031,
22509SEM_PERF_SEL_CPC1_OFFL_E12_REQ_WAIT = 0x00000032,
22510SEM_PERF_SEL_CPC1_OFFL_E13_REQ_WAIT = 0x00000033,
22511SEM_PERF_SEL_CPC1_OFFL_E14_REQ_WAIT = 0x00000034,
22512SEM_PERF_SEL_CPC1_OFFL_E15_REQ_WAIT = 0x00000035,
22513SEM_PERF_SEL_CPC1_OFFL_E16_REQ_WAIT = 0x00000036,
22514SEM_PERF_SEL_CPC1_OFFL_E17_REQ_WAIT = 0x00000037,
22515SEM_PERF_SEL_CPC1_OFFL_E18_REQ_WAIT = 0x00000038,
22516SEM_PERF_SEL_CPC1_OFFL_E19_REQ_WAIT = 0x00000039,
22517SEM_PERF_SEL_CPC1_OFFL_E20_REQ_WAIT = 0x0000003a,
22518SEM_PERF_SEL_CPC1_OFFL_E21_REQ_WAIT = 0x0000003b,
22519SEM_PERF_SEL_CPC1_OFFL_E22_REQ_WAIT = 0x0000003c,
22520SEM_PERF_SEL_CPC1_OFFL_E23_REQ_WAIT = 0x0000003d,
22521SEM_PERF_SEL_CPC1_OFFL_E24_REQ_WAIT = 0x0000003e,
22522SEM_PERF_SEL_CPC1_OFFL_E25_REQ_WAIT = 0x0000003f,
22523SEM_PERF_SEL_CPC1_OFFL_E26_REQ_WAIT = 0x00000040,
22524SEM_PERF_SEL_CPC1_OFFL_E27_REQ_WAIT = 0x00000041,
22525SEM_PERF_SEL_CPC1_OFFL_E28_REQ_WAIT = 0x00000042,
22526SEM_PERF_SEL_CPC1_OFFL_E29_REQ_WAIT = 0x00000043,
22527SEM_PERF_SEL_CPC1_OFFL_E30_REQ_WAIT = 0x00000044,
22528SEM_PERF_SEL_CPC1_OFFL_E31_REQ_WAIT = 0x00000045,
22529SEM_PERF_SEL_CPC2_OFFL_E0_REQ_WAIT = 0x00000046,
22530SEM_PERF_SEL_CPC2_OFFL_E1_REQ_WAIT = 0x00000047,
22531SEM_PERF_SEL_CPC2_OFFL_E2_REQ_WAIT = 0x00000048,
22532SEM_PERF_SEL_CPC2_OFFL_E3_REQ_WAIT = 0x00000049,
22533SEM_PERF_SEL_CPC2_OFFL_E4_REQ_WAIT = 0x0000004a,
22534SEM_PERF_SEL_CPC2_OFFL_E5_REQ_WAIT = 0x0000004b,
22535SEM_PERF_SEL_CPC2_OFFL_E6_REQ_WAIT = 0x0000004c,
22536SEM_PERF_SEL_CPC2_OFFL_E7_REQ_WAIT = 0x0000004d,
22537SEM_PERF_SEL_CPC2_OFFL_E8_REQ_WAIT = 0x0000004e,
22538SEM_PERF_SEL_CPC2_OFFL_E9_REQ_WAIT = 0x0000004f,
22539SEM_PERF_SEL_CPC2_OFFL_E10_REQ_WAIT = 0x00000050,
22540SEM_PERF_SEL_CPC2_OFFL_E11_REQ_WAIT = 0x00000051,
22541SEM_PERF_SEL_CPC2_OFFL_E12_REQ_WAIT = 0x00000052,
22542SEM_PERF_SEL_CPC2_OFFL_E13_REQ_WAIT = 0x00000053,
22543SEM_PERF_SEL_CPC2_OFFL_E14_REQ_WAIT = 0x00000054,
22544SEM_PERF_SEL_CPC2_OFFL_E15_REQ_WAIT = 0x00000055,
22545SEM_PERF_SEL_CPC2_OFFL_E16_REQ_WAIT = 0x00000056,
22546SEM_PERF_SEL_CPC2_OFFL_E17_REQ_WAIT = 0x00000057,
22547SEM_PERF_SEL_CPC2_OFFL_E18_REQ_WAIT = 0x00000058,
22548SEM_PERF_SEL_CPC2_OFFL_E19_REQ_WAIT = 0x00000059,
22549SEM_PERF_SEL_CPC2_OFFL_E20_REQ_WAIT = 0x0000005a,
22550SEM_PERF_SEL_CPC2_OFFL_E21_REQ_WAIT = 0x0000005b,
22551SEM_PERF_SEL_CPC2_OFFL_E22_REQ_WAIT = 0x0000005c,
22552SEM_PERF_SEL_CPC2_OFFL_E23_REQ_WAIT = 0x0000005d,
22553SEM_PERF_SEL_CPC2_OFFL_E24_REQ_WAIT = 0x0000005e,
22554SEM_PERF_SEL_CPC2_OFFL_E25_REQ_WAIT = 0x0000005f,
22555SEM_PERF_SEL_CPC2_OFFL_E26_REQ_WAIT = 0x00000060,
22556SEM_PERF_SEL_CPC2_OFFL_E27_REQ_WAIT = 0x00000061,
22557SEM_PERF_SEL_CPC2_OFFL_E28_REQ_WAIT = 0x00000062,
22558SEM_PERF_SEL_CPC2_OFFL_E29_REQ_WAIT = 0x00000063,
22559SEM_PERF_SEL_CPC2_OFFL_E30_REQ_WAIT = 0x00000064,
22560SEM_PERF_SEL_CPC2_OFFL_E31_REQ_WAIT = 0x00000065,
22561SEM_PERF_SEL_CPC1_OFFL_E0_POLL_WAIT = 0x00000066,
22562SEM_PERF_SEL_CPC1_OFFL_E1_POLL_WAIT = 0x00000067,
22563SEM_PERF_SEL_CPC1_OFFL_E2_POLL_WAIT = 0x00000068,
22564SEM_PERF_SEL_CPC1_OFFL_E3_POLL_WAIT = 0x00000069,
22565SEM_PERF_SEL_CPC1_OFFL_E4_POLL_WAIT = 0x0000006a,
22566SEM_PERF_SEL_CPC1_OFFL_E5_POLL_WAIT = 0x0000006b,
22567SEM_PERF_SEL_CPC1_OFFL_E6_POLL_WAIT = 0x0000006c,
22568SEM_PERF_SEL_CPC1_OFFL_E7_POLL_WAIT = 0x0000006d,
22569SEM_PERF_SEL_CPC1_OFFL_E8_POLL_WAIT = 0x0000006e,
22570SEM_PERF_SEL_CPC1_OFFL_E9_POLL_WAIT = 0x0000006f,
22571SEM_PERF_SEL_CPC1_OFFL_E10_POLL_WAIT = 0x00000070,
22572SEM_PERF_SEL_CPC1_OFFL_E11_POLL_WAIT = 0x00000071,
22573SEM_PERF_SEL_CPC1_OFFL_E12_POLL_WAIT = 0x00000072,
22574SEM_PERF_SEL_CPC1_OFFL_E13_POLL_WAIT = 0x00000073,
22575SEM_PERF_SEL_CPC1_OFFL_E14_POLL_WAIT = 0x00000074,
22576SEM_PERF_SEL_CPC1_OFFL_E15_POLL_WAIT = 0x00000075,
22577SEM_PERF_SEL_CPC1_OFFL_E16_POLL_WAIT = 0x00000076,
22578SEM_PERF_SEL_CPC1_OFFL_E17_POLL_WAIT = 0x00000077,
22579SEM_PERF_SEL_CPC1_OFFL_E18_POLL_WAIT = 0x00000078,
22580SEM_PERF_SEL_CPC1_OFFL_E19_POLL_WAIT = 0x00000079,
22581SEM_PERF_SEL_CPC1_OFFL_E20_POLL_WAIT = 0x0000007a,
22582SEM_PERF_SEL_CPC1_OFFL_E21_POLL_WAIT = 0x0000007b,
22583SEM_PERF_SEL_CPC1_OFFL_E22_POLL_WAIT = 0x0000007c,
22584SEM_PERF_SEL_CPC1_OFFL_E23_POLL_WAIT = 0x0000007d,
22585SEM_PERF_SEL_CPC1_OFFL_E24_POLL_WAIT = 0x0000007e,
22586SEM_PERF_SEL_CPC1_OFFL_E25_POLL_WAIT = 0x0000007f,
22587SEM_PERF_SEL_CPC1_OFFL_E26_POLL_WAIT = 0x00000080,
22588SEM_PERF_SEL_CPC1_OFFL_E27_POLL_WAIT = 0x00000081,
22589SEM_PERF_SEL_CPC1_OFFL_E28_POLL_WAIT = 0x00000082,
22590SEM_PERF_SEL_CPC1_OFFL_E29_POLL_WAIT = 0x00000083,
22591SEM_PERF_SEL_CPC1_OFFL_E30_POLL_WAIT = 0x00000084,
22592SEM_PERF_SEL_CPC1_OFFL_E31_POLL_WAIT = 0x00000085,
22593SEM_PERF_SEL_CPC2_OFFL_E0_POLL_WAIT = 0x00000086,
22594SEM_PERF_SEL_CPC2_OFFL_E1_POLL_WAIT = 0x00000087,
22595SEM_PERF_SEL_CPC2_OFFL_E2_POLL_WAIT = 0x00000088,
22596SEM_PERF_SEL_CPC2_OFFL_E3_POLL_WAIT = 0x00000089,
22597SEM_PERF_SEL_CPC2_OFFL_E4_POLL_WAIT = 0x0000008a,
22598SEM_PERF_SEL_CPC2_OFFL_E5_POLL_WAIT = 0x0000008b,
22599SEM_PERF_SEL_CPC2_OFFL_E6_POLL_WAIT = 0x0000008c,
22600SEM_PERF_SEL_CPC2_OFFL_E7_POLL_WAIT = 0x0000008d,
22601SEM_PERF_SEL_CPC2_OFFL_E8_POLL_WAIT = 0x0000008e,
22602SEM_PERF_SEL_CPC2_OFFL_E9_POLL_WAIT = 0x0000008f,
22603SEM_PERF_SEL_CPC2_OFFL_E10_POLL_WAIT = 0x00000090,
22604SEM_PERF_SEL_CPC2_OFFL_E11_POLL_WAIT = 0x00000091,
22605SEM_PERF_SEL_CPC2_OFFL_E12_POLL_WAIT = 0x00000092,
22606SEM_PERF_SEL_CPC2_OFFL_E13_POLL_WAIT = 0x00000093,
22607SEM_PERF_SEL_CPC2_OFFL_E14_POLL_WAIT = 0x00000094,
22608SEM_PERF_SEL_CPC2_OFFL_E15_POLL_WAIT = 0x00000095,
22609SEM_PERF_SEL_CPC2_OFFL_E16_POLL_WAIT = 0x00000096,
22610SEM_PERF_SEL_CPC2_OFFL_E17_POLL_WAIT = 0x00000097,
22611SEM_PERF_SEL_CPC2_OFFL_E18_POLL_WAIT = 0x00000098,
22612SEM_PERF_SEL_CPC2_OFFL_E19_POLL_WAIT = 0x00000099,
22613SEM_PERF_SEL_CPC2_OFFL_E20_POLL_WAIT = 0x0000009a,
22614SEM_PERF_SEL_CPC2_OFFL_E21_POLL_WAIT = 0x0000009b,
22615SEM_PERF_SEL_CPC2_OFFL_E22_POLL_WAIT = 0x0000009c,
22616SEM_PERF_SEL_CPC2_OFFL_E23_POLL_WAIT = 0x0000009d,
22617SEM_PERF_SEL_CPC2_OFFL_E24_POLL_WAIT = 0x0000009e,
22618SEM_PERF_SEL_CPC2_OFFL_E25_POLL_WAIT = 0x0000009f,
22619SEM_PERF_SEL_CPC2_OFFL_E26_POLL_WAIT = 0x000000a0,
22620SEM_PERF_SEL_CPC2_OFFL_E27_POLL_WAIT = 0x000000a1,
22621SEM_PERF_SEL_CPC2_OFFL_E28_POLL_WAIT = 0x000000a2,
22622SEM_PERF_SEL_CPC2_OFFL_E29_POLL_WAIT = 0x000000a3,
22623SEM_PERF_SEL_CPC2_OFFL_E30_POLL_WAIT = 0x000000a4,
22624SEM_PERF_SEL_CPC2_OFFL_E31_POLL_WAIT = 0x000000a5,
22625SEM_PERF_SEL_MC_RD_REQ = 0x000000a6,
22626SEM_PERF_SEL_MC_RD_RET = 0x000000a7,
22627SEM_PERF_SEL_MC_WR_REQ = 0x000000a8,
22628SEM_PERF_SEL_MC_WR_RET = 0x000000a9,
22629SEM_PERF_SEL_ATC_REQ = 0x000000aa,
22630SEM_PERF_SEL_ATC_RET = 0x000000ab,
22631SEM_PERF_SEL_ATC_XNACK = 0x000000ac,
22632SEM_PERF_SEL_ATC_INVALIDATION = 0x000000ad,
22633SEM_PERF_SEL_ATC_VM_INVALIDATION = 0x000000ae,
22634} SEM_PERF_SEL;
22635
22636/*******************************************************
22637 * SMUIO Enums
22638 *******************************************************/
22639
22640/*
22641 * ROM_SIGNATURE value
22642 */
22643
22644#define ROM_SIGNATURE 0x0000aa55
22645
22646/*******************************************************
22647 * UVD_EFC Enums
22648 *******************************************************/
22649
22650/*
22651 * EFC_SURFACE_PIXEL_FORMAT enum
22652 */
22653
22654typedef enum EFC_SURFACE_PIXEL_FORMAT {
22655EFC_ARGB1555 = 0x00000001,
22656EFC_RGBA5551 = 0x00000002,
22657EFC_RGB565 = 0x00000003,
22658EFC_BGR565 = 0x00000004,
22659EFC_ARGB4444 = 0x00000005,
22660EFC_RGBA4444 = 0x00000006,
22661EFC_ARGB8888 = 0x00000008,
22662EFC_RGBA8888 = 0x00000009,
22663EFC_ARGB2101010 = 0x0000000a,
22664EFC_RGBA1010102 = 0x0000000b,
22665EFC_AYCrCb8888 = 0x0000000c,
22666EFC_YCrCbA8888 = 0x0000000d,
22667EFC_ACrYCb8888 = 0x0000000e,
22668EFC_CrYCbA8888 = 0x0000000f,
22669EFC_ARGB16161616_10MSB = 0x00000010,
22670EFC_RGBA16161616_10MSB = 0x00000011,
22671EFC_ARGB16161616_10LSB = 0x00000012,
22672EFC_RGBA16161616_10LSB = 0x00000013,
22673EFC_ARGB16161616_12MSB = 0x00000014,
22674EFC_RGBA16161616_12MSB = 0x00000015,
22675EFC_ARGB16161616_12LSB = 0x00000016,
22676EFC_RGBA16161616_12LSB = 0x00000017,
22677EFC_ARGB16161616_FLOAT = 0x00000018,
22678EFC_RGBA16161616_FLOAT = 0x00000019,
22679EFC_ARGB16161616_UNORM = 0x0000001a,
22680EFC_RGBA16161616_UNORM = 0x0000001b,
22681EFC_ARGB16161616_SNORM = 0x0000001c,
22682EFC_RGBA16161616_SNORM = 0x0000001d,
22683EFC_AYCrCb16161616_10MSB = 0x00000020,
22684EFC_AYCrCb16161616_10LSB = 0x00000021,
22685EFC_YCrCbA16161616_10MSB = 0x00000022,
22686EFC_YCrCbA16161616_10LSB = 0x00000023,
22687EFC_ACrYCb16161616_10MSB = 0x00000024,
22688EFC_ACrYCb16161616_10LSB = 0x00000025,
22689EFC_CrYCbA16161616_10MSB = 0x00000026,
22690EFC_CrYCbA16161616_10LSB = 0x00000027,
22691EFC_AYCrCb16161616_12MSB = 0x00000028,
22692EFC_AYCrCb16161616_12LSB = 0x00000029,
22693EFC_YCrCbA16161616_12MSB = 0x0000002a,
22694EFC_YCrCbA16161616_12LSB = 0x0000002b,
22695EFC_ACrYCb16161616_12MSB = 0x0000002c,
22696EFC_ACrYCb16161616_12LSB = 0x0000002d,
22697EFC_CrYCbA16161616_12MSB = 0x0000002e,
22698EFC_CrYCbA16161616_12LSB = 0x0000002f,
22699EFC_Y8_CrCb88_420_PLANAR = 0x00000040,
22700EFC_Y8_CbCr88_420_PLANAR = 0x00000041,
22701EFC_Y10_CrCb1010_420_PLANAR = 0x00000042,
22702EFC_Y10_CbCr1010_420_PLANAR = 0x00000043,
22703EFC_Y12_CrCb1212_420_PLANAR = 0x00000044,
22704EFC_Y12_CbCr1212_420_PLANAR = 0x00000045,
22705EFC_YCrYCb8888_422_PACKED = 0x00000048,
22706EFC_YCbYCr8888_422_PACKED = 0x00000049,
22707EFC_CrYCbY8888_422_PACKED = 0x0000004a,
22708EFC_CbYCrY8888_422_PACKED = 0x0000004b,
22709EFC_YCrYCb10101010_422_PACKED = 0x0000004c,
22710EFC_YCbYCr10101010_422_PACKED = 0x0000004d,
22711EFC_CrYCbY10101010_422_PACKED = 0x0000004e,
22712EFC_CbYCrY10101010_422_PACKED = 0x0000004f,
22713EFC_YCrYCb12121212_422_PACKED = 0x00000050,
22714EFC_YCbYCr12121212_422_PACKED = 0x00000051,
22715EFC_CrYCbY12121212_422_PACKED = 0x00000052,
22716EFC_CbYCrY12121212_422_PACKED = 0x00000053,
22717EFC_RGB111110_FIX = 0x00000070,
22718EFC_BGR101111_FIX = 0x00000071,
22719EFC_ACrYCb2101010 = 0x00000072,
22720EFC_CrYCbA1010102 = 0x00000073,
22721EFC_RGB111110_FLOAT = 0x00000076,
22722EFC_BGR101111_FLOAT = 0x00000077,
22723EFC_MONO_8 = 0x00000078,
22724EFC_MONO_10MSB = 0x00000079,
22725EFC_MONO_10LSB = 0x0000007a,
22726EFC_MONO_12MSB = 0x0000007b,
22727EFC_MONO_12LSB = 0x0000007c,
22728EFC_MONO_16 = 0x0000007d,
22729} EFC_SURFACE_PIXEL_FORMAT;
22730
22731/*******************************************************
22732 * UVD Enums
22733 *******************************************************/
22734
22735/*
22736 * UVDFirmwareCommand enum
22737 */
22738
22739typedef enum UVDFirmwareCommand {
22740UVDFC_FENCE = 0x00000000,
22741UVDFC_TRAP = 0x00000001,
22742UVDFC_DECODED_ADDR = 0x00000002,
22743UVDFC_MBLOCK_ADDR = 0x00000003,
22744UVDFC_ITBUF_ADDR = 0x00000004,
22745UVDFC_DISPLAY_ADDR = 0x00000005,
22746UVDFC_EOD = 0x00000006,
22747UVDFC_DISPLAY_PITCH = 0x00000007,
22748UVDFC_DISPLAY_TILING = 0x00000008,
22749UVDFC_BITSTREAM_ADDR = 0x00000009,
22750UVDFC_BITSTREAM_SIZE = 0x0000000a,
22751} UVDFirmwareCommand;
22752
22753/*******************************************************
22754 * I2C_4_ Enums
22755 *******************************************************/
22756
22757/*
22758 * REVISION_ID value
22759 */
22760
22761#define IP_USB_PD_REVISION_ID 0x00000000
22762
22763#endif /*_navi10_ENUM_HEADER*/
22764