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1/*
2 * Copyright (C) 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _dimgrey_cavefish_ip_offset_HEADER
22#define _dimgrey_cavefish_ip_offset_HEADER
23
24#define MAX_INSTANCE 7
25#define MAX_SEGMENT 6
26
27
28struct IP_BASE_INSTANCE
29{
30 unsigned int segment[MAX_SEGMENT];
31};
32
33struct IP_BASE
34{
35 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
36} __maybe_unused;
37
38
39static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0, 0 } } } };
46static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
47 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
48 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
49 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
50 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
51 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
52 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
53static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
54 { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0, 0 } },
58 { { 0, 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0, 0 } } } };
60static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
61 { { 0, 0, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0, 0 } },
63 { { 0, 0, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0, 0 } } } };
67static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
68 { { 0, 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0, 0 } } } };
74static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
75 { { 0, 0, 0, 0, 0, 0 } },
76 { { 0, 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0, 0 } } } };
81static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0, 0 } },
87 { { 0, 0, 0, 0, 0, 0 } } } };
88static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
89 { { 0, 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0, 0 } },
93 { { 0, 0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0, 0 } } } };
95static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
96 { { 0, 0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0, 0 } } } };
102static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
103 { { 0, 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0, 0 } } } };
109static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
110 { { 0, 0, 0, 0, 0, 0 } },
111 { { 0, 0, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0, 0 } } } };
116static const struct IP_BASE MP1_BASE = { { { { 0x00016200, 0x00E80000, 0x00EC0000, 0x00F00000, 0x02400400, 0 } },
117 { { 0, 0, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0, 0 } } } };
123static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
124 { { 0, 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0, 0 } } } };
130static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0, 0 } },
135 { { 0, 0, 0, 0, 0, 0 } },
136 { { 0, 0, 0, 0, 0, 0 } } } };
137static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } },
138 { { 0, 0, 0, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0, 0 } },
143 { { 0, 0, 0, 0, 0, 0 } } } };
144static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
145 { { 0, 0, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0, 0 } } } };
151static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
152 { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
153 { { 0x00094000, 0x02426000, 0, 0, 0, 0 } },
154 { { 0x000D4000, 0x02426400, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0, 0 } },
156 { { 0, 0, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0, 0 } } } };
158static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
159 { { 0, 0, 0, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0, 0 } },
163 { { 0, 0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0, 0 } } } };
165
166
167#define ATHUB_BASE__INST0_SEG0 0x00000C00
168#define ATHUB_BASE__INST0_SEG1 0x02408C00
169#define ATHUB_BASE__INST0_SEG2 0
170#define ATHUB_BASE__INST0_SEG3 0
171#define ATHUB_BASE__INST0_SEG4 0
172#define ATHUB_BASE__INST0_SEG5 0
173
174#define ATHUB_BASE__INST1_SEG0 0
175#define ATHUB_BASE__INST1_SEG1 0
176#define ATHUB_BASE__INST1_SEG2 0
177#define ATHUB_BASE__INST1_SEG3 0
178#define ATHUB_BASE__INST1_SEG4 0
179#define ATHUB_BASE__INST1_SEG5 0
180
181#define ATHUB_BASE__INST2_SEG0 0
182#define ATHUB_BASE__INST2_SEG1 0
183#define ATHUB_BASE__INST2_SEG2 0
184#define ATHUB_BASE__INST2_SEG3 0
185#define ATHUB_BASE__INST2_SEG4 0
186#define ATHUB_BASE__INST2_SEG5 0
187
188#define ATHUB_BASE__INST3_SEG0 0
189#define ATHUB_BASE__INST3_SEG1 0
190#define ATHUB_BASE__INST3_SEG2 0
191#define ATHUB_BASE__INST3_SEG3 0
192#define ATHUB_BASE__INST3_SEG4 0
193#define ATHUB_BASE__INST3_SEG5 0
194
195#define ATHUB_BASE__INST4_SEG0 0
196#define ATHUB_BASE__INST4_SEG1 0
197#define ATHUB_BASE__INST4_SEG2 0
198#define ATHUB_BASE__INST4_SEG3 0
199#define ATHUB_BASE__INST4_SEG4 0
200#define ATHUB_BASE__INST4_SEG5 0
201
202#define ATHUB_BASE__INST5_SEG0 0
203#define ATHUB_BASE__INST5_SEG1 0
204#define ATHUB_BASE__INST5_SEG2 0
205#define ATHUB_BASE__INST5_SEG3 0
206#define ATHUB_BASE__INST5_SEG4 0
207#define ATHUB_BASE__INST5_SEG5 0
208
209#define ATHUB_BASE__INST6_SEG0 0
210#define ATHUB_BASE__INST6_SEG1 0
211#define ATHUB_BASE__INST6_SEG2 0
212#define ATHUB_BASE__INST6_SEG3 0
213#define ATHUB_BASE__INST6_SEG4 0
214#define ATHUB_BASE__INST6_SEG5 0
215
216#define CLK_BASE__INST0_SEG0 0x00016C00
217#define CLK_BASE__INST0_SEG1 0x02401800
218#define CLK_BASE__INST0_SEG2 0
219#define CLK_BASE__INST0_SEG3 0
220#define CLK_BASE__INST0_SEG4 0
221#define CLK_BASE__INST0_SEG5 0
222
223#define CLK_BASE__INST1_SEG0 0x00016E00
224#define CLK_BASE__INST1_SEG1 0x02401C00
225#define CLK_BASE__INST1_SEG2 0
226#define CLK_BASE__INST1_SEG3 0
227#define CLK_BASE__INST1_SEG4 0
228#define CLK_BASE__INST1_SEG5 0
229
230#define CLK_BASE__INST2_SEG0 0x00017000
231#define CLK_BASE__INST2_SEG1 0x02402000
232#define CLK_BASE__INST2_SEG2 0
233#define CLK_BASE__INST2_SEG3 0
234#define CLK_BASE__INST2_SEG4 0
235#define CLK_BASE__INST2_SEG5 0
236
237#define CLK_BASE__INST3_SEG0 0x00017200
238#define CLK_BASE__INST3_SEG1 0x02402400
239#define CLK_BASE__INST3_SEG2 0
240#define CLK_BASE__INST3_SEG3 0
241#define CLK_BASE__INST3_SEG4 0
242#define CLK_BASE__INST3_SEG5 0
243
244#define CLK_BASE__INST4_SEG0 0x0001B000
245#define CLK_BASE__INST4_SEG1 0x0242D800
246#define CLK_BASE__INST4_SEG2 0
247#define CLK_BASE__INST4_SEG3 0
248#define CLK_BASE__INST4_SEG4 0
249#define CLK_BASE__INST4_SEG5 0
250
251#define CLK_BASE__INST5_SEG0 0x0001B200
252#define CLK_BASE__INST5_SEG1 0x0242DC00
253#define CLK_BASE__INST5_SEG2 0
254#define CLK_BASE__INST5_SEG3 0
255#define CLK_BASE__INST5_SEG4 0
256#define CLK_BASE__INST5_SEG5 0
257
258#define CLK_BASE__INST6_SEG0 0x0001B400
259#define CLK_BASE__INST6_SEG1 0x0242E000
260#define CLK_BASE__INST6_SEG2 0
261#define CLK_BASE__INST6_SEG3 0
262#define CLK_BASE__INST6_SEG4 0
263#define CLK_BASE__INST6_SEG5 0
264
265#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0
266#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400
267#define DBGU_IO0_BASE__INST0_SEG2 0
268#define DBGU_IO0_BASE__INST0_SEG3 0
269#define DBGU_IO0_BASE__INST0_SEG4 0
270#define DBGU_IO0_BASE__INST0_SEG5 0
271
272#define DBGU_IO0_BASE__INST1_SEG0 0x00000260
273#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00
274#define DBGU_IO0_BASE__INST1_SEG2 0
275#define DBGU_IO0_BASE__INST1_SEG3 0
276#define DBGU_IO0_BASE__INST1_SEG4 0
277#define DBGU_IO0_BASE__INST1_SEG5 0
278
279#define DBGU_IO0_BASE__INST2_SEG0 0
280#define DBGU_IO0_BASE__INST2_SEG1 0
281#define DBGU_IO0_BASE__INST2_SEG2 0
282#define DBGU_IO0_BASE__INST2_SEG3 0
283#define DBGU_IO0_BASE__INST2_SEG4 0
284#define DBGU_IO0_BASE__INST2_SEG5 0
285
286#define DBGU_IO0_BASE__INST3_SEG0 0
287#define DBGU_IO0_BASE__INST3_SEG1 0
288#define DBGU_IO0_BASE__INST3_SEG2 0
289#define DBGU_IO0_BASE__INST3_SEG3 0
290#define DBGU_IO0_BASE__INST3_SEG4 0
291#define DBGU_IO0_BASE__INST3_SEG5 0
292
293#define DBGU_IO0_BASE__INST4_SEG0 0
294#define DBGU_IO0_BASE__INST4_SEG1 0
295#define DBGU_IO0_BASE__INST4_SEG2 0
296#define DBGU_IO0_BASE__INST4_SEG3 0
297#define DBGU_IO0_BASE__INST4_SEG4 0
298#define DBGU_IO0_BASE__INST4_SEG5 0
299
300#define DBGU_IO0_BASE__INST5_SEG0 0
301#define DBGU_IO0_BASE__INST5_SEG1 0
302#define DBGU_IO0_BASE__INST5_SEG2 0
303#define DBGU_IO0_BASE__INST5_SEG3 0
304#define DBGU_IO0_BASE__INST5_SEG4 0
305#define DBGU_IO0_BASE__INST5_SEG5 0
306
307#define DBGU_IO0_BASE__INST6_SEG0 0
308#define DBGU_IO0_BASE__INST6_SEG1 0
309#define DBGU_IO0_BASE__INST6_SEG2 0
310#define DBGU_IO0_BASE__INST6_SEG3 0
311#define DBGU_IO0_BASE__INST6_SEG4 0
312#define DBGU_IO0_BASE__INST6_SEG5 0
313
314#define DF_BASE__INST0_SEG0 0x00007000
315#define DF_BASE__INST0_SEG1 0x0240B800
316#define DF_BASE__INST0_SEG2 0
317#define DF_BASE__INST0_SEG3 0
318#define DF_BASE__INST0_SEG4 0
319#define DF_BASE__INST0_SEG5 0
320
321#define DF_BASE__INST1_SEG0 0
322#define DF_BASE__INST1_SEG1 0
323#define DF_BASE__INST1_SEG2 0
324#define DF_BASE__INST1_SEG3 0
325#define DF_BASE__INST1_SEG4 0
326#define DF_BASE__INST1_SEG5 0
327
328#define DF_BASE__INST2_SEG0 0
329#define DF_BASE__INST2_SEG1 0
330#define DF_BASE__INST2_SEG2 0
331#define DF_BASE__INST2_SEG3 0
332#define DF_BASE__INST2_SEG4 0
333#define DF_BASE__INST2_SEG5 0
334
335#define DF_BASE__INST3_SEG0 0
336#define DF_BASE__INST3_SEG1 0
337#define DF_BASE__INST3_SEG2 0
338#define DF_BASE__INST3_SEG3 0
339#define DF_BASE__INST3_SEG4 0
340#define DF_BASE__INST3_SEG5 0
341
342#define DF_BASE__INST4_SEG0 0
343#define DF_BASE__INST4_SEG1 0
344#define DF_BASE__INST4_SEG2 0
345#define DF_BASE__INST4_SEG3 0
346#define DF_BASE__INST4_SEG4 0
347#define DF_BASE__INST4_SEG5 0
348
349#define DF_BASE__INST5_SEG0 0
350#define DF_BASE__INST5_SEG1 0
351#define DF_BASE__INST5_SEG2 0
352#define DF_BASE__INST5_SEG3 0
353#define DF_BASE__INST5_SEG4 0
354#define DF_BASE__INST5_SEG5 0
355
356#define DF_BASE__INST6_SEG0 0
357#define DF_BASE__INST6_SEG1 0
358#define DF_BASE__INST6_SEG2 0
359#define DF_BASE__INST6_SEG3 0
360#define DF_BASE__INST6_SEG4 0
361#define DF_BASE__INST6_SEG5 0
362
363#define DCN_BASE__INST0_SEG0 0x00000012
364#define DCN_BASE__INST0_SEG1 0x000000C0
365#define DCN_BASE__INST0_SEG2 0x000034C0
366#define DCN_BASE__INST0_SEG3 0x00009000
367#define DCN_BASE__INST0_SEG4 0x02403C00
368#define DCN_BASE__INST0_SEG5 0
369
370#define DCN_BASE__INST1_SEG0 0
371#define DCN_BASE__INST1_SEG1 0
372#define DCN_BASE__INST1_SEG2 0
373#define DCN_BASE__INST1_SEG3 0
374#define DCN_BASE__INST1_SEG4 0
375#define DCN_BASE__INST1_SEG5 0
376
377#define DCN_BASE__INST2_SEG0 0
378#define DCN_BASE__INST2_SEG1 0
379#define DCN_BASE__INST2_SEG2 0
380#define DCN_BASE__INST2_SEG3 0
381#define DCN_BASE__INST2_SEG4 0
382#define DCN_BASE__INST2_SEG5 0
383
384#define DCN_BASE__INST3_SEG0 0
385#define DCN_BASE__INST3_SEG1 0
386#define DCN_BASE__INST3_SEG2 0
387#define DCN_BASE__INST3_SEG3 0
388#define DCN_BASE__INST3_SEG4 0
389#define DCN_BASE__INST3_SEG5 0
390
391#define DCN_BASE__INST4_SEG0 0
392#define DCN_BASE__INST4_SEG1 0
393#define DCN_BASE__INST4_SEG2 0
394#define DCN_BASE__INST4_SEG3 0
395#define DCN_BASE__INST4_SEG4 0
396#define DCN_BASE__INST4_SEG5 0
397
398#define DCN_BASE__INST5_SEG0 0
399#define DCN_BASE__INST5_SEG1 0
400#define DCN_BASE__INST5_SEG2 0
401#define DCN_BASE__INST5_SEG3 0
402#define DCN_BASE__INST5_SEG4 0
403#define DCN_BASE__INST5_SEG5 0
404
405#define DCN_BASE__INST6_SEG0 0
406#define DCN_BASE__INST6_SEG1 0
407#define DCN_BASE__INST6_SEG2 0
408#define DCN_BASE__INST6_SEG3 0
409#define DCN_BASE__INST6_SEG4 0
410#define DCN_BASE__INST6_SEG5 0
411
412#define DPCS_BASE__INST0_SEG0 0x00000012
413#define DPCS_BASE__INST0_SEG1 0x000000C0
414#define DPCS_BASE__INST0_SEG2 0x000034C0
415#define DPCS_BASE__INST0_SEG3 0x00009000
416#define DPCS_BASE__INST0_SEG4 0x02403C00
417#define DPCS_BASE__INST0_SEG5 0
418
419#define DPCS_BASE__INST1_SEG0 0
420#define DPCS_BASE__INST1_SEG1 0
421#define DPCS_BASE__INST1_SEG2 0
422#define DPCS_BASE__INST1_SEG3 0
423#define DPCS_BASE__INST1_SEG4 0
424#define DPCS_BASE__INST1_SEG5 0
425
426#define DPCS_BASE__INST2_SEG0 0
427#define DPCS_BASE__INST2_SEG1 0
428#define DPCS_BASE__INST2_SEG2 0
429#define DPCS_BASE__INST2_SEG3 0
430#define DPCS_BASE__INST2_SEG4 0
431#define DPCS_BASE__INST2_SEG5 0
432
433#define DPCS_BASE__INST3_SEG0 0
434#define DPCS_BASE__INST3_SEG1 0
435#define DPCS_BASE__INST3_SEG2 0
436#define DPCS_BASE__INST3_SEG3 0
437#define DPCS_BASE__INST3_SEG4 0
438#define DPCS_BASE__INST3_SEG5 0
439
440#define DPCS_BASE__INST4_SEG0 0
441#define DPCS_BASE__INST4_SEG1 0
442#define DPCS_BASE__INST4_SEG2 0
443#define DPCS_BASE__INST4_SEG3 0
444#define DPCS_BASE__INST4_SEG4 0
445#define DPCS_BASE__INST4_SEG5 0
446
447#define DPCS_BASE__INST5_SEG0 0
448#define DPCS_BASE__INST5_SEG1 0
449#define DPCS_BASE__INST5_SEG2 0
450#define DPCS_BASE__INST5_SEG3 0
451#define DPCS_BASE__INST5_SEG4 0
452#define DPCS_BASE__INST5_SEG5 0
453
454#define DPCS_BASE__INST6_SEG0 0
455#define DPCS_BASE__INST6_SEG1 0
456#define DPCS_BASE__INST6_SEG2 0
457#define DPCS_BASE__INST6_SEG3 0
458#define DPCS_BASE__INST6_SEG4 0
459#define DPCS_BASE__INST6_SEG5 0
460
461#define FUSE_BASE__INST0_SEG0 0x00017400
462#define FUSE_BASE__INST0_SEG1 0x02401400
463#define FUSE_BASE__INST0_SEG2 0
464#define FUSE_BASE__INST0_SEG3 0
465#define FUSE_BASE__INST0_SEG4 0
466#define FUSE_BASE__INST0_SEG5 0
467
468#define FUSE_BASE__INST1_SEG0 0
469#define FUSE_BASE__INST1_SEG1 0
470#define FUSE_BASE__INST1_SEG2 0
471#define FUSE_BASE__INST1_SEG3 0
472#define FUSE_BASE__INST1_SEG4 0
473#define FUSE_BASE__INST1_SEG5 0
474
475#define FUSE_BASE__INST2_SEG0 0
476#define FUSE_BASE__INST2_SEG1 0
477#define FUSE_BASE__INST2_SEG2 0
478#define FUSE_BASE__INST2_SEG3 0
479#define FUSE_BASE__INST2_SEG4 0
480#define FUSE_BASE__INST2_SEG5 0
481
482#define FUSE_BASE__INST3_SEG0 0
483#define FUSE_BASE__INST3_SEG1 0
484#define FUSE_BASE__INST3_SEG2 0
485#define FUSE_BASE__INST3_SEG3 0
486#define FUSE_BASE__INST3_SEG4 0
487#define FUSE_BASE__INST3_SEG5 0
488
489#define FUSE_BASE__INST4_SEG0 0
490#define FUSE_BASE__INST4_SEG1 0
491#define FUSE_BASE__INST4_SEG2 0
492#define FUSE_BASE__INST4_SEG3 0
493#define FUSE_BASE__INST4_SEG4 0
494#define FUSE_BASE__INST4_SEG5 0
495
496#define FUSE_BASE__INST5_SEG0 0
497#define FUSE_BASE__INST5_SEG1 0
498#define FUSE_BASE__INST5_SEG2 0
499#define FUSE_BASE__INST5_SEG3 0
500#define FUSE_BASE__INST5_SEG4 0
501#define FUSE_BASE__INST5_SEG5 0
502
503#define FUSE_BASE__INST6_SEG0 0
504#define FUSE_BASE__INST6_SEG1 0
505#define FUSE_BASE__INST6_SEG2 0
506#define FUSE_BASE__INST6_SEG3 0
507#define FUSE_BASE__INST6_SEG4 0
508#define FUSE_BASE__INST6_SEG5 0
509
510#define GC_BASE__INST0_SEG0 0x00001260
511#define GC_BASE__INST0_SEG1 0x0000A000
512#define GC_BASE__INST0_SEG2 0x0001C000
513#define GC_BASE__INST0_SEG3 0x02402C00
514#define GC_BASE__INST0_SEG4 0
515#define GC_BASE__INST0_SEG5 0
516
517#define GC_BASE__INST1_SEG0 0
518#define GC_BASE__INST1_SEG1 0
519#define GC_BASE__INST1_SEG2 0
520#define GC_BASE__INST1_SEG3 0
521#define GC_BASE__INST1_SEG4 0
522#define GC_BASE__INST1_SEG5 0
523
524#define GC_BASE__INST2_SEG0 0
525#define GC_BASE__INST2_SEG1 0
526#define GC_BASE__INST2_SEG2 0
527#define GC_BASE__INST2_SEG3 0
528#define GC_BASE__INST2_SEG4 0
529#define GC_BASE__INST2_SEG5 0
530
531#define GC_BASE__INST3_SEG0 0
532#define GC_BASE__INST3_SEG1 0
533#define GC_BASE__INST3_SEG2 0
534#define GC_BASE__INST3_SEG3 0
535#define GC_BASE__INST3_SEG4 0
536#define GC_BASE__INST3_SEG5 0
537
538#define GC_BASE__INST4_SEG0 0
539#define GC_BASE__INST4_SEG1 0
540#define GC_BASE__INST4_SEG2 0
541#define GC_BASE__INST4_SEG3 0
542#define GC_BASE__INST4_SEG4 0
543#define GC_BASE__INST4_SEG5 0
544
545#define GC_BASE__INST5_SEG0 0
546#define GC_BASE__INST5_SEG1 0
547#define GC_BASE__INST5_SEG2 0
548#define GC_BASE__INST5_SEG3 0
549#define GC_BASE__INST5_SEG4 0
550#define GC_BASE__INST5_SEG5 0
551
552#define GC_BASE__INST6_SEG0 0
553#define GC_BASE__INST6_SEG1 0
554#define GC_BASE__INST6_SEG2 0
555#define GC_BASE__INST6_SEG3 0
556#define GC_BASE__INST6_SEG4 0
557#define GC_BASE__INST6_SEG5 0
558
559#define HDP_BASE__INST0_SEG0 0x00000F20
560#define HDP_BASE__INST0_SEG1 0x0240A400
561#define HDP_BASE__INST0_SEG2 0
562#define HDP_BASE__INST0_SEG3 0
563#define HDP_BASE__INST0_SEG4 0
564#define HDP_BASE__INST0_SEG5 0
565
566#define HDP_BASE__INST1_SEG0 0
567#define HDP_BASE__INST1_SEG1 0
568#define HDP_BASE__INST1_SEG2 0
569#define HDP_BASE__INST1_SEG3 0
570#define HDP_BASE__INST1_SEG4 0
571#define HDP_BASE__INST1_SEG5 0
572
573#define HDP_BASE__INST2_SEG0 0
574#define HDP_BASE__INST2_SEG1 0
575#define HDP_BASE__INST2_SEG2 0
576#define HDP_BASE__INST2_SEG3 0
577#define HDP_BASE__INST2_SEG4 0
578#define HDP_BASE__INST2_SEG5 0
579
580#define HDP_BASE__INST3_SEG0 0
581#define HDP_BASE__INST3_SEG1 0
582#define HDP_BASE__INST3_SEG2 0
583#define HDP_BASE__INST3_SEG3 0
584#define HDP_BASE__INST3_SEG4 0
585#define HDP_BASE__INST3_SEG5 0
586
587#define HDP_BASE__INST4_SEG0 0
588#define HDP_BASE__INST4_SEG1 0
589#define HDP_BASE__INST4_SEG2 0
590#define HDP_BASE__INST4_SEG3 0
591#define HDP_BASE__INST4_SEG4 0
592#define HDP_BASE__INST4_SEG5 0
593
594#define HDP_BASE__INST5_SEG0 0
595#define HDP_BASE__INST5_SEG1 0
596#define HDP_BASE__INST5_SEG2 0
597#define HDP_BASE__INST5_SEG3 0
598#define HDP_BASE__INST5_SEG4 0
599#define HDP_BASE__INST5_SEG5 0
600
601#define HDP_BASE__INST6_SEG0 0
602#define HDP_BASE__INST6_SEG1 0
603#define HDP_BASE__INST6_SEG2 0
604#define HDP_BASE__INST6_SEG3 0
605#define HDP_BASE__INST6_SEG4 0
606#define HDP_BASE__INST6_SEG5 0
607
608#define MMHUB_BASE__INST0_SEG0 0x0001A000
609#define MMHUB_BASE__INST0_SEG1 0x02408800
610#define MMHUB_BASE__INST0_SEG2 0
611#define MMHUB_BASE__INST0_SEG3 0
612#define MMHUB_BASE__INST0_SEG4 0
613#define MMHUB_BASE__INST0_SEG5 0
614
615#define MMHUB_BASE__INST1_SEG0 0
616#define MMHUB_BASE__INST1_SEG1 0
617#define MMHUB_BASE__INST1_SEG2 0
618#define MMHUB_BASE__INST1_SEG3 0
619#define MMHUB_BASE__INST1_SEG4 0
620#define MMHUB_BASE__INST1_SEG5 0
621
622#define MMHUB_BASE__INST2_SEG0 0
623#define MMHUB_BASE__INST2_SEG1 0
624#define MMHUB_BASE__INST2_SEG2 0
625#define MMHUB_BASE__INST2_SEG3 0
626#define MMHUB_BASE__INST2_SEG4 0
627#define MMHUB_BASE__INST2_SEG5 0
628
629#define MMHUB_BASE__INST3_SEG0 0
630#define MMHUB_BASE__INST3_SEG1 0
631#define MMHUB_BASE__INST3_SEG2 0
632#define MMHUB_BASE__INST3_SEG3 0
633#define MMHUB_BASE__INST3_SEG4 0
634#define MMHUB_BASE__INST3_SEG5 0
635
636#define MMHUB_BASE__INST4_SEG0 0
637#define MMHUB_BASE__INST4_SEG1 0
638#define MMHUB_BASE__INST4_SEG2 0
639#define MMHUB_BASE__INST4_SEG3 0
640#define MMHUB_BASE__INST4_SEG4 0
641#define MMHUB_BASE__INST4_SEG5 0
642
643#define MMHUB_BASE__INST5_SEG0 0
644#define MMHUB_BASE__INST5_SEG1 0
645#define MMHUB_BASE__INST5_SEG2 0
646#define MMHUB_BASE__INST5_SEG3 0
647#define MMHUB_BASE__INST5_SEG4 0
648#define MMHUB_BASE__INST5_SEG5 0
649
650#define MMHUB_BASE__INST6_SEG0 0
651#define MMHUB_BASE__INST6_SEG1 0
652#define MMHUB_BASE__INST6_SEG2 0
653#define MMHUB_BASE__INST6_SEG3 0
654#define MMHUB_BASE__INST6_SEG4 0
655#define MMHUB_BASE__INST6_SEG5 0
656
657#define MP0_BASE__INST0_SEG0 0x00016000
658#define MP0_BASE__INST0_SEG1 0x00DC0000
659#define MP0_BASE__INST0_SEG2 0x00E00000
660#define MP0_BASE__INST0_SEG3 0x00E40000
661#define MP0_BASE__INST0_SEG4 0x0243FC00
662#define MP0_BASE__INST0_SEG5 0
663
664#define MP0_BASE__INST1_SEG0 0
665#define MP0_BASE__INST1_SEG1 0
666#define MP0_BASE__INST1_SEG2 0
667#define MP0_BASE__INST1_SEG3 0
668#define MP0_BASE__INST1_SEG4 0
669#define MP0_BASE__INST1_SEG5 0
670
671#define MP0_BASE__INST2_SEG0 0
672#define MP0_BASE__INST2_SEG1 0
673#define MP0_BASE__INST2_SEG2 0
674#define MP0_BASE__INST2_SEG3 0
675#define MP0_BASE__INST2_SEG4 0
676#define MP0_BASE__INST2_SEG5 0
677
678#define MP0_BASE__INST3_SEG0 0
679#define MP0_BASE__INST3_SEG1 0
680#define MP0_BASE__INST3_SEG2 0
681#define MP0_BASE__INST3_SEG3 0
682#define MP0_BASE__INST3_SEG4 0
683#define MP0_BASE__INST3_SEG5 0
684
685#define MP0_BASE__INST4_SEG0 0
686#define MP0_BASE__INST4_SEG1 0
687#define MP0_BASE__INST4_SEG2 0
688#define MP0_BASE__INST4_SEG3 0
689#define MP0_BASE__INST4_SEG4 0
690#define MP0_BASE__INST4_SEG5 0
691
692#define MP0_BASE__INST5_SEG0 0
693#define MP0_BASE__INST5_SEG1 0
694#define MP0_BASE__INST5_SEG2 0
695#define MP0_BASE__INST5_SEG3 0
696#define MP0_BASE__INST5_SEG4 0
697#define MP0_BASE__INST5_SEG5 0
698
699#define MP0_BASE__INST6_SEG0 0
700#define MP0_BASE__INST6_SEG1 0
701#define MP0_BASE__INST6_SEG2 0
702#define MP0_BASE__INST6_SEG3 0
703#define MP0_BASE__INST6_SEG4 0
704#define MP0_BASE__INST6_SEG5 0
705
706#define MP1_BASE__INST0_SEG0 0x00016200
707#define MP1_BASE__INST0_SEG1 0x00E80000
708#define MP1_BASE__INST0_SEG2 0x00EC0000
709#define MP1_BASE__INST0_SEG3 0x00F00000
710#define MP1_BASE__INST0_SEG4 0x02400400
711#define MP1_BASE__INST0_SEG5 0
712
713#define MP1_BASE__INST1_SEG0 0
714#define MP1_BASE__INST1_SEG1 0
715#define MP1_BASE__INST1_SEG2 0
716#define MP1_BASE__INST1_SEG3 0
717#define MP1_BASE__INST1_SEG4 0
718#define MP1_BASE__INST1_SEG5 0
719
720#define MP1_BASE__INST2_SEG0 0
721#define MP1_BASE__INST2_SEG1 0
722#define MP1_BASE__INST2_SEG2 0
723#define MP1_BASE__INST2_SEG3 0
724#define MP1_BASE__INST2_SEG4 0
725#define MP1_BASE__INST2_SEG5 0
726
727#define MP1_BASE__INST3_SEG0 0
728#define MP1_BASE__INST3_SEG1 0
729#define MP1_BASE__INST3_SEG2 0
730#define MP1_BASE__INST3_SEG3 0
731#define MP1_BASE__INST3_SEG4 0
732#define MP1_BASE__INST3_SEG5 0
733
734#define MP1_BASE__INST4_SEG0 0
735#define MP1_BASE__INST4_SEG1 0
736#define MP1_BASE__INST4_SEG2 0
737#define MP1_BASE__INST4_SEG3 0
738#define MP1_BASE__INST4_SEG4 0
739#define MP1_BASE__INST4_SEG5 0
740
741#define MP1_BASE__INST5_SEG0 0
742#define MP1_BASE__INST5_SEG1 0
743#define MP1_BASE__INST5_SEG2 0
744#define MP1_BASE__INST5_SEG3 0
745#define MP1_BASE__INST5_SEG4 0
746#define MP1_BASE__INST5_SEG5 0
747
748#define MP1_BASE__INST6_SEG0 0
749#define MP1_BASE__INST6_SEG1 0
750#define MP1_BASE__INST6_SEG2 0
751#define MP1_BASE__INST6_SEG3 0
752#define MP1_BASE__INST6_SEG4 0
753#define MP1_BASE__INST6_SEG5 0
754
755#define NBIO_BASE__INST0_SEG0 0x00000000
756#define NBIO_BASE__INST0_SEG1 0x00000014
757#define NBIO_BASE__INST0_SEG2 0x00000D20
758#define NBIO_BASE__INST0_SEG3 0x00010400
759#define NBIO_BASE__INST0_SEG4 0x0241B000
760#define NBIO_BASE__INST0_SEG5 0x04040000
761
762#define NBIO_BASE__INST1_SEG0 0
763#define NBIO_BASE__INST1_SEG1 0
764#define NBIO_BASE__INST1_SEG2 0
765#define NBIO_BASE__INST1_SEG3 0
766#define NBIO_BASE__INST1_SEG4 0
767#define NBIO_BASE__INST1_SEG5 0
768
769#define NBIO_BASE__INST2_SEG0 0
770#define NBIO_BASE__INST2_SEG1 0
771#define NBIO_BASE__INST2_SEG2 0
772#define NBIO_BASE__INST2_SEG3 0
773#define NBIO_BASE__INST2_SEG4 0
774#define NBIO_BASE__INST2_SEG5 0
775
776#define NBIO_BASE__INST3_SEG0 0
777#define NBIO_BASE__INST3_SEG1 0
778#define NBIO_BASE__INST3_SEG2 0
779#define NBIO_BASE__INST3_SEG3 0
780#define NBIO_BASE__INST3_SEG4 0
781#define NBIO_BASE__INST3_SEG5 0
782
783#define NBIO_BASE__INST4_SEG0 0
784#define NBIO_BASE__INST4_SEG1 0
785#define NBIO_BASE__INST4_SEG2 0
786#define NBIO_BASE__INST4_SEG3 0
787#define NBIO_BASE__INST4_SEG4 0
788#define NBIO_BASE__INST4_SEG5 0
789
790#define NBIO_BASE__INST5_SEG0 0
791#define NBIO_BASE__INST5_SEG1 0
792#define NBIO_BASE__INST5_SEG2 0
793#define NBIO_BASE__INST5_SEG3 0
794#define NBIO_BASE__INST5_SEG4 0
795#define NBIO_BASE__INST5_SEG5 0
796
797#define NBIO_BASE__INST6_SEG0 0
798#define NBIO_BASE__INST6_SEG1 0
799#define NBIO_BASE__INST6_SEG2 0
800#define NBIO_BASE__INST6_SEG3 0
801#define NBIO_BASE__INST6_SEG4 0
802#define NBIO_BASE__INST6_SEG5 0
803
804#define OSSSYS_BASE__INST0_SEG0 0x000010A0
805#define OSSSYS_BASE__INST0_SEG1 0x0240A000
806#define OSSSYS_BASE__INST0_SEG2 0
807#define OSSSYS_BASE__INST0_SEG3 0
808#define OSSSYS_BASE__INST0_SEG4 0
809#define OSSSYS_BASE__INST0_SEG5 0
810
811#define OSSSYS_BASE__INST1_SEG0 0
812#define OSSSYS_BASE__INST1_SEG1 0
813#define OSSSYS_BASE__INST1_SEG2 0
814#define OSSSYS_BASE__INST1_SEG3 0
815#define OSSSYS_BASE__INST1_SEG4 0
816#define OSSSYS_BASE__INST1_SEG5 0
817
818#define OSSSYS_BASE__INST2_SEG0 0
819#define OSSSYS_BASE__INST2_SEG1 0
820#define OSSSYS_BASE__INST2_SEG2 0
821#define OSSSYS_BASE__INST2_SEG3 0
822#define OSSSYS_BASE__INST2_SEG4 0
823#define OSSSYS_BASE__INST2_SEG5 0
824
825#define OSSSYS_BASE__INST3_SEG0 0
826#define OSSSYS_BASE__INST3_SEG1 0
827#define OSSSYS_BASE__INST3_SEG2 0
828#define OSSSYS_BASE__INST3_SEG3 0
829#define OSSSYS_BASE__INST3_SEG4 0
830#define OSSSYS_BASE__INST3_SEG5 0
831
832#define OSSSYS_BASE__INST4_SEG0 0
833#define OSSSYS_BASE__INST4_SEG1 0
834#define OSSSYS_BASE__INST4_SEG2 0
835#define OSSSYS_BASE__INST4_SEG3 0
836#define OSSSYS_BASE__INST4_SEG4 0
837#define OSSSYS_BASE__INST4_SEG5 0
838
839#define OSSSYS_BASE__INST5_SEG0 0
840#define OSSSYS_BASE__INST5_SEG1 0
841#define OSSSYS_BASE__INST5_SEG2 0
842#define OSSSYS_BASE__INST5_SEG3 0
843#define OSSSYS_BASE__INST5_SEG4 0
844#define OSSSYS_BASE__INST5_SEG5 0
845
846#define OSSSYS_BASE__INST6_SEG0 0
847#define OSSSYS_BASE__INST6_SEG1 0
848#define OSSSYS_BASE__INST6_SEG2 0
849#define OSSSYS_BASE__INST6_SEG3 0
850#define OSSSYS_BASE__INST6_SEG4 0
851#define OSSSYS_BASE__INST6_SEG5 0
852
853#define SMUIO_BASE__INST0_SEG0 0x00016800
854#define SMUIO_BASE__INST0_SEG1 0x00016A00
855#define SMUIO_BASE__INST0_SEG2 0x00440000
856#define SMUIO_BASE__INST0_SEG3 0x02401000
857#define SMUIO_BASE__INST0_SEG4 0
858#define SMUIO_BASE__INST0_SEG5 0
859
860#define SMUIO_BASE__INST1_SEG0 0
861#define SMUIO_BASE__INST1_SEG1 0
862#define SMUIO_BASE__INST1_SEG2 0
863#define SMUIO_BASE__INST1_SEG3 0
864#define SMUIO_BASE__INST1_SEG4 0
865#define SMUIO_BASE__INST1_SEG5 0
866
867#define SMUIO_BASE__INST2_SEG0 0
868#define SMUIO_BASE__INST2_SEG1 0
869#define SMUIO_BASE__INST2_SEG2 0
870#define SMUIO_BASE__INST2_SEG3 0
871#define SMUIO_BASE__INST2_SEG4 0
872#define SMUIO_BASE__INST2_SEG5 0
873
874#define SMUIO_BASE__INST3_SEG0 0
875#define SMUIO_BASE__INST3_SEG1 0
876#define SMUIO_BASE__INST3_SEG2 0
877#define SMUIO_BASE__INST3_SEG3 0
878#define SMUIO_BASE__INST3_SEG4 0
879#define SMUIO_BASE__INST3_SEG5 0
880
881#define SMUIO_BASE__INST4_SEG0 0
882#define SMUIO_BASE__INST4_SEG1 0
883#define SMUIO_BASE__INST4_SEG2 0
884#define SMUIO_BASE__INST4_SEG3 0
885#define SMUIO_BASE__INST4_SEG4 0
886#define SMUIO_BASE__INST4_SEG5 0
887
888#define SMUIO_BASE__INST5_SEG0 0
889#define SMUIO_BASE__INST5_SEG1 0
890#define SMUIO_BASE__INST5_SEG2 0
891#define SMUIO_BASE__INST5_SEG3 0
892#define SMUIO_BASE__INST5_SEG4 0
893#define SMUIO_BASE__INST5_SEG5 0
894
895#define SMUIO_BASE__INST6_SEG0 0
896#define SMUIO_BASE__INST6_SEG1 0
897#define SMUIO_BASE__INST6_SEG2 0
898#define SMUIO_BASE__INST6_SEG3 0
899#define SMUIO_BASE__INST6_SEG4 0
900#define SMUIO_BASE__INST6_SEG5 0
901
902#define THM_BASE__INST0_SEG0 0x00016600
903#define THM_BASE__INST0_SEG1 0x02400C00
904#define THM_BASE__INST0_SEG2 0
905#define THM_BASE__INST0_SEG3 0
906#define THM_BASE__INST0_SEG4 0
907#define THM_BASE__INST0_SEG5 0
908
909#define THM_BASE__INST1_SEG0 0
910#define THM_BASE__INST1_SEG1 0
911#define THM_BASE__INST1_SEG2 0
912#define THM_BASE__INST1_SEG3 0
913#define THM_BASE__INST1_SEG4 0
914#define THM_BASE__INST1_SEG5 0
915
916#define THM_BASE__INST2_SEG0 0
917#define THM_BASE__INST2_SEG1 0
918#define THM_BASE__INST2_SEG2 0
919#define THM_BASE__INST2_SEG3 0
920#define THM_BASE__INST2_SEG4 0
921#define THM_BASE__INST2_SEG5 0
922
923#define THM_BASE__INST3_SEG0 0
924#define THM_BASE__INST3_SEG1 0
925#define THM_BASE__INST3_SEG2 0
926#define THM_BASE__INST3_SEG3 0
927#define THM_BASE__INST3_SEG4 0
928#define THM_BASE__INST3_SEG5 0
929
930#define THM_BASE__INST4_SEG0 0
931#define THM_BASE__INST4_SEG1 0
932#define THM_BASE__INST4_SEG2 0
933#define THM_BASE__INST4_SEG3 0
934#define THM_BASE__INST4_SEG4 0
935#define THM_BASE__INST4_SEG5 0
936
937#define THM_BASE__INST5_SEG0 0
938#define THM_BASE__INST5_SEG1 0
939#define THM_BASE__INST5_SEG2 0
940#define THM_BASE__INST5_SEG3 0
941#define THM_BASE__INST5_SEG4 0
942#define THM_BASE__INST5_SEG5 0
943
944#define THM_BASE__INST6_SEG0 0
945#define THM_BASE__INST6_SEG1 0
946#define THM_BASE__INST6_SEG2 0
947#define THM_BASE__INST6_SEG3 0
948#define THM_BASE__INST6_SEG4 0
949#define THM_BASE__INST6_SEG5 0
950
951#define UMC_BASE__INST0_SEG0 0x00014000
952#define UMC_BASE__INST0_SEG1 0x02425800
953#define UMC_BASE__INST0_SEG2 0
954#define UMC_BASE__INST0_SEG3 0
955#define UMC_BASE__INST0_SEG4 0
956#define UMC_BASE__INST0_SEG5 0
957
958#define UMC_BASE__INST1_SEG0 0x00054000
959#define UMC_BASE__INST1_SEG1 0x02425C00
960#define UMC_BASE__INST1_SEG2 0
961#define UMC_BASE__INST1_SEG3 0
962#define UMC_BASE__INST1_SEG4 0
963#define UMC_BASE__INST1_SEG5 0
964
965#define UMC_BASE__INST2_SEG0 0x00094000
966#define UMC_BASE__INST2_SEG1 0x02426000
967#define UMC_BASE__INST2_SEG2 0
968#define UMC_BASE__INST2_SEG3 0
969#define UMC_BASE__INST2_SEG4 0
970#define UMC_BASE__INST2_SEG5 0
971
972#define UMC_BASE__INST3_SEG0 0x000D4000
973#define UMC_BASE__INST3_SEG1 0x02426400
974#define UMC_BASE__INST3_SEG2 0
975#define UMC_BASE__INST3_SEG3 0
976#define UMC_BASE__INST3_SEG4 0
977#define UMC_BASE__INST3_SEG5 0
978
979#define UMC_BASE__INST4_SEG0 0
980#define UMC_BASE__INST4_SEG1 0
981#define UMC_BASE__INST4_SEG2 0
982#define UMC_BASE__INST4_SEG3 0
983#define UMC_BASE__INST4_SEG4 0
984#define UMC_BASE__INST4_SEG5 0
985
986#define UMC_BASE__INST5_SEG0 0
987#define UMC_BASE__INST5_SEG1 0
988#define UMC_BASE__INST5_SEG2 0
989#define UMC_BASE__INST5_SEG3 0
990#define UMC_BASE__INST5_SEG4 0
991#define UMC_BASE__INST5_SEG5 0
992
993#define UMC_BASE__INST6_SEG0 0
994#define UMC_BASE__INST6_SEG1 0
995#define UMC_BASE__INST6_SEG2 0
996#define UMC_BASE__INST6_SEG3 0
997#define UMC_BASE__INST6_SEG4 0
998#define UMC_BASE__INST6_SEG5 0
999
1000#define VCN0_BASE__INST0_SEG0 0x00007800
1001#define VCN0_BASE__INST0_SEG1 0x00007E00
1002#define VCN0_BASE__INST0_SEG2 0x02403000
1003#define VCN0_BASE__INST0_SEG3 0
1004#define VCN0_BASE__INST0_SEG4 0
1005#define VCN0_BASE__INST0_SEG5 0
1006
1007#define VCN0_BASE__INST1_SEG0 0
1008#define VCN0_BASE__INST1_SEG1 0
1009#define VCN0_BASE__INST1_SEG2 0
1010#define VCN0_BASE__INST1_SEG3 0
1011#define VCN0_BASE__INST1_SEG4 0
1012#define VCN0_BASE__INST1_SEG5 0
1013
1014#define VCN0_BASE__INST2_SEG0 0
1015#define VCN0_BASE__INST2_SEG1 0
1016#define VCN0_BASE__INST2_SEG2 0
1017#define VCN0_BASE__INST2_SEG3 0
1018#define VCN0_BASE__INST2_SEG4 0
1019#define VCN0_BASE__INST2_SEG5 0
1020
1021#define VCN0_BASE__INST3_SEG0 0
1022#define VCN0_BASE__INST3_SEG1 0
1023#define VCN0_BASE__INST3_SEG2 0
1024#define VCN0_BASE__INST3_SEG3 0
1025#define VCN0_BASE__INST3_SEG4 0
1026#define VCN0_BASE__INST3_SEG5 0
1027
1028#define VCN0_BASE__INST4_SEG0 0
1029#define VCN0_BASE__INST4_SEG1 0
1030#define VCN0_BASE__INST4_SEG2 0
1031#define VCN0_BASE__INST4_SEG3 0
1032#define VCN0_BASE__INST4_SEG4 0
1033#define VCN0_BASE__INST4_SEG5 0
1034
1035#define VCN0_BASE__INST5_SEG0 0
1036#define VCN0_BASE__INST5_SEG1 0
1037#define VCN0_BASE__INST5_SEG2 0
1038#define VCN0_BASE__INST5_SEG3 0
1039#define VCN0_BASE__INST5_SEG4 0
1040#define VCN0_BASE__INST5_SEG5 0
1041
1042#define VCN0_BASE__INST6_SEG0 0
1043#define VCN0_BASE__INST6_SEG1 0
1044#define VCN0_BASE__INST6_SEG2 0
1045#define VCN0_BASE__INST6_SEG3 0
1046#define VCN0_BASE__INST6_SEG4 0
1047#define VCN0_BASE__INST6_SEG5 0
1048
1049#endif