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1/*
2 * Copyright (C) 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _beige_goby_ip_offset_HEADER
22#define _beige_goby_ip_offset_HEADER
23
24
25#define MAX_INSTANCE 7
26#define MAX_SEGMENT 6
27
28
29struct IP_BASE_INSTANCE
30{
31 unsigned int segment[MAX_SEGMENT];
32};
33
34struct IP_BASE
35{
36 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
37};
38
39
40static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x02408C00, 0, 0, 0, 0 } },
41 { { 0, 0, 0, 0, 0, 0 } },
42 { { 0, 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0, 0 } },
46 { { 0, 0, 0, 0, 0, 0 } } } };
47static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
48 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
49 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
50 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
51 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
52 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
53 { { 0x00017E00, 0x0240BC00, 0, 0, 0, 0 } } } };
54static const struct IP_BASE DBGU_IO0_BASE = { { { { 0x000001E0, 0x0240B400, 0, 0, 0, 0 } },
55 { { 0x00000260, 0x02413C00, 0, 0, 0, 0 } },
56 { { 0, 0, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0, 0 } },
58 { { 0, 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0, 0 } },
60 { { 0, 0, 0, 0, 0, 0 } } } };
61static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0, 0 } },
63 { { 0, 0, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0, 0 } },
66 { { 0, 0, 0, 0, 0, 0 } },
67 { { 0, 0, 0, 0, 0, 0 } } } };
68static const struct IP_BASE DIO_BASE = { { { { 0x02404000, 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0, 0 } },
71 { { 0, 0, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0, 0 } },
74 { { 0, 0, 0, 0, 0, 0 } } } };
75static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
76 { { 0, 0, 0, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0, 0 } },
81 { { 0, 0, 0, 0, 0, 0 } } } };
82static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } },
83 { { 0, 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0, 0 } },
86 { { 0, 0, 0, 0, 0, 0 } },
87 { { 0, 0, 0, 0, 0, 0 } },
88 { { 0, 0, 0, 0, 0, 0 } } } };
89static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0, 0 } },
91 { { 0, 0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0, 0 } },
93 { { 0, 0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0, 0 } },
95 { { 0, 0, 0, 0, 0, 0 } } } };
96static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
97 { { 0, 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0, 0 } },
101 { { 0, 0, 0, 0, 0, 0 } },
102 { { 0, 0, 0, 0, 0, 0 } } } };
103static const struct IP_BASE HDA_BASE = { { { { 0x004C0000, 0x02404800, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0, 0 } },
106 { { 0, 0, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0, 0 } },
109 { { 0, 0, 0, 0, 0, 0 } } } };
110static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } },
111 { { 0, 0, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0, 0 } },
116 { { 0, 0, 0, 0, 0, 0 } } } };
117static const struct IP_BASE MMHUB_BASE = { { { { 0x0001A000, 0x02408800, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0, 0 } },
121 { { 0, 0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0, 0 } },
123 { { 0, 0, 0, 0, 0, 0 } } } };
124static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
125 { { 0, 0, 0, 0, 0, 0 } },
126 { { 0, 0, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0, 0 } } } };
131static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
132 { { 0, 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0, 0 } },
135 { { 0, 0, 0, 0, 0, 0 } },
136 { { 0, 0, 0, 0, 0, 0 } },
137 { { 0, 0, 0, 0, 0, 0 } } } };
138static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
139 { { 0, 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0, 0 } },
141 { { 0, 0, 0, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0, 0 } },
143 { { 0, 0, 0, 0, 0, 0 } },
144 { { 0, 0, 0, 0, 0, 0 } } } };
145static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } },
146 { { 0, 0, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0, 0 } },
151 { { 0, 0, 0, 0, 0, 0 } } } };
152static const struct IP_BASE PCIE0_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } },
153 { { 0, 0, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0, 0 } },
156 { { 0, 0, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0, 0 } },
158 { { 0, 0, 0, 0, 0, 0 } } } };
159static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x0001C000, 0x02402C00, 0, 0 } },
160 { { 0, 0, 0, 0, 0, 0 } },
161 { { 0, 0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0, 0 } },
163 { { 0, 0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0, 0 } },
165 { { 0, 0, 0, 0, 0, 0 } } } };
166static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x00440000, 0x02401000, 0, 0 } },
167 { { 0, 0, 0, 0, 0, 0 } },
168 { { 0, 0, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0, 0 } },
170 { { 0, 0, 0, 0, 0, 0 } },
171 { { 0, 0, 0, 0, 0, 0 } },
172 { { 0, 0, 0, 0, 0, 0 } } } };
173static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } },
174 { { 0, 0, 0, 0, 0, 0 } },
175 { { 0, 0, 0, 0, 0, 0 } },
176 { { 0, 0, 0, 0, 0, 0 } },
177 { { 0, 0, 0, 0, 0, 0 } },
178 { { 0, 0, 0, 0, 0, 0 } },
179 { { 0, 0, 0, 0, 0, 0 } } } };
180static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x02425800, 0, 0, 0, 0 } },
181 { { 0x00054000, 0x02425C00, 0, 0, 0, 0 } },
182 { { 0, 0, 0, 0, 0, 0 } },
183 { { 0, 0, 0, 0, 0, 0 } },
184 { { 0, 0, 0, 0, 0, 0 } },
185 { { 0, 0, 0, 0, 0, 0 } },
186 { { 0, 0, 0, 0, 0, 0 } } } };
187static const struct IP_BASE VCN0_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } },
188 { { 0, 0, 0, 0, 0, 0 } },
189 { { 0, 0, 0, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0, 0 } },
191 { { 0, 0, 0, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0, 0 } },
193 { { 0, 0, 0, 0, 0, 0 } } } };
194
195
196#define ATHUB_BASE__INST0_SEG0 0x00000C00
197#define ATHUB_BASE__INST0_SEG1 0x02408C00
198#define ATHUB_BASE__INST0_SEG2 0
199#define ATHUB_BASE__INST0_SEG3 0
200#define ATHUB_BASE__INST0_SEG4 0
201#define ATHUB_BASE__INST0_SEG5 0
202
203#define ATHUB_BASE__INST1_SEG0 0
204#define ATHUB_BASE__INST1_SEG1 0
205#define ATHUB_BASE__INST1_SEG2 0
206#define ATHUB_BASE__INST1_SEG3 0
207#define ATHUB_BASE__INST1_SEG4 0
208#define ATHUB_BASE__INST1_SEG5 0
209
210#define ATHUB_BASE__INST2_SEG0 0
211#define ATHUB_BASE__INST2_SEG1 0
212#define ATHUB_BASE__INST2_SEG2 0
213#define ATHUB_BASE__INST2_SEG3 0
214#define ATHUB_BASE__INST2_SEG4 0
215#define ATHUB_BASE__INST2_SEG5 0
216
217#define ATHUB_BASE__INST3_SEG0 0
218#define ATHUB_BASE__INST3_SEG1 0
219#define ATHUB_BASE__INST3_SEG2 0
220#define ATHUB_BASE__INST3_SEG3 0
221#define ATHUB_BASE__INST3_SEG4 0
222#define ATHUB_BASE__INST3_SEG5 0
223
224#define ATHUB_BASE__INST4_SEG0 0
225#define ATHUB_BASE__INST4_SEG1 0
226#define ATHUB_BASE__INST4_SEG2 0
227#define ATHUB_BASE__INST4_SEG3 0
228#define ATHUB_BASE__INST4_SEG4 0
229#define ATHUB_BASE__INST4_SEG5 0
230
231#define ATHUB_BASE__INST5_SEG0 0
232#define ATHUB_BASE__INST5_SEG1 0
233#define ATHUB_BASE__INST5_SEG2 0
234#define ATHUB_BASE__INST5_SEG3 0
235#define ATHUB_BASE__INST5_SEG4 0
236#define ATHUB_BASE__INST5_SEG5 0
237
238#define ATHUB_BASE__INST6_SEG0 0
239#define ATHUB_BASE__INST6_SEG1 0
240#define ATHUB_BASE__INST6_SEG2 0
241#define ATHUB_BASE__INST6_SEG3 0
242#define ATHUB_BASE__INST6_SEG4 0
243#define ATHUB_BASE__INST6_SEG5 0
244
245#define CLK_BASE__INST0_SEG0 0x00016C00
246#define CLK_BASE__INST0_SEG1 0x02401800
247#define CLK_BASE__INST0_SEG2 0
248#define CLK_BASE__INST0_SEG3 0
249#define CLK_BASE__INST0_SEG4 0
250#define CLK_BASE__INST0_SEG5 0
251
252#define CLK_BASE__INST1_SEG0 0x00016E00
253#define CLK_BASE__INST1_SEG1 0x02401C00
254#define CLK_BASE__INST1_SEG2 0
255#define CLK_BASE__INST1_SEG3 0
256#define CLK_BASE__INST1_SEG4 0
257#define CLK_BASE__INST1_SEG5 0
258
259#define CLK_BASE__INST2_SEG0 0x00017000
260#define CLK_BASE__INST2_SEG1 0x02402000
261#define CLK_BASE__INST2_SEG2 0
262#define CLK_BASE__INST2_SEG3 0
263#define CLK_BASE__INST2_SEG4 0
264#define CLK_BASE__INST2_SEG5 0
265
266#define CLK_BASE__INST3_SEG0 0x00017200
267#define CLK_BASE__INST3_SEG1 0x02402400
268#define CLK_BASE__INST3_SEG2 0
269#define CLK_BASE__INST3_SEG3 0
270#define CLK_BASE__INST3_SEG4 0
271#define CLK_BASE__INST3_SEG5 0
272
273#define CLK_BASE__INST4_SEG0 0x0001B000
274#define CLK_BASE__INST4_SEG1 0x0242D800
275#define CLK_BASE__INST4_SEG2 0
276#define CLK_BASE__INST4_SEG3 0
277#define CLK_BASE__INST4_SEG4 0
278#define CLK_BASE__INST4_SEG5 0
279
280#define CLK_BASE__INST5_SEG0 0x0001B200
281#define CLK_BASE__INST5_SEG1 0x0242DC00
282#define CLK_BASE__INST5_SEG2 0
283#define CLK_BASE__INST5_SEG3 0
284#define CLK_BASE__INST5_SEG4 0
285#define CLK_BASE__INST5_SEG5 0
286
287#define CLK_BASE__INST6_SEG0 0x00017E00
288#define CLK_BASE__INST6_SEG1 0x0240BC00
289#define CLK_BASE__INST6_SEG2 0
290#define CLK_BASE__INST6_SEG3 0
291#define CLK_BASE__INST6_SEG4 0
292#define CLK_BASE__INST6_SEG5 0
293
294#define DBGU_IO0_BASE__INST0_SEG0 0x000001E0
295#define DBGU_IO0_BASE__INST0_SEG1 0x0240B400
296#define DBGU_IO0_BASE__INST0_SEG2 0
297#define DBGU_IO0_BASE__INST0_SEG3 0
298#define DBGU_IO0_BASE__INST0_SEG4 0
299#define DBGU_IO0_BASE__INST0_SEG5 0
300
301#define DBGU_IO0_BASE__INST1_SEG0 0x00000260
302#define DBGU_IO0_BASE__INST1_SEG1 0x02413C00
303#define DBGU_IO0_BASE__INST1_SEG2 0
304#define DBGU_IO0_BASE__INST1_SEG3 0
305#define DBGU_IO0_BASE__INST1_SEG4 0
306#define DBGU_IO0_BASE__INST1_SEG5 0
307
308#define DBGU_IO0_BASE__INST2_SEG0 0
309#define DBGU_IO0_BASE__INST2_SEG1 0
310#define DBGU_IO0_BASE__INST2_SEG2 0
311#define DBGU_IO0_BASE__INST2_SEG3 0
312#define DBGU_IO0_BASE__INST2_SEG4 0
313#define DBGU_IO0_BASE__INST2_SEG5 0
314
315#define DBGU_IO0_BASE__INST3_SEG0 0
316#define DBGU_IO0_BASE__INST3_SEG1 0
317#define DBGU_IO0_BASE__INST3_SEG2 0
318#define DBGU_IO0_BASE__INST3_SEG3 0
319#define DBGU_IO0_BASE__INST3_SEG4 0
320#define DBGU_IO0_BASE__INST3_SEG5 0
321
322#define DBGU_IO0_BASE__INST4_SEG0 0
323#define DBGU_IO0_BASE__INST4_SEG1 0
324#define DBGU_IO0_BASE__INST4_SEG2 0
325#define DBGU_IO0_BASE__INST4_SEG3 0
326#define DBGU_IO0_BASE__INST4_SEG4 0
327#define DBGU_IO0_BASE__INST4_SEG5 0
328
329#define DBGU_IO0_BASE__INST5_SEG0 0
330#define DBGU_IO0_BASE__INST5_SEG1 0
331#define DBGU_IO0_BASE__INST5_SEG2 0
332#define DBGU_IO0_BASE__INST5_SEG3 0
333#define DBGU_IO0_BASE__INST5_SEG4 0
334#define DBGU_IO0_BASE__INST5_SEG5 0
335
336#define DBGU_IO0_BASE__INST6_SEG0 0
337#define DBGU_IO0_BASE__INST6_SEG1 0
338#define DBGU_IO0_BASE__INST6_SEG2 0
339#define DBGU_IO0_BASE__INST6_SEG3 0
340#define DBGU_IO0_BASE__INST6_SEG4 0
341#define DBGU_IO0_BASE__INST6_SEG5 0
342
343#define DF_BASE__INST0_SEG0 0x00007000
344#define DF_BASE__INST0_SEG1 0x0240B800
345#define DF_BASE__INST0_SEG2 0
346#define DF_BASE__INST0_SEG3 0
347#define DF_BASE__INST0_SEG4 0
348#define DF_BASE__INST0_SEG5 0
349
350#define DF_BASE__INST1_SEG0 0
351#define DF_BASE__INST1_SEG1 0
352#define DF_BASE__INST1_SEG2 0
353#define DF_BASE__INST1_SEG3 0
354#define DF_BASE__INST1_SEG4 0
355#define DF_BASE__INST1_SEG5 0
356
357#define DF_BASE__INST2_SEG0 0
358#define DF_BASE__INST2_SEG1 0
359#define DF_BASE__INST2_SEG2 0
360#define DF_BASE__INST2_SEG3 0
361#define DF_BASE__INST2_SEG4 0
362#define DF_BASE__INST2_SEG5 0
363
364#define DF_BASE__INST3_SEG0 0
365#define DF_BASE__INST3_SEG1 0
366#define DF_BASE__INST3_SEG2 0
367#define DF_BASE__INST3_SEG3 0
368#define DF_BASE__INST3_SEG4 0
369#define DF_BASE__INST3_SEG5 0
370
371#define DF_BASE__INST4_SEG0 0
372#define DF_BASE__INST4_SEG1 0
373#define DF_BASE__INST4_SEG2 0
374#define DF_BASE__INST4_SEG3 0
375#define DF_BASE__INST4_SEG4 0
376#define DF_BASE__INST4_SEG5 0
377
378#define DF_BASE__INST5_SEG0 0
379#define DF_BASE__INST5_SEG1 0
380#define DF_BASE__INST5_SEG2 0
381#define DF_BASE__INST5_SEG3 0
382#define DF_BASE__INST5_SEG4 0
383#define DF_BASE__INST5_SEG5 0
384
385#define DF_BASE__INST6_SEG0 0
386#define DF_BASE__INST6_SEG1 0
387#define DF_BASE__INST6_SEG2 0
388#define DF_BASE__INST6_SEG3 0
389#define DF_BASE__INST6_SEG4 0
390#define DF_BASE__INST6_SEG5 0
391
392#define DIO_BASE__INST0_SEG0 0x02404000
393#define DIO_BASE__INST0_SEG1 0
394#define DIO_BASE__INST0_SEG2 0
395#define DIO_BASE__INST0_SEG3 0
396#define DIO_BASE__INST0_SEG4 0
397#define DIO_BASE__INST0_SEG5 0
398
399#define DIO_BASE__INST1_SEG0 0
400#define DIO_BASE__INST1_SEG1 0
401#define DIO_BASE__INST1_SEG2 0
402#define DIO_BASE__INST1_SEG3 0
403#define DIO_BASE__INST1_SEG4 0
404#define DIO_BASE__INST1_SEG5 0
405
406#define DIO_BASE__INST2_SEG0 0
407#define DIO_BASE__INST2_SEG1 0
408#define DIO_BASE__INST2_SEG2 0
409#define DIO_BASE__INST2_SEG3 0
410#define DIO_BASE__INST2_SEG4 0
411#define DIO_BASE__INST2_SEG5 0
412
413#define DIO_BASE__INST3_SEG0 0
414#define DIO_BASE__INST3_SEG1 0
415#define DIO_BASE__INST3_SEG2 0
416#define DIO_BASE__INST3_SEG3 0
417#define DIO_BASE__INST3_SEG4 0
418#define DIO_BASE__INST3_SEG5 0
419
420#define DIO_BASE__INST4_SEG0 0
421#define DIO_BASE__INST4_SEG1 0
422#define DIO_BASE__INST4_SEG2 0
423#define DIO_BASE__INST4_SEG3 0
424#define DIO_BASE__INST4_SEG4 0
425#define DIO_BASE__INST4_SEG5 0
426
427#define DIO_BASE__INST5_SEG0 0
428#define DIO_BASE__INST5_SEG1 0
429#define DIO_BASE__INST5_SEG2 0
430#define DIO_BASE__INST5_SEG3 0
431#define DIO_BASE__INST5_SEG4 0
432#define DIO_BASE__INST5_SEG5 0
433
434#define DIO_BASE__INST6_SEG0 0
435#define DIO_BASE__INST6_SEG1 0
436#define DIO_BASE__INST6_SEG2 0
437#define DIO_BASE__INST6_SEG3 0
438#define DIO_BASE__INST6_SEG4 0
439#define DIO_BASE__INST6_SEG5 0
440
441#define DCN_BASE__INST0_SEG0 0x00000012
442#define DCN_BASE__INST0_SEG1 0x000000C0
443#define DCN_BASE__INST0_SEG2 0x000034C0
444#define DCN_BASE__INST0_SEG3 0x00009000
445#define DCN_BASE__INST0_SEG4 0x02403C00
446#define DCN_BASE__INST0_SEG5 0
447
448#define DCN_BASE__INST1_SEG0 0
449#define DCN_BASE__INST1_SEG1 0
450#define DCN_BASE__INST1_SEG2 0
451#define DCN_BASE__INST1_SEG3 0
452#define DCN_BASE__INST1_SEG4 0
453#define DCN_BASE__INST1_SEG5 0
454
455#define DCN_BASE__INST2_SEG0 0
456#define DCN_BASE__INST2_SEG1 0
457#define DCN_BASE__INST2_SEG2 0
458#define DCN_BASE__INST2_SEG3 0
459#define DCN_BASE__INST2_SEG4 0
460#define DCN_BASE__INST2_SEG5 0
461
462#define DCN_BASE__INST3_SEG0 0
463#define DCN_BASE__INST3_SEG1 0
464#define DCN_BASE__INST3_SEG2 0
465#define DCN_BASE__INST3_SEG3 0
466#define DCN_BASE__INST3_SEG4 0
467#define DCN_BASE__INST3_SEG5 0
468
469#define DCN_BASE__INST4_SEG0 0
470#define DCN_BASE__INST4_SEG1 0
471#define DCN_BASE__INST4_SEG2 0
472#define DCN_BASE__INST4_SEG3 0
473#define DCN_BASE__INST4_SEG4 0
474#define DCN_BASE__INST4_SEG5 0
475
476#define DCN_BASE__INST5_SEG0 0
477#define DCN_BASE__INST5_SEG1 0
478#define DCN_BASE__INST5_SEG2 0
479#define DCN_BASE__INST5_SEG3 0
480#define DCN_BASE__INST5_SEG4 0
481#define DCN_BASE__INST5_SEG5 0
482
483#define DCN_BASE__INST6_SEG0 0
484#define DCN_BASE__INST6_SEG1 0
485#define DCN_BASE__INST6_SEG2 0
486#define DCN_BASE__INST6_SEG3 0
487#define DCN_BASE__INST6_SEG4 0
488#define DCN_BASE__INST6_SEG5 0
489
490#define DPCS_BASE__INST0_SEG0 0x00000012
491#define DPCS_BASE__INST0_SEG1 0x000000C0
492#define DPCS_BASE__INST0_SEG2 0x000034C0
493#define DPCS_BASE__INST0_SEG3 0x00009000
494#define DPCS_BASE__INST0_SEG4 0x02403C00
495#define DPCS_BASE__INST0_SEG5 0
496
497#define DPCS_BASE__INST1_SEG0 0
498#define DPCS_BASE__INST1_SEG1 0
499#define DPCS_BASE__INST1_SEG2 0
500#define DPCS_BASE__INST1_SEG3 0
501#define DPCS_BASE__INST1_SEG4 0
502#define DPCS_BASE__INST1_SEG5 0
503
504#define DPCS_BASE__INST2_SEG0 0
505#define DPCS_BASE__INST2_SEG1 0
506#define DPCS_BASE__INST2_SEG2 0
507#define DPCS_BASE__INST2_SEG3 0
508#define DPCS_BASE__INST2_SEG4 0
509#define DPCS_BASE__INST2_SEG5 0
510
511#define DPCS_BASE__INST3_SEG0 0
512#define DPCS_BASE__INST3_SEG1 0
513#define DPCS_BASE__INST3_SEG2 0
514#define DPCS_BASE__INST3_SEG3 0
515#define DPCS_BASE__INST3_SEG4 0
516#define DPCS_BASE__INST3_SEG5 0
517
518#define DPCS_BASE__INST4_SEG0 0
519#define DPCS_BASE__INST4_SEG1 0
520#define DPCS_BASE__INST4_SEG2 0
521#define DPCS_BASE__INST4_SEG3 0
522#define DPCS_BASE__INST4_SEG4 0
523#define DPCS_BASE__INST4_SEG5 0
524
525#define DPCS_BASE__INST5_SEG0 0
526#define DPCS_BASE__INST5_SEG1 0
527#define DPCS_BASE__INST5_SEG2 0
528#define DPCS_BASE__INST5_SEG3 0
529#define DPCS_BASE__INST5_SEG4 0
530#define DPCS_BASE__INST5_SEG5 0
531
532#define DPCS_BASE__INST6_SEG0 0
533#define DPCS_BASE__INST6_SEG1 0
534#define DPCS_BASE__INST6_SEG2 0
535#define DPCS_BASE__INST6_SEG3 0
536#define DPCS_BASE__INST6_SEG4 0
537#define DPCS_BASE__INST6_SEG5 0
538
539#define FUSE_BASE__INST0_SEG0 0x00017400
540#define FUSE_BASE__INST0_SEG1 0x02401400
541#define FUSE_BASE__INST0_SEG2 0
542#define FUSE_BASE__INST0_SEG3 0
543#define FUSE_BASE__INST0_SEG4 0
544#define FUSE_BASE__INST0_SEG5 0
545
546#define FUSE_BASE__INST1_SEG0 0
547#define FUSE_BASE__INST1_SEG1 0
548#define FUSE_BASE__INST1_SEG2 0
549#define FUSE_BASE__INST1_SEG3 0
550#define FUSE_BASE__INST1_SEG4 0
551#define FUSE_BASE__INST1_SEG5 0
552
553#define FUSE_BASE__INST2_SEG0 0
554#define FUSE_BASE__INST2_SEG1 0
555#define FUSE_BASE__INST2_SEG2 0
556#define FUSE_BASE__INST2_SEG3 0
557#define FUSE_BASE__INST2_SEG4 0
558#define FUSE_BASE__INST2_SEG5 0
559
560#define FUSE_BASE__INST3_SEG0 0
561#define FUSE_BASE__INST3_SEG1 0
562#define FUSE_BASE__INST3_SEG2 0
563#define FUSE_BASE__INST3_SEG3 0
564#define FUSE_BASE__INST3_SEG4 0
565#define FUSE_BASE__INST3_SEG5 0
566
567#define FUSE_BASE__INST4_SEG0 0
568#define FUSE_BASE__INST4_SEG1 0
569#define FUSE_BASE__INST4_SEG2 0
570#define FUSE_BASE__INST4_SEG3 0
571#define FUSE_BASE__INST4_SEG4 0
572#define FUSE_BASE__INST4_SEG5 0
573
574#define FUSE_BASE__INST5_SEG0 0
575#define FUSE_BASE__INST5_SEG1 0
576#define FUSE_BASE__INST5_SEG2 0
577#define FUSE_BASE__INST5_SEG3 0
578#define FUSE_BASE__INST5_SEG4 0
579#define FUSE_BASE__INST5_SEG5 0
580
581#define FUSE_BASE__INST6_SEG0 0
582#define FUSE_BASE__INST6_SEG1 0
583#define FUSE_BASE__INST6_SEG2 0
584#define FUSE_BASE__INST6_SEG3 0
585#define FUSE_BASE__INST6_SEG4 0
586#define FUSE_BASE__INST6_SEG5 0
587
588#define GC_BASE__INST0_SEG0 0x00001260
589#define GC_BASE__INST0_SEG1 0x0000A000
590#define GC_BASE__INST0_SEG2 0x0001C000
591#define GC_BASE__INST0_SEG3 0x02402C00
592#define GC_BASE__INST0_SEG4 0
593#define GC_BASE__INST0_SEG5 0
594
595#define GC_BASE__INST1_SEG0 0
596#define GC_BASE__INST1_SEG1 0
597#define GC_BASE__INST1_SEG2 0
598#define GC_BASE__INST1_SEG3 0
599#define GC_BASE__INST1_SEG4 0
600#define GC_BASE__INST1_SEG5 0
601
602#define GC_BASE__INST2_SEG0 0
603#define GC_BASE__INST2_SEG1 0
604#define GC_BASE__INST2_SEG2 0
605#define GC_BASE__INST2_SEG3 0
606#define GC_BASE__INST2_SEG4 0
607#define GC_BASE__INST2_SEG5 0
608
609#define GC_BASE__INST3_SEG0 0
610#define GC_BASE__INST3_SEG1 0
611#define GC_BASE__INST3_SEG2 0
612#define GC_BASE__INST3_SEG3 0
613#define GC_BASE__INST3_SEG4 0
614#define GC_BASE__INST3_SEG5 0
615
616#define GC_BASE__INST4_SEG0 0
617#define GC_BASE__INST4_SEG1 0
618#define GC_BASE__INST4_SEG2 0
619#define GC_BASE__INST4_SEG3 0
620#define GC_BASE__INST4_SEG4 0
621#define GC_BASE__INST4_SEG5 0
622
623#define GC_BASE__INST5_SEG0 0
624#define GC_BASE__INST5_SEG1 0
625#define GC_BASE__INST5_SEG2 0
626#define GC_BASE__INST5_SEG3 0
627#define GC_BASE__INST5_SEG4 0
628#define GC_BASE__INST5_SEG5 0
629
630#define GC_BASE__INST6_SEG0 0
631#define GC_BASE__INST6_SEG1 0
632#define GC_BASE__INST6_SEG2 0
633#define GC_BASE__INST6_SEG3 0
634#define GC_BASE__INST6_SEG4 0
635#define GC_BASE__INST6_SEG5 0
636
637#define HDA_BASE__INST0_SEG0 0x004C0000
638#define HDA_BASE__INST0_SEG1 0x02404800
639#define HDA_BASE__INST0_SEG2 0
640#define HDA_BASE__INST0_SEG3 0
641#define HDA_BASE__INST0_SEG4 0
642#define HDA_BASE__INST0_SEG5 0
643
644#define HDA_BASE__INST1_SEG0 0
645#define HDA_BASE__INST1_SEG1 0
646#define HDA_BASE__INST1_SEG2 0
647#define HDA_BASE__INST1_SEG3 0
648#define HDA_BASE__INST1_SEG4 0
649#define HDA_BASE__INST1_SEG5 0
650
651#define HDA_BASE__INST2_SEG0 0
652#define HDA_BASE__INST2_SEG1 0
653#define HDA_BASE__INST2_SEG2 0
654#define HDA_BASE__INST2_SEG3 0
655#define HDA_BASE__INST2_SEG4 0
656#define HDA_BASE__INST2_SEG5 0
657
658#define HDA_BASE__INST3_SEG0 0
659#define HDA_BASE__INST3_SEG1 0
660#define HDA_BASE__INST3_SEG2 0
661#define HDA_BASE__INST3_SEG3 0
662#define HDA_BASE__INST3_SEG4 0
663#define HDA_BASE__INST3_SEG5 0
664
665#define HDA_BASE__INST4_SEG0 0
666#define HDA_BASE__INST4_SEG1 0
667#define HDA_BASE__INST4_SEG2 0
668#define HDA_BASE__INST4_SEG3 0
669#define HDA_BASE__INST4_SEG4 0
670#define HDA_BASE__INST4_SEG5 0
671
672#define HDA_BASE__INST5_SEG0 0
673#define HDA_BASE__INST5_SEG1 0
674#define HDA_BASE__INST5_SEG2 0
675#define HDA_BASE__INST5_SEG3 0
676#define HDA_BASE__INST5_SEG4 0
677#define HDA_BASE__INST5_SEG5 0
678
679#define HDA_BASE__INST6_SEG0 0
680#define HDA_BASE__INST6_SEG1 0
681#define HDA_BASE__INST6_SEG2 0
682#define HDA_BASE__INST6_SEG3 0
683#define HDA_BASE__INST6_SEG4 0
684#define HDA_BASE__INST6_SEG5 0
685
686#define HDP_BASE__INST0_SEG0 0x00000F20
687#define HDP_BASE__INST0_SEG1 0x0240A400
688#define HDP_BASE__INST0_SEG2 0
689#define HDP_BASE__INST0_SEG3 0
690#define HDP_BASE__INST0_SEG4 0
691#define HDP_BASE__INST0_SEG5 0
692
693#define HDP_BASE__INST1_SEG0 0
694#define HDP_BASE__INST1_SEG1 0
695#define HDP_BASE__INST1_SEG2 0
696#define HDP_BASE__INST1_SEG3 0
697#define HDP_BASE__INST1_SEG4 0
698#define HDP_BASE__INST1_SEG5 0
699
700#define HDP_BASE__INST2_SEG0 0
701#define HDP_BASE__INST2_SEG1 0
702#define HDP_BASE__INST2_SEG2 0
703#define HDP_BASE__INST2_SEG3 0
704#define HDP_BASE__INST2_SEG4 0
705#define HDP_BASE__INST2_SEG5 0
706
707#define HDP_BASE__INST3_SEG0 0
708#define HDP_BASE__INST3_SEG1 0
709#define HDP_BASE__INST3_SEG2 0
710#define HDP_BASE__INST3_SEG3 0
711#define HDP_BASE__INST3_SEG4 0
712#define HDP_BASE__INST3_SEG5 0
713
714#define HDP_BASE__INST4_SEG0 0
715#define HDP_BASE__INST4_SEG1 0
716#define HDP_BASE__INST4_SEG2 0
717#define HDP_BASE__INST4_SEG3 0
718#define HDP_BASE__INST4_SEG4 0
719#define HDP_BASE__INST4_SEG5 0
720
721#define HDP_BASE__INST5_SEG0 0
722#define HDP_BASE__INST5_SEG1 0
723#define HDP_BASE__INST5_SEG2 0
724#define HDP_BASE__INST5_SEG3 0
725#define HDP_BASE__INST5_SEG4 0
726#define HDP_BASE__INST5_SEG5 0
727
728#define HDP_BASE__INST6_SEG0 0
729#define HDP_BASE__INST6_SEG1 0
730#define HDP_BASE__INST6_SEG2 0
731#define HDP_BASE__INST6_SEG3 0
732#define HDP_BASE__INST6_SEG4 0
733#define HDP_BASE__INST6_SEG5 0
734
735#define MMHUB_BASE__INST0_SEG0 0x0001A000
736#define MMHUB_BASE__INST0_SEG1 0x02408800
737#define MMHUB_BASE__INST0_SEG2 0
738#define MMHUB_BASE__INST0_SEG3 0
739#define MMHUB_BASE__INST0_SEG4 0
740#define MMHUB_BASE__INST0_SEG5 0
741
742#define MMHUB_BASE__INST1_SEG0 0
743#define MMHUB_BASE__INST1_SEG1 0
744#define MMHUB_BASE__INST1_SEG2 0
745#define MMHUB_BASE__INST1_SEG3 0
746#define MMHUB_BASE__INST1_SEG4 0
747#define MMHUB_BASE__INST1_SEG5 0
748
749#define MMHUB_BASE__INST2_SEG0 0
750#define MMHUB_BASE__INST2_SEG1 0
751#define MMHUB_BASE__INST2_SEG2 0
752#define MMHUB_BASE__INST2_SEG3 0
753#define MMHUB_BASE__INST2_SEG4 0
754#define MMHUB_BASE__INST2_SEG5 0
755
756#define MMHUB_BASE__INST3_SEG0 0
757#define MMHUB_BASE__INST3_SEG1 0
758#define MMHUB_BASE__INST3_SEG2 0
759#define MMHUB_BASE__INST3_SEG3 0
760#define MMHUB_BASE__INST3_SEG4 0
761#define MMHUB_BASE__INST3_SEG5 0
762
763#define MMHUB_BASE__INST4_SEG0 0
764#define MMHUB_BASE__INST4_SEG1 0
765#define MMHUB_BASE__INST4_SEG2 0
766#define MMHUB_BASE__INST4_SEG3 0
767#define MMHUB_BASE__INST4_SEG4 0
768#define MMHUB_BASE__INST4_SEG5 0
769
770#define MMHUB_BASE__INST5_SEG0 0
771#define MMHUB_BASE__INST5_SEG1 0
772#define MMHUB_BASE__INST5_SEG2 0
773#define MMHUB_BASE__INST5_SEG3 0
774#define MMHUB_BASE__INST5_SEG4 0
775#define MMHUB_BASE__INST5_SEG5 0
776
777#define MMHUB_BASE__INST6_SEG0 0
778#define MMHUB_BASE__INST6_SEG1 0
779#define MMHUB_BASE__INST6_SEG2 0
780#define MMHUB_BASE__INST6_SEG3 0
781#define MMHUB_BASE__INST6_SEG4 0
782#define MMHUB_BASE__INST6_SEG5 0
783
784#define MP0_BASE__INST0_SEG0 0x00016000
785#define MP0_BASE__INST0_SEG1 0x00DC0000
786#define MP0_BASE__INST0_SEG2 0x00E00000
787#define MP0_BASE__INST0_SEG3 0x00E40000
788#define MP0_BASE__INST0_SEG4 0x0243FC00
789#define MP0_BASE__INST0_SEG5 0
790
791#define MP0_BASE__INST1_SEG0 0
792#define MP0_BASE__INST1_SEG1 0
793#define MP0_BASE__INST1_SEG2 0
794#define MP0_BASE__INST1_SEG3 0
795#define MP0_BASE__INST1_SEG4 0
796#define MP0_BASE__INST1_SEG5 0
797
798#define MP0_BASE__INST2_SEG0 0
799#define MP0_BASE__INST2_SEG1 0
800#define MP0_BASE__INST2_SEG2 0
801#define MP0_BASE__INST2_SEG3 0
802#define MP0_BASE__INST2_SEG4 0
803#define MP0_BASE__INST2_SEG5 0
804
805#define MP0_BASE__INST3_SEG0 0
806#define MP0_BASE__INST3_SEG1 0
807#define MP0_BASE__INST3_SEG2 0
808#define MP0_BASE__INST3_SEG3 0
809#define MP0_BASE__INST3_SEG4 0
810#define MP0_BASE__INST3_SEG5 0
811
812#define MP0_BASE__INST4_SEG0 0
813#define MP0_BASE__INST4_SEG1 0
814#define MP0_BASE__INST4_SEG2 0
815#define MP0_BASE__INST4_SEG3 0
816#define MP0_BASE__INST4_SEG4 0
817#define MP0_BASE__INST4_SEG5 0
818
819#define MP0_BASE__INST5_SEG0 0
820#define MP0_BASE__INST5_SEG1 0
821#define MP0_BASE__INST5_SEG2 0
822#define MP0_BASE__INST5_SEG3 0
823#define MP0_BASE__INST5_SEG4 0
824#define MP0_BASE__INST5_SEG5 0
825
826#define MP0_BASE__INST6_SEG0 0
827#define MP0_BASE__INST6_SEG1 0
828#define MP0_BASE__INST6_SEG2 0
829#define MP0_BASE__INST6_SEG3 0
830#define MP0_BASE__INST6_SEG4 0
831#define MP0_BASE__INST6_SEG5 0
832
833#define MP1_BASE__INST0_SEG0 0x00016000
834#define MP1_BASE__INST0_SEG1 0x00DC0000
835#define MP1_BASE__INST0_SEG2 0x00E00000
836#define MP1_BASE__INST0_SEG3 0x00E40000
837#define MP1_BASE__INST0_SEG4 0x0243FC00
838#define MP1_BASE__INST0_SEG5 0
839
840#define MP1_BASE__INST1_SEG0 0
841#define MP1_BASE__INST1_SEG1 0
842#define MP1_BASE__INST1_SEG2 0
843#define MP1_BASE__INST1_SEG3 0
844#define MP1_BASE__INST1_SEG4 0
845#define MP1_BASE__INST1_SEG5 0
846
847#define MP1_BASE__INST2_SEG0 0
848#define MP1_BASE__INST2_SEG1 0
849#define MP1_BASE__INST2_SEG2 0
850#define MP1_BASE__INST2_SEG3 0
851#define MP1_BASE__INST2_SEG4 0
852#define MP1_BASE__INST2_SEG5 0
853
854#define MP1_BASE__INST3_SEG0 0
855#define MP1_BASE__INST3_SEG1 0
856#define MP1_BASE__INST3_SEG2 0
857#define MP1_BASE__INST3_SEG3 0
858#define MP1_BASE__INST3_SEG4 0
859#define MP1_BASE__INST3_SEG5 0
860
861#define MP1_BASE__INST4_SEG0 0
862#define MP1_BASE__INST4_SEG1 0
863#define MP1_BASE__INST4_SEG2 0
864#define MP1_BASE__INST4_SEG3 0
865#define MP1_BASE__INST4_SEG4 0
866#define MP1_BASE__INST4_SEG5 0
867
868#define MP1_BASE__INST5_SEG0 0
869#define MP1_BASE__INST5_SEG1 0
870#define MP1_BASE__INST5_SEG2 0
871#define MP1_BASE__INST5_SEG3 0
872#define MP1_BASE__INST5_SEG4 0
873#define MP1_BASE__INST5_SEG5 0
874
875#define MP1_BASE__INST6_SEG0 0
876#define MP1_BASE__INST6_SEG1 0
877#define MP1_BASE__INST6_SEG2 0
878#define MP1_BASE__INST6_SEG3 0
879#define MP1_BASE__INST6_SEG4 0
880#define MP1_BASE__INST6_SEG5 0
881
882#define NBIO_BASE__INST0_SEG0 0x00000000
883#define NBIO_BASE__INST0_SEG1 0x00000014
884#define NBIO_BASE__INST0_SEG2 0x00000D20
885#define NBIO_BASE__INST0_SEG3 0x00010400
886#define NBIO_BASE__INST0_SEG4 0x0241B000
887#define NBIO_BASE__INST0_SEG5 0x04040000
888
889#define NBIO_BASE__INST1_SEG0 0
890#define NBIO_BASE__INST1_SEG1 0
891#define NBIO_BASE__INST1_SEG2 0
892#define NBIO_BASE__INST1_SEG3 0
893#define NBIO_BASE__INST1_SEG4 0
894#define NBIO_BASE__INST1_SEG5 0
895
896#define NBIO_BASE__INST2_SEG0 0
897#define NBIO_BASE__INST2_SEG1 0
898#define NBIO_BASE__INST2_SEG2 0
899#define NBIO_BASE__INST2_SEG3 0
900#define NBIO_BASE__INST2_SEG4 0
901#define NBIO_BASE__INST2_SEG5 0
902
903#define NBIO_BASE__INST3_SEG0 0
904#define NBIO_BASE__INST3_SEG1 0
905#define NBIO_BASE__INST3_SEG2 0
906#define NBIO_BASE__INST3_SEG3 0
907#define NBIO_BASE__INST3_SEG4 0
908#define NBIO_BASE__INST3_SEG5 0
909
910#define NBIO_BASE__INST4_SEG0 0
911#define NBIO_BASE__INST4_SEG1 0
912#define NBIO_BASE__INST4_SEG2 0
913#define NBIO_BASE__INST4_SEG3 0
914#define NBIO_BASE__INST4_SEG4 0
915#define NBIO_BASE__INST4_SEG5 0
916
917#define NBIO_BASE__INST5_SEG0 0
918#define NBIO_BASE__INST5_SEG1 0
919#define NBIO_BASE__INST5_SEG2 0
920#define NBIO_BASE__INST5_SEG3 0
921#define NBIO_BASE__INST5_SEG4 0
922#define NBIO_BASE__INST5_SEG5 0
923
924#define NBIO_BASE__INST6_SEG0 0
925#define NBIO_BASE__INST6_SEG1 0
926#define NBIO_BASE__INST6_SEG2 0
927#define NBIO_BASE__INST6_SEG3 0
928#define NBIO_BASE__INST6_SEG4 0
929#define NBIO_BASE__INST6_SEG5 0
930
931#define OSSSYS_BASE__INST0_SEG0 0x000010A0
932#define OSSSYS_BASE__INST0_SEG1 0x0240A000
933#define OSSSYS_BASE__INST0_SEG2 0
934#define OSSSYS_BASE__INST0_SEG3 0
935#define OSSSYS_BASE__INST0_SEG4 0
936#define OSSSYS_BASE__INST0_SEG5 0
937
938#define OSSSYS_BASE__INST1_SEG0 0
939#define OSSSYS_BASE__INST1_SEG1 0
940#define OSSSYS_BASE__INST1_SEG2 0
941#define OSSSYS_BASE__INST1_SEG3 0
942#define OSSSYS_BASE__INST1_SEG4 0
943#define OSSSYS_BASE__INST1_SEG5 0
944
945#define OSSSYS_BASE__INST2_SEG0 0
946#define OSSSYS_BASE__INST2_SEG1 0
947#define OSSSYS_BASE__INST2_SEG2 0
948#define OSSSYS_BASE__INST2_SEG3 0
949#define OSSSYS_BASE__INST2_SEG4 0
950#define OSSSYS_BASE__INST2_SEG5 0
951
952#define OSSSYS_BASE__INST3_SEG0 0
953#define OSSSYS_BASE__INST3_SEG1 0
954#define OSSSYS_BASE__INST3_SEG2 0
955#define OSSSYS_BASE__INST3_SEG3 0
956#define OSSSYS_BASE__INST3_SEG4 0
957#define OSSSYS_BASE__INST3_SEG5 0
958
959#define OSSSYS_BASE__INST4_SEG0 0
960#define OSSSYS_BASE__INST4_SEG1 0
961#define OSSSYS_BASE__INST4_SEG2 0
962#define OSSSYS_BASE__INST4_SEG3 0
963#define OSSSYS_BASE__INST4_SEG4 0
964#define OSSSYS_BASE__INST4_SEG5 0
965
966#define OSSSYS_BASE__INST5_SEG0 0
967#define OSSSYS_BASE__INST5_SEG1 0
968#define OSSSYS_BASE__INST5_SEG2 0
969#define OSSSYS_BASE__INST5_SEG3 0
970#define OSSSYS_BASE__INST5_SEG4 0
971#define OSSSYS_BASE__INST5_SEG5 0
972
973#define OSSSYS_BASE__INST6_SEG0 0
974#define OSSSYS_BASE__INST6_SEG1 0
975#define OSSSYS_BASE__INST6_SEG2 0
976#define OSSSYS_BASE__INST6_SEG3 0
977#define OSSSYS_BASE__INST6_SEG4 0
978#define OSSSYS_BASE__INST6_SEG5 0
979
980#define PCIE0_BASE__INST0_SEG0 0x00000000
981#define PCIE0_BASE__INST0_SEG1 0x00000014
982#define PCIE0_BASE__INST0_SEG2 0x00000D20
983#define PCIE0_BASE__INST0_SEG3 0x00010400
984#define PCIE0_BASE__INST0_SEG4 0x0241B000
985#define PCIE0_BASE__INST0_SEG5 0x04040000
986
987#define PCIE0_BASE__INST1_SEG0 0
988#define PCIE0_BASE__INST1_SEG1 0
989#define PCIE0_BASE__INST1_SEG2 0
990#define PCIE0_BASE__INST1_SEG3 0
991#define PCIE0_BASE__INST1_SEG4 0
992#define PCIE0_BASE__INST1_SEG5 0
993
994#define PCIE0_BASE__INST2_SEG0 0
995#define PCIE0_BASE__INST2_SEG1 0
996#define PCIE0_BASE__INST2_SEG2 0
997#define PCIE0_BASE__INST2_SEG3 0
998#define PCIE0_BASE__INST2_SEG4 0
999#define PCIE0_BASE__INST2_SEG5 0
1000
1001#define PCIE0_BASE__INST3_SEG0 0
1002#define PCIE0_BASE__INST3_SEG1 0
1003#define PCIE0_BASE__INST3_SEG2 0
1004#define PCIE0_BASE__INST3_SEG3 0
1005#define PCIE0_BASE__INST3_SEG4 0
1006#define PCIE0_BASE__INST3_SEG5 0
1007
1008#define PCIE0_BASE__INST4_SEG0 0
1009#define PCIE0_BASE__INST4_SEG1 0
1010#define PCIE0_BASE__INST4_SEG2 0
1011#define PCIE0_BASE__INST4_SEG3 0
1012#define PCIE0_BASE__INST4_SEG4 0
1013#define PCIE0_BASE__INST4_SEG5 0
1014
1015#define PCIE0_BASE__INST5_SEG0 0
1016#define PCIE0_BASE__INST5_SEG1 0
1017#define PCIE0_BASE__INST5_SEG2 0
1018#define PCIE0_BASE__INST5_SEG3 0
1019#define PCIE0_BASE__INST5_SEG4 0
1020#define PCIE0_BASE__INST5_SEG5 0
1021
1022#define PCIE0_BASE__INST6_SEG0 0
1023#define PCIE0_BASE__INST6_SEG1 0
1024#define PCIE0_BASE__INST6_SEG2 0
1025#define PCIE0_BASE__INST6_SEG3 0
1026#define PCIE0_BASE__INST6_SEG4 0
1027#define PCIE0_BASE__INST6_SEG5 0
1028
1029#define SDMA0_BASE__INST0_SEG0 0x00001260
1030#define SDMA0_BASE__INST0_SEG1 0x0000A000
1031#define SDMA0_BASE__INST0_SEG2 0x0001C000
1032#define SDMA0_BASE__INST0_SEG3 0x02402C00
1033#define SDMA0_BASE__INST0_SEG4 0
1034#define SDMA0_BASE__INST0_SEG5 0
1035
1036#define SDMA0_BASE__INST1_SEG0 0
1037#define SDMA0_BASE__INST1_SEG1 0
1038#define SDMA0_BASE__INST1_SEG2 0
1039#define SDMA0_BASE__INST1_SEG3 0
1040#define SDMA0_BASE__INST1_SEG4 0
1041#define SDMA0_BASE__INST1_SEG5 0
1042
1043#define SDMA0_BASE__INST2_SEG0 0
1044#define SDMA0_BASE__INST2_SEG1 0
1045#define SDMA0_BASE__INST2_SEG2 0
1046#define SDMA0_BASE__INST2_SEG3 0
1047#define SDMA0_BASE__INST2_SEG4 0
1048#define SDMA0_BASE__INST2_SEG5 0
1049
1050#define SDMA0_BASE__INST3_SEG0 0
1051#define SDMA0_BASE__INST3_SEG1 0
1052#define SDMA0_BASE__INST3_SEG2 0
1053#define SDMA0_BASE__INST3_SEG3 0
1054#define SDMA0_BASE__INST3_SEG4 0
1055#define SDMA0_BASE__INST3_SEG5 0
1056
1057#define SDMA0_BASE__INST4_SEG0 0
1058#define SDMA0_BASE__INST4_SEG1 0
1059#define SDMA0_BASE__INST4_SEG2 0
1060#define SDMA0_BASE__INST4_SEG3 0
1061#define SDMA0_BASE__INST4_SEG4 0
1062#define SDMA0_BASE__INST4_SEG5 0
1063
1064#define SDMA0_BASE__INST5_SEG0 0
1065#define SDMA0_BASE__INST5_SEG1 0
1066#define SDMA0_BASE__INST5_SEG2 0
1067#define SDMA0_BASE__INST5_SEG3 0
1068#define SDMA0_BASE__INST5_SEG4 0
1069#define SDMA0_BASE__INST5_SEG5 0
1070
1071#define SDMA0_BASE__INST6_SEG0 0
1072#define SDMA0_BASE__INST6_SEG1 0
1073#define SDMA0_BASE__INST6_SEG2 0
1074#define SDMA0_BASE__INST6_SEG3 0
1075#define SDMA0_BASE__INST6_SEG4 0
1076#define SDMA0_BASE__INST6_SEG5 0
1077
1078#define SMUIO_BASE__INST0_SEG0 0x00016800
1079#define SMUIO_BASE__INST0_SEG1 0x00016A00
1080#define SMUIO_BASE__INST0_SEG2 0x00440000
1081#define SMUIO_BASE__INST0_SEG3 0x02401000
1082#define SMUIO_BASE__INST0_SEG4 0
1083#define SMUIO_BASE__INST0_SEG5 0
1084
1085#define SMUIO_BASE__INST1_SEG0 0
1086#define SMUIO_BASE__INST1_SEG1 0
1087#define SMUIO_BASE__INST1_SEG2 0
1088#define SMUIO_BASE__INST1_SEG3 0
1089#define SMUIO_BASE__INST1_SEG4 0
1090#define SMUIO_BASE__INST1_SEG5 0
1091
1092#define SMUIO_BASE__INST2_SEG0 0
1093#define SMUIO_BASE__INST2_SEG1 0
1094#define SMUIO_BASE__INST2_SEG2 0
1095#define SMUIO_BASE__INST2_SEG3 0
1096#define SMUIO_BASE__INST2_SEG4 0
1097#define SMUIO_BASE__INST2_SEG5 0
1098
1099#define SMUIO_BASE__INST3_SEG0 0
1100#define SMUIO_BASE__INST3_SEG1 0
1101#define SMUIO_BASE__INST3_SEG2 0
1102#define SMUIO_BASE__INST3_SEG3 0
1103#define SMUIO_BASE__INST3_SEG4 0
1104#define SMUIO_BASE__INST3_SEG5 0
1105
1106#define SMUIO_BASE__INST4_SEG0 0
1107#define SMUIO_BASE__INST4_SEG1 0
1108#define SMUIO_BASE__INST4_SEG2 0
1109#define SMUIO_BASE__INST4_SEG3 0
1110#define SMUIO_BASE__INST4_SEG4 0
1111#define SMUIO_BASE__INST4_SEG5 0
1112
1113#define SMUIO_BASE__INST5_SEG0 0
1114#define SMUIO_BASE__INST5_SEG1 0
1115#define SMUIO_BASE__INST5_SEG2 0
1116#define SMUIO_BASE__INST5_SEG3 0
1117#define SMUIO_BASE__INST5_SEG4 0
1118#define SMUIO_BASE__INST5_SEG5 0
1119
1120#define SMUIO_BASE__INST6_SEG0 0
1121#define SMUIO_BASE__INST6_SEG1 0
1122#define SMUIO_BASE__INST6_SEG2 0
1123#define SMUIO_BASE__INST6_SEG3 0
1124#define SMUIO_BASE__INST6_SEG4 0
1125#define SMUIO_BASE__INST6_SEG5 0
1126
1127#define THM_BASE__INST0_SEG0 0x00016600
1128#define THM_BASE__INST0_SEG1 0x02400C00
1129#define THM_BASE__INST0_SEG2 0
1130#define THM_BASE__INST0_SEG3 0
1131#define THM_BASE__INST0_SEG4 0
1132#define THM_BASE__INST0_SEG5 0
1133
1134#define THM_BASE__INST1_SEG0 0
1135#define THM_BASE__INST1_SEG1 0
1136#define THM_BASE__INST1_SEG2 0
1137#define THM_BASE__INST1_SEG3 0
1138#define THM_BASE__INST1_SEG4 0
1139#define THM_BASE__INST1_SEG5 0
1140
1141#define THM_BASE__INST2_SEG0 0
1142#define THM_BASE__INST2_SEG1 0
1143#define THM_BASE__INST2_SEG2 0
1144#define THM_BASE__INST2_SEG3 0
1145#define THM_BASE__INST2_SEG4 0
1146#define THM_BASE__INST2_SEG5 0
1147
1148#define THM_BASE__INST3_SEG0 0
1149#define THM_BASE__INST3_SEG1 0
1150#define THM_BASE__INST3_SEG2 0
1151#define THM_BASE__INST3_SEG3 0
1152#define THM_BASE__INST3_SEG4 0
1153#define THM_BASE__INST3_SEG5 0
1154
1155#define THM_BASE__INST4_SEG0 0
1156#define THM_BASE__INST4_SEG1 0
1157#define THM_BASE__INST4_SEG2 0
1158#define THM_BASE__INST4_SEG3 0
1159#define THM_BASE__INST4_SEG4 0
1160#define THM_BASE__INST4_SEG5 0
1161
1162#define THM_BASE__INST5_SEG0 0
1163#define THM_BASE__INST5_SEG1 0
1164#define THM_BASE__INST5_SEG2 0
1165#define THM_BASE__INST5_SEG3 0
1166#define THM_BASE__INST5_SEG4 0
1167#define THM_BASE__INST5_SEG5 0
1168
1169#define THM_BASE__INST6_SEG0 0
1170#define THM_BASE__INST6_SEG1 0
1171#define THM_BASE__INST6_SEG2 0
1172#define THM_BASE__INST6_SEG3 0
1173#define THM_BASE__INST6_SEG4 0
1174#define THM_BASE__INST6_SEG5 0
1175
1176#define UMC_BASE__INST0_SEG0 0x00014000
1177#define UMC_BASE__INST0_SEG1 0x02425800
1178#define UMC_BASE__INST0_SEG2 0
1179#define UMC_BASE__INST0_SEG3 0
1180#define UMC_BASE__INST0_SEG4 0
1181#define UMC_BASE__INST0_SEG5 0
1182
1183#define UMC_BASE__INST1_SEG0 0x00054000
1184#define UMC_BASE__INST1_SEG1 0x02425C00
1185#define UMC_BASE__INST1_SEG2 0
1186#define UMC_BASE__INST1_SEG3 0
1187#define UMC_BASE__INST1_SEG4 0
1188#define UMC_BASE__INST1_SEG5 0
1189
1190#define UMC_BASE__INST2_SEG0 0
1191#define UMC_BASE__INST2_SEG1 0
1192#define UMC_BASE__INST2_SEG2 0
1193#define UMC_BASE__INST2_SEG3 0
1194#define UMC_BASE__INST2_SEG4 0
1195#define UMC_BASE__INST2_SEG5 0
1196
1197#define UMC_BASE__INST3_SEG0 0
1198#define UMC_BASE__INST3_SEG1 0
1199#define UMC_BASE__INST3_SEG2 0
1200#define UMC_BASE__INST3_SEG3 0
1201#define UMC_BASE__INST3_SEG4 0
1202#define UMC_BASE__INST3_SEG5 0
1203
1204#define UMC_BASE__INST4_SEG0 0
1205#define UMC_BASE__INST4_SEG1 0
1206#define UMC_BASE__INST4_SEG2 0
1207#define UMC_BASE__INST4_SEG3 0
1208#define UMC_BASE__INST4_SEG4 0
1209#define UMC_BASE__INST4_SEG5 0
1210
1211#define UMC_BASE__INST5_SEG0 0
1212#define UMC_BASE__INST5_SEG1 0
1213#define UMC_BASE__INST5_SEG2 0
1214#define UMC_BASE__INST5_SEG3 0
1215#define UMC_BASE__INST5_SEG4 0
1216#define UMC_BASE__INST5_SEG5 0
1217
1218#define UMC_BASE__INST6_SEG0 0
1219#define UMC_BASE__INST6_SEG1 0
1220#define UMC_BASE__INST6_SEG2 0
1221#define UMC_BASE__INST6_SEG3 0
1222#define UMC_BASE__INST6_SEG4 0
1223#define UMC_BASE__INST6_SEG5 0
1224
1225#define VCN0_BASE__INST0_SEG0 0x00007800
1226#define VCN0_BASE__INST0_SEG1 0x00007E00
1227#define VCN0_BASE__INST0_SEG2 0x02403000
1228#define VCN0_BASE__INST0_SEG3 0
1229#define VCN0_BASE__INST0_SEG4 0
1230#define VCN0_BASE__INST0_SEG5 0
1231
1232#define VCN0_BASE__INST1_SEG0 0
1233#define VCN0_BASE__INST1_SEG1 0
1234#define VCN0_BASE__INST1_SEG2 0
1235#define VCN0_BASE__INST1_SEG3 0
1236#define VCN0_BASE__INST1_SEG4 0
1237#define VCN0_BASE__INST1_SEG5 0
1238
1239#define VCN0_BASE__INST2_SEG0 0
1240#define VCN0_BASE__INST2_SEG1 0
1241#define VCN0_BASE__INST2_SEG2 0
1242#define VCN0_BASE__INST2_SEG3 0
1243#define VCN0_BASE__INST2_SEG4 0
1244#define VCN0_BASE__INST2_SEG5 0
1245
1246#define VCN0_BASE__INST3_SEG0 0
1247#define VCN0_BASE__INST3_SEG1 0
1248#define VCN0_BASE__INST3_SEG2 0
1249#define VCN0_BASE__INST3_SEG3 0
1250#define VCN0_BASE__INST3_SEG4 0
1251#define VCN0_BASE__INST3_SEG5 0
1252
1253#define VCN0_BASE__INST4_SEG0 0
1254#define VCN0_BASE__INST4_SEG1 0
1255#define VCN0_BASE__INST4_SEG2 0
1256#define VCN0_BASE__INST4_SEG3 0
1257#define VCN0_BASE__INST4_SEG4 0
1258#define VCN0_BASE__INST4_SEG5 0
1259
1260#define VCN0_BASE__INST5_SEG0 0
1261#define VCN0_BASE__INST5_SEG1 0
1262#define VCN0_BASE__INST5_SEG2 0
1263#define VCN0_BASE__INST5_SEG3 0
1264#define VCN0_BASE__INST5_SEG4 0
1265#define VCN0_BASE__INST5_SEG5 0
1266
1267#define VCN0_BASE__INST6_SEG0 0
1268#define VCN0_BASE__INST6_SEG1 0
1269#define VCN0_BASE__INST6_SEG2 0
1270#define VCN0_BASE__INST6_SEG3 0
1271#define VCN0_BASE__INST6_SEG4 0
1272#define VCN0_BASE__INST6_SEG5 0
1273
1274#endif