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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DMUB_CMD_H
27#define DMUB_CMD_H
28
29#if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30#include "dmub_fw_types.h"
31#include "include_legacy/atomfirmware.h"
32
33#if defined(_TEST_HARNESS)
34#include <string.h>
35#endif
36#else
37
38#include <asm/byteorder.h>
39#include <linux/types.h>
40#include <linux/string.h>
41#include <linux/delay.h>
42
43#include "atomfirmware.h"
44
45#endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
46
47//<DMUB_TYPES>==================================================================
48/* Basic type definitions. */
49
50#define __forceinline inline
51
52/**
53 * Flag from driver to indicate that ABM should be disabled gradually
54 * by slowly reversing all backlight programming and pixel compensation.
55 */
56#define SET_ABM_PIPE_GRADUALLY_DISABLE 0
57
58/**
59 * Flag from driver to indicate that ABM should be disabled immediately
60 * and undo all backlight programming and pixel compensation.
61 */
62#define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
63
64/**
65 * Flag from driver to indicate that ABM should be disabled immediately
66 * and keep the current backlight programming and pixel compensation.
67 */
68#define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
69
70/**
71 * Flag from driver to set the current ABM pipe index or ABM operating level.
72 */
73#define SET_ABM_PIPE_NORMAL 1
74
75/**
76 * Number of ambient light levels in ABM algorithm.
77 */
78#define NUM_AMBI_LEVEL 5
79
80/**
81 * Number of operating/aggression levels in ABM algorithm.
82 */
83#define NUM_AGGR_LEVEL 4
84
85/**
86 * Number of segments in the gamma curve.
87 */
88#define NUM_POWER_FN_SEGS 8
89
90/**
91 * Number of segments in the backlight curve.
92 */
93#define NUM_BL_CURVE_SEGS 16
94
95/* Maximum number of SubVP streams */
96#define DMUB_MAX_SUBVP_STREAMS 2
97
98/* Define max FPO streams as 4 for now. Current implementation today
99 * only supports 1, but could be more in the future. Reduce array
100 * size to ensure the command size remains less than 64 bytes if
101 * adding new fields.
102 */
103#define DMUB_MAX_FPO_STREAMS 4
104
105/* Maximum number of streams on any ASIC. */
106#define DMUB_MAX_STREAMS 6
107
108/* Maximum number of planes on any ASIC. */
109#define DMUB_MAX_PLANES 6
110
111/* Trace buffer offset for entry */
112#define TRACE_BUFFER_ENTRY_OFFSET 16
113
114/**
115 * Maximum number of dirty rects supported by FW.
116 */
117#define DMUB_MAX_DIRTY_RECTS 3
118
119/**
120 *
121 * PSR control version legacy
122 */
123#define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
124/**
125 * PSR control version with multi edp support
126 */
127#define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
128
129
130/**
131 * ABM control version legacy
132 */
133#define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
134
135/**
136 * ABM control version with multi edp support
137 */
138#define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
139
140/**
141 * Physical framebuffer address location, 64-bit.
142 */
143#ifndef PHYSICAL_ADDRESS_LOC
144#define PHYSICAL_ADDRESS_LOC union large_integer
145#endif
146
147/**
148 * OS/FW agnostic memcpy
149 */
150#ifndef dmub_memcpy
151#define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
152#endif
153
154/**
155 * OS/FW agnostic memset
156 */
157#ifndef dmub_memset
158#define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
159#endif
160
161#if defined(__cplusplus)
162extern "C" {
163#endif
164
165/**
166 * OS/FW agnostic udelay
167 */
168#ifndef dmub_udelay
169#define dmub_udelay(microseconds) udelay(microseconds)
170#endif
171
172#pragma pack(push, 1)
173#define ABM_NUM_OF_ACE_SEGMENTS 5
174
175union abm_flags {
176 struct {
177 /**
178 * @abm_enabled: Indicates if ABM is enabled.
179 */
180 unsigned int abm_enabled : 1;
181
182 /**
183 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
184 */
185 unsigned int disable_abm_requested : 1;
186
187 /**
188 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.
189 */
190 unsigned int disable_abm_immediately : 1;
191
192 /**
193 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
194 * to be disabled immediately and keep gain.
195 */
196 unsigned int disable_abm_immediate_keep_gain : 1;
197
198 /**
199 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
200 */
201 unsigned int fractional_pwm : 1;
202
203 /**
204 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
205 * of user backlight level.
206 */
207 unsigned int abm_gradual_bl_change : 1;
208 } bitfields;
209
210 unsigned int u32All;
211};
212
213struct abm_save_restore {
214 /**
215 * @flags: Misc. ABM flags.
216 */
217 union abm_flags flags;
218
219 /**
220 * @pause: true: pause ABM and get state
221 * false: unpause ABM after setting state
222 */
223 uint32_t pause;
224
225 /**
226 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
227 */
228 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
229
230 /**
231 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
232 */
233 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
234
235 /**
236 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
237 */
238 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
239
240
241 /**
242 * @knee_threshold: Current x-position of ACE knee (u0.16).
243 */
244 uint32_t knee_threshold;
245 /**
246 * @current_gain: Current backlight reduction (u16.16).
247 */
248 uint32_t current_gain;
249 /**
250 * @curr_bl_level: Current actual backlight level converging to target backlight level.
251 */
252 uint16_t curr_bl_level;
253
254 /**
255 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
256 */
257 uint16_t curr_user_bl_level;
258
259};
260
261/**
262 * union dmub_addr - DMUB physical/virtual 64-bit address.
263 */
264union dmub_addr {
265 struct {
266 uint32_t low_part; /**< Lower 32 bits */
267 uint32_t high_part; /**< Upper 32 bits */
268 } u; /*<< Low/high bit access */
269 uint64_t quad_part; /*<< 64 bit address */
270};
271#pragma pack(pop)
272
273/**
274 * Dirty rect definition.
275 */
276struct dmub_rect {
277 /**
278 * Dirty rect x offset.
279 */
280 uint32_t x;
281
282 /**
283 * Dirty rect y offset.
284 */
285 uint32_t y;
286
287 /**
288 * Dirty rect width.
289 */
290 uint32_t width;
291
292 /**
293 * Dirty rect height.
294 */
295 uint32_t height;
296};
297
298/**
299 * Flags that can be set by driver to change some PSR behaviour.
300 */
301union dmub_psr_debug_flags {
302 /**
303 * Debug flags.
304 */
305 struct {
306 /**
307 * Enable visual confirm in FW.
308 */
309 uint32_t visual_confirm : 1;
310
311 /**
312 * Force all selective updates to bw full frame updates.
313 */
314 uint32_t force_full_frame_update : 1;
315
316 /**
317 * Use HW Lock Mgr object to do HW locking in FW.
318 */
319 uint32_t use_hw_lock_mgr : 1;
320
321 /**
322 * Use TPS3 signal when restore main link.
323 */
324 uint32_t force_wakeup_by_tps3 : 1;
325
326 /**
327 * Back to back flip, therefore cannot power down PHY
328 */
329 uint32_t back_to_back_flip : 1;
330
331 } bitfields;
332
333 /**
334 * Union for debug flags.
335 */
336 uint32_t u32All;
337};
338
339/**
340 * Flags that can be set by driver to change some Replay behaviour.
341 */
342union replay_debug_flags {
343 struct {
344 /**
345 * 0x1 (bit 0)
346 * Enable visual confirm in FW.
347 */
348 uint32_t visual_confirm : 1;
349
350 /**
351 * 0x2 (bit 1)
352 * @skip_crc: Set if need to skip CRC.
353 */
354 uint32_t skip_crc : 1;
355
356 /**
357 * 0x4 (bit 2)
358 * @force_link_power_on: Force disable ALPM control
359 */
360 uint32_t force_link_power_on : 1;
361
362 /**
363 * 0x8 (bit 3)
364 * @force_phy_power_on: Force phy power on
365 */
366 uint32_t force_phy_power_on : 1;
367
368 /**
369 * 0x10 (bit 4)
370 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
371 */
372 uint32_t timing_resync_disabled : 1;
373
374 /**
375 * 0x20 (bit 5)
376 * @skip_crtc_disabled: CRTC disable skipped
377 */
378 uint32_t skip_crtc_disabled : 1;
379
380 /**
381 * 0x40 (bit 6)
382 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
383 */
384 uint32_t force_defer_one_frame_update : 1;
385
386 /**
387 * 0x80 (bit 7)
388 * @disable_delay_alpm_on: Force disable delay alpm on
389 */
390 uint32_t disable_delay_alpm_on : 1;
391
392 /**
393 * 0x100 (bit 8)
394 * @disable_desync_error_check: Force disable desync error check
395 */
396 uint32_t disable_desync_error_check : 1;
397
398 /**
399 * 0x200 (bit 9)
400 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady
401 */
402 uint32_t force_self_update_when_abm_non_steady : 1;
403
404 /**
405 * 0x400 (bit 10)
406 * @force_disable_ips1: Force disable IPS1 state
407 */
408 uint32_t force_disable_ips1 : 1;
409
410 /**
411 * 0x800 (bit 11)
412 * @force_disable_ips2: Force disable IPS2 state
413 */
414 uint32_t force_disable_ips2 : 1;
415
416 uint32_t reserved : 20;
417 } bitfields;
418
419 uint32_t u32All;
420};
421
422union replay_hw_flags {
423 struct {
424 /**
425 * @allow_alpm_fw_standby_mode: To indicate whether the
426 * ALPM FW standby mode is allowed
427 */
428 uint32_t allow_alpm_fw_standby_mode : 1;
429
430 /*
431 * @dsc_enable_status: DSC enable status in driver
432 */
433 uint32_t dsc_enable_status : 1;
434
435 /**
436 * @fec_enable_status: receive fec enable/disable status from driver
437 */
438 uint32_t fec_enable_status : 1;
439
440 /*
441 * @smu_optimizations_en: SMU power optimization.
442 * Only when active display is Replay capable and display enters Replay.
443 * Trigger interrupt to SMU to powerup/down.
444 */
445 uint32_t smu_optimizations_en : 1;
446
447 /**
448 * @phy_power_state: Indicates current phy power state
449 */
450 uint32_t phy_power_state : 1;
451
452 /**
453 * @link_power_state: Indicates current link power state
454 */
455 uint32_t link_power_state : 1;
456 /**
457 * Use TPS3 signal when restore main link.
458 */
459 uint32_t force_wakeup_by_tps3 : 1;
460 } bitfields;
461
462 uint32_t u32All;
463};
464
465/**
466 * DMUB feature capabilities.
467 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
468 */
469struct dmub_feature_caps {
470 /**
471 * Max PSR version supported by FW.
472 */
473 uint8_t psr;
474 uint8_t fw_assisted_mclk_switch;
475 uint8_t reserved[4];
476 uint8_t subvp_psr_support;
477 uint8_t gecc_enable;
478 uint8_t replay_supported;
479 uint8_t replay_reserved[3];
480};
481
482struct dmub_visual_confirm_color {
483 /**
484 * Maximum 10 bits color value
485 */
486 uint16_t color_r_cr;
487 uint16_t color_g_y;
488 uint16_t color_b_cb;
489 uint16_t panel_inst;
490};
491
492#if defined(__cplusplus)
493}
494#endif
495
496//==============================================================================
497//</DMUB_TYPES>=================================================================
498//==============================================================================
499//< DMUB_META>==================================================================
500//==============================================================================
501#pragma pack(push, 1)
502
503/* Magic value for identifying dmub_fw_meta_info */
504#define DMUB_FW_META_MAGIC 0x444D5542
505
506/* Offset from the end of the file to the dmub_fw_meta_info */
507#define DMUB_FW_META_OFFSET 0x24
508
509/**
510 * struct dmub_fw_meta_info - metadata associated with fw binary
511 *
512 * NOTE: This should be considered a stable API. Fields should
513 * not be repurposed or reordered. New fields should be
514 * added instead to extend the structure.
515 *
516 * @magic_value: magic value identifying DMUB firmware meta info
517 * @fw_region_size: size of the firmware state region
518 * @trace_buffer_size: size of the tracebuffer region
519 * @fw_version: the firmware version information
520 * @dal_fw: 1 if the firmware is DAL
521 */
522struct dmub_fw_meta_info {
523 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
524 uint32_t fw_region_size; /**< size of the firmware state region */
525 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
526 uint32_t fw_version; /**< the firmware version information */
527 uint8_t dal_fw; /**< 1 if the firmware is DAL */
528 uint8_t reserved[3]; /**< padding bits */
529};
530
531/**
532 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
533 */
534union dmub_fw_meta {
535 struct dmub_fw_meta_info info; /**< metadata info */
536 uint8_t reserved[64]; /**< padding bits */
537};
538
539#pragma pack(pop)
540
541//==============================================================================
542//< DMUB Trace Buffer>================================================================
543//==============================================================================
544/**
545 * dmub_trace_code_t - firmware trace code, 32-bits
546 */
547typedef uint32_t dmub_trace_code_t;
548
549/**
550 * struct dmcub_trace_buf_entry - Firmware trace entry
551 */
552struct dmcub_trace_buf_entry {
553 dmub_trace_code_t trace_code; /**< trace code for the event */
554 uint32_t tick_count; /**< the tick count at time of trace */
555 uint32_t param0; /**< trace defined parameter 0 */
556 uint32_t param1; /**< trace defined parameter 1 */
557};
558
559//==============================================================================
560//< DMUB_STATUS>================================================================
561//==============================================================================
562
563/**
564 * DMCUB scratch registers can be used to determine firmware status.
565 * Current scratch register usage is as follows:
566 *
567 * SCRATCH0: FW Boot Status register
568 * SCRATCH5: LVTMA Status Register
569 * SCRATCH15: FW Boot Options register
570 */
571
572/**
573 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
574 */
575union dmub_fw_boot_status {
576 struct {
577 uint32_t dal_fw : 1; /**< 1 if DAL FW */
578 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
579 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
580 uint32_t restore_required : 1; /**< 1 if driver should call restore */
581 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
582 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
583 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
584 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
585 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
586 } bits; /**< status bits */
587 uint32_t all; /**< 32-bit access to status bits */
588};
589
590/**
591 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
592 */
593enum dmub_fw_boot_status_bit {
594 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
595 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
596 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
597 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
598 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
599 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
600 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
601 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
602 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
603};
604
605/* Register bit definition for SCRATCH5 */
606union dmub_lvtma_status {
607 struct {
608 uint32_t psp_ok : 1;
609 uint32_t edp_on : 1;
610 uint32_t reserved : 30;
611 } bits;
612 uint32_t all;
613};
614
615enum dmub_lvtma_status_bit {
616 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
617 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
618};
619
620enum dmub_ips_disable_type {
621 DMUB_IPS_ENABLE = 0,
622 DMUB_IPS_DISABLE_ALL = 1,
623 DMUB_IPS_DISABLE_IPS1 = 2,
624 DMUB_IPS_DISABLE_IPS2 = 3,
625 DMUB_IPS_DISABLE_IPS2_Z10 = 4,
626 DMUB_IPS_DISABLE_DYNAMIC = 5,
627};
628
629#define DMUB_IPS1_ALLOW_MASK 0x00000001
630#define DMUB_IPS2_ALLOW_MASK 0x00000002
631#define DMUB_IPS1_COMMIT_MASK 0x00000004
632#define DMUB_IPS2_COMMIT_MASK 0x00000008
633
634/**
635 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
636 */
637union dmub_fw_boot_options {
638 struct {
639 uint32_t pemu_env : 1; /**< 1 if PEMU */
640 uint32_t fpga_env : 1; /**< 1 if FPGA */
641 uint32_t optimized_init : 1; /**< 1 if optimized init */
642 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
643 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
644 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
645 uint32_t z10_disable: 1; /**< 1 to disable z10 */
646 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
647 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
648 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
649 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
650 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
651 uint32_t power_optimization: 1;
652 uint32_t diag_env: 1; /* 1 if diagnostic environment */
653 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
654 uint32_t usb4_cm_version: 1; /**< 1 CM support */
655 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
656 uint32_t reserved0: 1;
657 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
658 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
659 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
660 uint32_t ips_disable: 3; /* options to disable ips support*/
661 uint32_t reserved : 9; /**< reserved */
662 } bits; /**< boot bits */
663 uint32_t all; /**< 32-bit access to bits */
664};
665
666enum dmub_fw_boot_options_bit {
667 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
668 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
669 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
670};
671
672//==============================================================================
673//</DMUB_STATUS>================================================================
674//==============================================================================
675//< DMUB_VBIOS>=================================================================
676//==============================================================================
677
678/*
679 * enum dmub_cmd_vbios_type - VBIOS commands.
680 *
681 * Command IDs should be treated as stable ABI.
682 * Do not reuse or modify IDs.
683 */
684enum dmub_cmd_vbios_type {
685 /**
686 * Configures the DIG encoder.
687 */
688 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
689 /**
690 * Controls the PHY.
691 */
692 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
693 /**
694 * Sets the pixel clock/symbol clock.
695 */
696 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
697 /**
698 * Enables or disables power gating.
699 */
700 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
701 /**
702 * Controls embedded panels.
703 */
704 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
705 /**
706 * Query DP alt status on a transmitter.
707 */
708 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
709 /**
710 * Controls domain power gating
711 */
712 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
713};
714
715//==============================================================================
716//</DMUB_VBIOS>=================================================================
717//==============================================================================
718//< DMUB_GPINT>=================================================================
719//==============================================================================
720
721/**
722 * The shifts and masks below may alternatively be used to format and read
723 * the command register bits.
724 */
725
726#define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
727#define DMUB_GPINT_DATA_PARAM_SHIFT 0
728
729#define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
730#define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
731
732#define DMUB_GPINT_DATA_STATUS_MASK 0xF
733#define DMUB_GPINT_DATA_STATUS_SHIFT 28
734
735/**
736 * Command responses.
737 */
738
739/**
740 * Return response for DMUB_GPINT__STOP_FW command.
741 */
742#define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
743
744/**
745 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
746 */
747union dmub_gpint_data_register {
748 struct {
749 uint32_t param : 16; /**< 16-bit parameter */
750 uint32_t command_code : 12; /**< GPINT command */
751 uint32_t status : 4; /**< Command status bit */
752 } bits; /**< GPINT bit access */
753 uint32_t all; /**< GPINT 32-bit access */
754};
755
756/*
757 * enum dmub_gpint_command - GPINT command to DMCUB FW
758 *
759 * Command IDs should be treated as stable ABI.
760 * Do not reuse or modify IDs.
761 */
762enum dmub_gpint_command {
763 /**
764 * Invalid command, ignored.
765 */
766 DMUB_GPINT__INVALID_COMMAND = 0,
767 /**
768 * DESC: Queries the firmware version.
769 * RETURN: Firmware version.
770 */
771 DMUB_GPINT__GET_FW_VERSION = 1,
772 /**
773 * DESC: Halts the firmware.
774 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
775 */
776 DMUB_GPINT__STOP_FW = 2,
777 /**
778 * DESC: Get PSR state from FW.
779 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
780 */
781 DMUB_GPINT__GET_PSR_STATE = 7,
782 /**
783 * DESC: Notifies DMCUB of the currently active streams.
784 * ARGS: Stream mask, 1 bit per active stream index.
785 */
786 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
787 /**
788 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
789 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
790 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
791 * RETURN: PSR residency in milli-percent.
792 */
793 DMUB_GPINT__PSR_RESIDENCY = 9,
794
795 /**
796 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
797 */
798 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
799
800 /**
801 * DESC: Get REPLAY state from FW.
802 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
803 */
804 DMUB_GPINT__GET_REPLAY_STATE = 13,
805
806 /**
807 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
808 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
809 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
810 * RETURN: REPLAY residency in milli-percent.
811 */
812 DMUB_GPINT__REPLAY_RESIDENCY = 14,
813
814 /**
815 * DESC: Updates the trace buffer lower 32-bit mask.
816 * ARGS: The new mask
817 * RETURN: Lower 32-bit mask.
818 */
819 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
820
821 /**
822 * DESC: Updates the trace buffer mask bit0~bit15.
823 * ARGS: The new mask
824 * RETURN: Lower 32-bit mask.
825 */
826 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
827
828 /**
829 * DESC: Updates the trace buffer mask bit16~bit31.
830 * ARGS: The new mask
831 * RETURN: Lower 32-bit mask.
832 */
833 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
834
835 /**
836 * DESC: Updates the trace buffer mask bit32~bit47.
837 * ARGS: The new mask
838 * RETURN: Lower 32-bit mask.
839 */
840 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,
841
842 /**
843 * DESC: Updates the trace buffer mask bit48~bit63.
844 * ARGS: The new mask
845 * RETURN: Lower 32-bit mask.
846 */
847 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,
848
849 /**
850 * DESC: Read the trace buffer mask bi0~bit15.
851 */
852 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,
853
854 /**
855 * DESC: Read the trace buffer mask bit16~bit31.
856 */
857 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,
858
859 /**
860 * DESC: Read the trace buffer mask bi32~bit47.
861 */
862 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,
863
864 /**
865 * DESC: Updates the trace buffer mask bit32~bit63.
866 */
867 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,
868
869 /**
870 * DESC: Enable measurements for various task duration
871 * ARGS: 0 - Disable measurement
872 * 1 - Enable measurement
873 */
874 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,
875};
876
877/**
878 * INBOX0 generic command definition
879 */
880union dmub_inbox0_cmd_common {
881 struct {
882 uint32_t command_code: 8; /**< INBOX0 command code */
883 uint32_t param: 24; /**< 24-bit parameter */
884 } bits;
885 uint32_t all;
886};
887
888/**
889 * INBOX0 hw_lock command definition
890 */
891union dmub_inbox0_cmd_lock_hw {
892 struct {
893 uint32_t command_code: 8;
894
895 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
896 uint32_t hw_lock_client: 2;
897
898 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
899 uint32_t otg_inst: 3;
900 uint32_t opp_inst: 3;
901 uint32_t dig_inst: 3;
902
903 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
904 uint32_t lock_pipe: 1;
905 uint32_t lock_cursor: 1;
906 uint32_t lock_dig: 1;
907 uint32_t triple_buffer_lock: 1;
908
909 uint32_t lock: 1; /**< Lock */
910 uint32_t should_release: 1; /**< Release */
911 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
912 } bits;
913 uint32_t all;
914};
915
916union dmub_inbox0_data_register {
917 union dmub_inbox0_cmd_common inbox0_cmd_common;
918 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
919};
920
921enum dmub_inbox0_command {
922 /**
923 * DESC: Invalid command, ignored.
924 */
925 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
926 /**
927 * DESC: Notification to acquire/release HW lock
928 * ARGS:
929 */
930 DMUB_INBOX0_CMD__HW_LOCK = 1,
931};
932//==============================================================================
933//</DMUB_GPINT>=================================================================
934//==============================================================================
935//< DMUB_CMD>===================================================================
936//==============================================================================
937
938/**
939 * Size in bytes of each DMUB command.
940 */
941#define DMUB_RB_CMD_SIZE 64
942
943/**
944 * Maximum number of items in the DMUB ringbuffer.
945 */
946#define DMUB_RB_MAX_ENTRY 128
947
948/**
949 * Ringbuffer size in bytes.
950 */
951#define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
952
953/**
954 * REG_SET mask for reg offload.
955 */
956#define REG_SET_MASK 0xFFFF
957
958/*
959 * enum dmub_cmd_type - DMUB inbox command.
960 *
961 * Command IDs should be treated as stable ABI.
962 * Do not reuse or modify IDs.
963 */
964enum dmub_cmd_type {
965 /**
966 * Invalid command.
967 */
968 DMUB_CMD__NULL = 0,
969 /**
970 * Read modify write register sequence offload.
971 */
972 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
973 /**
974 * Field update register sequence offload.
975 */
976 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
977 /**
978 * Burst write sequence offload.
979 */
980 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
981 /**
982 * Reg wait sequence offload.
983 */
984 DMUB_CMD__REG_REG_WAIT = 4,
985 /**
986 * Workaround to avoid HUBP underflow during NV12 playback.
987 */
988 DMUB_CMD__PLAT_54186_WA = 5,
989 /**
990 * Command type used to query FW feature caps.
991 */
992 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
993 /**
994 * Command type used to get visual confirm color.
995 */
996 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
997 /**
998 * Command type used for all PSR commands.
999 */
1000 DMUB_CMD__PSR = 64,
1001 /**
1002 * Command type used for all MALL commands.
1003 */
1004 DMUB_CMD__MALL = 65,
1005 /**
1006 * Command type used for all ABM commands.
1007 */
1008 DMUB_CMD__ABM = 66,
1009 /**
1010 * Command type used to update dirty rects in FW.
1011 */
1012 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
1013 /**
1014 * Command type used to update cursor info in FW.
1015 */
1016 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
1017 /**
1018 * Command type used for HW locking in FW.
1019 */
1020 DMUB_CMD__HW_LOCK = 69,
1021 /**
1022 * Command type used to access DP AUX.
1023 */
1024 DMUB_CMD__DP_AUX_ACCESS = 70,
1025 /**
1026 * Command type used for OUTBOX1 notification enable
1027 */
1028 DMUB_CMD__OUTBOX1_ENABLE = 71,
1029
1030 /**
1031 * Command type used for all idle optimization commands.
1032 */
1033 DMUB_CMD__IDLE_OPT = 72,
1034 /**
1035 * Command type used for all clock manager commands.
1036 */
1037 DMUB_CMD__CLK_MGR = 73,
1038 /**
1039 * Command type used for all panel control commands.
1040 */
1041 DMUB_CMD__PANEL_CNTL = 74,
1042
1043 /**
1044 * Command type used for all CAB commands.
1045 */
1046 DMUB_CMD__CAB_FOR_SS = 75,
1047
1048 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
1049
1050 /**
1051 * Command type used for interfacing with DPIA.
1052 */
1053 DMUB_CMD__DPIA = 77,
1054 /**
1055 * Command type used for EDID CEA parsing
1056 */
1057 DMUB_CMD__EDID_CEA = 79,
1058 /**
1059 * Command type used for getting usbc cable ID
1060 */
1061 DMUB_CMD_GET_USBC_CABLE_ID = 81,
1062 /**
1063 * Command type used to query HPD state.
1064 */
1065 DMUB_CMD__QUERY_HPD_STATE = 82,
1066 /**
1067 * Command type used for all VBIOS interface commands.
1068 */
1069 /**
1070 * Command type used for all REPLAY commands.
1071 */
1072 DMUB_CMD__REPLAY = 83,
1073
1074 /**
1075 * Command type used for all SECURE_DISPLAY commands.
1076 */
1077 DMUB_CMD__SECURE_DISPLAY = 85,
1078
1079 /**
1080 * Command type used to set DPIA HPD interrupt state
1081 */
1082 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1083
1084 DMUB_CMD__VBIOS = 128,
1085};
1086
1087/**
1088 * enum dmub_out_cmd_type - DMUB outbox commands.
1089 */
1090enum dmub_out_cmd_type {
1091 /**
1092 * Invalid outbox command, ignored.
1093 */
1094 DMUB_OUT_CMD__NULL = 0,
1095 /**
1096 * Command type used for DP AUX Reply data notification
1097 */
1098 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1099 /**
1100 * Command type used for DP HPD event notification
1101 */
1102 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1103 /**
1104 * Command type used for SET_CONFIG Reply notification
1105 */
1106 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1107 /**
1108 * Command type used for USB4 DPIA notification
1109 */
1110 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1111};
1112
1113/* DMUB_CMD__DPIA command sub-types. */
1114enum dmub_cmd_dpia_type {
1115 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1116 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
1117 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1118};
1119
1120/* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1121enum dmub_cmd_dpia_notification_type {
1122 DPIA_NOTIFY__BW_ALLOCATION = 0,
1123};
1124
1125#pragma pack(push, 1)
1126
1127/**
1128 * struct dmub_cmd_header - Common command header fields.
1129 */
1130struct dmub_cmd_header {
1131 unsigned int type : 8; /**< command type */
1132 unsigned int sub_type : 8; /**< command sub type */
1133 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1134 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1135 unsigned int reserved0 : 6; /**< reserved bits */
1136 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1137 unsigned int reserved1 : 2; /**< reserved bits */
1138};
1139
1140/*
1141 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1142 *
1143 * 60 payload bytes can hold up to 5 sets of read modify writes,
1144 * each take 3 dwords.
1145 *
1146 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1147 *
1148 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1149 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1150 */
1151struct dmub_cmd_read_modify_write_sequence {
1152 uint32_t addr; /**< register address */
1153 uint32_t modify_mask; /**< modify mask */
1154 uint32_t modify_value; /**< modify value */
1155};
1156
1157/**
1158 * Maximum number of ops in read modify write sequence.
1159 */
1160#define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1161
1162/**
1163 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1164 */
1165struct dmub_rb_cmd_read_modify_write {
1166 struct dmub_cmd_header header; /**< command header */
1167 /**
1168 * Read modify write sequence.
1169 */
1170 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
1171};
1172
1173/*
1174 * Update a register with specified masks and values sequeunce
1175 *
1176 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
1177 *
1178 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
1179 *
1180 *
1181 * USE CASE:
1182 * 1. auto-increment register where additional read would update pointer and produce wrong result
1183 * 2. toggle a bit without read in the middle
1184 */
1185
1186struct dmub_cmd_reg_field_update_sequence {
1187 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1188 uint32_t modify_value; /**< value to update with */
1189};
1190
1191/**
1192 * Maximum number of ops in field update sequence.
1193 */
1194#define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1195
1196/**
1197 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1198 */
1199struct dmub_rb_cmd_reg_field_update_sequence {
1200 struct dmub_cmd_header header; /**< command header */
1201 uint32_t addr; /**< register address */
1202 /**
1203 * Field update sequence.
1204 */
1205 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
1206};
1207
1208
1209/**
1210 * Maximum number of burst write values.
1211 */
1212#define DMUB_BURST_WRITE_VALUES__MAX 14
1213
1214/*
1215 * struct dmub_rb_cmd_burst_write - Burst write
1216 *
1217 * support use case such as writing out LUTs.
1218 *
1219 * 60 payload bytes can hold up to 14 values to write to given address
1220 *
1221 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
1222 */
1223struct dmub_rb_cmd_burst_write {
1224 struct dmub_cmd_header header; /**< command header */
1225 uint32_t addr; /**< register start address */
1226 /**
1227 * Burst write register values.
1228 */
1229 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
1230};
1231
1232/**
1233 * struct dmub_rb_cmd_common - Common command header
1234 */
1235struct dmub_rb_cmd_common {
1236 struct dmub_cmd_header header; /**< command header */
1237 /**
1238 * Padding to RB_CMD_SIZE
1239 */
1240 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1241};
1242
1243/**
1244 * struct dmub_cmd_reg_wait_data - Register wait data
1245 */
1246struct dmub_cmd_reg_wait_data {
1247 uint32_t addr; /**< Register address */
1248 uint32_t mask; /**< Mask for register bits */
1249 uint32_t condition_field_value; /**< Value to wait for */
1250 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
1251};
1252
1253/**
1254 * struct dmub_rb_cmd_reg_wait - Register wait command
1255 */
1256struct dmub_rb_cmd_reg_wait {
1257 struct dmub_cmd_header header; /**< Command header */
1258 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
1259};
1260
1261/**
1262 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1263 *
1264 * Reprograms surface parameters to avoid underflow.
1265 */
1266struct dmub_cmd_PLAT_54186_wa {
1267 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1268 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1269 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1270 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1271 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
1272 struct {
1273 uint8_t hubp_inst : 4; /**< HUBP instance */
1274 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
1275 uint8_t immediate :1; /**< Immediate flip */
1276 uint8_t vmid : 4; /**< VMID */
1277 uint8_t grph_stereo : 1; /**< 1 if stereo */
1278 uint32_t reserved : 21; /**< Reserved */
1279 } flip_params; /**< Pageflip parameters */
1280 uint32_t reserved[9]; /**< Reserved bits */
1281};
1282
1283/**
1284 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1285 */
1286struct dmub_rb_cmd_PLAT_54186_wa {
1287 struct dmub_cmd_header header; /**< Command header */
1288 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
1289};
1290
1291/**
1292 * enum dmub_cmd_mall_type - MALL commands
1293 */
1294enum dmub_cmd_mall_type {
1295 /**
1296 * Allows display refresh from MALL.
1297 */
1298 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1299 /**
1300 * Disallows display refresh from MALL.
1301 */
1302 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1303 /**
1304 * Cursor copy for MALL.
1305 */
1306 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1307 /**
1308 * Controls DF requests.
1309 */
1310 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1311};
1312
1313/**
1314 * struct dmub_rb_cmd_mall - MALL command data.
1315 */
1316struct dmub_rb_cmd_mall {
1317 struct dmub_cmd_header header; /**< Common command header */
1318 union dmub_addr cursor_copy_src; /**< Cursor copy address */
1319 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1320 uint32_t tmr_delay; /**< Timer delay */
1321 uint32_t tmr_scale; /**< Timer scale */
1322 uint16_t cursor_width; /**< Cursor width in pixels */
1323 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1324 uint16_t cursor_height; /**< Cursor height in pixels */
1325 uint8_t cursor_bpp; /**< Cursor bits per pixel */
1326 uint8_t debug_bits; /**< Debug bits */
1327
1328 uint8_t reserved1; /**< Reserved bits */
1329 uint8_t reserved2; /**< Reserved bits */
1330};
1331
1332/**
1333 * enum dmub_cmd_cab_type - CAB command data.
1334 */
1335enum dmub_cmd_cab_type {
1336 /**
1337 * No idle optimizations (i.e. no CAB)
1338 */
1339 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1340 /**
1341 * No DCN requests for memory
1342 */
1343 DMUB_CMD__CAB_NO_DCN_REQ = 1,
1344 /**
1345 * Fit surfaces in CAB (i.e. CAB enable)
1346 */
1347 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1348 /**
1349 * Do not fit surfaces in CAB (i.e. no CAB)
1350 */
1351 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,
1352};
1353
1354/**
1355 * struct dmub_rb_cmd_cab - CAB command data.
1356 */
1357struct dmub_rb_cmd_cab_for_ss {
1358 struct dmub_cmd_header header;
1359 uint8_t cab_alloc_ways; /* total number of ways */
1360 uint8_t debug_bits; /* debug bits */
1361};
1362
1363/**
1364 * Enum for indicating which MCLK switch mode per pipe
1365 */
1366enum mclk_switch_mode {
1367 NONE = 0,
1368 FPO = 1,
1369 SUBVP = 2,
1370 VBLANK = 3,
1371};
1372
1373/* Per pipe struct which stores the MCLK switch mode
1374 * data to be sent to DMUB.
1375 * Named "v2" for now -- once FPO and SUBVP are fully merged
1376 * the type name can be updated
1377 */
1378struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
1379 union {
1380 struct {
1381 uint32_t pix_clk_100hz;
1382 uint16_t main_vblank_start;
1383 uint16_t main_vblank_end;
1384 uint16_t mall_region_lines;
1385 uint16_t prefetch_lines;
1386 uint16_t prefetch_to_mall_start_lines;
1387 uint16_t processing_delay_lines;
1388 uint16_t htotal; // required to calculate line time for multi-display cases
1389 uint16_t vtotal;
1390 uint8_t main_pipe_index;
1391 uint8_t phantom_pipe_index;
1392 /* Since the microschedule is calculated in terms of OTG lines,
1393 * include any scaling factors to make sure when we get accurate
1394 * conversion when programming MALL_START_LINE (which is in terms
1395 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1396 * is 1/2 (numerator = 1, denominator = 2).
1397 */
1398 uint8_t scale_factor_numerator;
1399 uint8_t scale_factor_denominator;
1400 uint8_t is_drr;
1401 uint8_t main_split_pipe_index;
1402 uint8_t phantom_split_pipe_index;
1403 } subvp_data;
1404
1405 struct {
1406 uint32_t pix_clk_100hz;
1407 uint16_t vblank_start;
1408 uint16_t vblank_end;
1409 uint16_t vstartup_start;
1410 uint16_t vtotal;
1411 uint16_t htotal;
1412 uint8_t vblank_pipe_index;
1413 uint8_t padding[1];
1414 struct {
1415 uint8_t drr_in_use;
1416 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1417 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1418 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1419 uint8_t use_ramping; // Use ramping or not
1420 uint8_t drr_vblank_start_margin;
1421 } drr_info; // DRR considered as part of SubVP + VBLANK case
1422 } vblank_data;
1423 } pipe_config;
1424
1425 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1426 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1427 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1428 */
1429 uint8_t mode; // enum mclk_switch_mode
1430};
1431
1432/**
1433 * Config data for Sub-VP and FPO
1434 * Named "v2" for now -- once FPO and SUBVP are fully merged
1435 * the type name can be updated
1436 */
1437struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1438 uint16_t watermark_a_cache;
1439 uint8_t vertical_int_margin_us;
1440 uint8_t pstate_allow_width_us;
1441 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1442};
1443
1444/**
1445 * DMUB rb command definition for Sub-VP and FPO
1446 * Named "v2" for now -- once FPO and SUBVP are fully merged
1447 * the type name can be updated
1448 */
1449struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1450 struct dmub_cmd_header header;
1451 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1452};
1453
1454/**
1455 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1456 */
1457enum dmub_cmd_idle_opt_type {
1458 /**
1459 * DCN hardware restore.
1460 */
1461 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1462
1463 /**
1464 * DCN hardware save.
1465 */
1466 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
1467
1468 /**
1469 * DCN hardware notify idle.
1470 */
1471 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2
1472};
1473
1474/**
1475 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1476 */
1477struct dmub_rb_cmd_idle_opt_dcn_restore {
1478 struct dmub_cmd_header header; /**< header */
1479};
1480
1481/**
1482 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1483 */
1484struct dmub_dcn_notify_idle_cntl_data {
1485 uint8_t driver_idle;
1486 uint8_t pad[1];
1487};
1488
1489/**
1490 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1491 */
1492struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
1493 struct dmub_cmd_header header; /**< header */
1494 struct dmub_dcn_notify_idle_cntl_data cntl_data;
1495};
1496
1497/**
1498 * struct dmub_clocks - Clock update notification.
1499 */
1500struct dmub_clocks {
1501 uint32_t dispclk_khz; /**< dispclk kHz */
1502 uint32_t dppclk_khz; /**< dppclk kHz */
1503 uint32_t dcfclk_khz; /**< dcfclk kHz */
1504 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1505};
1506
1507/**
1508 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1509 */
1510enum dmub_cmd_clk_mgr_type {
1511 /**
1512 * Notify DMCUB of clock update.
1513 */
1514 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1515};
1516
1517/**
1518 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1519 */
1520struct dmub_rb_cmd_clk_mgr_notify_clocks {
1521 struct dmub_cmd_header header; /**< header */
1522 struct dmub_clocks clocks; /**< clock data */
1523};
1524
1525/**
1526 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1527 */
1528struct dmub_cmd_digx_encoder_control_data {
1529 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1530};
1531
1532/**
1533 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1534 */
1535struct dmub_rb_cmd_digx_encoder_control {
1536 struct dmub_cmd_header header; /**< header */
1537 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1538};
1539
1540/**
1541 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1542 */
1543struct dmub_cmd_set_pixel_clock_data {
1544 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1545};
1546
1547/**
1548 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1549 */
1550struct dmub_rb_cmd_set_pixel_clock {
1551 struct dmub_cmd_header header; /**< header */
1552 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
1553};
1554
1555/**
1556 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
1557 */
1558struct dmub_cmd_enable_disp_power_gating_data {
1559 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
1560};
1561
1562/**
1563 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
1564 */
1565struct dmub_rb_cmd_enable_disp_power_gating {
1566 struct dmub_cmd_header header; /**< header */
1567 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
1568};
1569
1570/**
1571 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
1572 */
1573struct dmub_dig_transmitter_control_data_v1_7 {
1574 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
1575 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
1576 union {
1577 uint8_t digmode; /**< enum atom_encode_mode_def */
1578 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
1579 } mode_laneset;
1580 uint8_t lanenum; /**< Number of lanes */
1581 union {
1582 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
1583 } symclk_units;
1584 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
1585 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
1586 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
1587 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
1588 uint8_t reserved1; /**< For future use */
1589 uint8_t reserved2[3]; /**< For future use */
1590 uint32_t reserved3[11]; /**< For future use */
1591};
1592
1593/**
1594 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
1595 */
1596union dmub_cmd_dig1_transmitter_control_data {
1597 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
1598 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
1599};
1600
1601/**
1602 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
1603 */
1604struct dmub_rb_cmd_dig1_transmitter_control {
1605 struct dmub_cmd_header header; /**< header */
1606 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
1607};
1608
1609/**
1610 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
1611 */
1612struct dmub_rb_cmd_domain_control_data {
1613 uint8_t inst : 6; /**< DOMAIN instance to control */
1614 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
1615 uint8_t reserved[3]; /**< Reserved for future use */
1616};
1617
1618/**
1619 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
1620 */
1621struct dmub_rb_cmd_domain_control {
1622 struct dmub_cmd_header header; /**< header */
1623 struct dmub_rb_cmd_domain_control_data data; /**< payload */
1624};
1625
1626/**
1627 * DPIA tunnel command parameters.
1628 */
1629struct dmub_cmd_dig_dpia_control_data {
1630 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
1631 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
1632 union {
1633 uint8_t digmode; /** enum atom_encode_mode_def */
1634 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
1635 } mode_laneset;
1636 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
1637 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
1638 uint8_t hpdsel; /** =0: HPD is not assigned */
1639 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
1640 uint8_t dpia_id; /** Index of DPIA */
1641 uint8_t fec_rdy : 1;
1642 uint8_t reserved : 7;
1643 uint32_t reserved1;
1644};
1645
1646/**
1647 * DMUB command for DPIA tunnel control.
1648 */
1649struct dmub_rb_cmd_dig1_dpia_control {
1650 struct dmub_cmd_header header;
1651 struct dmub_cmd_dig_dpia_control_data dpia_control;
1652};
1653
1654/**
1655 * SET_CONFIG Command Payload
1656 */
1657struct set_config_cmd_payload {
1658 uint8_t msg_type; /* set config message type */
1659 uint8_t msg_data; /* set config message data */
1660};
1661
1662/**
1663 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
1664 */
1665struct dmub_cmd_set_config_control_data {
1666 struct set_config_cmd_payload cmd_pkt;
1667 uint8_t instance; /* DPIA instance */
1668 uint8_t immed_status; /* Immediate status returned in case of error */
1669};
1670
1671/**
1672 * DMUB command structure for SET_CONFIG command.
1673 */
1674struct dmub_rb_cmd_set_config_access {
1675 struct dmub_cmd_header header; /* header */
1676 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
1677};
1678
1679/**
1680 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
1681 */
1682struct dmub_cmd_mst_alloc_slots_control_data {
1683 uint8_t mst_alloc_slots; /* mst slots to be allotted */
1684 uint8_t instance; /* DPIA instance */
1685 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
1686 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
1687};
1688
1689/**
1690 * DMUB command structure for SET_ command.
1691 */
1692struct dmub_rb_cmd_set_mst_alloc_slots {
1693 struct dmub_cmd_header header; /* header */
1694 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
1695};
1696
1697/**
1698 * DMUB command structure for DPIA HPD int enable control.
1699 */
1700struct dmub_rb_cmd_dpia_hpd_int_enable {
1701 struct dmub_cmd_header header; /* header */
1702 uint32_t enable; /* dpia hpd interrupt enable */
1703};
1704
1705/**
1706 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1707 */
1708struct dmub_rb_cmd_dpphy_init {
1709 struct dmub_cmd_header header; /**< header */
1710 uint8_t reserved[60]; /**< reserved bits */
1711};
1712
1713/**
1714 * enum dp_aux_request_action - DP AUX request command listing.
1715 *
1716 * 4 AUX request command bits are shifted to high nibble.
1717 */
1718enum dp_aux_request_action {
1719 /** I2C-over-AUX write request */
1720 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
1721 /** I2C-over-AUX read request */
1722 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
1723 /** I2C-over-AUX write status request */
1724 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
1725 /** I2C-over-AUX write request with MOT=1 */
1726 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
1727 /** I2C-over-AUX read request with MOT=1 */
1728 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
1729 /** I2C-over-AUX write status request with MOT=1 */
1730 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
1731 /** Native AUX write request */
1732 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
1733 /** Native AUX read request */
1734 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1735};
1736
1737/**
1738 * enum aux_return_code_type - DP AUX process return code listing.
1739 */
1740enum aux_return_code_type {
1741 /** AUX process succeeded */
1742 AUX_RET_SUCCESS = 0,
1743 /** AUX process failed with unknown reason */
1744 AUX_RET_ERROR_UNKNOWN,
1745 /** AUX process completed with invalid reply */
1746 AUX_RET_ERROR_INVALID_REPLY,
1747 /** AUX process timed out */
1748 AUX_RET_ERROR_TIMEOUT,
1749 /** HPD was low during AUX process */
1750 AUX_RET_ERROR_HPD_DISCON,
1751 /** Failed to acquire AUX engine */
1752 AUX_RET_ERROR_ENGINE_ACQUIRE,
1753 /** AUX request not supported */
1754 AUX_RET_ERROR_INVALID_OPERATION,
1755 /** AUX process not available */
1756 AUX_RET_ERROR_PROTOCOL_ERROR,
1757};
1758
1759/**
1760 * enum aux_channel_type - DP AUX channel type listing.
1761 */
1762enum aux_channel_type {
1763 /** AUX thru Legacy DP AUX */
1764 AUX_CHANNEL_LEGACY_DDC,
1765 /** AUX thru DPIA DP tunneling */
1766 AUX_CHANNEL_DPIA
1767};
1768
1769/**
1770 * struct aux_transaction_parameters - DP AUX request transaction data
1771 */
1772struct aux_transaction_parameters {
1773 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1774 uint8_t action; /**< enum dp_aux_request_action */
1775 uint8_t length; /**< DP AUX request data length */
1776 uint8_t reserved; /**< For future use */
1777 uint32_t address; /**< DP AUX address */
1778 uint8_t data[16]; /**< DP AUX write data */
1779};
1780
1781/**
1782 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1783 */
1784struct dmub_cmd_dp_aux_control_data {
1785 uint8_t instance; /**< AUX instance or DPIA instance */
1786 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1787 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1788 uint8_t reserved0; /**< For future use */
1789 uint16_t timeout; /**< timeout time in us */
1790 uint16_t reserved1; /**< For future use */
1791 enum aux_channel_type type; /**< enum aux_channel_type */
1792 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1793};
1794
1795/**
1796 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1797 */
1798struct dmub_rb_cmd_dp_aux_access {
1799 /**
1800 * Command header.
1801 */
1802 struct dmub_cmd_header header;
1803 /**
1804 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1805 */
1806 struct dmub_cmd_dp_aux_control_data aux_control;
1807};
1808
1809/**
1810 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1811 */
1812struct dmub_rb_cmd_outbox1_enable {
1813 /**
1814 * Command header.
1815 */
1816 struct dmub_cmd_header header;
1817 /**
1818 * enable: 0x0 -> disable outbox1 notification (default value)
1819 * 0x1 -> enable outbox1 notification
1820 */
1821 uint32_t enable;
1822};
1823
1824/* DP AUX Reply command - OutBox Cmd */
1825/**
1826 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1827 */
1828struct aux_reply_data {
1829 /**
1830 * Aux cmd
1831 */
1832 uint8_t command;
1833 /**
1834 * Aux reply data length (max: 16 bytes)
1835 */
1836 uint8_t length;
1837 /**
1838 * Alignment only
1839 */
1840 uint8_t pad[2];
1841 /**
1842 * Aux reply data
1843 */
1844 uint8_t data[16];
1845};
1846
1847/**
1848 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1849 */
1850struct aux_reply_control_data {
1851 /**
1852 * Reserved for future use
1853 */
1854 uint32_t handle;
1855 /**
1856 * Aux Instance
1857 */
1858 uint8_t instance;
1859 /**
1860 * Aux transaction result: definition in enum aux_return_code_type
1861 */
1862 uint8_t result;
1863 /**
1864 * Alignment only
1865 */
1866 uint16_t pad;
1867};
1868
1869/**
1870 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1871 */
1872struct dmub_rb_cmd_dp_aux_reply {
1873 /**
1874 * Command header.
1875 */
1876 struct dmub_cmd_header header;
1877 /**
1878 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1879 */
1880 struct aux_reply_control_data control;
1881 /**
1882 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1883 */
1884 struct aux_reply_data reply_data;
1885};
1886
1887/* DP HPD Notify command - OutBox Cmd */
1888/**
1889 * DP HPD Type
1890 */
1891enum dp_hpd_type {
1892 /**
1893 * Normal DP HPD
1894 */
1895 DP_HPD = 0,
1896 /**
1897 * DP HPD short pulse
1898 */
1899 DP_IRQ
1900};
1901
1902/**
1903 * DP HPD Status
1904 */
1905enum dp_hpd_status {
1906 /**
1907 * DP_HPD status low
1908 */
1909 DP_HPD_UNPLUG = 0,
1910 /**
1911 * DP_HPD status high
1912 */
1913 DP_HPD_PLUG
1914};
1915
1916/**
1917 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1918 */
1919struct dp_hpd_data {
1920 /**
1921 * DP HPD instance
1922 */
1923 uint8_t instance;
1924 /**
1925 * HPD type
1926 */
1927 uint8_t hpd_type;
1928 /**
1929 * HPD status: only for type: DP_HPD to indicate status
1930 */
1931 uint8_t hpd_status;
1932 /**
1933 * Alignment only
1934 */
1935 uint8_t pad;
1936};
1937
1938/**
1939 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1940 */
1941struct dmub_rb_cmd_dp_hpd_notify {
1942 /**
1943 * Command header.
1944 */
1945 struct dmub_cmd_header header;
1946 /**
1947 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1948 */
1949 struct dp_hpd_data hpd_data;
1950};
1951
1952/**
1953 * Definition of a SET_CONFIG reply from DPOA.
1954 */
1955enum set_config_status {
1956 SET_CONFIG_PENDING = 0,
1957 SET_CONFIG_ACK_RECEIVED,
1958 SET_CONFIG_RX_TIMEOUT,
1959 SET_CONFIG_UNKNOWN_ERROR,
1960};
1961
1962/**
1963 * Definition of a set_config reply
1964 */
1965struct set_config_reply_control_data {
1966 uint8_t instance; /* DPIA Instance */
1967 uint8_t status; /* Set Config reply */
1968 uint16_t pad; /* Alignment */
1969};
1970
1971/**
1972 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
1973 */
1974struct dmub_rb_cmd_dp_set_config_reply {
1975 struct dmub_cmd_header header;
1976 struct set_config_reply_control_data set_config_reply_control;
1977};
1978
1979/**
1980 * Definition of a DPIA notification header
1981 */
1982struct dpia_notification_header {
1983 uint8_t instance; /**< DPIA Instance */
1984 uint8_t reserved[3];
1985 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
1986};
1987
1988/**
1989 * Definition of the common data struct of DPIA notification
1990 */
1991struct dpia_notification_common {
1992 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
1993 - sizeof(struct dpia_notification_header)];
1994};
1995
1996/**
1997 * Definition of a DPIA notification data
1998 */
1999struct dpia_bw_allocation_notify_data {
2000 union {
2001 struct {
2002 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
2003 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
2004 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
2005 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
2006 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
2007 uint16_t reserved: 11; /**< Reserved */
2008 } bits;
2009
2010 uint16_t flags;
2011 };
2012
2013 uint8_t cm_id; /**< CM ID */
2014 uint8_t group_id; /**< Group ID */
2015 uint8_t granularity; /**< BW Allocation Granularity */
2016 uint8_t estimated_bw; /**< Estimated_BW */
2017 uint8_t allocated_bw; /**< Allocated_BW */
2018 uint8_t reserved;
2019};
2020
2021/**
2022 * union dpia_notify_data_type - DPIA Notification in Outbox command
2023 */
2024union dpia_notification_data {
2025 /**
2026 * DPIA Notification for common data struct
2027 */
2028 struct dpia_notification_common common_data;
2029
2030 /**
2031 * DPIA Notification for DP BW Allocation support
2032 */
2033 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
2034};
2035
2036/**
2037 * Definition of a DPIA notification payload
2038 */
2039struct dpia_notification_payload {
2040 struct dpia_notification_header header;
2041 union dpia_notification_data data; /**< DPIA notification payload data */
2042};
2043
2044/**
2045 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
2046 */
2047struct dmub_rb_cmd_dpia_notification {
2048 struct dmub_cmd_header header; /**< DPIA notification header */
2049 struct dpia_notification_payload payload; /**< DPIA notification payload */
2050};
2051
2052/**
2053 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2054 */
2055struct dmub_cmd_hpd_state_query_data {
2056 uint8_t instance; /**< HPD instance or DPIA instance */
2057 uint8_t result; /**< For returning HPD state */
2058 uint16_t pad; /** < Alignment */
2059 enum aux_channel_type ch_type; /**< enum aux_channel_type */
2060 enum aux_return_code_type status; /**< for returning the status of command */
2061};
2062
2063/**
2064 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
2065 */
2066struct dmub_rb_cmd_query_hpd_state {
2067 /**
2068 * Command header.
2069 */
2070 struct dmub_cmd_header header;
2071 /**
2072 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2073 */
2074 struct dmub_cmd_hpd_state_query_data data;
2075};
2076
2077/*
2078 * Command IDs should be treated as stable ABI.
2079 * Do not reuse or modify IDs.
2080 */
2081
2082/**
2083 * PSR command sub-types.
2084 */
2085enum dmub_cmd_psr_type {
2086 /**
2087 * Set PSR version support.
2088 */
2089 DMUB_CMD__PSR_SET_VERSION = 0,
2090 /**
2091 * Copy driver-calculated parameters to PSR state.
2092 */
2093 DMUB_CMD__PSR_COPY_SETTINGS = 1,
2094 /**
2095 * Enable PSR.
2096 */
2097 DMUB_CMD__PSR_ENABLE = 2,
2098
2099 /**
2100 * Disable PSR.
2101 */
2102 DMUB_CMD__PSR_DISABLE = 3,
2103
2104 /**
2105 * Set PSR level.
2106 * PSR level is a 16-bit value dicated by driver that
2107 * will enable/disable different functionality.
2108 */
2109 DMUB_CMD__PSR_SET_LEVEL = 4,
2110
2111 /**
2112 * Forces PSR enabled until an explicit PSR disable call.
2113 */
2114 DMUB_CMD__PSR_FORCE_STATIC = 5,
2115 /**
2116 * Set vtotal in psr active for FreeSync PSR.
2117 */
2118 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
2119 /**
2120 * Set PSR power option
2121 */
2122 DMUB_CMD__SET_PSR_POWER_OPT = 7,
2123};
2124
2125enum dmub_cmd_fams_type {
2126 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
2127 DMUB_CMD__FAMS_DRR_UPDATE = 1,
2128 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
2129 /**
2130 * For SubVP set manual trigger in FW because it
2131 * triggers DRR_UPDATE_PENDING which SubVP relies
2132 * on (for any SubVP cases that use a DRR display)
2133 */
2134 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
2135};
2136
2137/**
2138 * PSR versions.
2139 */
2140enum psr_version {
2141 /**
2142 * PSR version 1.
2143 */
2144 PSR_VERSION_1 = 0,
2145 /**
2146 * Freesync PSR SU.
2147 */
2148 PSR_VERSION_SU_1 = 1,
2149 /**
2150 * PSR not supported.
2151 */
2152 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide
2153};
2154
2155/**
2156 * PHY Link rate for DP.
2157 */
2158enum phy_link_rate {
2159 /**
2160 * not supported.
2161 */
2162 PHY_RATE_UNKNOWN = 0,
2163 /**
2164 * Rate_1 (RBR) - 1.62 Gbps/Lane
2165 */
2166 PHY_RATE_162 = 1,
2167 /**
2168 * Rate_2 - 2.16 Gbps/Lane
2169 */
2170 PHY_RATE_216 = 2,
2171 /**
2172 * Rate_3 - 2.43 Gbps/Lane
2173 */
2174 PHY_RATE_243 = 3,
2175 /**
2176 * Rate_4 (HBR) - 2.70 Gbps/Lane
2177 */
2178 PHY_RATE_270 = 4,
2179 /**
2180 * Rate_5 (RBR2)- 3.24 Gbps/Lane
2181 */
2182 PHY_RATE_324 = 5,
2183 /**
2184 * Rate_6 - 4.32 Gbps/Lane
2185 */
2186 PHY_RATE_432 = 6,
2187 /**
2188 * Rate_7 (HBR2)- 5.40 Gbps/Lane
2189 */
2190 PHY_RATE_540 = 7,
2191 /**
2192 * Rate_8 (HBR3)- 8.10 Gbps/Lane
2193 */
2194 PHY_RATE_810 = 8,
2195 /**
2196 * UHBR10 - 10.0 Gbps/Lane
2197 */
2198 PHY_RATE_1000 = 9,
2199 /**
2200 * UHBR13.5 - 13.5 Gbps/Lane
2201 */
2202 PHY_RATE_1350 = 10,
2203 /**
2204 * UHBR10 - 20.0 Gbps/Lane
2205 */
2206 PHY_RATE_2000 = 11,
2207};
2208
2209/**
2210 * enum dmub_phy_fsm_state - PHY FSM states.
2211 * PHY FSM state to transit to during PSR enable/disable.
2212 */
2213enum dmub_phy_fsm_state {
2214 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
2215 DMUB_PHY_FSM_RESET,
2216 DMUB_PHY_FSM_RESET_RELEASED,
2217 DMUB_PHY_FSM_SRAM_LOAD_DONE,
2218 DMUB_PHY_FSM_INITIALIZED,
2219 DMUB_PHY_FSM_CALIBRATED,
2220 DMUB_PHY_FSM_CALIBRATED_LP,
2221 DMUB_PHY_FSM_CALIBRATED_PG,
2222 DMUB_PHY_FSM_POWER_DOWN,
2223 DMUB_PHY_FSM_PLL_EN,
2224 DMUB_PHY_FSM_TX_EN,
2225 DMUB_PHY_FSM_FAST_LP,
2226 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
2227 DMUB_PHY_FSM_P2_PLL_OFF_PG,
2228 DMUB_PHY_FSM_P2_PLL_OFF,
2229 DMUB_PHY_FSM_P2_PLL_ON,
2230};
2231
2232/**
2233 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2234 */
2235struct dmub_cmd_psr_copy_settings_data {
2236 /**
2237 * Flags that can be set by driver to change some PSR behaviour.
2238 */
2239 union dmub_psr_debug_flags debug;
2240 /**
2241 * 16-bit value dicated by driver that will enable/disable different functionality.
2242 */
2243 uint16_t psr_level;
2244 /**
2245 * DPP HW instance.
2246 */
2247 uint8_t dpp_inst;
2248 /**
2249 * MPCC HW instance.
2250 * Not used in dmub fw,
2251 * dmub fw will get active opp by reading odm registers.
2252 */
2253 uint8_t mpcc_inst;
2254 /**
2255 * OPP HW instance.
2256 * Not used in dmub fw,
2257 * dmub fw will get active opp by reading odm registers.
2258 */
2259 uint8_t opp_inst;
2260 /**
2261 * OTG HW instance.
2262 */
2263 uint8_t otg_inst;
2264 /**
2265 * DIG FE HW instance.
2266 */
2267 uint8_t digfe_inst;
2268 /**
2269 * DIG BE HW instance.
2270 */
2271 uint8_t digbe_inst;
2272 /**
2273 * DP PHY HW instance.
2274 */
2275 uint8_t dpphy_inst;
2276 /**
2277 * AUX HW instance.
2278 */
2279 uint8_t aux_inst;
2280 /**
2281 * Determines if SMU optimzations are enabled/disabled.
2282 */
2283 uint8_t smu_optimizations_en;
2284 /**
2285 * Unused.
2286 * TODO: Remove.
2287 */
2288 uint8_t frame_delay;
2289 /**
2290 * If RFB setup time is greater than the total VBLANK time,
2291 * it is not possible for the sink to capture the video frame
2292 * in the same frame the SDP is sent. In this case,
2293 * the frame capture indication bit should be set and an extra
2294 * static frame should be transmitted to the sink.
2295 */
2296 uint8_t frame_cap_ind;
2297 /**
2298 * Granularity of Y offset supported by sink.
2299 */
2300 uint8_t su_y_granularity;
2301 /**
2302 * Indicates whether sink should start capturing
2303 * immediately following active scan line,
2304 * or starting with the 2nd active scan line.
2305 */
2306 uint8_t line_capture_indication;
2307 /**
2308 * Multi-display optimizations are implemented on certain ASICs.
2309 */
2310 uint8_t multi_disp_optimizations_en;
2311 /**
2312 * The last possible line SDP may be transmitted without violating
2313 * the RFB setup time or entering the active video frame.
2314 */
2315 uint16_t init_sdp_deadline;
2316 /**
2317 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
2318 */
2319 uint8_t rate_control_caps ;
2320 /*
2321 * Force PSRSU always doing full frame update
2322 */
2323 uint8_t force_ffu_mode;
2324 /**
2325 * Length of each horizontal line in us.
2326 */
2327 uint32_t line_time_in_us;
2328 /**
2329 * FEC enable status in driver
2330 */
2331 uint8_t fec_enable_status;
2332 /**
2333 * FEC re-enable delay when PSR exit.
2334 * unit is 100us, range form 0~255(0xFF).
2335 */
2336 uint8_t fec_enable_delay_in100us;
2337 /**
2338 * PSR control version.
2339 */
2340 uint8_t cmd_version;
2341 /**
2342 * Panel Instance.
2343 * Panel instance to identify which psr_state to use
2344 * Currently the support is only for 0 or 1
2345 */
2346 uint8_t panel_inst;
2347 /*
2348 * DSC enable status in driver
2349 */
2350 uint8_t dsc_enable_status;
2351 /*
2352 * Use FSM state for PSR power up/down
2353 */
2354 uint8_t use_phy_fsm;
2355 /**
2356 * frame delay for frame re-lock
2357 */
2358 uint8_t relock_delay_frame_cnt;
2359 /**
2360 * Explicit padding to 4 byte boundary.
2361 */
2362 uint8_t pad3;
2363 /**
2364 * DSC Slice height.
2365 */
2366 uint16_t dsc_slice_height;
2367 /**
2368 * Some panels request main link off before xth vertical line
2369 */
2370 uint16_t poweroff_before_vertical_line;
2371};
2372
2373/**
2374 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2375 */
2376struct dmub_rb_cmd_psr_copy_settings {
2377 /**
2378 * Command header.
2379 */
2380 struct dmub_cmd_header header;
2381 /**
2382 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2383 */
2384 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
2385};
2386
2387/**
2388 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
2389 */
2390struct dmub_cmd_psr_set_level_data {
2391 /**
2392 * 16-bit value dicated by driver that will enable/disable different functionality.
2393 */
2394 uint16_t psr_level;
2395 /**
2396 * PSR control version.
2397 */
2398 uint8_t cmd_version;
2399 /**
2400 * Panel Instance.
2401 * Panel instance to identify which psr_state to use
2402 * Currently the support is only for 0 or 1
2403 */
2404 uint8_t panel_inst;
2405};
2406
2407/**
2408 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2409 */
2410struct dmub_rb_cmd_psr_set_level {
2411 /**
2412 * Command header.
2413 */
2414 struct dmub_cmd_header header;
2415 /**
2416 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2417 */
2418 struct dmub_cmd_psr_set_level_data psr_set_level_data;
2419};
2420
2421struct dmub_rb_cmd_psr_enable_data {
2422 /**
2423 * PSR control version.
2424 */
2425 uint8_t cmd_version;
2426 /**
2427 * Panel Instance.
2428 * Panel instance to identify which psr_state to use
2429 * Currently the support is only for 0 or 1
2430 */
2431 uint8_t panel_inst;
2432 /**
2433 * Phy state to enter.
2434 * Values to use are defined in dmub_phy_fsm_state
2435 */
2436 uint8_t phy_fsm_state;
2437 /**
2438 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2439 * Set this using enum phy_link_rate.
2440 * This does not support HDMI/DP2 for now.
2441 */
2442 uint8_t phy_rate;
2443};
2444
2445/**
2446 * Definition of a DMUB_CMD__PSR_ENABLE command.
2447 * PSR enable/disable is controlled using the sub_type.
2448 */
2449struct dmub_rb_cmd_psr_enable {
2450 /**
2451 * Command header.
2452 */
2453 struct dmub_cmd_header header;
2454
2455 struct dmub_rb_cmd_psr_enable_data data;
2456};
2457
2458/**
2459 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2460 */
2461struct dmub_cmd_psr_set_version_data {
2462 /**
2463 * PSR version that FW should implement.
2464 */
2465 enum psr_version version;
2466 /**
2467 * PSR control version.
2468 */
2469 uint8_t cmd_version;
2470 /**
2471 * Panel Instance.
2472 * Panel instance to identify which psr_state to use
2473 * Currently the support is only for 0 or 1
2474 */
2475 uint8_t panel_inst;
2476 /**
2477 * Explicit padding to 4 byte boundary.
2478 */
2479 uint8_t pad[2];
2480};
2481
2482/**
2483 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2484 */
2485struct dmub_rb_cmd_psr_set_version {
2486 /**
2487 * Command header.
2488 */
2489 struct dmub_cmd_header header;
2490 /**
2491 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2492 */
2493 struct dmub_cmd_psr_set_version_data psr_set_version_data;
2494};
2495
2496struct dmub_cmd_psr_force_static_data {
2497 /**
2498 * PSR control version.
2499 */
2500 uint8_t cmd_version;
2501 /**
2502 * Panel Instance.
2503 * Panel instance to identify which psr_state to use
2504 * Currently the support is only for 0 or 1
2505 */
2506 uint8_t panel_inst;
2507 /**
2508 * Explicit padding to 4 byte boundary.
2509 */
2510 uint8_t pad[2];
2511};
2512
2513/**
2514 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2515 */
2516struct dmub_rb_cmd_psr_force_static {
2517 /**
2518 * Command header.
2519 */
2520 struct dmub_cmd_header header;
2521 /**
2522 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
2523 */
2524 struct dmub_cmd_psr_force_static_data psr_force_static_data;
2525};
2526
2527/**
2528 * PSR SU debug flags.
2529 */
2530union dmub_psr_su_debug_flags {
2531 /**
2532 * PSR SU debug flags.
2533 */
2534 struct {
2535 /**
2536 * Update dirty rect in SW only.
2537 */
2538 uint8_t update_dirty_rect_only : 1;
2539 /**
2540 * Reset the cursor/plane state before processing the call.
2541 */
2542 uint8_t reset_state : 1;
2543 } bitfields;
2544
2545 /**
2546 * Union for debug flags.
2547 */
2548 uint32_t u32All;
2549};
2550
2551/**
2552 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2553 * This triggers a selective update for PSR SU.
2554 */
2555struct dmub_cmd_update_dirty_rect_data {
2556 /**
2557 * Dirty rects from OS.
2558 */
2559 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
2560 /**
2561 * PSR SU debug flags.
2562 */
2563 union dmub_psr_su_debug_flags debug_flags;
2564 /**
2565 * OTG HW instance.
2566 */
2567 uint8_t pipe_idx;
2568 /**
2569 * Number of dirty rects.
2570 */
2571 uint8_t dirty_rect_count;
2572 /**
2573 * PSR control version.
2574 */
2575 uint8_t cmd_version;
2576 /**
2577 * Panel Instance.
2578 * Panel instance to identify which psr_state to use
2579 * Currently the support is only for 0 or 1
2580 */
2581 uint8_t panel_inst;
2582};
2583
2584/**
2585 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
2586 */
2587struct dmub_rb_cmd_update_dirty_rect {
2588 /**
2589 * Command header.
2590 */
2591 struct dmub_cmd_header header;
2592 /**
2593 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2594 */
2595 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
2596};
2597
2598/**
2599 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2600 */
2601union dmub_reg_cursor_control_cfg {
2602 struct {
2603 uint32_t cur_enable: 1;
2604 uint32_t reser0: 3;
2605 uint32_t cur_2x_magnify: 1;
2606 uint32_t reser1: 3;
2607 uint32_t mode: 3;
2608 uint32_t reser2: 5;
2609 uint32_t pitch: 2;
2610 uint32_t reser3: 6;
2611 uint32_t line_per_chunk: 5;
2612 uint32_t reser4: 3;
2613 } bits;
2614 uint32_t raw;
2615};
2616struct dmub_cursor_position_cache_hubp {
2617 union dmub_reg_cursor_control_cfg cur_ctl;
2618 union dmub_reg_position_cfg {
2619 struct {
2620 uint32_t cur_x_pos: 16;
2621 uint32_t cur_y_pos: 16;
2622 } bits;
2623 uint32_t raw;
2624 } position;
2625 union dmub_reg_hot_spot_cfg {
2626 struct {
2627 uint32_t hot_x: 16;
2628 uint32_t hot_y: 16;
2629 } bits;
2630 uint32_t raw;
2631 } hot_spot;
2632 union dmub_reg_dst_offset_cfg {
2633 struct {
2634 uint32_t dst_x_offset: 13;
2635 uint32_t reserved: 19;
2636 } bits;
2637 uint32_t raw;
2638 } dst_offset;
2639};
2640
2641union dmub_reg_cur0_control_cfg {
2642 struct {
2643 uint32_t cur0_enable: 1;
2644 uint32_t expansion_mode: 1;
2645 uint32_t reser0: 1;
2646 uint32_t cur0_rom_en: 1;
2647 uint32_t mode: 3;
2648 uint32_t reserved: 25;
2649 } bits;
2650 uint32_t raw;
2651};
2652struct dmub_cursor_position_cache_dpp {
2653 union dmub_reg_cur0_control_cfg cur0_ctl;
2654};
2655struct dmub_cursor_position_cfg {
2656 struct dmub_cursor_position_cache_hubp pHubp;
2657 struct dmub_cursor_position_cache_dpp pDpp;
2658 uint8_t pipe_idx;
2659 /*
2660 * Padding is required. To be 4 Bytes Aligned.
2661 */
2662 uint8_t padding[3];
2663};
2664
2665struct dmub_cursor_attribute_cache_hubp {
2666 uint32_t SURFACE_ADDR_HIGH;
2667 uint32_t SURFACE_ADDR;
2668 union dmub_reg_cursor_control_cfg cur_ctl;
2669 union dmub_reg_cursor_size_cfg {
2670 struct {
2671 uint32_t width: 16;
2672 uint32_t height: 16;
2673 } bits;
2674 uint32_t raw;
2675 } size;
2676 union dmub_reg_cursor_settings_cfg {
2677 struct {
2678 uint32_t dst_y_offset: 8;
2679 uint32_t chunk_hdl_adjust: 2;
2680 uint32_t reserved: 22;
2681 } bits;
2682 uint32_t raw;
2683 } settings;
2684};
2685struct dmub_cursor_attribute_cache_dpp {
2686 union dmub_reg_cur0_control_cfg cur0_ctl;
2687};
2688struct dmub_cursor_attributes_cfg {
2689 struct dmub_cursor_attribute_cache_hubp aHubp;
2690 struct dmub_cursor_attribute_cache_dpp aDpp;
2691};
2692
2693struct dmub_cmd_update_cursor_payload0 {
2694 /**
2695 * Cursor dirty rects.
2696 */
2697 struct dmub_rect cursor_rect;
2698 /**
2699 * PSR SU debug flags.
2700 */
2701 union dmub_psr_su_debug_flags debug_flags;
2702 /**
2703 * Cursor enable/disable.
2704 */
2705 uint8_t enable;
2706 /**
2707 * OTG HW instance.
2708 */
2709 uint8_t pipe_idx;
2710 /**
2711 * PSR control version.
2712 */
2713 uint8_t cmd_version;
2714 /**
2715 * Panel Instance.
2716 * Panel instance to identify which psr_state to use
2717 * Currently the support is only for 0 or 1
2718 */
2719 uint8_t panel_inst;
2720 /**
2721 * Cursor Position Register.
2722 * Registers contains Hubp & Dpp modules
2723 */
2724 struct dmub_cursor_position_cfg position_cfg;
2725};
2726
2727struct dmub_cmd_update_cursor_payload1 {
2728 struct dmub_cursor_attributes_cfg attribute_cfg;
2729};
2730
2731union dmub_cmd_update_cursor_info_data {
2732 struct dmub_cmd_update_cursor_payload0 payload0;
2733 struct dmub_cmd_update_cursor_payload1 payload1;
2734};
2735/**
2736 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
2737 */
2738struct dmub_rb_cmd_update_cursor_info {
2739 /**
2740 * Command header.
2741 */
2742 struct dmub_cmd_header header;
2743 /**
2744 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2745 */
2746 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
2747};
2748
2749/**
2750 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2751 */
2752struct dmub_cmd_psr_set_vtotal_data {
2753 /**
2754 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
2755 */
2756 uint16_t psr_vtotal_idle;
2757 /**
2758 * PSR control version.
2759 */
2760 uint8_t cmd_version;
2761 /**
2762 * Panel Instance.
2763 * Panel instance to identify which psr_state to use
2764 * Currently the support is only for 0 or 1
2765 */
2766 uint8_t panel_inst;
2767 /*
2768 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
2769 */
2770 uint16_t psr_vtotal_su;
2771 /**
2772 * Explicit padding to 4 byte boundary.
2773 */
2774 uint8_t pad2[2];
2775};
2776
2777/**
2778 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2779 */
2780struct dmub_rb_cmd_psr_set_vtotal {
2781 /**
2782 * Command header.
2783 */
2784 struct dmub_cmd_header header;
2785 /**
2786 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2787 */
2788 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
2789};
2790
2791/**
2792 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
2793 */
2794struct dmub_cmd_psr_set_power_opt_data {
2795 /**
2796 * PSR control version.
2797 */
2798 uint8_t cmd_version;
2799 /**
2800 * Panel Instance.
2801 * Panel instance to identify which psr_state to use
2802 * Currently the support is only for 0 or 1
2803 */
2804 uint8_t panel_inst;
2805 /**
2806 * Explicit padding to 4 byte boundary.
2807 */
2808 uint8_t pad[2];
2809 /**
2810 * PSR power option
2811 */
2812 uint32_t power_opt;
2813};
2814
2815/**
2816 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
2817 */
2818struct dmub_rb_cmd_psr_set_power_opt {
2819 /**
2820 * Command header.
2821 */
2822 struct dmub_cmd_header header;
2823 /**
2824 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
2825 */
2826 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
2827};
2828
2829#define REPLAY_RESIDENCY_MODE_SHIFT (0)
2830#define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
2831
2832#define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2833# define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
2834# define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2835# define REPLAY_RESIDENCY_MODE_IPS 0x10
2836
2837#define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2838# define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2839# define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2840
2841enum replay_state {
2842 REPLAY_STATE_0 = 0x0,
2843 REPLAY_STATE_1 = 0x10,
2844 REPLAY_STATE_1A = 0x11,
2845 REPLAY_STATE_2 = 0x20,
2846 REPLAY_STATE_3 = 0x30,
2847 REPLAY_STATE_3INIT = 0x31,
2848 REPLAY_STATE_4 = 0x40,
2849 REPLAY_STATE_4A = 0x41,
2850 REPLAY_STATE_4B = 0x42,
2851 REPLAY_STATE_4C = 0x43,
2852 REPLAY_STATE_4D = 0x44,
2853 REPLAY_STATE_4B_LOCKED = 0x4A,
2854 REPLAY_STATE_4C_UNLOCKED = 0x4B,
2855 REPLAY_STATE_5 = 0x50,
2856 REPLAY_STATE_5A = 0x51,
2857 REPLAY_STATE_5B = 0x52,
2858 REPLAY_STATE_5A_LOCKED = 0x5A,
2859 REPLAY_STATE_5B_UNLOCKED = 0x5B,
2860 REPLAY_STATE_6 = 0x60,
2861 REPLAY_STATE_6A = 0x61,
2862 REPLAY_STATE_6B = 0x62,
2863 REPLAY_STATE_INVALID = 0xFF,
2864};
2865
2866/**
2867 * Replay command sub-types.
2868 */
2869enum dmub_cmd_replay_type {
2870 /**
2871 * Copy driver-calculated parameters to REPLAY state.
2872 */
2873 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
2874 /**
2875 * Enable REPLAY.
2876 */
2877 DMUB_CMD__REPLAY_ENABLE = 1,
2878 /**
2879 * Set Replay power option.
2880 */
2881 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
2882 /**
2883 * Set coasting vtotal.
2884 */
2885 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
2886 /**
2887 * Set power opt and coasting vtotal.
2888 */
2889 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4,
2890 /**
2891 * Set disabled iiming sync.
2892 */
2893 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5,
2894 /**
2895 * Set Residency Frameupdate Timer.
2896 */
2897 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,
2898 /**
2899 * Set pseudo vtotal
2900 */
2901 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
2902};
2903
2904/**
2905 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2906 */
2907struct dmub_cmd_replay_copy_settings_data {
2908 /**
2909 * Flags that can be set by driver to change some replay behaviour.
2910 */
2911 union replay_debug_flags debug;
2912
2913 /**
2914 * @flags: Flags used to determine feature functionality.
2915 */
2916 union replay_hw_flags flags;
2917
2918 /**
2919 * DPP HW instance.
2920 */
2921 uint8_t dpp_inst;
2922 /**
2923 * OTG HW instance.
2924 */
2925 uint8_t otg_inst;
2926 /**
2927 * DIG FE HW instance.
2928 */
2929 uint8_t digfe_inst;
2930 /**
2931 * DIG BE HW instance.
2932 */
2933 uint8_t digbe_inst;
2934 /**
2935 * AUX HW instance.
2936 */
2937 uint8_t aux_inst;
2938 /**
2939 * Panel Instance.
2940 * Panel isntance to identify which psr_state to use
2941 * Currently the support is only for 0 or 1
2942 */
2943 uint8_t panel_inst;
2944 /**
2945 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
2946 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
2947 */
2948 uint8_t pixel_deviation_per_line;
2949 /**
2950 * @max_deviation_line: The max number of deviation line that can keep the timing
2951 * synchronized between the Source and Sink during Replay normal sleep mode.
2952 */
2953 uint8_t max_deviation_line;
2954 /**
2955 * Length of each horizontal line in ns.
2956 */
2957 uint32_t line_time_in_ns;
2958 /**
2959 * PHY instance.
2960 */
2961 uint8_t dpphy_inst;
2962 /**
2963 * Determines if SMU optimzations are enabled/disabled.
2964 */
2965 uint8_t smu_optimizations_en;
2966 /**
2967 * Determines if timing sync are enabled/disabled.
2968 */
2969 uint8_t replay_timing_sync_supported;
2970 /*
2971 * Use FSM state for Replay power up/down
2972 */
2973 uint8_t use_phy_fsm;
2974};
2975
2976/**
2977 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2978 */
2979struct dmub_rb_cmd_replay_copy_settings {
2980 /**
2981 * Command header.
2982 */
2983 struct dmub_cmd_header header;
2984 /**
2985 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2986 */
2987 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
2988};
2989
2990/**
2991 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
2992 */
2993enum replay_enable {
2994 /**
2995 * Disable REPLAY.
2996 */
2997 REPLAY_DISABLE = 0,
2998 /**
2999 * Enable REPLAY.
3000 */
3001 REPLAY_ENABLE = 1,
3002};
3003
3004/**
3005 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
3006 */
3007struct dmub_rb_cmd_replay_enable_data {
3008 /**
3009 * Replay enable or disable.
3010 */
3011 uint8_t enable;
3012 /**
3013 * Panel Instance.
3014 * Panel isntance to identify which replay_state to use
3015 * Currently the support is only for 0 or 1
3016 */
3017 uint8_t panel_inst;
3018 /**
3019 * Phy state to enter.
3020 * Values to use are defined in dmub_phy_fsm_state
3021 */
3022 uint8_t phy_fsm_state;
3023 /**
3024 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
3025 * Set this using enum phy_link_rate.
3026 * This does not support HDMI/DP2 for now.
3027 */
3028 uint8_t phy_rate;
3029};
3030
3031/**
3032 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
3033 * Replay enable/disable is controlled using action in data.
3034 */
3035struct dmub_rb_cmd_replay_enable {
3036 /**
3037 * Command header.
3038 */
3039 struct dmub_cmd_header header;
3040
3041 struct dmub_rb_cmd_replay_enable_data data;
3042};
3043
3044/**
3045 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3046 */
3047struct dmub_cmd_replay_set_power_opt_data {
3048 /**
3049 * Panel Instance.
3050 * Panel isntance to identify which replay_state to use
3051 * Currently the support is only for 0 or 1
3052 */
3053 uint8_t panel_inst;
3054 /**
3055 * Explicit padding to 4 byte boundary.
3056 */
3057 uint8_t pad[3];
3058 /**
3059 * REPLAY power option
3060 */
3061 uint32_t power_opt;
3062};
3063
3064/**
3065 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3066 */
3067struct dmub_cmd_replay_set_timing_sync_data {
3068 /**
3069 * Panel Instance.
3070 * Panel isntance to identify which replay_state to use
3071 * Currently the support is only for 0 or 1
3072 */
3073 uint8_t panel_inst;
3074 /**
3075 * REPLAY set_timing_sync
3076 */
3077 uint8_t timing_sync_supported;
3078 /**
3079 * Explicit padding to 4 byte boundary.
3080 */
3081 uint8_t pad[2];
3082};
3083
3084/**
3085 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3086 */
3087struct dmub_cmd_replay_set_pseudo_vtotal {
3088 /**
3089 * Panel Instance.
3090 * Panel isntance to identify which replay_state to use
3091 * Currently the support is only for 0 or 1
3092 */
3093 uint8_t panel_inst;
3094 /**
3095 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal
3096 */
3097 uint16_t vtotal;
3098 /**
3099 * Explicit padding to 4 byte boundary.
3100 */
3101 uint8_t pad;
3102};
3103
3104/**
3105 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3106 */
3107struct dmub_rb_cmd_replay_set_power_opt {
3108 /**
3109 * Command header.
3110 */
3111 struct dmub_cmd_header header;
3112 /**
3113 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3114 */
3115 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
3116};
3117
3118/**
3119 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3120 */
3121struct dmub_cmd_replay_set_coasting_vtotal_data {
3122 /**
3123 * 16-bit value dicated by driver that indicates the coasting vtotal.
3124 */
3125 uint16_t coasting_vtotal;
3126 /**
3127 * REPLAY control version.
3128 */
3129 uint8_t cmd_version;
3130 /**
3131 * Panel Instance.
3132 * Panel isntance to identify which replay_state to use
3133 * Currently the support is only for 0 or 1
3134 */
3135 uint8_t panel_inst;
3136};
3137
3138/**
3139 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3140 */
3141struct dmub_rb_cmd_replay_set_coasting_vtotal {
3142 /**
3143 * Command header.
3144 */
3145 struct dmub_cmd_header header;
3146 /**
3147 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3148 */
3149 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3150};
3151
3152/**
3153 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
3154 */
3155struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
3156 /**
3157 * Command header.
3158 */
3159 struct dmub_cmd_header header;
3160 /**
3161 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3162 */
3163 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
3164 /**
3165 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3166 */
3167 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3168};
3169
3170/**
3171 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3172 */
3173struct dmub_rb_cmd_replay_set_timing_sync {
3174 /**
3175 * Command header.
3176 */
3177 struct dmub_cmd_header header;
3178 /**
3179 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3180 */
3181 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;
3182};
3183
3184/**
3185 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3186 */
3187struct dmub_rb_cmd_replay_set_pseudo_vtotal {
3188 /**
3189 * Command header.
3190 */
3191 struct dmub_cmd_header header;
3192 /**
3193 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3194 */
3195 struct dmub_cmd_replay_set_pseudo_vtotal data;
3196};
3197
3198/**
3199 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
3200 */
3201struct dmub_cmd_replay_frameupdate_timer_data {
3202 /**
3203 * Panel Instance.
3204 * Panel isntance to identify which replay_state to use
3205 * Currently the support is only for 0 or 1
3206 */
3207 uint8_t panel_inst;
3208 /**
3209 * Replay Frameupdate Timer Enable or not
3210 */
3211 uint8_t enable;
3212 /**
3213 * REPLAY force reflash frame update number
3214 */
3215 uint16_t frameupdate_count;
3216};
3217/**
3218 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
3219 */
3220struct dmub_rb_cmd_replay_set_frameupdate_timer {
3221 /**
3222 * Command header.
3223 */
3224 struct dmub_cmd_header header;
3225 /**
3226 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3227 */
3228 struct dmub_cmd_replay_frameupdate_timer_data data;
3229};
3230
3231/**
3232 * Definition union of replay command set
3233 */
3234union dmub_replay_cmd_set {
3235 /**
3236 * Panel Instance.
3237 * Panel isntance to identify which replay_state to use
3238 * Currently the support is only for 0 or 1
3239 */
3240 uint8_t panel_inst;
3241 /**
3242 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.
3243 */
3244 struct dmub_cmd_replay_set_timing_sync_data sync_data;
3245 /**
3246 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.
3247 */
3248 struct dmub_cmd_replay_frameupdate_timer_data timer_data;
3249 /**
3250 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
3251 */
3252 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
3253};
3254
3255/**
3256 * Set of HW components that can be locked.
3257 *
3258 * Note: If updating with more HW components, fields
3259 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3260 */
3261union dmub_hw_lock_flags {
3262 /**
3263 * Set of HW components that can be locked.
3264 */
3265 struct {
3266 /**
3267 * Lock/unlock OTG master update lock.
3268 */
3269 uint8_t lock_pipe : 1;
3270 /**
3271 * Lock/unlock cursor.
3272 */
3273 uint8_t lock_cursor : 1;
3274 /**
3275 * Lock/unlock global update lock.
3276 */
3277 uint8_t lock_dig : 1;
3278 /**
3279 * Triple buffer lock requires additional hw programming to usual OTG master lock.
3280 */
3281 uint8_t triple_buffer_lock : 1;
3282 } bits;
3283
3284 /**
3285 * Union for HW Lock flags.
3286 */
3287 uint8_t u8All;
3288};
3289
3290/**
3291 * Instances of HW to be locked.
3292 *
3293 * Note: If updating with more HW components, fields
3294 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3295 */
3296struct dmub_hw_lock_inst_flags {
3297 /**
3298 * OTG HW instance for OTG master update lock.
3299 */
3300 uint8_t otg_inst;
3301 /**
3302 * OPP instance for cursor lock.
3303 */
3304 uint8_t opp_inst;
3305 /**
3306 * OTG HW instance for global update lock.
3307 * TODO: Remove, and re-use otg_inst.
3308 */
3309 uint8_t dig_inst;
3310 /**
3311 * Explicit pad to 4 byte boundary.
3312 */
3313 uint8_t pad;
3314};
3315
3316/**
3317 * Clients that can acquire the HW Lock Manager.
3318 *
3319 * Note: If updating with more clients, fields in
3320 * dmub_inbox0_cmd_lock_hw must be updated to match.
3321 */
3322enum hw_lock_client {
3323 /**
3324 * Driver is the client of HW Lock Manager.
3325 */
3326 HW_LOCK_CLIENT_DRIVER = 0,
3327 /**
3328 * PSR SU is the client of HW Lock Manager.
3329 */
3330 HW_LOCK_CLIENT_PSR_SU = 1,
3331 HW_LOCK_CLIENT_SUBVP = 3,
3332 /**
3333 * Replay is the client of HW Lock Manager.
3334 */
3335 HW_LOCK_CLIENT_REPLAY = 4,
3336 /**
3337 * Invalid client.
3338 */
3339 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
3340};
3341
3342/**
3343 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3344 */
3345struct dmub_cmd_lock_hw_data {
3346 /**
3347 * Specifies the client accessing HW Lock Manager.
3348 */
3349 enum hw_lock_client client;
3350 /**
3351 * HW instances to be locked.
3352 */
3353 struct dmub_hw_lock_inst_flags inst_flags;
3354 /**
3355 * Which components to be locked.
3356 */
3357 union dmub_hw_lock_flags hw_locks;
3358 /**
3359 * Specifies lock/unlock.
3360 */
3361 uint8_t lock;
3362 /**
3363 * HW can be unlocked separately from releasing the HW Lock Mgr.
3364 * This flag is set if the client wishes to release the object.
3365 */
3366 uint8_t should_release;
3367 /**
3368 * Explicit padding to 4 byte boundary.
3369 */
3370 uint8_t pad;
3371};
3372
3373/**
3374 * Definition of a DMUB_CMD__HW_LOCK command.
3375 * Command is used by driver and FW.
3376 */
3377struct dmub_rb_cmd_lock_hw {
3378 /**
3379 * Command header.
3380 */
3381 struct dmub_cmd_header header;
3382 /**
3383 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3384 */
3385 struct dmub_cmd_lock_hw_data lock_hw_data;
3386};
3387
3388/**
3389 * ABM command sub-types.
3390 */
3391enum dmub_cmd_abm_type {
3392 /**
3393 * Initialize parameters for ABM algorithm.
3394 * Data is passed through an indirect buffer.
3395 */
3396 DMUB_CMD__ABM_INIT_CONFIG = 0,
3397 /**
3398 * Set OTG and panel HW instance.
3399 */
3400 DMUB_CMD__ABM_SET_PIPE = 1,
3401 /**
3402 * Set user requested backklight level.
3403 */
3404 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
3405 /**
3406 * Set ABM operating/aggression level.
3407 */
3408 DMUB_CMD__ABM_SET_LEVEL = 3,
3409 /**
3410 * Set ambient light level.
3411 */
3412 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
3413 /**
3414 * Enable/disable fractional duty cycle for backlight PWM.
3415 */
3416 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
3417
3418 /**
3419 * unregister vertical interrupt after steady state is reached
3420 */
3421 DMUB_CMD__ABM_PAUSE = 6,
3422
3423 /**
3424 * Save and Restore ABM state. On save we save parameters, and
3425 * on restore we update state with passed in data.
3426 */
3427 DMUB_CMD__ABM_SAVE_RESTORE = 7,
3428};
3429
3430/**
3431 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
3432 * Requirements:
3433 * - Padded explicitly to 32-bit boundary.
3434 * - Must ensure this structure matches the one on driver-side,
3435 * otherwise it won't be aligned.
3436 */
3437struct abm_config_table {
3438 /**
3439 * Gamma curve thresholds, used for crgb conversion.
3440 */
3441 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
3442 /**
3443 * Gamma curve offsets, used for crgb conversion.
3444 */
3445 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
3446 /**
3447 * Gamma curve slopes, used for crgb conversion.
3448 */
3449 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
3450 /**
3451 * Custom backlight curve thresholds.
3452 */
3453 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
3454 /**
3455 * Custom backlight curve offsets.
3456 */
3457 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
3458 /**
3459 * Ambient light thresholds.
3460 */
3461 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
3462 /**
3463 * Minimum programmable backlight.
3464 */
3465 uint16_t min_abm_backlight; // 122B
3466 /**
3467 * Minimum reduction values.
3468 */
3469 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
3470 /**
3471 * Maximum reduction values.
3472 */
3473 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
3474 /**
3475 * Bright positive gain.
3476 */
3477 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
3478 /**
3479 * Dark negative gain.
3480 */
3481 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
3482 /**
3483 * Hybrid factor.
3484 */
3485 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
3486 /**
3487 * Contrast factor.
3488 */
3489 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
3490 /**
3491 * Deviation gain.
3492 */
3493 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
3494 /**
3495 * Minimum knee.
3496 */
3497 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
3498 /**
3499 * Maximum knee.
3500 */
3501 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
3502 /**
3503 * Unused.
3504 */
3505 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
3506 /**
3507 * Explicit padding to 4 byte boundary.
3508 */
3509 uint8_t pad3[3]; // 229B
3510 /**
3511 * Backlight ramp reduction.
3512 */
3513 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
3514 /**
3515 * Backlight ramp start.
3516 */
3517 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
3518};
3519
3520/**
3521 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3522 */
3523struct dmub_cmd_abm_set_pipe_data {
3524 /**
3525 * OTG HW instance.
3526 */
3527 uint8_t otg_inst;
3528
3529 /**
3530 * Panel Control HW instance.
3531 */
3532 uint8_t panel_inst;
3533
3534 /**
3535 * Controls how ABM will interpret a set pipe or set level command.
3536 */
3537 uint8_t set_pipe_option;
3538
3539 /**
3540 * Unused.
3541 * TODO: Remove.
3542 */
3543 uint8_t ramping_boundary;
3544
3545 /**
3546 * PwrSeq HW Instance.
3547 */
3548 uint8_t pwrseq_inst;
3549
3550 /**
3551 * Explicit padding to 4 byte boundary.
3552 */
3553 uint8_t pad[3];
3554};
3555
3556/**
3557 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
3558 */
3559struct dmub_rb_cmd_abm_set_pipe {
3560 /**
3561 * Command header.
3562 */
3563 struct dmub_cmd_header header;
3564
3565 /**
3566 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3567 */
3568 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
3569};
3570
3571/**
3572 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3573 */
3574struct dmub_cmd_abm_set_backlight_data {
3575 /**
3576 * Number of frames to ramp to backlight user level.
3577 */
3578 uint32_t frame_ramp;
3579
3580 /**
3581 * Requested backlight level from user.
3582 */
3583 uint32_t backlight_user_level;
3584
3585 /**
3586 * ABM control version.
3587 */
3588 uint8_t version;
3589
3590 /**
3591 * Panel Control HW instance mask.
3592 * Bit 0 is Panel Control HW instance 0.
3593 * Bit 1 is Panel Control HW instance 1.
3594 */
3595 uint8_t panel_mask;
3596
3597 /**
3598 * Explicit padding to 4 byte boundary.
3599 */
3600 uint8_t pad[2];
3601};
3602
3603/**
3604 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
3605 */
3606struct dmub_rb_cmd_abm_set_backlight {
3607 /**
3608 * Command header.
3609 */
3610 struct dmub_cmd_header header;
3611
3612 /**
3613 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3614 */
3615 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
3616};
3617
3618/**
3619 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3620 */
3621struct dmub_cmd_abm_set_level_data {
3622 /**
3623 * Set current ABM operating/aggression level.
3624 */
3625 uint32_t level;
3626
3627 /**
3628 * ABM control version.
3629 */
3630 uint8_t version;
3631
3632 /**
3633 * Panel Control HW instance mask.
3634 * Bit 0 is Panel Control HW instance 0.
3635 * Bit 1 is Panel Control HW instance 1.
3636 */
3637 uint8_t panel_mask;
3638
3639 /**
3640 * Explicit padding to 4 byte boundary.
3641 */
3642 uint8_t pad[2];
3643};
3644
3645/**
3646 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
3647 */
3648struct dmub_rb_cmd_abm_set_level {
3649 /**
3650 * Command header.
3651 */
3652 struct dmub_cmd_header header;
3653
3654 /**
3655 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3656 */
3657 struct dmub_cmd_abm_set_level_data abm_set_level_data;
3658};
3659
3660/**
3661 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3662 */
3663struct dmub_cmd_abm_set_ambient_level_data {
3664 /**
3665 * Ambient light sensor reading from OS.
3666 */
3667 uint32_t ambient_lux;
3668
3669 /**
3670 * ABM control version.
3671 */
3672 uint8_t version;
3673
3674 /**
3675 * Panel Control HW instance mask.
3676 * Bit 0 is Panel Control HW instance 0.
3677 * Bit 1 is Panel Control HW instance 1.
3678 */
3679 uint8_t panel_mask;
3680
3681 /**
3682 * Explicit padding to 4 byte boundary.
3683 */
3684 uint8_t pad[2];
3685};
3686
3687/**
3688 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3689 */
3690struct dmub_rb_cmd_abm_set_ambient_level {
3691 /**
3692 * Command header.
3693 */
3694 struct dmub_cmd_header header;
3695
3696 /**
3697 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3698 */
3699 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
3700};
3701
3702/**
3703 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3704 */
3705struct dmub_cmd_abm_set_pwm_frac_data {
3706 /**
3707 * Enable/disable fractional duty cycle for backlight PWM.
3708 * TODO: Convert to uint8_t.
3709 */
3710 uint32_t fractional_pwm;
3711
3712 /**
3713 * ABM control version.
3714 */
3715 uint8_t version;
3716
3717 /**
3718 * Panel Control HW instance mask.
3719 * Bit 0 is Panel Control HW instance 0.
3720 * Bit 1 is Panel Control HW instance 1.
3721 */
3722 uint8_t panel_mask;
3723
3724 /**
3725 * Explicit padding to 4 byte boundary.
3726 */
3727 uint8_t pad[2];
3728};
3729
3730/**
3731 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
3732 */
3733struct dmub_rb_cmd_abm_set_pwm_frac {
3734 /**
3735 * Command header.
3736 */
3737 struct dmub_cmd_header header;
3738
3739 /**
3740 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3741 */
3742 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
3743};
3744
3745/**
3746 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3747 */
3748struct dmub_cmd_abm_init_config_data {
3749 /**
3750 * Location of indirect buffer used to pass init data to ABM.
3751 */
3752 union dmub_addr src;
3753
3754 /**
3755 * Indirect buffer length.
3756 */
3757 uint16_t bytes;
3758
3759
3760 /**
3761 * ABM control version.
3762 */
3763 uint8_t version;
3764
3765 /**
3766 * Panel Control HW instance mask.
3767 * Bit 0 is Panel Control HW instance 0.
3768 * Bit 1 is Panel Control HW instance 1.
3769 */
3770 uint8_t panel_mask;
3771
3772 /**
3773 * Explicit padding to 4 byte boundary.
3774 */
3775 uint8_t pad[2];
3776};
3777
3778/**
3779 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
3780 */
3781struct dmub_rb_cmd_abm_init_config {
3782 /**
3783 * Command header.
3784 */
3785 struct dmub_cmd_header header;
3786
3787 /**
3788 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3789 */
3790 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3791};
3792
3793/**
3794 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3795 */
3796
3797struct dmub_cmd_abm_pause_data {
3798
3799 /**
3800 * Panel Control HW instance mask.
3801 * Bit 0 is Panel Control HW instance 0.
3802 * Bit 1 is Panel Control HW instance 1.
3803 */
3804 uint8_t panel_mask;
3805
3806 /**
3807 * OTG hw instance
3808 */
3809 uint8_t otg_inst;
3810
3811 /**
3812 * Enable or disable ABM pause
3813 */
3814 uint8_t enable;
3815
3816 /**
3817 * Explicit padding to 4 byte boundary.
3818 */
3819 uint8_t pad[1];
3820};
3821
3822/**
3823 * Definition of a DMUB_CMD__ABM_PAUSE command.
3824 */
3825struct dmub_rb_cmd_abm_pause {
3826 /**
3827 * Command header.
3828 */
3829 struct dmub_cmd_header header;
3830
3831 /**
3832 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3833 */
3834 struct dmub_cmd_abm_pause_data abm_pause_data;
3835};
3836
3837/**
3838 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
3839 */
3840struct dmub_rb_cmd_abm_save_restore {
3841 /**
3842 * Command header.
3843 */
3844 struct dmub_cmd_header header;
3845
3846 /**
3847 * OTG hw instance
3848 */
3849 uint8_t otg_inst;
3850
3851 /**
3852 * Enable or disable ABM pause
3853 */
3854 uint8_t freeze;
3855
3856 /**
3857 * Explicit padding to 4 byte boundary.
3858 */
3859 uint8_t debug;
3860
3861 /**
3862 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3863 */
3864 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3865};
3866
3867/**
3868 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3869 */
3870struct dmub_cmd_query_feature_caps_data {
3871 /**
3872 * DMUB feature capabilities.
3873 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3874 */
3875 struct dmub_feature_caps feature_caps;
3876};
3877
3878/**
3879 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
3880 */
3881struct dmub_rb_cmd_query_feature_caps {
3882 /**
3883 * Command header.
3884 */
3885 struct dmub_cmd_header header;
3886 /**
3887 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3888 */
3889 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
3890};
3891
3892/**
3893 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3894 */
3895struct dmub_cmd_visual_confirm_color_data {
3896 /**
3897 * DMUB visual confirm color
3898 */
3899 struct dmub_visual_confirm_color visual_confirm_color;
3900};
3901
3902/**
3903 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3904 */
3905struct dmub_rb_cmd_get_visual_confirm_color {
3906 /**
3907 * Command header.
3908 */
3909 struct dmub_cmd_header header;
3910 /**
3911 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3912 */
3913 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
3914};
3915
3916/**
3917 * enum dmub_cmd_panel_cntl_type - Panel control command.
3918 */
3919enum dmub_cmd_panel_cntl_type {
3920 /**
3921 * Initializes embedded panel hardware blocks.
3922 */
3923 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
3924 /**
3925 * Queries backlight info for the embedded panel.
3926 */
3927 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
3928};
3929
3930/**
3931 * struct dmub_cmd_panel_cntl_data - Panel control data.
3932 */
3933struct dmub_cmd_panel_cntl_data {
3934 uint32_t pwrseq_inst; /**< pwrseq instance */
3935 uint32_t current_backlight; /* in/out */
3936 uint32_t bl_pwm_cntl; /* in/out */
3937 uint32_t bl_pwm_period_cntl; /* in/out */
3938 uint32_t bl_pwm_ref_div1; /* in/out */
3939 uint8_t is_backlight_on : 1; /* in/out */
3940 uint8_t is_powered_on : 1; /* in/out */
3941 uint8_t padding[3];
3942 uint32_t bl_pwm_ref_div2; /* in/out */
3943 uint8_t reserved[4];
3944};
3945
3946/**
3947 * struct dmub_rb_cmd_panel_cntl - Panel control command.
3948 */
3949struct dmub_rb_cmd_panel_cntl {
3950 struct dmub_cmd_header header; /**< header */
3951 struct dmub_cmd_panel_cntl_data data; /**< payload */
3952};
3953
3954struct dmub_optc_state {
3955 uint32_t v_total_max;
3956 uint32_t v_total_min;
3957 uint32_t tg_inst;
3958};
3959
3960struct dmub_rb_cmd_drr_update {
3961 struct dmub_cmd_header header;
3962 struct dmub_optc_state dmub_optc_state_req;
3963};
3964
3965struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
3966 uint32_t pix_clk_100hz;
3967 uint8_t max_ramp_step;
3968 uint8_t pipes;
3969 uint8_t min_refresh_in_hz;
3970 uint8_t pipe_count;
3971 uint8_t pipe_index[4];
3972};
3973
3974struct dmub_cmd_fw_assisted_mclk_switch_config {
3975 uint8_t fams_enabled;
3976 uint8_t visual_confirm_enabled;
3977 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
3978 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
3979};
3980
3981struct dmub_rb_cmd_fw_assisted_mclk_switch {
3982 struct dmub_cmd_header header;
3983 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
3984};
3985
3986/**
3987 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3988 */
3989struct dmub_cmd_lvtma_control_data {
3990 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
3991 uint8_t bypass_panel_control_wait;
3992 uint8_t reserved_0[2]; /**< For future use */
3993 uint8_t pwrseq_inst; /**< LVTMA control instance */
3994 uint8_t reserved_1[3]; /**< For future use */
3995};
3996
3997/**
3998 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3999 */
4000struct dmub_rb_cmd_lvtma_control {
4001 /**
4002 * Command header.
4003 */
4004 struct dmub_cmd_header header;
4005 /**
4006 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4007 */
4008 struct dmub_cmd_lvtma_control_data data;
4009};
4010
4011/**
4012 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4013 */
4014struct dmub_rb_cmd_transmitter_query_dp_alt_data {
4015 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
4016 uint8_t is_usb; /**< is phy is usb */
4017 uint8_t is_dp_alt_disable; /**< is dp alt disable */
4018 uint8_t is_dp4; /**< is dp in 4 lane */
4019};
4020
4021/**
4022 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4023 */
4024struct dmub_rb_cmd_transmitter_query_dp_alt {
4025 struct dmub_cmd_header header; /**< header */
4026 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
4027};
4028
4029/**
4030 * Maximum number of bytes a chunk sent to DMUB for parsing
4031 */
4032#define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
4033
4034/**
4035 * Represent a chunk of CEA blocks sent to DMUB for parsing
4036 */
4037struct dmub_cmd_send_edid_cea {
4038 uint16_t offset; /**< offset into the CEA block */
4039 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
4040 uint16_t cea_total_length; /**< total length of the CEA block */
4041 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
4042 uint8_t pad[3]; /**< padding and for future expansion */
4043};
4044
4045/**
4046 * Result of VSDB parsing from CEA block
4047 */
4048struct dmub_cmd_edid_cea_amd_vsdb {
4049 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
4050 uint8_t freesync_supported; /**< 1 if Freesync is supported */
4051 uint16_t amd_vsdb_version; /**< AMD VSDB version */
4052 uint16_t min_frame_rate; /**< Maximum frame rate */
4053 uint16_t max_frame_rate; /**< Minimum frame rate */
4054};
4055
4056/**
4057 * Result of sending a CEA chunk
4058 */
4059struct dmub_cmd_edid_cea_ack {
4060 uint16_t offset; /**< offset of the chunk into the CEA block */
4061 uint8_t success; /**< 1 if this sending of chunk succeeded */
4062 uint8_t pad; /**< padding and for future expansion */
4063};
4064
4065/**
4066 * Specify whether the result is an ACK/NACK or the parsing has finished
4067 */
4068enum dmub_cmd_edid_cea_reply_type {
4069 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
4070 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
4071};
4072
4073/**
4074 * Definition of a DMUB_CMD__EDID_CEA command.
4075 */
4076struct dmub_rb_cmd_edid_cea {
4077 struct dmub_cmd_header header; /**< Command header */
4078 union dmub_cmd_edid_cea_data {
4079 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
4080 struct dmub_cmd_edid_cea_output { /**< output with results */
4081 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
4082 union {
4083 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
4084 struct dmub_cmd_edid_cea_ack ack;
4085 };
4086 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
4087 } data; /**< Command data */
4088
4089};
4090
4091/**
4092 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
4093 */
4094struct dmub_cmd_cable_id_input {
4095 uint8_t phy_inst; /**< phy inst for cable id data */
4096};
4097
4098/**
4099 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
4100 */
4101struct dmub_cmd_cable_id_output {
4102 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
4103 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
4104 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
4105 uint8_t RESERVED :2; /**< reserved means not defined */
4106};
4107
4108/**
4109 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
4110 */
4111struct dmub_rb_cmd_get_usbc_cable_id {
4112 struct dmub_cmd_header header; /**< Command header */
4113 /**
4114 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
4115 */
4116 union dmub_cmd_cable_id_data {
4117 struct dmub_cmd_cable_id_input input; /**< Input */
4118 struct dmub_cmd_cable_id_output output; /**< Output */
4119 uint8_t output_raw; /**< Raw data output */
4120 } data;
4121};
4122
4123/**
4124 * Command type of a DMUB_CMD__SECURE_DISPLAY command
4125 */
4126enum dmub_cmd_secure_display_type {
4127 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
4128 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
4129 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
4130};
4131
4132/**
4133 * Definition of a DMUB_CMD__SECURE_DISPLAY command
4134 */
4135struct dmub_rb_cmd_secure_display {
4136 struct dmub_cmd_header header;
4137 /**
4138 * Data passed from driver to dmub firmware.
4139 */
4140 struct dmub_cmd_roi_info {
4141 uint16_t x_start;
4142 uint16_t x_end;
4143 uint16_t y_start;
4144 uint16_t y_end;
4145 uint8_t otg_id;
4146 uint8_t phy_id;
4147 } roi_info;
4148};
4149
4150/**
4151 * union dmub_rb_cmd - DMUB inbox command.
4152 */
4153union dmub_rb_cmd {
4154 /**
4155 * Elements shared with all commands.
4156 */
4157 struct dmub_rb_cmd_common cmd_common;
4158 /**
4159 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
4160 */
4161 struct dmub_rb_cmd_read_modify_write read_modify_write;
4162 /**
4163 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
4164 */
4165 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
4166 /**
4167 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
4168 */
4169 struct dmub_rb_cmd_burst_write burst_write;
4170 /**
4171 * Definition of a DMUB_CMD__REG_REG_WAIT command.
4172 */
4173 struct dmub_rb_cmd_reg_wait reg_wait;
4174 /**
4175 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
4176 */
4177 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
4178 /**
4179 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
4180 */
4181 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
4182 /**
4183 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
4184 */
4185 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
4186 /**
4187 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
4188 */
4189 struct dmub_rb_cmd_dpphy_init dpphy_init;
4190 /**
4191 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
4192 */
4193 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
4194 /**
4195 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
4196 */
4197 struct dmub_rb_cmd_domain_control domain_control;
4198 /**
4199 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
4200 */
4201 struct dmub_rb_cmd_psr_set_version psr_set_version;
4202 /**
4203 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
4204 */
4205 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
4206 /**
4207 * Definition of a DMUB_CMD__PSR_ENABLE command.
4208 */
4209 struct dmub_rb_cmd_psr_enable psr_enable;
4210 /**
4211 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
4212 */
4213 struct dmub_rb_cmd_psr_set_level psr_set_level;
4214 /**
4215 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
4216 */
4217 struct dmub_rb_cmd_psr_force_static psr_force_static;
4218 /**
4219 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
4220 */
4221 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
4222 /**
4223 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
4224 */
4225 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
4226 /**
4227 * Definition of a DMUB_CMD__HW_LOCK command.
4228 * Command is used by driver and FW.
4229 */
4230 struct dmub_rb_cmd_lock_hw lock_hw;
4231 /**
4232 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
4233 */
4234 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
4235 /**
4236 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
4237 */
4238 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
4239 /**
4240 * Definition of a DMUB_CMD__PLAT_54186_WA command.
4241 */
4242 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
4243 /**
4244 * Definition of a DMUB_CMD__MALL command.
4245 */
4246 struct dmub_rb_cmd_mall mall;
4247
4248 /**
4249 * Definition of a DMUB_CMD__CAB command.
4250 */
4251 struct dmub_rb_cmd_cab_for_ss cab;
4252
4253 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
4254
4255 /**
4256 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
4257 */
4258 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
4259
4260 /**
4261 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
4262 */
4263 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
4264
4265 /**
4266 * Definition of DMUB_CMD__PANEL_CNTL commands.
4267 */
4268 struct dmub_rb_cmd_panel_cntl panel_cntl;
4269
4270 /**
4271 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
4272 */
4273 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
4274
4275 /**
4276 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
4277 */
4278 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
4279
4280 /**
4281 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
4282 */
4283 struct dmub_rb_cmd_abm_set_level abm_set_level;
4284
4285 /**
4286 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4287 */
4288 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
4289
4290 /**
4291 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
4292 */
4293 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
4294
4295 /**
4296 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
4297 */
4298 struct dmub_rb_cmd_abm_init_config abm_init_config;
4299
4300 /**
4301 * Definition of a DMUB_CMD__ABM_PAUSE command.
4302 */
4303 struct dmub_rb_cmd_abm_pause abm_pause;
4304
4305 /**
4306 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4307 */
4308 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
4309
4310 /**
4311 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
4312 */
4313 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
4314
4315 /**
4316 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
4317 */
4318 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
4319
4320 /**
4321 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
4322 */
4323 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
4324
4325 /**
4326 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4327 */
4328 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
4329 struct dmub_rb_cmd_drr_update drr_update;
4330 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
4331
4332 /**
4333 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4334 */
4335 struct dmub_rb_cmd_lvtma_control lvtma_control;
4336 /**
4337 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4338 */
4339 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
4340 /**
4341 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
4342 */
4343 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
4344 /**
4345 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
4346 */
4347 struct dmub_rb_cmd_set_config_access set_config_access;
4348 /**
4349 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
4350 */
4351 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
4352 /**
4353 * Definition of a DMUB_CMD__EDID_CEA command.
4354 */
4355 struct dmub_rb_cmd_edid_cea edid_cea;
4356 /**
4357 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
4358 */
4359 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
4360
4361 /**
4362 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
4363 */
4364 struct dmub_rb_cmd_query_hpd_state query_hpd;
4365 /**
4366 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
4367 */
4368 struct dmub_rb_cmd_secure_display secure_display;
4369
4370 /**
4371 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
4372 */
4373 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
4374 /**
4375 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
4376 */
4377 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
4378 /*
4379 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4380 */
4381 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
4382 /**
4383 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
4384 */
4385 struct dmub_rb_cmd_replay_enable replay_enable;
4386 /**
4387 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4388 */
4389 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
4390 /**
4391 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4392 */
4393 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
4394 /**
4395 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
4396 */
4397 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;
4398
4399 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;
4400 /**
4401 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
4402 */
4403 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;
4404 /**
4405 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
4406 */
4407 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
4408};
4409
4410/**
4411 * union dmub_rb_out_cmd - Outbox command
4412 */
4413union dmub_rb_out_cmd {
4414 /**
4415 * Parameters common to every command.
4416 */
4417 struct dmub_rb_cmd_common cmd_common;
4418 /**
4419 * AUX reply command.
4420 */
4421 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
4422 /**
4423 * HPD notify command.
4424 */
4425 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
4426 /**
4427 * SET_CONFIG reply command.
4428 */
4429 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
4430 /**
4431 * DPIA notification command.
4432 */
4433 struct dmub_rb_cmd_dpia_notification dpia_notification;
4434};
4435#pragma pack(pop)
4436
4437
4438//==============================================================================
4439//</DMUB_CMD>===================================================================
4440//==============================================================================
4441//< DMUB_RB>====================================================================
4442//==============================================================================
4443
4444#if defined(__cplusplus)
4445extern "C" {
4446#endif
4447
4448/**
4449 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
4450 */
4451struct dmub_rb_init_params {
4452 void *ctx; /**< Caller provided context pointer */
4453 void *base_address; /**< CPU base address for ring's data */
4454 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4455 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
4456 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
4457};
4458
4459/**
4460 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
4461 */
4462struct dmub_rb {
4463 void *base_address; /**< CPU address for the ring's data */
4464 uint32_t rptr; /**< Read pointer for consumer in bytes */
4465 uint32_t wrpt; /**< Write pointer for producer in bytes */
4466 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4467
4468 void *ctx; /**< Caller provided context pointer */
4469 void *dmub; /**< Pointer to the DMUB interface */
4470};
4471
4472/**
4473 * @brief Checks if the ringbuffer is empty.
4474 *
4475 * @param rb DMUB Ringbuffer
4476 * @return true if empty
4477 * @return false otherwise
4478 */
4479static inline bool dmub_rb_empty(struct dmub_rb *rb)
4480{
4481 return (rb->wrpt == rb->rptr);
4482}
4483
4484/**
4485 * @brief Checks if the ringbuffer is full
4486 *
4487 * @param rb DMUB Ringbuffer
4488 * @return true if full
4489 * @return false otherwise
4490 */
4491static inline bool dmub_rb_full(struct dmub_rb *rb)
4492{
4493 uint32_t data_count;
4494
4495 if (rb->wrpt >= rb->rptr)
4496 data_count = rb->wrpt - rb->rptr;
4497 else
4498 data_count = rb->capacity - (rb->rptr - rb->wrpt);
4499
4500 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
4501}
4502
4503/**
4504 * @brief Pushes a command into the ringbuffer
4505 *
4506 * @param rb DMUB ringbuffer
4507 * @param cmd The command to push
4508 * @return true if the ringbuffer was not full
4509 * @return false otherwise
4510 */
4511static inline bool dmub_rb_push_front(struct dmub_rb *rb,
4512 const union dmub_rb_cmd *cmd)
4513{
4514 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
4515 const uint64_t *src = (const uint64_t *)cmd;
4516 uint8_t i;
4517
4518 if (dmub_rb_full(rb))
4519 return false;
4520
4521 // copying data
4522 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4523 *dst++ = *src++;
4524
4525 rb->wrpt += DMUB_RB_CMD_SIZE;
4526
4527 if (rb->wrpt >= rb->capacity)
4528 rb->wrpt %= rb->capacity;
4529
4530 return true;
4531}
4532
4533/**
4534 * @brief Pushes a command into the DMUB outbox ringbuffer
4535 *
4536 * @param rb DMUB outbox ringbuffer
4537 * @param cmd Outbox command
4538 * @return true if not full
4539 * @return false otherwise
4540 */
4541static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
4542 const union dmub_rb_out_cmd *cmd)
4543{
4544 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
4545 const uint8_t *src = (const uint8_t *)cmd;
4546
4547 if (dmub_rb_full(rb))
4548 return false;
4549
4550 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
4551
4552 rb->wrpt += DMUB_RB_CMD_SIZE;
4553
4554 if (rb->wrpt >= rb->capacity)
4555 rb->wrpt %= rb->capacity;
4556
4557 return true;
4558}
4559
4560/**
4561 * @brief Returns the next unprocessed command in the ringbuffer.
4562 *
4563 * @param rb DMUB ringbuffer
4564 * @param cmd The command to return
4565 * @return true if not empty
4566 * @return false otherwise
4567 */
4568static inline bool dmub_rb_front(struct dmub_rb *rb,
4569 union dmub_rb_cmd **cmd)
4570{
4571 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
4572
4573 if (dmub_rb_empty(rb))
4574 return false;
4575
4576 *cmd = (union dmub_rb_cmd *)rb_cmd;
4577
4578 return true;
4579}
4580
4581/**
4582 * @brief Determines the next ringbuffer offset.
4583 *
4584 * @param rb DMUB inbox ringbuffer
4585 * @param num_cmds Number of commands
4586 * @param next_rptr The next offset in the ringbuffer
4587 */
4588static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
4589 uint32_t num_cmds,
4590 uint32_t *next_rptr)
4591{
4592 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
4593
4594 if (*next_rptr >= rb->capacity)
4595 *next_rptr %= rb->capacity;
4596}
4597
4598/**
4599 * @brief Returns a pointer to a command in the inbox.
4600 *
4601 * @param rb DMUB inbox ringbuffer
4602 * @param cmd The inbox command to return
4603 * @param rptr The ringbuffer offset
4604 * @return true if not empty
4605 * @return false otherwise
4606 */
4607static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
4608 union dmub_rb_cmd **cmd,
4609 uint32_t rptr)
4610{
4611 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
4612
4613 if (dmub_rb_empty(rb))
4614 return false;
4615
4616 *cmd = (union dmub_rb_cmd *)rb_cmd;
4617
4618 return true;
4619}
4620
4621/**
4622 * @brief Returns the next unprocessed command in the outbox.
4623 *
4624 * @param rb DMUB outbox ringbuffer
4625 * @param cmd The outbox command to return
4626 * @return true if not empty
4627 * @return false otherwise
4628 */
4629static inline bool dmub_rb_out_front(struct dmub_rb *rb,
4630 union dmub_rb_out_cmd *cmd)
4631{
4632 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
4633 uint64_t *dst = (uint64_t *)cmd;
4634 uint8_t i;
4635
4636 if (dmub_rb_empty(rb))
4637 return false;
4638
4639 // copying data
4640 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4641 *dst++ = *src++;
4642
4643 return true;
4644}
4645
4646/**
4647 * @brief Removes the front entry in the ringbuffer.
4648 *
4649 * @param rb DMUB ringbuffer
4650 * @return true if the command was removed
4651 * @return false if there were no commands
4652 */
4653static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
4654{
4655 if (dmub_rb_empty(rb))
4656 return false;
4657
4658 rb->rptr += DMUB_RB_CMD_SIZE;
4659
4660 if (rb->rptr >= rb->capacity)
4661 rb->rptr %= rb->capacity;
4662
4663 return true;
4664}
4665
4666/**
4667 * @brief Flushes commands in the ringbuffer to framebuffer memory.
4668 *
4669 * Avoids a race condition where DMCUB accesses memory while
4670 * there are still writes in flight to framebuffer.
4671 *
4672 * @param rb DMUB ringbuffer
4673 */
4674static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
4675{
4676 uint32_t rptr = rb->rptr;
4677 uint32_t wptr = rb->wrpt;
4678
4679 while (rptr != wptr) {
4680 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
4681 uint8_t i;
4682
4683 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4684 (void)READ_ONCE(*data++);
4685
4686 rptr += DMUB_RB_CMD_SIZE;
4687 if (rptr >= rb->capacity)
4688 rptr %= rb->capacity;
4689 }
4690}
4691
4692/**
4693 * @brief Initializes a DMCUB ringbuffer
4694 *
4695 * @param rb DMUB ringbuffer
4696 * @param init_params initial configuration for the ringbuffer
4697 */
4698static inline void dmub_rb_init(struct dmub_rb *rb,
4699 struct dmub_rb_init_params *init_params)
4700{
4701 rb->base_address = init_params->base_address;
4702 rb->capacity = init_params->capacity;
4703 rb->rptr = init_params->read_ptr;
4704 rb->wrpt = init_params->write_ptr;
4705}
4706
4707/**
4708 * @brief Copies output data from in/out commands into the given command.
4709 *
4710 * @param rb DMUB ringbuffer
4711 * @param cmd Command to copy data into
4712 */
4713static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
4714 union dmub_rb_cmd *cmd)
4715{
4716 // Copy rb entry back into command
4717 uint8_t *rd_ptr = (rb->rptr == 0) ?
4718 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
4719 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
4720
4721 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
4722}
4723
4724#if defined(__cplusplus)
4725}
4726#endif
4727
4728//==============================================================================
4729//</DMUB_RB>====================================================================
4730//==============================================================================
4731#endif /* _DMUB_CMD_H_ */