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1/*
2 * Dynamic DMA mapping support for AMD Hammer.
3 *
4 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
5 * This allows to use PCI devices that only support 32bit addresses on systems
6 * with more than 4GB.
7 *
8 * See Documentation/PCI/PCI-DMA-mapping.txt for the interface specification.
9 *
10 * Copyright 2002 Andi Kleen, SuSE Labs.
11 * Subject to the GNU General Public License v2 only.
12 */
13
14#include <linux/types.h>
15#include <linux/ctype.h>
16#include <linux/agp_backend.h>
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/sched.h>
20#include <linux/string.h>
21#include <linux/spinlock.h>
22#include <linux/pci.h>
23#include <linux/module.h>
24#include <linux/topology.h>
25#include <linux/interrupt.h>
26#include <linux/bitmap.h>
27#include <linux/kdebug.h>
28#include <linux/scatterlist.h>
29#include <linux/iommu-helper.h>
30#include <linux/syscore_ops.h>
31#include <linux/io.h>
32#include <linux/gfp.h>
33#include <linux/atomic.h>
34#include <asm/mtrr.h>
35#include <asm/pgtable.h>
36#include <asm/proto.h>
37#include <asm/iommu.h>
38#include <asm/gart.h>
39#include <asm/cacheflush.h>
40#include <asm/swiotlb.h>
41#include <asm/dma.h>
42#include <asm/amd_nb.h>
43#include <asm/x86_init.h>
44#include <asm/iommu_table.h>
45
46static unsigned long iommu_bus_base; /* GART remapping area (physical) */
47static unsigned long iommu_size; /* size of remapping area bytes */
48static unsigned long iommu_pages; /* .. and in pages */
49
50static u32 *iommu_gatt_base; /* Remapping table */
51
52static dma_addr_t bad_dma_addr;
53
54/*
55 * If this is disabled the IOMMU will use an optimized flushing strategy
56 * of only flushing when an mapping is reused. With it true the GART is
57 * flushed for every mapping. Problem is that doing the lazy flush seems
58 * to trigger bugs with some popular PCI cards, in particular 3ware (but
59 * has been also also seen with Qlogic at least).
60 */
61static int iommu_fullflush = 1;
62
63/* Allocation bitmap for the remapping area: */
64static DEFINE_SPINLOCK(iommu_bitmap_lock);
65/* Guarded by iommu_bitmap_lock: */
66static unsigned long *iommu_gart_bitmap;
67
68static u32 gart_unmapped_entry;
69
70#define GPTE_VALID 1
71#define GPTE_COHERENT 2
72#define GPTE_ENCODE(x) \
73 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
74#define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
75
76#define EMERGENCY_PAGES 32 /* = 128KB */
77
78#ifdef CONFIG_AGP
79#define AGPEXTERN extern
80#else
81#define AGPEXTERN
82#endif
83
84/* GART can only remap to physical addresses < 1TB */
85#define GART_MAX_PHYS_ADDR (1ULL << 40)
86
87/* backdoor interface to AGP driver */
88AGPEXTERN int agp_memory_reserved;
89AGPEXTERN __u32 *agp_gatt_table;
90
91static unsigned long next_bit; /* protected by iommu_bitmap_lock */
92static bool need_flush; /* global flush state. set for each gart wrap */
93
94static unsigned long alloc_iommu(struct device *dev, int size,
95 unsigned long align_mask)
96{
97 unsigned long offset, flags;
98 unsigned long boundary_size;
99 unsigned long base_index;
100
101 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
102 PAGE_SIZE) >> PAGE_SHIFT;
103 boundary_size = ALIGN((u64)dma_get_seg_boundary(dev) + 1,
104 PAGE_SIZE) >> PAGE_SHIFT;
105
106 spin_lock_irqsave(&iommu_bitmap_lock, flags);
107 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
108 size, base_index, boundary_size, align_mask);
109 if (offset == -1) {
110 need_flush = true;
111 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
112 size, base_index, boundary_size,
113 align_mask);
114 }
115 if (offset != -1) {
116 next_bit = offset+size;
117 if (next_bit >= iommu_pages) {
118 next_bit = 0;
119 need_flush = true;
120 }
121 }
122 if (iommu_fullflush)
123 need_flush = true;
124 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
125
126 return offset;
127}
128
129static void free_iommu(unsigned long offset, int size)
130{
131 unsigned long flags;
132
133 spin_lock_irqsave(&iommu_bitmap_lock, flags);
134 bitmap_clear(iommu_gart_bitmap, offset, size);
135 if (offset >= next_bit)
136 next_bit = offset + size;
137 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
138}
139
140/*
141 * Use global flush state to avoid races with multiple flushers.
142 */
143static void flush_gart(void)
144{
145 unsigned long flags;
146
147 spin_lock_irqsave(&iommu_bitmap_lock, flags);
148 if (need_flush) {
149 amd_flush_garts();
150 need_flush = false;
151 }
152 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
153}
154
155#ifdef CONFIG_IOMMU_LEAK
156/* Debugging aid for drivers that don't free their IOMMU tables */
157static int leak_trace;
158static int iommu_leak_pages = 20;
159
160static void dump_leak(void)
161{
162 static int dump;
163
164 if (dump)
165 return;
166 dump = 1;
167
168 show_stack(NULL, NULL);
169 debug_dma_dump_mappings(NULL);
170}
171#endif
172
173static void iommu_full(struct device *dev, size_t size, int dir)
174{
175 /*
176 * Ran out of IOMMU space for this operation. This is very bad.
177 * Unfortunately the drivers cannot handle this operation properly.
178 * Return some non mapped prereserved space in the aperture and
179 * let the Northbridge deal with it. This will result in garbage
180 * in the IO operation. When the size exceeds the prereserved space
181 * memory corruption will occur or random memory will be DMAed
182 * out. Hopefully no network devices use single mappings that big.
183 */
184
185 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
186
187 if (size > PAGE_SIZE*EMERGENCY_PAGES) {
188 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
189 panic("PCI-DMA: Memory would be corrupted\n");
190 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
191 panic(KERN_ERR
192 "PCI-DMA: Random memory would be DMAed\n");
193 }
194#ifdef CONFIG_IOMMU_LEAK
195 dump_leak();
196#endif
197}
198
199static inline int
200need_iommu(struct device *dev, unsigned long addr, size_t size)
201{
202 return force_iommu || !dma_capable(dev, addr, size);
203}
204
205static inline int
206nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
207{
208 return !dma_capable(dev, addr, size);
209}
210
211/* Map a single continuous physical area into the IOMMU.
212 * Caller needs to check if the iommu is needed and flush.
213 */
214static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
215 size_t size, int dir, unsigned long align_mask)
216{
217 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
218 unsigned long iommu_page;
219 int i;
220
221 if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR))
222 return bad_dma_addr;
223
224 iommu_page = alloc_iommu(dev, npages, align_mask);
225 if (iommu_page == -1) {
226 if (!nonforced_iommu(dev, phys_mem, size))
227 return phys_mem;
228 if (panic_on_overflow)
229 panic("dma_map_area overflow %lu bytes\n", size);
230 iommu_full(dev, size, dir);
231 return bad_dma_addr;
232 }
233
234 for (i = 0; i < npages; i++) {
235 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
236 phys_mem += PAGE_SIZE;
237 }
238 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
239}
240
241/* Map a single area into the IOMMU */
242static dma_addr_t gart_map_page(struct device *dev, struct page *page,
243 unsigned long offset, size_t size,
244 enum dma_data_direction dir,
245 struct dma_attrs *attrs)
246{
247 unsigned long bus;
248 phys_addr_t paddr = page_to_phys(page) + offset;
249
250 if (!dev)
251 dev = &x86_dma_fallback_dev;
252
253 if (!need_iommu(dev, paddr, size))
254 return paddr;
255
256 bus = dma_map_area(dev, paddr, size, dir, 0);
257 flush_gart();
258
259 return bus;
260}
261
262/*
263 * Free a DMA mapping.
264 */
265static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
266 size_t size, enum dma_data_direction dir,
267 struct dma_attrs *attrs)
268{
269 unsigned long iommu_page;
270 int npages;
271 int i;
272
273 if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
274 dma_addr >= iommu_bus_base + iommu_size)
275 return;
276
277 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
278 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
279 for (i = 0; i < npages; i++) {
280 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
281 }
282 free_iommu(iommu_page, npages);
283}
284
285/*
286 * Wrapper for pci_unmap_single working with scatterlists.
287 */
288static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
289 enum dma_data_direction dir, struct dma_attrs *attrs)
290{
291 struct scatterlist *s;
292 int i;
293
294 for_each_sg(sg, s, nents, i) {
295 if (!s->dma_length || !s->length)
296 break;
297 gart_unmap_page(dev, s->dma_address, s->dma_length, dir, NULL);
298 }
299}
300
301/* Fallback for dma_map_sg in case of overflow */
302static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
303 int nents, int dir)
304{
305 struct scatterlist *s;
306 int i;
307
308#ifdef CONFIG_IOMMU_DEBUG
309 pr_debug("dma_map_sg overflow\n");
310#endif
311
312 for_each_sg(sg, s, nents, i) {
313 unsigned long addr = sg_phys(s);
314
315 if (nonforced_iommu(dev, addr, s->length)) {
316 addr = dma_map_area(dev, addr, s->length, dir, 0);
317 if (addr == bad_dma_addr) {
318 if (i > 0)
319 gart_unmap_sg(dev, sg, i, dir, NULL);
320 nents = 0;
321 sg[0].dma_length = 0;
322 break;
323 }
324 }
325 s->dma_address = addr;
326 s->dma_length = s->length;
327 }
328 flush_gart();
329
330 return nents;
331}
332
333/* Map multiple scatterlist entries continuous into the first. */
334static int __dma_map_cont(struct device *dev, struct scatterlist *start,
335 int nelems, struct scatterlist *sout,
336 unsigned long pages)
337{
338 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
339 unsigned long iommu_page = iommu_start;
340 struct scatterlist *s;
341 int i;
342
343 if (iommu_start == -1)
344 return -1;
345
346 for_each_sg(start, s, nelems, i) {
347 unsigned long pages, addr;
348 unsigned long phys_addr = s->dma_address;
349
350 BUG_ON(s != start && s->offset);
351 if (s == start) {
352 sout->dma_address = iommu_bus_base;
353 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
354 sout->dma_length = s->length;
355 } else {
356 sout->dma_length += s->length;
357 }
358
359 addr = phys_addr;
360 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
361 while (pages--) {
362 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
363 addr += PAGE_SIZE;
364 iommu_page++;
365 }
366 }
367 BUG_ON(iommu_page - iommu_start != pages);
368
369 return 0;
370}
371
372static inline int
373dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
374 struct scatterlist *sout, unsigned long pages, int need)
375{
376 if (!need) {
377 BUG_ON(nelems != 1);
378 sout->dma_address = start->dma_address;
379 sout->dma_length = start->length;
380 return 0;
381 }
382 return __dma_map_cont(dev, start, nelems, sout, pages);
383}
384
385/*
386 * DMA map all entries in a scatterlist.
387 * Merge chunks that have page aligned sizes into a continuous mapping.
388 */
389static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
390 enum dma_data_direction dir, struct dma_attrs *attrs)
391{
392 struct scatterlist *s, *ps, *start_sg, *sgmap;
393 int need = 0, nextneed, i, out, start;
394 unsigned long pages = 0;
395 unsigned int seg_size;
396 unsigned int max_seg_size;
397
398 if (nents == 0)
399 return 0;
400
401 if (!dev)
402 dev = &x86_dma_fallback_dev;
403
404 out = 0;
405 start = 0;
406 start_sg = sg;
407 sgmap = sg;
408 seg_size = 0;
409 max_seg_size = dma_get_max_seg_size(dev);
410 ps = NULL; /* shut up gcc */
411
412 for_each_sg(sg, s, nents, i) {
413 dma_addr_t addr = sg_phys(s);
414
415 s->dma_address = addr;
416 BUG_ON(s->length == 0);
417
418 nextneed = need_iommu(dev, addr, s->length);
419
420 /* Handle the previous not yet processed entries */
421 if (i > start) {
422 /*
423 * Can only merge when the last chunk ends on a
424 * page boundary and the new one doesn't have an
425 * offset.
426 */
427 if (!iommu_merge || !nextneed || !need || s->offset ||
428 (s->length + seg_size > max_seg_size) ||
429 (ps->offset + ps->length) % PAGE_SIZE) {
430 if (dma_map_cont(dev, start_sg, i - start,
431 sgmap, pages, need) < 0)
432 goto error;
433 out++;
434
435 seg_size = 0;
436 sgmap = sg_next(sgmap);
437 pages = 0;
438 start = i;
439 start_sg = s;
440 }
441 }
442
443 seg_size += s->length;
444 need = nextneed;
445 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
446 ps = s;
447 }
448 if (dma_map_cont(dev, start_sg, i - start, sgmap, pages, need) < 0)
449 goto error;
450 out++;
451 flush_gart();
452 if (out < nents) {
453 sgmap = sg_next(sgmap);
454 sgmap->dma_length = 0;
455 }
456 return out;
457
458error:
459 flush_gart();
460 gart_unmap_sg(dev, sg, out, dir, NULL);
461
462 /* When it was forced or merged try again in a dumb way */
463 if (force_iommu || iommu_merge) {
464 out = dma_map_sg_nonforce(dev, sg, nents, dir);
465 if (out > 0)
466 return out;
467 }
468 if (panic_on_overflow)
469 panic("dma_map_sg: overflow on %lu pages\n", pages);
470
471 iommu_full(dev, pages << PAGE_SHIFT, dir);
472 for_each_sg(sg, s, nents, i)
473 s->dma_address = bad_dma_addr;
474 return 0;
475}
476
477/* allocate and map a coherent mapping */
478static void *
479gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
480 gfp_t flag)
481{
482 dma_addr_t paddr;
483 unsigned long align_mask;
484 struct page *page;
485
486 if (force_iommu && !(flag & GFP_DMA)) {
487 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
488 page = alloc_pages(flag | __GFP_ZERO, get_order(size));
489 if (!page)
490 return NULL;
491
492 align_mask = (1UL << get_order(size)) - 1;
493 paddr = dma_map_area(dev, page_to_phys(page), size,
494 DMA_BIDIRECTIONAL, align_mask);
495
496 flush_gart();
497 if (paddr != bad_dma_addr) {
498 *dma_addr = paddr;
499 return page_address(page);
500 }
501 __free_pages(page, get_order(size));
502 } else
503 return dma_generic_alloc_coherent(dev, size, dma_addr, flag);
504
505 return NULL;
506}
507
508/* free a coherent mapping */
509static void
510gart_free_coherent(struct device *dev, size_t size, void *vaddr,
511 dma_addr_t dma_addr)
512{
513 gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, NULL);
514 free_pages((unsigned long)vaddr, get_order(size));
515}
516
517static int gart_mapping_error(struct device *dev, dma_addr_t dma_addr)
518{
519 return (dma_addr == bad_dma_addr);
520}
521
522static int no_agp;
523
524static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
525{
526 unsigned long a;
527
528 if (!iommu_size) {
529 iommu_size = aper_size;
530 if (!no_agp)
531 iommu_size /= 2;
532 }
533
534 a = aper + iommu_size;
535 iommu_size -= round_up(a, PMD_PAGE_SIZE) - a;
536
537 if (iommu_size < 64*1024*1024) {
538 pr_warning(
539 "PCI-DMA: Warning: Small IOMMU %luMB."
540 " Consider increasing the AGP aperture in BIOS\n",
541 iommu_size >> 20);
542 }
543
544 return iommu_size;
545}
546
547static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
548{
549 unsigned aper_size = 0, aper_base_32, aper_order;
550 u64 aper_base;
551
552 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
553 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
554 aper_order = (aper_order >> 1) & 7;
555
556 aper_base = aper_base_32 & 0x7fff;
557 aper_base <<= 25;
558
559 aper_size = (32 * 1024 * 1024) << aper_order;
560 if (aper_base + aper_size > 0x100000000UL || !aper_size)
561 aper_base = 0;
562
563 *size = aper_size;
564 return aper_base;
565}
566
567static void enable_gart_translations(void)
568{
569 int i;
570
571 if (!amd_nb_has_feature(AMD_NB_GART))
572 return;
573
574 for (i = 0; i < amd_nb_num(); i++) {
575 struct pci_dev *dev = node_to_amd_nb(i)->misc;
576
577 enable_gart_translation(dev, __pa(agp_gatt_table));
578 }
579
580 /* Flush the GART-TLB to remove stale entries */
581 amd_flush_garts();
582}
583
584/*
585 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
586 * resume in the same way as they are handled in gart_iommu_hole_init().
587 */
588static bool fix_up_north_bridges;
589static u32 aperture_order;
590static u32 aperture_alloc;
591
592void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
593{
594 fix_up_north_bridges = true;
595 aperture_order = aper_order;
596 aperture_alloc = aper_alloc;
597}
598
599static void gart_fixup_northbridges(void)
600{
601 int i;
602
603 if (!fix_up_north_bridges)
604 return;
605
606 if (!amd_nb_has_feature(AMD_NB_GART))
607 return;
608
609 pr_info("PCI-DMA: Restoring GART aperture settings\n");
610
611 for (i = 0; i < amd_nb_num(); i++) {
612 struct pci_dev *dev = node_to_amd_nb(i)->misc;
613
614 /*
615 * Don't enable translations just yet. That is the next
616 * step. Restore the pre-suspend aperture settings.
617 */
618 gart_set_size_and_enable(dev, aperture_order);
619 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25);
620 }
621}
622
623static void gart_resume(void)
624{
625 pr_info("PCI-DMA: Resuming GART IOMMU\n");
626
627 gart_fixup_northbridges();
628
629 enable_gart_translations();
630}
631
632static struct syscore_ops gart_syscore_ops = {
633 .resume = gart_resume,
634
635};
636
637/*
638 * Private Northbridge GATT initialization in case we cannot use the
639 * AGP driver for some reason.
640 */
641static __init int init_amd_gatt(struct agp_kern_info *info)
642{
643 unsigned aper_size, gatt_size, new_aper_size;
644 unsigned aper_base, new_aper_base;
645 struct pci_dev *dev;
646 void *gatt;
647 int i;
648
649 pr_info("PCI-DMA: Disabling AGP.\n");
650
651 aper_size = aper_base = info->aper_size = 0;
652 dev = NULL;
653 for (i = 0; i < amd_nb_num(); i++) {
654 dev = node_to_amd_nb(i)->misc;
655 new_aper_base = read_aperture(dev, &new_aper_size);
656 if (!new_aper_base)
657 goto nommu;
658
659 if (!aper_base) {
660 aper_size = new_aper_size;
661 aper_base = new_aper_base;
662 }
663 if (aper_size != new_aper_size || aper_base != new_aper_base)
664 goto nommu;
665 }
666 if (!aper_base)
667 goto nommu;
668
669 info->aper_base = aper_base;
670 info->aper_size = aper_size >> 20;
671
672 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
673 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
674 get_order(gatt_size));
675 if (!gatt)
676 panic("Cannot allocate GATT table");
677 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
678 panic("Could not set GART PTEs to uncacheable pages");
679
680 agp_gatt_table = gatt;
681
682 register_syscore_ops(&gart_syscore_ops);
683
684 flush_gart();
685
686 pr_info("PCI-DMA: aperture base @ %x size %u KB\n",
687 aper_base, aper_size>>10);
688
689 return 0;
690
691 nommu:
692 /* Should not happen anymore */
693 pr_warning("PCI-DMA: More than 4GB of RAM and no IOMMU\n"
694 "falling back to iommu=soft.\n");
695 return -1;
696}
697
698static struct dma_map_ops gart_dma_ops = {
699 .map_sg = gart_map_sg,
700 .unmap_sg = gart_unmap_sg,
701 .map_page = gart_map_page,
702 .unmap_page = gart_unmap_page,
703 .alloc_coherent = gart_alloc_coherent,
704 .free_coherent = gart_free_coherent,
705 .mapping_error = gart_mapping_error,
706};
707
708static void gart_iommu_shutdown(void)
709{
710 struct pci_dev *dev;
711 int i;
712
713 /* don't shutdown it if there is AGP installed */
714 if (!no_agp)
715 return;
716
717 if (!amd_nb_has_feature(AMD_NB_GART))
718 return;
719
720 for (i = 0; i < amd_nb_num(); i++) {
721 u32 ctl;
722
723 dev = node_to_amd_nb(i)->misc;
724 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
725
726 ctl &= ~GARTEN;
727
728 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
729 }
730}
731
732int __init gart_iommu_init(void)
733{
734 struct agp_kern_info info;
735 unsigned long iommu_start;
736 unsigned long aper_base, aper_size;
737 unsigned long start_pfn, end_pfn;
738 unsigned long scratch;
739 long i;
740
741 if (!amd_nb_has_feature(AMD_NB_GART))
742 return 0;
743
744#ifndef CONFIG_AGP_AMD64
745 no_agp = 1;
746#else
747 /* Makefile puts PCI initialization via subsys_initcall first. */
748 /* Add other AMD AGP bridge drivers here */
749 no_agp = no_agp ||
750 (agp_amd64_init() < 0) ||
751 (agp_copy_info(agp_bridge, &info) < 0);
752#endif
753
754 if (no_iommu ||
755 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
756 !gart_iommu_aperture ||
757 (no_agp && init_amd_gatt(&info) < 0)) {
758 if (max_pfn > MAX_DMA32_PFN) {
759 pr_warning("More than 4GB of memory but GART IOMMU not available.\n");
760 pr_warning("falling back to iommu=soft.\n");
761 }
762 return 0;
763 }
764
765 /* need to map that range */
766 aper_size = info.aper_size << 20;
767 aper_base = info.aper_base;
768 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
769
770 if (end_pfn > max_low_pfn_mapped) {
771 start_pfn = (aper_base>>PAGE_SHIFT);
772 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
773 }
774
775 pr_info("PCI-DMA: using GART IOMMU.\n");
776 iommu_size = check_iommu_size(info.aper_base, aper_size);
777 iommu_pages = iommu_size >> PAGE_SHIFT;
778
779 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
780 get_order(iommu_pages/8));
781 if (!iommu_gart_bitmap)
782 panic("Cannot allocate iommu bitmap\n");
783
784#ifdef CONFIG_IOMMU_LEAK
785 if (leak_trace) {
786 int ret;
787
788 ret = dma_debug_resize_entries(iommu_pages);
789 if (ret)
790 pr_debug("PCI-DMA: Cannot trace all the entries\n");
791 }
792#endif
793
794 /*
795 * Out of IOMMU space handling.
796 * Reserve some invalid pages at the beginning of the GART.
797 */
798 bitmap_set(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
799
800 pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
801 iommu_size >> 20);
802
803 agp_memory_reserved = iommu_size;
804 iommu_start = aper_size - iommu_size;
805 iommu_bus_base = info.aper_base + iommu_start;
806 bad_dma_addr = iommu_bus_base;
807 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
808
809 /*
810 * Unmap the IOMMU part of the GART. The alias of the page is
811 * always mapped with cache enabled and there is no full cache
812 * coherency across the GART remapping. The unmapping avoids
813 * automatic prefetches from the CPU allocating cache lines in
814 * there. All CPU accesses are done via the direct mapping to
815 * the backing memory. The GART address is only used by PCI
816 * devices.
817 */
818 set_memory_np((unsigned long)__va(iommu_bus_base),
819 iommu_size >> PAGE_SHIFT);
820 /*
821 * Tricky. The GART table remaps the physical memory range,
822 * so the CPU wont notice potential aliases and if the memory
823 * is remapped to UC later on, we might surprise the PCI devices
824 * with a stray writeout of a cacheline. So play it sure and
825 * do an explicit, full-scale wbinvd() _after_ having marked all
826 * the pages as Not-Present:
827 */
828 wbinvd();
829
830 /*
831 * Now all caches are flushed and we can safely enable
832 * GART hardware. Doing it early leaves the possibility
833 * of stale cache entries that can lead to GART PTE
834 * errors.
835 */
836 enable_gart_translations();
837
838 /*
839 * Try to workaround a bug (thanks to BenH):
840 * Set unmapped entries to a scratch page instead of 0.
841 * Any prefetches that hit unmapped entries won't get an bus abort
842 * then. (P2P bridge may be prefetching on DMA reads).
843 */
844 scratch = get_zeroed_page(GFP_KERNEL);
845 if (!scratch)
846 panic("Cannot allocate iommu scratch page");
847 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
848 for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
849 iommu_gatt_base[i] = gart_unmapped_entry;
850
851 flush_gart();
852 dma_ops = &gart_dma_ops;
853 x86_platform.iommu_shutdown = gart_iommu_shutdown;
854 swiotlb = 0;
855
856 return 0;
857}
858
859void __init gart_parse_options(char *p)
860{
861 int arg;
862
863#ifdef CONFIG_IOMMU_LEAK
864 if (!strncmp(p, "leak", 4)) {
865 leak_trace = 1;
866 p += 4;
867 if (*p == '=')
868 ++p;
869 if (isdigit(*p) && get_option(&p, &arg))
870 iommu_leak_pages = arg;
871 }
872#endif
873 if (isdigit(*p) && get_option(&p, &arg))
874 iommu_size = arg;
875 if (!strncmp(p, "fullflush", 9))
876 iommu_fullflush = 1;
877 if (!strncmp(p, "nofullflush", 11))
878 iommu_fullflush = 0;
879 if (!strncmp(p, "noagp", 5))
880 no_agp = 1;
881 if (!strncmp(p, "noaperture", 10))
882 fix_aperture = 0;
883 /* duplicated from pci-dma.c */
884 if (!strncmp(p, "force", 5))
885 gart_iommu_aperture_allowed = 1;
886 if (!strncmp(p, "allowed", 7))
887 gart_iommu_aperture_allowed = 1;
888 if (!strncmp(p, "memaper", 7)) {
889 fallback_aper_force = 1;
890 p += 7;
891 if (*p == '=') {
892 ++p;
893 if (get_option(&p, &arg))
894 fallback_aper_order = arg;
895 }
896 }
897}
898IOMMU_INIT_POST(gart_iommu_hole_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Dynamic DMA mapping support for AMD Hammer.
4 *
5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
6 * This allows to use PCI devices that only support 32bit addresses on systems
7 * with more than 4GB.
8 *
9 * See Documentation/core-api/dma-api-howto.rst for the interface specification.
10 *
11 * Copyright 2002 Andi Kleen, SuSE Labs.
12 */
13
14#include <linux/types.h>
15#include <linux/ctype.h>
16#include <linux/agp_backend.h>
17#include <linux/init.h>
18#include <linux/mm.h>
19#include <linux/sched.h>
20#include <linux/sched/debug.h>
21#include <linux/string.h>
22#include <linux/spinlock.h>
23#include <linux/pci.h>
24#include <linux/topology.h>
25#include <linux/interrupt.h>
26#include <linux/bitmap.h>
27#include <linux/kdebug.h>
28#include <linux/scatterlist.h>
29#include <linux/iommu-helper.h>
30#include <linux/syscore_ops.h>
31#include <linux/io.h>
32#include <linux/gfp.h>
33#include <linux/atomic.h>
34#include <linux/dma-direct.h>
35#include <linux/dma-map-ops.h>
36#include <asm/mtrr.h>
37#include <asm/proto.h>
38#include <asm/iommu.h>
39#include <asm/gart.h>
40#include <asm/set_memory.h>
41#include <asm/dma.h>
42#include <asm/amd_nb.h>
43#include <asm/x86_init.h>
44
45static unsigned long iommu_bus_base; /* GART remapping area (physical) */
46static unsigned long iommu_size; /* size of remapping area bytes */
47static unsigned long iommu_pages; /* .. and in pages */
48
49static u32 *iommu_gatt_base; /* Remapping table */
50
51/*
52 * If this is disabled the IOMMU will use an optimized flushing strategy
53 * of only flushing when an mapping is reused. With it true the GART is
54 * flushed for every mapping. Problem is that doing the lazy flush seems
55 * to trigger bugs with some popular PCI cards, in particular 3ware (but
56 * has been also seen with Qlogic at least).
57 */
58static int iommu_fullflush = 1;
59
60/* Allocation bitmap for the remapping area: */
61static DEFINE_SPINLOCK(iommu_bitmap_lock);
62/* Guarded by iommu_bitmap_lock: */
63static unsigned long *iommu_gart_bitmap;
64
65static u32 gart_unmapped_entry;
66
67#define GPTE_VALID 1
68#define GPTE_COHERENT 2
69#define GPTE_ENCODE(x) \
70 (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
71#define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
72
73#ifdef CONFIG_AGP
74#define AGPEXTERN extern
75#else
76#define AGPEXTERN
77#endif
78
79/* GART can only remap to physical addresses < 1TB */
80#define GART_MAX_PHYS_ADDR (1ULL << 40)
81
82/* backdoor interface to AGP driver */
83AGPEXTERN int agp_memory_reserved;
84AGPEXTERN __u32 *agp_gatt_table;
85
86static unsigned long next_bit; /* protected by iommu_bitmap_lock */
87static bool need_flush; /* global flush state. set for each gart wrap */
88
89static unsigned long alloc_iommu(struct device *dev, int size,
90 unsigned long align_mask)
91{
92 unsigned long offset, flags;
93 unsigned long boundary_size;
94 unsigned long base_index;
95
96 base_index = ALIGN(iommu_bus_base & dma_get_seg_boundary(dev),
97 PAGE_SIZE) >> PAGE_SHIFT;
98 boundary_size = dma_get_seg_boundary_nr_pages(dev, PAGE_SHIFT);
99
100 spin_lock_irqsave(&iommu_bitmap_lock, flags);
101 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, next_bit,
102 size, base_index, boundary_size, align_mask);
103 if (offset == -1) {
104 need_flush = true;
105 offset = iommu_area_alloc(iommu_gart_bitmap, iommu_pages, 0,
106 size, base_index, boundary_size,
107 align_mask);
108 }
109 if (offset != -1) {
110 next_bit = offset+size;
111 if (next_bit >= iommu_pages) {
112 next_bit = 0;
113 need_flush = true;
114 }
115 }
116 if (iommu_fullflush)
117 need_flush = true;
118 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
119
120 return offset;
121}
122
123static void free_iommu(unsigned long offset, int size)
124{
125 unsigned long flags;
126
127 spin_lock_irqsave(&iommu_bitmap_lock, flags);
128 bitmap_clear(iommu_gart_bitmap, offset, size);
129 if (offset >= next_bit)
130 next_bit = offset + size;
131 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
132}
133
134/*
135 * Use global flush state to avoid races with multiple flushers.
136 */
137static void flush_gart(void)
138{
139 unsigned long flags;
140
141 spin_lock_irqsave(&iommu_bitmap_lock, flags);
142 if (need_flush) {
143 amd_flush_garts();
144 need_flush = false;
145 }
146 spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
147}
148
149#ifdef CONFIG_IOMMU_LEAK
150/* Debugging aid for drivers that don't free their IOMMU tables */
151static void dump_leak(void)
152{
153 static int dump;
154
155 if (dump)
156 return;
157 dump = 1;
158
159 show_stack(NULL, NULL, KERN_ERR);
160 debug_dma_dump_mappings(NULL);
161}
162#endif
163
164static void iommu_full(struct device *dev, size_t size, int dir)
165{
166 /*
167 * Ran out of IOMMU space for this operation. This is very bad.
168 * Unfortunately the drivers cannot handle this operation properly.
169 * Return some non mapped prereserved space in the aperture and
170 * let the Northbridge deal with it. This will result in garbage
171 * in the IO operation. When the size exceeds the prereserved space
172 * memory corruption will occur or random memory will be DMAed
173 * out. Hopefully no network devices use single mappings that big.
174 */
175
176 dev_err(dev, "PCI-DMA: Out of IOMMU space for %lu bytes\n", size);
177#ifdef CONFIG_IOMMU_LEAK
178 dump_leak();
179#endif
180}
181
182static inline int
183need_iommu(struct device *dev, unsigned long addr, size_t size)
184{
185 return force_iommu || !dma_capable(dev, addr, size, true);
186}
187
188static inline int
189nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
190{
191 return !dma_capable(dev, addr, size, true);
192}
193
194/* Map a single continuous physical area into the IOMMU.
195 * Caller needs to check if the iommu is needed and flush.
196 */
197static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
198 size_t size, int dir, unsigned long align_mask)
199{
200 unsigned long npages = iommu_num_pages(phys_mem, size, PAGE_SIZE);
201 unsigned long iommu_page;
202 int i;
203
204 if (unlikely(phys_mem + size > GART_MAX_PHYS_ADDR))
205 return DMA_MAPPING_ERROR;
206
207 iommu_page = alloc_iommu(dev, npages, align_mask);
208 if (iommu_page == -1) {
209 if (!nonforced_iommu(dev, phys_mem, size))
210 return phys_mem;
211 if (panic_on_overflow)
212 panic("dma_map_area overflow %lu bytes\n", size);
213 iommu_full(dev, size, dir);
214 return DMA_MAPPING_ERROR;
215 }
216
217 for (i = 0; i < npages; i++) {
218 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
219 phys_mem += PAGE_SIZE;
220 }
221 return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
222}
223
224/* Map a single area into the IOMMU */
225static dma_addr_t gart_map_page(struct device *dev, struct page *page,
226 unsigned long offset, size_t size,
227 enum dma_data_direction dir,
228 unsigned long attrs)
229{
230 unsigned long bus;
231 phys_addr_t paddr = page_to_phys(page) + offset;
232
233 if (!need_iommu(dev, paddr, size))
234 return paddr;
235
236 bus = dma_map_area(dev, paddr, size, dir, 0);
237 flush_gart();
238
239 return bus;
240}
241
242/*
243 * Free a DMA mapping.
244 */
245static void gart_unmap_page(struct device *dev, dma_addr_t dma_addr,
246 size_t size, enum dma_data_direction dir,
247 unsigned long attrs)
248{
249 unsigned long iommu_page;
250 int npages;
251 int i;
252
253 if (WARN_ON_ONCE(dma_addr == DMA_MAPPING_ERROR))
254 return;
255
256 /*
257 * This driver will not always use a GART mapping, but might have
258 * created a direct mapping instead. If that is the case there is
259 * nothing to unmap here.
260 */
261 if (dma_addr < iommu_bus_base ||
262 dma_addr >= iommu_bus_base + iommu_size)
263 return;
264
265 iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
266 npages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
267 for (i = 0; i < npages; i++) {
268 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
269 }
270 free_iommu(iommu_page, npages);
271}
272
273/*
274 * Wrapper for pci_unmap_single working with scatterlists.
275 */
276static void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
277 enum dma_data_direction dir, unsigned long attrs)
278{
279 struct scatterlist *s;
280 int i;
281
282 for_each_sg(sg, s, nents, i) {
283 if (!s->dma_length || !s->length)
284 break;
285 gart_unmap_page(dev, s->dma_address, s->dma_length, dir, 0);
286 }
287}
288
289/* Fallback for dma_map_sg in case of overflow */
290static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
291 int nents, int dir)
292{
293 struct scatterlist *s;
294 int i;
295
296#ifdef CONFIG_IOMMU_DEBUG
297 pr_debug("dma_map_sg overflow\n");
298#endif
299
300 for_each_sg(sg, s, nents, i) {
301 unsigned long addr = sg_phys(s);
302
303 if (nonforced_iommu(dev, addr, s->length)) {
304 addr = dma_map_area(dev, addr, s->length, dir, 0);
305 if (addr == DMA_MAPPING_ERROR) {
306 if (i > 0)
307 gart_unmap_sg(dev, sg, i, dir, 0);
308 nents = 0;
309 sg[0].dma_length = 0;
310 break;
311 }
312 }
313 s->dma_address = addr;
314 s->dma_length = s->length;
315 }
316 flush_gart();
317
318 return nents;
319}
320
321/* Map multiple scatterlist entries continuous into the first. */
322static int __dma_map_cont(struct device *dev, struct scatterlist *start,
323 int nelems, struct scatterlist *sout,
324 unsigned long pages)
325{
326 unsigned long iommu_start = alloc_iommu(dev, pages, 0);
327 unsigned long iommu_page = iommu_start;
328 struct scatterlist *s;
329 int i;
330
331 if (iommu_start == -1)
332 return -ENOMEM;
333
334 for_each_sg(start, s, nelems, i) {
335 unsigned long pages, addr;
336 unsigned long phys_addr = s->dma_address;
337
338 BUG_ON(s != start && s->offset);
339 if (s == start) {
340 sout->dma_address = iommu_bus_base;
341 sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
342 sout->dma_length = s->length;
343 } else {
344 sout->dma_length += s->length;
345 }
346
347 addr = phys_addr;
348 pages = iommu_num_pages(s->offset, s->length, PAGE_SIZE);
349 while (pages--) {
350 iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
351 addr += PAGE_SIZE;
352 iommu_page++;
353 }
354 }
355 BUG_ON(iommu_page - iommu_start != pages);
356
357 return 0;
358}
359
360static inline int
361dma_map_cont(struct device *dev, struct scatterlist *start, int nelems,
362 struct scatterlist *sout, unsigned long pages, int need)
363{
364 if (!need) {
365 BUG_ON(nelems != 1);
366 sout->dma_address = start->dma_address;
367 sout->dma_length = start->length;
368 return 0;
369 }
370 return __dma_map_cont(dev, start, nelems, sout, pages);
371}
372
373/*
374 * DMA map all entries in a scatterlist.
375 * Merge chunks that have page aligned sizes into a continuous mapping.
376 */
377static int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents,
378 enum dma_data_direction dir, unsigned long attrs)
379{
380 struct scatterlist *s, *ps, *start_sg, *sgmap;
381 int need = 0, nextneed, i, out, start, ret;
382 unsigned long pages = 0;
383 unsigned int seg_size;
384 unsigned int max_seg_size;
385
386 if (nents == 0)
387 return -EINVAL;
388
389 out = 0;
390 start = 0;
391 start_sg = sg;
392 sgmap = sg;
393 seg_size = 0;
394 max_seg_size = dma_get_max_seg_size(dev);
395 ps = NULL; /* shut up gcc */
396
397 for_each_sg(sg, s, nents, i) {
398 dma_addr_t addr = sg_phys(s);
399
400 s->dma_address = addr;
401 BUG_ON(s->length == 0);
402
403 nextneed = need_iommu(dev, addr, s->length);
404
405 /* Handle the previous not yet processed entries */
406 if (i > start) {
407 /*
408 * Can only merge when the last chunk ends on a
409 * page boundary and the new one doesn't have an
410 * offset.
411 */
412 if (!iommu_merge || !nextneed || !need || s->offset ||
413 (s->length + seg_size > max_seg_size) ||
414 (ps->offset + ps->length) % PAGE_SIZE) {
415 ret = dma_map_cont(dev, start_sg, i - start,
416 sgmap, pages, need);
417 if (ret < 0)
418 goto error;
419 out++;
420
421 seg_size = 0;
422 sgmap = sg_next(sgmap);
423 pages = 0;
424 start = i;
425 start_sg = s;
426 }
427 }
428
429 seg_size += s->length;
430 need = nextneed;
431 pages += iommu_num_pages(s->offset, s->length, PAGE_SIZE);
432 ps = s;
433 }
434 ret = dma_map_cont(dev, start_sg, i - start, sgmap, pages, need);
435 if (ret < 0)
436 goto error;
437 out++;
438 flush_gart();
439 if (out < nents) {
440 sgmap = sg_next(sgmap);
441 sgmap->dma_length = 0;
442 }
443 return out;
444
445error:
446 flush_gart();
447 gart_unmap_sg(dev, sg, out, dir, 0);
448
449 /* When it was forced or merged try again in a dumb way */
450 if (force_iommu || iommu_merge) {
451 out = dma_map_sg_nonforce(dev, sg, nents, dir);
452 if (out > 0)
453 return out;
454 }
455 if (panic_on_overflow)
456 panic("dma_map_sg: overflow on %lu pages\n", pages);
457
458 iommu_full(dev, pages << PAGE_SHIFT, dir);
459 return ret;
460}
461
462/* allocate and map a coherent mapping */
463static void *
464gart_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_addr,
465 gfp_t flag, unsigned long attrs)
466{
467 void *vaddr;
468
469 vaddr = dma_direct_alloc(dev, size, dma_addr, flag, attrs);
470 if (!vaddr ||
471 !force_iommu || dev->coherent_dma_mask <= DMA_BIT_MASK(24))
472 return vaddr;
473
474 *dma_addr = dma_map_area(dev, virt_to_phys(vaddr), size,
475 DMA_BIDIRECTIONAL, (1UL << get_order(size)) - 1);
476 flush_gart();
477 if (unlikely(*dma_addr == DMA_MAPPING_ERROR))
478 goto out_free;
479 return vaddr;
480out_free:
481 dma_direct_free(dev, size, vaddr, *dma_addr, attrs);
482 return NULL;
483}
484
485/* free a coherent mapping */
486static void
487gart_free_coherent(struct device *dev, size_t size, void *vaddr,
488 dma_addr_t dma_addr, unsigned long attrs)
489{
490 gart_unmap_page(dev, dma_addr, size, DMA_BIDIRECTIONAL, 0);
491 dma_direct_free(dev, size, vaddr, dma_addr, attrs);
492}
493
494static int no_agp;
495
496static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
497{
498 unsigned long a;
499
500 if (!iommu_size) {
501 iommu_size = aper_size;
502 if (!no_agp)
503 iommu_size /= 2;
504 }
505
506 a = aper + iommu_size;
507 iommu_size -= round_up(a, PMD_SIZE) - a;
508
509 if (iommu_size < 64*1024*1024) {
510 pr_warn("PCI-DMA: Warning: Small IOMMU %luMB."
511 " Consider increasing the AGP aperture in BIOS\n",
512 iommu_size >> 20);
513 }
514
515 return iommu_size;
516}
517
518static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
519{
520 unsigned aper_size = 0, aper_base_32, aper_order;
521 u64 aper_base;
522
523 pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
524 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
525 aper_order = (aper_order >> 1) & 7;
526
527 aper_base = aper_base_32 & 0x7fff;
528 aper_base <<= 25;
529
530 aper_size = (32 * 1024 * 1024) << aper_order;
531 if (aper_base + aper_size > 0x100000000UL || !aper_size)
532 aper_base = 0;
533
534 *size = aper_size;
535 return aper_base;
536}
537
538static void enable_gart_translations(void)
539{
540 int i;
541
542 if (!amd_nb_has_feature(AMD_NB_GART))
543 return;
544
545 for (i = 0; i < amd_nb_num(); i++) {
546 struct pci_dev *dev = node_to_amd_nb(i)->misc;
547
548 enable_gart_translation(dev, __pa(agp_gatt_table));
549 }
550
551 /* Flush the GART-TLB to remove stale entries */
552 amd_flush_garts();
553}
554
555/*
556 * If fix_up_north_bridges is set, the north bridges have to be fixed up on
557 * resume in the same way as they are handled in gart_iommu_hole_init().
558 */
559static bool fix_up_north_bridges;
560static u32 aperture_order;
561static u32 aperture_alloc;
562
563void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
564{
565 fix_up_north_bridges = true;
566 aperture_order = aper_order;
567 aperture_alloc = aper_alloc;
568}
569
570static void gart_fixup_northbridges(void)
571{
572 int i;
573
574 if (!fix_up_north_bridges)
575 return;
576
577 if (!amd_nb_has_feature(AMD_NB_GART))
578 return;
579
580 pr_info("PCI-DMA: Restoring GART aperture settings\n");
581
582 for (i = 0; i < amd_nb_num(); i++) {
583 struct pci_dev *dev = node_to_amd_nb(i)->misc;
584
585 /*
586 * Don't enable translations just yet. That is the next
587 * step. Restore the pre-suspend aperture settings.
588 */
589 gart_set_size_and_enable(dev, aperture_order);
590 pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE, aperture_alloc >> 25);
591 }
592}
593
594static void gart_resume(void)
595{
596 pr_info("PCI-DMA: Resuming GART IOMMU\n");
597
598 gart_fixup_northbridges();
599
600 enable_gart_translations();
601}
602
603static struct syscore_ops gart_syscore_ops = {
604 .resume = gart_resume,
605
606};
607
608/*
609 * Private Northbridge GATT initialization in case we cannot use the
610 * AGP driver for some reason.
611 */
612static __init int init_amd_gatt(struct agp_kern_info *info)
613{
614 unsigned aper_size, gatt_size, new_aper_size;
615 unsigned aper_base, new_aper_base;
616 struct pci_dev *dev;
617 void *gatt;
618 int i;
619
620 pr_info("PCI-DMA: Disabling AGP.\n");
621
622 aper_size = aper_base = info->aper_size = 0;
623 dev = NULL;
624 for (i = 0; i < amd_nb_num(); i++) {
625 dev = node_to_amd_nb(i)->misc;
626 new_aper_base = read_aperture(dev, &new_aper_size);
627 if (!new_aper_base)
628 goto nommu;
629
630 if (!aper_base) {
631 aper_size = new_aper_size;
632 aper_base = new_aper_base;
633 }
634 if (aper_size != new_aper_size || aper_base != new_aper_base)
635 goto nommu;
636 }
637 if (!aper_base)
638 goto nommu;
639
640 info->aper_base = aper_base;
641 info->aper_size = aper_size >> 20;
642
643 gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
644 gatt = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
645 get_order(gatt_size));
646 if (!gatt)
647 panic("Cannot allocate GATT table");
648 if (set_memory_uc((unsigned long)gatt, gatt_size >> PAGE_SHIFT))
649 panic("Could not set GART PTEs to uncacheable pages");
650
651 agp_gatt_table = gatt;
652
653 register_syscore_ops(&gart_syscore_ops);
654
655 flush_gart();
656
657 pr_info("PCI-DMA: aperture base @ %x size %u KB\n",
658 aper_base, aper_size>>10);
659
660 return 0;
661
662 nommu:
663 /* Should not happen anymore */
664 pr_warn("PCI-DMA: More than 4GB of RAM and no IOMMU - falling back to iommu=soft.\n");
665 return -1;
666}
667
668static const struct dma_map_ops gart_dma_ops = {
669 .map_sg = gart_map_sg,
670 .unmap_sg = gart_unmap_sg,
671 .map_page = gart_map_page,
672 .unmap_page = gart_unmap_page,
673 .alloc = gart_alloc_coherent,
674 .free = gart_free_coherent,
675 .mmap = dma_common_mmap,
676 .get_sgtable = dma_common_get_sgtable,
677 .dma_supported = dma_direct_supported,
678 .get_required_mask = dma_direct_get_required_mask,
679 .alloc_pages = dma_direct_alloc_pages,
680 .free_pages = dma_direct_free_pages,
681};
682
683static void gart_iommu_shutdown(void)
684{
685 struct pci_dev *dev;
686 int i;
687
688 /* don't shutdown it if there is AGP installed */
689 if (!no_agp)
690 return;
691
692 if (!amd_nb_has_feature(AMD_NB_GART))
693 return;
694
695 for (i = 0; i < amd_nb_num(); i++) {
696 u32 ctl;
697
698 dev = node_to_amd_nb(i)->misc;
699 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
700
701 ctl &= ~GARTEN;
702
703 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
704 }
705}
706
707int __init gart_iommu_init(void)
708{
709 struct agp_kern_info info;
710 unsigned long iommu_start;
711 unsigned long aper_base, aper_size;
712 unsigned long start_pfn, end_pfn;
713 unsigned long scratch;
714
715 if (!amd_nb_has_feature(AMD_NB_GART))
716 return 0;
717
718#ifndef CONFIG_AGP_AMD64
719 no_agp = 1;
720#else
721 /* Makefile puts PCI initialization via subsys_initcall first. */
722 /* Add other AMD AGP bridge drivers here */
723 no_agp = no_agp ||
724 (agp_amd64_init() < 0) ||
725 (agp_copy_info(agp_bridge, &info) < 0);
726#endif
727
728 if (no_iommu ||
729 (!force_iommu && max_pfn <= MAX_DMA32_PFN) ||
730 !gart_iommu_aperture ||
731 (no_agp && init_amd_gatt(&info) < 0)) {
732 if (max_pfn > MAX_DMA32_PFN) {
733 pr_warn("More than 4GB of memory but GART IOMMU not available.\n");
734 pr_warn("falling back to iommu=soft.\n");
735 }
736 return 0;
737 }
738
739 /* need to map that range */
740 aper_size = info.aper_size << 20;
741 aper_base = info.aper_base;
742 end_pfn = (aper_base>>PAGE_SHIFT) + (aper_size>>PAGE_SHIFT);
743
744 start_pfn = PFN_DOWN(aper_base);
745 if (!pfn_range_is_mapped(start_pfn, end_pfn))
746 init_memory_mapping(start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT,
747 PAGE_KERNEL);
748
749 pr_info("PCI-DMA: using GART IOMMU.\n");
750 iommu_size = check_iommu_size(info.aper_base, aper_size);
751 iommu_pages = iommu_size >> PAGE_SHIFT;
752
753 iommu_gart_bitmap = (void *) __get_free_pages(GFP_KERNEL | __GFP_ZERO,
754 get_order(iommu_pages/8));
755 if (!iommu_gart_bitmap)
756 panic("Cannot allocate iommu bitmap\n");
757
758 pr_info("PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
759 iommu_size >> 20);
760
761 agp_memory_reserved = iommu_size;
762 iommu_start = aper_size - iommu_size;
763 iommu_bus_base = info.aper_base + iommu_start;
764 iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
765
766 /*
767 * Unmap the IOMMU part of the GART. The alias of the page is
768 * always mapped with cache enabled and there is no full cache
769 * coherency across the GART remapping. The unmapping avoids
770 * automatic prefetches from the CPU allocating cache lines in
771 * there. All CPU accesses are done via the direct mapping to
772 * the backing memory. The GART address is only used by PCI
773 * devices.
774 */
775 set_memory_np((unsigned long)__va(iommu_bus_base),
776 iommu_size >> PAGE_SHIFT);
777 /*
778 * Tricky. The GART table remaps the physical memory range,
779 * so the CPU won't notice potential aliases and if the memory
780 * is remapped to UC later on, we might surprise the PCI devices
781 * with a stray writeout of a cacheline. So play it sure and
782 * do an explicit, full-scale wbinvd() _after_ having marked all
783 * the pages as Not-Present:
784 */
785 wbinvd();
786
787 /*
788 * Now all caches are flushed and we can safely enable
789 * GART hardware. Doing it early leaves the possibility
790 * of stale cache entries that can lead to GART PTE
791 * errors.
792 */
793 enable_gart_translations();
794
795 /*
796 * Try to workaround a bug (thanks to BenH):
797 * Set unmapped entries to a scratch page instead of 0.
798 * Any prefetches that hit unmapped entries won't get an bus abort
799 * then. (P2P bridge may be prefetching on DMA reads).
800 */
801 scratch = get_zeroed_page(GFP_KERNEL);
802 if (!scratch)
803 panic("Cannot allocate iommu scratch page");
804 gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
805
806 flush_gart();
807 dma_ops = &gart_dma_ops;
808 x86_platform.iommu_shutdown = gart_iommu_shutdown;
809 x86_swiotlb_enable = false;
810
811 return 0;
812}
813
814void __init gart_parse_options(char *p)
815{
816 int arg;
817
818 if (isdigit(*p) && get_option(&p, &arg))
819 iommu_size = arg;
820 if (!strncmp(p, "fullflush", 9))
821 iommu_fullflush = 1;
822 if (!strncmp(p, "nofullflush", 11))
823 iommu_fullflush = 0;
824 if (!strncmp(p, "noagp", 5))
825 no_agp = 1;
826 if (!strncmp(p, "noaperture", 10))
827 fix_aperture = 0;
828 /* duplicated from pci-dma.c */
829 if (!strncmp(p, "force", 5))
830 gart_iommu_aperture_allowed = 1;
831 if (!strncmp(p, "allowed", 7))
832 gart_iommu_aperture_allowed = 1;
833 if (!strncmp(p, "memaper", 7)) {
834 fallback_aper_force = 1;
835 p += 7;
836 if (*p == '=') {
837 ++p;
838 if (get_option(&p, &arg))
839 fallback_aper_order = arg;
840 }
841 }
842}