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1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Defines for the Malta interrupt controller.
23 *
24 */
25#ifndef _MIPS_MALTAINT_H
26#define _MIPS_MALTAINT_H
27
28#include <irq.h>
29
30/*
31 * Interrupts 0..15 are used for Malta ISA compatible interrupts
32 */
33#define MALTA_INT_BASE 0
34
35/* CPU interrupt offsets */
36#define MIPSCPU_INT_SW0 0
37#define MIPSCPU_INT_SW1 1
38#define MIPSCPU_INT_MB0 2
39#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
40#define MIPSCPU_INT_MB1 3
41#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
42#define MIPSCPU_INT_IPI0 MIPSCPU_INT_MB1 /* GIC IPI */
43#define MIPSCPU_INT_MB2 4
44#define MIPSCPU_INT_IPI1 MIPSCPU_INT_MB2 /* GIC IPI */
45#define MIPSCPU_INT_MB3 5
46#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
47#define MIPSCPU_INT_MB4 6
48#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
49
50/*
51 * Interrupts 64..127 are used for Soc-it Classic interrupts
52 */
53#define MSC01C_INT_BASE 64
54
55/* SOC-it Classic interrupt offsets */
56#define MSC01C_INT_TMR 0
57#define MSC01C_INT_PCI 1
58
59/*
60 * Interrupts 64..127 are used for Soc-it EIC interrupts
61 */
62#define MSC01E_INT_BASE 64
63
64/* SOC-it EIC interrupt offsets */
65#define MSC01E_INT_SW0 1
66#define MSC01E_INT_SW1 2
67#define MSC01E_INT_MB0 3
68#define MSC01E_INT_I8259A MSC01E_INT_MB0
69#define MSC01E_INT_MB1 4
70#define MSC01E_INT_SMI MSC01E_INT_MB1
71#define MSC01E_INT_MB2 5
72#define MSC01E_INT_MB3 6
73#define MSC01E_INT_COREHI MSC01E_INT_MB3
74#define MSC01E_INT_MB4 7
75#define MSC01E_INT_CORELO MSC01E_INT_MB4
76#define MSC01E_INT_TMR 8
77#define MSC01E_INT_PCI 9
78#define MSC01E_INT_PERFCTR 10
79#define MSC01E_INT_CPUCTR 11
80
81/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
82#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
83#define GIC_CPU_INT1 1 /* . */
84#define GIC_CPU_INT2 2 /* . */
85#define GIC_CPU_INT3 3 /* . */
86#define GIC_CPU_INT4 4 /* . */
87#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
88
89#define GIC_EXT_INTR(x) x
90
91/* External Interrupts used for IPI */
92#define GIC_IPI_EXT_INTR_RESCHED_VPE0 16
93#define GIC_IPI_EXT_INTR_CALLFNC_VPE0 17
94#define GIC_IPI_EXT_INTR_RESCHED_VPE1 18
95#define GIC_IPI_EXT_INTR_CALLFNC_VPE1 19
96#define GIC_IPI_EXT_INTR_RESCHED_VPE2 20
97#define GIC_IPI_EXT_INTR_CALLFNC_VPE2 21
98#define GIC_IPI_EXT_INTR_RESCHED_VPE3 22
99#define GIC_IPI_EXT_INTR_CALLFNC_VPE3 23
100
101#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
102
103#ifndef __ASSEMBLY__
104extern void maltaint_init(void);
105#endif
106
107#endif /* !(_MIPS_MALTAINT_H) */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000,2012 MIPS Technologies, Inc. All rights reserved.
7 * Carsten Langgaard <carstenl@mips.com>
8 * Steven J. Hill <sjhill@mips.com>
9 */
10#ifndef _MIPS_MALTAINT_H
11#define _MIPS_MALTAINT_H
12
13/*
14 * Interrupts 0..15 are used for Malta ISA compatible interrupts
15 */
16#define MALTA_INT_BASE 0
17
18/* CPU interrupt offsets */
19#define MIPSCPU_INT_SW0 0
20#define MIPSCPU_INT_SW1 1
21#define MIPSCPU_INT_MB0 2
22#define MIPSCPU_INT_I8259A MIPSCPU_INT_MB0
23#define MIPSCPU_INT_GIC MIPSCPU_INT_MB0 /* GIC chained interrupt */
24#define MIPSCPU_INT_MB1 3
25#define MIPSCPU_INT_SMI MIPSCPU_INT_MB1
26#define MIPSCPU_INT_MB2 4
27#define MIPSCPU_INT_MB3 5
28#define MIPSCPU_INT_COREHI MIPSCPU_INT_MB3
29#define MIPSCPU_INT_MB4 6
30#define MIPSCPU_INT_CORELO MIPSCPU_INT_MB4
31
32/*
33 * Interrupts 96..127 are used for Soc-it Classic interrupts
34 */
35#define MSC01C_INT_BASE 96
36
37/* SOC-it Classic interrupt offsets */
38#define MSC01C_INT_TMR 0
39#define MSC01C_INT_PCI 1
40
41/*
42 * Interrupts 96..127 are used for Soc-it EIC interrupts
43 */
44#define MSC01E_INT_BASE 96
45
46/* SOC-it EIC interrupt offsets */
47#define MSC01E_INT_SW0 1
48#define MSC01E_INT_SW1 2
49#define MSC01E_INT_MB0 3
50#define MSC01E_INT_I8259A MSC01E_INT_MB0
51#define MSC01E_INT_MB1 4
52#define MSC01E_INT_SMI MSC01E_INT_MB1
53#define MSC01E_INT_MB2 5
54#define MSC01E_INT_MB3 6
55#define MSC01E_INT_COREHI MSC01E_INT_MB3
56#define MSC01E_INT_MB4 7
57#define MSC01E_INT_CORELO MSC01E_INT_MB4
58#define MSC01E_INT_TMR 8
59#define MSC01E_INT_PCI 9
60#define MSC01E_INT_PERFCTR 10
61#define MSC01E_INT_CPUCTR 11
62
63#endif /* !(_MIPS_MALTAINT_H) */