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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for STM32 Independent Watchdog
4 *
5 * Copyright (C) STMicroelectronics 2017
6 * Author: Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
7 *
8 * This driver is based on tegra_wdt.c
9 *
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/iopoll.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/watchdog.h>
22
23/* IWDG registers */
24#define IWDG_KR 0x00 /* Key register */
25#define IWDG_PR 0x04 /* Prescaler Register */
26#define IWDG_RLR 0x08 /* ReLoad Register */
27#define IWDG_SR 0x0C /* Status Register */
28#define IWDG_WINR 0x10 /* Windows Register */
29
30/* IWDG_KR register bit mask */
31#define KR_KEY_RELOAD 0xAAAA /* reload counter enable */
32#define KR_KEY_ENABLE 0xCCCC /* peripheral enable */
33#define KR_KEY_EWA 0x5555 /* write access enable */
34#define KR_KEY_DWA 0x0000 /* write access disable */
35
36/* IWDG_PR register */
37#define PR_SHIFT 2
38#define PR_MIN BIT(PR_SHIFT)
39
40/* IWDG_RLR register values */
41#define RLR_MIN 0x2 /* min value recommended */
42#define RLR_MAX GENMASK(11, 0) /* max value of reload register */
43
44/* IWDG_SR register bit mask */
45#define SR_PVU BIT(0) /* Watchdog prescaler value update */
46#define SR_RVU BIT(1) /* Watchdog counter reload value update */
47
48/* set timeout to 100000 us */
49#define TIMEOUT_US 100000
50#define SLEEP_US 1000
51
52struct stm32_iwdg_data {
53 bool has_pclk;
54 u32 max_prescaler;
55};
56
57static const struct stm32_iwdg_data stm32_iwdg_data = {
58 .has_pclk = false,
59 .max_prescaler = 256,
60};
61
62static const struct stm32_iwdg_data stm32mp1_iwdg_data = {
63 .has_pclk = true,
64 .max_prescaler = 1024,
65};
66
67struct stm32_iwdg {
68 struct watchdog_device wdd;
69 const struct stm32_iwdg_data *data;
70 void __iomem *regs;
71 struct clk *clk_lsi;
72 struct clk *clk_pclk;
73 unsigned int rate;
74};
75
76static inline u32 reg_read(void __iomem *base, u32 reg)
77{
78 return readl_relaxed(base + reg);
79}
80
81static inline void reg_write(void __iomem *base, u32 reg, u32 val)
82{
83 writel_relaxed(val, base + reg);
84}
85
86static int stm32_iwdg_start(struct watchdog_device *wdd)
87{
88 struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
89 u32 tout, presc, iwdg_rlr, iwdg_pr, iwdg_sr;
90 int ret;
91
92 dev_dbg(wdd->parent, "%s\n", __func__);
93
94 tout = clamp_t(unsigned int, wdd->timeout,
95 wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000);
96
97 presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1);
98
99 /* The prescaler is align on power of 2 and start at 2 ^ PR_SHIFT. */
100 presc = roundup_pow_of_two(presc);
101 iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT;
102 iwdg_rlr = ((tout * wdt->rate) / presc) - 1;
103
104 /* enable write access */
105 reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA);
106
107 /* set prescaler & reload registers */
108 reg_write(wdt->regs, IWDG_PR, iwdg_pr);
109 reg_write(wdt->regs, IWDG_RLR, iwdg_rlr);
110 reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE);
111
112 /* wait for the registers to be updated (max 100ms) */
113 ret = readl_relaxed_poll_timeout(wdt->regs + IWDG_SR, iwdg_sr,
114 !(iwdg_sr & (SR_PVU | SR_RVU)),
115 SLEEP_US, TIMEOUT_US);
116 if (ret) {
117 dev_err(wdd->parent, "Fail to set prescaler, reload regs\n");
118 return ret;
119 }
120
121 /* reload watchdog */
122 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
123
124 return 0;
125}
126
127static int stm32_iwdg_ping(struct watchdog_device *wdd)
128{
129 struct stm32_iwdg *wdt = watchdog_get_drvdata(wdd);
130
131 dev_dbg(wdd->parent, "%s\n", __func__);
132
133 /* reload watchdog */
134 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD);
135
136 return 0;
137}
138
139static int stm32_iwdg_set_timeout(struct watchdog_device *wdd,
140 unsigned int timeout)
141{
142 dev_dbg(wdd->parent, "%s timeout: %d sec\n", __func__, timeout);
143
144 wdd->timeout = timeout;
145
146 if (watchdog_active(wdd))
147 return stm32_iwdg_start(wdd);
148
149 return 0;
150}
151
152static void stm32_clk_disable_unprepare(void *data)
153{
154 clk_disable_unprepare(data);
155}
156
157static int stm32_iwdg_clk_init(struct platform_device *pdev,
158 struct stm32_iwdg *wdt)
159{
160 struct device *dev = &pdev->dev;
161 u32 ret;
162
163 wdt->clk_lsi = devm_clk_get(dev, "lsi");
164 if (IS_ERR(wdt->clk_lsi))
165 return dev_err_probe(dev, PTR_ERR(wdt->clk_lsi), "Unable to get lsi clock\n");
166
167 /* optional peripheral clock */
168 if (wdt->data->has_pclk) {
169 wdt->clk_pclk = devm_clk_get(dev, "pclk");
170 if (IS_ERR(wdt->clk_pclk))
171 return dev_err_probe(dev, PTR_ERR(wdt->clk_pclk),
172 "Unable to get pclk clock\n");
173
174 ret = clk_prepare_enable(wdt->clk_pclk);
175 if (ret) {
176 dev_err(dev, "Unable to prepare pclk clock\n");
177 return ret;
178 }
179 ret = devm_add_action_or_reset(dev,
180 stm32_clk_disable_unprepare,
181 wdt->clk_pclk);
182 if (ret)
183 return ret;
184 }
185
186 ret = clk_prepare_enable(wdt->clk_lsi);
187 if (ret) {
188 dev_err(dev, "Unable to prepare lsi clock\n");
189 return ret;
190 }
191 ret = devm_add_action_or_reset(dev, stm32_clk_disable_unprepare,
192 wdt->clk_lsi);
193 if (ret)
194 return ret;
195
196 wdt->rate = clk_get_rate(wdt->clk_lsi);
197
198 return 0;
199}
200
201static const struct watchdog_info stm32_iwdg_info = {
202 .options = WDIOF_SETTIMEOUT |
203 WDIOF_MAGICCLOSE |
204 WDIOF_KEEPALIVEPING,
205 .identity = "STM32 Independent Watchdog",
206};
207
208static const struct watchdog_ops stm32_iwdg_ops = {
209 .owner = THIS_MODULE,
210 .start = stm32_iwdg_start,
211 .ping = stm32_iwdg_ping,
212 .set_timeout = stm32_iwdg_set_timeout,
213};
214
215static const struct of_device_id stm32_iwdg_of_match[] = {
216 { .compatible = "st,stm32-iwdg", .data = &stm32_iwdg_data },
217 { .compatible = "st,stm32mp1-iwdg", .data = &stm32mp1_iwdg_data },
218 { /* end node */ }
219};
220MODULE_DEVICE_TABLE(of, stm32_iwdg_of_match);
221
222static int stm32_iwdg_probe(struct platform_device *pdev)
223{
224 struct device *dev = &pdev->dev;
225 struct watchdog_device *wdd;
226 struct stm32_iwdg *wdt;
227 int ret;
228
229 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
230 if (!wdt)
231 return -ENOMEM;
232
233 wdt->data = of_device_get_match_data(&pdev->dev);
234 if (!wdt->data)
235 return -ENODEV;
236
237 /* This is the timer base. */
238 wdt->regs = devm_platform_ioremap_resource(pdev, 0);
239 if (IS_ERR(wdt->regs))
240 return PTR_ERR(wdt->regs);
241
242 ret = stm32_iwdg_clk_init(pdev, wdt);
243 if (ret)
244 return ret;
245
246 /* Initialize struct watchdog_device. */
247 wdd = &wdt->wdd;
248 wdd->parent = dev;
249 wdd->info = &stm32_iwdg_info;
250 wdd->ops = &stm32_iwdg_ops;
251 wdd->min_timeout = DIV_ROUND_UP((RLR_MIN + 1) * PR_MIN, wdt->rate);
252 wdd->max_hw_heartbeat_ms = ((RLR_MAX + 1) * wdt->data->max_prescaler *
253 1000) / wdt->rate;
254
255 watchdog_set_drvdata(wdd, wdt);
256 watchdog_set_nowayout(wdd, WATCHDOG_NOWAYOUT);
257 watchdog_init_timeout(wdd, 0, dev);
258
259 /*
260 * In case of CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED is set
261 * (Means U-Boot/bootloaders leaves the watchdog running)
262 * When we get here we should make a decision to prevent
263 * any side effects before user space daemon will take care of it.
264 * The best option, taking into consideration that there is no
265 * way to read values back from hardware, is to enforce watchdog
266 * being run with deterministic values.
267 */
268 if (IS_ENABLED(CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED)) {
269 ret = stm32_iwdg_start(wdd);
270 if (ret)
271 return ret;
272
273 /* Make sure the watchdog is serviced */
274 set_bit(WDOG_HW_RUNNING, &wdd->status);
275 }
276
277 ret = devm_watchdog_register_device(dev, wdd);
278 if (ret)
279 return ret;
280
281 platform_set_drvdata(pdev, wdt);
282
283 return 0;
284}
285
286static struct platform_driver stm32_iwdg_driver = {
287 .probe = stm32_iwdg_probe,
288 .driver = {
289 .name = "iwdg",
290 .of_match_table = stm32_iwdg_of_match,
291 },
292};
293module_platform_driver(stm32_iwdg_driver);
294
295MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
296MODULE_DESCRIPTION("STMicroelectronics STM32 Independent Watchdog Driver");
297MODULE_LICENSE("GPL v2");