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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 * Based on EP93xx wdt driver
8 */
9
10#include <linux/module.h>
11#include <linux/fs.h>
12#include <linux/miscdevice.h>
13#include <linux/watchdog.h>
14#include <linux/platform_device.h>
15#include <linux/uaccess.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18
19#include <lantiq.h>
20
21/* Section 3.4 of the datasheet
22 * The password sequence protects the WDT control register from unintended
23 * write actions, which might cause malfunction of the WDT.
24 *
25 * essentially the following two magic passwords need to be written to allow
26 * IO access to the WDT core
27 */
28#define LTQ_WDT_PW1 0x00BE0000
29#define LTQ_WDT_PW2 0x00DC0000
30
31#define LTQ_WDT_CR 0x0 /* watchdog control register */
32#define LTQ_WDT_SR 0x8 /* watchdog status register */
33
34#define LTQ_WDT_SR_EN (0x1 << 31) /* enable bit */
35#define LTQ_WDT_SR_PWD (0x3 << 26) /* turn on power */
36#define LTQ_WDT_SR_CLKDIV (0x3 << 24) /* turn on clock and set */
37 /* divider to 0x40000 */
38#define LTQ_WDT_DIVIDER 0x40000
39#define LTQ_MAX_TIMEOUT ((1 << 16) - 1) /* the reload field is 16 bit */
40
41static int nowayout = WATCHDOG_NOWAYOUT;
42
43static void __iomem *ltq_wdt_membase;
44static unsigned long ltq_io_region_clk_rate;
45
46static unsigned long ltq_wdt_bootstatus;
47static unsigned long ltq_wdt_in_use;
48static int ltq_wdt_timeout = 30;
49static int ltq_wdt_ok_to_close;
50
51static void
52ltq_wdt_enable(void)
53{
54 unsigned long int timeout = ltq_wdt_timeout *
55 (ltq_io_region_clk_rate / LTQ_WDT_DIVIDER) + 0x1000;
56 if (timeout > LTQ_MAX_TIMEOUT)
57 timeout = LTQ_MAX_TIMEOUT;
58
59 /* write the first password magic */
60 ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
61 /* write the second magic plus the configuration and new timeout */
62 ltq_w32(LTQ_WDT_SR_EN | LTQ_WDT_SR_PWD | LTQ_WDT_SR_CLKDIV |
63 LTQ_WDT_PW2 | timeout, ltq_wdt_membase + LTQ_WDT_CR);
64}
65
66static void
67ltq_wdt_disable(void)
68{
69 /* write the first password magic */
70 ltq_w32(LTQ_WDT_PW1, ltq_wdt_membase + LTQ_WDT_CR);
71 /* write the second password magic with no config
72 * this turns the watchdog off
73 */
74 ltq_w32(LTQ_WDT_PW2, ltq_wdt_membase + LTQ_WDT_CR);
75}
76
77static ssize_t
78ltq_wdt_write(struct file *file, const char __user *data,
79 size_t len, loff_t *ppos)
80{
81 if (len) {
82 if (!nowayout) {
83 size_t i;
84
85 ltq_wdt_ok_to_close = 0;
86 for (i = 0; i != len; i++) {
87 char c;
88
89 if (get_user(c, data + i))
90 return -EFAULT;
91 if (c == 'V')
92 ltq_wdt_ok_to_close = 1;
93 else
94 ltq_wdt_ok_to_close = 0;
95 }
96 }
97 ltq_wdt_enable();
98 }
99
100 return len;
101}
102
103static struct watchdog_info ident = {
104 .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
105 WDIOF_CARDRESET,
106 .identity = "ltq_wdt",
107};
108
109static long
110ltq_wdt_ioctl(struct file *file,
111 unsigned int cmd, unsigned long arg)
112{
113 int ret = -ENOTTY;
114
115 switch (cmd) {
116 case WDIOC_GETSUPPORT:
117 ret = copy_to_user((struct watchdog_info __user *)arg, &ident,
118 sizeof(ident)) ? -EFAULT : 0;
119 break;
120
121 case WDIOC_GETBOOTSTATUS:
122 ret = put_user(ltq_wdt_bootstatus, (int __user *)arg);
123 break;
124
125 case WDIOC_GETSTATUS:
126 ret = put_user(0, (int __user *)arg);
127 break;
128
129 case WDIOC_SETTIMEOUT:
130 ret = get_user(ltq_wdt_timeout, (int __user *)arg);
131 if (!ret)
132 ltq_wdt_enable();
133 /* intentional drop through */
134 case WDIOC_GETTIMEOUT:
135 ret = put_user(ltq_wdt_timeout, (int __user *)arg);
136 break;
137
138 case WDIOC_KEEPALIVE:
139 ltq_wdt_enable();
140 ret = 0;
141 break;
142 }
143 return ret;
144}
145
146static int
147ltq_wdt_open(struct inode *inode, struct file *file)
148{
149 if (test_and_set_bit(0, <q_wdt_in_use))
150 return -EBUSY;
151 ltq_wdt_in_use = 1;
152 ltq_wdt_enable();
153
154 return nonseekable_open(inode, file);
155}
156
157static int
158ltq_wdt_release(struct inode *inode, struct file *file)
159{
160 if (ltq_wdt_ok_to_close)
161 ltq_wdt_disable();
162 else
163 pr_err("ltq_wdt: watchdog closed without warning\n");
164 ltq_wdt_ok_to_close = 0;
165 clear_bit(0, <q_wdt_in_use);
166
167 return 0;
168}
169
170static const struct file_operations ltq_wdt_fops = {
171 .owner = THIS_MODULE,
172 .write = ltq_wdt_write,
173 .unlocked_ioctl = ltq_wdt_ioctl,
174 .open = ltq_wdt_open,
175 .release = ltq_wdt_release,
176 .llseek = no_llseek,
177};
178
179static struct miscdevice ltq_wdt_miscdev = {
180 .minor = WATCHDOG_MINOR,
181 .name = "watchdog",
182 .fops = <q_wdt_fops,
183};
184
185static int __init
186ltq_wdt_probe(struct platform_device *pdev)
187{
188 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
189 struct clk *clk;
190
191 if (!res) {
192 dev_err(&pdev->dev, "cannot obtain I/O memory region");
193 return -ENOENT;
194 }
195 res = devm_request_mem_region(&pdev->dev, res->start,
196 resource_size(res), dev_name(&pdev->dev));
197 if (!res) {
198 dev_err(&pdev->dev, "cannot request I/O memory region");
199 return -EBUSY;
200 }
201 ltq_wdt_membase = devm_ioremap_nocache(&pdev->dev, res->start,
202 resource_size(res));
203 if (!ltq_wdt_membase) {
204 dev_err(&pdev->dev, "cannot remap I/O memory region\n");
205 return -ENOMEM;
206 }
207
208 /* we do not need to enable the clock as it is always running */
209 clk = clk_get(&pdev->dev, "io");
210 WARN_ON(!clk);
211 ltq_io_region_clk_rate = clk_get_rate(clk);
212 clk_put(clk);
213
214 if (ltq_reset_cause() == LTQ_RST_CAUSE_WDTRST)
215 ltq_wdt_bootstatus = WDIOF_CARDRESET;
216
217 return misc_register(<q_wdt_miscdev);
218}
219
220static int __devexit
221ltq_wdt_remove(struct platform_device *pdev)
222{
223 misc_deregister(<q_wdt_miscdev);
224
225 if (ltq_wdt_membase)
226 iounmap(ltq_wdt_membase);
227
228 return 0;
229}
230
231
232static struct platform_driver ltq_wdt_driver = {
233 .remove = __devexit_p(ltq_wdt_remove),
234 .driver = {
235 .name = "ltq_wdt",
236 .owner = THIS_MODULE,
237 },
238};
239
240static int __init
241init_ltq_wdt(void)
242{
243 return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe);
244}
245
246static void __exit
247exit_ltq_wdt(void)
248{
249 return platform_driver_unregister(<q_wdt_driver);
250}
251
252module_init(init_ltq_wdt);
253module_exit(exit_ltq_wdt);
254
255module_param(nowayout, int, 0);
256MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
257
258MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
259MODULE_DESCRIPTION("Lantiq SoC Watchdog");
260MODULE_LICENSE("GPL");
261MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2010 John Crispin <john@phrozen.org>
5 * Copyright (C) 2017 Hauke Mehrtens <hauke@hauke-m.de>
6 * Based on EP93xx wdt driver
7 */
8
9#include <linux/module.h>
10#include <linux/bitops.h>
11#include <linux/watchdog.h>
12#include <linux/of.h>
13#include <linux/platform_device.h>
14#include <linux/uaccess.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/regmap.h>
18#include <linux/mfd/syscon.h>
19
20#include <lantiq_soc.h>
21
22#define LTQ_XRX_RCU_RST_STAT 0x0014
23#define LTQ_XRX_RCU_RST_STAT_WDT BIT(31)
24
25/* CPU0 Reset Source Register */
26#define LTQ_FALCON_SYS1_CPU0RS 0x0060
27/* reset cause mask */
28#define LTQ_FALCON_SYS1_CPU0RS_MASK 0x0007
29#define LTQ_FALCON_SYS1_CPU0RS_WDT 0x02
30
31/*
32 * Section 3.4 of the datasheet
33 * The password sequence protects the WDT control register from unintended
34 * write actions, which might cause malfunction of the WDT.
35 *
36 * essentially the following two magic passwords need to be written to allow
37 * IO access to the WDT core
38 */
39#define LTQ_WDT_CR_PW1 0x00BE0000
40#define LTQ_WDT_CR_PW2 0x00DC0000
41
42#define LTQ_WDT_CR 0x0 /* watchdog control register */
43#define LTQ_WDT_CR_GEN BIT(31) /* enable bit */
44/* Pre-warning limit set to 1/16 of max WDT period */
45#define LTQ_WDT_CR_PWL (0x3 << 26)
46/* set clock divider to 0x40000 */
47#define LTQ_WDT_CR_CLKDIV (0x3 << 24)
48#define LTQ_WDT_CR_PW_MASK GENMASK(23, 16) /* Password field */
49#define LTQ_WDT_CR_MAX_TIMEOUT ((1 << 16) - 1) /* The reload field is 16 bit */
50#define LTQ_WDT_SR 0x8 /* watchdog status register */
51#define LTQ_WDT_SR_EN BIT(31) /* Enable */
52#define LTQ_WDT_SR_VALUE_MASK GENMASK(15, 0) /* Timer value */
53
54#define LTQ_WDT_DIVIDER 0x40000
55
56static bool nowayout = WATCHDOG_NOWAYOUT;
57
58struct ltq_wdt_hw {
59 int (*bootstatus_get)(struct device *dev);
60};
61
62struct ltq_wdt_priv {
63 struct watchdog_device wdt;
64 void __iomem *membase;
65 unsigned long clk_rate;
66};
67
68static u32 ltq_wdt_r32(struct ltq_wdt_priv *priv, u32 offset)
69{
70 return __raw_readl(priv->membase + offset);
71}
72
73static void ltq_wdt_w32(struct ltq_wdt_priv *priv, u32 val, u32 offset)
74{
75 __raw_writel(val, priv->membase + offset);
76}
77
78static void ltq_wdt_mask(struct ltq_wdt_priv *priv, u32 clear, u32 set,
79 u32 offset)
80{
81 u32 val = ltq_wdt_r32(priv, offset);
82
83 val &= ~(clear);
84 val |= set;
85 ltq_wdt_w32(priv, val, offset);
86}
87
88static struct ltq_wdt_priv *ltq_wdt_get_priv(struct watchdog_device *wdt)
89{
90 return container_of(wdt, struct ltq_wdt_priv, wdt);
91}
92
93static struct watchdog_info ltq_wdt_info = {
94 .options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
95 WDIOF_CARDRESET,
96 .identity = "ltq_wdt",
97};
98
99static int ltq_wdt_start(struct watchdog_device *wdt)
100{
101 struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
102 u32 timeout;
103
104 timeout = wdt->timeout * priv->clk_rate;
105
106 ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
107 /* write the second magic plus the configuration and new timeout */
108 ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
109 LTQ_WDT_CR_GEN | LTQ_WDT_CR_PWL | LTQ_WDT_CR_CLKDIV |
110 LTQ_WDT_CR_PW2 | timeout,
111 LTQ_WDT_CR);
112
113 return 0;
114}
115
116static int ltq_wdt_stop(struct watchdog_device *wdt)
117{
118 struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
119
120 ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
121 ltq_wdt_mask(priv, LTQ_WDT_CR_GEN | LTQ_WDT_CR_PW_MASK,
122 LTQ_WDT_CR_PW2, LTQ_WDT_CR);
123
124 return 0;
125}
126
127static int ltq_wdt_ping(struct watchdog_device *wdt)
128{
129 struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
130 u32 timeout;
131
132 timeout = wdt->timeout * priv->clk_rate;
133
134 ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK, LTQ_WDT_CR_PW1, LTQ_WDT_CR);
135 /* write the second magic plus the configuration and new timeout */
136 ltq_wdt_mask(priv, LTQ_WDT_CR_PW_MASK | LTQ_WDT_CR_MAX_TIMEOUT,
137 LTQ_WDT_CR_PW2 | timeout, LTQ_WDT_CR);
138
139 return 0;
140}
141
142static unsigned int ltq_wdt_get_timeleft(struct watchdog_device *wdt)
143{
144 struct ltq_wdt_priv *priv = ltq_wdt_get_priv(wdt);
145 u64 timeout;
146
147 timeout = ltq_wdt_r32(priv, LTQ_WDT_SR) & LTQ_WDT_SR_VALUE_MASK;
148 return do_div(timeout, priv->clk_rate);
149}
150
151static const struct watchdog_ops ltq_wdt_ops = {
152 .owner = THIS_MODULE,
153 .start = ltq_wdt_start,
154 .stop = ltq_wdt_stop,
155 .ping = ltq_wdt_ping,
156 .get_timeleft = ltq_wdt_get_timeleft,
157};
158
159static int ltq_wdt_xrx_bootstatus_get(struct device *dev)
160{
161 struct regmap *rcu_regmap;
162 u32 val;
163 int err;
164
165 rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "regmap");
166 if (IS_ERR(rcu_regmap))
167 return PTR_ERR(rcu_regmap);
168
169 err = regmap_read(rcu_regmap, LTQ_XRX_RCU_RST_STAT, &val);
170 if (err)
171 return err;
172
173 if (val & LTQ_XRX_RCU_RST_STAT_WDT)
174 return WDIOF_CARDRESET;
175
176 return 0;
177}
178
179static int ltq_wdt_falcon_bootstatus_get(struct device *dev)
180{
181 struct regmap *rcu_regmap;
182 u32 val;
183 int err;
184
185 rcu_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
186 "lantiq,rcu");
187 if (IS_ERR(rcu_regmap))
188 return PTR_ERR(rcu_regmap);
189
190 err = regmap_read(rcu_regmap, LTQ_FALCON_SYS1_CPU0RS, &val);
191 if (err)
192 return err;
193
194 if ((val & LTQ_FALCON_SYS1_CPU0RS_MASK) == LTQ_FALCON_SYS1_CPU0RS_WDT)
195 return WDIOF_CARDRESET;
196
197 return 0;
198}
199
200static int ltq_wdt_probe(struct platform_device *pdev)
201{
202 struct device *dev = &pdev->dev;
203 struct ltq_wdt_priv *priv;
204 struct watchdog_device *wdt;
205 struct clk *clk;
206 const struct ltq_wdt_hw *ltq_wdt_hw;
207 int ret;
208 u32 status;
209
210 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
211 if (!priv)
212 return -ENOMEM;
213
214 priv->membase = devm_platform_ioremap_resource(pdev, 0);
215 if (IS_ERR(priv->membase))
216 return PTR_ERR(priv->membase);
217
218 /* we do not need to enable the clock as it is always running */
219 clk = clk_get_io();
220 priv->clk_rate = clk_get_rate(clk) / LTQ_WDT_DIVIDER;
221 if (!priv->clk_rate) {
222 dev_err(dev, "clock rate less than divider %i\n",
223 LTQ_WDT_DIVIDER);
224 return -EINVAL;
225 }
226
227 wdt = &priv->wdt;
228 wdt->info = <q_wdt_info;
229 wdt->ops = <q_wdt_ops;
230 wdt->min_timeout = 1;
231 wdt->max_timeout = LTQ_WDT_CR_MAX_TIMEOUT / priv->clk_rate;
232 wdt->timeout = wdt->max_timeout;
233 wdt->parent = dev;
234
235 ltq_wdt_hw = of_device_get_match_data(dev);
236 if (ltq_wdt_hw && ltq_wdt_hw->bootstatus_get) {
237 ret = ltq_wdt_hw->bootstatus_get(dev);
238 if (ret >= 0)
239 wdt->bootstatus = ret;
240 }
241
242 watchdog_set_nowayout(wdt, nowayout);
243 watchdog_init_timeout(wdt, 0, dev);
244
245 status = ltq_wdt_r32(priv, LTQ_WDT_SR);
246 if (status & LTQ_WDT_SR_EN) {
247 /*
248 * If the watchdog is already running overwrite it with our
249 * new settings. Stop is not needed as the start call will
250 * replace all settings anyway.
251 */
252 ltq_wdt_start(wdt);
253 set_bit(WDOG_HW_RUNNING, &wdt->status);
254 }
255
256 return devm_watchdog_register_device(dev, wdt);
257}
258
259static const struct ltq_wdt_hw ltq_wdt_xrx100 = {
260 .bootstatus_get = ltq_wdt_xrx_bootstatus_get,
261};
262
263static const struct ltq_wdt_hw ltq_wdt_falcon = {
264 .bootstatus_get = ltq_wdt_falcon_bootstatus_get,
265};
266
267static const struct of_device_id ltq_wdt_match[] = {
268 { .compatible = "lantiq,wdt", .data = NULL },
269 { .compatible = "lantiq,xrx100-wdt", .data = <q_wdt_xrx100 },
270 { .compatible = "lantiq,falcon-wdt", .data = <q_wdt_falcon },
271 {},
272};
273MODULE_DEVICE_TABLE(of, ltq_wdt_match);
274
275static struct platform_driver ltq_wdt_driver = {
276 .probe = ltq_wdt_probe,
277 .driver = {
278 .name = "wdt",
279 .of_match_table = ltq_wdt_match,
280 },
281};
282
283module_platform_driver(ltq_wdt_driver);
284
285module_param(nowayout, bool, 0);
286MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started");
287MODULE_AUTHOR("John Crispin <john@phrozen.org>");
288MODULE_DESCRIPTION("Lantiq SoC Watchdog");
289MODULE_LICENSE("GPL");