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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Ice Lake PCH pinctrl/GPIO driver
4 *
5 * Copyright (C) 2018, 2022 Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#include <linux/acpi.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/pm.h>
14
15#include <linux/pinctrl/pinctrl.h>
16
17#include "pinctrl-intel.h"
18
19#define ICL_LP_PAD_OWN 0x020
20#define ICL_LP_PADCFGLOCK 0x080
21#define ICL_LP_HOSTSW_OWN 0x0b0
22#define ICL_LP_GPI_IS 0x100
23#define ICL_LP_GPI_IE 0x110
24
25#define ICL_N_PAD_OWN 0x020
26#define ICL_N_PADCFGLOCK 0x080
27#define ICL_N_HOSTSW_OWN 0x0b0
28#define ICL_N_GPI_IS 0x100
29#define ICL_N_GPI_IE 0x120
30
31#define ICL_GPP(r, s, e, g) \
32 { \
33 .reg_num = (r), \
34 .base = (s), \
35 .size = ((e) - (s) + 1), \
36 .gpio_base = (g), \
37 }
38
39#define ICL_LP_COMMUNITY(b, s, e, g) \
40 INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_LP)
41
42#define ICL_N_COMMUNITY(b, s, e, g) \
43 INTEL_COMMUNITY_GPPS(b, s, e, g, ICL_N)
44
45/* Ice Lake-LP */
46static const struct pinctrl_pin_desc icllp_pins[] = {
47 /* GPP_G */
48 PINCTRL_PIN(0, "SD3_CMD"),
49 PINCTRL_PIN(1, "SD3_D0"),
50 PINCTRL_PIN(2, "SD3_D1"),
51 PINCTRL_PIN(3, "SD3_D2"),
52 PINCTRL_PIN(4, "SD3_D3"),
53 PINCTRL_PIN(5, "SD3_CDB"),
54 PINCTRL_PIN(6, "SD3_CLK"),
55 PINCTRL_PIN(7, "SD3_WP"),
56 /* GPP_B */
57 PINCTRL_PIN(8, "CORE_VID_0"),
58 PINCTRL_PIN(9, "CORE_VID_1"),
59 PINCTRL_PIN(10, "VRALERTB"),
60 PINCTRL_PIN(11, "CPU_GP_2"),
61 PINCTRL_PIN(12, "CPU_GP_3"),
62 PINCTRL_PIN(13, "ISH_I2C0_SDA"),
63 PINCTRL_PIN(14, "ISH_I2C0_SCL"),
64 PINCTRL_PIN(15, "ISH_I2C1_SDA"),
65 PINCTRL_PIN(16, "ISH_I2C1_SCL"),
66 PINCTRL_PIN(17, "I2C5_SDA"),
67 PINCTRL_PIN(18, "I2C5_SCL"),
68 PINCTRL_PIN(19, "PMCALERTB"),
69 PINCTRL_PIN(20, "SLP_S0B"),
70 PINCTRL_PIN(21, "PLTRSTB"),
71 PINCTRL_PIN(22, "SPKR"),
72 PINCTRL_PIN(23, "GSPI0_CS0B"),
73 PINCTRL_PIN(24, "GSPI0_CLK"),
74 PINCTRL_PIN(25, "GSPI0_MISO"),
75 PINCTRL_PIN(26, "GSPI0_MOSI"),
76 PINCTRL_PIN(27, "GSPI1_CS0B"),
77 PINCTRL_PIN(28, "GSPI1_CLK"),
78 PINCTRL_PIN(29, "GSPI1_MISO"),
79 PINCTRL_PIN(30, "GSPI1_MOSI"),
80 PINCTRL_PIN(31, "SML1ALERTB"),
81 PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"),
82 PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"),
83 /* GPP_A */
84 PINCTRL_PIN(34, "ESPI_IO_0"),
85 PINCTRL_PIN(35, "ESPI_IO_1"),
86 PINCTRL_PIN(36, "ESPI_IO_2"),
87 PINCTRL_PIN(37, "ESPI_IO_3"),
88 PINCTRL_PIN(38, "ESPI_CSB"),
89 PINCTRL_PIN(39, "ESPI_CLK"),
90 PINCTRL_PIN(40, "ESPI_RESETB"),
91 PINCTRL_PIN(41, "I2S2_SCLK"),
92 PINCTRL_PIN(42, "I2S2_SFRM"),
93 PINCTRL_PIN(43, "I2S2_TXD"),
94 PINCTRL_PIN(44, "I2S2_RXD"),
95 PINCTRL_PIN(45, "SATA_DEVSLP_2"),
96 PINCTRL_PIN(46, "SATAXPCIE_1"),
97 PINCTRL_PIN(47, "SATAXPCIE_2"),
98 PINCTRL_PIN(48, "USB2_OCB_1"),
99 PINCTRL_PIN(49, "USB2_OCB_2"),
100 PINCTRL_PIN(50, "USB2_OCB_3"),
101 PINCTRL_PIN(51, "DDSP_HPD_C"),
102 PINCTRL_PIN(52, "DDSP_HPD_B"),
103 PINCTRL_PIN(53, "DDSP_HPD_1"),
104 PINCTRL_PIN(54, "DDSP_HPD_2"),
105 PINCTRL_PIN(55, "I2S5_TXD"),
106 PINCTRL_PIN(56, "I2S5_RXD"),
107 PINCTRL_PIN(57, "I2S1_SCLK"),
108 PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"),
109 /* GPP_H */
110 PINCTRL_PIN(59, "SD_1P8_SEL"),
111 PINCTRL_PIN(60, "SD_PWR_EN_B"),
112 PINCTRL_PIN(61, "GPPC_H_2"),
113 PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"),
114 PINCTRL_PIN(63, "I2C2_SDA"),
115 PINCTRL_PIN(64, "I2C2_SCL"),
116 PINCTRL_PIN(65, "I2C3_SDA"),
117 PINCTRL_PIN(66, "I2C3_SCL"),
118 PINCTRL_PIN(67, "I2C4_SDA"),
119 PINCTRL_PIN(68, "I2C4_SCL"),
120 PINCTRL_PIN(69, "SRCCLKREQB_4"),
121 PINCTRL_PIN(70, "SRCCLKREQB_5"),
122 PINCTRL_PIN(71, "M2_SKT2_CFG_0"),
123 PINCTRL_PIN(72, "M2_SKT2_CFG_1"),
124 PINCTRL_PIN(73, "M2_SKT2_CFG_2"),
125 PINCTRL_PIN(74, "M2_SKT2_CFG_3"),
126 PINCTRL_PIN(75, "DDPB_CTRLCLK"),
127 PINCTRL_PIN(76, "DDPB_CTRLDATA"),
128 PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"),
129 PINCTRL_PIN(78, "TIME_SYNC_0"),
130 PINCTRL_PIN(79, "IMGCLKOUT_1"),
131 PINCTRL_PIN(80, "IMGCLKOUT_2"),
132 PINCTRL_PIN(81, "IMGCLKOUT_3"),
133 PINCTRL_PIN(82, "IMGCLKOUT_4"),
134 /* GPP_D */
135 PINCTRL_PIN(83, "ISH_GP_0"),
136 PINCTRL_PIN(84, "ISH_GP_1"),
137 PINCTRL_PIN(85, "ISH_GP_2"),
138 PINCTRL_PIN(86, "ISH_GP_3"),
139 PINCTRL_PIN(87, "IMGCLKOUT_0"),
140 PINCTRL_PIN(88, "SRCCLKREQB_0"),
141 PINCTRL_PIN(89, "SRCCLKREQB_1"),
142 PINCTRL_PIN(90, "SRCCLKREQB_2"),
143 PINCTRL_PIN(91, "SRCCLKREQB_3"),
144 PINCTRL_PIN(92, "ISH_SPI_CSB"),
145 PINCTRL_PIN(93, "ISH_SPI_CLK"),
146 PINCTRL_PIN(94, "ISH_SPI_MISO"),
147 PINCTRL_PIN(95, "ISH_SPI_MOSI"),
148 PINCTRL_PIN(96, "ISH_UART0_RXD"),
149 PINCTRL_PIN(97, "ISH_UART0_TXD"),
150 PINCTRL_PIN(98, "ISH_UART0_RTSB"),
151 PINCTRL_PIN(99, "ISH_UART0_CTSB"),
152 PINCTRL_PIN(100, "ISH_GP_4"),
153 PINCTRL_PIN(101, "ISH_GP_5"),
154 PINCTRL_PIN(102, "I2S_MCLK"),
155 PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"),
156 /* GPP_F */
157 PINCTRL_PIN(104, "CNV_BRI_DT"),
158 PINCTRL_PIN(105, "CNV_BRI_RSP"),
159 PINCTRL_PIN(106, "CNV_RGI_DT"),
160 PINCTRL_PIN(107, "CNV_RGI_RSP"),
161 PINCTRL_PIN(108, "CNV_RF_RESET_B"),
162 PINCTRL_PIN(109, "EMMC_HIP_MON"),
163 PINCTRL_PIN(110, "CNV_PA_BLANKING"),
164 PINCTRL_PIN(111, "EMMC_CMD"),
165 PINCTRL_PIN(112, "EMMC_DATA0"),
166 PINCTRL_PIN(113, "EMMC_DATA1"),
167 PINCTRL_PIN(114, "EMMC_DATA2"),
168 PINCTRL_PIN(115, "EMMC_DATA3"),
169 PINCTRL_PIN(116, "EMMC_DATA4"),
170 PINCTRL_PIN(117, "EMMC_DATA5"),
171 PINCTRL_PIN(118, "EMMC_DATA6"),
172 PINCTRL_PIN(119, "EMMC_DATA7"),
173 PINCTRL_PIN(120, "EMMC_RCLK"),
174 PINCTRL_PIN(121, "EMMC_CLK"),
175 PINCTRL_PIN(122, "EMMC_RESETB"),
176 PINCTRL_PIN(123, "A4WP_PRESENT"),
177 /* vGPIO */
178 PINCTRL_PIN(124, "CNV_BTEN"),
179 PINCTRL_PIN(125, "CNV_WCEN"),
180 PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"),
181 PINCTRL_PIN(127, "CNV_BT_IF_SELECT"),
182 PINCTRL_PIN(128, "vCNV_BT_UART_TXD"),
183 PINCTRL_PIN(129, "vCNV_BT_UART_RXD"),
184 PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"),
185 PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"),
186 PINCTRL_PIN(132, "vCNV_MFUART1_TXD"),
187 PINCTRL_PIN(133, "vCNV_MFUART1_RXD"),
188 PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"),
189 PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"),
190 PINCTRL_PIN(136, "vUART0_TXD"),
191 PINCTRL_PIN(137, "vUART0_RXD"),
192 PINCTRL_PIN(138, "vUART0_CTS_B"),
193 PINCTRL_PIN(139, "vUART0_RTS_B"),
194 PINCTRL_PIN(140, "vISH_UART0_TXD"),
195 PINCTRL_PIN(141, "vISH_UART0_RXD"),
196 PINCTRL_PIN(142, "vISH_UART0_CTS_B"),
197 PINCTRL_PIN(143, "vISH_UART0_RTS_B"),
198 PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"),
199 PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"),
200 PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"),
201 PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"),
202 PINCTRL_PIN(148, "vI2S2_SCLK"),
203 PINCTRL_PIN(149, "vI2S2_SFRM"),
204 PINCTRL_PIN(150, "vI2S2_TXD"),
205 PINCTRL_PIN(151, "vI2S2_RXD"),
206 PINCTRL_PIN(152, "vSD3_CD_B"),
207 /* GPP_C */
208 PINCTRL_PIN(153, "SMBCLK"),
209 PINCTRL_PIN(154, "SMBDATA"),
210 PINCTRL_PIN(155, "SMBALERTB"),
211 PINCTRL_PIN(156, "SML0CLK"),
212 PINCTRL_PIN(157, "SML0DATA"),
213 PINCTRL_PIN(158, "SML0ALERTB"),
214 PINCTRL_PIN(159, "SML1CLK"),
215 PINCTRL_PIN(160, "SML1DATA"),
216 PINCTRL_PIN(161, "UART0_RXD"),
217 PINCTRL_PIN(162, "UART0_TXD"),
218 PINCTRL_PIN(163, "UART0_RTSB"),
219 PINCTRL_PIN(164, "UART0_CTSB"),
220 PINCTRL_PIN(165, "UART1_RXD"),
221 PINCTRL_PIN(166, "UART1_TXD"),
222 PINCTRL_PIN(167, "UART1_RTSB"),
223 PINCTRL_PIN(168, "UART1_CTSB"),
224 PINCTRL_PIN(169, "I2C0_SDA"),
225 PINCTRL_PIN(170, "I2C0_SCL"),
226 PINCTRL_PIN(171, "I2C1_SDA"),
227 PINCTRL_PIN(172, "I2C1_SCL"),
228 PINCTRL_PIN(173, "UART2_RXD"),
229 PINCTRL_PIN(174, "UART2_TXD"),
230 PINCTRL_PIN(175, "UART2_RTSB"),
231 PINCTRL_PIN(176, "UART2_CTSB"),
232 /* HVCMOS */
233 PINCTRL_PIN(177, "L_BKLTEN"),
234 PINCTRL_PIN(178, "L_BKLTCTL"),
235 PINCTRL_PIN(179, "L_VDDEN"),
236 PINCTRL_PIN(180, "SYS_PWROK"),
237 PINCTRL_PIN(181, "SYS_RESETB"),
238 PINCTRL_PIN(182, "MLK_RSTB"),
239 /* GPP_E */
240 PINCTRL_PIN(183, "SATAXPCIE_0"),
241 PINCTRL_PIN(184, "SPI1_IO_2"),
242 PINCTRL_PIN(185, "SPI1_IO_3"),
243 PINCTRL_PIN(186, "CPU_GP_0"),
244 PINCTRL_PIN(187, "SATA_DEVSLP_0"),
245 PINCTRL_PIN(188, "SATA_DEVSLP_1"),
246 PINCTRL_PIN(189, "GPPC_E_6"),
247 PINCTRL_PIN(190, "CPU_GP_1"),
248 PINCTRL_PIN(191, "SATA_LEDB"),
249 PINCTRL_PIN(192, "USB2_OCB_0"),
250 PINCTRL_PIN(193, "SPI1_CSB"),
251 PINCTRL_PIN(194, "SPI1_CLK"),
252 PINCTRL_PIN(195, "SPI1_MISO_IO_1"),
253 PINCTRL_PIN(196, "SPI1_MOSI_IO_0"),
254 PINCTRL_PIN(197, "DDSP_HPD_A"),
255 PINCTRL_PIN(198, "ISH_GP_6"),
256 PINCTRL_PIN(199, "ISH_GP_7"),
257 PINCTRL_PIN(200, "DISP_MISC_4"),
258 PINCTRL_PIN(201, "DDP1_CTRLCLK"),
259 PINCTRL_PIN(202, "DDP1_CTRLDATA"),
260 PINCTRL_PIN(203, "DDP2_CTRLCLK"),
261 PINCTRL_PIN(204, "DDP2_CTRLDATA"),
262 PINCTRL_PIN(205, "DDPA_CTRLCLK"),
263 PINCTRL_PIN(206, "DDPA_CTRLDATA"),
264 /* JTAG */
265 PINCTRL_PIN(207, "JTAG_TDO"),
266 PINCTRL_PIN(208, "JTAGX"),
267 PINCTRL_PIN(209, "PRDYB"),
268 PINCTRL_PIN(210, "PREQB"),
269 PINCTRL_PIN(211, "CPU_TRSTB"),
270 PINCTRL_PIN(212, "JTAG_TDI"),
271 PINCTRL_PIN(213, "JTAG_TMS"),
272 PINCTRL_PIN(214, "JTAG_TCK"),
273 PINCTRL_PIN(215, "ITP_PMODE"),
274 /* GPP_R */
275 PINCTRL_PIN(216, "HDA_BCLK"),
276 PINCTRL_PIN(217, "HDA_SYNC"),
277 PINCTRL_PIN(218, "HDA_SDO"),
278 PINCTRL_PIN(219, "HDA_SDI_0"),
279 PINCTRL_PIN(220, "HDA_RSTB"),
280 PINCTRL_PIN(221, "HDA_SDI_1"),
281 PINCTRL_PIN(222, "I2S1_TXD"),
282 PINCTRL_PIN(223, "I2S1_RXD"),
283 /* GPP_S */
284 PINCTRL_PIN(224, "SNDW1_CLK"),
285 PINCTRL_PIN(225, "SNDW1_DATA"),
286 PINCTRL_PIN(226, "SNDW2_CLK"),
287 PINCTRL_PIN(227, "SNDW2_DATA"),
288 PINCTRL_PIN(228, "SNDW3_CLK"),
289 PINCTRL_PIN(229, "SNDW3_DATA"),
290 PINCTRL_PIN(230, "SNDW4_CLK"),
291 PINCTRL_PIN(231, "SNDW4_DATA"),
292 /* SPI */
293 PINCTRL_PIN(232, "SPI0_IO_2"),
294 PINCTRL_PIN(233, "SPI0_IO_3"),
295 PINCTRL_PIN(234, "SPI0_MOSI_IO_0"),
296 PINCTRL_PIN(235, "SPI0_MISO_IO_1"),
297 PINCTRL_PIN(236, "SPI0_TPM_CSB"),
298 PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"),
299 PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"),
300 PINCTRL_PIN(239, "SPI0_CLK"),
301 PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"),
302};
303
304static const struct intel_padgroup icllp_community0_gpps[] = {
305 ICL_GPP(0, 0, 7, 0), /* GPP_G */
306 ICL_GPP(1, 8, 33, 32), /* GPP_B */
307 ICL_GPP(2, 34, 58, 64), /* GPP_A */
308};
309
310static const struct intel_padgroup icllp_community1_gpps[] = {
311 ICL_GPP(0, 59, 82, 96), /* GPP_H */
312 ICL_GPP(1, 83, 103, 128), /* GPP_D */
313 ICL_GPP(2, 104, 123, 160), /* GPP_F */
314 ICL_GPP(3, 124, 152, 192), /* vGPIO */
315};
316
317static const struct intel_padgroup icllp_community4_gpps[] = {
318 ICL_GPP(0, 153, 176, 224), /* GPP_C */
319 ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
320 ICL_GPP(2, 183, 206, 256), /* GPP_E */
321 ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
322};
323
324static const struct intel_padgroup icllp_community5_gpps[] = {
325 ICL_GPP(0, 216, 223, 288), /* GPP_R */
326 ICL_GPP(1, 224, 231, 320), /* GPP_S */
327 ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
328};
329
330static const struct intel_community icllp_communities[] = {
331 ICL_LP_COMMUNITY(0, 0, 58, icllp_community0_gpps),
332 ICL_LP_COMMUNITY(1, 59, 152, icllp_community1_gpps),
333 ICL_LP_COMMUNITY(2, 153, 215, icllp_community4_gpps),
334 ICL_LP_COMMUNITY(3, 216, 240, icllp_community5_gpps),
335};
336
337static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
338static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };
339static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };
340static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };
341static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };
342static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
343
344static const unsigned int icllp_i2c0_pins[] = { 169, 170 };
345static const unsigned int icllp_i2c1_pins[] = { 171, 172 };
346static const unsigned int icllp_i2c2_pins[] = { 63, 64 };
347static const unsigned int icllp_i2c3_pins[] = { 65, 66 };
348static const unsigned int icllp_i2c4_pins[] = { 67, 68 };
349
350static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };
351static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };
352static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };
353
354static const struct intel_pingroup icllp_groups[] = {
355 PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes),
356 PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes),
357 PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes),
358 PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1),
359 PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1),
360 PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1),
361 PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1),
362 PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1),
363 PIN_GROUP("uart0_grp", icllp_uart0_pins, 1),
364 PIN_GROUP("uart1_grp", icllp_uart1_pins, 1),
365 PIN_GROUP("uart2_grp", icllp_uart2_pins, 1),
366};
367
368static const char * const icllp_spi0_groups[] = { "spi0_grp" };
369static const char * const icllp_spi1_groups[] = { "spi1_grp" };
370static const char * const icllp_spi2_groups[] = { "spi2_grp" };
371static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };
372static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };
373static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };
374static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };
375static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };
376static const char * const icllp_uart0_groups[] = { "uart0_grp" };
377static const char * const icllp_uart1_groups[] = { "uart1_grp" };
378static const char * const icllp_uart2_groups[] = { "uart2_grp" };
379
380static const struct intel_function icllp_functions[] = {
381 FUNCTION("spi0", icllp_spi0_groups),
382 FUNCTION("spi1", icllp_spi1_groups),
383 FUNCTION("spi2", icllp_spi2_groups),
384 FUNCTION("i2c0", icllp_i2c0_groups),
385 FUNCTION("i2c1", icllp_i2c1_groups),
386 FUNCTION("i2c2", icllp_i2c2_groups),
387 FUNCTION("i2c3", icllp_i2c3_groups),
388 FUNCTION("i2c4", icllp_i2c4_groups),
389 FUNCTION("uart0", icllp_uart0_groups),
390 FUNCTION("uart1", icllp_uart1_groups),
391 FUNCTION("uart2", icllp_uart2_groups),
392};
393
394static const struct intel_pinctrl_soc_data icllp_soc_data = {
395 .pins = icllp_pins,
396 .npins = ARRAY_SIZE(icllp_pins),
397 .groups = icllp_groups,
398 .ngroups = ARRAY_SIZE(icllp_groups),
399 .functions = icllp_functions,
400 .nfunctions = ARRAY_SIZE(icllp_functions),
401 .communities = icllp_communities,
402 .ncommunities = ARRAY_SIZE(icllp_communities),
403};
404
405/* Ice Lake-N */
406static const struct pinctrl_pin_desc icln_pins[] = {
407 /* SPI */
408 PINCTRL_PIN(0, "SPI0_IO_2"),
409 PINCTRL_PIN(1, "SPI0_IO_3"),
410 PINCTRL_PIN(2, "SPI0_MOSI_IO_0"),
411 PINCTRL_PIN(3, "SPI0_MISO_IO_1"),
412 PINCTRL_PIN(4, "SPI0_TPM_CSB"),
413 PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"),
414 PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"),
415 PINCTRL_PIN(7, "SPI0_CLK"),
416 PINCTRL_PIN(8, "SPI0_CLK_LOOPBK"),
417 /* GPP_B */
418 PINCTRL_PIN(9, "CORE_VID_0"),
419 PINCTRL_PIN(10, "CORE_VID_1"),
420 PINCTRL_PIN(11, "VRALERTB"),
421 PINCTRL_PIN(12, "CPU_GP_2"),
422 PINCTRL_PIN(13, "CPU_GP_3"),
423 PINCTRL_PIN(14, "SRCCLKREQB_0"),
424 PINCTRL_PIN(15, "SRCCLKREQB_1"),
425 PINCTRL_PIN(16, "SRCCLKREQB_2"),
426 PINCTRL_PIN(17, "SRCCLKREQB_3"),
427 PINCTRL_PIN(18, "SRCCLKREQB_4"),
428 PINCTRL_PIN(19, "SRCCLKREQB_5"),
429 PINCTRL_PIN(20, "EXT_PWR_GATEB"),
430 PINCTRL_PIN(21, "SLP_S0B"),
431 PINCTRL_PIN(22, "PLTRSTB"),
432 PINCTRL_PIN(23, "SPKR_GSPI0_CS1B"),
433 PINCTRL_PIN(24, "GSPI0_CS0B"),
434 PINCTRL_PIN(25, "GSPI0_CLK"),
435 PINCTRL_PIN(26, "GSPI0_MISO_TBT_LSX3_A"),
436 PINCTRL_PIN(27, "GSPI0_MOSI_TBT_LSX3_B"),
437 PINCTRL_PIN(28, "GSPI1_CS0B"),
438 PINCTRL_PIN(29, "GSPI1_CLK_NFC_CLK"),
439 PINCTRL_PIN(30, "GSPI1_MISO_NFC_CLKREQ"),
440 PINCTRL_PIN(31, "GSPI1_MOSI"),
441 PINCTRL_PIN(32, "GSPI1_CS1B"),
442 PINCTRL_PIN(33, "GSPI0_CLK_LOOPBK"),
443 PINCTRL_PIN(34, "GSPI1_CLK_LOOPBK"),
444 /* GPP_A */
445 PINCTRL_PIN(35, "ESPI_IO_0"),
446 PINCTRL_PIN(36, "ESPI_IO_1"),
447 PINCTRL_PIN(37, "ESPI_IO_2"),
448 PINCTRL_PIN(38, "ESPI_IO_3"),
449 PINCTRL_PIN(39, "ESPI_CSB"),
450 PINCTRL_PIN(40, "ESPI_CLK"),
451 PINCTRL_PIN(41, "ESPI_RESETB"),
452 PINCTRL_PIN(42, "SMBCLK"),
453 PINCTRL_PIN(43, "SMBDATA"),
454 PINCTRL_PIN(44, "SMBALERTB"),
455 PINCTRL_PIN(45, "CPU_GP_0"),
456 PINCTRL_PIN(46, "CPU_GP_1"),
457 PINCTRL_PIN(47, "USB2_OCB_1"),
458 PINCTRL_PIN(48, "USB2_OCB_2"),
459 PINCTRL_PIN(49, "USB2_OCB_3"),
460 PINCTRL_PIN(50, "DDSP_HPD_A_TIME_SYNC_0"),
461 PINCTRL_PIN(51, "DDSP_HPD_B_TIME_SYNC_1"),
462 PINCTRL_PIN(52, "DDSP_HPD_C"),
463 PINCTRL_PIN(53, "USB2_OCB_0"),
464 PINCTRL_PIN(54, "PCHHOTB"),
465 PINCTRL_PIN(55, "ESPI_CLK_LOOPBK"),
466 /* GPP_S */
467 PINCTRL_PIN(56, "SNDW1_CLK"),
468 PINCTRL_PIN(57, "SNDW1_DATA"),
469 PINCTRL_PIN(58, "SNDW2_CLK"),
470 PINCTRL_PIN(59, "SNDW2_DATA"),
471 PINCTRL_PIN(60, "SNDW3_CLK_DMIC_CLK_1"),
472 PINCTRL_PIN(61, "SNDW3_DATA_DMIC_DATA_1"),
473 PINCTRL_PIN(62, "SNDW4_CLK_DMIC_CLK_0"),
474 PINCTRL_PIN(63, "SNDW4_DATA_DMIC_DATA_0"),
475 /* GPP_R */
476 PINCTRL_PIN(64, "HDA_BCLK"),
477 PINCTRL_PIN(65, "HDA_SYNC"),
478 PINCTRL_PIN(66, "HDA_SDO"),
479 PINCTRL_PIN(67, "HDA_SDI_0"),
480 PINCTRL_PIN(68, "HDA_RSTB"),
481 PINCTRL_PIN(69, "HDA_SDI_1_I2S1_RXD"),
482 PINCTRL_PIN(70, "I2S1_SFRM"),
483 PINCTRL_PIN(71, "I2S1_TXD"),
484 /* GPP_H */
485 PINCTRL_PIN(72, "GPPC_H_0"),
486 PINCTRL_PIN(73, "CNV_RF_RESET_B"),
487 PINCTRL_PIN(74, "MODEM_CLKREQ"),
488 PINCTRL_PIN(75, "SX_EXIT_HOLDOFFB"),
489 PINCTRL_PIN(76, "I2C2_SDA"),
490 PINCTRL_PIN(77, "I2C2_SCL"),
491 PINCTRL_PIN(78, "I2C3_SDA"),
492 PINCTRL_PIN(79, "I2C3_SCL"),
493 PINCTRL_PIN(80, "I2C4_SDA"),
494 PINCTRL_PIN(81, "I2C4_SCL"),
495 PINCTRL_PIN(82, "CPU_VCCIO_PWR_GATEB"),
496 PINCTRL_PIN(83, "I2S2_SCLK"),
497 PINCTRL_PIN(84, "CNV_RF_RESET_B"),
498 PINCTRL_PIN(85, "MODEM_CLKREQ"),
499 PINCTRL_PIN(86, "I2S2_RXD"),
500 PINCTRL_PIN(87, "I2S1_SCLK"),
501 PINCTRL_PIN(88, "GPPC_H_16"),
502 PINCTRL_PIN(89, "GPPC_H_17"),
503 PINCTRL_PIN(90, "GPPC_H_18"),
504 PINCTRL_PIN(91, "GPPC_H_19"),
505 PINCTRL_PIN(92, "GPPC_H_20"),
506 PINCTRL_PIN(93, "GPPC_H_21"),
507 PINCTRL_PIN(94, "GPPC_H_22"),
508 PINCTRL_PIN(95, "GPPC_H_23"),
509 /* GPP_D */
510 PINCTRL_PIN(96, "SPI1_CSB_BK_0_SBK_0"),
511 PINCTRL_PIN(97, "SPI1_CLK_BK_1_SBK_1"),
512 PINCTRL_PIN(98, "SPI1_MISO_IO_1_BK_2_SBK_2"),
513 PINCTRL_PIN(99, "SPI1_MOSI_IO_0_BK_3_SBK_3"),
514 PINCTRL_PIN(100, "ISH_I2C0_SDA"),
515 PINCTRL_PIN(101, "ISH_I2C0_SCL"),
516 PINCTRL_PIN(102, "ISH_I2C1_SDA"),
517 PINCTRL_PIN(103, "ISH_I2C1_SCL"),
518 PINCTRL_PIN(104, "ISH_SPI_CSB_GSPI2_CS0B_TBT_LSX4_A"),
519 PINCTRL_PIN(105, "ISH_SPI_CLK_GSPI2_CLK_TBT_LSX4_B"),
520 PINCTRL_PIN(106, "ISH_SPI_MISO_GSPI2_MISO_TBT_LSX5_A"),
521 PINCTRL_PIN(107, "ISH_SPI_MOSI_GSPI2_MOSI_TBT_LSX5_B"),
522 PINCTRL_PIN(108, "ISH_UART0_RXD_I2C4B_SDA"),
523 PINCTRL_PIN(109, "ISH_UART0_TXD_I2C4B_SCL"),
524 PINCTRL_PIN(110, "ISH_UART0_RTSB_GSPI2_CS1B"),
525 PINCTRL_PIN(111, "ISH_UART0_CTSB_CNV_WCEN"),
526 PINCTRL_PIN(112, "SPI1_IO_2"),
527 PINCTRL_PIN(113, "SPI1_IO_3"),
528 PINCTRL_PIN(114, "I2S_MCLK"),
529 PINCTRL_PIN(115, "CNV_MFUART2_RXD"),
530 PINCTRL_PIN(116, "CNV_MFUART2_TXD"),
531 PINCTRL_PIN(117, "CNV_PA_BLANKING"),
532 PINCTRL_PIN(118, "I2C5_SDA_ISH_I2C2_SDA"),
533 PINCTRL_PIN(119, "I2C5_SCL_ISH_I2C2_SCL"),
534 PINCTRL_PIN(120, "GSPI2_CLK_LOOPBK"),
535 PINCTRL_PIN(121, "SPI1_CLK_LOOPBK"),
536 /* vGPIO */
537 PINCTRL_PIN(122, "CNV_BTEN"),
538 PINCTRL_PIN(123, "CNV_WCEN"),
539 PINCTRL_PIN(124, "CNV_BT_HOST_WAKEB"),
540 PINCTRL_PIN(125, "CNV_BT_IF_SELECT"),
541 PINCTRL_PIN(126, "vCNV_BT_UART_TXD"),
542 PINCTRL_PIN(127, "vCNV_BT_UART_RXD"),
543 PINCTRL_PIN(128, "vCNV_BT_UART_CTS_B"),
544 PINCTRL_PIN(129, "vCNV_BT_UART_RTS_B"),
545 PINCTRL_PIN(130, "vCNV_MFUART1_TXD"),
546 PINCTRL_PIN(131, "vCNV_MFUART1_RXD"),
547 PINCTRL_PIN(132, "vCNV_MFUART1_CTS_B"),
548 PINCTRL_PIN(133, "vCNV_MFUART1_RTS_B"),
549 PINCTRL_PIN(134, "vUART0_TXD"),
550 PINCTRL_PIN(135, "vUART0_RXD"),
551 PINCTRL_PIN(136, "vUART0_CTS_B"),
552 PINCTRL_PIN(137, "vUART0_RTS_B"),
553 PINCTRL_PIN(138, "vISH_UART0_TXD"),
554 PINCTRL_PIN(139, "vISH_UART0_RXD"),
555 PINCTRL_PIN(140, "vISH_UART0_CTS_B"),
556 PINCTRL_PIN(141, "vISH_UART0_RTS_B"),
557 PINCTRL_PIN(142, "vCNV_BT_I2S_BCLK"),
558 PINCTRL_PIN(143, "vCNV_BT_I2S_WS_SYNC"),
559 PINCTRL_PIN(144, "vCNV_BT_I2S_SDO"),
560 PINCTRL_PIN(145, "vCNV_BT_I2S_SDI"),
561 PINCTRL_PIN(146, "vI2S2_SCLK"),
562 PINCTRL_PIN(147, "vI2S2_SFRM"),
563 PINCTRL_PIN(148, "vI2S2_TXD"),
564 PINCTRL_PIN(149, "vI2S2_RXD"),
565 PINCTRL_PIN(150, "vSD3_CD_B"),
566 /* GPP_C */
567 PINCTRL_PIN(151, "GPPC_C_0"),
568 PINCTRL_PIN(152, "GPPC_C_1"),
569 PINCTRL_PIN(153, "GPPC_C_2"),
570 PINCTRL_PIN(154, "GPPC_C_3"),
571 PINCTRL_PIN(155, "GPPC_C_4"),
572 PINCTRL_PIN(156, "GPPC_C_5"),
573 PINCTRL_PIN(157, "SUSWARNB_SUSPWRDNACK"),
574 PINCTRL_PIN(158, "SUSACKB"),
575 PINCTRL_PIN(159, "UART0_RXD"),
576 PINCTRL_PIN(160, "UART0_TXD"),
577 PINCTRL_PIN(161, "UART0_RTSB"),
578 PINCTRL_PIN(162, "UART0_CTSB"),
579 PINCTRL_PIN(163, "UART1_RXD_ISH_UART1_RXD"),
580 PINCTRL_PIN(164, "UART1_TXD_ISH_UART1_TXD"),
581 PINCTRL_PIN(165, "UART1_RTSB_ISH_UART1_RTSB"),
582 PINCTRL_PIN(166, "UART1_CTSB_ISH_UART1_CTSB"),
583 PINCTRL_PIN(167, "I2C0_SDA"),
584 PINCTRL_PIN(168, "I2C0_SCL"),
585 PINCTRL_PIN(169, "I2C1_SDA"),
586 PINCTRL_PIN(170, "I2C1_SCL"),
587 PINCTRL_PIN(171, "UART2_RXD_CNV_MFUART0_RXD"),
588 PINCTRL_PIN(172, "UART2_TXD_CNV_MFUART0_TXD"),
589 PINCTRL_PIN(173, "UART2_RTSB_CNV_MFUART0_RTS_B"),
590 PINCTRL_PIN(174, "UART2_CTSB_CNV_MFUART0_CTS_B"),
591 /* HVCMOS */
592 PINCTRL_PIN(175, "L_BKLTEN"),
593 PINCTRL_PIN(176, "L_BKLTCTL"),
594 PINCTRL_PIN(177, "L_VDDEN"),
595 PINCTRL_PIN(178, "SYS_PWROK"),
596 PINCTRL_PIN(179, "SYS_RESETB"),
597 PINCTRL_PIN(180, "MLK_RSTB"),
598 /* GPP_E */
599 PINCTRL_PIN(181, "ISH_GP_0_IMGCLKOUT_0"),
600 PINCTRL_PIN(182, "ISH_GP_1"),
601 PINCTRL_PIN(183, "IMGCLKOUT_1"),
602 PINCTRL_PIN(184, "ISH_GP_2_SATA_DEVSLP_0"),
603 PINCTRL_PIN(185, "IMGCLKOUT_2"),
604 PINCTRL_PIN(186, "SATA_LEDB_SPI1_CS1B"),
605 PINCTRL_PIN(187, "IMGCLKOUT_3"),
606 PINCTRL_PIN(188, "ISH_GP_3_SATA_DEVSLP_1"),
607 PINCTRL_PIN(189, "FIVR_DIGPB_0"),
608 PINCTRL_PIN(190, "SML0CLK"),
609 PINCTRL_PIN(191, "SML0DATA"),
610 PINCTRL_PIN(192, "BSSB_LS3_RX"),
611 PINCTRL_PIN(193, "BSSB_LS3_TX"),
612 PINCTRL_PIN(194, "BSSB_LS0_RX"),
613 PINCTRL_PIN(195, "BSSB_LS0_TX"),
614 PINCTRL_PIN(196, "BSSB_LS1_RX"),
615 PINCTRL_PIN(197, "BSSB_LS1_TX"),
616 PINCTRL_PIN(198, "BSSB_LS2_RX"),
617 PINCTRL_PIN(199, "BSSB_LS2_TX"),
618 PINCTRL_PIN(200, "FIVR_DIGPB_1"),
619 PINCTRL_PIN(201, "CNV_BRI_DT"),
620 PINCTRL_PIN(202, "CNV_BRI_RSP"),
621 PINCTRL_PIN(203, "CNV_RGI_DT"),
622 PINCTRL_PIN(204, "CNV_RGI_RSP"),
623 /* GPP_G */
624 PINCTRL_PIN(205, "SD3_CMD"),
625 PINCTRL_PIN(206, "SD3_D0"),
626 PINCTRL_PIN(207, "SD3_D1"),
627 PINCTRL_PIN(208, "SD3_D2"),
628 PINCTRL_PIN(209, "SD3_D3"),
629 PINCTRL_PIN(210, "SD3_CDB"),
630 PINCTRL_PIN(211, "SD3_CLK"),
631 PINCTRL_PIN(212, "SD3_WP"),
632};
633
634static const struct intel_padgroup icln_community0_gpps[] = {
635 ICL_GPP(0, 0, 8, INTEL_GPIO_BASE_NOMAP), /* SPI */
636 ICL_GPP(1, 9, 34, 32), /* GPP_B */
637 ICL_GPP(2, 35, 55, 64), /* GPP_A */
638 ICL_GPP(3, 56, 63, 96), /* GPP_S */
639 ICL_GPP(4, 64, 71, 128), /* GPP_R */
640};
641
642static const struct intel_padgroup icln_community1_gpps[] = {
643 ICL_GPP(0, 72, 95, 160), /* GPP_H */
644 ICL_GPP(1, 96, 121, 192), /* GPP_D */
645 ICL_GPP(2, 122, 150, 224), /* vGPIO */
646 ICL_GPP(3, 151, 174, 256), /* GPP_C */
647};
648
649static const struct intel_padgroup icln_community4_gpps[] = {
650 ICL_GPP(0, 175, 180, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
651 ICL_GPP(1, 181, 204, 288), /* GPP_E */
652};
653
654static const struct intel_padgroup icln_community5_gpps[] = {
655 ICL_GPP(0, 205, 212, INTEL_GPIO_BASE_ZERO), /* GPP_G */
656};
657
658static const struct intel_community icln_communities[] = {
659 ICL_N_COMMUNITY(0, 0, 71, icln_community0_gpps),
660 ICL_N_COMMUNITY(1, 72, 174, icln_community1_gpps),
661 ICL_N_COMMUNITY(2, 175, 204, icln_community4_gpps),
662 ICL_N_COMMUNITY(3, 205, 212, icln_community5_gpps),
663};
664
665static const struct intel_pinctrl_soc_data icln_soc_data = {
666 .pins = icln_pins,
667 .npins = ARRAY_SIZE(icln_pins),
668 .communities = icln_communities,
669 .ncommunities = ARRAY_SIZE(icln_communities),
670};
671
672static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
673 { "INT3455", (kernel_ulong_t)&icllp_soc_data },
674 { "INT34C3", (kernel_ulong_t)&icln_soc_data },
675 { }
676};
677MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
678
679static struct platform_driver icl_pinctrl_driver = {
680 .probe = intel_pinctrl_probe_by_hid,
681 .driver = {
682 .name = "icelake-pinctrl",
683 .acpi_match_table = icl_pinctrl_acpi_match,
684 .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
685 },
686};
687module_platform_driver(icl_pinctrl_driver);
688
689MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
690MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
691MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver");
692MODULE_LICENSE("GPL v2");
693MODULE_IMPORT_NS(PINCTRL_INTEL);