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1/*
2 * Base driver for Maxim MAX8925
3 *
4 * Copyright (C) 2009-2010 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/i2c.h>
15#include <linux/irq.h>
16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18#include <linux/mfd/core.h>
19#include <linux/mfd/max8925.h>
20
21static struct resource backlight_resources[] = {
22 {
23 .name = "max8925-backlight",
24 .start = MAX8925_WLED_MODE_CNTL,
25 .end = MAX8925_WLED_CNTL,
26 .flags = IORESOURCE_IO,
27 },
28};
29
30static struct mfd_cell backlight_devs[] = {
31 {
32 .name = "max8925-backlight",
33 .num_resources = 1,
34 .resources = &backlight_resources[0],
35 .id = -1,
36 },
37};
38
39static struct resource touch_resources[] = {
40 {
41 .name = "max8925-tsc",
42 .start = MAX8925_TSC_IRQ,
43 .end = MAX8925_ADC_RES_END,
44 .flags = IORESOURCE_IO,
45 },
46};
47
48static struct mfd_cell touch_devs[] = {
49 {
50 .name = "max8925-touch",
51 .num_resources = 1,
52 .resources = &touch_resources[0],
53 .id = -1,
54 },
55};
56
57static struct resource power_supply_resources[] = {
58 {
59 .name = "max8925-power",
60 .start = MAX8925_CHG_IRQ1,
61 .end = MAX8925_CHG_IRQ1_MASK,
62 .flags = IORESOURCE_IO,
63 },
64};
65
66static struct mfd_cell power_devs[] = {
67 {
68 .name = "max8925-power",
69 .num_resources = 1,
70 .resources = &power_supply_resources[0],
71 .id = -1,
72 },
73};
74
75static struct resource rtc_resources[] = {
76 {
77 .name = "max8925-rtc",
78 .start = MAX8925_RTC_IRQ,
79 .end = MAX8925_RTC_IRQ_MASK,
80 .flags = IORESOURCE_IO,
81 },
82};
83
84static struct mfd_cell rtc_devs[] = {
85 {
86 .name = "max8925-rtc",
87 .num_resources = 1,
88 .resources = &rtc_resources[0],
89 .id = -1,
90 },
91};
92
93static struct resource onkey_resources[] = {
94 {
95 .name = "max8925-onkey",
96 .start = MAX8925_IRQ_GPM_SW_R,
97 .end = MAX8925_IRQ_GPM_SW_R,
98 .flags = IORESOURCE_IRQ,
99 }, {
100 .name = "max8925-onkey",
101 .start = MAX8925_IRQ_GPM_SW_F,
102 .end = MAX8925_IRQ_GPM_SW_F,
103 .flags = IORESOURCE_IRQ,
104 },
105};
106
107static struct mfd_cell onkey_devs[] = {
108 {
109 .name = "max8925-onkey",
110 .num_resources = 2,
111 .resources = &onkey_resources[0],
112 .id = -1,
113 },
114};
115
116#define MAX8925_REG_RESOURCE(_start, _end) \
117{ \
118 .start = MAX8925_##_start, \
119 .end = MAX8925_##_end, \
120 .flags = IORESOURCE_IO, \
121}
122
123static struct resource regulator_resources[] = {
124 MAX8925_REG_RESOURCE(SDCTL1, SDCTL1),
125 MAX8925_REG_RESOURCE(SDCTL2, SDCTL2),
126 MAX8925_REG_RESOURCE(SDCTL3, SDCTL3),
127 MAX8925_REG_RESOURCE(LDOCTL1, LDOCTL1),
128 MAX8925_REG_RESOURCE(LDOCTL2, LDOCTL2),
129 MAX8925_REG_RESOURCE(LDOCTL3, LDOCTL3),
130 MAX8925_REG_RESOURCE(LDOCTL4, LDOCTL4),
131 MAX8925_REG_RESOURCE(LDOCTL5, LDOCTL5),
132 MAX8925_REG_RESOURCE(LDOCTL6, LDOCTL6),
133 MAX8925_REG_RESOURCE(LDOCTL7, LDOCTL7),
134 MAX8925_REG_RESOURCE(LDOCTL8, LDOCTL8),
135 MAX8925_REG_RESOURCE(LDOCTL9, LDOCTL9),
136 MAX8925_REG_RESOURCE(LDOCTL10, LDOCTL10),
137 MAX8925_REG_RESOURCE(LDOCTL11, LDOCTL11),
138 MAX8925_REG_RESOURCE(LDOCTL12, LDOCTL12),
139 MAX8925_REG_RESOURCE(LDOCTL13, LDOCTL13),
140 MAX8925_REG_RESOURCE(LDOCTL14, LDOCTL14),
141 MAX8925_REG_RESOURCE(LDOCTL15, LDOCTL15),
142 MAX8925_REG_RESOURCE(LDOCTL16, LDOCTL16),
143 MAX8925_REG_RESOURCE(LDOCTL17, LDOCTL17),
144 MAX8925_REG_RESOURCE(LDOCTL18, LDOCTL18),
145 MAX8925_REG_RESOURCE(LDOCTL19, LDOCTL19),
146 MAX8925_REG_RESOURCE(LDOCTL20, LDOCTL20),
147};
148
149#define MAX8925_REG_DEVS(_id) \
150{ \
151 .name = "max8925-regulator", \
152 .num_resources = 1, \
153 .resources = ®ulator_resources[MAX8925_ID_##_id], \
154 .id = MAX8925_ID_##_id, \
155}
156
157static struct mfd_cell regulator_devs[] = {
158 MAX8925_REG_DEVS(SD1),
159 MAX8925_REG_DEVS(SD2),
160 MAX8925_REG_DEVS(SD3),
161 MAX8925_REG_DEVS(LDO1),
162 MAX8925_REG_DEVS(LDO2),
163 MAX8925_REG_DEVS(LDO3),
164 MAX8925_REG_DEVS(LDO4),
165 MAX8925_REG_DEVS(LDO5),
166 MAX8925_REG_DEVS(LDO6),
167 MAX8925_REG_DEVS(LDO7),
168 MAX8925_REG_DEVS(LDO8),
169 MAX8925_REG_DEVS(LDO9),
170 MAX8925_REG_DEVS(LDO10),
171 MAX8925_REG_DEVS(LDO11),
172 MAX8925_REG_DEVS(LDO12),
173 MAX8925_REG_DEVS(LDO13),
174 MAX8925_REG_DEVS(LDO14),
175 MAX8925_REG_DEVS(LDO15),
176 MAX8925_REG_DEVS(LDO16),
177 MAX8925_REG_DEVS(LDO17),
178 MAX8925_REG_DEVS(LDO18),
179 MAX8925_REG_DEVS(LDO19),
180 MAX8925_REG_DEVS(LDO20),
181};
182
183enum {
184 FLAGS_ADC = 1, /* register in ADC component */
185 FLAGS_RTC, /* register in RTC component */
186};
187
188struct max8925_irq_data {
189 int reg;
190 int mask_reg;
191 int enable; /* enable or not */
192 int offs; /* bit offset in mask register */
193 int flags;
194 int tsc_irq;
195};
196
197static struct max8925_irq_data max8925_irqs[] = {
198 [MAX8925_IRQ_VCHG_DC_OVP] = {
199 .reg = MAX8925_CHG_IRQ1,
200 .mask_reg = MAX8925_CHG_IRQ1_MASK,
201 .offs = 1 << 0,
202 },
203 [MAX8925_IRQ_VCHG_DC_F] = {
204 .reg = MAX8925_CHG_IRQ1,
205 .mask_reg = MAX8925_CHG_IRQ1_MASK,
206 .offs = 1 << 1,
207 },
208 [MAX8925_IRQ_VCHG_DC_R] = {
209 .reg = MAX8925_CHG_IRQ1,
210 .mask_reg = MAX8925_CHG_IRQ1_MASK,
211 .offs = 1 << 2,
212 },
213 [MAX8925_IRQ_VCHG_USB_OVP] = {
214 .reg = MAX8925_CHG_IRQ1,
215 .mask_reg = MAX8925_CHG_IRQ1_MASK,
216 .offs = 1 << 3,
217 },
218 [MAX8925_IRQ_VCHG_USB_F] = {
219 .reg = MAX8925_CHG_IRQ1,
220 .mask_reg = MAX8925_CHG_IRQ1_MASK,
221 .offs = 1 << 4,
222 },
223 [MAX8925_IRQ_VCHG_USB_R] = {
224 .reg = MAX8925_CHG_IRQ1,
225 .mask_reg = MAX8925_CHG_IRQ1_MASK,
226 .offs = 1 << 5,
227 },
228 [MAX8925_IRQ_VCHG_THM_OK_R] = {
229 .reg = MAX8925_CHG_IRQ2,
230 .mask_reg = MAX8925_CHG_IRQ2_MASK,
231 .offs = 1 << 0,
232 },
233 [MAX8925_IRQ_VCHG_THM_OK_F] = {
234 .reg = MAX8925_CHG_IRQ2,
235 .mask_reg = MAX8925_CHG_IRQ2_MASK,
236 .offs = 1 << 1,
237 },
238 [MAX8925_IRQ_VCHG_SYSLOW_F] = {
239 .reg = MAX8925_CHG_IRQ2,
240 .mask_reg = MAX8925_CHG_IRQ2_MASK,
241 .offs = 1 << 2,
242 },
243 [MAX8925_IRQ_VCHG_SYSLOW_R] = {
244 .reg = MAX8925_CHG_IRQ2,
245 .mask_reg = MAX8925_CHG_IRQ2_MASK,
246 .offs = 1 << 3,
247 },
248 [MAX8925_IRQ_VCHG_RST] = {
249 .reg = MAX8925_CHG_IRQ2,
250 .mask_reg = MAX8925_CHG_IRQ2_MASK,
251 .offs = 1 << 4,
252 },
253 [MAX8925_IRQ_VCHG_DONE] = {
254 .reg = MAX8925_CHG_IRQ2,
255 .mask_reg = MAX8925_CHG_IRQ2_MASK,
256 .offs = 1 << 5,
257 },
258 [MAX8925_IRQ_VCHG_TOPOFF] = {
259 .reg = MAX8925_CHG_IRQ2,
260 .mask_reg = MAX8925_CHG_IRQ2_MASK,
261 .offs = 1 << 6,
262 },
263 [MAX8925_IRQ_VCHG_TMR_FAULT] = {
264 .reg = MAX8925_CHG_IRQ2,
265 .mask_reg = MAX8925_CHG_IRQ2_MASK,
266 .offs = 1 << 7,
267 },
268 [MAX8925_IRQ_GPM_RSTIN] = {
269 .reg = MAX8925_ON_OFF_IRQ1,
270 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
271 .offs = 1 << 0,
272 },
273 [MAX8925_IRQ_GPM_MPL] = {
274 .reg = MAX8925_ON_OFF_IRQ1,
275 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
276 .offs = 1 << 1,
277 },
278 [MAX8925_IRQ_GPM_SW_3SEC] = {
279 .reg = MAX8925_ON_OFF_IRQ1,
280 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
281 .offs = 1 << 2,
282 },
283 [MAX8925_IRQ_GPM_EXTON_F] = {
284 .reg = MAX8925_ON_OFF_IRQ1,
285 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
286 .offs = 1 << 3,
287 },
288 [MAX8925_IRQ_GPM_EXTON_R] = {
289 .reg = MAX8925_ON_OFF_IRQ1,
290 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
291 .offs = 1 << 4,
292 },
293 [MAX8925_IRQ_GPM_SW_1SEC] = {
294 .reg = MAX8925_ON_OFF_IRQ1,
295 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
296 .offs = 1 << 5,
297 },
298 [MAX8925_IRQ_GPM_SW_F] = {
299 .reg = MAX8925_ON_OFF_IRQ1,
300 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
301 .offs = 1 << 6,
302 },
303 [MAX8925_IRQ_GPM_SW_R] = {
304 .reg = MAX8925_ON_OFF_IRQ1,
305 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
306 .offs = 1 << 7,
307 },
308 [MAX8925_IRQ_GPM_SYSCKEN_F] = {
309 .reg = MAX8925_ON_OFF_IRQ2,
310 .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
311 .offs = 1 << 0,
312 },
313 [MAX8925_IRQ_GPM_SYSCKEN_R] = {
314 .reg = MAX8925_ON_OFF_IRQ2,
315 .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
316 .offs = 1 << 1,
317 },
318 [MAX8925_IRQ_RTC_ALARM1] = {
319 .reg = MAX8925_RTC_IRQ,
320 .mask_reg = MAX8925_RTC_IRQ_MASK,
321 .offs = 1 << 2,
322 .flags = FLAGS_RTC,
323 },
324 [MAX8925_IRQ_RTC_ALARM0] = {
325 .reg = MAX8925_RTC_IRQ,
326 .mask_reg = MAX8925_RTC_IRQ_MASK,
327 .offs = 1 << 3,
328 .flags = FLAGS_RTC,
329 },
330 [MAX8925_IRQ_TSC_STICK] = {
331 .reg = MAX8925_TSC_IRQ,
332 .mask_reg = MAX8925_TSC_IRQ_MASK,
333 .offs = 1 << 0,
334 .flags = FLAGS_ADC,
335 .tsc_irq = 1,
336 },
337 [MAX8925_IRQ_TSC_NSTICK] = {
338 .reg = MAX8925_TSC_IRQ,
339 .mask_reg = MAX8925_TSC_IRQ_MASK,
340 .offs = 1 << 1,
341 .flags = FLAGS_ADC,
342 .tsc_irq = 1,
343 },
344};
345
346static inline struct max8925_irq_data *irq_to_max8925(struct max8925_chip *chip,
347 int irq)
348{
349 return &max8925_irqs[irq - chip->irq_base];
350}
351
352static irqreturn_t max8925_irq(int irq, void *data)
353{
354 struct max8925_chip *chip = data;
355 struct max8925_irq_data *irq_data;
356 struct i2c_client *i2c;
357 int read_reg = -1, value = 0;
358 int i;
359
360 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
361 irq_data = &max8925_irqs[i];
362 /* TSC IRQ should be serviced in max8925_tsc_irq() */
363 if (irq_data->tsc_irq)
364 continue;
365 if (irq_data->flags == FLAGS_RTC)
366 i2c = chip->rtc;
367 else if (irq_data->flags == FLAGS_ADC)
368 i2c = chip->adc;
369 else
370 i2c = chip->i2c;
371 if (read_reg != irq_data->reg) {
372 read_reg = irq_data->reg;
373 value = max8925_reg_read(i2c, irq_data->reg);
374 }
375 if (value & irq_data->enable)
376 handle_nested_irq(chip->irq_base + i);
377 }
378 return IRQ_HANDLED;
379}
380
381static irqreturn_t max8925_tsc_irq(int irq, void *data)
382{
383 struct max8925_chip *chip = data;
384 struct max8925_irq_data *irq_data;
385 struct i2c_client *i2c;
386 int read_reg = -1, value = 0;
387 int i;
388
389 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
390 irq_data = &max8925_irqs[i];
391 /* non TSC IRQ should be serviced in max8925_irq() */
392 if (!irq_data->tsc_irq)
393 continue;
394 if (irq_data->flags == FLAGS_RTC)
395 i2c = chip->rtc;
396 else if (irq_data->flags == FLAGS_ADC)
397 i2c = chip->adc;
398 else
399 i2c = chip->i2c;
400 if (read_reg != irq_data->reg) {
401 read_reg = irq_data->reg;
402 value = max8925_reg_read(i2c, irq_data->reg);
403 }
404 if (value & irq_data->enable)
405 handle_nested_irq(chip->irq_base + i);
406 }
407 return IRQ_HANDLED;
408}
409
410static void max8925_irq_lock(struct irq_data *data)
411{
412 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
413
414 mutex_lock(&chip->irq_lock);
415}
416
417static void max8925_irq_sync_unlock(struct irq_data *data)
418{
419 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
420 struct max8925_irq_data *irq_data;
421 static unsigned char cache_chg[2] = {0xff, 0xff};
422 static unsigned char cache_on[2] = {0xff, 0xff};
423 static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
424 unsigned char irq_chg[2], irq_on[2];
425 unsigned char irq_rtc, irq_tsc;
426 int i;
427
428 /* Load cached value. In initial, all IRQs are masked */
429 irq_chg[0] = cache_chg[0];
430 irq_chg[1] = cache_chg[1];
431 irq_on[0] = cache_on[0];
432 irq_on[1] = cache_on[1];
433 irq_rtc = cache_rtc;
434 irq_tsc = cache_tsc;
435 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
436 irq_data = &max8925_irqs[i];
437 /* 1 -- disable, 0 -- enable */
438 switch (irq_data->mask_reg) {
439 case MAX8925_CHG_IRQ1_MASK:
440 irq_chg[0] &= ~irq_data->enable;
441 break;
442 case MAX8925_CHG_IRQ2_MASK:
443 irq_chg[1] &= ~irq_data->enable;
444 break;
445 case MAX8925_ON_OFF_IRQ1_MASK:
446 irq_on[0] &= ~irq_data->enable;
447 break;
448 case MAX8925_ON_OFF_IRQ2_MASK:
449 irq_on[1] &= ~irq_data->enable;
450 break;
451 case MAX8925_RTC_IRQ_MASK:
452 irq_rtc &= ~irq_data->enable;
453 break;
454 case MAX8925_TSC_IRQ_MASK:
455 irq_tsc &= ~irq_data->enable;
456 break;
457 default:
458 dev_err(chip->dev, "wrong IRQ\n");
459 break;
460 }
461 }
462 /* update mask into registers */
463 if (cache_chg[0] != irq_chg[0]) {
464 cache_chg[0] = irq_chg[0];
465 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
466 irq_chg[0]);
467 }
468 if (cache_chg[1] != irq_chg[1]) {
469 cache_chg[1] = irq_chg[1];
470 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
471 irq_chg[1]);
472 }
473 if (cache_on[0] != irq_on[0]) {
474 cache_on[0] = irq_on[0];
475 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
476 irq_on[0]);
477 }
478 if (cache_on[1] != irq_on[1]) {
479 cache_on[1] = irq_on[1];
480 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
481 irq_on[1]);
482 }
483 if (cache_rtc != irq_rtc) {
484 cache_rtc = irq_rtc;
485 max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
486 }
487 if (cache_tsc != irq_tsc) {
488 cache_tsc = irq_tsc;
489 max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
490 }
491
492 mutex_unlock(&chip->irq_lock);
493}
494
495static void max8925_irq_enable(struct irq_data *data)
496{
497 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
498 max8925_irqs[data->irq - chip->irq_base].enable
499 = max8925_irqs[data->irq - chip->irq_base].offs;
500}
501
502static void max8925_irq_disable(struct irq_data *data)
503{
504 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
505 max8925_irqs[data->irq - chip->irq_base].enable = 0;
506}
507
508static struct irq_chip max8925_irq_chip = {
509 .name = "max8925",
510 .irq_bus_lock = max8925_irq_lock,
511 .irq_bus_sync_unlock = max8925_irq_sync_unlock,
512 .irq_enable = max8925_irq_enable,
513 .irq_disable = max8925_irq_disable,
514};
515
516static int max8925_irq_init(struct max8925_chip *chip, int irq,
517 struct max8925_platform_data *pdata)
518{
519 unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
520 int i, ret;
521 int __irq;
522
523 if (!pdata || !pdata->irq_base) {
524 dev_warn(chip->dev, "No interrupt support on IRQ base\n");
525 return -EINVAL;
526 }
527 /* clear all interrupts */
528 max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
529 max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
530 max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
531 max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
532 max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
533 max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
534 /* mask all interrupts except for TSC */
535 max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
536 max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
537 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
538 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
539 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
540 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
541 max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
542
543 mutex_init(&chip->irq_lock);
544 chip->core_irq = irq;
545 chip->irq_base = pdata->irq_base;
546
547 /* register with genirq */
548 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
549 __irq = i + chip->irq_base;
550 irq_set_chip_data(__irq, chip);
551 irq_set_chip_and_handler(__irq, &max8925_irq_chip,
552 handle_edge_irq);
553 irq_set_nested_thread(__irq, 1);
554#ifdef CONFIG_ARM
555 set_irq_flags(__irq, IRQF_VALID);
556#else
557 irq_set_noprobe(__irq);
558#endif
559 }
560 if (!irq) {
561 dev_warn(chip->dev, "No interrupt support on core IRQ\n");
562 goto tsc_irq;
563 }
564
565 ret = request_threaded_irq(irq, NULL, max8925_irq, flags,
566 "max8925", chip);
567 if (ret) {
568 dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
569 chip->core_irq = 0;
570 }
571
572tsc_irq:
573 /* mask TSC interrupt */
574 max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
575
576 if (!pdata->tsc_irq) {
577 dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
578 return 0;
579 }
580 chip->tsc_irq = pdata->tsc_irq;
581
582 ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
583 flags, "max8925-tsc", chip);
584 if (ret) {
585 dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
586 chip->tsc_irq = 0;
587 }
588 return 0;
589}
590
591int __devinit max8925_device_init(struct max8925_chip *chip,
592 struct max8925_platform_data *pdata)
593{
594 int ret;
595
596 max8925_irq_init(chip, chip->i2c->irq, pdata);
597
598 if (pdata && (pdata->power || pdata->touch)) {
599 /* enable ADC to control internal reference */
600 max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
601 /* enable internal reference for ADC */
602 max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
603 /* check for internal reference IRQ */
604 do {
605 ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
606 } while (ret & MAX8925_NREF_OK);
607 /* enaable ADC scheduler, interval is 1 second */
608 max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
609 }
610
611 /* enable Momentary Power Loss */
612 max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
613
614 ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
615 ARRAY_SIZE(rtc_devs),
616 &rtc_resources[0], 0);
617 if (ret < 0) {
618 dev_err(chip->dev, "Failed to add rtc subdev\n");
619 goto out;
620 }
621
622 ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
623 ARRAY_SIZE(onkey_devs),
624 &onkey_resources[0], 0);
625 if (ret < 0) {
626 dev_err(chip->dev, "Failed to add onkey subdev\n");
627 goto out_dev;
628 }
629
630 if (pdata) {
631 ret = mfd_add_devices(chip->dev, 0, ®ulator_devs[0],
632 ARRAY_SIZE(regulator_devs),
633 ®ulator_resources[0], 0);
634 if (ret < 0) {
635 dev_err(chip->dev, "Failed to add regulator subdev\n");
636 goto out_dev;
637 }
638 }
639
640 if (pdata && pdata->backlight) {
641 ret = mfd_add_devices(chip->dev, 0, &backlight_devs[0],
642 ARRAY_SIZE(backlight_devs),
643 &backlight_resources[0], 0);
644 if (ret < 0) {
645 dev_err(chip->dev, "Failed to add backlight subdev\n");
646 goto out_dev;
647 }
648 }
649
650 if (pdata && pdata->power) {
651 ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
652 ARRAY_SIZE(power_devs),
653 &power_supply_resources[0], 0);
654 if (ret < 0) {
655 dev_err(chip->dev, "Failed to add power supply "
656 "subdev\n");
657 goto out_dev;
658 }
659 }
660
661 if (pdata && pdata->touch) {
662 ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
663 ARRAY_SIZE(touch_devs),
664 &touch_resources[0], 0);
665 if (ret < 0) {
666 dev_err(chip->dev, "Failed to add touch subdev\n");
667 goto out_dev;
668 }
669 }
670
671 return 0;
672out_dev:
673 mfd_remove_devices(chip->dev);
674out:
675 return ret;
676}
677
678void __devexit max8925_device_exit(struct max8925_chip *chip)
679{
680 if (chip->core_irq)
681 free_irq(chip->core_irq, chip);
682 if (chip->tsc_irq)
683 free_irq(chip->tsc_irq, chip);
684 mfd_remove_devices(chip->dev);
685}
686
687
688MODULE_DESCRIPTION("PMIC Driver for Maxim MAX8925");
689MODULE_AUTHOR("Haojian Zhuang <haojian.zhuang@marvell.com");
690MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Base driver for Maxim MAX8925
4 *
5 * Copyright (C) 2009-2010 Marvell International Ltd.
6 * Haojian Zhuang <haojian.zhuang@marvell.com>
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/i2c.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/irqdomain.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/machine.h>
17#include <linux/mfd/core.h>
18#include <linux/mfd/max8925.h>
19#include <linux/of.h>
20
21static const struct resource bk_resources[] = {
22 { 0x84, 0x84, "mode control", IORESOURCE_REG, },
23 { 0x85, 0x85, "control", IORESOURCE_REG, },
24};
25
26static struct mfd_cell bk_devs[] = {
27 {
28 .name = "max8925-backlight",
29 .num_resources = ARRAY_SIZE(bk_resources),
30 .resources = &bk_resources[0],
31 .id = -1,
32 },
33};
34
35static const struct resource touch_resources[] = {
36 {
37 .name = "max8925-tsc",
38 .start = MAX8925_TSC_IRQ,
39 .end = MAX8925_ADC_RES_END,
40 .flags = IORESOURCE_REG,
41 },
42};
43
44static const struct mfd_cell touch_devs[] = {
45 {
46 .name = "max8925-touch",
47 .num_resources = 1,
48 .resources = &touch_resources[0],
49 .id = -1,
50 },
51};
52
53static const struct resource power_supply_resources[] = {
54 {
55 .name = "max8925-power",
56 .start = MAX8925_CHG_IRQ1,
57 .end = MAX8925_CHG_IRQ1_MASK,
58 .flags = IORESOURCE_REG,
59 },
60};
61
62static const struct mfd_cell power_devs[] = {
63 {
64 .name = "max8925-power",
65 .num_resources = 1,
66 .resources = &power_supply_resources[0],
67 .id = -1,
68 },
69};
70
71static const struct resource rtc_resources[] = {
72 {
73 .name = "max8925-rtc",
74 .start = MAX8925_IRQ_RTC_ALARM0,
75 .end = MAX8925_IRQ_RTC_ALARM0,
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static const struct mfd_cell rtc_devs[] = {
81 {
82 .name = "max8925-rtc",
83 .num_resources = 1,
84 .resources = &rtc_resources[0],
85 .id = -1,
86 },
87};
88
89static const struct resource onkey_resources[] = {
90 {
91 .name = "max8925-onkey",
92 .start = MAX8925_IRQ_GPM_SW_R,
93 .end = MAX8925_IRQ_GPM_SW_R,
94 .flags = IORESOURCE_IRQ,
95 }, {
96 .name = "max8925-onkey",
97 .start = MAX8925_IRQ_GPM_SW_F,
98 .end = MAX8925_IRQ_GPM_SW_F,
99 .flags = IORESOURCE_IRQ,
100 },
101};
102
103static const struct mfd_cell onkey_devs[] = {
104 {
105 .name = "max8925-onkey",
106 .num_resources = 2,
107 .resources = &onkey_resources[0],
108 .id = -1,
109 },
110};
111
112static const struct resource sd1_resources[] = {
113 {0x06, 0x06, "sdv", IORESOURCE_REG, },
114};
115
116static const struct resource sd2_resources[] = {
117 {0x09, 0x09, "sdv", IORESOURCE_REG, },
118};
119
120static const struct resource sd3_resources[] = {
121 {0x0c, 0x0c, "sdv", IORESOURCE_REG, },
122};
123
124static const struct resource ldo1_resources[] = {
125 {0x1a, 0x1a, "ldov", IORESOURCE_REG, },
126};
127
128static const struct resource ldo2_resources[] = {
129 {0x1e, 0x1e, "ldov", IORESOURCE_REG, },
130};
131
132static const struct resource ldo3_resources[] = {
133 {0x22, 0x22, "ldov", IORESOURCE_REG, },
134};
135
136static const struct resource ldo4_resources[] = {
137 {0x26, 0x26, "ldov", IORESOURCE_REG, },
138};
139
140static const struct resource ldo5_resources[] = {
141 {0x2a, 0x2a, "ldov", IORESOURCE_REG, },
142};
143
144static const struct resource ldo6_resources[] = {
145 {0x2e, 0x2e, "ldov", IORESOURCE_REG, },
146};
147
148static const struct resource ldo7_resources[] = {
149 {0x32, 0x32, "ldov", IORESOURCE_REG, },
150};
151
152static const struct resource ldo8_resources[] = {
153 {0x36, 0x36, "ldov", IORESOURCE_REG, },
154};
155
156static const struct resource ldo9_resources[] = {
157 {0x3a, 0x3a, "ldov", IORESOURCE_REG, },
158};
159
160static const struct resource ldo10_resources[] = {
161 {0x3e, 0x3e, "ldov", IORESOURCE_REG, },
162};
163
164static const struct resource ldo11_resources[] = {
165 {0x42, 0x42, "ldov", IORESOURCE_REG, },
166};
167
168static const struct resource ldo12_resources[] = {
169 {0x46, 0x46, "ldov", IORESOURCE_REG, },
170};
171
172static const struct resource ldo13_resources[] = {
173 {0x4a, 0x4a, "ldov", IORESOURCE_REG, },
174};
175
176static const struct resource ldo14_resources[] = {
177 {0x4e, 0x4e, "ldov", IORESOURCE_REG, },
178};
179
180static const struct resource ldo15_resources[] = {
181 {0x52, 0x52, "ldov", IORESOURCE_REG, },
182};
183
184static const struct resource ldo16_resources[] = {
185 {0x12, 0x12, "ldov", IORESOURCE_REG, },
186};
187
188static const struct resource ldo17_resources[] = {
189 {0x16, 0x16, "ldov", IORESOURCE_REG, },
190};
191
192static const struct resource ldo18_resources[] = {
193 {0x74, 0x74, "ldov", IORESOURCE_REG, },
194};
195
196static const struct resource ldo19_resources[] = {
197 {0x5e, 0x5e, "ldov", IORESOURCE_REG, },
198};
199
200static const struct resource ldo20_resources[] = {
201 {0x9e, 0x9e, "ldov", IORESOURCE_REG, },
202};
203
204static struct mfd_cell reg_devs[] = {
205 {
206 .name = "max8925-regulator",
207 .id = 0,
208 .num_resources = ARRAY_SIZE(sd1_resources),
209 .resources = sd1_resources,
210 }, {
211 .name = "max8925-regulator",
212 .id = 1,
213 .num_resources = ARRAY_SIZE(sd2_resources),
214 .resources = sd2_resources,
215 }, {
216 .name = "max8925-regulator",
217 .id = 2,
218 .num_resources = ARRAY_SIZE(sd3_resources),
219 .resources = sd3_resources,
220 }, {
221 .name = "max8925-regulator",
222 .id = 3,
223 .num_resources = ARRAY_SIZE(ldo1_resources),
224 .resources = ldo1_resources,
225 }, {
226 .name = "max8925-regulator",
227 .id = 4,
228 .num_resources = ARRAY_SIZE(ldo2_resources),
229 .resources = ldo2_resources,
230 }, {
231 .name = "max8925-regulator",
232 .id = 5,
233 .num_resources = ARRAY_SIZE(ldo3_resources),
234 .resources = ldo3_resources,
235 }, {
236 .name = "max8925-regulator",
237 .id = 6,
238 .num_resources = ARRAY_SIZE(ldo4_resources),
239 .resources = ldo4_resources,
240 }, {
241 .name = "max8925-regulator",
242 .id = 7,
243 .num_resources = ARRAY_SIZE(ldo5_resources),
244 .resources = ldo5_resources,
245 }, {
246 .name = "max8925-regulator",
247 .id = 8,
248 .num_resources = ARRAY_SIZE(ldo6_resources),
249 .resources = ldo6_resources,
250 }, {
251 .name = "max8925-regulator",
252 .id = 9,
253 .num_resources = ARRAY_SIZE(ldo7_resources),
254 .resources = ldo7_resources,
255 }, {
256 .name = "max8925-regulator",
257 .id = 10,
258 .num_resources = ARRAY_SIZE(ldo8_resources),
259 .resources = ldo8_resources,
260 }, {
261 .name = "max8925-regulator",
262 .id = 11,
263 .num_resources = ARRAY_SIZE(ldo9_resources),
264 .resources = ldo9_resources,
265 }, {
266 .name = "max8925-regulator",
267 .id = 12,
268 .num_resources = ARRAY_SIZE(ldo10_resources),
269 .resources = ldo10_resources,
270 }, {
271 .name = "max8925-regulator",
272 .id = 13,
273 .num_resources = ARRAY_SIZE(ldo11_resources),
274 .resources = ldo11_resources,
275 }, {
276 .name = "max8925-regulator",
277 .id = 14,
278 .num_resources = ARRAY_SIZE(ldo12_resources),
279 .resources = ldo12_resources,
280 }, {
281 .name = "max8925-regulator",
282 .id = 15,
283 .num_resources = ARRAY_SIZE(ldo13_resources),
284 .resources = ldo13_resources,
285 }, {
286 .name = "max8925-regulator",
287 .id = 16,
288 .num_resources = ARRAY_SIZE(ldo14_resources),
289 .resources = ldo14_resources,
290 }, {
291 .name = "max8925-regulator",
292 .id = 17,
293 .num_resources = ARRAY_SIZE(ldo15_resources),
294 .resources = ldo15_resources,
295 }, {
296 .name = "max8925-regulator",
297 .id = 18,
298 .num_resources = ARRAY_SIZE(ldo16_resources),
299 .resources = ldo16_resources,
300 }, {
301 .name = "max8925-regulator",
302 .id = 19,
303 .num_resources = ARRAY_SIZE(ldo17_resources),
304 .resources = ldo17_resources,
305 }, {
306 .name = "max8925-regulator",
307 .id = 20,
308 .num_resources = ARRAY_SIZE(ldo18_resources),
309 .resources = ldo18_resources,
310 }, {
311 .name = "max8925-regulator",
312 .id = 21,
313 .num_resources = ARRAY_SIZE(ldo19_resources),
314 .resources = ldo19_resources,
315 }, {
316 .name = "max8925-regulator",
317 .id = 22,
318 .num_resources = ARRAY_SIZE(ldo20_resources),
319 .resources = ldo20_resources,
320 },
321};
322
323enum {
324 FLAGS_ADC = 1, /* register in ADC component */
325 FLAGS_RTC, /* register in RTC component */
326};
327
328struct max8925_irq_data {
329 int reg;
330 int mask_reg;
331 int enable; /* enable or not */
332 int offs; /* bit offset in mask register */
333 int flags;
334 int tsc_irq;
335};
336
337static struct max8925_irq_data max8925_irqs[] = {
338 [MAX8925_IRQ_VCHG_DC_OVP] = {
339 .reg = MAX8925_CHG_IRQ1,
340 .mask_reg = MAX8925_CHG_IRQ1_MASK,
341 .offs = 1 << 0,
342 },
343 [MAX8925_IRQ_VCHG_DC_F] = {
344 .reg = MAX8925_CHG_IRQ1,
345 .mask_reg = MAX8925_CHG_IRQ1_MASK,
346 .offs = 1 << 1,
347 },
348 [MAX8925_IRQ_VCHG_DC_R] = {
349 .reg = MAX8925_CHG_IRQ1,
350 .mask_reg = MAX8925_CHG_IRQ1_MASK,
351 .offs = 1 << 2,
352 },
353 [MAX8925_IRQ_VCHG_THM_OK_R] = {
354 .reg = MAX8925_CHG_IRQ2,
355 .mask_reg = MAX8925_CHG_IRQ2_MASK,
356 .offs = 1 << 0,
357 },
358 [MAX8925_IRQ_VCHG_THM_OK_F] = {
359 .reg = MAX8925_CHG_IRQ2,
360 .mask_reg = MAX8925_CHG_IRQ2_MASK,
361 .offs = 1 << 1,
362 },
363 [MAX8925_IRQ_VCHG_SYSLOW_F] = {
364 .reg = MAX8925_CHG_IRQ2,
365 .mask_reg = MAX8925_CHG_IRQ2_MASK,
366 .offs = 1 << 2,
367 },
368 [MAX8925_IRQ_VCHG_SYSLOW_R] = {
369 .reg = MAX8925_CHG_IRQ2,
370 .mask_reg = MAX8925_CHG_IRQ2_MASK,
371 .offs = 1 << 3,
372 },
373 [MAX8925_IRQ_VCHG_RST] = {
374 .reg = MAX8925_CHG_IRQ2,
375 .mask_reg = MAX8925_CHG_IRQ2_MASK,
376 .offs = 1 << 4,
377 },
378 [MAX8925_IRQ_VCHG_DONE] = {
379 .reg = MAX8925_CHG_IRQ2,
380 .mask_reg = MAX8925_CHG_IRQ2_MASK,
381 .offs = 1 << 5,
382 },
383 [MAX8925_IRQ_VCHG_TOPOFF] = {
384 .reg = MAX8925_CHG_IRQ2,
385 .mask_reg = MAX8925_CHG_IRQ2_MASK,
386 .offs = 1 << 6,
387 },
388 [MAX8925_IRQ_VCHG_TMR_FAULT] = {
389 .reg = MAX8925_CHG_IRQ2,
390 .mask_reg = MAX8925_CHG_IRQ2_MASK,
391 .offs = 1 << 7,
392 },
393 [MAX8925_IRQ_GPM_RSTIN] = {
394 .reg = MAX8925_ON_OFF_IRQ1,
395 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
396 .offs = 1 << 0,
397 },
398 [MAX8925_IRQ_GPM_MPL] = {
399 .reg = MAX8925_ON_OFF_IRQ1,
400 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
401 .offs = 1 << 1,
402 },
403 [MAX8925_IRQ_GPM_SW_3SEC] = {
404 .reg = MAX8925_ON_OFF_IRQ1,
405 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
406 .offs = 1 << 2,
407 },
408 [MAX8925_IRQ_GPM_EXTON_F] = {
409 .reg = MAX8925_ON_OFF_IRQ1,
410 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
411 .offs = 1 << 3,
412 },
413 [MAX8925_IRQ_GPM_EXTON_R] = {
414 .reg = MAX8925_ON_OFF_IRQ1,
415 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
416 .offs = 1 << 4,
417 },
418 [MAX8925_IRQ_GPM_SW_1SEC] = {
419 .reg = MAX8925_ON_OFF_IRQ1,
420 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
421 .offs = 1 << 5,
422 },
423 [MAX8925_IRQ_GPM_SW_F] = {
424 .reg = MAX8925_ON_OFF_IRQ1,
425 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
426 .offs = 1 << 6,
427 },
428 [MAX8925_IRQ_GPM_SW_R] = {
429 .reg = MAX8925_ON_OFF_IRQ1,
430 .mask_reg = MAX8925_ON_OFF_IRQ1_MASK,
431 .offs = 1 << 7,
432 },
433 [MAX8925_IRQ_GPM_SYSCKEN_F] = {
434 .reg = MAX8925_ON_OFF_IRQ2,
435 .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
436 .offs = 1 << 0,
437 },
438 [MAX8925_IRQ_GPM_SYSCKEN_R] = {
439 .reg = MAX8925_ON_OFF_IRQ2,
440 .mask_reg = MAX8925_ON_OFF_IRQ2_MASK,
441 .offs = 1 << 1,
442 },
443 [MAX8925_IRQ_RTC_ALARM1] = {
444 .reg = MAX8925_RTC_IRQ,
445 .mask_reg = MAX8925_RTC_IRQ_MASK,
446 .offs = 1 << 2,
447 .flags = FLAGS_RTC,
448 },
449 [MAX8925_IRQ_RTC_ALARM0] = {
450 .reg = MAX8925_RTC_IRQ,
451 .mask_reg = MAX8925_RTC_IRQ_MASK,
452 .offs = 1 << 3,
453 .flags = FLAGS_RTC,
454 },
455 [MAX8925_IRQ_TSC_STICK] = {
456 .reg = MAX8925_TSC_IRQ,
457 .mask_reg = MAX8925_TSC_IRQ_MASK,
458 .offs = 1 << 0,
459 .flags = FLAGS_ADC,
460 .tsc_irq = 1,
461 },
462 [MAX8925_IRQ_TSC_NSTICK] = {
463 .reg = MAX8925_TSC_IRQ,
464 .mask_reg = MAX8925_TSC_IRQ_MASK,
465 .offs = 1 << 1,
466 .flags = FLAGS_ADC,
467 .tsc_irq = 1,
468 },
469};
470
471static irqreturn_t max8925_irq(int irq, void *data)
472{
473 struct max8925_chip *chip = data;
474 struct max8925_irq_data *irq_data;
475 struct i2c_client *i2c;
476 int read_reg = -1, value = 0;
477 int i;
478
479 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
480 irq_data = &max8925_irqs[i];
481 /* TSC IRQ should be serviced in max8925_tsc_irq() */
482 if (irq_data->tsc_irq)
483 continue;
484 if (irq_data->flags == FLAGS_RTC)
485 i2c = chip->rtc;
486 else if (irq_data->flags == FLAGS_ADC)
487 i2c = chip->adc;
488 else
489 i2c = chip->i2c;
490 if (read_reg != irq_data->reg) {
491 read_reg = irq_data->reg;
492 value = max8925_reg_read(i2c, irq_data->reg);
493 }
494 if (value & irq_data->enable)
495 handle_nested_irq(chip->irq_base + i);
496 }
497 return IRQ_HANDLED;
498}
499
500static irqreturn_t max8925_tsc_irq(int irq, void *data)
501{
502 struct max8925_chip *chip = data;
503 struct max8925_irq_data *irq_data;
504 struct i2c_client *i2c;
505 int read_reg = -1, value = 0;
506 int i;
507
508 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
509 irq_data = &max8925_irqs[i];
510 /* non TSC IRQ should be serviced in max8925_irq() */
511 if (!irq_data->tsc_irq)
512 continue;
513 if (irq_data->flags == FLAGS_RTC)
514 i2c = chip->rtc;
515 else if (irq_data->flags == FLAGS_ADC)
516 i2c = chip->adc;
517 else
518 i2c = chip->i2c;
519 if (read_reg != irq_data->reg) {
520 read_reg = irq_data->reg;
521 value = max8925_reg_read(i2c, irq_data->reg);
522 }
523 if (value & irq_data->enable)
524 handle_nested_irq(chip->irq_base + i);
525 }
526 return IRQ_HANDLED;
527}
528
529static void max8925_irq_lock(struct irq_data *data)
530{
531 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
532
533 mutex_lock(&chip->irq_lock);
534}
535
536static void max8925_irq_sync_unlock(struct irq_data *data)
537{
538 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
539 struct max8925_irq_data *irq_data;
540 static unsigned char cache_chg[2] = {0xff, 0xff};
541 static unsigned char cache_on[2] = {0xff, 0xff};
542 static unsigned char cache_rtc = 0xff, cache_tsc = 0xff;
543 unsigned char irq_chg[2], irq_on[2];
544 unsigned char irq_rtc, irq_tsc;
545 int i;
546
547 /* Load cached value. In initial, all IRQs are masked */
548 irq_chg[0] = cache_chg[0];
549 irq_chg[1] = cache_chg[1];
550 irq_on[0] = cache_on[0];
551 irq_on[1] = cache_on[1];
552 irq_rtc = cache_rtc;
553 irq_tsc = cache_tsc;
554 for (i = 0; i < ARRAY_SIZE(max8925_irqs); i++) {
555 irq_data = &max8925_irqs[i];
556 /* 1 -- disable, 0 -- enable */
557 switch (irq_data->mask_reg) {
558 case MAX8925_CHG_IRQ1_MASK:
559 irq_chg[0] &= ~irq_data->enable;
560 break;
561 case MAX8925_CHG_IRQ2_MASK:
562 irq_chg[1] &= ~irq_data->enable;
563 break;
564 case MAX8925_ON_OFF_IRQ1_MASK:
565 irq_on[0] &= ~irq_data->enable;
566 break;
567 case MAX8925_ON_OFF_IRQ2_MASK:
568 irq_on[1] &= ~irq_data->enable;
569 break;
570 case MAX8925_RTC_IRQ_MASK:
571 irq_rtc &= ~irq_data->enable;
572 break;
573 case MAX8925_TSC_IRQ_MASK:
574 irq_tsc &= ~irq_data->enable;
575 break;
576 default:
577 dev_err(chip->dev, "wrong IRQ\n");
578 break;
579 }
580 }
581 /* update mask into registers */
582 if (cache_chg[0] != irq_chg[0]) {
583 cache_chg[0] = irq_chg[0];
584 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK,
585 irq_chg[0]);
586 }
587 if (cache_chg[1] != irq_chg[1]) {
588 cache_chg[1] = irq_chg[1];
589 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK,
590 irq_chg[1]);
591 }
592 if (cache_on[0] != irq_on[0]) {
593 cache_on[0] = irq_on[0];
594 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK,
595 irq_on[0]);
596 }
597 if (cache_on[1] != irq_on[1]) {
598 cache_on[1] = irq_on[1];
599 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK,
600 irq_on[1]);
601 }
602 if (cache_rtc != irq_rtc) {
603 cache_rtc = irq_rtc;
604 max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, irq_rtc);
605 }
606 if (cache_tsc != irq_tsc) {
607 cache_tsc = irq_tsc;
608 max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, irq_tsc);
609 }
610
611 mutex_unlock(&chip->irq_lock);
612}
613
614static void max8925_irq_enable(struct irq_data *data)
615{
616 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
617
618 max8925_irqs[data->irq - chip->irq_base].enable
619 = max8925_irqs[data->irq - chip->irq_base].offs;
620}
621
622static void max8925_irq_disable(struct irq_data *data)
623{
624 struct max8925_chip *chip = irq_data_get_irq_chip_data(data);
625
626 max8925_irqs[data->irq - chip->irq_base].enable = 0;
627}
628
629static struct irq_chip max8925_irq_chip = {
630 .name = "max8925",
631 .irq_bus_lock = max8925_irq_lock,
632 .irq_bus_sync_unlock = max8925_irq_sync_unlock,
633 .irq_enable = max8925_irq_enable,
634 .irq_disable = max8925_irq_disable,
635};
636
637static int max8925_irq_domain_map(struct irq_domain *d, unsigned int virq,
638 irq_hw_number_t hw)
639{
640 irq_set_chip_data(virq, d->host_data);
641 irq_set_chip_and_handler(virq, &max8925_irq_chip, handle_edge_irq);
642 irq_set_nested_thread(virq, 1);
643 irq_set_noprobe(virq);
644
645 return 0;
646}
647
648static const struct irq_domain_ops max8925_irq_domain_ops = {
649 .map = max8925_irq_domain_map,
650 .xlate = irq_domain_xlate_onetwocell,
651};
652
653
654static int max8925_irq_init(struct max8925_chip *chip, int irq,
655 struct max8925_platform_data *pdata)
656{
657 unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
658 int ret;
659 struct device_node *node = chip->dev->of_node;
660
661 /* clear all interrupts */
662 max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ1);
663 max8925_reg_read(chip->i2c, MAX8925_CHG_IRQ2);
664 max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ1);
665 max8925_reg_read(chip->i2c, MAX8925_ON_OFF_IRQ2);
666 max8925_reg_read(chip->rtc, MAX8925_RTC_IRQ);
667 max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
668 /* mask all interrupts except for TSC */
669 max8925_reg_write(chip->rtc, MAX8925_ALARM0_CNTL, 0);
670 max8925_reg_write(chip->rtc, MAX8925_ALARM1_CNTL, 0);
671 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ1_MASK, 0xff);
672 max8925_reg_write(chip->i2c, MAX8925_CHG_IRQ2_MASK, 0xff);
673 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ1_MASK, 0xff);
674 max8925_reg_write(chip->i2c, MAX8925_ON_OFF_IRQ2_MASK, 0xff);
675 max8925_reg_write(chip->rtc, MAX8925_RTC_IRQ_MASK, 0xff);
676
677 mutex_init(&chip->irq_lock);
678 chip->irq_base = irq_alloc_descs(-1, 0, MAX8925_NR_IRQS, 0);
679 if (chip->irq_base < 0) {
680 dev_err(chip->dev, "Failed to allocate interrupts, ret:%d\n",
681 chip->irq_base);
682 return -EBUSY;
683 }
684
685 irq_domain_add_legacy(node, MAX8925_NR_IRQS, chip->irq_base, 0,
686 &max8925_irq_domain_ops, chip);
687
688 /* request irq handler for pmic main irq*/
689 chip->core_irq = irq;
690 if (!chip->core_irq)
691 return -EBUSY;
692 ret = request_threaded_irq(irq, NULL, max8925_irq, flags | IRQF_ONESHOT,
693 "max8925", chip);
694 if (ret) {
695 dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
696 chip->core_irq = 0;
697 return -EBUSY;
698 }
699
700 /* request irq handler for pmic tsc irq*/
701
702 /* mask TSC interrupt */
703 max8925_reg_write(chip->adc, MAX8925_TSC_IRQ_MASK, 0x0f);
704
705 if (!pdata->tsc_irq) {
706 dev_warn(chip->dev, "No interrupt support on TSC IRQ\n");
707 return 0;
708 }
709 chip->tsc_irq = pdata->tsc_irq;
710 ret = request_threaded_irq(chip->tsc_irq, NULL, max8925_tsc_irq,
711 flags | IRQF_ONESHOT, "max8925-tsc", chip);
712 if (ret) {
713 dev_err(chip->dev, "Failed to request TSC IRQ: %d\n", ret);
714 chip->tsc_irq = 0;
715 }
716 return 0;
717}
718
719static void init_regulator(struct max8925_chip *chip,
720 struct max8925_platform_data *pdata)
721{
722 int ret;
723
724 if (!pdata)
725 return;
726 if (pdata->sd1) {
727 reg_devs[0].platform_data = pdata->sd1;
728 reg_devs[0].pdata_size = sizeof(struct regulator_init_data);
729 }
730 if (pdata->sd2) {
731 reg_devs[1].platform_data = pdata->sd2;
732 reg_devs[1].pdata_size = sizeof(struct regulator_init_data);
733 }
734 if (pdata->sd3) {
735 reg_devs[2].platform_data = pdata->sd3;
736 reg_devs[2].pdata_size = sizeof(struct regulator_init_data);
737 }
738 if (pdata->ldo1) {
739 reg_devs[3].platform_data = pdata->ldo1;
740 reg_devs[3].pdata_size = sizeof(struct regulator_init_data);
741 }
742 if (pdata->ldo2) {
743 reg_devs[4].platform_data = pdata->ldo2;
744 reg_devs[4].pdata_size = sizeof(struct regulator_init_data);
745 }
746 if (pdata->ldo3) {
747 reg_devs[5].platform_data = pdata->ldo3;
748 reg_devs[5].pdata_size = sizeof(struct regulator_init_data);
749 }
750 if (pdata->ldo4) {
751 reg_devs[6].platform_data = pdata->ldo4;
752 reg_devs[6].pdata_size = sizeof(struct regulator_init_data);
753 }
754 if (pdata->ldo5) {
755 reg_devs[7].platform_data = pdata->ldo5;
756 reg_devs[7].pdata_size = sizeof(struct regulator_init_data);
757 }
758 if (pdata->ldo6) {
759 reg_devs[8].platform_data = pdata->ldo6;
760 reg_devs[8].pdata_size = sizeof(struct regulator_init_data);
761 }
762 if (pdata->ldo7) {
763 reg_devs[9].platform_data = pdata->ldo7;
764 reg_devs[9].pdata_size = sizeof(struct regulator_init_data);
765 }
766 if (pdata->ldo8) {
767 reg_devs[10].platform_data = pdata->ldo8;
768 reg_devs[10].pdata_size = sizeof(struct regulator_init_data);
769 }
770 if (pdata->ldo9) {
771 reg_devs[11].platform_data = pdata->ldo9;
772 reg_devs[11].pdata_size = sizeof(struct regulator_init_data);
773 }
774 if (pdata->ldo10) {
775 reg_devs[12].platform_data = pdata->ldo10;
776 reg_devs[12].pdata_size = sizeof(struct regulator_init_data);
777 }
778 if (pdata->ldo11) {
779 reg_devs[13].platform_data = pdata->ldo11;
780 reg_devs[13].pdata_size = sizeof(struct regulator_init_data);
781 }
782 if (pdata->ldo12) {
783 reg_devs[14].platform_data = pdata->ldo12;
784 reg_devs[14].pdata_size = sizeof(struct regulator_init_data);
785 }
786 if (pdata->ldo13) {
787 reg_devs[15].platform_data = pdata->ldo13;
788 reg_devs[15].pdata_size = sizeof(struct regulator_init_data);
789 }
790 if (pdata->ldo14) {
791 reg_devs[16].platform_data = pdata->ldo14;
792 reg_devs[16].pdata_size = sizeof(struct regulator_init_data);
793 }
794 if (pdata->ldo15) {
795 reg_devs[17].platform_data = pdata->ldo15;
796 reg_devs[17].pdata_size = sizeof(struct regulator_init_data);
797 }
798 if (pdata->ldo16) {
799 reg_devs[18].platform_data = pdata->ldo16;
800 reg_devs[18].pdata_size = sizeof(struct regulator_init_data);
801 }
802 if (pdata->ldo17) {
803 reg_devs[19].platform_data = pdata->ldo17;
804 reg_devs[19].pdata_size = sizeof(struct regulator_init_data);
805 }
806 if (pdata->ldo18) {
807 reg_devs[20].platform_data = pdata->ldo18;
808 reg_devs[20].pdata_size = sizeof(struct regulator_init_data);
809 }
810 if (pdata->ldo19) {
811 reg_devs[21].platform_data = pdata->ldo19;
812 reg_devs[21].pdata_size = sizeof(struct regulator_init_data);
813 }
814 if (pdata->ldo20) {
815 reg_devs[22].platform_data = pdata->ldo20;
816 reg_devs[22].pdata_size = sizeof(struct regulator_init_data);
817 }
818 ret = mfd_add_devices(chip->dev, 0, reg_devs, ARRAY_SIZE(reg_devs),
819 NULL, 0, NULL);
820 if (ret < 0) {
821 dev_err(chip->dev, "Failed to add regulator subdev\n");
822 return;
823 }
824}
825
826int max8925_device_init(struct max8925_chip *chip,
827 struct max8925_platform_data *pdata)
828{
829 int ret;
830
831 max8925_irq_init(chip, chip->i2c->irq, pdata);
832
833 if (pdata && (pdata->power || pdata->touch)) {
834 /* enable ADC to control internal reference */
835 max8925_set_bits(chip->i2c, MAX8925_RESET_CNFG, 1, 1);
836 /* enable internal reference for ADC */
837 max8925_set_bits(chip->adc, MAX8925_TSC_CNFG1, 3, 2);
838 /* check for internal reference IRQ */
839 do {
840 ret = max8925_reg_read(chip->adc, MAX8925_TSC_IRQ);
841 } while (ret & MAX8925_NREF_OK);
842 /* enaable ADC scheduler, interval is 1 second */
843 max8925_set_bits(chip->adc, MAX8925_ADC_SCHED, 3, 2);
844 }
845
846 /* enable Momentary Power Loss */
847 max8925_set_bits(chip->rtc, MAX8925_MPL_CNTL, 1 << 4, 1 << 4);
848
849 ret = mfd_add_devices(chip->dev, 0, &rtc_devs[0],
850 ARRAY_SIZE(rtc_devs),
851 NULL, chip->irq_base, NULL);
852 if (ret < 0) {
853 dev_err(chip->dev, "Failed to add rtc subdev\n");
854 goto out;
855 }
856
857 ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
858 ARRAY_SIZE(onkey_devs),
859 NULL, chip->irq_base, NULL);
860 if (ret < 0) {
861 dev_err(chip->dev, "Failed to add onkey subdev\n");
862 goto out_dev;
863 }
864
865 init_regulator(chip, pdata);
866
867 if (pdata && pdata->backlight) {
868 bk_devs[0].platform_data = &pdata->backlight;
869 bk_devs[0].pdata_size = sizeof(struct max8925_backlight_pdata);
870 }
871 ret = mfd_add_devices(chip->dev, 0, bk_devs, ARRAY_SIZE(bk_devs),
872 NULL, 0, NULL);
873 if (ret < 0) {
874 dev_err(chip->dev, "Failed to add backlight subdev\n");
875 goto out_dev;
876 }
877
878 ret = mfd_add_devices(chip->dev, 0, &power_devs[0],
879 ARRAY_SIZE(power_devs),
880 NULL, 0, NULL);
881 if (ret < 0) {
882 dev_err(chip->dev,
883 "Failed to add power supply subdev, err = %d\n", ret);
884 goto out_dev;
885 }
886
887 if (pdata && pdata->touch) {
888 ret = mfd_add_devices(chip->dev, 0, &touch_devs[0],
889 ARRAY_SIZE(touch_devs),
890 NULL, chip->tsc_irq, NULL);
891 if (ret < 0) {
892 dev_err(chip->dev, "Failed to add touch subdev\n");
893 goto out_dev;
894 }
895 }
896
897 return 0;
898out_dev:
899 mfd_remove_devices(chip->dev);
900out:
901 return ret;
902}
903
904void max8925_device_exit(struct max8925_chip *chip)
905{
906 if (chip->core_irq)
907 free_irq(chip->core_irq, chip);
908 if (chip->tsc_irq)
909 free_irq(chip->tsc_irq, chip);
910 mfd_remove_devices(chip->dev);
911}