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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <linux/slab.h>
34#include <linux/dma-buf.h>
35
36#include <drm/drm_drv.h>
37#include <drm/amdgpu_drm.h>
38#include <drm/drm_cache.h>
39#include "amdgpu.h"
40#include "amdgpu_trace.h"
41#include "amdgpu_amdkfd.h"
42
43/**
44 * DOC: amdgpu_object
45 *
46 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
47 * represents memory used by driver (VRAM, system memory, etc.). The driver
48 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
49 * to create/destroy/set buffer object which are then managed by the kernel TTM
50 * memory manager.
51 * The interfaces are also used internally by kernel clients, including gfx,
52 * uvd, etc. for kernel managed allocations used by the GPU.
53 *
54 */
55
56static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
57{
58 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
59
60 amdgpu_bo_kunmap(bo);
61
62 if (bo->tbo.base.import_attach)
63 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
64 drm_gem_object_release(&bo->tbo.base);
65 amdgpu_bo_unref(&bo->parent);
66 kvfree(bo);
67}
68
69static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo)
70{
71 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
72 struct amdgpu_bo_user *ubo;
73
74 ubo = to_amdgpu_bo_user(bo);
75 kfree(ubo->metadata);
76 amdgpu_bo_destroy(tbo);
77}
78
79static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo)
80{
81 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
82 struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo;
83 struct amdgpu_bo_vm *vmbo;
84
85 bo = shadow_bo->parent;
86 vmbo = to_amdgpu_bo_vm(bo);
87 /* in case amdgpu_device_recover_vram got NULL of bo->parent */
88 if (!list_empty(&vmbo->shadow_list)) {
89 mutex_lock(&adev->shadow_list_lock);
90 list_del_init(&vmbo->shadow_list);
91 mutex_unlock(&adev->shadow_list_lock);
92 }
93
94 amdgpu_bo_destroy(tbo);
95}
96
97/**
98 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
99 * @bo: buffer object to be checked
100 *
101 * Uses destroy function associated with the object to determine if this is
102 * an &amdgpu_bo.
103 *
104 * Returns:
105 * true if the object belongs to &amdgpu_bo, false if not.
106 */
107bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
108{
109 if (bo->destroy == &amdgpu_bo_destroy ||
110 bo->destroy == &amdgpu_bo_user_destroy ||
111 bo->destroy == &amdgpu_bo_vm_destroy)
112 return true;
113
114 return false;
115}
116
117/**
118 * amdgpu_bo_placement_from_domain - set buffer's placement
119 * @abo: &amdgpu_bo buffer object whose placement is to be set
120 * @domain: requested domain
121 *
122 * Sets buffer's placement according to requested domain and the buffer's
123 * flags.
124 */
125void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
126{
127 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
128 struct ttm_placement *placement = &abo->placement;
129 struct ttm_place *places = abo->placements;
130 u64 flags = abo->flags;
131 u32 c = 0;
132
133 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
134 unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
135 int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id);
136
137 if (adev->gmc.mem_partitions && mem_id >= 0) {
138 places[c].fpfn = adev->gmc.mem_partitions[mem_id].range.fpfn;
139 /*
140 * memory partition range lpfn is inclusive start + size - 1
141 * TTM place lpfn is exclusive start + size
142 */
143 places[c].lpfn = adev->gmc.mem_partitions[mem_id].range.lpfn + 1;
144 } else {
145 places[c].fpfn = 0;
146 places[c].lpfn = 0;
147 }
148 places[c].mem_type = TTM_PL_VRAM;
149 places[c].flags = 0;
150
151 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
152 places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn);
153 else
154 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
155
156 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
157 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
158 c++;
159 }
160
161 if (domain & AMDGPU_GEM_DOMAIN_DOORBELL) {
162 places[c].fpfn = 0;
163 places[c].lpfn = 0;
164 places[c].mem_type = AMDGPU_PL_DOORBELL;
165 places[c].flags = 0;
166 c++;
167 }
168
169 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
170 places[c].fpfn = 0;
171 places[c].lpfn = 0;
172 places[c].mem_type =
173 abo->flags & AMDGPU_GEM_CREATE_PREEMPTIBLE ?
174 AMDGPU_PL_PREEMPT : TTM_PL_TT;
175 places[c].flags = 0;
176 c++;
177 }
178
179 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
180 places[c].fpfn = 0;
181 places[c].lpfn = 0;
182 places[c].mem_type = TTM_PL_SYSTEM;
183 places[c].flags = 0;
184 c++;
185 }
186
187 if (domain & AMDGPU_GEM_DOMAIN_GDS) {
188 places[c].fpfn = 0;
189 places[c].lpfn = 0;
190 places[c].mem_type = AMDGPU_PL_GDS;
191 places[c].flags = 0;
192 c++;
193 }
194
195 if (domain & AMDGPU_GEM_DOMAIN_GWS) {
196 places[c].fpfn = 0;
197 places[c].lpfn = 0;
198 places[c].mem_type = AMDGPU_PL_GWS;
199 places[c].flags = 0;
200 c++;
201 }
202
203 if (domain & AMDGPU_GEM_DOMAIN_OA) {
204 places[c].fpfn = 0;
205 places[c].lpfn = 0;
206 places[c].mem_type = AMDGPU_PL_OA;
207 places[c].flags = 0;
208 c++;
209 }
210
211 if (!c) {
212 places[c].fpfn = 0;
213 places[c].lpfn = 0;
214 places[c].mem_type = TTM_PL_SYSTEM;
215 places[c].flags = 0;
216 c++;
217 }
218
219 BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
220
221 placement->num_placement = c;
222 placement->placement = places;
223
224 placement->num_busy_placement = c;
225 placement->busy_placement = places;
226}
227
228/**
229 * amdgpu_bo_create_reserved - create reserved BO for kernel use
230 *
231 * @adev: amdgpu device object
232 * @size: size for the new BO
233 * @align: alignment for the new BO
234 * @domain: where to place it
235 * @bo_ptr: used to initialize BOs in structures
236 * @gpu_addr: GPU addr of the pinned BO
237 * @cpu_addr: optional CPU address mapping
238 *
239 * Allocates and pins a BO for kernel internal use, and returns it still
240 * reserved.
241 *
242 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
243 *
244 * Returns:
245 * 0 on success, negative error code otherwise.
246 */
247int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
248 unsigned long size, int align,
249 u32 domain, struct amdgpu_bo **bo_ptr,
250 u64 *gpu_addr, void **cpu_addr)
251{
252 struct amdgpu_bo_param bp;
253 bool free = false;
254 int r;
255
256 if (!size) {
257 amdgpu_bo_unref(bo_ptr);
258 return 0;
259 }
260
261 memset(&bp, 0, sizeof(bp));
262 bp.size = size;
263 bp.byte_align = align;
264 bp.domain = domain;
265 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
266 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
267 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
268 bp.type = ttm_bo_type_kernel;
269 bp.resv = NULL;
270 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
271
272 if (!*bo_ptr) {
273 r = amdgpu_bo_create(adev, &bp, bo_ptr);
274 if (r) {
275 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
276 r);
277 return r;
278 }
279 free = true;
280 }
281
282 r = amdgpu_bo_reserve(*bo_ptr, false);
283 if (r) {
284 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
285 goto error_free;
286 }
287
288 r = amdgpu_bo_pin(*bo_ptr, domain);
289 if (r) {
290 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
291 goto error_unreserve;
292 }
293
294 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
295 if (r) {
296 dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
297 goto error_unpin;
298 }
299
300 if (gpu_addr)
301 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
302
303 if (cpu_addr) {
304 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
305 if (r) {
306 dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
307 goto error_unpin;
308 }
309 }
310
311 return 0;
312
313error_unpin:
314 amdgpu_bo_unpin(*bo_ptr);
315error_unreserve:
316 amdgpu_bo_unreserve(*bo_ptr);
317
318error_free:
319 if (free)
320 amdgpu_bo_unref(bo_ptr);
321
322 return r;
323}
324
325/**
326 * amdgpu_bo_create_kernel - create BO for kernel use
327 *
328 * @adev: amdgpu device object
329 * @size: size for the new BO
330 * @align: alignment for the new BO
331 * @domain: where to place it
332 * @bo_ptr: used to initialize BOs in structures
333 * @gpu_addr: GPU addr of the pinned BO
334 * @cpu_addr: optional CPU address mapping
335 *
336 * Allocates and pins a BO for kernel internal use.
337 *
338 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
339 *
340 * Returns:
341 * 0 on success, negative error code otherwise.
342 */
343int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
344 unsigned long size, int align,
345 u32 domain, struct amdgpu_bo **bo_ptr,
346 u64 *gpu_addr, void **cpu_addr)
347{
348 int r;
349
350 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
351 gpu_addr, cpu_addr);
352
353 if (r)
354 return r;
355
356 if (*bo_ptr)
357 amdgpu_bo_unreserve(*bo_ptr);
358
359 return 0;
360}
361
362/**
363 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
364 *
365 * @adev: amdgpu device object
366 * @offset: offset of the BO
367 * @size: size of the BO
368 * @bo_ptr: used to initialize BOs in structures
369 * @cpu_addr: optional CPU address mapping
370 *
371 * Creates a kernel BO at a specific offset in VRAM.
372 *
373 * Returns:
374 * 0 on success, negative error code otherwise.
375 */
376int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
377 uint64_t offset, uint64_t size,
378 struct amdgpu_bo **bo_ptr, void **cpu_addr)
379{
380 struct ttm_operation_ctx ctx = { false, false };
381 unsigned int i;
382 int r;
383
384 offset &= PAGE_MASK;
385 size = ALIGN(size, PAGE_SIZE);
386
387 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
388 AMDGPU_GEM_DOMAIN_VRAM, bo_ptr, NULL,
389 cpu_addr);
390 if (r)
391 return r;
392
393 if ((*bo_ptr) == NULL)
394 return 0;
395
396 /*
397 * Remove the original mem node and create a new one at the request
398 * position.
399 */
400 if (cpu_addr)
401 amdgpu_bo_kunmap(*bo_ptr);
402
403 ttm_resource_free(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.resource);
404
405 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
406 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
407 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
408 }
409 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
410 &(*bo_ptr)->tbo.resource, &ctx);
411 if (r)
412 goto error;
413
414 if (cpu_addr) {
415 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
416 if (r)
417 goto error;
418 }
419
420 amdgpu_bo_unreserve(*bo_ptr);
421 return 0;
422
423error:
424 amdgpu_bo_unreserve(*bo_ptr);
425 amdgpu_bo_unref(bo_ptr);
426 return r;
427}
428
429/**
430 * amdgpu_bo_free_kernel - free BO for kernel use
431 *
432 * @bo: amdgpu BO to free
433 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
434 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
435 *
436 * unmaps and unpin a BO for kernel internal use.
437 */
438void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
439 void **cpu_addr)
440{
441 if (*bo == NULL)
442 return;
443
444 WARN_ON(amdgpu_ttm_adev((*bo)->tbo.bdev)->in_suspend);
445
446 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
447 if (cpu_addr)
448 amdgpu_bo_kunmap(*bo);
449
450 amdgpu_bo_unpin(*bo);
451 amdgpu_bo_unreserve(*bo);
452 }
453 amdgpu_bo_unref(bo);
454
455 if (gpu_addr)
456 *gpu_addr = 0;
457
458 if (cpu_addr)
459 *cpu_addr = NULL;
460}
461
462/* Validate bo size is bit bigger than the request domain */
463static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
464 unsigned long size, u32 domain)
465{
466 struct ttm_resource_manager *man = NULL;
467
468 /*
469 * If GTT is part of requested domains the check must succeed to
470 * allow fall back to GTT.
471 */
472 if (domain & AMDGPU_GEM_DOMAIN_GTT)
473 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
474 else if (domain & AMDGPU_GEM_DOMAIN_VRAM)
475 man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
476 else
477 return true;
478
479 if (!man) {
480 if (domain & AMDGPU_GEM_DOMAIN_GTT)
481 WARN_ON_ONCE("GTT domain requested but GTT mem manager uninitialized");
482 return false;
483 }
484
485 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU, _DOMAIN_DOORBELL */
486 if (size < man->size)
487 return true;
488
489 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size, man->size);
490 return false;
491}
492
493bool amdgpu_bo_support_uswc(u64 bo_flags)
494{
495
496#ifdef CONFIG_X86_32
497 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
498 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
499 */
500 return false;
501#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
502 /* Don't try to enable write-combining when it can't work, or things
503 * may be slow
504 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
505 */
506
507#ifndef CONFIG_COMPILE_TEST
508#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
509 thanks to write-combining
510#endif
511
512 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
513 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
514 "better performance thanks to write-combining\n");
515 return false;
516#else
517 /* For architectures that don't support WC memory,
518 * mask out the WC flag from the BO
519 */
520 if (!drm_arch_can_wc_memory())
521 return false;
522
523 return true;
524#endif
525}
526
527/**
528 * amdgpu_bo_create - create an &amdgpu_bo buffer object
529 * @adev: amdgpu device object
530 * @bp: parameters to be used for the buffer object
531 * @bo_ptr: pointer to the buffer object pointer
532 *
533 * Creates an &amdgpu_bo buffer object.
534 *
535 * Returns:
536 * 0 for success or a negative error code on failure.
537 */
538int amdgpu_bo_create(struct amdgpu_device *adev,
539 struct amdgpu_bo_param *bp,
540 struct amdgpu_bo **bo_ptr)
541{
542 struct ttm_operation_ctx ctx = {
543 .interruptible = (bp->type != ttm_bo_type_kernel),
544 .no_wait_gpu = bp->no_wait_gpu,
545 /* We opt to avoid OOM on system pages allocations */
546 .gfp_retry_mayfail = true,
547 .allow_res_evict = bp->type != ttm_bo_type_kernel,
548 .resv = bp->resv
549 };
550 struct amdgpu_bo *bo;
551 unsigned long page_align, size = bp->size;
552 int r;
553
554 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
555 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
556 /* GWS and OA don't need any alignment. */
557 page_align = bp->byte_align;
558 size <<= PAGE_SHIFT;
559
560 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
561 /* Both size and alignment must be a multiple of 4. */
562 page_align = ALIGN(bp->byte_align, 4);
563 size = ALIGN(size, 4) << PAGE_SHIFT;
564 } else {
565 /* Memory should be aligned at least to a page size. */
566 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
567 size = ALIGN(size, PAGE_SIZE);
568 }
569
570 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
571 return -ENOMEM;
572
573 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo));
574
575 *bo_ptr = NULL;
576 bo = kvzalloc(bp->bo_ptr_size, GFP_KERNEL);
577 if (bo == NULL)
578 return -ENOMEM;
579 drm_gem_private_object_init(adev_to_drm(adev), &bo->tbo.base, size);
580 bo->vm_bo = NULL;
581 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
582 bp->domain;
583 bo->allowed_domains = bo->preferred_domains;
584 if (bp->type != ttm_bo_type_kernel &&
585 !(bp->flags & AMDGPU_GEM_CREATE_DISCARDABLE) &&
586 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
587 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
588
589 bo->flags = bp->flags;
590
591 if (adev->gmc.mem_partitions)
592 /* For GPUs with spatial partitioning, bo->xcp_id=-1 means any partition */
593 bo->xcp_id = bp->xcp_id_plus1 - 1;
594 else
595 /* For GPUs without spatial partitioning */
596 bo->xcp_id = 0;
597
598 if (!amdgpu_bo_support_uswc(bo->flags))
599 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
600
601 if (adev->ras_enabled)
602 bo->flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE;
603
604 bo->tbo.bdev = &adev->mman.bdev;
605 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
606 AMDGPU_GEM_DOMAIN_GDS))
607 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
608 else
609 amdgpu_bo_placement_from_domain(bo, bp->domain);
610 if (bp->type == ttm_bo_type_kernel)
611 bo->tbo.priority = 1;
612
613 if (!bp->destroy)
614 bp->destroy = &amdgpu_bo_destroy;
615
616 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, bp->type,
617 &bo->placement, page_align, &ctx, NULL,
618 bp->resv, bp->destroy);
619 if (unlikely(r != 0))
620 return r;
621
622 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
623 bo->tbo.resource->mem_type == TTM_PL_VRAM &&
624 amdgpu_bo_in_cpu_visible_vram(bo))
625 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
626 ctx.bytes_moved);
627 else
628 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
629
630 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
631 bo->tbo.resource->mem_type == TTM_PL_VRAM) {
632 struct dma_fence *fence;
633
634 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence, true);
635 if (unlikely(r))
636 goto fail_unreserve;
637
638 dma_resv_add_fence(bo->tbo.base.resv, fence,
639 DMA_RESV_USAGE_KERNEL);
640 dma_fence_put(fence);
641 }
642 if (!bp->resv)
643 amdgpu_bo_unreserve(bo);
644 *bo_ptr = bo;
645
646 trace_amdgpu_bo_create(bo);
647
648 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
649 if (bp->type == ttm_bo_type_device)
650 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
651
652 return 0;
653
654fail_unreserve:
655 if (!bp->resv)
656 dma_resv_unlock(bo->tbo.base.resv);
657 amdgpu_bo_unref(&bo);
658 return r;
659}
660
661/**
662 * amdgpu_bo_create_user - create an &amdgpu_bo_user buffer object
663 * @adev: amdgpu device object
664 * @bp: parameters to be used for the buffer object
665 * @ubo_ptr: pointer to the buffer object pointer
666 *
667 * Create a BO to be used by user application;
668 *
669 * Returns:
670 * 0 for success or a negative error code on failure.
671 */
672
673int amdgpu_bo_create_user(struct amdgpu_device *adev,
674 struct amdgpu_bo_param *bp,
675 struct amdgpu_bo_user **ubo_ptr)
676{
677 struct amdgpu_bo *bo_ptr;
678 int r;
679
680 bp->bo_ptr_size = sizeof(struct amdgpu_bo_user);
681 bp->destroy = &amdgpu_bo_user_destroy;
682 r = amdgpu_bo_create(adev, bp, &bo_ptr);
683 if (r)
684 return r;
685
686 *ubo_ptr = to_amdgpu_bo_user(bo_ptr);
687 return r;
688}
689
690/**
691 * amdgpu_bo_create_vm - create an &amdgpu_bo_vm buffer object
692 * @adev: amdgpu device object
693 * @bp: parameters to be used for the buffer object
694 * @vmbo_ptr: pointer to the buffer object pointer
695 *
696 * Create a BO to be for GPUVM.
697 *
698 * Returns:
699 * 0 for success or a negative error code on failure.
700 */
701
702int amdgpu_bo_create_vm(struct amdgpu_device *adev,
703 struct amdgpu_bo_param *bp,
704 struct amdgpu_bo_vm **vmbo_ptr)
705{
706 struct amdgpu_bo *bo_ptr;
707 int r;
708
709 /* bo_ptr_size will be determined by the caller and it depends on
710 * num of amdgpu_vm_pt entries.
711 */
712 BUG_ON(bp->bo_ptr_size < sizeof(struct amdgpu_bo_vm));
713 r = amdgpu_bo_create(adev, bp, &bo_ptr);
714 if (r)
715 return r;
716
717 *vmbo_ptr = to_amdgpu_bo_vm(bo_ptr);
718 return r;
719}
720
721/**
722 * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list
723 *
724 * @vmbo: BO that will be inserted into the shadow list
725 *
726 * Insert a BO to the shadow list.
727 */
728void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo)
729{
730 struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev);
731
732 mutex_lock(&adev->shadow_list_lock);
733 list_add_tail(&vmbo->shadow_list, &adev->shadow_list);
734 vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo);
735 vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy;
736 mutex_unlock(&adev->shadow_list_lock);
737}
738
739/**
740 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
741 *
742 * @shadow: &amdgpu_bo shadow to be restored
743 * @fence: dma_fence associated with the operation
744 *
745 * Copies a buffer object's shadow content back to the object.
746 * This is used for recovering a buffer from its shadow in case of a gpu
747 * reset where vram context may be lost.
748 *
749 * Returns:
750 * 0 for success or a negative error code on failure.
751 */
752int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
753
754{
755 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
756 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
757 uint64_t shadow_addr, parent_addr;
758
759 shadow_addr = amdgpu_bo_gpu_offset(shadow);
760 parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
761
762 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
763 amdgpu_bo_size(shadow), NULL, fence,
764 true, false, false);
765}
766
767/**
768 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
769 * @bo: &amdgpu_bo buffer object to be mapped
770 * @ptr: kernel virtual address to be returned
771 *
772 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
773 * amdgpu_bo_kptr() to get the kernel virtual address.
774 *
775 * Returns:
776 * 0 for success or a negative error code on failure.
777 */
778int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
779{
780 void *kptr;
781 long r;
782
783 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
784 return -EPERM;
785
786 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL,
787 false, MAX_SCHEDULE_TIMEOUT);
788 if (r < 0)
789 return r;
790
791 kptr = amdgpu_bo_kptr(bo);
792 if (kptr) {
793 if (ptr)
794 *ptr = kptr;
795 return 0;
796 }
797
798 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap);
799 if (r)
800 return r;
801
802 if (ptr)
803 *ptr = amdgpu_bo_kptr(bo);
804
805 return 0;
806}
807
808/**
809 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
810 * @bo: &amdgpu_bo buffer object
811 *
812 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
813 *
814 * Returns:
815 * the virtual address of a buffer object area.
816 */
817void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
818{
819 bool is_iomem;
820
821 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
822}
823
824/**
825 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
826 * @bo: &amdgpu_bo buffer object to be unmapped
827 *
828 * Unmaps a kernel map set up by amdgpu_bo_kmap().
829 */
830void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
831{
832 if (bo->kmap.bo)
833 ttm_bo_kunmap(&bo->kmap);
834}
835
836/**
837 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
838 * @bo: &amdgpu_bo buffer object
839 *
840 * References the contained &ttm_buffer_object.
841 *
842 * Returns:
843 * a refcounted pointer to the &amdgpu_bo buffer object.
844 */
845struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
846{
847 if (bo == NULL)
848 return NULL;
849
850 ttm_bo_get(&bo->tbo);
851 return bo;
852}
853
854/**
855 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
856 * @bo: &amdgpu_bo buffer object
857 *
858 * Unreferences the contained &ttm_buffer_object and clear the pointer
859 */
860void amdgpu_bo_unref(struct amdgpu_bo **bo)
861{
862 struct ttm_buffer_object *tbo;
863
864 if ((*bo) == NULL)
865 return;
866
867 tbo = &((*bo)->tbo);
868 ttm_bo_put(tbo);
869 *bo = NULL;
870}
871
872/**
873 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
874 * @bo: &amdgpu_bo buffer object to be pinned
875 * @domain: domain to be pinned to
876 * @min_offset: the start of requested address range
877 * @max_offset: the end of requested address range
878 *
879 * Pins the buffer object according to requested domain and address range. If
880 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
881 * pin_count and pin_size accordingly.
882 *
883 * Pinning means to lock pages in memory along with keeping them at a fixed
884 * offset. It is required when a buffer can not be moved, for example, when
885 * a display buffer is being scanned out.
886 *
887 * Compared with amdgpu_bo_pin(), this function gives more flexibility on
888 * where to pin a buffer if there are specific restrictions on where a buffer
889 * must be located.
890 *
891 * Returns:
892 * 0 for success or a negative error code on failure.
893 */
894int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
895 u64 min_offset, u64 max_offset)
896{
897 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
898 struct ttm_operation_ctx ctx = { false, false };
899 int r, i;
900
901 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
902 return -EPERM;
903
904 if (WARN_ON_ONCE(min_offset > max_offset))
905 return -EINVAL;
906
907 /* Check domain to be pinned to against preferred domains */
908 if (bo->preferred_domains & domain)
909 domain = bo->preferred_domains & domain;
910
911 /* A shared bo cannot be migrated to VRAM */
912 if (bo->tbo.base.import_attach) {
913 if (domain & AMDGPU_GEM_DOMAIN_GTT)
914 domain = AMDGPU_GEM_DOMAIN_GTT;
915 else
916 return -EINVAL;
917 }
918
919 if (bo->tbo.pin_count) {
920 uint32_t mem_type = bo->tbo.resource->mem_type;
921 uint32_t mem_flags = bo->tbo.resource->placement;
922
923 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
924 return -EINVAL;
925
926 if ((mem_type == TTM_PL_VRAM) &&
927 (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS) &&
928 !(mem_flags & TTM_PL_FLAG_CONTIGUOUS))
929 return -EINVAL;
930
931 ttm_bo_pin(&bo->tbo);
932
933 if (max_offset != 0) {
934 u64 domain_start = amdgpu_ttm_domain_start(adev,
935 mem_type);
936 WARN_ON_ONCE(max_offset <
937 (amdgpu_bo_gpu_offset(bo) - domain_start));
938 }
939
940 return 0;
941 }
942
943 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
944 * See function amdgpu_display_supported_domains()
945 */
946 domain = amdgpu_bo_get_preferred_domain(adev, domain);
947
948 if (bo->tbo.base.import_attach)
949 dma_buf_pin(bo->tbo.base.import_attach);
950
951 /* force to pin into visible video ram */
952 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
953 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
954 amdgpu_bo_placement_from_domain(bo, domain);
955 for (i = 0; i < bo->placement.num_placement; i++) {
956 unsigned int fpfn, lpfn;
957
958 fpfn = min_offset >> PAGE_SHIFT;
959 lpfn = max_offset >> PAGE_SHIFT;
960
961 if (fpfn > bo->placements[i].fpfn)
962 bo->placements[i].fpfn = fpfn;
963 if (!bo->placements[i].lpfn ||
964 (lpfn && lpfn < bo->placements[i].lpfn))
965 bo->placements[i].lpfn = lpfn;
966 }
967
968 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
969 if (unlikely(r)) {
970 dev_err(adev->dev, "%p pin failed\n", bo);
971 goto error;
972 }
973
974 ttm_bo_pin(&bo->tbo);
975
976 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
977 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
978 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
979 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
980 &adev->visible_pin_size);
981 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
982 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
983 }
984
985error:
986 return r;
987}
988
989/**
990 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
991 * @bo: &amdgpu_bo buffer object to be pinned
992 * @domain: domain to be pinned to
993 *
994 * A simple wrapper to amdgpu_bo_pin_restricted().
995 * Provides a simpler API for buffers that do not have any strict restrictions
996 * on where a buffer must be located.
997 *
998 * Returns:
999 * 0 for success or a negative error code on failure.
1000 */
1001int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
1002{
1003 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1004 return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
1005}
1006
1007/**
1008 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
1009 * @bo: &amdgpu_bo buffer object to be unpinned
1010 *
1011 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
1012 * Changes placement and pin size accordingly.
1013 *
1014 * Returns:
1015 * 0 for success or a negative error code on failure.
1016 */
1017void amdgpu_bo_unpin(struct amdgpu_bo *bo)
1018{
1019 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1020
1021 ttm_bo_unpin(&bo->tbo);
1022 if (bo->tbo.pin_count)
1023 return;
1024
1025 if (bo->tbo.base.import_attach)
1026 dma_buf_unpin(bo->tbo.base.import_attach);
1027
1028 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) {
1029 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
1030 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
1031 &adev->visible_pin_size);
1032 } else if (bo->tbo.resource->mem_type == TTM_PL_TT) {
1033 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
1034 }
1035
1036}
1037
1038static const char * const amdgpu_vram_names[] = {
1039 "UNKNOWN",
1040 "GDDR1",
1041 "DDR2",
1042 "GDDR3",
1043 "GDDR4",
1044 "GDDR5",
1045 "HBM",
1046 "DDR3",
1047 "DDR4",
1048 "GDDR6",
1049 "DDR5",
1050 "LPDDR4",
1051 "LPDDR5"
1052};
1053
1054/**
1055 * amdgpu_bo_init - initialize memory manager
1056 * @adev: amdgpu device object
1057 *
1058 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1059 *
1060 * Returns:
1061 * 0 for success or a negative error code on failure.
1062 */
1063int amdgpu_bo_init(struct amdgpu_device *adev)
1064{
1065 /* On A+A platform, VRAM can be mapped as WB */
1066 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
1067 /* reserve PAT memory space to WC for VRAM */
1068 int r = arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1069 adev->gmc.aper_size);
1070
1071 if (r) {
1072 DRM_ERROR("Unable to set WC memtype for the aperture base\n");
1073 return r;
1074 }
1075
1076 /* Add an MTRR for the VRAM */
1077 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1078 adev->gmc.aper_size);
1079 }
1080
1081 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1082 adev->gmc.mc_vram_size >> 20,
1083 (unsigned long long)adev->gmc.aper_size >> 20);
1084 DRM_INFO("RAM width %dbits %s\n",
1085 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1086 return amdgpu_ttm_init(adev);
1087}
1088
1089/**
1090 * amdgpu_bo_fini - tear down memory manager
1091 * @adev: amdgpu device object
1092 *
1093 * Reverses amdgpu_bo_init() to tear down memory manager.
1094 */
1095void amdgpu_bo_fini(struct amdgpu_device *adev)
1096{
1097 int idx;
1098
1099 amdgpu_ttm_fini(adev);
1100
1101 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
1102 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) {
1103 arch_phys_wc_del(adev->gmc.vram_mtrr);
1104 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
1105 }
1106 drm_dev_exit(idx);
1107 }
1108}
1109
1110/**
1111 * amdgpu_bo_set_tiling_flags - set tiling flags
1112 * @bo: &amdgpu_bo buffer object
1113 * @tiling_flags: new flags
1114 *
1115 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1116 * kernel driver to set the tiling flags on a buffer.
1117 *
1118 * Returns:
1119 * 0 for success or a negative error code on failure.
1120 */
1121int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1122{
1123 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1124 struct amdgpu_bo_user *ubo;
1125
1126 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1127 if (adev->family <= AMDGPU_FAMILY_CZ &&
1128 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1129 return -EINVAL;
1130
1131 ubo = to_amdgpu_bo_user(bo);
1132 ubo->tiling_flags = tiling_flags;
1133 return 0;
1134}
1135
1136/**
1137 * amdgpu_bo_get_tiling_flags - get tiling flags
1138 * @bo: &amdgpu_bo buffer object
1139 * @tiling_flags: returned flags
1140 *
1141 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1142 * set the tiling flags on a buffer.
1143 */
1144void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1145{
1146 struct amdgpu_bo_user *ubo;
1147
1148 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1149 dma_resv_assert_held(bo->tbo.base.resv);
1150 ubo = to_amdgpu_bo_user(bo);
1151
1152 if (tiling_flags)
1153 *tiling_flags = ubo->tiling_flags;
1154}
1155
1156/**
1157 * amdgpu_bo_set_metadata - set metadata
1158 * @bo: &amdgpu_bo buffer object
1159 * @metadata: new metadata
1160 * @metadata_size: size of the new metadata
1161 * @flags: flags of the new metadata
1162 *
1163 * Sets buffer object's metadata, its size and flags.
1164 * Used via GEM ioctl.
1165 *
1166 * Returns:
1167 * 0 for success or a negative error code on failure.
1168 */
1169int amdgpu_bo_set_metadata(struct amdgpu_bo *bo, void *metadata,
1170 u32 metadata_size, uint64_t flags)
1171{
1172 struct amdgpu_bo_user *ubo;
1173 void *buffer;
1174
1175 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1176 ubo = to_amdgpu_bo_user(bo);
1177 if (!metadata_size) {
1178 if (ubo->metadata_size) {
1179 kfree(ubo->metadata);
1180 ubo->metadata = NULL;
1181 ubo->metadata_size = 0;
1182 }
1183 return 0;
1184 }
1185
1186 if (metadata == NULL)
1187 return -EINVAL;
1188
1189 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1190 if (buffer == NULL)
1191 return -ENOMEM;
1192
1193 kfree(ubo->metadata);
1194 ubo->metadata_flags = flags;
1195 ubo->metadata = buffer;
1196 ubo->metadata_size = metadata_size;
1197
1198 return 0;
1199}
1200
1201/**
1202 * amdgpu_bo_get_metadata - get metadata
1203 * @bo: &amdgpu_bo buffer object
1204 * @buffer: returned metadata
1205 * @buffer_size: size of the buffer
1206 * @metadata_size: size of the returned metadata
1207 * @flags: flags of the returned metadata
1208 *
1209 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1210 * less than metadata_size.
1211 * Used via GEM ioctl.
1212 *
1213 * Returns:
1214 * 0 for success or a negative error code on failure.
1215 */
1216int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1217 size_t buffer_size, uint32_t *metadata_size,
1218 uint64_t *flags)
1219{
1220 struct amdgpu_bo_user *ubo;
1221
1222 if (!buffer && !metadata_size)
1223 return -EINVAL;
1224
1225 BUG_ON(bo->tbo.type == ttm_bo_type_kernel);
1226 ubo = to_amdgpu_bo_user(bo);
1227 if (metadata_size)
1228 *metadata_size = ubo->metadata_size;
1229
1230 if (buffer) {
1231 if (buffer_size < ubo->metadata_size)
1232 return -EINVAL;
1233
1234 if (ubo->metadata_size)
1235 memcpy(buffer, ubo->metadata, ubo->metadata_size);
1236 }
1237
1238 if (flags)
1239 *flags = ubo->metadata_flags;
1240
1241 return 0;
1242}
1243
1244/**
1245 * amdgpu_bo_move_notify - notification about a memory move
1246 * @bo: pointer to a buffer object
1247 * @evict: if this move is evicting the buffer from the graphics address space
1248 *
1249 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1250 * bookkeeping.
1251 * TTM driver callback which is called when ttm moves a buffer.
1252 */
1253void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, bool evict)
1254{
1255 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1256 struct amdgpu_bo *abo;
1257
1258 if (!amdgpu_bo_is_amdgpu_bo(bo))
1259 return;
1260
1261 abo = ttm_to_amdgpu_bo(bo);
1262 amdgpu_vm_bo_invalidate(adev, abo, evict);
1263
1264 amdgpu_bo_kunmap(abo);
1265
1266 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1267 bo->resource->mem_type != TTM_PL_SYSTEM)
1268 dma_buf_move_notify(abo->tbo.base.dma_buf);
1269
1270 /* remember the eviction */
1271 if (evict)
1272 atomic64_inc(&adev->num_evictions);
1273}
1274
1275void amdgpu_bo_get_memory(struct amdgpu_bo *bo,
1276 struct amdgpu_mem_stats *stats)
1277{
1278 uint64_t size = amdgpu_bo_size(bo);
1279 unsigned int domain;
1280
1281 /* Abort if the BO doesn't currently have a backing store */
1282 if (!bo->tbo.resource)
1283 return;
1284
1285 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1286 switch (domain) {
1287 case AMDGPU_GEM_DOMAIN_VRAM:
1288 stats->vram += size;
1289 if (amdgpu_bo_in_cpu_visible_vram(bo))
1290 stats->visible_vram += size;
1291 break;
1292 case AMDGPU_GEM_DOMAIN_GTT:
1293 stats->gtt += size;
1294 break;
1295 case AMDGPU_GEM_DOMAIN_CPU:
1296 default:
1297 stats->cpu += size;
1298 break;
1299 }
1300
1301 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) {
1302 stats->requested_vram += size;
1303 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1304 stats->requested_visible_vram += size;
1305
1306 if (domain != AMDGPU_GEM_DOMAIN_VRAM) {
1307 stats->evicted_vram += size;
1308 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
1309 stats->evicted_visible_vram += size;
1310 }
1311 } else if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_GTT) {
1312 stats->requested_gtt += size;
1313 }
1314}
1315
1316/**
1317 * amdgpu_bo_release_notify - notification about a BO being released
1318 * @bo: pointer to a buffer object
1319 *
1320 * Wipes VRAM buffers whose contents should not be leaked before the
1321 * memory is released.
1322 */
1323void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1324{
1325 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1326 struct dma_fence *fence = NULL;
1327 struct amdgpu_bo *abo;
1328 int r;
1329
1330 if (!amdgpu_bo_is_amdgpu_bo(bo))
1331 return;
1332
1333 abo = ttm_to_amdgpu_bo(bo);
1334
1335 WARN_ON(abo->vm_bo);
1336
1337 if (abo->kfd_bo)
1338 amdgpu_amdkfd_release_notify(abo);
1339
1340 /* We only remove the fence if the resv has individualized. */
1341 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1342 && bo->base.resv != &bo->base._resv);
1343 if (bo->base.resv == &bo->base._resv)
1344 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1345
1346 if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM ||
1347 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE) ||
1348 adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
1349 return;
1350
1351 if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv)))
1352 return;
1353
1354 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence, true);
1355 if (!WARN_ON(r)) {
1356 amdgpu_bo_fence(abo, fence, false);
1357 dma_fence_put(fence);
1358 }
1359
1360 dma_resv_unlock(bo->base.resv);
1361}
1362
1363/**
1364 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1365 * @bo: pointer to a buffer object
1366 *
1367 * Notifies the driver we are taking a fault on this BO and have reserved it,
1368 * also performs bookkeeping.
1369 * TTM driver callback for dealing with vm faults.
1370 *
1371 * Returns:
1372 * 0 for success or a negative error code on failure.
1373 */
1374vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1375{
1376 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1377 struct ttm_operation_ctx ctx = { false, false };
1378 struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1379 int r;
1380
1381 /* Remember that this BO was accessed by the CPU */
1382 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1383
1384 if (bo->resource->mem_type != TTM_PL_VRAM)
1385 return 0;
1386
1387 if (amdgpu_bo_in_cpu_visible_vram(abo))
1388 return 0;
1389
1390 /* Can't move a pinned BO to visible VRAM */
1391 if (abo->tbo.pin_count > 0)
1392 return VM_FAULT_SIGBUS;
1393
1394 /* hurrah the memory is not visible ! */
1395 atomic64_inc(&adev->num_vram_cpu_page_faults);
1396 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1397 AMDGPU_GEM_DOMAIN_GTT);
1398
1399 /* Avoid costly evictions; only set GTT as a busy placement */
1400 abo->placement.num_busy_placement = 1;
1401 abo->placement.busy_placement = &abo->placements[1];
1402
1403 r = ttm_bo_validate(bo, &abo->placement, &ctx);
1404 if (unlikely(r == -EBUSY || r == -ERESTARTSYS))
1405 return VM_FAULT_NOPAGE;
1406 else if (unlikely(r))
1407 return VM_FAULT_SIGBUS;
1408
1409 /* this should never happen */
1410 if (bo->resource->mem_type == TTM_PL_VRAM &&
1411 !amdgpu_bo_in_cpu_visible_vram(abo))
1412 return VM_FAULT_SIGBUS;
1413
1414 ttm_bo_move_to_lru_tail_unlocked(bo);
1415 return 0;
1416}
1417
1418/**
1419 * amdgpu_bo_fence - add fence to buffer object
1420 *
1421 * @bo: buffer object in question
1422 * @fence: fence to add
1423 * @shared: true if fence should be added shared
1424 *
1425 */
1426void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1427 bool shared)
1428{
1429 struct dma_resv *resv = bo->tbo.base.resv;
1430 int r;
1431
1432 r = dma_resv_reserve_fences(resv, 1);
1433 if (r) {
1434 /* As last resort on OOM we block for the fence */
1435 dma_fence_wait(fence, false);
1436 return;
1437 }
1438
1439 dma_resv_add_fence(resv, fence, shared ? DMA_RESV_USAGE_READ :
1440 DMA_RESV_USAGE_WRITE);
1441}
1442
1443/**
1444 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1445 *
1446 * @adev: amdgpu device pointer
1447 * @resv: reservation object to sync to
1448 * @sync_mode: synchronization mode
1449 * @owner: fence owner
1450 * @intr: Whether the wait is interruptible
1451 *
1452 * Extract the fences from the reservation object and waits for them to finish.
1453 *
1454 * Returns:
1455 * 0 on success, errno otherwise.
1456 */
1457int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1458 enum amdgpu_sync_mode sync_mode, void *owner,
1459 bool intr)
1460{
1461 struct amdgpu_sync sync;
1462 int r;
1463
1464 amdgpu_sync_create(&sync);
1465 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1466 r = amdgpu_sync_wait(&sync, intr);
1467 amdgpu_sync_free(&sync);
1468 return r;
1469}
1470
1471/**
1472 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1473 * @bo: buffer object to wait for
1474 * @owner: fence owner
1475 * @intr: Whether the wait is interruptible
1476 *
1477 * Wrapper to wait for fences in a BO.
1478 * Returns:
1479 * 0 on success, errno otherwise.
1480 */
1481int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1482{
1483 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1484
1485 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1486 AMDGPU_SYNC_NE_OWNER, owner, intr);
1487}
1488
1489/**
1490 * amdgpu_bo_gpu_offset - return GPU offset of bo
1491 * @bo: amdgpu object for which we query the offset
1492 *
1493 * Note: object should either be pinned or reserved when calling this
1494 * function, it might be useful to add check for this for debugging.
1495 *
1496 * Returns:
1497 * current GPU offset of the object.
1498 */
1499u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1500{
1501 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM);
1502 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1503 !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
1504 WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET);
1505 WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM &&
1506 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1507
1508 return amdgpu_bo_gpu_offset_no_check(bo);
1509}
1510
1511/**
1512 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1513 * @bo: amdgpu object for which we query the offset
1514 *
1515 * Returns:
1516 * current GPU offset of the object without raising warnings.
1517 */
1518u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1519{
1520 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1521 uint64_t offset = AMDGPU_BO_INVALID_OFFSET;
1522
1523 if (bo->tbo.resource->mem_type == TTM_PL_TT)
1524 offset = amdgpu_gmc_agp_addr(&bo->tbo);
1525
1526 if (offset == AMDGPU_BO_INVALID_OFFSET)
1527 offset = (bo->tbo.resource->start << PAGE_SHIFT) +
1528 amdgpu_ttm_domain_start(adev, bo->tbo.resource->mem_type);
1529
1530 return amdgpu_gmc_sign_extend(offset);
1531}
1532
1533/**
1534 * amdgpu_bo_get_preferred_domain - get preferred domain
1535 * @adev: amdgpu device object
1536 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1537 *
1538 * Returns:
1539 * Which of the allowed domains is preferred for allocating the BO.
1540 */
1541uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
1542 uint32_t domain)
1543{
1544 if ((domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) &&
1545 ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_STONEY))) {
1546 domain = AMDGPU_GEM_DOMAIN_VRAM;
1547 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1548 domain = AMDGPU_GEM_DOMAIN_GTT;
1549 }
1550 return domain;
1551}
1552
1553#if defined(CONFIG_DEBUG_FS)
1554#define amdgpu_bo_print_flag(m, bo, flag) \
1555 do { \
1556 if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
1557 seq_printf((m), " " #flag); \
1558 } \
1559 } while (0)
1560
1561/**
1562 * amdgpu_bo_print_info - print BO info in debugfs file
1563 *
1564 * @id: Index or Id of the BO
1565 * @bo: Requested BO for printing info
1566 * @m: debugfs file
1567 *
1568 * Print BO information in debugfs file
1569 *
1570 * Returns:
1571 * Size of the BO in bytes.
1572 */
1573u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
1574{
1575 struct dma_buf_attachment *attachment;
1576 struct dma_buf *dma_buf;
1577 const char *placement;
1578 unsigned int pin_count;
1579 u64 size;
1580
1581 if (dma_resv_trylock(bo->tbo.base.resv)) {
1582 unsigned int domain;
1583 domain = amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type);
1584 switch (domain) {
1585 case AMDGPU_GEM_DOMAIN_VRAM:
1586 if (amdgpu_bo_in_cpu_visible_vram(bo))
1587 placement = "VRAM VISIBLE";
1588 else
1589 placement = "VRAM";
1590 break;
1591 case AMDGPU_GEM_DOMAIN_GTT:
1592 placement = "GTT";
1593 break;
1594 case AMDGPU_GEM_DOMAIN_CPU:
1595 default:
1596 placement = "CPU";
1597 break;
1598 }
1599 dma_resv_unlock(bo->tbo.base.resv);
1600 } else {
1601 placement = "UNKNOWN";
1602 }
1603
1604 size = amdgpu_bo_size(bo);
1605 seq_printf(m, "\t\t0x%08x: %12lld byte %s",
1606 id, size, placement);
1607
1608 pin_count = READ_ONCE(bo->tbo.pin_count);
1609 if (pin_count)
1610 seq_printf(m, " pin count %d", pin_count);
1611
1612 dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
1613 attachment = READ_ONCE(bo->tbo.base.import_attach);
1614
1615 if (attachment)
1616 seq_printf(m, " imported from ino:%lu", file_inode(dma_buf->file)->i_ino);
1617 else if (dma_buf)
1618 seq_printf(m, " exported as ino:%lu", file_inode(dma_buf->file)->i_ino);
1619
1620 amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
1621 amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
1622 amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
1623 amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
1624 amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
1625 amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
1626 amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
1627
1628 seq_puts(m, "\n");
1629
1630 return size;
1631}
1632#endif