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1/*
2 * Architecture specific OF callbacks.
3 */
4#include <linux/bootmem.h>
5#include <linux/io.h>
6#include <linux/interrupt.h>
7#include <linux/list.h>
8#include <linux/of.h>
9#include <linux/of_fdt.h>
10#include <linux/of_address.h>
11#include <linux/of_platform.h>
12#include <linux/of_irq.h>
13#include <linux/slab.h>
14#include <linux/pci.h>
15#include <linux/of_pci.h>
16#include <linux/initrd.h>
17
18#include <asm/hpet.h>
19#include <asm/irq_controller.h>
20#include <asm/apic.h>
21#include <asm/pci_x86.h>
22
23__initdata u64 initial_dtb;
24char __initdata cmd_line[COMMAND_LINE_SIZE];
25static LIST_HEAD(irq_domains);
26static DEFINE_RAW_SPINLOCK(big_irq_lock);
27
28int __initdata of_ioapic;
29
30#ifdef CONFIG_X86_IO_APIC
31static void add_interrupt_host(struct irq_domain *ih)
32{
33 unsigned long flags;
34
35 raw_spin_lock_irqsave(&big_irq_lock, flags);
36 list_add(&ih->l, &irq_domains);
37 raw_spin_unlock_irqrestore(&big_irq_lock, flags);
38}
39#endif
40
41static struct irq_domain *get_ih_from_node(struct device_node *controller)
42{
43 struct irq_domain *ih, *found = NULL;
44 unsigned long flags;
45
46 raw_spin_lock_irqsave(&big_irq_lock, flags);
47 list_for_each_entry(ih, &irq_domains, l) {
48 if (ih->controller == controller) {
49 found = ih;
50 break;
51 }
52 }
53 raw_spin_unlock_irqrestore(&big_irq_lock, flags);
54 return found;
55}
56
57unsigned int irq_create_of_mapping(struct device_node *controller,
58 const u32 *intspec, unsigned int intsize)
59{
60 struct irq_domain *ih;
61 u32 virq, type;
62 int ret;
63
64 ih = get_ih_from_node(controller);
65 if (!ih)
66 return 0;
67 ret = ih->xlate(ih, intspec, intsize, &virq, &type);
68 if (ret)
69 return 0;
70 if (type == IRQ_TYPE_NONE)
71 return virq;
72 irq_set_irq_type(virq, type);
73 return virq;
74}
75EXPORT_SYMBOL_GPL(irq_create_of_mapping);
76
77unsigned long pci_address_to_pio(phys_addr_t address)
78{
79 /*
80 * The ioport address can be directly used by inX / outX
81 */
82 BUG_ON(address >= (1 << 16));
83 return (unsigned long)address;
84}
85EXPORT_SYMBOL_GPL(pci_address_to_pio);
86
87void __init early_init_dt_scan_chosen_arch(unsigned long node)
88{
89 BUG();
90}
91
92void __init early_init_dt_add_memory_arch(u64 base, u64 size)
93{
94 BUG();
95}
96
97void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
98{
99 return __alloc_bootmem(size, align, __pa(MAX_DMA_ADDRESS));
100}
101
102#ifdef CONFIG_BLK_DEV_INITRD
103void __init early_init_dt_setup_initrd_arch(unsigned long start,
104 unsigned long end)
105{
106 initrd_start = (unsigned long)__va(start);
107 initrd_end = (unsigned long)__va(end);
108 initrd_below_start_ok = 1;
109}
110#endif
111
112void __init add_dtb(u64 data)
113{
114 initial_dtb = data + offsetof(struct setup_data, data);
115}
116
117/*
118 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
119 */
120static struct of_device_id __initdata ce4100_ids[] = {
121 { .compatible = "intel,ce4100-cp", },
122 { .compatible = "isa", },
123 { .compatible = "pci", },
124 {},
125};
126
127static int __init add_bus_probe(void)
128{
129 if (!of_have_populated_dt())
130 return 0;
131
132 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
133}
134module_init(add_bus_probe);
135
136#ifdef CONFIG_PCI
137struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
138{
139 struct device_node *np;
140
141 for_each_node_by_type(np, "pci") {
142 const void *prop;
143 unsigned int bus_min;
144
145 prop = of_get_property(np, "bus-range", NULL);
146 if (!prop)
147 continue;
148 bus_min = be32_to_cpup(prop);
149 if (bus->number == bus_min)
150 return np;
151 }
152 return NULL;
153}
154
155static int x86_of_pci_irq_enable(struct pci_dev *dev)
156{
157 struct of_irq oirq;
158 u32 virq;
159 int ret;
160 u8 pin;
161
162 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
163 if (ret)
164 return ret;
165 if (!pin)
166 return 0;
167
168 ret = of_irq_map_pci(dev, &oirq);
169 if (ret)
170 return ret;
171
172 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
173 oirq.size);
174 if (virq == 0)
175 return -EINVAL;
176 dev->irq = virq;
177 return 0;
178}
179
180static void x86_of_pci_irq_disable(struct pci_dev *dev)
181{
182}
183
184void __cpuinit x86_of_pci_init(void)
185{
186 pcibios_enable_irq = x86_of_pci_irq_enable;
187 pcibios_disable_irq = x86_of_pci_irq_disable;
188}
189#endif
190
191static void __init dtb_setup_hpet(void)
192{
193#ifdef CONFIG_HPET_TIMER
194 struct device_node *dn;
195 struct resource r;
196 int ret;
197
198 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
199 if (!dn)
200 return;
201 ret = of_address_to_resource(dn, 0, &r);
202 if (ret) {
203 WARN_ON(1);
204 return;
205 }
206 hpet_address = r.start;
207#endif
208}
209
210static void __init dtb_lapic_setup(void)
211{
212#ifdef CONFIG_X86_LOCAL_APIC
213 struct device_node *dn;
214 struct resource r;
215 int ret;
216
217 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
218 if (!dn)
219 return;
220
221 ret = of_address_to_resource(dn, 0, &r);
222 if (WARN_ON(ret))
223 return;
224
225 /* Did the boot loader setup the local APIC ? */
226 if (!cpu_has_apic) {
227 if (apic_force_enable(r.start))
228 return;
229 }
230 smp_found_config = 1;
231 pic_mode = 1;
232 register_lapic_address(r.start);
233 generic_processor_info(boot_cpu_physical_apicid,
234 GET_APIC_VERSION(apic_read(APIC_LVR)));
235#endif
236}
237
238#ifdef CONFIG_X86_IO_APIC
239static unsigned int ioapic_id;
240
241static void __init dtb_add_ioapic(struct device_node *dn)
242{
243 struct resource r;
244 int ret;
245
246 ret = of_address_to_resource(dn, 0, &r);
247 if (ret) {
248 printk(KERN_ERR "Can't obtain address from node %s.\n",
249 dn->full_name);
250 return;
251 }
252 mp_register_ioapic(++ioapic_id, r.start, gsi_top);
253}
254
255static void __init dtb_ioapic_setup(void)
256{
257 struct device_node *dn;
258
259 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
260 dtb_add_ioapic(dn);
261
262 if (nr_ioapics) {
263 of_ioapic = 1;
264 return;
265 }
266 printk(KERN_ERR "Error: No information about IO-APIC in OF.\n");
267}
268#else
269static void __init dtb_ioapic_setup(void) {}
270#endif
271
272static void __init dtb_apic_setup(void)
273{
274 dtb_lapic_setup();
275 dtb_ioapic_setup();
276}
277
278#ifdef CONFIG_OF_FLATTREE
279static void __init x86_flattree_get_config(void)
280{
281 u32 size, map_len;
282 void *new_dtb;
283
284 if (!initial_dtb)
285 return;
286
287 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK),
288 (u64)sizeof(struct boot_param_header));
289
290 initial_boot_params = early_memremap(initial_dtb, map_len);
291 size = be32_to_cpu(initial_boot_params->totalsize);
292 if (map_len < size) {
293 early_iounmap(initial_boot_params, map_len);
294 initial_boot_params = early_memremap(initial_dtb, size);
295 map_len = size;
296 }
297
298 new_dtb = alloc_bootmem(size);
299 memcpy(new_dtb, initial_boot_params, size);
300 early_iounmap(initial_boot_params, map_len);
301
302 initial_boot_params = new_dtb;
303
304 /* root level address cells */
305 of_scan_flat_dt(early_init_dt_scan_root, NULL);
306
307 unflatten_device_tree();
308}
309#else
310static inline void x86_flattree_get_config(void) { }
311#endif
312
313void __init x86_dtb_init(void)
314{
315 x86_flattree_get_config();
316
317 if (!of_have_populated_dt())
318 return;
319
320 dtb_setup_hpet();
321 dtb_apic_setup();
322}
323
324#ifdef CONFIG_X86_IO_APIC
325
326struct of_ioapic_type {
327 u32 out_type;
328 u32 trigger;
329 u32 polarity;
330};
331
332static struct of_ioapic_type of_ioapic_type[] =
333{
334 {
335 .out_type = IRQ_TYPE_EDGE_RISING,
336 .trigger = IOAPIC_EDGE,
337 .polarity = 1,
338 },
339 {
340 .out_type = IRQ_TYPE_LEVEL_LOW,
341 .trigger = IOAPIC_LEVEL,
342 .polarity = 0,
343 },
344 {
345 .out_type = IRQ_TYPE_LEVEL_HIGH,
346 .trigger = IOAPIC_LEVEL,
347 .polarity = 1,
348 },
349 {
350 .out_type = IRQ_TYPE_EDGE_FALLING,
351 .trigger = IOAPIC_EDGE,
352 .polarity = 0,
353 },
354};
355
356static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
357 u32 *out_hwirq, u32 *out_type)
358{
359 struct mp_ioapic_gsi *gsi_cfg;
360 struct io_apic_irq_attr attr;
361 struct of_ioapic_type *it;
362 u32 line, idx, type;
363
364 if (intsize < 2)
365 return -EINVAL;
366
367 line = *intspec;
368 idx = (u32) id->priv;
369 gsi_cfg = mp_ioapic_gsi_routing(idx);
370 *out_hwirq = line + gsi_cfg->gsi_base;
371
372 intspec++;
373 type = *intspec;
374
375 if (type >= ARRAY_SIZE(of_ioapic_type))
376 return -EINVAL;
377
378 it = of_ioapic_type + type;
379 *out_type = it->out_type;
380
381 set_io_apic_irq_attr(&attr, idx, line, it->trigger, it->polarity);
382
383 return io_apic_setup_irq_pin_once(*out_hwirq, cpu_to_node(0), &attr);
384}
385
386static void __init ioapic_add_ofnode(struct device_node *np)
387{
388 struct resource r;
389 int i, ret;
390
391 ret = of_address_to_resource(np, 0, &r);
392 if (ret) {
393 printk(KERN_ERR "Failed to obtain address for %s\n",
394 np->full_name);
395 return;
396 }
397
398 for (i = 0; i < nr_ioapics; i++) {
399 if (r.start == mpc_ioapic_addr(i)) {
400 struct irq_domain *id;
401
402 id = kzalloc(sizeof(*id), GFP_KERNEL);
403 BUG_ON(!id);
404 id->controller = np;
405 id->xlate = ioapic_xlate;
406 id->priv = (void *)i;
407 add_interrupt_host(id);
408 return;
409 }
410 }
411 printk(KERN_ERR "IOxAPIC at %s is not registered.\n", np->full_name);
412}
413
414void __init x86_add_irq_domains(void)
415{
416 struct device_node *dp;
417
418 if (!of_have_populated_dt())
419 return;
420
421 for_each_node_with_property(dp, "interrupt-controller") {
422 if (of_device_is_compatible(dp, "intel,ce4100-ioapic"))
423 ioapic_add_ofnode(dp);
424 }
425}
426#else
427void __init x86_add_irq_domains(void) { }
428#endif
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Architecture specific OF callbacks.
4 */
5#include <linux/export.h>
6#include <linux/io.h>
7#include <linux/interrupt.h>
8#include <linux/list.h>
9#include <linux/of.h>
10#include <linux/of_fdt.h>
11#include <linux/of_address.h>
12#include <linux/of_platform.h>
13#include <linux/of_irq.h>
14#include <linux/libfdt.h>
15#include <linux/slab.h>
16#include <linux/pci.h>
17#include <linux/of_pci.h>
18#include <linux/initrd.h>
19
20#include <asm/irqdomain.h>
21#include <asm/hpet.h>
22#include <asm/apic.h>
23#include <asm/io_apic.h>
24#include <asm/pci_x86.h>
25#include <asm/setup.h>
26#include <asm/i8259.h>
27#include <asm/prom.h>
28
29__initdata u64 initial_dtb;
30char __initdata cmd_line[COMMAND_LINE_SIZE];
31
32int __initdata of_ioapic;
33
34void __init add_dtb(u64 data)
35{
36 initial_dtb = data + offsetof(struct setup_data, data);
37}
38
39/*
40 * CE4100 ids. Will be moved to machine_device_initcall() once we have it.
41 */
42static struct of_device_id __initdata ce4100_ids[] = {
43 { .compatible = "intel,ce4100-cp", },
44 { .compatible = "isa", },
45 { .compatible = "pci", },
46 {},
47};
48
49static int __init add_bus_probe(void)
50{
51 if (!of_have_populated_dt())
52 return 0;
53
54 return of_platform_bus_probe(NULL, ce4100_ids, NULL);
55}
56device_initcall(add_bus_probe);
57
58#ifdef CONFIG_PCI
59struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
60{
61 struct device_node *np;
62
63 for_each_node_by_type(np, "pci") {
64 const void *prop;
65 unsigned int bus_min;
66
67 prop = of_get_property(np, "bus-range", NULL);
68 if (!prop)
69 continue;
70 bus_min = be32_to_cpup(prop);
71 if (bus->number == bus_min)
72 return np;
73 }
74 return NULL;
75}
76
77static int x86_of_pci_irq_enable(struct pci_dev *dev)
78{
79 u32 virq;
80 int ret;
81 u8 pin;
82
83 ret = pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
84 if (ret)
85 return ret;
86 if (!pin)
87 return 0;
88
89 virq = of_irq_parse_and_map_pci(dev, 0, 0);
90 if (virq == 0)
91 return -EINVAL;
92 dev->irq = virq;
93 return 0;
94}
95
96static void x86_of_pci_irq_disable(struct pci_dev *dev)
97{
98}
99
100void x86_of_pci_init(void)
101{
102 pcibios_enable_irq = x86_of_pci_irq_enable;
103 pcibios_disable_irq = x86_of_pci_irq_disable;
104}
105#endif
106
107static void __init dtb_setup_hpet(void)
108{
109#ifdef CONFIG_HPET_TIMER
110 struct device_node *dn;
111 struct resource r;
112 int ret;
113
114 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-hpet");
115 if (!dn)
116 return;
117 ret = of_address_to_resource(dn, 0, &r);
118 if (ret) {
119 WARN_ON(1);
120 return;
121 }
122 hpet_address = r.start;
123#endif
124}
125
126#ifdef CONFIG_X86_LOCAL_APIC
127
128static void __init dtb_cpu_setup(void)
129{
130 struct device_node *dn;
131 u32 apic_id;
132
133 for_each_of_cpu_node(dn) {
134 apic_id = of_get_cpu_hwid(dn, 0);
135 if (apic_id == ~0U) {
136 pr_warn("%pOF: missing local APIC ID\n", dn);
137 continue;
138 }
139 generic_processor_info(apic_id);
140 }
141}
142
143static void __init dtb_lapic_setup(void)
144{
145 struct device_node *dn;
146 struct resource r;
147 unsigned long lapic_addr = APIC_DEFAULT_PHYS_BASE;
148 int ret;
149
150 dn = of_find_compatible_node(NULL, NULL, "intel,ce4100-lapic");
151 if (dn) {
152 ret = of_address_to_resource(dn, 0, &r);
153 if (WARN_ON(ret))
154 return;
155 lapic_addr = r.start;
156 }
157
158 /* Did the boot loader setup the local APIC ? */
159 if (!boot_cpu_has(X86_FEATURE_APIC)) {
160 /* Try force enabling, which registers the APIC address */
161 if (!apic_force_enable(lapic_addr))
162 return;
163 } else {
164 register_lapic_address(lapic_addr);
165 }
166 smp_found_config = 1;
167 pic_mode = !of_property_read_bool(dn, "intel,virtual-wire-mode");
168 pr_info("%s compatibility mode.\n", pic_mode ? "IMCR and PIC" : "Virtual Wire");
169}
170
171#endif /* CONFIG_X86_LOCAL_APIC */
172
173#ifdef CONFIG_X86_IO_APIC
174static unsigned int ioapic_id;
175
176struct of_ioapic_type {
177 u32 out_type;
178 u32 is_level;
179 u32 active_low;
180};
181
182static struct of_ioapic_type of_ioapic_type[] =
183{
184 {
185 .out_type = IRQ_TYPE_EDGE_FALLING,
186 .is_level = 0,
187 .active_low = 1,
188 },
189 {
190 .out_type = IRQ_TYPE_LEVEL_HIGH,
191 .is_level = 1,
192 .active_low = 0,
193 },
194 {
195 .out_type = IRQ_TYPE_LEVEL_LOW,
196 .is_level = 1,
197 .active_low = 1,
198 },
199 {
200 .out_type = IRQ_TYPE_EDGE_RISING,
201 .is_level = 0,
202 .active_low = 0,
203 },
204};
205
206static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
207 unsigned int nr_irqs, void *arg)
208{
209 struct irq_fwspec *fwspec = (struct irq_fwspec *)arg;
210 struct of_ioapic_type *it;
211 struct irq_alloc_info tmp;
212 int type_index;
213
214 if (WARN_ON(fwspec->param_count < 2))
215 return -EINVAL;
216
217 type_index = fwspec->param[1];
218 if (type_index >= ARRAY_SIZE(of_ioapic_type))
219 return -EINVAL;
220
221 it = &of_ioapic_type[type_index];
222 ioapic_set_alloc_attr(&tmp, NUMA_NO_NODE, it->is_level, it->active_low);
223 tmp.devid = mpc_ioapic_id(mp_irqdomain_ioapic_idx(domain));
224 tmp.ioapic.pin = fwspec->param[0];
225
226 return mp_irqdomain_alloc(domain, virq, nr_irqs, &tmp);
227}
228
229static const struct irq_domain_ops ioapic_irq_domain_ops = {
230 .alloc = dt_irqdomain_alloc,
231 .free = mp_irqdomain_free,
232 .activate = mp_irqdomain_activate,
233 .deactivate = mp_irqdomain_deactivate,
234};
235
236static void __init dtb_add_ioapic(struct device_node *dn)
237{
238 struct resource r;
239 int ret;
240 struct ioapic_domain_cfg cfg = {
241 .type = IOAPIC_DOMAIN_DYNAMIC,
242 .ops = &ioapic_irq_domain_ops,
243 .dev = dn,
244 };
245
246 ret = of_address_to_resource(dn, 0, &r);
247 if (ret) {
248 pr_err("Can't obtain address from device node %pOF.\n", dn);
249 return;
250 }
251 mp_register_ioapic(++ioapic_id, r.start, gsi_top, &cfg);
252}
253
254static void __init dtb_ioapic_setup(void)
255{
256 struct device_node *dn;
257
258 for_each_compatible_node(dn, NULL, "intel,ce4100-ioapic")
259 dtb_add_ioapic(dn);
260
261 if (nr_ioapics) {
262 of_ioapic = 1;
263 return;
264 }
265 pr_err("Error: No information about IO-APIC in OF.\n");
266}
267#else
268static void __init dtb_ioapic_setup(void) {}
269#endif
270
271static void __init dtb_apic_setup(void)
272{
273#ifdef CONFIG_X86_LOCAL_APIC
274 dtb_lapic_setup();
275 dtb_cpu_setup();
276#endif
277 dtb_ioapic_setup();
278}
279
280#ifdef CONFIG_OF_EARLY_FLATTREE
281void __init x86_flattree_get_config(void)
282{
283 u32 size, map_len;
284 void *dt;
285
286 if (!initial_dtb)
287 return;
288
289 map_len = max(PAGE_SIZE - (initial_dtb & ~PAGE_MASK), (u64)128);
290
291 dt = early_memremap(initial_dtb, map_len);
292 size = fdt_totalsize(dt);
293 if (map_len < size) {
294 early_memunmap(dt, map_len);
295 dt = early_memremap(initial_dtb, size);
296 map_len = size;
297 }
298
299 early_init_dt_verify(dt);
300 unflatten_and_copy_device_tree();
301 early_memunmap(dt, map_len);
302}
303#endif
304
305void __init x86_dtb_init(void)
306{
307 if (!of_have_populated_dt())
308 return;
309
310 dtb_setup_hpet();
311 dtb_apic_setup();
312}