1#ifndef __PCR_H
 2#define __PCR_H
 3
 4struct pcr_ops {
 5	u64 (*read)(void);
 6	void (*write)(u64);
 
 
 
 
 
 7};
 8extern const struct pcr_ops *pcr_ops;
 9
10extern void deferred_pcr_work_irq(int irq, struct pt_regs *regs);
11extern void schedule_deferred_pcr_work(void);
12
13#define PCR_PIC_PRIV		0x00000001 /* PIC access is privileged */
14#define PCR_STRACE		0x00000002 /* Trace supervisor events  */
15#define PCR_UTRACE		0x00000004 /* Trace user events        */
16#define PCR_N2_HTRACE		0x00000008 /* Trace hypervisor events  */
17#define PCR_N2_TOE_OV0		0x00000010 /* Trap if PIC 0 overflows  */
18#define PCR_N2_TOE_OV1		0x00000020 /* Trap if PIC 1 overflows  */
19#define PCR_N2_MASK0		0x00003fc0
20#define PCR_N2_MASK0_SHIFT	6
21#define PCR_N2_SL0		0x0003c000
22#define PCR_N2_SL0_SHIFT	14
23#define PCR_N2_OV0		0x00040000
24#define PCR_N2_MASK1		0x07f80000
25#define PCR_N2_MASK1_SHIFT	19
26#define PCR_N2_SL1		0x78000000
27#define PCR_N2_SL1_SHIFT	27
28#define PCR_N2_OV1		0x80000000
29
30extern unsigned int picl_shift;
 
 
 
 
 
 
 
 
 
 
 
31
32/* In order to commonize as much of the implementation as
33 * possible, we use PICH as our counter.  Mostly this is
34 * to accommodate Niagara-1 which can only count insn cycles
35 * in PICH.
36 */
37static inline u64 picl_value(unsigned int nmi_hz)
38{
39	u32 delta = local_cpu_data().clock_tick / (nmi_hz << picl_shift);
40
41	return ((u64)((0 - delta) & 0xffffffff)) << 32;
42}
43
44extern u64 pcr_enable;
45
46extern int pcr_arch_init(void);
47
48#endif /* __PCR_H */

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __PCR_H
 3#define __PCR_H
 4
 5struct pcr_ops {
 6	u64 (*read_pcr)(unsigned long);
 7	void (*write_pcr)(unsigned long, u64);
 8	u64 (*read_pic)(unsigned long);
 9	void (*write_pic)(unsigned long, u64);
10	u64 (*nmi_picl_value)(unsigned int nmi_hz);
11	u64 pcr_nmi_enable;
12	u64 pcr_nmi_disable;
13};
14extern const struct pcr_ops *pcr_ops;
15
16void deferred_pcr_work_irq(int irq, struct pt_regs *regs);
17void schedule_deferred_pcr_work(void);
18
19#define PCR_PIC_PRIV		0x00000001 /* PIC access is privileged */
20#define PCR_STRACE		0x00000002 /* Trace supervisor events  */
21#define PCR_UTRACE		0x00000004 /* Trace user events        */
22#define PCR_N2_HTRACE		0x00000008 /* Trace hypervisor events  */
23#define PCR_N2_TOE_OV0		0x00000010 /* Trap if PIC 0 overflows  */
24#define PCR_N2_TOE_OV1		0x00000020 /* Trap if PIC 1 overflows  */
25#define PCR_N2_MASK0		0x00003fc0
26#define PCR_N2_MASK0_SHIFT	6
27#define PCR_N2_SL0		0x0003c000
28#define PCR_N2_SL0_SHIFT	14
29#define PCR_N2_OV0		0x00040000
30#define PCR_N2_MASK1		0x07f80000
31#define PCR_N2_MASK1_SHIFT	19
32#define PCR_N2_SL1		0x78000000
33#define PCR_N2_SL1_SHIFT	27
34#define PCR_N2_OV1		0x80000000
35
36#define PCR_N4_OV		0x00000001 /* PIC overflow             */
37#define PCR_N4_TOE		0x00000002 /* Trap On Event            */
38#define PCR_N4_UTRACE		0x00000004 /* Trace user events        */
39#define PCR_N4_STRACE		0x00000008 /* Trace supervisor events  */
40#define PCR_N4_HTRACE		0x00000010 /* Trace hypervisor events  */
41#define PCR_N4_MASK		0x000007e0 /* Event mask               */
42#define PCR_N4_MASK_SHIFT	5
43#define PCR_N4_SL		0x0000f800 /* Event Select             */
44#define PCR_N4_SL_SHIFT		11
45#define PCR_N4_PICNPT		0x00010000 /* PIC non-privileged trap  */
46#define PCR_N4_PICNHT		0x00020000 /* PIC non-hypervisor trap  */
47#define PCR_N4_NTC		0x00040000 /* Next-To-Commit wrap      */
48
49int pcr_arch_init(void);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
50
51#endif /* __PCR_H */