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1#ifndef __ASM_SH_IO_H
2#define __ASM_SH_IO_H
3
4/*
5 * Convention:
6 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
7 * while in{b,w,l}/out{b,w,l} are for ISA
8 *
9 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
10 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
11 *
12 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
13 * automatically, there are also __raw versions, which do not.
14 */
15#include <linux/errno.h>
16#include <asm/cache.h>
17#include <asm/system.h>
18#include <asm/addrspace.h>
19#include <asm/machvec.h>
20#include <asm/pgtable.h>
21#include <asm-generic/iomap.h>
22
23#ifdef __KERNEL__
24#define __IO_PREFIX generic
25#include <asm/io_generic.h>
26#include <asm/io_trapped.h>
27
28#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
29#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
30#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
31#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
32
33#define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
34#define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
35#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
36#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
37
38#define readb_relaxed(c) ({ u8 __v = __raw_readb(c); __v; })
39#define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16) \
40 __raw_readw(c)); __v; })
41#define readl_relaxed(c) ({ u32 __v = le32_to_cpu((__force __le32) \
42 __raw_readl(c)); __v; })
43#define readq_relaxed(c) ({ u64 __v = le64_to_cpu((__force __le64) \
44 __raw_readq(c)); __v; })
45
46#define writeb_relaxed(v,c) ((void)__raw_writeb(v,c))
47#define writew_relaxed(v,c) ((void)__raw_writew((__force u16) \
48 cpu_to_le16(v),c))
49#define writel_relaxed(v,c) ((void)__raw_writel((__force u32) \
50 cpu_to_le32(v),c))
51#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64) \
52 cpu_to_le64(v),c))
53
54#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
55#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
56#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
57#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
58
59#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
60#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
61#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
62#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
63
64#define readsb(p,d,l) __raw_readsb(p,d,l)
65#define readsw(p,d,l) __raw_readsw(p,d,l)
66#define readsl(p,d,l) __raw_readsl(p,d,l)
67
68#define writesb(p,d,l) __raw_writesb(p,d,l)
69#define writesw(p,d,l) __raw_writesw(p,d,l)
70#define writesl(p,d,l) __raw_writesl(p,d,l)
71
72#define __BUILD_UNCACHED_IO(bwlq, type) \
73static inline type read##bwlq##_uncached(unsigned long addr) \
74{ \
75 type ret; \
76 jump_to_uncached(); \
77 ret = __raw_read##bwlq(addr); \
78 back_to_cached(); \
79 return ret; \
80} \
81 \
82static inline void write##bwlq##_uncached(type v, unsigned long addr) \
83{ \
84 jump_to_uncached(); \
85 __raw_write##bwlq(v, addr); \
86 back_to_cached(); \
87}
88
89__BUILD_UNCACHED_IO(b, u8)
90__BUILD_UNCACHED_IO(w, u16)
91__BUILD_UNCACHED_IO(l, u32)
92__BUILD_UNCACHED_IO(q, u64)
93
94#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
95 \
96static inline void \
97pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
98 unsigned int count) \
99{ \
100 const volatile type *__addr = addr; \
101 \
102 while (count--) { \
103 __raw_write##bwlq(*__addr, mem); \
104 __addr++; \
105 } \
106} \
107 \
108static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
109 void *addr, unsigned int count) \
110{ \
111 volatile type *__addr = addr; \
112 \
113 while (count--) { \
114 *__addr = __raw_read##bwlq(mem); \
115 __addr++; \
116 } \
117}
118
119__BUILD_MEMORY_STRING(__raw_, b, u8)
120__BUILD_MEMORY_STRING(__raw_, w, u16)
121
122#ifdef CONFIG_SUPERH32
123void __raw_writesl(void __iomem *addr, const void *data, int longlen);
124void __raw_readsl(const void __iomem *addr, void *data, int longlen);
125#else
126__BUILD_MEMORY_STRING(__raw_, l, u32)
127#endif
128
129__BUILD_MEMORY_STRING(__raw_, q, u64)
130
131#ifdef CONFIG_HAS_IOPORT
132
133/*
134 * Slowdown I/O port space accesses for antique hardware.
135 */
136#undef CONF_SLOWDOWN_IO
137
138/*
139 * On SuperH I/O ports are memory mapped, so we access them using normal
140 * load/store instructions. sh_io_port_base is the virtual address to
141 * which all ports are being mapped.
142 */
143extern const unsigned long sh_io_port_base;
144
145static inline void __set_io_port_base(unsigned long pbase)
146{
147 *(unsigned long *)&sh_io_port_base = pbase;
148 barrier();
149}
150
151#ifdef CONFIG_GENERIC_IOMAP
152#define __ioport_map ioport_map
153#else
154extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
155#endif
156
157#ifdef CONF_SLOWDOWN_IO
158#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
159#else
160#define SLOW_DOWN_IO
161#endif
162
163#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
164 \
165static inline void pfx##out##bwlq##p(type val, unsigned long port) \
166{ \
167 volatile type *__addr; \
168 \
169 __addr = __ioport_map(port, sizeof(type)); \
170 *__addr = val; \
171 slow; \
172} \
173 \
174static inline type pfx##in##bwlq##p(unsigned long port) \
175{ \
176 volatile type *__addr; \
177 type __val; \
178 \
179 __addr = __ioport_map(port, sizeof(type)); \
180 __val = *__addr; \
181 slow; \
182 \
183 return __val; \
184}
185
186#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
187 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
188 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
189
190#define BUILDIO_IOPORT(bwlq, type) \
191 __BUILD_IOPORT_PFX(, bwlq, type)
192
193BUILDIO_IOPORT(b, u8)
194BUILDIO_IOPORT(w, u16)
195BUILDIO_IOPORT(l, u32)
196BUILDIO_IOPORT(q, u64)
197
198#define __BUILD_IOPORT_STRING(bwlq, type) \
199 \
200static inline void outs##bwlq(unsigned long port, const void *addr, \
201 unsigned int count) \
202{ \
203 const volatile type *__addr = addr; \
204 \
205 while (count--) { \
206 out##bwlq(*__addr, port); \
207 __addr++; \
208 } \
209} \
210 \
211static inline void ins##bwlq(unsigned long port, void *addr, \
212 unsigned int count) \
213{ \
214 volatile type *__addr = addr; \
215 \
216 while (count--) { \
217 *__addr = in##bwlq(port); \
218 __addr++; \
219 } \
220}
221
222__BUILD_IOPORT_STRING(b, u8)
223__BUILD_IOPORT_STRING(w, u16)
224__BUILD_IOPORT_STRING(l, u32)
225__BUILD_IOPORT_STRING(q, u64)
226
227#endif
228
229#define IO_SPACE_LIMIT 0xffffffff
230
231/* synco on SH-4A, otherwise a nop */
232#define mmiowb() wmb()
233
234/* We really want to try and get these to memcpy etc */
235void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
236void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
237void memset_io(volatile void __iomem *, int, unsigned long);
238
239/* Quad-word real-mode I/O, don't ask.. */
240unsigned long long peek_real_address_q(unsigned long long addr);
241unsigned long long poke_real_address_q(unsigned long long addr,
242 unsigned long long val);
243
244#if !defined(CONFIG_MMU)
245#define virt_to_phys(address) ((unsigned long)(address))
246#define phys_to_virt(address) ((void *)(address))
247#else
248#define virt_to_phys(address) (__pa(address))
249#define phys_to_virt(address) (__va(address))
250#endif
251
252/*
253 * On 32-bit SH, we traditionally have the whole physical address space
254 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
255 * not need to do anything but place the address in the proper segment.
256 * This is true for P1 and P2 addresses, as well as some P3 ones.
257 * However, most of the P3 addresses and newer cores using extended
258 * addressing need to map through page tables, so the ioremap()
259 * implementation becomes a bit more complicated.
260 *
261 * See arch/sh/mm/ioremap.c for additional notes on this.
262 *
263 * We cheat a bit and always return uncachable areas until we've fixed
264 * the drivers to handle caching properly.
265 *
266 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
267 * doesn't exist, so everything must go through page tables.
268 */
269#ifdef CONFIG_MMU
270void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
271 pgprot_t prot, void *caller);
272void __iounmap(void __iomem *addr);
273
274static inline void __iomem *
275__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
276{
277 return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
278}
279
280static inline void __iomem *
281__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
282{
283#ifdef CONFIG_29BIT
284 phys_addr_t last_addr = offset + size - 1;
285
286 /*
287 * For P1 and P2 space this is trivial, as everything is already
288 * mapped. Uncached access for P1 addresses are done through P2.
289 * In the P3 case or for addresses outside of the 29-bit space,
290 * mapping must be done by the PMB or by using page tables.
291 */
292 if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
293 u64 flags = pgprot_val(prot);
294
295 /*
296 * Anything using the legacy PTEA space attributes needs
297 * to be kicked down to page table mappings.
298 */
299 if (unlikely(flags & _PAGE_PCC_MASK))
300 return NULL;
301 if (unlikely(flags & _PAGE_CACHABLE))
302 return (void __iomem *)P1SEGADDR(offset);
303
304 return (void __iomem *)P2SEGADDR(offset);
305 }
306
307 /* P4 above the store queues are always mapped. */
308 if (unlikely(offset >= P3_ADDR_MAX))
309 return (void __iomem *)P4SEGADDR(offset);
310#endif
311
312 return NULL;
313}
314
315static inline void __iomem *
316__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
317{
318 void __iomem *ret;
319
320 ret = __ioremap_trapped(offset, size);
321 if (ret)
322 return ret;
323
324 ret = __ioremap_29bit(offset, size, prot);
325 if (ret)
326 return ret;
327
328 return __ioremap(offset, size, prot);
329}
330#else
331#define __ioremap(offset, size, prot) ((void __iomem *)(offset))
332#define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset))
333#define __iounmap(addr) do { } while (0)
334#endif /* CONFIG_MMU */
335
336static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
337{
338 return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
339}
340
341static inline void __iomem *
342ioremap_cache(phys_addr_t offset, unsigned long size)
343{
344 return __ioremap_mode(offset, size, PAGE_KERNEL);
345}
346
347#ifdef CONFIG_HAVE_IOREMAP_PROT
348static inline void __iomem *
349ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
350{
351 return __ioremap_mode(offset, size, __pgprot(flags));
352}
353#endif
354
355#ifdef CONFIG_IOREMAP_FIXED
356extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
357extern int iounmap_fixed(void __iomem *);
358extern void ioremap_fixed_init(void);
359#else
360static inline void __iomem *
361ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
362{
363 BUG();
364 return NULL;
365}
366
367static inline void ioremap_fixed_init(void) { }
368static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
369#endif
370
371#define ioremap_nocache ioremap
372#define iounmap __iounmap
373
374/*
375 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
376 * access
377 */
378#define xlate_dev_mem_ptr(p) __va(p)
379
380/*
381 * Convert a virtual cached pointer to an uncached pointer
382 */
383#define xlate_dev_kmem_ptr(p) p
384
385#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
386int valid_phys_addr_range(unsigned long addr, size_t size);
387int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
388
389#endif /* __KERNEL__ */
390
391#endif /* __ASM_SH_IO_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef __ASM_SH_IO_H
3#define __ASM_SH_IO_H
4
5/*
6 * Convention:
7 * read{b,w,l,q}/write{b,w,l,q} are for PCI,
8 * while in{b,w,l}/out{b,w,l} are for ISA
9 *
10 * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
11 * and 'string' versions: ins{b,w,l}/outs{b,w,l}
12 *
13 * While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
14 * automatically, there are also __raw versions, which do not.
15 */
16#include <linux/errno.h>
17#include <asm/cache.h>
18#include <asm/addrspace.h>
19#include <asm/machvec.h>
20#include <asm/page.h>
21#include <linux/pgtable.h>
22#include <asm-generic/iomap.h>
23
24#define __IO_PREFIX generic
25#include <asm/io_generic.h>
26#include <asm-generic/pci_iomap.h>
27#include <mach/mangle-port.h>
28
29#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
30#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
31#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
32#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
33
34#define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
35#define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
36#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
37#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
38
39#define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; })
40#define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; })
41#define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; })
42#define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; })
43
44#define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c))
45#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c))
46#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
47#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
48
49#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
50#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
51#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
52#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
53
54#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
55#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
56#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
57#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
58
59#define readsb(p,d,l) __raw_readsb(p,d,l)
60#define readsw(p,d,l) __raw_readsw(p,d,l)
61#define readsl(p,d,l) __raw_readsl(p,d,l)
62
63#define writesb(p,d,l) __raw_writesb(p,d,l)
64#define writesw(p,d,l) __raw_writesw(p,d,l)
65#define writesl(p,d,l) __raw_writesl(p,d,l)
66
67#define __BUILD_UNCACHED_IO(bwlq, type) \
68static inline type read##bwlq##_uncached(unsigned long addr) \
69{ \
70 type ret; \
71 jump_to_uncached(); \
72 ret = __raw_read##bwlq(addr); \
73 back_to_cached(); \
74 return ret; \
75} \
76 \
77static inline void write##bwlq##_uncached(type v, unsigned long addr) \
78{ \
79 jump_to_uncached(); \
80 __raw_write##bwlq(v, addr); \
81 back_to_cached(); \
82}
83
84__BUILD_UNCACHED_IO(b, u8)
85__BUILD_UNCACHED_IO(w, u16)
86__BUILD_UNCACHED_IO(l, u32)
87__BUILD_UNCACHED_IO(q, u64)
88
89#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
90 \
91static inline void \
92pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
93 unsigned int count) \
94{ \
95 const volatile type *__addr = addr; \
96 \
97 while (count--) { \
98 __raw_write##bwlq(*__addr, mem); \
99 __addr++; \
100 } \
101} \
102 \
103static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
104 void *addr, unsigned int count) \
105{ \
106 volatile type *__addr = addr; \
107 \
108 while (count--) { \
109 *__addr = __raw_read##bwlq(mem); \
110 __addr++; \
111 } \
112}
113
114__BUILD_MEMORY_STRING(__raw_, b, u8)
115__BUILD_MEMORY_STRING(__raw_, w, u16)
116
117void __raw_writesl(void __iomem *addr, const void *data, int longlen);
118void __raw_readsl(const void __iomem *addr, void *data, int longlen);
119
120__BUILD_MEMORY_STRING(__raw_, q, u64)
121
122#define ioport_map ioport_map
123#define ioport_unmap ioport_unmap
124#define pci_iounmap pci_iounmap
125
126#define ioread8 ioread8
127#define ioread16 ioread16
128#define ioread16be ioread16be
129#define ioread32 ioread32
130#define ioread32be ioread32be
131
132#define iowrite8 iowrite8
133#define iowrite16 iowrite16
134#define iowrite16be iowrite16be
135#define iowrite32 iowrite32
136#define iowrite32be iowrite32be
137
138#define ioread8_rep ioread8_rep
139#define ioread16_rep ioread16_rep
140#define ioread32_rep ioread32_rep
141
142#define iowrite8_rep iowrite8_rep
143#define iowrite16_rep iowrite16_rep
144#define iowrite32_rep iowrite32_rep
145
146#ifdef CONFIG_HAS_IOPORT_MAP
147
148/*
149 * Slowdown I/O port space accesses for antique hardware.
150 */
151#undef CONF_SLOWDOWN_IO
152
153/*
154 * On SuperH I/O ports are memory mapped, so we access them using normal
155 * load/store instructions. sh_io_port_base is the virtual address to
156 * which all ports are being mapped.
157 */
158extern unsigned long sh_io_port_base;
159
160static inline void __set_io_port_base(unsigned long pbase)
161{
162 *(unsigned long *)&sh_io_port_base = pbase;
163 barrier();
164}
165
166#ifdef CONFIG_GENERIC_IOMAP
167#define __ioport_map ioport_map
168#else
169extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
170#endif
171
172#ifdef CONF_SLOWDOWN_IO
173#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
174#else
175#define SLOW_DOWN_IO
176#endif
177
178#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
179 \
180static inline void pfx##out##bwlq##p(type val, unsigned long port) \
181{ \
182 volatile type *__addr; \
183 \
184 __addr = (void __iomem *)sh_io_port_base + port; \
185 *__addr = val; \
186 slow; \
187} \
188 \
189static inline type pfx##in##bwlq##p(unsigned long port) \
190{ \
191 volatile type *__addr; \
192 type __val; \
193 \
194 __addr = (void __iomem *)sh_io_port_base + port; \
195 __val = *__addr; \
196 slow; \
197 \
198 return __val; \
199}
200
201#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
202 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
203 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
204
205#define BUILDIO_IOPORT(bwlq, type) \
206 __BUILD_IOPORT_PFX(, bwlq, type)
207
208BUILDIO_IOPORT(b, u8)
209BUILDIO_IOPORT(w, u16)
210BUILDIO_IOPORT(l, u32)
211BUILDIO_IOPORT(q, u64)
212
213#define __BUILD_IOPORT_STRING(bwlq, type) \
214 \
215static inline void outs##bwlq(unsigned long port, const void *addr, \
216 unsigned int count) \
217{ \
218 const volatile type *__addr = addr; \
219 \
220 while (count--) { \
221 out##bwlq(*__addr, port); \
222 __addr++; \
223 } \
224} \
225 \
226static inline void ins##bwlq(unsigned long port, void *addr, \
227 unsigned int count) \
228{ \
229 volatile type *__addr = addr; \
230 \
231 while (count--) { \
232 *__addr = in##bwlq(port); \
233 __addr++; \
234 } \
235}
236
237__BUILD_IOPORT_STRING(b, u8)
238__BUILD_IOPORT_STRING(w, u16)
239__BUILD_IOPORT_STRING(l, u32)
240__BUILD_IOPORT_STRING(q, u64)
241
242#else /* !CONFIG_HAS_IOPORT_MAP */
243
244#include <asm/io_noioport.h>
245
246#endif
247
248#define inb(addr) inb(addr)
249#define inw(addr) inw(addr)
250#define inl(addr) inl(addr)
251#define outb(x, addr) outb((x), (addr))
252#define outw(x, addr) outw((x), (addr))
253#define outl(x, addr) outl((x), (addr))
254
255#define inb_p(addr) inb(addr)
256#define inw_p(addr) inw(addr)
257#define inl_p(addr) inl(addr)
258#define outb_p(x, addr) outb((x), (addr))
259#define outw_p(x, addr) outw((x), (addr))
260#define outl_p(x, addr) outl((x), (addr))
261
262#define insb insb
263#define insw insw
264#define insl insl
265#define outsb outsb
266#define outsw outsw
267#define outsl outsl
268
269#define IO_SPACE_LIMIT 0xffffffff
270
271/* We really want to try and get these to memcpy etc */
272#define memset_io memset_io
273#define memcpy_fromio memcpy_fromio
274#define memcpy_toio memcpy_toio
275void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
276void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
277void memset_io(volatile void __iomem *, int, unsigned long);
278
279/* Quad-word real-mode I/O, don't ask.. */
280unsigned long long peek_real_address_q(unsigned long long addr);
281unsigned long long poke_real_address_q(unsigned long long addr,
282 unsigned long long val);
283
284#if !defined(CONFIG_MMU)
285#define virt_to_phys(address) ((unsigned long)(address))
286#define phys_to_virt(address) ((void *)(address))
287#else
288#define virt_to_phys(address) (__pa(address))
289#define phys_to_virt(address) (__va(address))
290#endif
291
292#ifdef CONFIG_MMU
293/*
294 * I/O memory mapping functions.
295 */
296#define ioremap_prot ioremap_prot
297#define iounmap iounmap
298
299#define _PAGE_IOREMAP pgprot_val(PAGE_KERNEL_NOCACHE)
300
301#define ioremap_cache(addr, size) \
302 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
303#endif /* CONFIG_MMU */
304
305#include <asm-generic/io.h>
306
307#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
308int valid_phys_addr_range(phys_addr_t addr, size_t size);
309int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
310
311#endif /* __ASM_SH_IO_H */