1/*
 2 * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
 3 * differently than every other instruction, so it is set to 0 (write)
 4 * even though the instructions are read instructions. This means that
 5 * during an abort the instructions will be treated as a write and the
 6 * handler will raise a signal from unwriteable locations if they
 7 * fault. We have to specifically check for these instructions
 8 * from the abort handlers to treat them properly.
 9 *
10 */
11
12	.macro	do_thumb_abort, fsr, pc, psr, tmp
13	tst	\psr, #PSR_T_BIT
14	beq	not_thumb
15	ldrh	\tmp, [\pc]			@ Read aborted Thumb instruction
 
16	and	\tmp, \tmp, # 0xfe00		@ Mask opcode field
17	cmp	\tmp, # 0x5600			@ Is it ldrsb?
18	orreq	\tmp, \tmp, #1 << 11		@ Set L-bit if yes
19	tst	\tmp, #1 << 11			@ L = 0 -> write
20	orreq	\fsr, \fsr, #1 << 11		@ yes.
21	b	do_DataAbort
22not_thumb:
23	.endm
24
25/*
26 * We check for the following instruction encoding for LDRD.
27 *
28 * [27:25] == 000
29 *   [7:4] == 1101
30 *    [20] == 0
31 */
32	.macro	do_ldrd_abort, tmp, insn
33	tst	\insn, #0x0e100000		@ [27:25,20] == 0
34	bne	not_ldrd
35	and	\tmp, \insn, #0x000000f0	@ [7:4] == 1101
36	cmp	\tmp, #0x000000d0
37	beq	do_DataAbort
38not_ldrd:
39	.endm
40

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb)
 4 * differently than every other instruction, so it is set to 0 (write)
 5 * even though the instructions are read instructions. This means that
 6 * during an abort the instructions will be treated as a write and the
 7 * handler will raise a signal from unwriteable locations if they
 8 * fault. We have to specifically check for these instructions
 9 * from the abort handlers to treat them properly.
10 *
11 */
12
13	.macro	do_thumb_abort, fsr, pc, psr, tmp
14	tst	\psr, #PSR_T_BIT
15	beq	not_thumb
16	ldrh	\tmp, [\pc]			@ Read aborted Thumb instruction
17	uaccess_disable ip			@ disable userspace access
18	and	\tmp, \tmp, # 0xfe00		@ Mask opcode field
19	cmp	\tmp, # 0x5600			@ Is it ldrsb?
20	orreq	\tmp, \tmp, #1 << 11		@ Set L-bit if yes
21	tst	\tmp, #1 << 11			@ L = 0 -> write
22	orreq	\fsr, \fsr, #1 << 11		@ yes.
23	b	do_DataAbort
24not_thumb:
25	.endm
26
27/*
28 * We check for the following instruction encoding for LDRD.
29 *
30 * [27:25] == 000
31 *   [7:4] == 1101
32 *    [20] == 0
33 */
34	.macro	teq_ldrd, tmp, insn
35	mov	\tmp, #0x0e100000
36	orr	\tmp, #0x000000f0
37	and	\tmp, \insn, \tmp
38	teq	\tmp, #0x000000d0
 
 
39	.endm