Loading...
1/*
2 * Fifo-attached Serial Interface (FSI) support for SH7724
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ssi.c
8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/delay.h>
16#include <linux/pm_runtime.h>
17#include <linux/io.h>
18#include <linux/slab.h>
19#include <sound/soc.h>
20#include <sound/sh_fsi.h>
21
22/* PortA/PortB register */
23#define REG_DO_FMT 0x0000
24#define REG_DOFF_CTL 0x0004
25#define REG_DOFF_ST 0x0008
26#define REG_DI_FMT 0x000C
27#define REG_DIFF_CTL 0x0010
28#define REG_DIFF_ST 0x0014
29#define REG_CKG1 0x0018
30#define REG_CKG2 0x001C
31#define REG_DIDT 0x0020
32#define REG_DODT 0x0024
33#define REG_MUTE_ST 0x0028
34#define REG_OUT_SEL 0x0030
35
36/* master register */
37#define MST_CLK_RST 0x0210
38#define MST_SOFT_RST 0x0214
39#define MST_FIFO_SZ 0x0218
40
41/* core register (depend on FSI version) */
42#define A_MST_CTLR 0x0180
43#define B_MST_CTLR 0x01A0
44#define CPU_INT_ST 0x01F4
45#define CPU_IEMSK 0x01F8
46#define CPU_IMSK 0x01FC
47#define INT_ST 0x0200
48#define IEMSK 0x0204
49#define IMSK 0x0208
50
51/* DO_FMT */
52/* DI_FMT */
53#define CR_BWS_24 (0x0 << 20) /* FSI2 */
54#define CR_BWS_16 (0x1 << 20) /* FSI2 */
55#define CR_BWS_20 (0x2 << 20) /* FSI2 */
56
57#define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
58#define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
59#define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
60
61#define CR_MONO (0x0 << 4)
62#define CR_MONO_D (0x1 << 4)
63#define CR_PCM (0x2 << 4)
64#define CR_I2S (0x3 << 4)
65#define CR_TDM (0x4 << 4)
66#define CR_TDM_D (0x5 << 4)
67
68/* DOFF_CTL */
69/* DIFF_CTL */
70#define IRQ_HALF 0x00100000
71#define FIFO_CLR 0x00000001
72
73/* DOFF_ST */
74#define ERR_OVER 0x00000010
75#define ERR_UNDER 0x00000001
76#define ST_ERR (ERR_OVER | ERR_UNDER)
77
78/* CKG1 */
79#define ACKMD_MASK 0x00007000
80#define BPFMD_MASK 0x00000700
81#define DIMD (1 << 4)
82#define DOMD (1 << 0)
83
84/* A/B MST_CTLR */
85#define BP (1 << 4) /* Fix the signal of Biphase output */
86#define SE (1 << 0) /* Fix the master clock */
87
88/* CLK_RST */
89#define CRB (1 << 4)
90#define CRA (1 << 0)
91
92/* IO SHIFT / MACRO */
93#define BI_SHIFT 12
94#define BO_SHIFT 8
95#define AI_SHIFT 4
96#define AO_SHIFT 0
97#define AB_IO(param, shift) (param << shift)
98
99/* SOFT_RST */
100#define PBSR (1 << 12) /* Port B Software Reset */
101#define PASR (1 << 8) /* Port A Software Reset */
102#define IR (1 << 4) /* Interrupt Reset */
103#define FSISR (1 << 0) /* Software Reset */
104
105/* OUT_SEL (FSI2) */
106#define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
107 /* 1: Biphase and serial */
108
109/* FIFO_SZ */
110#define FIFO_SZ_MASK 0x7
111
112#define FSI_RATES SNDRV_PCM_RATE_8000_96000
113
114#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
115
116typedef int (*set_rate_func)(struct device *dev, int is_porta, int rate, int enable);
117
118/*
119 * FSI driver use below type name for variable
120 *
121 * xxx_num : number of data
122 * xxx_pos : position of data
123 * xxx_capa : capacity of data
124 */
125
126/*
127 * period/frame/sample image
128 *
129 * ex) PCM (2ch)
130 *
131 * period pos period pos
132 * [n] [n + 1]
133 * |<-------------------- period--------------------->|
134 * ==|============================================ ... =|==
135 * | |
136 * ||<----- frame ----->|<------ frame ----->| ... |
137 * |+--------------------+--------------------+- ... |
138 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
139 * |+--------------------+--------------------+- ... |
140 * ==|============================================ ... =|==
141 */
142
143/*
144 * FSI FIFO image
145 *
146 * | |
147 * | |
148 * | [ sample ] |
149 * | [ sample ] |
150 * | [ sample ] |
151 * | [ sample ] |
152 * --> go to codecs
153 */
154
155/*
156 * struct
157 */
158
159struct fsi_stream {
160 struct snd_pcm_substream *substream;
161
162 int fifo_sample_capa; /* sample capacity of FSI FIFO */
163 int buff_sample_capa; /* sample capacity of ALSA buffer */
164 int buff_sample_pos; /* sample position of ALSA buffer */
165 int period_samples; /* sample number / 1 period */
166 int period_pos; /* current period position */
167
168 int uerr_num;
169 int oerr_num;
170};
171
172struct fsi_priv {
173 void __iomem *base;
174 struct fsi_master *master;
175
176 struct fsi_stream playback;
177 struct fsi_stream capture;
178
179 u32 do_fmt;
180 u32 di_fmt;
181
182 int chan_num:16;
183 int clk_master:1;
184 int spdif:1;
185
186 long rate;
187};
188
189struct fsi_core {
190 int ver;
191
192 u32 int_st;
193 u32 iemsk;
194 u32 imsk;
195 u32 a_mclk;
196 u32 b_mclk;
197};
198
199struct fsi_master {
200 void __iomem *base;
201 int irq;
202 struct fsi_priv fsia;
203 struct fsi_priv fsib;
204 struct fsi_core *core;
205 struct sh_fsi_platform_info *info;
206 spinlock_t lock;
207};
208
209/*
210 * basic read write function
211 */
212
213static void __fsi_reg_write(u32 reg, u32 data)
214{
215 /* valid data area is 24bit */
216 data &= 0x00ffffff;
217
218 __raw_writel(data, reg);
219}
220
221static u32 __fsi_reg_read(u32 reg)
222{
223 return __raw_readl(reg);
224}
225
226static void __fsi_reg_mask_set(u32 reg, u32 mask, u32 data)
227{
228 u32 val = __fsi_reg_read(reg);
229
230 val &= ~mask;
231 val |= data & mask;
232
233 __fsi_reg_write(reg, val);
234}
235
236#define fsi_reg_write(p, r, d)\
237 __fsi_reg_write((u32)(p->base + REG_##r), d)
238
239#define fsi_reg_read(p, r)\
240 __fsi_reg_read((u32)(p->base + REG_##r))
241
242#define fsi_reg_mask_set(p, r, m, d)\
243 __fsi_reg_mask_set((u32)(p->base + REG_##r), m, d)
244
245#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
246#define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
247static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
248{
249 u32 ret;
250 unsigned long flags;
251
252 spin_lock_irqsave(&master->lock, flags);
253 ret = __fsi_reg_read((u32)(master->base + reg));
254 spin_unlock_irqrestore(&master->lock, flags);
255
256 return ret;
257}
258
259#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
260#define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
261static void _fsi_master_mask_set(struct fsi_master *master,
262 u32 reg, u32 mask, u32 data)
263{
264 unsigned long flags;
265
266 spin_lock_irqsave(&master->lock, flags);
267 __fsi_reg_mask_set((u32)(master->base + reg), mask, data);
268 spin_unlock_irqrestore(&master->lock, flags);
269}
270
271/*
272 * basic function
273 */
274
275static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
276{
277 return fsi->master;
278}
279
280static int fsi_is_clk_master(struct fsi_priv *fsi)
281{
282 return fsi->clk_master;
283}
284
285static int fsi_is_port_a(struct fsi_priv *fsi)
286{
287 return fsi->master->base == fsi->base;
288}
289
290static int fsi_is_spdif(struct fsi_priv *fsi)
291{
292 return fsi->spdif;
293}
294
295static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
296{
297 struct snd_soc_pcm_runtime *rtd = substream->private_data;
298
299 return rtd->cpu_dai;
300}
301
302static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
303{
304 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
305
306 if (dai->id == 0)
307 return &master->fsia;
308 else
309 return &master->fsib;
310}
311
312static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
313{
314 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
315}
316
317static set_rate_func fsi_get_info_set_rate(struct fsi_master *master)
318{
319 if (!master->info)
320 return NULL;
321
322 return master->info->set_rate;
323}
324
325static u32 fsi_get_info_flags(struct fsi_priv *fsi)
326{
327 int is_porta = fsi_is_port_a(fsi);
328 struct fsi_master *master = fsi_get_master(fsi);
329
330 if (!master->info)
331 return 0;
332
333 return is_porta ? master->info->porta_flags :
334 master->info->portb_flags;
335}
336
337static inline int fsi_stream_is_play(int stream)
338{
339 return stream == SNDRV_PCM_STREAM_PLAYBACK;
340}
341
342static inline int fsi_is_play(struct snd_pcm_substream *substream)
343{
344 return fsi_stream_is_play(substream->stream);
345}
346
347static inline struct fsi_stream *fsi_get_stream(struct fsi_priv *fsi,
348 int is_play)
349{
350 return is_play ? &fsi->playback : &fsi->capture;
351}
352
353static u32 fsi_get_port_shift(struct fsi_priv *fsi, int is_play)
354{
355 int is_porta = fsi_is_port_a(fsi);
356 u32 shift;
357
358 if (is_porta)
359 shift = is_play ? AO_SHIFT : AI_SHIFT;
360 else
361 shift = is_play ? BO_SHIFT : BI_SHIFT;
362
363 return shift;
364}
365
366static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
367{
368 return frames * fsi->chan_num;
369}
370
371static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
372{
373 return samples / fsi->chan_num;
374}
375
376static int fsi_stream_is_working(struct fsi_priv *fsi,
377 int is_play)
378{
379 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
380 struct fsi_master *master = fsi_get_master(fsi);
381 unsigned long flags;
382 int ret;
383
384 spin_lock_irqsave(&master->lock, flags);
385 ret = !!io->substream;
386 spin_unlock_irqrestore(&master->lock, flags);
387
388 return ret;
389}
390
391static void fsi_stream_push(struct fsi_priv *fsi,
392 int is_play,
393 struct snd_pcm_substream *substream)
394{
395 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
396 struct snd_pcm_runtime *runtime = substream->runtime;
397 struct fsi_master *master = fsi_get_master(fsi);
398 unsigned long flags;
399
400 spin_lock_irqsave(&master->lock, flags);
401 io->substream = substream;
402 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
403 io->buff_sample_pos = 0;
404 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
405 io->period_pos = 0;
406 io->oerr_num = -1; /* ignore 1st err */
407 io->uerr_num = -1; /* ignore 1st err */
408 spin_unlock_irqrestore(&master->lock, flags);
409}
410
411static void fsi_stream_pop(struct fsi_priv *fsi, int is_play)
412{
413 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
414 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
415 struct fsi_master *master = fsi_get_master(fsi);
416 unsigned long flags;
417
418 spin_lock_irqsave(&master->lock, flags);
419
420 if (io->oerr_num > 0)
421 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
422
423 if (io->uerr_num > 0)
424 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
425
426 io->substream = NULL;
427 io->buff_sample_capa = 0;
428 io->buff_sample_pos = 0;
429 io->period_samples = 0;
430 io->period_pos = 0;
431 io->oerr_num = 0;
432 io->uerr_num = 0;
433 spin_unlock_irqrestore(&master->lock, flags);
434}
435
436static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, int is_play)
437{
438 u32 status;
439 int frames;
440
441 status = is_play ?
442 fsi_reg_read(fsi, DOFF_ST) :
443 fsi_reg_read(fsi, DIFF_ST);
444
445 frames = 0x1ff & (status >> 8);
446
447 return fsi_frame2sample(fsi, frames);
448}
449
450static void fsi_count_fifo_err(struct fsi_priv *fsi)
451{
452 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
453 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
454
455 if (ostatus & ERR_OVER)
456 fsi->playback.oerr_num++;
457
458 if (ostatus & ERR_UNDER)
459 fsi->playback.uerr_num++;
460
461 if (istatus & ERR_OVER)
462 fsi->capture.oerr_num++;
463
464 if (istatus & ERR_UNDER)
465 fsi->capture.uerr_num++;
466
467 fsi_reg_write(fsi, DOFF_ST, 0);
468 fsi_reg_write(fsi, DIFF_ST, 0);
469}
470
471/*
472 * dma function
473 */
474
475static u8 *fsi_dma_get_area(struct fsi_priv *fsi, int stream)
476{
477 int is_play = fsi_stream_is_play(stream);
478 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
479 struct snd_pcm_runtime *runtime = io->substream->runtime;
480
481 return runtime->dma_area +
482 samples_to_bytes(runtime, io->buff_sample_pos);
483}
484
485static void fsi_dma_soft_push16(struct fsi_priv *fsi, int num)
486{
487 u16 *start;
488 int i;
489
490 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
491
492 for (i = 0; i < num; i++)
493 fsi_reg_write(fsi, DODT, ((u32)*(start + i) << 8));
494}
495
496static void fsi_dma_soft_pop16(struct fsi_priv *fsi, int num)
497{
498 u16 *start;
499 int i;
500
501 start = (u16 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
502
503
504 for (i = 0; i < num; i++)
505 *(start + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
506}
507
508static void fsi_dma_soft_push32(struct fsi_priv *fsi, int num)
509{
510 u32 *start;
511 int i;
512
513 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_PLAYBACK);
514
515
516 for (i = 0; i < num; i++)
517 fsi_reg_write(fsi, DODT, *(start + i));
518}
519
520static void fsi_dma_soft_pop32(struct fsi_priv *fsi, int num)
521{
522 u32 *start;
523 int i;
524
525 start = (u32 *)fsi_dma_get_area(fsi, SNDRV_PCM_STREAM_CAPTURE);
526
527 for (i = 0; i < num; i++)
528 *(start + i) = fsi_reg_read(fsi, DIDT);
529}
530
531/*
532 * irq function
533 */
534
535static void fsi_irq_enable(struct fsi_priv *fsi, int is_play)
536{
537 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
538 struct fsi_master *master = fsi_get_master(fsi);
539
540 fsi_core_mask_set(master, imsk, data, data);
541 fsi_core_mask_set(master, iemsk, data, data);
542}
543
544static void fsi_irq_disable(struct fsi_priv *fsi, int is_play)
545{
546 u32 data = AB_IO(1, fsi_get_port_shift(fsi, is_play));
547 struct fsi_master *master = fsi_get_master(fsi);
548
549 fsi_core_mask_set(master, imsk, data, 0);
550 fsi_core_mask_set(master, iemsk, data, 0);
551}
552
553static u32 fsi_irq_get_status(struct fsi_master *master)
554{
555 return fsi_core_read(master, int_st);
556}
557
558static void fsi_irq_clear_status(struct fsi_priv *fsi)
559{
560 u32 data = 0;
561 struct fsi_master *master = fsi_get_master(fsi);
562
563 data |= AB_IO(1, fsi_get_port_shift(fsi, 0));
564 data |= AB_IO(1, fsi_get_port_shift(fsi, 1));
565
566 /* clear interrupt factor */
567 fsi_core_mask_set(master, int_st, data, 0);
568}
569
570/*
571 * SPDIF master clock function
572 *
573 * These functions are used later FSI2
574 */
575static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
576{
577 struct fsi_master *master = fsi_get_master(fsi);
578 u32 mask, val;
579
580 if (master->core->ver < 2) {
581 pr_err("fsi: register access err (%s)\n", __func__);
582 return;
583 }
584
585 mask = BP | SE;
586 val = enable ? mask : 0;
587
588 fsi_is_port_a(fsi) ?
589 fsi_core_mask_set(master, a_mclk, mask, val) :
590 fsi_core_mask_set(master, b_mclk, mask, val);
591}
592
593/*
594 * clock function
595 */
596static int fsi_set_master_clk(struct device *dev, struct fsi_priv *fsi,
597 long rate, int enable)
598{
599 struct fsi_master *master = fsi_get_master(fsi);
600 set_rate_func set_rate = fsi_get_info_set_rate(master);
601 int fsi_ver = master->core->ver;
602 int ret;
603
604 ret = set_rate(dev, fsi_is_port_a(fsi), rate, enable);
605 if (ret < 0) /* error */
606 return ret;
607
608 if (!enable)
609 return 0;
610
611 if (ret > 0) {
612 u32 data = 0;
613
614 switch (ret & SH_FSI_ACKMD_MASK) {
615 default:
616 /* FALL THROUGH */
617 case SH_FSI_ACKMD_512:
618 data |= (0x0 << 12);
619 break;
620 case SH_FSI_ACKMD_256:
621 data |= (0x1 << 12);
622 break;
623 case SH_FSI_ACKMD_128:
624 data |= (0x2 << 12);
625 break;
626 case SH_FSI_ACKMD_64:
627 data |= (0x3 << 12);
628 break;
629 case SH_FSI_ACKMD_32:
630 if (fsi_ver < 2)
631 dev_err(dev, "unsupported ACKMD\n");
632 else
633 data |= (0x4 << 12);
634 break;
635 }
636
637 switch (ret & SH_FSI_BPFMD_MASK) {
638 default:
639 /* FALL THROUGH */
640 case SH_FSI_BPFMD_32:
641 data |= (0x0 << 8);
642 break;
643 case SH_FSI_BPFMD_64:
644 data |= (0x1 << 8);
645 break;
646 case SH_FSI_BPFMD_128:
647 data |= (0x2 << 8);
648 break;
649 case SH_FSI_BPFMD_256:
650 data |= (0x3 << 8);
651 break;
652 case SH_FSI_BPFMD_512:
653 data |= (0x4 << 8);
654 break;
655 case SH_FSI_BPFMD_16:
656 if (fsi_ver < 2)
657 dev_err(dev, "unsupported ACKMD\n");
658 else
659 data |= (0x7 << 8);
660 break;
661 }
662
663 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
664 udelay(10);
665 ret = 0;
666 }
667
668 return ret;
669}
670
671#define fsi_port_start(f, i) __fsi_port_clk_ctrl(f, i, 1)
672#define fsi_port_stop(f, i) __fsi_port_clk_ctrl(f, i, 0)
673static void __fsi_port_clk_ctrl(struct fsi_priv *fsi, int is_play, int enable)
674{
675 struct fsi_master *master = fsi_get_master(fsi);
676 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
677
678 if (enable)
679 fsi_irq_enable(fsi, is_play);
680 else
681 fsi_irq_disable(fsi, is_play);
682
683 if (fsi_is_clk_master(fsi))
684 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
685}
686
687/*
688 * ctrl function
689 */
690static void fsi_fifo_init(struct fsi_priv *fsi,
691 int is_play,
692 struct device *dev)
693{
694 struct fsi_master *master = fsi_get_master(fsi);
695 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
696 u32 shift, i;
697 int frame_capa;
698
699 /* get on-chip RAM capacity */
700 shift = fsi_master_read(master, FIFO_SZ);
701 shift >>= fsi_get_port_shift(fsi, is_play);
702 shift &= FIFO_SZ_MASK;
703 frame_capa = 256 << shift;
704 dev_dbg(dev, "fifo = %d words\n", frame_capa);
705
706 /*
707 * The maximum number of sample data varies depending
708 * on the number of channels selected for the format.
709 *
710 * FIFOs are used in 4-channel units in 3-channel mode
711 * and in 8-channel units in 5- to 7-channel mode
712 * meaning that more FIFOs than the required size of DPRAM
713 * are used.
714 *
715 * ex) if 256 words of DP-RAM is connected
716 * 1 channel: 256 (256 x 1 = 256)
717 * 2 channels: 128 (128 x 2 = 256)
718 * 3 channels: 64 ( 64 x 3 = 192)
719 * 4 channels: 64 ( 64 x 4 = 256)
720 * 5 channels: 32 ( 32 x 5 = 160)
721 * 6 channels: 32 ( 32 x 6 = 192)
722 * 7 channels: 32 ( 32 x 7 = 224)
723 * 8 channels: 32 ( 32 x 8 = 256)
724 */
725 for (i = 1; i < fsi->chan_num; i <<= 1)
726 frame_capa >>= 1;
727 dev_dbg(dev, "%d channel %d store\n",
728 fsi->chan_num, frame_capa);
729
730 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
731
732 /*
733 * set interrupt generation factor
734 * clear FIFO
735 */
736 if (is_play) {
737 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
738 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
739 } else {
740 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
741 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
742 }
743}
744
745static int fsi_fifo_data_ctrl(struct fsi_priv *fsi, int stream)
746{
747 struct snd_pcm_runtime *runtime;
748 struct snd_pcm_substream *substream = NULL;
749 int is_play = fsi_stream_is_play(stream);
750 struct fsi_stream *io = fsi_get_stream(fsi, is_play);
751 int sample_residues;
752 int sample_width;
753 int samples;
754 int samples_max;
755 int over_period;
756 void (*fn)(struct fsi_priv *fsi, int size);
757
758 if (!fsi ||
759 !io->substream ||
760 !io->substream->runtime)
761 return -EINVAL;
762
763 over_period = 0;
764 substream = io->substream;
765 runtime = substream->runtime;
766
767 /* FSI FIFO has limit.
768 * So, this driver can not send periods data at a time
769 */
770 if (io->buff_sample_pos >=
771 io->period_samples * (io->period_pos + 1)) {
772
773 over_period = 1;
774 io->period_pos = (io->period_pos + 1) % runtime->periods;
775
776 if (0 == io->period_pos)
777 io->buff_sample_pos = 0;
778 }
779
780 /* get 1 sample data width */
781 sample_width = samples_to_bytes(runtime, 1);
782
783 /* get number of residue samples */
784 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
785
786 if (is_play) {
787 /*
788 * for play-back
789 *
790 * samples_max : number of FSI fifo free samples space
791 * samples : number of ALSA residue samples
792 */
793 samples_max = io->fifo_sample_capa;
794 samples_max -= fsi_get_current_fifo_samples(fsi, is_play);
795
796 samples = sample_residues;
797
798 switch (sample_width) {
799 case 2:
800 fn = fsi_dma_soft_push16;
801 break;
802 case 4:
803 fn = fsi_dma_soft_push32;
804 break;
805 default:
806 return -EINVAL;
807 }
808 } else {
809 /*
810 * for capture
811 *
812 * samples_max : number of ALSA free samples space
813 * samples : number of samples in FSI fifo
814 */
815 samples_max = sample_residues;
816 samples = fsi_get_current_fifo_samples(fsi, is_play);
817
818 switch (sample_width) {
819 case 2:
820 fn = fsi_dma_soft_pop16;
821 break;
822 case 4:
823 fn = fsi_dma_soft_pop32;
824 break;
825 default:
826 return -EINVAL;
827 }
828 }
829
830 samples = min(samples, samples_max);
831
832 fn(fsi, samples);
833
834 /* update buff_sample_pos */
835 io->buff_sample_pos += samples;
836
837 if (over_period)
838 snd_pcm_period_elapsed(substream);
839
840 return 0;
841}
842
843static int fsi_data_pop(struct fsi_priv *fsi)
844{
845 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_CAPTURE);
846}
847
848static int fsi_data_push(struct fsi_priv *fsi)
849{
850 return fsi_fifo_data_ctrl(fsi, SNDRV_PCM_STREAM_PLAYBACK);
851}
852
853static irqreturn_t fsi_interrupt(int irq, void *data)
854{
855 struct fsi_master *master = data;
856 u32 int_st = fsi_irq_get_status(master);
857
858 /* clear irq status */
859 fsi_master_mask_set(master, SOFT_RST, IR, 0);
860 fsi_master_mask_set(master, SOFT_RST, IR, IR);
861
862 if (int_st & AB_IO(1, AO_SHIFT))
863 fsi_data_push(&master->fsia);
864 if (int_st & AB_IO(1, BO_SHIFT))
865 fsi_data_push(&master->fsib);
866 if (int_st & AB_IO(1, AI_SHIFT))
867 fsi_data_pop(&master->fsia);
868 if (int_st & AB_IO(1, BI_SHIFT))
869 fsi_data_pop(&master->fsib);
870
871 fsi_count_fifo_err(&master->fsia);
872 fsi_count_fifo_err(&master->fsib);
873
874 fsi_irq_clear_status(&master->fsia);
875 fsi_irq_clear_status(&master->fsib);
876
877 return IRQ_HANDLED;
878}
879
880/*
881 * dai ops
882 */
883
884static int fsi_hw_startup(struct fsi_priv *fsi,
885 int is_play,
886 struct device *dev)
887{
888 u32 flags = fsi_get_info_flags(fsi);
889 u32 data = 0;
890
891 pm_runtime_get_sync(dev);
892
893 /* clock setting */
894 if (fsi_is_clk_master(fsi))
895 data = DIMD | DOMD;
896
897 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
898
899 /* clock inversion (CKG2) */
900 data = 0;
901 if (SH_FSI_LRM_INV & flags)
902 data |= 1 << 12;
903 if (SH_FSI_BRM_INV & flags)
904 data |= 1 << 8;
905 if (SH_FSI_LRS_INV & flags)
906 data |= 1 << 4;
907 if (SH_FSI_BRS_INV & flags)
908 data |= 1 << 0;
909
910 fsi_reg_write(fsi, CKG2, data);
911
912 /* set format */
913 fsi_reg_write(fsi, DO_FMT, fsi->do_fmt);
914 fsi_reg_write(fsi, DI_FMT, fsi->di_fmt);
915
916 /* spdif ? */
917 if (fsi_is_spdif(fsi)) {
918 fsi_spdif_clk_ctrl(fsi, 1);
919 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
920 }
921
922 /* irq clear */
923 fsi_irq_disable(fsi, is_play);
924 fsi_irq_clear_status(fsi);
925
926 /* fifo init */
927 fsi_fifo_init(fsi, is_play, dev);
928
929 return 0;
930}
931
932static void fsi_hw_shutdown(struct fsi_priv *fsi,
933 int is_play,
934 struct device *dev)
935{
936 if (fsi_is_clk_master(fsi))
937 fsi_set_master_clk(dev, fsi, fsi->rate, 0);
938
939 pm_runtime_put_sync(dev);
940}
941
942static int fsi_dai_startup(struct snd_pcm_substream *substream,
943 struct snd_soc_dai *dai)
944{
945 struct fsi_priv *fsi = fsi_get_priv(substream);
946 int is_play = fsi_is_play(substream);
947
948 return fsi_hw_startup(fsi, is_play, dai->dev);
949}
950
951static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
952 struct snd_soc_dai *dai)
953{
954 struct fsi_priv *fsi = fsi_get_priv(substream);
955 int is_play = fsi_is_play(substream);
956
957 fsi_hw_shutdown(fsi, is_play, dai->dev);
958 fsi->rate = 0;
959}
960
961static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
962 struct snd_soc_dai *dai)
963{
964 struct fsi_priv *fsi = fsi_get_priv(substream);
965 int is_play = fsi_is_play(substream);
966 int ret = 0;
967
968 switch (cmd) {
969 case SNDRV_PCM_TRIGGER_START:
970 fsi_stream_push(fsi, is_play, substream);
971 ret = is_play ? fsi_data_push(fsi) : fsi_data_pop(fsi);
972 fsi_port_start(fsi, is_play);
973 break;
974 case SNDRV_PCM_TRIGGER_STOP:
975 fsi_port_stop(fsi, is_play);
976 fsi_stream_pop(fsi, is_play);
977 break;
978 }
979
980 return ret;
981}
982
983static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
984{
985 u32 data = 0;
986
987 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
988 case SND_SOC_DAIFMT_I2S:
989 data = CR_I2S;
990 fsi->chan_num = 2;
991 break;
992 case SND_SOC_DAIFMT_LEFT_J:
993 data = CR_PCM;
994 fsi->chan_num = 2;
995 break;
996 default:
997 return -EINVAL;
998 }
999
1000 fsi->do_fmt = data;
1001 fsi->di_fmt = data;
1002
1003 return 0;
1004}
1005
1006static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1007{
1008 struct fsi_master *master = fsi_get_master(fsi);
1009 u32 data = 0;
1010
1011 if (master->core->ver < 2)
1012 return -EINVAL;
1013
1014 data = CR_BWS_16 | CR_DTMD_SPDIF_PCM | CR_PCM;
1015 fsi->chan_num = 2;
1016 fsi->spdif = 1;
1017
1018 fsi->do_fmt = data;
1019 fsi->di_fmt = data;
1020
1021 return 0;
1022}
1023
1024static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1025{
1026 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1027 struct fsi_master *master = fsi_get_master(fsi);
1028 set_rate_func set_rate = fsi_get_info_set_rate(master);
1029 u32 flags = fsi_get_info_flags(fsi);
1030 int ret;
1031
1032 /* set master/slave audio interface */
1033 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1034 case SND_SOC_DAIFMT_CBM_CFM:
1035 fsi->clk_master = 1;
1036 break;
1037 case SND_SOC_DAIFMT_CBS_CFS:
1038 break;
1039 default:
1040 return -EINVAL;
1041 }
1042
1043 if (fsi_is_clk_master(fsi) && !set_rate) {
1044 dev_err(dai->dev, "platform doesn't have set_rate\n");
1045 return -EINVAL;
1046 }
1047
1048 /* set format */
1049 switch (flags & SH_FSI_FMT_MASK) {
1050 case SH_FSI_FMT_DAI:
1051 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1052 break;
1053 case SH_FSI_FMT_SPDIF:
1054 ret = fsi_set_fmt_spdif(fsi);
1055 break;
1056 default:
1057 ret = -EINVAL;
1058 }
1059
1060 return ret;
1061}
1062
1063static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1064 struct snd_pcm_hw_params *params,
1065 struct snd_soc_dai *dai)
1066{
1067 struct fsi_priv *fsi = fsi_get_priv(substream);
1068 long rate = params_rate(params);
1069 int ret;
1070
1071 if (!fsi_is_clk_master(fsi))
1072 return 0;
1073
1074 ret = fsi_set_master_clk(dai->dev, fsi, rate, 1);
1075 if (ret < 0)
1076 return ret;
1077
1078 fsi->rate = rate;
1079
1080 return ret;
1081}
1082
1083static struct snd_soc_dai_ops fsi_dai_ops = {
1084 .startup = fsi_dai_startup,
1085 .shutdown = fsi_dai_shutdown,
1086 .trigger = fsi_dai_trigger,
1087 .set_fmt = fsi_dai_set_fmt,
1088 .hw_params = fsi_dai_hw_params,
1089};
1090
1091/*
1092 * pcm ops
1093 */
1094
1095static struct snd_pcm_hardware fsi_pcm_hardware = {
1096 .info = SNDRV_PCM_INFO_INTERLEAVED |
1097 SNDRV_PCM_INFO_MMAP |
1098 SNDRV_PCM_INFO_MMAP_VALID |
1099 SNDRV_PCM_INFO_PAUSE,
1100 .formats = FSI_FMTS,
1101 .rates = FSI_RATES,
1102 .rate_min = 8000,
1103 .rate_max = 192000,
1104 .channels_min = 1,
1105 .channels_max = 2,
1106 .buffer_bytes_max = 64 * 1024,
1107 .period_bytes_min = 32,
1108 .period_bytes_max = 8192,
1109 .periods_min = 1,
1110 .periods_max = 32,
1111 .fifo_size = 256,
1112};
1113
1114static int fsi_pcm_open(struct snd_pcm_substream *substream)
1115{
1116 struct snd_pcm_runtime *runtime = substream->runtime;
1117 int ret = 0;
1118
1119 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1120
1121 ret = snd_pcm_hw_constraint_integer(runtime,
1122 SNDRV_PCM_HW_PARAM_PERIODS);
1123
1124 return ret;
1125}
1126
1127static int fsi_hw_params(struct snd_pcm_substream *substream,
1128 struct snd_pcm_hw_params *hw_params)
1129{
1130 return snd_pcm_lib_malloc_pages(substream,
1131 params_buffer_bytes(hw_params));
1132}
1133
1134static int fsi_hw_free(struct snd_pcm_substream *substream)
1135{
1136 return snd_pcm_lib_free_pages(substream);
1137}
1138
1139static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
1140{
1141 struct fsi_priv *fsi = fsi_get_priv(substream);
1142 struct fsi_stream *io = fsi_get_stream(fsi, fsi_is_play(substream));
1143 int samples_pos = io->buff_sample_pos - 1;
1144
1145 if (samples_pos < 0)
1146 samples_pos = 0;
1147
1148 return fsi_sample2frame(fsi, samples_pos);
1149}
1150
1151static struct snd_pcm_ops fsi_pcm_ops = {
1152 .open = fsi_pcm_open,
1153 .ioctl = snd_pcm_lib_ioctl,
1154 .hw_params = fsi_hw_params,
1155 .hw_free = fsi_hw_free,
1156 .pointer = fsi_pointer,
1157};
1158
1159/*
1160 * snd_soc_platform
1161 */
1162
1163#define PREALLOC_BUFFER (32 * 1024)
1164#define PREALLOC_BUFFER_MAX (32 * 1024)
1165
1166static void fsi_pcm_free(struct snd_pcm *pcm)
1167{
1168 snd_pcm_lib_preallocate_free_for_all(pcm);
1169}
1170
1171static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
1172{
1173 struct snd_pcm *pcm = rtd->pcm;
1174
1175 /*
1176 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
1177 * in MMAP mode (i.e. aplay -M)
1178 */
1179 return snd_pcm_lib_preallocate_pages_for_all(
1180 pcm,
1181 SNDRV_DMA_TYPE_CONTINUOUS,
1182 snd_dma_continuous_data(GFP_KERNEL),
1183 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1184}
1185
1186/*
1187 * alsa struct
1188 */
1189
1190static struct snd_soc_dai_driver fsi_soc_dai[] = {
1191 {
1192 .name = "fsia-dai",
1193 .playback = {
1194 .rates = FSI_RATES,
1195 .formats = FSI_FMTS,
1196 .channels_min = 1,
1197 .channels_max = 8,
1198 },
1199 .capture = {
1200 .rates = FSI_RATES,
1201 .formats = FSI_FMTS,
1202 .channels_min = 1,
1203 .channels_max = 8,
1204 },
1205 .ops = &fsi_dai_ops,
1206 },
1207 {
1208 .name = "fsib-dai",
1209 .playback = {
1210 .rates = FSI_RATES,
1211 .formats = FSI_FMTS,
1212 .channels_min = 1,
1213 .channels_max = 8,
1214 },
1215 .capture = {
1216 .rates = FSI_RATES,
1217 .formats = FSI_FMTS,
1218 .channels_min = 1,
1219 .channels_max = 8,
1220 },
1221 .ops = &fsi_dai_ops,
1222 },
1223};
1224
1225static struct snd_soc_platform_driver fsi_soc_platform = {
1226 .ops = &fsi_pcm_ops,
1227 .pcm_new = fsi_pcm_new,
1228 .pcm_free = fsi_pcm_free,
1229};
1230
1231/*
1232 * platform function
1233 */
1234
1235static int fsi_probe(struct platform_device *pdev)
1236{
1237 struct fsi_master *master;
1238 const struct platform_device_id *id_entry;
1239 struct resource *res;
1240 unsigned int irq;
1241 int ret;
1242
1243 id_entry = pdev->id_entry;
1244 if (!id_entry) {
1245 dev_err(&pdev->dev, "unknown fsi device\n");
1246 return -ENODEV;
1247 }
1248
1249 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1250 irq = platform_get_irq(pdev, 0);
1251 if (!res || (int)irq <= 0) {
1252 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1253 ret = -ENODEV;
1254 goto exit;
1255 }
1256
1257 master = kzalloc(sizeof(*master), GFP_KERNEL);
1258 if (!master) {
1259 dev_err(&pdev->dev, "Could not allocate master\n");
1260 ret = -ENOMEM;
1261 goto exit;
1262 }
1263
1264 master->base = ioremap_nocache(res->start, resource_size(res));
1265 if (!master->base) {
1266 ret = -ENXIO;
1267 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1268 goto exit_kfree;
1269 }
1270
1271 /* master setting */
1272 master->irq = irq;
1273 master->info = pdev->dev.platform_data;
1274 master->core = (struct fsi_core *)id_entry->driver_data;
1275 spin_lock_init(&master->lock);
1276
1277 /* FSI A setting */
1278 master->fsia.base = master->base;
1279 master->fsia.master = master;
1280
1281 /* FSI B setting */
1282 master->fsib.base = master->base + 0x40;
1283 master->fsib.master = master;
1284
1285 pm_runtime_enable(&pdev->dev);
1286 dev_set_drvdata(&pdev->dev, master);
1287
1288 ret = request_irq(irq, &fsi_interrupt, IRQF_DISABLED,
1289 id_entry->name, master);
1290 if (ret) {
1291 dev_err(&pdev->dev, "irq request err\n");
1292 goto exit_iounmap;
1293 }
1294
1295 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
1296 if (ret < 0) {
1297 dev_err(&pdev->dev, "cannot snd soc register\n");
1298 goto exit_free_irq;
1299 }
1300
1301 ret = snd_soc_register_dais(&pdev->dev, fsi_soc_dai,
1302 ARRAY_SIZE(fsi_soc_dai));
1303 if (ret < 0) {
1304 dev_err(&pdev->dev, "cannot snd dai register\n");
1305 goto exit_snd_soc;
1306 }
1307
1308 return ret;
1309
1310exit_snd_soc:
1311 snd_soc_unregister_platform(&pdev->dev);
1312exit_free_irq:
1313 free_irq(irq, master);
1314exit_iounmap:
1315 iounmap(master->base);
1316 pm_runtime_disable(&pdev->dev);
1317exit_kfree:
1318 kfree(master);
1319 master = NULL;
1320exit:
1321 return ret;
1322}
1323
1324static int fsi_remove(struct platform_device *pdev)
1325{
1326 struct fsi_master *master;
1327
1328 master = dev_get_drvdata(&pdev->dev);
1329
1330 free_irq(master->irq, master);
1331 pm_runtime_disable(&pdev->dev);
1332
1333 snd_soc_unregister_dais(&pdev->dev, ARRAY_SIZE(fsi_soc_dai));
1334 snd_soc_unregister_platform(&pdev->dev);
1335
1336 iounmap(master->base);
1337 kfree(master);
1338
1339 return 0;
1340}
1341
1342static void __fsi_suspend(struct fsi_priv *fsi,
1343 int is_play,
1344 struct device *dev)
1345{
1346 if (!fsi_stream_is_working(fsi, is_play))
1347 return;
1348
1349 fsi_port_stop(fsi, is_play);
1350 fsi_hw_shutdown(fsi, is_play, dev);
1351}
1352
1353static void __fsi_resume(struct fsi_priv *fsi,
1354 int is_play,
1355 struct device *dev)
1356{
1357 if (!fsi_stream_is_working(fsi, is_play))
1358 return;
1359
1360 fsi_hw_startup(fsi, is_play, dev);
1361
1362 if (fsi_is_clk_master(fsi) && fsi->rate)
1363 fsi_set_master_clk(dev, fsi, fsi->rate, 1);
1364
1365 fsi_port_start(fsi, is_play);
1366
1367}
1368
1369static int fsi_suspend(struct device *dev)
1370{
1371 struct fsi_master *master = dev_get_drvdata(dev);
1372 struct fsi_priv *fsia = &master->fsia;
1373 struct fsi_priv *fsib = &master->fsib;
1374
1375 __fsi_suspend(fsia, 1, dev);
1376 __fsi_suspend(fsia, 0, dev);
1377
1378 __fsi_suspend(fsib, 1, dev);
1379 __fsi_suspend(fsib, 0, dev);
1380
1381 return 0;
1382}
1383
1384static int fsi_resume(struct device *dev)
1385{
1386 struct fsi_master *master = dev_get_drvdata(dev);
1387 struct fsi_priv *fsia = &master->fsia;
1388 struct fsi_priv *fsib = &master->fsib;
1389
1390 __fsi_resume(fsia, 1, dev);
1391 __fsi_resume(fsia, 0, dev);
1392
1393 __fsi_resume(fsib, 1, dev);
1394 __fsi_resume(fsib, 0, dev);
1395
1396 return 0;
1397}
1398
1399static int fsi_runtime_nop(struct device *dev)
1400{
1401 /* Runtime PM callback shared between ->runtime_suspend()
1402 * and ->runtime_resume(). Simply returns success.
1403 *
1404 * This driver re-initializes all registers after
1405 * pm_runtime_get_sync() anyway so there is no need
1406 * to save and restore registers here.
1407 */
1408 return 0;
1409}
1410
1411static struct dev_pm_ops fsi_pm_ops = {
1412 .suspend = fsi_suspend,
1413 .resume = fsi_resume,
1414 .runtime_suspend = fsi_runtime_nop,
1415 .runtime_resume = fsi_runtime_nop,
1416};
1417
1418static struct fsi_core fsi1_core = {
1419 .ver = 1,
1420
1421 /* Interrupt */
1422 .int_st = INT_ST,
1423 .iemsk = IEMSK,
1424 .imsk = IMSK,
1425};
1426
1427static struct fsi_core fsi2_core = {
1428 .ver = 2,
1429
1430 /* Interrupt */
1431 .int_st = CPU_INT_ST,
1432 .iemsk = CPU_IEMSK,
1433 .imsk = CPU_IMSK,
1434 .a_mclk = A_MST_CTLR,
1435 .b_mclk = B_MST_CTLR,
1436};
1437
1438static struct platform_device_id fsi_id_table[] = {
1439 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1440 { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
1441 {},
1442};
1443MODULE_DEVICE_TABLE(platform, fsi_id_table);
1444
1445static struct platform_driver fsi_driver = {
1446 .driver = {
1447 .name = "fsi-pcm-audio",
1448 .pm = &fsi_pm_ops,
1449 },
1450 .probe = fsi_probe,
1451 .remove = fsi_remove,
1452 .id_table = fsi_id_table,
1453};
1454
1455static int __init fsi_mobile_init(void)
1456{
1457 return platform_driver_register(&fsi_driver);
1458}
1459
1460static void __exit fsi_mobile_exit(void)
1461{
1462 platform_driver_unregister(&fsi_driver);
1463}
1464
1465module_init(fsi_mobile_init);
1466module_exit(fsi_mobile_exit);
1467
1468MODULE_LICENSE("GPL");
1469MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
1470MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
1471MODULE_ALIAS("platform:fsi-pcm-audio");
1// SPDX-License-Identifier: GPL-2.0
2//
3// Fifo-attached Serial Interface (FSI) support for SH7724
4//
5// Copyright (C) 2009 Renesas Solutions Corp.
6// Kuninori Morimoto <morimoto.kuninori@renesas.com>
7//
8// Based on ssi.c
9// Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
10
11#include <linux/delay.h>
12#include <linux/dma-mapping.h>
13#include <linux/pm_runtime.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/scatterlist.h>
18#include <linux/sh_dma.h>
19#include <linux/slab.h>
20#include <linux/module.h>
21#include <linux/workqueue.h>
22#include <sound/soc.h>
23#include <sound/pcm_params.h>
24#include <sound/sh_fsi.h>
25
26/* PortA/PortB register */
27#define REG_DO_FMT 0x0000
28#define REG_DOFF_CTL 0x0004
29#define REG_DOFF_ST 0x0008
30#define REG_DI_FMT 0x000C
31#define REG_DIFF_CTL 0x0010
32#define REG_DIFF_ST 0x0014
33#define REG_CKG1 0x0018
34#define REG_CKG2 0x001C
35#define REG_DIDT 0x0020
36#define REG_DODT 0x0024
37#define REG_MUTE_ST 0x0028
38#define REG_OUT_DMAC 0x002C
39#define REG_OUT_SEL 0x0030
40#define REG_IN_DMAC 0x0038
41
42/* master register */
43#define MST_CLK_RST 0x0210
44#define MST_SOFT_RST 0x0214
45#define MST_FIFO_SZ 0x0218
46
47/* core register (depend on FSI version) */
48#define A_MST_CTLR 0x0180
49#define B_MST_CTLR 0x01A0
50#define CPU_INT_ST 0x01F4
51#define CPU_IEMSK 0x01F8
52#define CPU_IMSK 0x01FC
53#define INT_ST 0x0200
54#define IEMSK 0x0204
55#define IMSK 0x0208
56
57/* DO_FMT */
58/* DI_FMT */
59#define CR_BWS_MASK (0x3 << 20) /* FSI2 */
60#define CR_BWS_24 (0x0 << 20) /* FSI2 */
61#define CR_BWS_16 (0x1 << 20) /* FSI2 */
62#define CR_BWS_20 (0x2 << 20) /* FSI2 */
63
64#define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
65#define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
66#define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
67
68#define CR_MONO (0x0 << 4)
69#define CR_MONO_D (0x1 << 4)
70#define CR_PCM (0x2 << 4)
71#define CR_I2S (0x3 << 4)
72#define CR_TDM (0x4 << 4)
73#define CR_TDM_D (0x5 << 4)
74
75/* OUT_DMAC */
76/* IN_DMAC */
77#define VDMD_MASK (0x3 << 4)
78#define VDMD_FRONT (0x0 << 4) /* Package in front */
79#define VDMD_BACK (0x1 << 4) /* Package in back */
80#define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
81
82#define DMA_ON (0x1 << 0)
83
84/* DOFF_CTL */
85/* DIFF_CTL */
86#define IRQ_HALF 0x00100000
87#define FIFO_CLR 0x00000001
88
89/* DOFF_ST */
90#define ERR_OVER 0x00000010
91#define ERR_UNDER 0x00000001
92#define ST_ERR (ERR_OVER | ERR_UNDER)
93
94/* CKG1 */
95#define ACKMD_MASK 0x00007000
96#define BPFMD_MASK 0x00000700
97#define DIMD (1 << 4)
98#define DOMD (1 << 0)
99
100/* A/B MST_CTLR */
101#define BP (1 << 4) /* Fix the signal of Biphase output */
102#define SE (1 << 0) /* Fix the master clock */
103
104/* CLK_RST */
105#define CRB (1 << 4)
106#define CRA (1 << 0)
107
108/* IO SHIFT / MACRO */
109#define BI_SHIFT 12
110#define BO_SHIFT 8
111#define AI_SHIFT 4
112#define AO_SHIFT 0
113#define AB_IO(param, shift) (param << shift)
114
115/* SOFT_RST */
116#define PBSR (1 << 12) /* Port B Software Reset */
117#define PASR (1 << 8) /* Port A Software Reset */
118#define IR (1 << 4) /* Interrupt Reset */
119#define FSISR (1 << 0) /* Software Reset */
120
121/* OUT_SEL (FSI2) */
122#define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
123 /* 1: Biphase and serial */
124
125/* FIFO_SZ */
126#define FIFO_SZ_MASK 0x7
127
128#define FSI_RATES SNDRV_PCM_RATE_8000_96000
129
130#define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
131
132/*
133 * bus options
134 *
135 * 0x000000BA
136 *
137 * A : sample widtht 16bit setting
138 * B : sample widtht 24bit setting
139 */
140
141#define SHIFT_16DATA 0
142#define SHIFT_24DATA 4
143
144#define PACKAGE_24BITBUS_BACK 0
145#define PACKAGE_24BITBUS_FRONT 1
146#define PACKAGE_16BITBUS_STREAM 2
147
148#define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
149#define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
150
151/*
152 * FSI driver use below type name for variable
153 *
154 * xxx_num : number of data
155 * xxx_pos : position of data
156 * xxx_capa : capacity of data
157 */
158
159/*
160 * period/frame/sample image
161 *
162 * ex) PCM (2ch)
163 *
164 * period pos period pos
165 * [n] [n + 1]
166 * |<-------------------- period--------------------->|
167 * ==|============================================ ... =|==
168 * | |
169 * ||<----- frame ----->|<------ frame ----->| ... |
170 * |+--------------------+--------------------+- ... |
171 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
172 * |+--------------------+--------------------+- ... |
173 * ==|============================================ ... =|==
174 */
175
176/*
177 * FSI FIFO image
178 *
179 * | |
180 * | |
181 * | [ sample ] |
182 * | [ sample ] |
183 * | [ sample ] |
184 * | [ sample ] |
185 * --> go to codecs
186 */
187
188/*
189 * FSI clock
190 *
191 * FSIxCLK [CPG] (ick) -------> |
192 * |-> FSI_DIV (div)-> FSI2
193 * FSIxCK [external] (xck) ---> |
194 */
195
196/*
197 * struct
198 */
199
200struct fsi_stream_handler;
201struct fsi_stream {
202
203 /*
204 * these are initialized by fsi_stream_init()
205 */
206 struct snd_pcm_substream *substream;
207 int fifo_sample_capa; /* sample capacity of FSI FIFO */
208 int buff_sample_capa; /* sample capacity of ALSA buffer */
209 int buff_sample_pos; /* sample position of ALSA buffer */
210 int period_samples; /* sample number / 1 period */
211 int period_pos; /* current period position */
212 int sample_width; /* sample width */
213 int uerr_num;
214 int oerr_num;
215
216 /*
217 * bus options
218 */
219 u32 bus_option;
220
221 /*
222 * these are initialized by fsi_handler_init()
223 */
224 struct fsi_stream_handler *handler;
225 struct fsi_priv *priv;
226
227 /*
228 * these are for DMAEngine
229 */
230 struct dma_chan *chan;
231 int dma_id;
232};
233
234struct fsi_clk {
235 /* see [FSI clock] */
236 struct clk *own;
237 struct clk *xck;
238 struct clk *ick;
239 struct clk *div;
240 int (*set_rate)(struct device *dev,
241 struct fsi_priv *fsi);
242
243 unsigned long rate;
244 unsigned int count;
245};
246
247struct fsi_priv {
248 void __iomem *base;
249 phys_addr_t phys;
250 struct fsi_master *master;
251
252 struct fsi_stream playback;
253 struct fsi_stream capture;
254
255 struct fsi_clk clock;
256
257 u32 fmt;
258
259 int chan_num:16;
260 unsigned int clk_master:1;
261 unsigned int clk_cpg:1;
262 unsigned int spdif:1;
263 unsigned int enable_stream:1;
264 unsigned int bit_clk_inv:1;
265 unsigned int lr_clk_inv:1;
266};
267
268struct fsi_stream_handler {
269 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
270 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
271 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
272 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
273 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
274 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
275 int enable);
276};
277#define fsi_stream_handler_call(io, func, args...) \
278 (!(io) ? -ENODEV : \
279 !((io)->handler->func) ? 0 : \
280 (io)->handler->func(args))
281
282struct fsi_core {
283 int ver;
284
285 u32 int_st;
286 u32 iemsk;
287 u32 imsk;
288 u32 a_mclk;
289 u32 b_mclk;
290};
291
292struct fsi_master {
293 void __iomem *base;
294 struct fsi_priv fsia;
295 struct fsi_priv fsib;
296 const struct fsi_core *core;
297 spinlock_t lock;
298};
299
300static inline int fsi_stream_is_play(struct fsi_priv *fsi,
301 struct fsi_stream *io)
302{
303 return &fsi->playback == io;
304}
305
306
307/*
308 * basic read write function
309 */
310
311static void __fsi_reg_write(u32 __iomem *reg, u32 data)
312{
313 /* valid data area is 24bit */
314 data &= 0x00ffffff;
315
316 __raw_writel(data, reg);
317}
318
319static u32 __fsi_reg_read(u32 __iomem *reg)
320{
321 return __raw_readl(reg);
322}
323
324static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
325{
326 u32 val = __fsi_reg_read(reg);
327
328 val &= ~mask;
329 val |= data & mask;
330
331 __fsi_reg_write(reg, val);
332}
333
334#define fsi_reg_write(p, r, d)\
335 __fsi_reg_write((p->base + REG_##r), d)
336
337#define fsi_reg_read(p, r)\
338 __fsi_reg_read((p->base + REG_##r))
339
340#define fsi_reg_mask_set(p, r, m, d)\
341 __fsi_reg_mask_set((p->base + REG_##r), m, d)
342
343#define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
344#define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
345static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
346{
347 u32 ret;
348 unsigned long flags;
349
350 spin_lock_irqsave(&master->lock, flags);
351 ret = __fsi_reg_read(master->base + reg);
352 spin_unlock_irqrestore(&master->lock, flags);
353
354 return ret;
355}
356
357#define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
358#define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
359static void _fsi_master_mask_set(struct fsi_master *master,
360 u32 reg, u32 mask, u32 data)
361{
362 unsigned long flags;
363
364 spin_lock_irqsave(&master->lock, flags);
365 __fsi_reg_mask_set(master->base + reg, mask, data);
366 spin_unlock_irqrestore(&master->lock, flags);
367}
368
369/*
370 * basic function
371 */
372static int fsi_version(struct fsi_master *master)
373{
374 return master->core->ver;
375}
376
377static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
378{
379 return fsi->master;
380}
381
382static int fsi_is_clk_master(struct fsi_priv *fsi)
383{
384 return fsi->clk_master;
385}
386
387static int fsi_is_port_a(struct fsi_priv *fsi)
388{
389 return fsi->master->base == fsi->base;
390}
391
392static int fsi_is_spdif(struct fsi_priv *fsi)
393{
394 return fsi->spdif;
395}
396
397static int fsi_is_enable_stream(struct fsi_priv *fsi)
398{
399 return fsi->enable_stream;
400}
401
402static int fsi_is_play(struct snd_pcm_substream *substream)
403{
404 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
405}
406
407static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
408{
409 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
410
411 return asoc_rtd_to_cpu(rtd, 0);
412}
413
414static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
415{
416 struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
417
418 if (dai->id == 0)
419 return &master->fsia;
420 else
421 return &master->fsib;
422}
423
424static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
425{
426 return fsi_get_priv_frm_dai(fsi_get_dai(substream));
427}
428
429static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
430{
431 int is_play = fsi_stream_is_play(fsi, io);
432 int is_porta = fsi_is_port_a(fsi);
433 u32 shift;
434
435 if (is_porta)
436 shift = is_play ? AO_SHIFT : AI_SHIFT;
437 else
438 shift = is_play ? BO_SHIFT : BI_SHIFT;
439
440 return shift;
441}
442
443static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
444{
445 return frames * fsi->chan_num;
446}
447
448static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
449{
450 return samples / fsi->chan_num;
451}
452
453static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
454 struct fsi_stream *io)
455{
456 int is_play = fsi_stream_is_play(fsi, io);
457 u32 status;
458 int frames;
459
460 status = is_play ?
461 fsi_reg_read(fsi, DOFF_ST) :
462 fsi_reg_read(fsi, DIFF_ST);
463
464 frames = 0x1ff & (status >> 8);
465
466 return fsi_frame2sample(fsi, frames);
467}
468
469static void fsi_count_fifo_err(struct fsi_priv *fsi)
470{
471 u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
472 u32 istatus = fsi_reg_read(fsi, DIFF_ST);
473
474 if (ostatus & ERR_OVER)
475 fsi->playback.oerr_num++;
476
477 if (ostatus & ERR_UNDER)
478 fsi->playback.uerr_num++;
479
480 if (istatus & ERR_OVER)
481 fsi->capture.oerr_num++;
482
483 if (istatus & ERR_UNDER)
484 fsi->capture.uerr_num++;
485
486 fsi_reg_write(fsi, DOFF_ST, 0);
487 fsi_reg_write(fsi, DIFF_ST, 0);
488}
489
490/*
491 * fsi_stream_xx() function
492 */
493static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
494 struct snd_pcm_substream *substream)
495{
496 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
497}
498
499static int fsi_stream_is_working(struct fsi_priv *fsi,
500 struct fsi_stream *io)
501{
502 struct fsi_master *master = fsi_get_master(fsi);
503 unsigned long flags;
504 int ret;
505
506 spin_lock_irqsave(&master->lock, flags);
507 ret = !!(io->substream && io->substream->runtime);
508 spin_unlock_irqrestore(&master->lock, flags);
509
510 return ret;
511}
512
513static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
514{
515 return io->priv;
516}
517
518static void fsi_stream_init(struct fsi_priv *fsi,
519 struct fsi_stream *io,
520 struct snd_pcm_substream *substream)
521{
522 struct snd_pcm_runtime *runtime = substream->runtime;
523 struct fsi_master *master = fsi_get_master(fsi);
524 unsigned long flags;
525
526 spin_lock_irqsave(&master->lock, flags);
527 io->substream = substream;
528 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
529 io->buff_sample_pos = 0;
530 io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
531 io->period_pos = 0;
532 io->sample_width = samples_to_bytes(runtime, 1);
533 io->bus_option = 0;
534 io->oerr_num = -1; /* ignore 1st err */
535 io->uerr_num = -1; /* ignore 1st err */
536 fsi_stream_handler_call(io, init, fsi, io);
537 spin_unlock_irqrestore(&master->lock, flags);
538}
539
540static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
541{
542 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
543 struct fsi_master *master = fsi_get_master(fsi);
544 unsigned long flags;
545
546 spin_lock_irqsave(&master->lock, flags);
547
548 if (io->oerr_num > 0)
549 dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
550
551 if (io->uerr_num > 0)
552 dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
553
554 fsi_stream_handler_call(io, quit, fsi, io);
555 io->substream = NULL;
556 io->buff_sample_capa = 0;
557 io->buff_sample_pos = 0;
558 io->period_samples = 0;
559 io->period_pos = 0;
560 io->sample_width = 0;
561 io->bus_option = 0;
562 io->oerr_num = 0;
563 io->uerr_num = 0;
564 spin_unlock_irqrestore(&master->lock, flags);
565}
566
567static int fsi_stream_transfer(struct fsi_stream *io)
568{
569 struct fsi_priv *fsi = fsi_stream_to_priv(io);
570 if (!fsi)
571 return -EIO;
572
573 return fsi_stream_handler_call(io, transfer, fsi, io);
574}
575
576#define fsi_stream_start(fsi, io)\
577 fsi_stream_handler_call(io, start_stop, fsi, io, 1)
578
579#define fsi_stream_stop(fsi, io)\
580 fsi_stream_handler_call(io, start_stop, fsi, io, 0)
581
582static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
583{
584 struct fsi_stream *io;
585 int ret1, ret2;
586
587 io = &fsi->playback;
588 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
589
590 io = &fsi->capture;
591 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
592
593 if (ret1 < 0)
594 return ret1;
595 if (ret2 < 0)
596 return ret2;
597
598 return 0;
599}
600
601static int fsi_stream_remove(struct fsi_priv *fsi)
602{
603 struct fsi_stream *io;
604 int ret1, ret2;
605
606 io = &fsi->playback;
607 ret1 = fsi_stream_handler_call(io, remove, fsi, io);
608
609 io = &fsi->capture;
610 ret2 = fsi_stream_handler_call(io, remove, fsi, io);
611
612 if (ret1 < 0)
613 return ret1;
614 if (ret2 < 0)
615 return ret2;
616
617 return 0;
618}
619
620/*
621 * format/bus/dma setting
622 */
623static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
624 u32 bus, struct device *dev)
625{
626 struct fsi_master *master = fsi_get_master(fsi);
627 int is_play = fsi_stream_is_play(fsi, io);
628 u32 fmt = fsi->fmt;
629
630 if (fsi_version(master) >= 2) {
631 u32 dma = 0;
632
633 /*
634 * FSI2 needs DMA/Bus setting
635 */
636 switch (bus) {
637 case PACKAGE_24BITBUS_FRONT:
638 fmt |= CR_BWS_24;
639 dma |= VDMD_FRONT;
640 dev_dbg(dev, "24bit bus / package in front\n");
641 break;
642 case PACKAGE_16BITBUS_STREAM:
643 fmt |= CR_BWS_16;
644 dma |= VDMD_STREAM;
645 dev_dbg(dev, "16bit bus / stream mode\n");
646 break;
647 case PACKAGE_24BITBUS_BACK:
648 default:
649 fmt |= CR_BWS_24;
650 dma |= VDMD_BACK;
651 dev_dbg(dev, "24bit bus / package in back\n");
652 break;
653 }
654
655 if (is_play)
656 fsi_reg_write(fsi, OUT_DMAC, dma);
657 else
658 fsi_reg_write(fsi, IN_DMAC, dma);
659 }
660
661 if (is_play)
662 fsi_reg_write(fsi, DO_FMT, fmt);
663 else
664 fsi_reg_write(fsi, DI_FMT, fmt);
665}
666
667/*
668 * irq function
669 */
670
671static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
672{
673 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
674 struct fsi_master *master = fsi_get_master(fsi);
675
676 fsi_core_mask_set(master, imsk, data, data);
677 fsi_core_mask_set(master, iemsk, data, data);
678}
679
680static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
681{
682 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
683 struct fsi_master *master = fsi_get_master(fsi);
684
685 fsi_core_mask_set(master, imsk, data, 0);
686 fsi_core_mask_set(master, iemsk, data, 0);
687}
688
689static u32 fsi_irq_get_status(struct fsi_master *master)
690{
691 return fsi_core_read(master, int_st);
692}
693
694static void fsi_irq_clear_status(struct fsi_priv *fsi)
695{
696 u32 data = 0;
697 struct fsi_master *master = fsi_get_master(fsi);
698
699 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
700 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
701
702 /* clear interrupt factor */
703 fsi_core_mask_set(master, int_st, data, 0);
704}
705
706/*
707 * SPDIF master clock function
708 *
709 * These functions are used later FSI2
710 */
711static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
712{
713 struct fsi_master *master = fsi_get_master(fsi);
714 u32 mask, val;
715
716 mask = BP | SE;
717 val = enable ? mask : 0;
718
719 fsi_is_port_a(fsi) ?
720 fsi_core_mask_set(master, a_mclk, mask, val) :
721 fsi_core_mask_set(master, b_mclk, mask, val);
722}
723
724/*
725 * clock function
726 */
727static int fsi_clk_init(struct device *dev,
728 struct fsi_priv *fsi,
729 int xck,
730 int ick,
731 int div,
732 int (*set_rate)(struct device *dev,
733 struct fsi_priv *fsi))
734{
735 struct fsi_clk *clock = &fsi->clock;
736 int is_porta = fsi_is_port_a(fsi);
737
738 clock->xck = NULL;
739 clock->ick = NULL;
740 clock->div = NULL;
741 clock->rate = 0;
742 clock->count = 0;
743 clock->set_rate = set_rate;
744
745 clock->own = devm_clk_get(dev, NULL);
746 if (IS_ERR(clock->own))
747 return -EINVAL;
748
749 /* external clock */
750 if (xck) {
751 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
752 if (IS_ERR(clock->xck)) {
753 dev_err(dev, "can't get xck clock\n");
754 return -EINVAL;
755 }
756 if (clock->xck == clock->own) {
757 dev_err(dev, "cpu doesn't support xck clock\n");
758 return -EINVAL;
759 }
760 }
761
762 /* FSIACLK/FSIBCLK */
763 if (ick) {
764 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
765 if (IS_ERR(clock->ick)) {
766 dev_err(dev, "can't get ick clock\n");
767 return -EINVAL;
768 }
769 if (clock->ick == clock->own) {
770 dev_err(dev, "cpu doesn't support ick clock\n");
771 return -EINVAL;
772 }
773 }
774
775 /* FSI-DIV */
776 if (div) {
777 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
778 if (IS_ERR(clock->div)) {
779 dev_err(dev, "can't get div clock\n");
780 return -EINVAL;
781 }
782 if (clock->div == clock->own) {
783 dev_err(dev, "cpu doesn't support div clock\n");
784 return -EINVAL;
785 }
786 }
787
788 return 0;
789}
790
791#define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
792static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
793{
794 fsi->clock.rate = rate;
795}
796
797static int fsi_clk_is_valid(struct fsi_priv *fsi)
798{
799 return fsi->clock.set_rate &&
800 fsi->clock.rate;
801}
802
803static int fsi_clk_enable(struct device *dev,
804 struct fsi_priv *fsi)
805{
806 struct fsi_clk *clock = &fsi->clock;
807 int ret = -EINVAL;
808
809 if (!fsi_clk_is_valid(fsi))
810 return ret;
811
812 if (0 == clock->count) {
813 ret = clock->set_rate(dev, fsi);
814 if (ret < 0) {
815 fsi_clk_invalid(fsi);
816 return ret;
817 }
818
819 ret = clk_enable(clock->xck);
820 if (ret)
821 goto err;
822 ret = clk_enable(clock->ick);
823 if (ret)
824 goto disable_xck;
825 ret = clk_enable(clock->div);
826 if (ret)
827 goto disable_ick;
828
829 clock->count++;
830 }
831
832 return ret;
833
834disable_ick:
835 clk_disable(clock->ick);
836disable_xck:
837 clk_disable(clock->xck);
838err:
839 return ret;
840}
841
842static int fsi_clk_disable(struct device *dev,
843 struct fsi_priv *fsi)
844{
845 struct fsi_clk *clock = &fsi->clock;
846
847 if (!fsi_clk_is_valid(fsi))
848 return -EINVAL;
849
850 if (1 == clock->count--) {
851 clk_disable(clock->xck);
852 clk_disable(clock->ick);
853 clk_disable(clock->div);
854 }
855
856 return 0;
857}
858
859static int fsi_clk_set_ackbpf(struct device *dev,
860 struct fsi_priv *fsi,
861 int ackmd, int bpfmd)
862{
863 u32 data = 0;
864
865 /* check ackmd/bpfmd relationship */
866 if (bpfmd > ackmd) {
867 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
868 return -EINVAL;
869 }
870
871 /* ACKMD */
872 switch (ackmd) {
873 case 512:
874 data |= (0x0 << 12);
875 break;
876 case 256:
877 data |= (0x1 << 12);
878 break;
879 case 128:
880 data |= (0x2 << 12);
881 break;
882 case 64:
883 data |= (0x3 << 12);
884 break;
885 case 32:
886 data |= (0x4 << 12);
887 break;
888 default:
889 dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
890 return -EINVAL;
891 }
892
893 /* BPFMD */
894 switch (bpfmd) {
895 case 32:
896 data |= (0x0 << 8);
897 break;
898 case 64:
899 data |= (0x1 << 8);
900 break;
901 case 128:
902 data |= (0x2 << 8);
903 break;
904 case 256:
905 data |= (0x3 << 8);
906 break;
907 case 512:
908 data |= (0x4 << 8);
909 break;
910 case 16:
911 data |= (0x7 << 8);
912 break;
913 default:
914 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
915 return -EINVAL;
916 }
917
918 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
919
920 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
921 udelay(10);
922
923 return 0;
924}
925
926static int fsi_clk_set_rate_external(struct device *dev,
927 struct fsi_priv *fsi)
928{
929 struct clk *xck = fsi->clock.xck;
930 struct clk *ick = fsi->clock.ick;
931 unsigned long rate = fsi->clock.rate;
932 unsigned long xrate;
933 int ackmd, bpfmd;
934 int ret = 0;
935
936 /* check clock rate */
937 xrate = clk_get_rate(xck);
938 if (xrate % rate) {
939 dev_err(dev, "unsupported clock rate\n");
940 return -EINVAL;
941 }
942
943 clk_set_parent(ick, xck);
944 clk_set_rate(ick, xrate);
945
946 bpfmd = fsi->chan_num * 32;
947 ackmd = xrate / rate;
948
949 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
950
951 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
952 if (ret < 0)
953 dev_err(dev, "%s failed", __func__);
954
955 return ret;
956}
957
958static int fsi_clk_set_rate_cpg(struct device *dev,
959 struct fsi_priv *fsi)
960{
961 struct clk *ick = fsi->clock.ick;
962 struct clk *div = fsi->clock.div;
963 unsigned long rate = fsi->clock.rate;
964 unsigned long target = 0; /* 12288000 or 11289600 */
965 unsigned long actual, cout;
966 unsigned long diff, min;
967 unsigned long best_cout, best_act;
968 int adj;
969 int ackmd, bpfmd;
970 int ret = -EINVAL;
971
972 if (!(12288000 % rate))
973 target = 12288000;
974 if (!(11289600 % rate))
975 target = 11289600;
976 if (!target) {
977 dev_err(dev, "unsupported rate\n");
978 return ret;
979 }
980
981 bpfmd = fsi->chan_num * 32;
982 ackmd = target / rate;
983 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
984 if (ret < 0) {
985 dev_err(dev, "%s failed", __func__);
986 return ret;
987 }
988
989 /*
990 * The clock flow is
991 *
992 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
993 *
994 * But, it needs to find best match of CPG and FSI_DIV
995 * combination, since it is difficult to generate correct
996 * frequency of audio clock from ick clock only.
997 * Because ick is created from its parent clock.
998 *
999 * target = rate x [512/256/128/64]fs
1000 * cout = round(target x adjustment)
1001 * actual = cout / adjustment (by FSI-DIV) ~= target
1002 * audio = actual
1003 */
1004 min = ~0;
1005 best_cout = 0;
1006 best_act = 0;
1007 for (adj = 1; adj < 0xffff; adj++) {
1008
1009 cout = target * adj;
1010 if (cout > 100000000) /* max clock = 100MHz */
1011 break;
1012
1013 /* cout/actual audio clock */
1014 cout = clk_round_rate(ick, cout);
1015 actual = cout / adj;
1016
1017 /* find best frequency */
1018 diff = abs(actual - target);
1019 if (diff < min) {
1020 min = diff;
1021 best_cout = cout;
1022 best_act = actual;
1023 }
1024 }
1025
1026 ret = clk_set_rate(ick, best_cout);
1027 if (ret < 0) {
1028 dev_err(dev, "ick clock failed\n");
1029 return -EIO;
1030 }
1031
1032 ret = clk_set_rate(div, clk_round_rate(div, best_act));
1033 if (ret < 0) {
1034 dev_err(dev, "div clock failed\n");
1035 return -EIO;
1036 }
1037
1038 dev_dbg(dev, "ick/div = %ld/%ld\n",
1039 clk_get_rate(ick), clk_get_rate(div));
1040
1041 return ret;
1042}
1043
1044static void fsi_pointer_update(struct fsi_stream *io, int size)
1045{
1046 io->buff_sample_pos += size;
1047
1048 if (io->buff_sample_pos >=
1049 io->period_samples * (io->period_pos + 1)) {
1050 struct snd_pcm_substream *substream = io->substream;
1051 struct snd_pcm_runtime *runtime = substream->runtime;
1052
1053 io->period_pos++;
1054
1055 if (io->period_pos >= runtime->periods) {
1056 io->buff_sample_pos = 0;
1057 io->period_pos = 0;
1058 }
1059
1060 snd_pcm_period_elapsed(substream);
1061 }
1062}
1063
1064/*
1065 * pio data transfer handler
1066 */
1067static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
1068{
1069 int i;
1070
1071 if (fsi_is_enable_stream(fsi)) {
1072 /*
1073 * stream mode
1074 * see
1075 * fsi_pio_push_init()
1076 */
1077 u32 *buf = (u32 *)_buf;
1078
1079 for (i = 0; i < samples / 2; i++)
1080 fsi_reg_write(fsi, DODT, buf[i]);
1081 } else {
1082 /* normal mode */
1083 u16 *buf = (u16 *)_buf;
1084
1085 for (i = 0; i < samples; i++)
1086 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
1087 }
1088}
1089
1090static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
1091{
1092 u16 *buf = (u16 *)_buf;
1093 int i;
1094
1095 for (i = 0; i < samples; i++)
1096 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
1097}
1098
1099static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
1100{
1101 u32 *buf = (u32 *)_buf;
1102 int i;
1103
1104 for (i = 0; i < samples; i++)
1105 fsi_reg_write(fsi, DODT, *(buf + i));
1106}
1107
1108static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
1109{
1110 u32 *buf = (u32 *)_buf;
1111 int i;
1112
1113 for (i = 0; i < samples; i++)
1114 *(buf + i) = fsi_reg_read(fsi, DIDT);
1115}
1116
1117static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
1118{
1119 struct snd_pcm_runtime *runtime = io->substream->runtime;
1120
1121 return runtime->dma_area +
1122 samples_to_bytes(runtime, io->buff_sample_pos);
1123}
1124
1125static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
1126 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
1127 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
1128 int samples)
1129{
1130 u8 *buf;
1131
1132 if (!fsi_stream_is_working(fsi, io))
1133 return -EINVAL;
1134
1135 buf = fsi_pio_get_area(fsi, io);
1136
1137 switch (io->sample_width) {
1138 case 2:
1139 run16(fsi, buf, samples);
1140 break;
1141 case 4:
1142 run32(fsi, buf, samples);
1143 break;
1144 default:
1145 return -EINVAL;
1146 }
1147
1148 fsi_pointer_update(io, samples);
1149
1150 return 0;
1151}
1152
1153static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
1154{
1155 int sample_residues; /* samples in FSI fifo */
1156 int sample_space; /* ALSA free samples space */
1157 int samples;
1158
1159 sample_residues = fsi_get_current_fifo_samples(fsi, io);
1160 sample_space = io->buff_sample_capa - io->buff_sample_pos;
1161
1162 samples = min(sample_residues, sample_space);
1163
1164 return fsi_pio_transfer(fsi, io,
1165 fsi_pio_pop16,
1166 fsi_pio_pop32,
1167 samples);
1168}
1169
1170static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
1171{
1172 int sample_residues; /* ALSA residue samples */
1173 int sample_space; /* FSI fifo free samples space */
1174 int samples;
1175
1176 sample_residues = io->buff_sample_capa - io->buff_sample_pos;
1177 sample_space = io->fifo_sample_capa -
1178 fsi_get_current_fifo_samples(fsi, io);
1179
1180 samples = min(sample_residues, sample_space);
1181
1182 return fsi_pio_transfer(fsi, io,
1183 fsi_pio_push16,
1184 fsi_pio_push32,
1185 samples);
1186}
1187
1188static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1189 int enable)
1190{
1191 struct fsi_master *master = fsi_get_master(fsi);
1192 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1193
1194 if (enable)
1195 fsi_irq_enable(fsi, io);
1196 else
1197 fsi_irq_disable(fsi, io);
1198
1199 if (fsi_is_clk_master(fsi))
1200 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1201
1202 return 0;
1203}
1204
1205static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
1206{
1207 /*
1208 * we can use 16bit stream mode
1209 * when "playback" and "16bit data"
1210 * and platform allows "stream mode"
1211 * see
1212 * fsi_pio_push16()
1213 */
1214 if (fsi_is_enable_stream(fsi))
1215 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1216 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1217 else
1218 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1219 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1220 return 0;
1221}
1222
1223static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
1224{
1225 /*
1226 * always 24bit bus, package back when "capture"
1227 */
1228 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1229 BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
1230 return 0;
1231}
1232
1233static struct fsi_stream_handler fsi_pio_push_handler = {
1234 .init = fsi_pio_push_init,
1235 .transfer = fsi_pio_push,
1236 .start_stop = fsi_pio_start_stop,
1237};
1238
1239static struct fsi_stream_handler fsi_pio_pop_handler = {
1240 .init = fsi_pio_pop_init,
1241 .transfer = fsi_pio_pop,
1242 .start_stop = fsi_pio_start_stop,
1243};
1244
1245static irqreturn_t fsi_interrupt(int irq, void *data)
1246{
1247 struct fsi_master *master = data;
1248 u32 int_st = fsi_irq_get_status(master);
1249
1250 /* clear irq status */
1251 fsi_master_mask_set(master, SOFT_RST, IR, 0);
1252 fsi_master_mask_set(master, SOFT_RST, IR, IR);
1253
1254 if (int_st & AB_IO(1, AO_SHIFT))
1255 fsi_stream_transfer(&master->fsia.playback);
1256 if (int_st & AB_IO(1, BO_SHIFT))
1257 fsi_stream_transfer(&master->fsib.playback);
1258 if (int_st & AB_IO(1, AI_SHIFT))
1259 fsi_stream_transfer(&master->fsia.capture);
1260 if (int_st & AB_IO(1, BI_SHIFT))
1261 fsi_stream_transfer(&master->fsib.capture);
1262
1263 fsi_count_fifo_err(&master->fsia);
1264 fsi_count_fifo_err(&master->fsib);
1265
1266 fsi_irq_clear_status(&master->fsia);
1267 fsi_irq_clear_status(&master->fsib);
1268
1269 return IRQ_HANDLED;
1270}
1271
1272/*
1273 * dma data transfer handler
1274 */
1275static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
1276{
1277 /*
1278 * 24bit data : 24bit bus / package in back
1279 * 16bit data : 16bit bus / stream mode
1280 */
1281 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
1282 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
1283
1284 return 0;
1285}
1286
1287static void fsi_dma_complete(void *data)
1288{
1289 struct fsi_stream *io = (struct fsi_stream *)data;
1290 struct fsi_priv *fsi = fsi_stream_to_priv(io);
1291
1292 fsi_pointer_update(io, io->period_samples);
1293
1294 fsi_count_fifo_err(fsi);
1295}
1296
1297static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
1298{
1299 struct snd_soc_dai *dai = fsi_get_dai(io->substream);
1300 struct snd_pcm_substream *substream = io->substream;
1301 struct dma_async_tx_descriptor *desc;
1302 int is_play = fsi_stream_is_play(fsi, io);
1303 enum dma_transfer_direction dir;
1304 int ret = -EIO;
1305
1306 if (is_play)
1307 dir = DMA_MEM_TO_DEV;
1308 else
1309 dir = DMA_DEV_TO_MEM;
1310
1311 desc = dmaengine_prep_dma_cyclic(io->chan,
1312 substream->runtime->dma_addr,
1313 snd_pcm_lib_buffer_bytes(substream),
1314 snd_pcm_lib_period_bytes(substream),
1315 dir,
1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1317 if (!desc) {
1318 dev_err(dai->dev, "dmaengine_prep_dma_cyclic() fail\n");
1319 goto fsi_dma_transfer_err;
1320 }
1321
1322 desc->callback = fsi_dma_complete;
1323 desc->callback_param = io;
1324
1325 if (dmaengine_submit(desc) < 0) {
1326 dev_err(dai->dev, "tx_submit() fail\n");
1327 goto fsi_dma_transfer_err;
1328 }
1329
1330 dma_async_issue_pending(io->chan);
1331
1332 /*
1333 * FIXME
1334 *
1335 * In DMAEngine case, codec and FSI cannot be started simultaneously
1336 * since FSI is using the scheduler work queue.
1337 * Therefore, in capture case, probably FSI FIFO will have got
1338 * overflow error in this point.
1339 * in that case, DMA cannot start transfer until error was cleared.
1340 */
1341 if (!is_play) {
1342 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
1343 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1344 fsi_reg_write(fsi, DIFF_ST, 0);
1345 }
1346 }
1347
1348 ret = 0;
1349
1350fsi_dma_transfer_err:
1351 return ret;
1352}
1353
1354static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
1355 int start)
1356{
1357 struct fsi_master *master = fsi_get_master(fsi);
1358 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
1359 u32 enable = start ? DMA_ON : 0;
1360
1361 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
1362
1363 dmaengine_terminate_all(io->chan);
1364
1365 if (fsi_is_clk_master(fsi))
1366 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
1367
1368 return 0;
1369}
1370
1371static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
1372{
1373 int is_play = fsi_stream_is_play(fsi, io);
1374
1375#ifdef CONFIG_SUPERH
1376 dma_cap_mask_t mask;
1377 dma_cap_zero(mask);
1378 dma_cap_set(DMA_SLAVE, mask);
1379
1380 io->chan = dma_request_channel(mask, shdma_chan_filter,
1381 (void *)io->dma_id);
1382#else
1383 io->chan = dma_request_slave_channel(dev, is_play ? "tx" : "rx");
1384#endif
1385 if (io->chan) {
1386 struct dma_slave_config cfg = {};
1387 int ret;
1388
1389 if (is_play) {
1390 cfg.dst_addr = fsi->phys + REG_DODT;
1391 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1392 cfg.direction = DMA_MEM_TO_DEV;
1393 } else {
1394 cfg.src_addr = fsi->phys + REG_DIDT;
1395 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1396 cfg.direction = DMA_DEV_TO_MEM;
1397 }
1398
1399 ret = dmaengine_slave_config(io->chan, &cfg);
1400 if (ret < 0) {
1401 dma_release_channel(io->chan);
1402 io->chan = NULL;
1403 }
1404 }
1405
1406 if (!io->chan) {
1407
1408 /* switch to PIO handler */
1409 if (is_play)
1410 fsi->playback.handler = &fsi_pio_push_handler;
1411 else
1412 fsi->capture.handler = &fsi_pio_pop_handler;
1413
1414 dev_info(dev, "switch handler (dma => pio)\n");
1415
1416 /* probe again */
1417 return fsi_stream_probe(fsi, dev);
1418 }
1419
1420 return 0;
1421}
1422
1423static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
1424{
1425 fsi_stream_stop(fsi, io);
1426
1427 if (io->chan)
1428 dma_release_channel(io->chan);
1429
1430 io->chan = NULL;
1431 return 0;
1432}
1433
1434static struct fsi_stream_handler fsi_dma_push_handler = {
1435 .init = fsi_dma_init,
1436 .probe = fsi_dma_probe,
1437 .transfer = fsi_dma_transfer,
1438 .remove = fsi_dma_remove,
1439 .start_stop = fsi_dma_push_start_stop,
1440};
1441
1442/*
1443 * dai ops
1444 */
1445static void fsi_fifo_init(struct fsi_priv *fsi,
1446 struct fsi_stream *io,
1447 struct device *dev)
1448{
1449 struct fsi_master *master = fsi_get_master(fsi);
1450 int is_play = fsi_stream_is_play(fsi, io);
1451 u32 shift, i;
1452 int frame_capa;
1453
1454 /* get on-chip RAM capacity */
1455 shift = fsi_master_read(master, FIFO_SZ);
1456 shift >>= fsi_get_port_shift(fsi, io);
1457 shift &= FIFO_SZ_MASK;
1458 frame_capa = 256 << shift;
1459 dev_dbg(dev, "fifo = %d words\n", frame_capa);
1460
1461 /*
1462 * The maximum number of sample data varies depending
1463 * on the number of channels selected for the format.
1464 *
1465 * FIFOs are used in 4-channel units in 3-channel mode
1466 * and in 8-channel units in 5- to 7-channel mode
1467 * meaning that more FIFOs than the required size of DPRAM
1468 * are used.
1469 *
1470 * ex) if 256 words of DP-RAM is connected
1471 * 1 channel: 256 (256 x 1 = 256)
1472 * 2 channels: 128 (128 x 2 = 256)
1473 * 3 channels: 64 ( 64 x 3 = 192)
1474 * 4 channels: 64 ( 64 x 4 = 256)
1475 * 5 channels: 32 ( 32 x 5 = 160)
1476 * 6 channels: 32 ( 32 x 6 = 192)
1477 * 7 channels: 32 ( 32 x 7 = 224)
1478 * 8 channels: 32 ( 32 x 8 = 256)
1479 */
1480 for (i = 1; i < fsi->chan_num; i <<= 1)
1481 frame_capa >>= 1;
1482 dev_dbg(dev, "%d channel %d store\n",
1483 fsi->chan_num, frame_capa);
1484
1485 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
1486
1487 /*
1488 * set interrupt generation factor
1489 * clear FIFO
1490 */
1491 if (is_play) {
1492 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
1493 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
1494 } else {
1495 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
1496 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
1497 }
1498}
1499
1500static int fsi_hw_startup(struct fsi_priv *fsi,
1501 struct fsi_stream *io,
1502 struct device *dev)
1503{
1504 u32 data = 0;
1505
1506 /* clock setting */
1507 if (fsi_is_clk_master(fsi))
1508 data = DIMD | DOMD;
1509
1510 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
1511
1512 /* clock inversion (CKG2) */
1513 data = 0;
1514 if (fsi->bit_clk_inv)
1515 data |= (1 << 0);
1516 if (fsi->lr_clk_inv)
1517 data |= (1 << 4);
1518 if (fsi_is_clk_master(fsi))
1519 data <<= 8;
1520 fsi_reg_write(fsi, CKG2, data);
1521
1522 /* spdif ? */
1523 if (fsi_is_spdif(fsi)) {
1524 fsi_spdif_clk_ctrl(fsi, 1);
1525 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
1526 }
1527
1528 /*
1529 * get bus settings
1530 */
1531 data = 0;
1532 switch (io->sample_width) {
1533 case 2:
1534 data = BUSOP_GET(16, io->bus_option);
1535 break;
1536 case 4:
1537 data = BUSOP_GET(24, io->bus_option);
1538 break;
1539 }
1540 fsi_format_bus_setup(fsi, io, data, dev);
1541
1542 /* irq clear */
1543 fsi_irq_disable(fsi, io);
1544 fsi_irq_clear_status(fsi);
1545
1546 /* fifo init */
1547 fsi_fifo_init(fsi, io, dev);
1548
1549 /* start master clock */
1550 if (fsi_is_clk_master(fsi))
1551 return fsi_clk_enable(dev, fsi);
1552
1553 return 0;
1554}
1555
1556static int fsi_hw_shutdown(struct fsi_priv *fsi,
1557 struct device *dev)
1558{
1559 /* stop master clock */
1560 if (fsi_is_clk_master(fsi))
1561 return fsi_clk_disable(dev, fsi);
1562
1563 return 0;
1564}
1565
1566static int fsi_dai_startup(struct snd_pcm_substream *substream,
1567 struct snd_soc_dai *dai)
1568{
1569 struct fsi_priv *fsi = fsi_get_priv(substream);
1570
1571 fsi_clk_invalid(fsi);
1572
1573 return 0;
1574}
1575
1576static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
1577 struct snd_soc_dai *dai)
1578{
1579 struct fsi_priv *fsi = fsi_get_priv(substream);
1580
1581 fsi_clk_invalid(fsi);
1582}
1583
1584static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
1585 struct snd_soc_dai *dai)
1586{
1587 struct fsi_priv *fsi = fsi_get_priv(substream);
1588 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1589 int ret = 0;
1590
1591 switch (cmd) {
1592 case SNDRV_PCM_TRIGGER_START:
1593 fsi_stream_init(fsi, io, substream);
1594 if (!ret)
1595 ret = fsi_hw_startup(fsi, io, dai->dev);
1596 if (!ret)
1597 ret = fsi_stream_start(fsi, io);
1598 if (!ret)
1599 ret = fsi_stream_transfer(io);
1600 break;
1601 case SNDRV_PCM_TRIGGER_STOP:
1602 if (!ret)
1603 ret = fsi_hw_shutdown(fsi, dai->dev);
1604 fsi_stream_stop(fsi, io);
1605 fsi_stream_quit(fsi, io);
1606 break;
1607 }
1608
1609 return ret;
1610}
1611
1612static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
1613{
1614 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1615 case SND_SOC_DAIFMT_I2S:
1616 fsi->fmt = CR_I2S;
1617 fsi->chan_num = 2;
1618 break;
1619 case SND_SOC_DAIFMT_LEFT_J:
1620 fsi->fmt = CR_PCM;
1621 fsi->chan_num = 2;
1622 break;
1623 default:
1624 return -EINVAL;
1625 }
1626
1627 return 0;
1628}
1629
1630static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
1631{
1632 struct fsi_master *master = fsi_get_master(fsi);
1633
1634 if (fsi_version(master) < 2)
1635 return -EINVAL;
1636
1637 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
1638 fsi->chan_num = 2;
1639
1640 return 0;
1641}
1642
1643static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1644{
1645 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
1646 int ret;
1647
1648 /* set clock master audio interface */
1649 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1650 case SND_SOC_DAIFMT_BC_FC:
1651 break;
1652 case SND_SOC_DAIFMT_BP_FP:
1653 fsi->clk_master = 1; /* cpu is master */
1654 break;
1655 default:
1656 return -EINVAL;
1657 }
1658
1659 /* set clock inversion */
1660 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1661 case SND_SOC_DAIFMT_NB_IF:
1662 fsi->bit_clk_inv = 0;
1663 fsi->lr_clk_inv = 1;
1664 break;
1665 case SND_SOC_DAIFMT_IB_NF:
1666 fsi->bit_clk_inv = 1;
1667 fsi->lr_clk_inv = 0;
1668 break;
1669 case SND_SOC_DAIFMT_IB_IF:
1670 fsi->bit_clk_inv = 1;
1671 fsi->lr_clk_inv = 1;
1672 break;
1673 case SND_SOC_DAIFMT_NB_NF:
1674 default:
1675 fsi->bit_clk_inv = 0;
1676 fsi->lr_clk_inv = 0;
1677 break;
1678 }
1679
1680 if (fsi_is_clk_master(fsi)) {
1681 if (fsi->clk_cpg)
1682 fsi_clk_init(dai->dev, fsi, 0, 1, 1,
1683 fsi_clk_set_rate_cpg);
1684 else
1685 fsi_clk_init(dai->dev, fsi, 1, 1, 0,
1686 fsi_clk_set_rate_external);
1687 }
1688
1689 /* set format */
1690 if (fsi_is_spdif(fsi))
1691 ret = fsi_set_fmt_spdif(fsi);
1692 else
1693 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1694
1695 return ret;
1696}
1697
1698static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
1699 struct snd_pcm_hw_params *params,
1700 struct snd_soc_dai *dai)
1701{
1702 struct fsi_priv *fsi = fsi_get_priv(substream);
1703
1704 if (fsi_is_clk_master(fsi))
1705 fsi_clk_valid(fsi, params_rate(params));
1706
1707 return 0;
1708}
1709
1710/*
1711 * Select below from Sound Card, not auto
1712 * SND_SOC_DAIFMT_CBC_CFC
1713 * SND_SOC_DAIFMT_CBP_CFP
1714 */
1715static u64 fsi_dai_formats =
1716 SND_SOC_POSSIBLE_DAIFMT_I2S |
1717 SND_SOC_POSSIBLE_DAIFMT_LEFT_J |
1718 SND_SOC_POSSIBLE_DAIFMT_NB_NF |
1719 SND_SOC_POSSIBLE_DAIFMT_NB_IF |
1720 SND_SOC_POSSIBLE_DAIFMT_IB_NF |
1721 SND_SOC_POSSIBLE_DAIFMT_IB_IF;
1722
1723static const struct snd_soc_dai_ops fsi_dai_ops = {
1724 .startup = fsi_dai_startup,
1725 .shutdown = fsi_dai_shutdown,
1726 .trigger = fsi_dai_trigger,
1727 .set_fmt = fsi_dai_set_fmt,
1728 .hw_params = fsi_dai_hw_params,
1729 .auto_selectable_formats = &fsi_dai_formats,
1730 .num_auto_selectable_formats = 1,
1731};
1732
1733/*
1734 * pcm ops
1735 */
1736
1737static const struct snd_pcm_hardware fsi_pcm_hardware = {
1738 .info = SNDRV_PCM_INFO_INTERLEAVED |
1739 SNDRV_PCM_INFO_MMAP |
1740 SNDRV_PCM_INFO_MMAP_VALID,
1741 .buffer_bytes_max = 64 * 1024,
1742 .period_bytes_min = 32,
1743 .period_bytes_max = 8192,
1744 .periods_min = 1,
1745 .periods_max = 32,
1746 .fifo_size = 256,
1747};
1748
1749static int fsi_pcm_open(struct snd_soc_component *component,
1750 struct snd_pcm_substream *substream)
1751{
1752 struct snd_pcm_runtime *runtime = substream->runtime;
1753 int ret = 0;
1754
1755 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
1756
1757 ret = snd_pcm_hw_constraint_integer(runtime,
1758 SNDRV_PCM_HW_PARAM_PERIODS);
1759
1760 return ret;
1761}
1762
1763static snd_pcm_uframes_t fsi_pointer(struct snd_soc_component *component,
1764 struct snd_pcm_substream *substream)
1765{
1766 struct fsi_priv *fsi = fsi_get_priv(substream);
1767 struct fsi_stream *io = fsi_stream_get(fsi, substream);
1768
1769 return fsi_sample2frame(fsi, io->buff_sample_pos);
1770}
1771
1772/*
1773 * snd_soc_component
1774 */
1775
1776#define PREALLOC_BUFFER (32 * 1024)
1777#define PREALLOC_BUFFER_MAX (32 * 1024)
1778
1779static int fsi_pcm_new(struct snd_soc_component *component,
1780 struct snd_soc_pcm_runtime *rtd)
1781{
1782 snd_pcm_set_managed_buffer_all(
1783 rtd->pcm,
1784 SNDRV_DMA_TYPE_DEV,
1785 rtd->card->snd_card->dev,
1786 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
1787 return 0;
1788}
1789
1790/*
1791 * alsa struct
1792 */
1793
1794static struct snd_soc_dai_driver fsi_soc_dai[] = {
1795 {
1796 .name = "fsia-dai",
1797 .playback = {
1798 .rates = FSI_RATES,
1799 .formats = FSI_FMTS,
1800 .channels_min = 2,
1801 .channels_max = 2,
1802 },
1803 .capture = {
1804 .rates = FSI_RATES,
1805 .formats = FSI_FMTS,
1806 .channels_min = 2,
1807 .channels_max = 2,
1808 },
1809 .ops = &fsi_dai_ops,
1810 },
1811 {
1812 .name = "fsib-dai",
1813 .playback = {
1814 .rates = FSI_RATES,
1815 .formats = FSI_FMTS,
1816 .channels_min = 2,
1817 .channels_max = 2,
1818 },
1819 .capture = {
1820 .rates = FSI_RATES,
1821 .formats = FSI_FMTS,
1822 .channels_min = 2,
1823 .channels_max = 2,
1824 },
1825 .ops = &fsi_dai_ops,
1826 },
1827};
1828
1829static const struct snd_soc_component_driver fsi_soc_component = {
1830 .name = "fsi",
1831 .open = fsi_pcm_open,
1832 .pointer = fsi_pointer,
1833 .pcm_construct = fsi_pcm_new,
1834};
1835
1836/*
1837 * platform function
1838 */
1839static void fsi_of_parse(char *name,
1840 struct device_node *np,
1841 struct sh_fsi_port_info *info,
1842 struct device *dev)
1843{
1844 int i;
1845 char prop[128];
1846 unsigned long flags = 0;
1847 struct {
1848 char *name;
1849 unsigned int val;
1850 } of_parse_property[] = {
1851 { "spdif-connection", SH_FSI_FMT_SPDIF },
1852 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
1853 { "use-internal-clock", SH_FSI_CLK_CPG },
1854 };
1855
1856 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
1857 sprintf(prop, "%s,%s", name, of_parse_property[i].name);
1858 if (of_get_property(np, prop, NULL))
1859 flags |= of_parse_property[i].val;
1860 }
1861 info->flags = flags;
1862
1863 dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
1864}
1865
1866static void fsi_port_info_init(struct fsi_priv *fsi,
1867 struct sh_fsi_port_info *info)
1868{
1869 if (info->flags & SH_FSI_FMT_SPDIF)
1870 fsi->spdif = 1;
1871
1872 if (info->flags & SH_FSI_CLK_CPG)
1873 fsi->clk_cpg = 1;
1874
1875 if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
1876 fsi->enable_stream = 1;
1877}
1878
1879static void fsi_handler_init(struct fsi_priv *fsi,
1880 struct sh_fsi_port_info *info)
1881{
1882 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
1883 fsi->playback.priv = fsi;
1884 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
1885 fsi->capture.priv = fsi;
1886
1887 if (info->tx_id) {
1888 fsi->playback.dma_id = info->tx_id;
1889 fsi->playback.handler = &fsi_dma_push_handler;
1890 }
1891}
1892
1893static const struct fsi_core fsi1_core = {
1894 .ver = 1,
1895
1896 /* Interrupt */
1897 .int_st = INT_ST,
1898 .iemsk = IEMSK,
1899 .imsk = IMSK,
1900};
1901
1902static const struct fsi_core fsi2_core = {
1903 .ver = 2,
1904
1905 /* Interrupt */
1906 .int_st = CPU_INT_ST,
1907 .iemsk = CPU_IEMSK,
1908 .imsk = CPU_IMSK,
1909 .a_mclk = A_MST_CTLR,
1910 .b_mclk = B_MST_CTLR,
1911};
1912
1913static const struct of_device_id fsi_of_match[] = {
1914 { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
1915 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
1916 {},
1917};
1918MODULE_DEVICE_TABLE(of, fsi_of_match);
1919
1920static const struct platform_device_id fsi_id_table[] = {
1921 { "sh_fsi", (kernel_ulong_t)&fsi1_core },
1922 {},
1923};
1924MODULE_DEVICE_TABLE(platform, fsi_id_table);
1925
1926static int fsi_probe(struct platform_device *pdev)
1927{
1928 struct fsi_master *master;
1929 struct device_node *np = pdev->dev.of_node;
1930 struct sh_fsi_platform_info info;
1931 const struct fsi_core *core;
1932 struct fsi_priv *fsi;
1933 struct resource *res;
1934 unsigned int irq;
1935 int ret;
1936
1937 memset(&info, 0, sizeof(info));
1938
1939 core = NULL;
1940 if (np) {
1941 core = of_device_get_match_data(&pdev->dev);
1942 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
1943 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
1944 } else {
1945 const struct platform_device_id *id_entry = pdev->id_entry;
1946 if (id_entry)
1947 core = (struct fsi_core *)id_entry->driver_data;
1948
1949 if (pdev->dev.platform_data)
1950 memcpy(&info, pdev->dev.platform_data, sizeof(info));
1951 }
1952
1953 if (!core) {
1954 dev_err(&pdev->dev, "unknown fsi device\n");
1955 return -ENODEV;
1956 }
1957
1958 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1959 irq = platform_get_irq(pdev, 0);
1960 if (!res || (int)irq <= 0) {
1961 dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
1962 return -ENODEV;
1963 }
1964
1965 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
1966 if (!master)
1967 return -ENOMEM;
1968
1969 master->base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
1970 if (!master->base) {
1971 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
1972 return -ENXIO;
1973 }
1974
1975 /* master setting */
1976 master->core = core;
1977 spin_lock_init(&master->lock);
1978
1979 /* FSI A setting */
1980 fsi = &master->fsia;
1981 fsi->base = master->base;
1982 fsi->phys = res->start;
1983 fsi->master = master;
1984 fsi_port_info_init(fsi, &info.port_a);
1985 fsi_handler_init(fsi, &info.port_a);
1986 ret = fsi_stream_probe(fsi, &pdev->dev);
1987 if (ret < 0) {
1988 dev_err(&pdev->dev, "FSIA stream probe failed\n");
1989 return ret;
1990 }
1991
1992 /* FSI B setting */
1993 fsi = &master->fsib;
1994 fsi->base = master->base + 0x40;
1995 fsi->phys = res->start + 0x40;
1996 fsi->master = master;
1997 fsi_port_info_init(fsi, &info.port_b);
1998 fsi_handler_init(fsi, &info.port_b);
1999 ret = fsi_stream_probe(fsi, &pdev->dev);
2000 if (ret < 0) {
2001 dev_err(&pdev->dev, "FSIB stream probe failed\n");
2002 goto exit_fsia;
2003 }
2004
2005 pm_runtime_enable(&pdev->dev);
2006 dev_set_drvdata(&pdev->dev, master);
2007
2008 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
2009 dev_name(&pdev->dev), master);
2010 if (ret) {
2011 dev_err(&pdev->dev, "irq request err\n");
2012 goto exit_fsib;
2013 }
2014
2015 ret = devm_snd_soc_register_component(&pdev->dev, &fsi_soc_component,
2016 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
2017 if (ret < 0) {
2018 dev_err(&pdev->dev, "cannot snd component register\n");
2019 goto exit_fsib;
2020 }
2021
2022 return ret;
2023
2024exit_fsib:
2025 pm_runtime_disable(&pdev->dev);
2026 fsi_stream_remove(&master->fsib);
2027exit_fsia:
2028 fsi_stream_remove(&master->fsia);
2029
2030 return ret;
2031}
2032
2033static int fsi_remove(struct platform_device *pdev)
2034{
2035 struct fsi_master *master;
2036
2037 master = dev_get_drvdata(&pdev->dev);
2038
2039 pm_runtime_disable(&pdev->dev);
2040
2041 fsi_stream_remove(&master->fsia);
2042 fsi_stream_remove(&master->fsib);
2043
2044 return 0;
2045}
2046
2047static void __fsi_suspend(struct fsi_priv *fsi,
2048 struct fsi_stream *io,
2049 struct device *dev)
2050{
2051 if (!fsi_stream_is_working(fsi, io))
2052 return;
2053
2054 fsi_stream_stop(fsi, io);
2055 fsi_hw_shutdown(fsi, dev);
2056}
2057
2058static void __fsi_resume(struct fsi_priv *fsi,
2059 struct fsi_stream *io,
2060 struct device *dev)
2061{
2062 if (!fsi_stream_is_working(fsi, io))
2063 return;
2064
2065 fsi_hw_startup(fsi, io, dev);
2066 fsi_stream_start(fsi, io);
2067}
2068
2069static int fsi_suspend(struct device *dev)
2070{
2071 struct fsi_master *master = dev_get_drvdata(dev);
2072 struct fsi_priv *fsia = &master->fsia;
2073 struct fsi_priv *fsib = &master->fsib;
2074
2075 __fsi_suspend(fsia, &fsia->playback, dev);
2076 __fsi_suspend(fsia, &fsia->capture, dev);
2077
2078 __fsi_suspend(fsib, &fsib->playback, dev);
2079 __fsi_suspend(fsib, &fsib->capture, dev);
2080
2081 return 0;
2082}
2083
2084static int fsi_resume(struct device *dev)
2085{
2086 struct fsi_master *master = dev_get_drvdata(dev);
2087 struct fsi_priv *fsia = &master->fsia;
2088 struct fsi_priv *fsib = &master->fsib;
2089
2090 __fsi_resume(fsia, &fsia->playback, dev);
2091 __fsi_resume(fsia, &fsia->capture, dev);
2092
2093 __fsi_resume(fsib, &fsib->playback, dev);
2094 __fsi_resume(fsib, &fsib->capture, dev);
2095
2096 return 0;
2097}
2098
2099static const struct dev_pm_ops fsi_pm_ops = {
2100 .suspend = fsi_suspend,
2101 .resume = fsi_resume,
2102};
2103
2104static struct platform_driver fsi_driver = {
2105 .driver = {
2106 .name = "fsi-pcm-audio",
2107 .pm = &fsi_pm_ops,
2108 .of_match_table = fsi_of_match,
2109 },
2110 .probe = fsi_probe,
2111 .remove = fsi_remove,
2112 .id_table = fsi_id_table,
2113};
2114
2115module_platform_driver(fsi_driver);
2116
2117MODULE_LICENSE("GPL v2");
2118MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
2119MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
2120MODULE_ALIAS("platform:fsi-pcm-audio");