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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/sound/cs42l42.h -- Platform data for CS42L42 ALSA SoC audio driver header
4 *
5 * Copyright 2016-2022 Cirrus Logic, Inc.
6 *
7 * Author: James Schulman <james.schulman@cirrus.com>
8 * Author: Brian Austin <brian.austin@cirrus.com>
9 * Author: Michael White <michael.white@cirrus.com>
10 */
11
12#ifndef __CS42L42_H
13#define __CS42L42_H
14
15#define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
16#define CS42L42_WIN_START 0x00
17#define CS42L42_WIN_LEN 0x100
18#define CS42L42_RANGE_MIN 0x00
19#define CS42L42_RANGE_MAX 0x7F
20
21#define CS42L42_PAGE_10 0x1000
22#define CS42L42_PAGE_11 0x1100
23#define CS42L42_PAGE_12 0x1200
24#define CS42L42_PAGE_13 0x1300
25#define CS42L42_PAGE_15 0x1500
26#define CS42L42_PAGE_19 0x1900
27#define CS42L42_PAGE_1B 0x1B00
28#define CS42L42_PAGE_1C 0x1C00
29#define CS42L42_PAGE_1D 0x1D00
30#define CS42L42_PAGE_1F 0x1F00
31#define CS42L42_PAGE_20 0x2000
32#define CS42L42_PAGE_21 0x2100
33#define CS42L42_PAGE_23 0x2300
34#define CS42L42_PAGE_24 0x2400
35#define CS42L42_PAGE_25 0x2500
36#define CS42L42_PAGE_26 0x2600
37#define CS42L42_PAGE_28 0x2800
38#define CS42L42_PAGE_29 0x2900
39#define CS42L42_PAGE_2A 0x2A00
40#define CS42L42_PAGE_30 0x3000
41
42#define CS42L42_CHIP_ID 0x42A42
43#define CS42L83_CHIP_ID 0x42A83
44
45/* Page 0x10 Global Registers */
46#define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
47#define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02)
48#define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03)
49#define CS42L42_FABID (CS42L42_PAGE_10 + 0x04)
50#define CS42L42_REVID (CS42L42_PAGE_10 + 0x05)
51#define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06)
52
53#define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07)
54#define CS42L42_SRC_BYPASS_DAC_SHIFT 1
55#define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT)
56
57#define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08)
58
59#define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09)
60#define CS42L42_INTERNAL_FS_SHIFT 1
61#define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT)
62
63#define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A)
64#define CS42L42_SLOW_START_ENABLE (CS42L42_PAGE_10 + 0x0B)
65#define CS42L42_SLOW_START_EN_MASK GENMASK(6, 4)
66#define CS42L42_SLOW_START_EN_SHIFT 4
67#define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E)
68#define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F)
69#define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10)
70
71/* Page 0x11 Power and Headset Detect Registers */
72#define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01)
73#define CS42L42_ASP_DAO_PDN_SHIFT 7
74#define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT)
75#define CS42L42_ASP_DAI_PDN_SHIFT 6
76#define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT)
77#define CS42L42_MIXER_PDN_SHIFT 5
78#define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT)
79#define CS42L42_EQ_PDN_SHIFT 4
80#define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT)
81#define CS42L42_HP_PDN_SHIFT 3
82#define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT)
83#define CS42L42_ADC_PDN_SHIFT 2
84#define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT)
85#define CS42L42_PDN_ALL_SHIFT 0
86#define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT)
87
88#define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02)
89#define CS42L42_ADC_SRC_PDNB_SHIFT 0
90#define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT)
91#define CS42L42_DAC_SRC_PDNB_SHIFT 1
92#define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT)
93#define CS42L42_ASP_DAI1_PDN_SHIFT 2
94#define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT)
95#define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3
96#define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT)
97#define CS42L42_DISCHARGE_FILT_SHIFT 4
98#define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT)
99
100#define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03)
101#define CS42L42_RING_SENSE_PDNB_SHIFT 1
102#define CS42L42_RING_SENSE_PDNB_MASK (1 << CS42L42_RING_SENSE_PDNB_SHIFT)
103#define CS42L42_VPMON_PDNB_SHIFT 2
104#define CS42L42_VPMON_PDNB_MASK (1 << CS42L42_VPMON_PDNB_SHIFT)
105#define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5
106#define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << CS42L42_SW_CLK_STP_STAT_SEL_SHIFT)
107
108#define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04)
109#define CS42L42_RS_TRIM_R_SHIFT 0
110#define CS42L42_RS_TRIM_R_MASK (1 << CS42L42_RS_TRIM_R_SHIFT)
111#define CS42L42_RS_TRIM_T_SHIFT 1
112#define CS42L42_RS_TRIM_T_MASK (1 << CS42L42_RS_TRIM_T_SHIFT)
113#define CS42L42_HPREF_RS_SHIFT 2
114#define CS42L42_HPREF_RS_MASK (1 << CS42L42_HPREF_RS_SHIFT)
115#define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3
116#define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << CS42L42_HSBIAS_FILT_REF_RS_SHIFT)
117#define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6
118#define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << CS42L42_RING_SENSE_PU_HIZ_SHIFT)
119
120#define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05)
121#define CS42L42_TS_RS_GATE_SHIFT 7
122#define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT)
123
124#define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07)
125#define CS42L42_SCLK_PRESENT_SHIFT 0
126#define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT)
127
128#define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09)
129#define CS42L42_OSC_SW_SEL_STAT_SHIFT 0
130#define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
131#define CS42L42_OSC_PDNB_STAT_SHIFT 2
132#define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT)
133
134#define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12)
135#define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0
136#define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << CS42L42_RS_RISE_DBNCE_TIME_SHIFT)
137#define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3
138#define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << CS42L42_RS_FALL_DBNCE_TIME_SHIFT)
139#define CS42L42_RS_PU_EN_SHIFT 6
140#define CS42L42_RS_PU_EN_MASK (1 << CS42L42_RS_PU_EN_SHIFT)
141#define CS42L42_RS_INV_SHIFT 7
142#define CS42L42_RS_INV_MASK (1 << CS42L42_RS_INV_SHIFT)
143
144#define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13)
145#define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0
146#define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << CS42L42_TS_RISE_DBNCE_TIME_SHIFT)
147#define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3
148#define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << CS42L42_TS_FALL_DBNCE_TIME_SHIFT)
149#define CS42L42_TS_INV_SHIFT 7
150#define CS42L42_TS_INV_MASK (1 << CS42L42_TS_INV_SHIFT)
151
152#define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14)
153#define CS42L42_D_RS_PLUG_DBNC_SHIFT 0
154#define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT)
155#define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1
156#define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT)
157#define CS42L42_D_TS_PLUG_DBNC_SHIFT 2
158#define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT)
159#define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3
160#define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT)
161
162#define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15)
163#define CS42L42_RS_PLUG_DBNC_SHIFT 0
164#define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT)
165#define CS42L42_RS_UNPLUG_DBNC_SHIFT 1
166#define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT)
167#define CS42L42_TS_PLUG_DBNC_SHIFT 2
168#define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT)
169#define CS42L42_TS_UNPLUG_DBNC_SHIFT 3
170#define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT)
171
172#define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F)
173#define CS42L42_HSDET_COMP1_LVL_SHIFT 0
174#define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT)
175#define CS42L42_HSDET_COMP2_LVL_SHIFT 4
176#define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT)
177
178#define CS42L42_HSDET_COMP1_LVL_VAL 12 /* 1.25V Comparator */
179#define CS42L42_HSDET_COMP2_LVL_VAL 2 /* 1.75V Comparator */
180#define CS42L42_HSDET_COMP1_LVL_DEFAULT 7 /* 1V Comparator */
181#define CS42L42_HSDET_COMP2_LVL_DEFAULT 7 /* 2V Comparator */
182
183#define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20)
184#define CS42L42_HSDET_AUTO_TIME_SHIFT 0
185#define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT)
186#define CS42L42_HSBIAS_REF_SHIFT 3
187#define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT)
188#define CS42L42_HSDET_SET_SHIFT 4
189#define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT)
190#define CS42L42_HSDET_CTRL_SHIFT 6
191#define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT)
192
193#define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21)
194#define CS42L42_SW_GNDHS_HS4_SHIFT 0
195#define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT)
196#define CS42L42_SW_GNDHS_HS3_SHIFT 1
197#define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT)
198#define CS42L42_SW_HSB_HS4_SHIFT 2
199#define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT)
200#define CS42L42_SW_HSB_HS3_SHIFT 3
201#define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT)
202#define CS42L42_SW_HSB_FILT_HS4_SHIFT 4
203#define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT)
204#define CS42L42_SW_HSB_FILT_HS3_SHIFT 5
205#define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT)
206#define CS42L42_SW_REF_HS4_SHIFT 6
207#define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT)
208#define CS42L42_SW_REF_HS3_SHIFT 7
209#define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT)
210
211#define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24)
212#define CS42L42_HSDET_TYPE_SHIFT 0
213#define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT)
214#define CS42L42_HSDET_COMP1_OUT_SHIFT 6
215#define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT)
216#define CS42L42_HSDET_COMP2_OUT_SHIFT 7
217#define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT)
218#define CS42L42_PLUG_CTIA 0
219#define CS42L42_PLUG_OMTP 1
220#define CS42L42_PLUG_HEADPHONE 2
221#define CS42L42_PLUG_INVALID 3
222
223#define CS42L42_HSDET_SW_COMP1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
224 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
225 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
226 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
227 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
228 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
229 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
230 (1 << CS42L42_SW_REF_HS3_SHIFT))
231#define CS42L42_HSDET_SW_COMP2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
232 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
233 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
234 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \
235 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
236 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
237 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
238 (0 << CS42L42_SW_REF_HS3_SHIFT))
239#define CS42L42_HSDET_SW_TYPE1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
240 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
241 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
242 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
243 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
244 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
245 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
246 (1 << CS42L42_SW_REF_HS3_SHIFT))
247#define CS42L42_HSDET_SW_TYPE2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
248 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
249 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
250 (1 << CS42L42_SW_HSB_HS3_SHIFT) | \
251 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
252 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
253 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
254 (0 << CS42L42_SW_REF_HS3_SHIFT))
255#define CS42L42_HSDET_SW_TYPE3 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
256 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
257 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
258 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
259 (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
260 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
261 (1 << CS42L42_SW_REF_HS4_SHIFT) | \
262 (1 << CS42L42_SW_REF_HS3_SHIFT))
263#define CS42L42_HSDET_SW_TYPE4 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
264 (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
265 (1 << CS42L42_SW_HSB_HS4_SHIFT) | \
266 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
267 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
268 (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
269 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
270 (1 << CS42L42_SW_REF_HS3_SHIFT))
271
272#define CS42L42_HSDET_COMP_TYPE1 1
273#define CS42L42_HSDET_COMP_TYPE2 2
274#define CS42L42_HSDET_COMP_TYPE3 0
275#define CS42L42_HSDET_COMP_TYPE4 3
276
277#define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29)
278#define CS42L42_HS_CLAMP_DISABLE_SHIFT 0
279#define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT)
280
281/* Page 0x12 Clocking Registers */
282#define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01)
283#define CS42L42_MCLKDIV_SHIFT 1
284#define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT)
285#define CS42L42_MCLK_SRC_SEL_SHIFT 0
286#define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT)
287
288#define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02)
289#define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03)
290
291#define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04)
292#define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0
293#define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \
294 CS42L42_FSYNC_PULSE_WIDTH_SHIFT)
295
296#define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05)
297
298#define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06)
299#define CS42L42_FSYNC_PERIOD_SHIFT 0
300#define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
301
302#define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07)
303#define CS42L42_ASP_SCLK_EN_SHIFT 5
304#define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT)
305#define CS42L42_ASP_MASTER_MODE 0x01
306#define CS42L42_ASP_SLAVE_MODE 0x00
307#define CS42L42_ASP_MODE_SHIFT 4
308#define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT)
309#define CS42L42_ASP_SCPOL_SHIFT 2
310#define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT)
311#define CS42L42_ASP_SCPOL_NOR 3
312#define CS42L42_ASP_LCPOL_SHIFT 0
313#define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT)
314#define CS42L42_ASP_LCPOL_INV 3
315
316#define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08)
317#define CS42L42_ASP_STP_SHIFT 4
318#define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT)
319#define CS42L42_ASP_5050_SHIFT 3
320#define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT)
321#define CS42L42_ASP_FSD_SHIFT 0
322#define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT)
323#define CS42L42_ASP_FSD_0_5 1
324#define CS42L42_ASP_FSD_1_0 2
325#define CS42L42_ASP_FSD_1_5 3
326#define CS42L42_ASP_FSD_2_0 4
327
328#define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09)
329#define CS42L42_FS_EN_SHIFT 0
330#define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT)
331#define CS42L42_FS_EN_IASRC_96K 0x1
332#define CS42L42_FS_EN_OASRC_96K 0x2
333
334#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
335#define CS42L42_CLK_IASRC_SEL_SHIFT 0
336#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT)
337#define CS42L42_CLK_IASRC_SEL_6 0
338#define CS42L42_CLK_IASRC_SEL_12 1
339
340#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
341#define CS42L42_CLK_OASRC_SEL_SHIFT 0
342#define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT)
343#define CS42L42_CLK_OASRC_SEL_12 1
344
345#define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C)
346#define CS42L42_SCLK_PREDIV_SHIFT 0
347#define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT)
348
349/* Page 0x13 Interrupt Registers */
350/* Interrupts */
351#define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01)
352#define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02)
353#define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03)
354#define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04)
355#define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05)
356#define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08)
357#define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09)
358#define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A)
359#define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B)
360#define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D)
361#define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E)
362#define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F)
363/* Masks */
364#define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16)
365#define CS42L42_ADC_OVFL_SHIFT 0
366#define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT)
367#define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK
368
369#define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17)
370#define CS42L42_MIX_CHB_OVFL_SHIFT 0
371#define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT)
372#define CS42L42_MIX_CHA_OVFL_SHIFT 1
373#define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT)
374#define CS42L42_EQ_OVFL_SHIFT 2
375#define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT)
376#define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3
377#define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT)
378#define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \
379 CS42L42_MIX_CHA_OVFL_MASK | \
380 CS42L42_EQ_OVFL_MASK | \
381 CS42L42_EQ_BIQUAD_OVFL_MASK)
382
383#define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18)
384#define CS42L42_SRC_ILK_SHIFT 0
385#define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT)
386#define CS42L42_SRC_OLK_SHIFT 1
387#define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT)
388#define CS42L42_SRC_IUNLK_SHIFT 2
389#define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT)
390#define CS42L42_SRC_OUNLK_SHIFT 3
391#define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT)
392#define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \
393 CS42L42_SRC_OLK_MASK | \
394 CS42L42_SRC_IUNLK_MASK | \
395 CS42L42_SRC_OUNLK_MASK)
396
397#define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19)
398#define CS42L42_ASPRX_NOLRCK_SHIFT 0
399#define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT)
400#define CS42L42_ASPRX_EARLY_SHIFT 1
401#define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT)
402#define CS42L42_ASPRX_LATE_SHIFT 2
403#define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT)
404#define CS42L42_ASPRX_ERROR_SHIFT 3
405#define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT)
406#define CS42L42_ASPRX_OVLD_SHIFT 4
407#define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT)
408#define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \
409 CS42L42_ASPRX_EARLY_MASK | \
410 CS42L42_ASPRX_LATE_MASK | \
411 CS42L42_ASPRX_ERROR_MASK | \
412 CS42L42_ASPRX_OVLD_MASK)
413
414#define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A)
415#define CS42L42_ASPTX_NOLRCK_SHIFT 0
416#define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT)
417#define CS42L42_ASPTX_EARLY_SHIFT 1
418#define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT)
419#define CS42L42_ASPTX_LATE_SHIFT 2
420#define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT)
421#define CS42L42_ASPTX_SMERROR_SHIFT 3
422#define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT)
423#define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \
424 CS42L42_ASPTX_EARLY_MASK | \
425 CS42L42_ASPTX_LATE_MASK | \
426 CS42L42_ASPTX_SMERROR_MASK)
427
428#define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B)
429#define CS42L42_PDN_DONE_SHIFT 0
430#define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT)
431#define CS42L42_HSDET_AUTO_DONE_SHIFT 1
432#define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT)
433#define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \
434 CS42L42_HSDET_AUTO_DONE_MASK)
435
436#define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C)
437#define CS42L42_SRCPL_ADC_LK_SHIFT 0
438#define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT)
439#define CS42L42_SRCPL_DAC_LK_SHIFT 2
440#define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT)
441#define CS42L42_SRCPL_ADC_UNLK_SHIFT 5
442#define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT)
443#define CS42L42_SRCPL_DAC_UNLK_SHIFT 6
444#define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT)
445#define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \
446 CS42L42_SRCPL_DAC_LK_MASK | \
447 CS42L42_SRCPL_ADC_UNLK_MASK | \
448 CS42L42_SRCPL_DAC_UNLK_MASK)
449
450#define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E)
451#define CS42L42_VPMON_SHIFT 0
452#define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT)
453#define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK
454
455#define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F)
456#define CS42L42_PLL_LOCK_SHIFT 0
457#define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT)
458#define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK
459
460#define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20)
461#define CS42L42_RS_PLUG_SHIFT 0
462#define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT)
463#define CS42L42_RS_UNPLUG_SHIFT 1
464#define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT)
465#define CS42L42_TS_PLUG_SHIFT 2
466#define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT)
467#define CS42L42_TS_UNPLUG_SHIFT 3
468#define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT)
469#define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \
470 CS42L42_RS_UNPLUG_MASK | \
471 CS42L42_TS_PLUG_MASK | \
472 CS42L42_TS_UNPLUG_MASK)
473#define CS42L42_TS_PLUG 3
474#define CS42L42_TS_UNPLUG 0
475#define CS42L42_TS_TRANS 1
476
477/*
478 * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1.
479 * Otherwise it will prevent FILT+ from charging properly.
480 */
481#define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01)
482#define CS42L42_PLL_START_SHIFT 0
483#define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT)
484
485#define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02)
486#define CS42L42_PLL_DIV_FRAC_SHIFT 0
487#define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
488
489#define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03)
490#define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04)
491
492#define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05)
493#define CS42L42_PLL_DIV_INT_SHIFT 0
494#define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT)
495
496#define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08)
497#define CS42L42_PLL_DIVOUT_SHIFT 0
498#define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT)
499
500#define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A)
501#define CS42L42_PLL_CAL_RATIO_SHIFT 0
502#define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
503
504#define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B)
505#define CS42L42_PLL_MODE_SHIFT 0
506#define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT)
507
508/* Page 0x19 HP Load Detect Registers */
509#define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25)
510#define CS42L42_RLA_STAT_SHIFT 0
511#define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT)
512#define CS42L42_RLA_STAT_15_OHM 0
513
514#define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26)
515#define CS42L42_HPLOAD_DET_DONE_SHIFT 0
516#define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT)
517
518#define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27)
519#define CS42L42_HP_LD_EN_SHIFT 0
520#define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT)
521
522/* Page 0x1B Headset Interface Registers */
523#define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70)
524#define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0
525#define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT)
526#define CS42L42_TIP_SENSE_EN_SHIFT 5
527#define CS42L42_TIP_SENSE_EN_MASK (1 << CS42L42_TIP_SENSE_EN_SHIFT)
528#define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6
529#define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT)
530#define CS42L42_HSBIAS_SENSE_EN_SHIFT 7
531#define CS42L42_HSBIAS_SENSE_EN_MASK (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT)
532
533#define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71)
534#define CS42L42_WAKEB_CLEAR_SHIFT 0
535#define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT)
536#define CS42L42_WAKEB_MODE_SHIFT 5
537#define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT)
538#define CS42L42_M_HP_WAKE_SHIFT 6
539#define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT)
540#define CS42L42_M_MIC_WAKE_SHIFT 7
541#define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT)
542
543#define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72)
544#define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7
545#define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << CS42L42_ADC_DISABLE_S0_MUTE_SHIFT)
546
547#define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73)
548#define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0
549#define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT)
550#define CS42L42_TIP_SENSE_INV_SHIFT 5
551#define CS42L42_TIP_SENSE_INV_MASK (1 << CS42L42_TIP_SENSE_INV_SHIFT)
552#define CS42L42_TIP_SENSE_CTRL_SHIFT 6
553#define CS42L42_TIP_SENSE_CTRL_MASK (3 << CS42L42_TIP_SENSE_CTRL_SHIFT)
554
555/*
556 * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1.
557 * Otherwise it will prevent FILT+ from charging properly.
558 */
559#define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74)
560#define CS42L42_PDN_MIC_LVL_DET_SHIFT 0
561#define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT)
562#define CS42L42_HSBIAS_CTL_SHIFT 1
563#define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT)
564#define CS42L42_DETECT_MODE_SHIFT 3
565#define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT)
566
567#define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75)
568#define CS42L42_HS_DET_LEVEL_SHIFT 0
569#define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
570#define CS42L42_EVENT_STAT_SEL_SHIFT 6
571#define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT)
572#define CS42L42_LATCH_TO_VP_SHIFT 7
573#define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT)
574
575#define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76)
576#define CS42L42_DEBOUNCE_TIME_SHIFT 5
577#define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
578
579#define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77)
580#define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6
581#define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT)
582#define CS42L42_TIP_SENSE_SHIFT 7
583#define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT)
584
585#define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78)
586#define CS42L42_SHORT_TRUE_SHIFT 0
587#define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT)
588#define CS42L42_HS_TRUE_SHIFT 1
589#define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT)
590
591#define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79)
592#define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5
593#define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT)
594#define CS42L42_TIP_SENSE_PLUG_SHIFT 6
595#define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT)
596#define CS42L42_HSBIAS_SENSE_SHIFT 7
597#define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT)
598#define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \
599 CS42L42_TIP_SENSE_PLUG_MASK | \
600 CS42L42_HSBIAS_SENSE_MASK)
601
602#define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A)
603#define CS42L42_M_SHORT_DET_SHIFT 0
604#define CS42L42_M_SHORT_DET_MASK (1 << CS42L42_M_SHORT_DET_SHIFT)
605#define CS42L42_M_SHORT_RLS_SHIFT 1
606#define CS42L42_M_SHORT_RLS_MASK (1 << CS42L42_M_SHORT_RLS_SHIFT)
607#define CS42L42_M_HSBIAS_HIZ_SHIFT 2
608#define CS42L42_M_HSBIAS_HIZ_MASK (1 << CS42L42_M_HSBIAS_HIZ_SHIFT)
609#define CS42L42_M_DETECT_FT_SHIFT 6
610#define CS42L42_M_DETECT_FT_MASK (1 << CS42L42_M_DETECT_FT_SHIFT)
611#define CS42L42_M_DETECT_TF_SHIFT 7
612#define CS42L42_M_DETECT_TF_MASK (1 << CS42L42_M_DETECT_TF_SHIFT)
613#define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \
614 CS42L42_M_SHORT_RLS_MASK | \
615 CS42L42_M_HSBIAS_HIZ_MASK | \
616 CS42L42_M_DETECT_FT_MASK | \
617 CS42L42_M_DETECT_TF_MASK)
618
619/* Page 0x1C Headset Bias Registers */
620#define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03)
621#define CS42L42_HSBIAS_RAMP_SHIFT 0
622#define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT)
623#define CS42L42_HSBIAS_PD_SHIFT 4
624#define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT)
625#define CS42L42_HSBIAS_CAPLESS_SHIFT 7
626#define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT)
627
628/* Page 0x1D ADC Registers */
629#define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01)
630#define CS42L42_ADC_NOTCH_DIS_SHIFT 5
631#define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4
632#define CS42L42_ADC_INV_SHIFT 2
633#define CS42L42_ADC_DIG_BOOST_SHIFT 0
634
635#define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03)
636#define CS42L42_ADC_VOL_SHIFT 0
637
638#define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04)
639#define CS42L42_ADC_WNF_CF_SHIFT 4
640#define CS42L42_ADC_WNF_EN_SHIFT 3
641#define CS42L42_ADC_HPF_CF_SHIFT 1
642#define CS42L42_ADC_HPF_EN_SHIFT 0
643
644/* Page 0x1F DAC Registers */
645#define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01)
646#define CS42L42_DACB_INV_SHIFT 1
647#define CS42L42_DACA_INV_SHIFT 0
648
649#define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06)
650#define CS42L42_HPOUT_PULLDOWN_SHIFT 4
651#define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT)
652#define CS42L42_HPOUT_LOAD_SHIFT 3
653#define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT)
654#define CS42L42_HPOUT_CLAMP_SHIFT 2
655#define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT)
656#define CS42L42_DAC_HPF_EN_SHIFT 1
657#define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT)
658#define CS42L42_DAC_MON_EN_SHIFT 0
659#define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT)
660
661/* Page 0x20 HP CTL Registers */
662#define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01)
663#define CS42L42_HP_ANA_BMUTE_SHIFT 3
664#define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT)
665#define CS42L42_HP_ANA_AMUTE_SHIFT 2
666#define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT)
667#define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1
668#define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT)
669
670/* Page 0x21 Class H Registers */
671#define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01)
672
673/* Page 0x23 Mixer Volume Registers */
674#define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01)
675#define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02)
676
677#define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03)
678#define CS42L42_MIXER_CH_VOL_SHIFT 0
679#define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
680
681/* Page 0x24 EQ Registers */
682#define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01)
683#define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02)
684#define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03)
685#define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04)
686#define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06)
687#define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07)
688#define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08)
689#define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09)
690#define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A)
691#define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B)
692#define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C)
693#define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E)
694
695/* Page 0x25 Audio Port Registers */
696#define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01)
697#define CS42L42_SP_RX_CHB_SEL_SHIFT 2
698#define CS42L42_SP_RX_CHB_SEL_MASK (3 << CS42L42_SP_RX_CHB_SEL_SHIFT)
699
700#define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02)
701#define CS42L42_SP_RX_RSYNC_SHIFT 6
702#define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT)
703#define CS42L42_SP_RX_NSB_POS_SHIFT 3
704#define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT)
705#define CS42L42_SP_RX_NFS_NSBB_SHIFT 2
706#define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT)
707#define CS42L42_SP_RX_ISOC_MODE_SHIFT 0
708#define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT)
709
710#define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03)
711#define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04)
712#define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05)
713#define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06)
714#define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07)
715
716/* Page 0x26 SRC Registers */
717#define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01)
718#define CS42L42_SRC_SDIN_FS_SHIFT 0
719#define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
720
721#define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
722
723/* Page 0x28 S/PDIF Registers */
724#define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
725#define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
726#define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03)
727#define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04)
728
729/* Page 0x29 Serial Port TX Registers */
730#define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01)
731#define CS42L42_ASP_TX_EN_SHIFT 0
732#define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02)
733#define CS42L42_ASP_TX0_CH2_SHIFT 1
734#define CS42L42_ASP_TX0_CH1_SHIFT 0
735
736#define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03)
737#define CS42L42_ASP_TX_CH1_AP_SHIFT 7
738#define CS42L42_ASP_TX_CH1_AP_MASK (1 << CS42L42_ASP_TX_CH1_AP_SHIFT)
739#define CS42L42_ASP_TX_CH2_AP_SHIFT 6
740#define CS42L42_ASP_TX_CH2_AP_MASK (1 << CS42L42_ASP_TX_CH2_AP_SHIFT)
741#define CS42L42_ASP_TX_CH2_RES_SHIFT 2
742#define CS42L42_ASP_TX_CH2_RES_MASK (3 << CS42L42_ASP_TX_CH2_RES_SHIFT)
743#define CS42L42_ASP_TX_CH1_RES_SHIFT 0
744#define CS42L42_ASP_TX_CH1_RES_MASK (3 << CS42L42_ASP_TX_CH1_RES_SHIFT)
745#define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04)
746#define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05)
747#define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06)
748#define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A)
749#define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B)
750
751/* Page 0x2A Serial Port RX Registers */
752#define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01)
753#define CS42L42_ASP_RX0_CH_EN_SHIFT 2
754#define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
755#define CS42L42_ASP_RX0_CH1_SHIFT 2
756#define CS42L42_ASP_RX0_CH2_SHIFT 3
757#define CS42L42_ASP_RX0_CH3_SHIFT 4
758#define CS42L42_ASP_RX0_CH4_SHIFT 5
759
760#define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02)
761#define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
762#define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
763#define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05)
764#define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
765#define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
766#define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08)
767#define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
768#define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
769#define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B)
770#define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
771#define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
772#define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E)
773#define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
774#define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
775#define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11)
776#define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
777#define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
778
779#define CS42L42_ASP_RX_CH_AP_SHIFT 6
780#define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT)
781#define CS42L42_ASP_RX_CH_AP_LOW 0
782#define CS42L42_ASP_RX_CH_AP_HI 1
783#define CS42L42_ASP_RX_CH_RES_SHIFT 0
784#define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT)
785#define CS42L42_ASP_RX_CH_RES_32 3
786#define CS42L42_ASP_RX_CH_RES_16 1
787#define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0
788#define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
789
790/* Page 0x30 ID Registers */
791#define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14)
792#define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14)
793
794/* Defines for fracturing values spread across multiple registers */
795#define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff)
796#define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8)
797#define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16)
798
799#define CS42L42_NUM_SUPPLIES 5
800#define CS42L42_BOOT_TIME_US 3000
801#define CS42L42_PLL_DIVOUT_TIME_US 800
802#define CS42L42_CLOCK_SWITCH_DELAY_US 150
803#define CS42L42_PLL_LOCK_POLL_US 250
804#define CS42L42_PLL_LOCK_TIMEOUT_US 1250
805#define CS42L42_HP_ADC_EN_TIME_US 20000
806#define CS42L42_PDN_DONE_POLL_US 1000
807#define CS42L42_PDN_DONE_TIMEOUT_US 200000
808#define CS42L42_PDN_DONE_TIME_MS 100
809#define CS42L42_FILT_DISCHARGE_TIME_MS 46
810
811#endif /* __CS42L42_H */