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1/*
2 * intel TCO Watchdog Driver
3 *
4 * (c) Copyright 2006-2010 Wim Van Sebroeck <wim@iguana.be>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
14 *
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
36 * document number TBD : Patsburg (PBG)
37 * document number TBD : DH89xxCC
38 * document number TBD : Panther Point
39 */
40
41/*
42 * Includes, defines, variables, module parameters, ...
43 */
44
45/* Module and version information */
46#define DRV_NAME "iTCO_wdt"
47#define DRV_VERSION "1.06"
48#define PFX DRV_NAME ": "
49
50/* Includes */
51#include <linux/module.h> /* For module specific items */
52#include <linux/moduleparam.h> /* For new moduleparam's */
53#include <linux/types.h> /* For standard types (like size_t) */
54#include <linux/errno.h> /* For the -ENODEV/... values */
55#include <linux/kernel.h> /* For printk/panic/... */
56#include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
57 (WATCHDOG_MINOR) */
58#include <linux/watchdog.h> /* For the watchdog specific items */
59#include <linux/init.h> /* For __init/__exit/... */
60#include <linux/fs.h> /* For file operations */
61#include <linux/platform_device.h> /* For platform_driver framework */
62#include <linux/pci.h> /* For pci functions */
63#include <linux/ioport.h> /* For io-port access */
64#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
65#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
66#include <linux/io.h> /* For inb/outb/... */
67
68#include "iTCO_vendor.h"
69
70/* TCO related info */
71enum iTCO_chipsets {
72 TCO_ICH = 0, /* ICH */
73 TCO_ICH0, /* ICH0 */
74 TCO_ICH2, /* ICH2 */
75 TCO_ICH2M, /* ICH2-M */
76 TCO_ICH3, /* ICH3-S */
77 TCO_ICH3M, /* ICH3-M */
78 TCO_ICH4, /* ICH4 */
79 TCO_ICH4M, /* ICH4-M */
80 TCO_CICH, /* C-ICH */
81 TCO_ICH5, /* ICH5 & ICH5R */
82 TCO_6300ESB, /* 6300ESB */
83 TCO_ICH6, /* ICH6 & ICH6R */
84 TCO_ICH6M, /* ICH6-M */
85 TCO_ICH6W, /* ICH6W & ICH6RW */
86 TCO_631XESB, /* 631xESB/632xESB */
87 TCO_ICH7, /* ICH7 & ICH7R */
88 TCO_ICH7DH, /* ICH7DH */
89 TCO_ICH7M, /* ICH7-M & ICH7-U */
90 TCO_ICH7MDH, /* ICH7-M DH */
91 TCO_NM10, /* NM10 */
92 TCO_ICH8, /* ICH8 & ICH8R */
93 TCO_ICH8DH, /* ICH8DH */
94 TCO_ICH8DO, /* ICH8DO */
95 TCO_ICH8M, /* ICH8M */
96 TCO_ICH8ME, /* ICH8M-E */
97 TCO_ICH9, /* ICH9 */
98 TCO_ICH9R, /* ICH9R */
99 TCO_ICH9DH, /* ICH9DH */
100 TCO_ICH9DO, /* ICH9DO */
101 TCO_ICH9M, /* ICH9M */
102 TCO_ICH9ME, /* ICH9M-E */
103 TCO_ICH10, /* ICH10 */
104 TCO_ICH10R, /* ICH10R */
105 TCO_ICH10D, /* ICH10D */
106 TCO_ICH10DO, /* ICH10DO */
107 TCO_PCH, /* PCH Desktop Full Featured */
108 TCO_PCHM, /* PCH Mobile Full Featured */
109 TCO_P55, /* P55 */
110 TCO_PM55, /* PM55 */
111 TCO_H55, /* H55 */
112 TCO_QM57, /* QM57 */
113 TCO_H57, /* H57 */
114 TCO_HM55, /* HM55 */
115 TCO_Q57, /* Q57 */
116 TCO_HM57, /* HM57 */
117 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */
118 TCO_QS57, /* QS57 */
119 TCO_3400, /* 3400 */
120 TCO_3420, /* 3420 */
121 TCO_3450, /* 3450 */
122 TCO_EP80579, /* EP80579 */
123 TCO_CPT, /* Cougar Point */
124 TCO_CPTD, /* Cougar Point Desktop */
125 TCO_CPTM, /* Cougar Point Mobile */
126 TCO_PBG, /* Patsburg */
127 TCO_DH89XXCC, /* DH89xxCC */
128 TCO_PPT, /* Panther Point */
129};
130
131static struct {
132 char *name;
133 unsigned int iTCO_version;
134} iTCO_chipset_info[] __devinitdata = {
135 {"ICH", 1},
136 {"ICH0", 1},
137 {"ICH2", 1},
138 {"ICH2-M", 1},
139 {"ICH3-S", 1},
140 {"ICH3-M", 1},
141 {"ICH4", 1},
142 {"ICH4-M", 1},
143 {"C-ICH", 1},
144 {"ICH5 or ICH5R", 1},
145 {"6300ESB", 1},
146 {"ICH6 or ICH6R", 2},
147 {"ICH6-M", 2},
148 {"ICH6W or ICH6RW", 2},
149 {"631xESB/632xESB", 2},
150 {"ICH7 or ICH7R", 2},
151 {"ICH7DH", 2},
152 {"ICH7-M or ICH7-U", 2},
153 {"ICH7-M DH", 2},
154 {"NM10", 2},
155 {"ICH8 or ICH8R", 2},
156 {"ICH8DH", 2},
157 {"ICH8DO", 2},
158 {"ICH8M", 2},
159 {"ICH8M-E", 2},
160 {"ICH9", 2},
161 {"ICH9R", 2},
162 {"ICH9DH", 2},
163 {"ICH9DO", 2},
164 {"ICH9M", 2},
165 {"ICH9M-E", 2},
166 {"ICH10", 2},
167 {"ICH10R", 2},
168 {"ICH10D", 2},
169 {"ICH10DO", 2},
170 {"PCH Desktop Full Featured", 2},
171 {"PCH Mobile Full Featured", 2},
172 {"P55", 2},
173 {"PM55", 2},
174 {"H55", 2},
175 {"QM57", 2},
176 {"H57", 2},
177 {"HM55", 2},
178 {"Q57", 2},
179 {"HM57", 2},
180 {"PCH Mobile SFF Full Featured", 2},
181 {"QS57", 2},
182 {"3400", 2},
183 {"3420", 2},
184 {"3450", 2},
185 {"EP80579", 2},
186 {"Cougar Point", 2},
187 {"Cougar Point Desktop", 2},
188 {"Cougar Point Mobile", 2},
189 {"Patsburg", 2},
190 {"DH89xxCC", 2},
191 {"Panther Point", 2},
192 {NULL, 0}
193};
194
195/*
196 * This data only exists for exporting the supported PCI ids
197 * via MODULE_DEVICE_TABLE. We do not actually register a
198 * pci_driver, because the I/O Controller Hub has also other
199 * functions that probably will be registered by other drivers.
200 */
201static DEFINE_PCI_DEVICE_TABLE(iTCO_wdt_pci_tbl) = {
202 { PCI_VDEVICE(INTEL, 0x2410), TCO_ICH},
203 { PCI_VDEVICE(INTEL, 0x2420), TCO_ICH0},
204 { PCI_VDEVICE(INTEL, 0x2440), TCO_ICH2},
205 { PCI_VDEVICE(INTEL, 0x244c), TCO_ICH2M},
206 { PCI_VDEVICE(INTEL, 0x2480), TCO_ICH3},
207 { PCI_VDEVICE(INTEL, 0x248c), TCO_ICH3M},
208 { PCI_VDEVICE(INTEL, 0x24c0), TCO_ICH4},
209 { PCI_VDEVICE(INTEL, 0x24cc), TCO_ICH4M},
210 { PCI_VDEVICE(INTEL, 0x2450), TCO_CICH},
211 { PCI_VDEVICE(INTEL, 0x24d0), TCO_ICH5},
212 { PCI_VDEVICE(INTEL, 0x25a1), TCO_6300ESB},
213 { PCI_VDEVICE(INTEL, 0x2640), TCO_ICH6},
214 { PCI_VDEVICE(INTEL, 0x2641), TCO_ICH6M},
215 { PCI_VDEVICE(INTEL, 0x2642), TCO_ICH6W},
216 { PCI_VDEVICE(INTEL, 0x2670), TCO_631XESB},
217 { PCI_VDEVICE(INTEL, 0x2671), TCO_631XESB},
218 { PCI_VDEVICE(INTEL, 0x2672), TCO_631XESB},
219 { PCI_VDEVICE(INTEL, 0x2673), TCO_631XESB},
220 { PCI_VDEVICE(INTEL, 0x2674), TCO_631XESB},
221 { PCI_VDEVICE(INTEL, 0x2675), TCO_631XESB},
222 { PCI_VDEVICE(INTEL, 0x2676), TCO_631XESB},
223 { PCI_VDEVICE(INTEL, 0x2677), TCO_631XESB},
224 { PCI_VDEVICE(INTEL, 0x2678), TCO_631XESB},
225 { PCI_VDEVICE(INTEL, 0x2679), TCO_631XESB},
226 { PCI_VDEVICE(INTEL, 0x267a), TCO_631XESB},
227 { PCI_VDEVICE(INTEL, 0x267b), TCO_631XESB},
228 { PCI_VDEVICE(INTEL, 0x267c), TCO_631XESB},
229 { PCI_VDEVICE(INTEL, 0x267d), TCO_631XESB},
230 { PCI_VDEVICE(INTEL, 0x267e), TCO_631XESB},
231 { PCI_VDEVICE(INTEL, 0x267f), TCO_631XESB},
232 { PCI_VDEVICE(INTEL, 0x27b8), TCO_ICH7},
233 { PCI_VDEVICE(INTEL, 0x27b0), TCO_ICH7DH},
234 { PCI_VDEVICE(INTEL, 0x27b9), TCO_ICH7M},
235 { PCI_VDEVICE(INTEL, 0x27bd), TCO_ICH7MDH},
236 { PCI_VDEVICE(INTEL, 0x27bc), TCO_NM10},
237 { PCI_VDEVICE(INTEL, 0x2810), TCO_ICH8},
238 { PCI_VDEVICE(INTEL, 0x2812), TCO_ICH8DH},
239 { PCI_VDEVICE(INTEL, 0x2814), TCO_ICH8DO},
240 { PCI_VDEVICE(INTEL, 0x2815), TCO_ICH8M},
241 { PCI_VDEVICE(INTEL, 0x2811), TCO_ICH8ME},
242 { PCI_VDEVICE(INTEL, 0x2918), TCO_ICH9},
243 { PCI_VDEVICE(INTEL, 0x2916), TCO_ICH9R},
244 { PCI_VDEVICE(INTEL, 0x2912), TCO_ICH9DH},
245 { PCI_VDEVICE(INTEL, 0x2914), TCO_ICH9DO},
246 { PCI_VDEVICE(INTEL, 0x2919), TCO_ICH9M},
247 { PCI_VDEVICE(INTEL, 0x2917), TCO_ICH9ME},
248 { PCI_VDEVICE(INTEL, 0x3a18), TCO_ICH10},
249 { PCI_VDEVICE(INTEL, 0x3a16), TCO_ICH10R},
250 { PCI_VDEVICE(INTEL, 0x3a1a), TCO_ICH10D},
251 { PCI_VDEVICE(INTEL, 0x3a14), TCO_ICH10DO},
252 { PCI_VDEVICE(INTEL, 0x3b00), TCO_PCH},
253 { PCI_VDEVICE(INTEL, 0x3b01), TCO_PCHM},
254 { PCI_VDEVICE(INTEL, 0x3b02), TCO_P55},
255 { PCI_VDEVICE(INTEL, 0x3b03), TCO_PM55},
256 { PCI_VDEVICE(INTEL, 0x3b06), TCO_H55},
257 { PCI_VDEVICE(INTEL, 0x3b07), TCO_QM57},
258 { PCI_VDEVICE(INTEL, 0x3b08), TCO_H57},
259 { PCI_VDEVICE(INTEL, 0x3b09), TCO_HM55},
260 { PCI_VDEVICE(INTEL, 0x3b0a), TCO_Q57},
261 { PCI_VDEVICE(INTEL, 0x3b0b), TCO_HM57},
262 { PCI_VDEVICE(INTEL, 0x3b0d), TCO_PCHMSFF},
263 { PCI_VDEVICE(INTEL, 0x3b0f), TCO_QS57},
264 { PCI_VDEVICE(INTEL, 0x3b12), TCO_3400},
265 { PCI_VDEVICE(INTEL, 0x3b14), TCO_3420},
266 { PCI_VDEVICE(INTEL, 0x3b16), TCO_3450},
267 { PCI_VDEVICE(INTEL, 0x5031), TCO_EP80579},
268 { PCI_VDEVICE(INTEL, 0x1c41), TCO_CPT},
269 { PCI_VDEVICE(INTEL, 0x1c42), TCO_CPTD},
270 { PCI_VDEVICE(INTEL, 0x1c43), TCO_CPTM},
271 { PCI_VDEVICE(INTEL, 0x1c44), TCO_CPT},
272 { PCI_VDEVICE(INTEL, 0x1c45), TCO_CPT},
273 { PCI_VDEVICE(INTEL, 0x1c46), TCO_CPT},
274 { PCI_VDEVICE(INTEL, 0x1c47), TCO_CPT},
275 { PCI_VDEVICE(INTEL, 0x1c48), TCO_CPT},
276 { PCI_VDEVICE(INTEL, 0x1c49), TCO_CPT},
277 { PCI_VDEVICE(INTEL, 0x1c4a), TCO_CPT},
278 { PCI_VDEVICE(INTEL, 0x1c4b), TCO_CPT},
279 { PCI_VDEVICE(INTEL, 0x1c4c), TCO_CPT},
280 { PCI_VDEVICE(INTEL, 0x1c4d), TCO_CPT},
281 { PCI_VDEVICE(INTEL, 0x1c4e), TCO_CPT},
282 { PCI_VDEVICE(INTEL, 0x1c4f), TCO_CPT},
283 { PCI_VDEVICE(INTEL, 0x1c50), TCO_CPT},
284 { PCI_VDEVICE(INTEL, 0x1c51), TCO_CPT},
285 { PCI_VDEVICE(INTEL, 0x1c52), TCO_CPT},
286 { PCI_VDEVICE(INTEL, 0x1c53), TCO_CPT},
287 { PCI_VDEVICE(INTEL, 0x1c54), TCO_CPT},
288 { PCI_VDEVICE(INTEL, 0x1c55), TCO_CPT},
289 { PCI_VDEVICE(INTEL, 0x1c56), TCO_CPT},
290 { PCI_VDEVICE(INTEL, 0x1c57), TCO_CPT},
291 { PCI_VDEVICE(INTEL, 0x1c58), TCO_CPT},
292 { PCI_VDEVICE(INTEL, 0x1c59), TCO_CPT},
293 { PCI_VDEVICE(INTEL, 0x1c5a), TCO_CPT},
294 { PCI_VDEVICE(INTEL, 0x1c5b), TCO_CPT},
295 { PCI_VDEVICE(INTEL, 0x1c5c), TCO_CPT},
296 { PCI_VDEVICE(INTEL, 0x1c5d), TCO_CPT},
297 { PCI_VDEVICE(INTEL, 0x1c5e), TCO_CPT},
298 { PCI_VDEVICE(INTEL, 0x1c5f), TCO_CPT},
299 { PCI_VDEVICE(INTEL, 0x1d40), TCO_PBG},
300 { PCI_VDEVICE(INTEL, 0x1d41), TCO_PBG},
301 { PCI_VDEVICE(INTEL, 0x2310), TCO_DH89XXCC},
302 { PCI_VDEVICE(INTEL, 0x1e40), TCO_PPT},
303 { PCI_VDEVICE(INTEL, 0x1e41), TCO_PPT},
304 { PCI_VDEVICE(INTEL, 0x1e42), TCO_PPT},
305 { PCI_VDEVICE(INTEL, 0x1e43), TCO_PPT},
306 { PCI_VDEVICE(INTEL, 0x1e44), TCO_PPT},
307 { PCI_VDEVICE(INTEL, 0x1e45), TCO_PPT},
308 { PCI_VDEVICE(INTEL, 0x1e46), TCO_PPT},
309 { PCI_VDEVICE(INTEL, 0x1e47), TCO_PPT},
310 { PCI_VDEVICE(INTEL, 0x1e48), TCO_PPT},
311 { PCI_VDEVICE(INTEL, 0x1e49), TCO_PPT},
312 { PCI_VDEVICE(INTEL, 0x1e4a), TCO_PPT},
313 { PCI_VDEVICE(INTEL, 0x1e4b), TCO_PPT},
314 { PCI_VDEVICE(INTEL, 0x1e4c), TCO_PPT},
315 { PCI_VDEVICE(INTEL, 0x1e4d), TCO_PPT},
316 { PCI_VDEVICE(INTEL, 0x1e4e), TCO_PPT},
317 { PCI_VDEVICE(INTEL, 0x1e4f), TCO_PPT},
318 { PCI_VDEVICE(INTEL, 0x1e50), TCO_PPT},
319 { PCI_VDEVICE(INTEL, 0x1e51), TCO_PPT},
320 { PCI_VDEVICE(INTEL, 0x1e52), TCO_PPT},
321 { PCI_VDEVICE(INTEL, 0x1e53), TCO_PPT},
322 { PCI_VDEVICE(INTEL, 0x1e54), TCO_PPT},
323 { PCI_VDEVICE(INTEL, 0x1e55), TCO_PPT},
324 { PCI_VDEVICE(INTEL, 0x1e56), TCO_PPT},
325 { PCI_VDEVICE(INTEL, 0x1e57), TCO_PPT},
326 { PCI_VDEVICE(INTEL, 0x1e58), TCO_PPT},
327 { PCI_VDEVICE(INTEL, 0x1e59), TCO_PPT},
328 { PCI_VDEVICE(INTEL, 0x1e5a), TCO_PPT},
329 { PCI_VDEVICE(INTEL, 0x1e5b), TCO_PPT},
330 { PCI_VDEVICE(INTEL, 0x1e5c), TCO_PPT},
331 { PCI_VDEVICE(INTEL, 0x1e5d), TCO_PPT},
332 { PCI_VDEVICE(INTEL, 0x1e5e), TCO_PPT},
333 { PCI_VDEVICE(INTEL, 0x1e5f), TCO_PPT},
334 { 0, }, /* End of list */
335};
336MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
337
338/* Address definitions for the TCO */
339/* TCO base address */
340#define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
341/* SMI Control and Enable Register */
342#define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
343
344#define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
345#define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
346#define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
347#define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
348#define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
349#define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
350#define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
351#define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
352#define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
353
354/* internal variables */
355static unsigned long is_active;
356static char expect_release;
357static struct { /* this is private data for the iTCO_wdt device */
358 /* TCO version/generation */
359 unsigned int iTCO_version;
360 /* The device's ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
361 unsigned long ACPIBASE;
362 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
363 unsigned long __iomem *gcs;
364 /* the lock for io operations */
365 spinlock_t io_lock;
366 /* the PCI-device */
367 struct pci_dev *pdev;
368} iTCO_wdt_private;
369
370/* the watchdog platform device */
371static struct platform_device *iTCO_wdt_platform_device;
372
373/* module parameters */
374#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
375static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
376module_param(heartbeat, int, 0);
377MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
378 "5..76 (TCO v1) or 3..614 (TCO v2), default="
379 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
380
381static int nowayout = WATCHDOG_NOWAYOUT;
382module_param(nowayout, int, 0);
383MODULE_PARM_DESC(nowayout,
384 "Watchdog cannot be stopped once started (default="
385 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
386
387/*
388 * Some TCO specific functions
389 */
390
391static inline unsigned int seconds_to_ticks(int seconds)
392{
393 /* the internal timer is stored as ticks which decrement
394 * every 0.6 seconds */
395 return (seconds * 10) / 6;
396}
397
398static void iTCO_wdt_set_NO_REBOOT_bit(void)
399{
400 u32 val32;
401
402 /* Set the NO_REBOOT bit: this disables reboots */
403 if (iTCO_wdt_private.iTCO_version == 2) {
404 val32 = readl(iTCO_wdt_private.gcs);
405 val32 |= 0x00000020;
406 writel(val32, iTCO_wdt_private.gcs);
407 } else if (iTCO_wdt_private.iTCO_version == 1) {
408 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
409 val32 |= 0x00000002;
410 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
411 }
412}
413
414static int iTCO_wdt_unset_NO_REBOOT_bit(void)
415{
416 int ret = 0;
417 u32 val32;
418
419 /* Unset the NO_REBOOT bit: this enables reboots */
420 if (iTCO_wdt_private.iTCO_version == 2) {
421 val32 = readl(iTCO_wdt_private.gcs);
422 val32 &= 0xffffffdf;
423 writel(val32, iTCO_wdt_private.gcs);
424
425 val32 = readl(iTCO_wdt_private.gcs);
426 if (val32 & 0x00000020)
427 ret = -EIO;
428 } else if (iTCO_wdt_private.iTCO_version == 1) {
429 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
430 val32 &= 0xfffffffd;
431 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
432
433 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
434 if (val32 & 0x00000002)
435 ret = -EIO;
436 }
437
438 return ret; /* returns: 0 = OK, -EIO = Error */
439}
440
441static int iTCO_wdt_start(void)
442{
443 unsigned int val;
444
445 spin_lock(&iTCO_wdt_private.io_lock);
446
447 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
448
449 /* disable chipset's NO_REBOOT bit */
450 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
451 spin_unlock(&iTCO_wdt_private.io_lock);
452 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
453 "reboot disabled by hardware/BIOS\n");
454 return -EIO;
455 }
456
457 /* Force the timer to its reload value by writing to the TCO_RLD
458 register */
459 if (iTCO_wdt_private.iTCO_version == 2)
460 outw(0x01, TCO_RLD);
461 else if (iTCO_wdt_private.iTCO_version == 1)
462 outb(0x01, TCO_RLD);
463
464 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
465 val = inw(TCO1_CNT);
466 val &= 0xf7ff;
467 outw(val, TCO1_CNT);
468 val = inw(TCO1_CNT);
469 spin_unlock(&iTCO_wdt_private.io_lock);
470
471 if (val & 0x0800)
472 return -1;
473 return 0;
474}
475
476static int iTCO_wdt_stop(void)
477{
478 unsigned int val;
479
480 spin_lock(&iTCO_wdt_private.io_lock);
481
482 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
483
484 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
485 val = inw(TCO1_CNT);
486 val |= 0x0800;
487 outw(val, TCO1_CNT);
488 val = inw(TCO1_CNT);
489
490 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
491 iTCO_wdt_set_NO_REBOOT_bit();
492
493 spin_unlock(&iTCO_wdt_private.io_lock);
494
495 if ((val & 0x0800) == 0)
496 return -1;
497 return 0;
498}
499
500static int iTCO_wdt_keepalive(void)
501{
502 spin_lock(&iTCO_wdt_private.io_lock);
503
504 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
505
506 /* Reload the timer by writing to the TCO Timer Counter register */
507 if (iTCO_wdt_private.iTCO_version == 2)
508 outw(0x01, TCO_RLD);
509 else if (iTCO_wdt_private.iTCO_version == 1) {
510 /* Reset the timeout status bit so that the timer
511 * needs to count down twice again before rebooting */
512 outw(0x0008, TCO1_STS); /* write 1 to clear bit */
513
514 outb(0x01, TCO_RLD);
515 }
516
517 spin_unlock(&iTCO_wdt_private.io_lock);
518 return 0;
519}
520
521static int iTCO_wdt_set_heartbeat(int t)
522{
523 unsigned int val16;
524 unsigned char val8;
525 unsigned int tmrval;
526
527 tmrval = seconds_to_ticks(t);
528
529 /* For TCO v1 the timer counts down twice before rebooting */
530 if (iTCO_wdt_private.iTCO_version == 1)
531 tmrval /= 2;
532
533 /* from the specs: */
534 /* "Values of 0h-3h are ignored and should not be attempted" */
535 if (tmrval < 0x04)
536 return -EINVAL;
537 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
538 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
539 return -EINVAL;
540
541 iTCO_vendor_pre_set_heartbeat(tmrval);
542
543 /* Write new heartbeat to watchdog */
544 if (iTCO_wdt_private.iTCO_version == 2) {
545 spin_lock(&iTCO_wdt_private.io_lock);
546 val16 = inw(TCOv2_TMR);
547 val16 &= 0xfc00;
548 val16 |= tmrval;
549 outw(val16, TCOv2_TMR);
550 val16 = inw(TCOv2_TMR);
551 spin_unlock(&iTCO_wdt_private.io_lock);
552
553 if ((val16 & 0x3ff) != tmrval)
554 return -EINVAL;
555 } else if (iTCO_wdt_private.iTCO_version == 1) {
556 spin_lock(&iTCO_wdt_private.io_lock);
557 val8 = inb(TCOv1_TMR);
558 val8 &= 0xc0;
559 val8 |= (tmrval & 0xff);
560 outb(val8, TCOv1_TMR);
561 val8 = inb(TCOv1_TMR);
562 spin_unlock(&iTCO_wdt_private.io_lock);
563
564 if ((val8 & 0x3f) != tmrval)
565 return -EINVAL;
566 }
567
568 heartbeat = t;
569 return 0;
570}
571
572static int iTCO_wdt_get_timeleft(int *time_left)
573{
574 unsigned int val16;
575 unsigned char val8;
576
577 /* read the TCO Timer */
578 if (iTCO_wdt_private.iTCO_version == 2) {
579 spin_lock(&iTCO_wdt_private.io_lock);
580 val16 = inw(TCO_RLD);
581 val16 &= 0x3ff;
582 spin_unlock(&iTCO_wdt_private.io_lock);
583
584 *time_left = (val16 * 6) / 10;
585 } else if (iTCO_wdt_private.iTCO_version == 1) {
586 spin_lock(&iTCO_wdt_private.io_lock);
587 val8 = inb(TCO_RLD);
588 val8 &= 0x3f;
589 if (!(inw(TCO1_STS) & 0x0008))
590 val8 += (inb(TCOv1_TMR) & 0x3f);
591 spin_unlock(&iTCO_wdt_private.io_lock);
592
593 *time_left = (val8 * 6) / 10;
594 } else
595 return -EINVAL;
596 return 0;
597}
598
599/*
600 * /dev/watchdog handling
601 */
602
603static int iTCO_wdt_open(struct inode *inode, struct file *file)
604{
605 /* /dev/watchdog can only be opened once */
606 if (test_and_set_bit(0, &is_active))
607 return -EBUSY;
608
609 /*
610 * Reload and activate timer
611 */
612 iTCO_wdt_start();
613 return nonseekable_open(inode, file);
614}
615
616static int iTCO_wdt_release(struct inode *inode, struct file *file)
617{
618 /*
619 * Shut off the timer.
620 */
621 if (expect_release == 42) {
622 iTCO_wdt_stop();
623 } else {
624 printk(KERN_CRIT PFX
625 "Unexpected close, not stopping watchdog!\n");
626 iTCO_wdt_keepalive();
627 }
628 clear_bit(0, &is_active);
629 expect_release = 0;
630 return 0;
631}
632
633static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
634 size_t len, loff_t *ppos)
635{
636 /* See if we got the magic character 'V' and reload the timer */
637 if (len) {
638 if (!nowayout) {
639 size_t i;
640
641 /* note: just in case someone wrote the magic
642 character five months ago... */
643 expect_release = 0;
644
645 /* scan to see whether or not we got the
646 magic character */
647 for (i = 0; i != len; i++) {
648 char c;
649 if (get_user(c, data + i))
650 return -EFAULT;
651 if (c == 'V')
652 expect_release = 42;
653 }
654 }
655
656 /* someone wrote to us, we should reload the timer */
657 iTCO_wdt_keepalive();
658 }
659 return len;
660}
661
662static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
663 unsigned long arg)
664{
665 int new_options, retval = -EINVAL;
666 int new_heartbeat;
667 void __user *argp = (void __user *)arg;
668 int __user *p = argp;
669 static const struct watchdog_info ident = {
670 .options = WDIOF_SETTIMEOUT |
671 WDIOF_KEEPALIVEPING |
672 WDIOF_MAGICCLOSE,
673 .firmware_version = 0,
674 .identity = DRV_NAME,
675 };
676
677 switch (cmd) {
678 case WDIOC_GETSUPPORT:
679 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
680 case WDIOC_GETSTATUS:
681 case WDIOC_GETBOOTSTATUS:
682 return put_user(0, p);
683
684 case WDIOC_SETOPTIONS:
685 {
686 if (get_user(new_options, p))
687 return -EFAULT;
688
689 if (new_options & WDIOS_DISABLECARD) {
690 iTCO_wdt_stop();
691 retval = 0;
692 }
693 if (new_options & WDIOS_ENABLECARD) {
694 iTCO_wdt_keepalive();
695 iTCO_wdt_start();
696 retval = 0;
697 }
698 return retval;
699 }
700 case WDIOC_KEEPALIVE:
701 iTCO_wdt_keepalive();
702 return 0;
703
704 case WDIOC_SETTIMEOUT:
705 {
706 if (get_user(new_heartbeat, p))
707 return -EFAULT;
708 if (iTCO_wdt_set_heartbeat(new_heartbeat))
709 return -EINVAL;
710 iTCO_wdt_keepalive();
711 /* Fall */
712 }
713 case WDIOC_GETTIMEOUT:
714 return put_user(heartbeat, p);
715 case WDIOC_GETTIMELEFT:
716 {
717 int time_left;
718 if (iTCO_wdt_get_timeleft(&time_left))
719 return -EINVAL;
720 return put_user(time_left, p);
721 }
722 default:
723 return -ENOTTY;
724 }
725}
726
727/*
728 * Kernel Interfaces
729 */
730
731static const struct file_operations iTCO_wdt_fops = {
732 .owner = THIS_MODULE,
733 .llseek = no_llseek,
734 .write = iTCO_wdt_write,
735 .unlocked_ioctl = iTCO_wdt_ioctl,
736 .open = iTCO_wdt_open,
737 .release = iTCO_wdt_release,
738};
739
740static struct miscdevice iTCO_wdt_miscdev = {
741 .minor = WATCHDOG_MINOR,
742 .name = "watchdog",
743 .fops = &iTCO_wdt_fops,
744};
745
746/*
747 * Init & exit routines
748 */
749
750static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
751 const struct pci_device_id *ent, struct platform_device *dev)
752{
753 int ret;
754 u32 base_address;
755 unsigned long RCBA;
756 unsigned long val32;
757
758 /*
759 * Find the ACPI/PM base I/O address which is the base
760 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
761 * ACPIBASE is bits [15:7] from 0x40-0x43
762 */
763 pci_read_config_dword(pdev, 0x40, &base_address);
764 base_address &= 0x0000ff80;
765 if (base_address == 0x00000000) {
766 /* Something's wrong here, ACPIBASE has to be set */
767 printk(KERN_ERR PFX "failed to get TCOBASE address, "
768 "device disabled by hardware/BIOS\n");
769 return -ENODEV;
770 }
771 iTCO_wdt_private.iTCO_version =
772 iTCO_chipset_info[ent->driver_data].iTCO_version;
773 iTCO_wdt_private.ACPIBASE = base_address;
774 iTCO_wdt_private.pdev = pdev;
775
776 /* Get the Memory-Mapped GCS register, we need it for the
777 NO_REBOOT flag (TCO v2). To get access to it you have to
778 read RCBA from PCI Config space 0xf0 and use it as base.
779 GCS = RCBA + ICH6_GCS(0x3410). */
780 if (iTCO_wdt_private.iTCO_version == 2) {
781 pci_read_config_dword(pdev, 0xf0, &base_address);
782 if ((base_address & 1) == 0) {
783 printk(KERN_ERR PFX "RCBA is disabled by hardware"
784 "/BIOS, device disabled\n");
785 ret = -ENODEV;
786 goto out;
787 }
788 RCBA = base_address & 0xffffc000;
789 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
790 }
791
792 /* Check chipset's NO_REBOOT bit */
793 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
794 printk(KERN_INFO PFX "unable to reset NO_REBOOT flag, "
795 "device disabled by hardware/BIOS\n");
796 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
797 goto out_unmap;
798 }
799
800 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
801 iTCO_wdt_set_NO_REBOOT_bit();
802
803 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
804 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
805 printk(KERN_ERR PFX
806 "I/O address 0x%04lx already in use, "
807 "device disabled\n", SMI_EN);
808 ret = -EIO;
809 goto out_unmap;
810 }
811 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
812 val32 = inl(SMI_EN);
813 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
814 outl(val32, SMI_EN);
815
816 /* The TCO I/O registers reside in a 32-byte range pointed to
817 by the TCOBASE value */
818 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
819 printk(KERN_ERR PFX "I/O address 0x%04lx already in use "
820 "device disabled\n", TCOBASE);
821 ret = -EIO;
822 goto unreg_smi_en;
823 }
824
825 printk(KERN_INFO PFX
826 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
827 iTCO_chipset_info[ent->driver_data].name,
828 iTCO_chipset_info[ent->driver_data].iTCO_version,
829 TCOBASE);
830
831 /* Clear out the (probably old) status */
832 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
833 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
834 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
835
836 /* Make sure the watchdog is not running */
837 iTCO_wdt_stop();
838
839 /* Check that the heartbeat value is within it's range;
840 if not reset to the default */
841 if (iTCO_wdt_set_heartbeat(heartbeat)) {
842 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
843 printk(KERN_INFO PFX
844 "timeout value out of range, using %d\n", heartbeat);
845 }
846
847 ret = misc_register(&iTCO_wdt_miscdev);
848 if (ret != 0) {
849 printk(KERN_ERR PFX
850 "cannot register miscdev on minor=%d (err=%d)\n",
851 WATCHDOG_MINOR, ret);
852 goto unreg_region;
853 }
854
855 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
856 heartbeat, nowayout);
857
858 return 0;
859
860unreg_region:
861 release_region(TCOBASE, 0x20);
862unreg_smi_en:
863 release_region(SMI_EN, 4);
864out_unmap:
865 if (iTCO_wdt_private.iTCO_version == 2)
866 iounmap(iTCO_wdt_private.gcs);
867out:
868 iTCO_wdt_private.ACPIBASE = 0;
869 return ret;
870}
871
872static void __devexit iTCO_wdt_cleanup(void)
873{
874 /* Stop the timer before we leave */
875 if (!nowayout)
876 iTCO_wdt_stop();
877
878 /* Deregister */
879 misc_deregister(&iTCO_wdt_miscdev);
880 release_region(TCOBASE, 0x20);
881 release_region(SMI_EN, 4);
882 if (iTCO_wdt_private.iTCO_version == 2)
883 iounmap(iTCO_wdt_private.gcs);
884 pci_dev_put(iTCO_wdt_private.pdev);
885 iTCO_wdt_private.ACPIBASE = 0;
886}
887
888static int __devinit iTCO_wdt_probe(struct platform_device *dev)
889{
890 int ret = -ENODEV;
891 int found = 0;
892 struct pci_dev *pdev = NULL;
893 const struct pci_device_id *ent;
894
895 spin_lock_init(&iTCO_wdt_private.io_lock);
896
897 for_each_pci_dev(pdev) {
898 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
899 if (ent) {
900 found++;
901 ret = iTCO_wdt_init(pdev, ent, dev);
902 if (!ret)
903 break;
904 }
905 }
906
907 if (!found)
908 printk(KERN_INFO PFX "No device detected.\n");
909
910 return ret;
911}
912
913static int __devexit iTCO_wdt_remove(struct platform_device *dev)
914{
915 if (iTCO_wdt_private.ACPIBASE)
916 iTCO_wdt_cleanup();
917
918 return 0;
919}
920
921static void iTCO_wdt_shutdown(struct platform_device *dev)
922{
923 iTCO_wdt_stop();
924}
925
926static struct platform_driver iTCO_wdt_driver = {
927 .probe = iTCO_wdt_probe,
928 .remove = __devexit_p(iTCO_wdt_remove),
929 .shutdown = iTCO_wdt_shutdown,
930 .driver = {
931 .owner = THIS_MODULE,
932 .name = DRV_NAME,
933 },
934};
935
936static int __init iTCO_wdt_init_module(void)
937{
938 int err;
939
940 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
941 DRV_VERSION);
942
943 err = platform_driver_register(&iTCO_wdt_driver);
944 if (err)
945 return err;
946
947 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
948 -1, NULL, 0);
949 if (IS_ERR(iTCO_wdt_platform_device)) {
950 err = PTR_ERR(iTCO_wdt_platform_device);
951 goto unreg_platform_driver;
952 }
953
954 return 0;
955
956unreg_platform_driver:
957 platform_driver_unregister(&iTCO_wdt_driver);
958 return err;
959}
960
961static void __exit iTCO_wdt_cleanup_module(void)
962{
963 platform_device_unregister(iTCO_wdt_platform_device);
964 platform_driver_unregister(&iTCO_wdt_driver);
965 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
966}
967
968module_init(iTCO_wdt_init_module);
969module_exit(iTCO_wdt_cleanup_module);
970
971MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
972MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
973MODULE_VERSION(DRV_VERSION);
974MODULE_LICENSE("GPL");
975MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * intel TCO Watchdog Driver
4 *
5 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
6 *
7 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
8 * provide warranty for any of this software. This material is
9 * provided "AS-IS" and at no charge.
10 *
11 * The TCO watchdog is implemented in the following I/O controller hubs:
12 * (See the intel documentation on http://developer.intel.com.)
13 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
14 * document number 290687-002, 298242-027: 82801BA (ICH2)
15 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
16 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
17 * document number 290744-001, 290745-025: 82801DB (ICH4)
18 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
19 * document number 273599-001, 273645-002: 82801E (C-ICH)
20 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
21 * document number 300641-004, 300884-013: 6300ESB
22 * document number 301473-002, 301474-026: 82801F (ICH6)
23 * document number 313082-001, 313075-006: 631xESB, 632xESB
24 * document number 307013-003, 307014-024: 82801G (ICH7)
25 * document number 322896-001, 322897-001: NM10
26 * document number 313056-003, 313057-017: 82801H (ICH8)
27 * document number 316972-004, 316973-012: 82801I (ICH9)
28 * document number 319973-002, 319974-002: 82801J (ICH10)
29 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
30 * document number 320066-003, 320257-008: EP80597 (IICH)
31 * document number 324645-001, 324646-001: Cougar Point (CPT)
32 * document number TBD : Patsburg (PBG)
33 * document number TBD : DH89xxCC
34 * document number TBD : Panther Point
35 * document number TBD : Lynx Point
36 * document number TBD : Lynx Point-LP
37 */
38
39/*
40 * Includes, defines, variables, module parameters, ...
41 */
42
43/* Module and version information */
44#define DRV_NAME "iTCO_wdt"
45#define DRV_VERSION "1.11"
46
47/* Includes */
48#include <linux/acpi.h> /* For ACPI support */
49#include <linux/bits.h> /* For BIT() */
50#include <linux/module.h> /* For module specific items */
51#include <linux/moduleparam.h> /* For new moduleparam's */
52#include <linux/types.h> /* For standard types (like size_t) */
53#include <linux/errno.h> /* For the -ENODEV/... values */
54#include <linux/kernel.h> /* For printk/panic/... */
55#include <linux/watchdog.h> /* For the watchdog specific items */
56#include <linux/init.h> /* For __init/__exit/... */
57#include <linux/fs.h> /* For file operations */
58#include <linux/platform_device.h> /* For platform_driver framework */
59#include <linux/pci.h> /* For pci functions */
60#include <linux/ioport.h> /* For io-port access */
61#include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
62#include <linux/uaccess.h> /* For copy_to_user/put_user/... */
63#include <linux/io.h> /* For inb/outb/... */
64#include <linux/platform_data/itco_wdt.h>
65#include <linux/mfd/intel_pmc_bxt.h>
66
67#include "iTCO_vendor.h"
68
69/* Address definitions for the TCO */
70/* TCO base address */
71#define TCOBASE(p) ((p)->tco_res->start)
72/* SMI Control and Enable Register */
73#define SMI_EN(p) ((p)->smi_res->start)
74
75#define TCO_RLD(p) (TCOBASE(p) + 0x00) /* TCO Timer Reload/Curr. Value */
76#define TCOv1_TMR(p) (TCOBASE(p) + 0x01) /* TCOv1 Timer Initial Value*/
77#define TCO_DAT_IN(p) (TCOBASE(p) + 0x02) /* TCO Data In Register */
78#define TCO_DAT_OUT(p) (TCOBASE(p) + 0x03) /* TCO Data Out Register */
79#define TCO1_STS(p) (TCOBASE(p) + 0x04) /* TCO1 Status Register */
80#define TCO2_STS(p) (TCOBASE(p) + 0x06) /* TCO2 Status Register */
81#define TCO1_CNT(p) (TCOBASE(p) + 0x08) /* TCO1 Control Register */
82#define TCO2_CNT(p) (TCOBASE(p) + 0x0a) /* TCO2 Control Register */
83#define TCOv2_TMR(p) (TCOBASE(p) + 0x12) /* TCOv2 Timer Initial Value*/
84
85/* internal variables */
86struct iTCO_wdt_private {
87 struct watchdog_device wddev;
88
89 /* TCO version/generation */
90 unsigned int iTCO_version;
91 struct resource *tco_res;
92 struct resource *smi_res;
93 /*
94 * NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2),
95 * or memory-mapped PMC register bit 4 (TCO version 3).
96 */
97 unsigned long __iomem *gcs_pmc;
98 /* the lock for io operations */
99 spinlock_t io_lock;
100 /* the PCI-device */
101 struct pci_dev *pci_dev;
102 /* whether or not the watchdog has been suspended */
103 bool suspended;
104 /* no reboot API private data */
105 void *no_reboot_priv;
106 /* no reboot update function pointer */
107 int (*update_no_reboot_bit)(void *p, bool set);
108};
109
110/* module parameters */
111#define WATCHDOG_TIMEOUT 30 /* 30 sec default heartbeat */
112static int heartbeat = WATCHDOG_TIMEOUT; /* in seconds */
113module_param(heartbeat, int, 0);
114MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
115 "5..76 (TCO v1) or 3..614 (TCO v2), default="
116 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
117
118static bool nowayout = WATCHDOG_NOWAYOUT;
119module_param(nowayout, bool, 0);
120MODULE_PARM_DESC(nowayout,
121 "Watchdog cannot be stopped once started (default="
122 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
123
124static int turn_SMI_watchdog_clear_off = 1;
125module_param(turn_SMI_watchdog_clear_off, int, 0);
126MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
127 "Turn off SMI clearing watchdog (depends on TCO-version)(default=1)");
128
129/*
130 * Some TCO specific functions
131 */
132
133/*
134 * The iTCO v1 and v2's internal timer is stored as ticks which decrement
135 * every 0.6 seconds. v3's internal timer is stored as seconds (some
136 * datasheets incorrectly state 0.6 seconds).
137 */
138static inline unsigned int seconds_to_ticks(struct iTCO_wdt_private *p,
139 int secs)
140{
141 return p->iTCO_version == 3 ? secs : (secs * 10) / 6;
142}
143
144static inline unsigned int ticks_to_seconds(struct iTCO_wdt_private *p,
145 int ticks)
146{
147 return p->iTCO_version == 3 ? ticks : (ticks * 6) / 10;
148}
149
150static inline u32 no_reboot_bit(struct iTCO_wdt_private *p)
151{
152 u32 enable_bit;
153
154 switch (p->iTCO_version) {
155 case 5:
156 case 3:
157 enable_bit = 0x00000010;
158 break;
159 case 2:
160 enable_bit = 0x00000020;
161 break;
162 case 4:
163 case 1:
164 default:
165 enable_bit = 0x00000002;
166 break;
167 }
168
169 return enable_bit;
170}
171
172static int update_no_reboot_bit_def(void *priv, bool set)
173{
174 return 0;
175}
176
177static int update_no_reboot_bit_pci(void *priv, bool set)
178{
179 struct iTCO_wdt_private *p = priv;
180 u32 val32 = 0, newval32 = 0;
181
182 pci_read_config_dword(p->pci_dev, 0xd4, &val32);
183 if (set)
184 val32 |= no_reboot_bit(p);
185 else
186 val32 &= ~no_reboot_bit(p);
187 pci_write_config_dword(p->pci_dev, 0xd4, val32);
188 pci_read_config_dword(p->pci_dev, 0xd4, &newval32);
189
190 /* make sure the update is successful */
191 if (val32 != newval32)
192 return -EIO;
193
194 return 0;
195}
196
197static int update_no_reboot_bit_mem(void *priv, bool set)
198{
199 struct iTCO_wdt_private *p = priv;
200 u32 val32 = 0, newval32 = 0;
201
202 val32 = readl(p->gcs_pmc);
203 if (set)
204 val32 |= no_reboot_bit(p);
205 else
206 val32 &= ~no_reboot_bit(p);
207 writel(val32, p->gcs_pmc);
208 newval32 = readl(p->gcs_pmc);
209
210 /* make sure the update is successful */
211 if (val32 != newval32)
212 return -EIO;
213
214 return 0;
215}
216
217static int update_no_reboot_bit_cnt(void *priv, bool set)
218{
219 struct iTCO_wdt_private *p = priv;
220 u16 val, newval;
221
222 val = inw(TCO1_CNT(p));
223 if (set)
224 val |= BIT(0);
225 else
226 val &= ~BIT(0);
227 outw(val, TCO1_CNT(p));
228 newval = inw(TCO1_CNT(p));
229
230 /* make sure the update is successful */
231 return val != newval ? -EIO : 0;
232}
233
234static int update_no_reboot_bit_pmc(void *priv, bool set)
235{
236 struct intel_pmc_dev *pmc = priv;
237 u32 bits = PMC_CFG_NO_REBOOT_EN;
238 u32 value = set ? bits : 0;
239
240 return intel_pmc_gcr_update(pmc, PMC_GCR_PMC_CFG_REG, bits, value);
241}
242
243static void iTCO_wdt_no_reboot_bit_setup(struct iTCO_wdt_private *p,
244 struct platform_device *pdev,
245 struct itco_wdt_platform_data *pdata)
246{
247 if (pdata->no_reboot_use_pmc) {
248 struct intel_pmc_dev *pmc = dev_get_drvdata(pdev->dev.parent);
249
250 p->update_no_reboot_bit = update_no_reboot_bit_pmc;
251 p->no_reboot_priv = pmc;
252 return;
253 }
254
255 if (p->iTCO_version >= 6)
256 p->update_no_reboot_bit = update_no_reboot_bit_cnt;
257 else if (p->iTCO_version >= 2)
258 p->update_no_reboot_bit = update_no_reboot_bit_mem;
259 else if (p->iTCO_version == 1)
260 p->update_no_reboot_bit = update_no_reboot_bit_pci;
261 else
262 p->update_no_reboot_bit = update_no_reboot_bit_def;
263
264 p->no_reboot_priv = p;
265}
266
267static int iTCO_wdt_start(struct watchdog_device *wd_dev)
268{
269 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
270 unsigned int val;
271
272 spin_lock(&p->io_lock);
273
274 iTCO_vendor_pre_start(p->smi_res, wd_dev->timeout);
275
276 /* disable chipset's NO_REBOOT bit */
277 if (p->update_no_reboot_bit(p->no_reboot_priv, false)) {
278 spin_unlock(&p->io_lock);
279 dev_err(wd_dev->parent, "failed to reset NO_REBOOT flag, reboot disabled by hardware/BIOS\n");
280 return -EIO;
281 }
282
283 /* Force the timer to its reload value by writing to the TCO_RLD
284 register */
285 if (p->iTCO_version >= 2)
286 outw(0x01, TCO_RLD(p));
287 else if (p->iTCO_version == 1)
288 outb(0x01, TCO_RLD(p));
289
290 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
291 val = inw(TCO1_CNT(p));
292 val &= 0xf7ff;
293 outw(val, TCO1_CNT(p));
294 val = inw(TCO1_CNT(p));
295 spin_unlock(&p->io_lock);
296
297 if (val & 0x0800)
298 return -1;
299 return 0;
300}
301
302static int iTCO_wdt_stop(struct watchdog_device *wd_dev)
303{
304 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
305 unsigned int val;
306
307 spin_lock(&p->io_lock);
308
309 iTCO_vendor_pre_stop(p->smi_res);
310
311 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
312 val = inw(TCO1_CNT(p));
313 val |= 0x0800;
314 outw(val, TCO1_CNT(p));
315 val = inw(TCO1_CNT(p));
316
317 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
318 p->update_no_reboot_bit(p->no_reboot_priv, true);
319
320 spin_unlock(&p->io_lock);
321
322 if ((val & 0x0800) == 0)
323 return -1;
324 return 0;
325}
326
327static int iTCO_wdt_ping(struct watchdog_device *wd_dev)
328{
329 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
330
331 spin_lock(&p->io_lock);
332
333 /* Reload the timer by writing to the TCO Timer Counter register */
334 if (p->iTCO_version >= 2) {
335 outw(0x01, TCO_RLD(p));
336 } else if (p->iTCO_version == 1) {
337 /* Reset the timeout status bit so that the timer
338 * needs to count down twice again before rebooting */
339 outw(0x0008, TCO1_STS(p)); /* write 1 to clear bit */
340
341 outb(0x01, TCO_RLD(p));
342 }
343
344 spin_unlock(&p->io_lock);
345 return 0;
346}
347
348static int iTCO_wdt_set_timeout(struct watchdog_device *wd_dev, unsigned int t)
349{
350 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
351 unsigned int val16;
352 unsigned char val8;
353 unsigned int tmrval;
354
355 tmrval = seconds_to_ticks(p, t);
356
357 /* For TCO v1 the timer counts down twice before rebooting */
358 if (p->iTCO_version == 1)
359 tmrval /= 2;
360
361 /* from the specs: */
362 /* "Values of 0h-3h are ignored and should not be attempted" */
363 if (tmrval < 0x04)
364 return -EINVAL;
365 if ((p->iTCO_version >= 2 && tmrval > 0x3ff) ||
366 (p->iTCO_version == 1 && tmrval > 0x03f))
367 return -EINVAL;
368
369 /* Write new heartbeat to watchdog */
370 if (p->iTCO_version >= 2) {
371 spin_lock(&p->io_lock);
372 val16 = inw(TCOv2_TMR(p));
373 val16 &= 0xfc00;
374 val16 |= tmrval;
375 outw(val16, TCOv2_TMR(p));
376 val16 = inw(TCOv2_TMR(p));
377 spin_unlock(&p->io_lock);
378
379 if ((val16 & 0x3ff) != tmrval)
380 return -EINVAL;
381 } else if (p->iTCO_version == 1) {
382 spin_lock(&p->io_lock);
383 val8 = inb(TCOv1_TMR(p));
384 val8 &= 0xc0;
385 val8 |= (tmrval & 0xff);
386 outb(val8, TCOv1_TMR(p));
387 val8 = inb(TCOv1_TMR(p));
388 spin_unlock(&p->io_lock);
389
390 if ((val8 & 0x3f) != tmrval)
391 return -EINVAL;
392 }
393
394 wd_dev->timeout = t;
395 return 0;
396}
397
398static unsigned int iTCO_wdt_get_timeleft(struct watchdog_device *wd_dev)
399{
400 struct iTCO_wdt_private *p = watchdog_get_drvdata(wd_dev);
401 unsigned int val16;
402 unsigned char val8;
403 unsigned int time_left = 0;
404
405 /* read the TCO Timer */
406 if (p->iTCO_version >= 2) {
407 spin_lock(&p->io_lock);
408 val16 = inw(TCO_RLD(p));
409 val16 &= 0x3ff;
410 spin_unlock(&p->io_lock);
411
412 time_left = ticks_to_seconds(p, val16);
413 } else if (p->iTCO_version == 1) {
414 spin_lock(&p->io_lock);
415 val8 = inb(TCO_RLD(p));
416 val8 &= 0x3f;
417 if (!(inw(TCO1_STS(p)) & 0x0008))
418 val8 += (inb(TCOv1_TMR(p)) & 0x3f);
419 spin_unlock(&p->io_lock);
420
421 time_left = ticks_to_seconds(p, val8);
422 }
423 return time_left;
424}
425
426/* Returns true if the watchdog was running */
427static bool iTCO_wdt_set_running(struct iTCO_wdt_private *p)
428{
429 u16 val;
430
431 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled */
432 val = inw(TCO1_CNT(p));
433 if (!(val & BIT(11))) {
434 set_bit(WDOG_HW_RUNNING, &p->wddev.status);
435 return true;
436 }
437 return false;
438}
439
440/*
441 * Kernel Interfaces
442 */
443
444static const struct watchdog_info ident = {
445 .options = WDIOF_SETTIMEOUT |
446 WDIOF_KEEPALIVEPING |
447 WDIOF_MAGICCLOSE,
448 .firmware_version = 0,
449 .identity = DRV_NAME,
450};
451
452static const struct watchdog_ops iTCO_wdt_ops = {
453 .owner = THIS_MODULE,
454 .start = iTCO_wdt_start,
455 .stop = iTCO_wdt_stop,
456 .ping = iTCO_wdt_ping,
457 .set_timeout = iTCO_wdt_set_timeout,
458 .get_timeleft = iTCO_wdt_get_timeleft,
459};
460
461/*
462 * Init & exit routines
463 */
464
465static int iTCO_wdt_probe(struct platform_device *pdev)
466{
467 struct device *dev = &pdev->dev;
468 struct itco_wdt_platform_data *pdata = dev_get_platdata(dev);
469 struct iTCO_wdt_private *p;
470 unsigned long val32;
471 int ret;
472
473 if (!pdata)
474 return -ENODEV;
475
476 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
477 if (!p)
478 return -ENOMEM;
479
480 spin_lock_init(&p->io_lock);
481
482 p->tco_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_TCO);
483 if (!p->tco_res)
484 return -ENODEV;
485
486 p->iTCO_version = pdata->version;
487 p->pci_dev = to_pci_dev(dev->parent);
488
489 p->smi_res = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_IO_SMI);
490 if (p->smi_res) {
491 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
492 if (!devm_request_region(dev, p->smi_res->start,
493 resource_size(p->smi_res),
494 pdev->name)) {
495 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
496 (u64)SMI_EN(p));
497 return -EBUSY;
498 }
499 } else if (iTCO_vendorsupport ||
500 turn_SMI_watchdog_clear_off >= p->iTCO_version) {
501 dev_err(dev, "SMI I/O resource is missing\n");
502 return -ENODEV;
503 }
504
505 iTCO_wdt_no_reboot_bit_setup(p, pdev, pdata);
506
507 /*
508 * Get the Memory-Mapped GCS or PMC register, we need it for the
509 * NO_REBOOT flag (TCO v2 and v3).
510 */
511 if (p->iTCO_version >= 2 && p->iTCO_version < 6 &&
512 !pdata->no_reboot_use_pmc) {
513 p->gcs_pmc = devm_platform_ioremap_resource(pdev, ICH_RES_MEM_GCS_PMC);
514 if (IS_ERR(p->gcs_pmc))
515 return PTR_ERR(p->gcs_pmc);
516 }
517
518 /* Check chipset's NO_REBOOT bit */
519 if (p->update_no_reboot_bit(p->no_reboot_priv, false) &&
520 iTCO_vendor_check_noreboot_on()) {
521 dev_info(dev, "unable to reset NO_REBOOT flag, device disabled by hardware/BIOS\n");
522 return -ENODEV; /* Cannot reset NO_REBOOT bit */
523 }
524
525 if (turn_SMI_watchdog_clear_off >= p->iTCO_version) {
526 /*
527 * Bit 13: TCO_EN -> 0
528 * Disables TCO logic generating an SMI#
529 */
530 val32 = inl(SMI_EN(p));
531 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
532 outl(val32, SMI_EN(p));
533 }
534
535 if (!devm_request_region(dev, p->tco_res->start,
536 resource_size(p->tco_res),
537 pdev->name)) {
538 dev_err(dev, "I/O address 0x%04llx already in use, device disabled\n",
539 (u64)TCOBASE(p));
540 return -EBUSY;
541 }
542
543 dev_info(dev, "Found a %s TCO device (Version=%d, TCOBASE=0x%04llx)\n",
544 pdata->name, pdata->version, (u64)TCOBASE(p));
545
546 /* Clear out the (probably old) status */
547 switch (p->iTCO_version) {
548 case 6:
549 case 5:
550 case 4:
551 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
552 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
553 break;
554 case 3:
555 outl(0x20008, TCO1_STS(p));
556 break;
557 case 2:
558 case 1:
559 default:
560 outw(0x0008, TCO1_STS(p)); /* Clear the Time Out Status bit */
561 outw(0x0002, TCO2_STS(p)); /* Clear SECOND_TO_STS bit */
562 outw(0x0004, TCO2_STS(p)); /* Clear BOOT_STS bit */
563 break;
564 }
565
566 p->wddev.info = &ident,
567 p->wddev.ops = &iTCO_wdt_ops,
568 p->wddev.bootstatus = 0;
569 p->wddev.timeout = WATCHDOG_TIMEOUT;
570 watchdog_set_nowayout(&p->wddev, nowayout);
571 p->wddev.parent = dev;
572
573 watchdog_set_drvdata(&p->wddev, p);
574 platform_set_drvdata(pdev, p);
575
576 if (!iTCO_wdt_set_running(p)) {
577 /*
578 * If the watchdog was not running set NO_REBOOT now to
579 * prevent later reboots.
580 */
581 p->update_no_reboot_bit(p->no_reboot_priv, true);
582 }
583
584 /* Check that the heartbeat value is within it's range;
585 if not reset to the default */
586 if (iTCO_wdt_set_timeout(&p->wddev, heartbeat)) {
587 iTCO_wdt_set_timeout(&p->wddev, WATCHDOG_TIMEOUT);
588 dev_info(dev, "timeout value out of range, using %d\n",
589 WATCHDOG_TIMEOUT);
590 }
591
592 watchdog_stop_on_reboot(&p->wddev);
593 watchdog_stop_on_unregister(&p->wddev);
594 ret = devm_watchdog_register_device(dev, &p->wddev);
595 if (ret != 0) {
596 dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
597 return ret;
598 }
599
600 dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
601 heartbeat, nowayout);
602
603 return 0;
604}
605
606/*
607 * Suspend-to-idle requires this, because it stops the ticks and timekeeping, so
608 * the watchdog cannot be pinged while in that state. In ACPI sleep states the
609 * watchdog is stopped by the platform firmware.
610 */
611
612#ifdef CONFIG_ACPI
613static inline bool __maybe_unused need_suspend(void)
614{
615 return acpi_target_system_state() == ACPI_STATE_S0;
616}
617#else
618static inline bool __maybe_unused need_suspend(void) { return true; }
619#endif
620
621static int __maybe_unused iTCO_wdt_suspend_noirq(struct device *dev)
622{
623 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
624 int ret = 0;
625
626 p->suspended = false;
627 if (watchdog_active(&p->wddev) && need_suspend()) {
628 ret = iTCO_wdt_stop(&p->wddev);
629 if (!ret)
630 p->suspended = true;
631 }
632 return ret;
633}
634
635static int __maybe_unused iTCO_wdt_resume_noirq(struct device *dev)
636{
637 struct iTCO_wdt_private *p = dev_get_drvdata(dev);
638
639 if (p->suspended)
640 iTCO_wdt_start(&p->wddev);
641
642 return 0;
643}
644
645static const struct dev_pm_ops iTCO_wdt_pm = {
646 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(iTCO_wdt_suspend_noirq,
647 iTCO_wdt_resume_noirq)
648};
649
650static struct platform_driver iTCO_wdt_driver = {
651 .probe = iTCO_wdt_probe,
652 .driver = {
653 .name = DRV_NAME,
654 .pm = &iTCO_wdt_pm,
655 },
656};
657
658module_platform_driver(iTCO_wdt_driver);
659
660MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
661MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
662MODULE_VERSION(DRV_VERSION);
663MODULE_LICENSE("GPL");
664MODULE_ALIAS("platform:" DRV_NAME);