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1/*
2 * Driver for SA11x0 serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/ioport.h>
29#include <linux/init.h>
30#include <linux/console.h>
31#include <linux/sysrq.h>
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/io.h>
38
39#include <asm/irq.h>
40#include <mach/hardware.h>
41#include <asm/mach/serial_sa1100.h>
42
43/* We've been assigned a range on the "Low-density serial ports" major */
44#define SERIAL_SA1100_MAJOR 204
45#define MINOR_START 5
46
47#define NR_PORTS 3
48
49#define SA1100_ISR_PASS_LIMIT 256
50
51/*
52 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
53 */
54#define SM_TO_UTSR0(x) ((x) & 0xff)
55#define SM_TO_UTSR1(x) ((x) >> 8)
56#define UTSR0_TO_SM(x) ((x))
57#define UTSR1_TO_SM(x) ((x) << 8)
58
59#define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
60#define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
61#define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
62#define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
63#define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
64#define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
65#define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
66
67#define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
68#define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
69#define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
70#define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
71#define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
72#define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
73#define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
74
75/*
76 * This is the size of our serial port register set.
77 */
78#define UART_PORT_SIZE 0x24
79
80/*
81 * This determines how often we check the modem status signals
82 * for any change. They generally aren't connected to an IRQ
83 * so we have to poll them. We also check immediately before
84 * filling the TX fifo incase CTS has been dropped.
85 */
86#define MCTRL_TIMEOUT (250*HZ/1000)
87
88struct sa1100_port {
89 struct uart_port port;
90 struct timer_list timer;
91 unsigned int old_status;
92};
93
94/*
95 * Handle any change of modem status signal since we were last called.
96 */
97static void sa1100_mctrl_check(struct sa1100_port *sport)
98{
99 unsigned int status, changed;
100
101 status = sport->port.ops->get_mctrl(&sport->port);
102 changed = status ^ sport->old_status;
103
104 if (changed == 0)
105 return;
106
107 sport->old_status = status;
108
109 if (changed & TIOCM_RI)
110 sport->port.icount.rng++;
111 if (changed & TIOCM_DSR)
112 sport->port.icount.dsr++;
113 if (changed & TIOCM_CAR)
114 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
115 if (changed & TIOCM_CTS)
116 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
117
118 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
119}
120
121/*
122 * This is our per-port timeout handler, for checking the
123 * modem status signals.
124 */
125static void sa1100_timeout(unsigned long data)
126{
127 struct sa1100_port *sport = (struct sa1100_port *)data;
128 unsigned long flags;
129
130 if (sport->port.state) {
131 spin_lock_irqsave(&sport->port.lock, flags);
132 sa1100_mctrl_check(sport);
133 spin_unlock_irqrestore(&sport->port.lock, flags);
134
135 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
136 }
137}
138
139/*
140 * interrupts disabled on entry
141 */
142static void sa1100_stop_tx(struct uart_port *port)
143{
144 struct sa1100_port *sport = (struct sa1100_port *)port;
145 u32 utcr3;
146
147 utcr3 = UART_GET_UTCR3(sport);
148 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
149 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
150}
151
152/*
153 * port locked and interrupts disabled
154 */
155static void sa1100_start_tx(struct uart_port *port)
156{
157 struct sa1100_port *sport = (struct sa1100_port *)port;
158 u32 utcr3;
159
160 utcr3 = UART_GET_UTCR3(sport);
161 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
162 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
163}
164
165/*
166 * Interrupts enabled
167 */
168static void sa1100_stop_rx(struct uart_port *port)
169{
170 struct sa1100_port *sport = (struct sa1100_port *)port;
171 u32 utcr3;
172
173 utcr3 = UART_GET_UTCR3(sport);
174 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
175}
176
177/*
178 * Set the modem control timer to fire immediately.
179 */
180static void sa1100_enable_ms(struct uart_port *port)
181{
182 struct sa1100_port *sport = (struct sa1100_port *)port;
183
184 mod_timer(&sport->timer, jiffies);
185}
186
187static void
188sa1100_rx_chars(struct sa1100_port *sport)
189{
190 struct tty_struct *tty = sport->port.state->port.tty;
191 unsigned int status, ch, flg;
192
193 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
194 UTSR0_TO_SM(UART_GET_UTSR0(sport));
195 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
196 ch = UART_GET_CHAR(sport);
197
198 sport->port.icount.rx++;
199
200 flg = TTY_NORMAL;
201
202 /*
203 * note that the error handling code is
204 * out of the main execution path
205 */
206 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
207 if (status & UTSR1_TO_SM(UTSR1_PRE))
208 sport->port.icount.parity++;
209 else if (status & UTSR1_TO_SM(UTSR1_FRE))
210 sport->port.icount.frame++;
211 if (status & UTSR1_TO_SM(UTSR1_ROR))
212 sport->port.icount.overrun++;
213
214 status &= sport->port.read_status_mask;
215
216 if (status & UTSR1_TO_SM(UTSR1_PRE))
217 flg = TTY_PARITY;
218 else if (status & UTSR1_TO_SM(UTSR1_FRE))
219 flg = TTY_FRAME;
220
221#ifdef SUPPORT_SYSRQ
222 sport->port.sysrq = 0;
223#endif
224 }
225
226 if (uart_handle_sysrq_char(&sport->port, ch))
227 goto ignore_char;
228
229 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
230
231 ignore_char:
232 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
233 UTSR0_TO_SM(UART_GET_UTSR0(sport));
234 }
235 tty_flip_buffer_push(tty);
236}
237
238static void sa1100_tx_chars(struct sa1100_port *sport)
239{
240 struct circ_buf *xmit = &sport->port.state->xmit;
241
242 if (sport->port.x_char) {
243 UART_PUT_CHAR(sport, sport->port.x_char);
244 sport->port.icount.tx++;
245 sport->port.x_char = 0;
246 return;
247 }
248
249 /*
250 * Check the modem control lines before
251 * transmitting anything.
252 */
253 sa1100_mctrl_check(sport);
254
255 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
256 sa1100_stop_tx(&sport->port);
257 return;
258 }
259
260 /*
261 * Tried using FIFO (not checking TNF) for fifo fill:
262 * still had the '4 bytes repeated' problem.
263 */
264 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
265 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
266 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
267 sport->port.icount.tx++;
268 if (uart_circ_empty(xmit))
269 break;
270 }
271
272 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
273 uart_write_wakeup(&sport->port);
274
275 if (uart_circ_empty(xmit))
276 sa1100_stop_tx(&sport->port);
277}
278
279static irqreturn_t sa1100_int(int irq, void *dev_id)
280{
281 struct sa1100_port *sport = dev_id;
282 unsigned int status, pass_counter = 0;
283
284 spin_lock(&sport->port.lock);
285 status = UART_GET_UTSR0(sport);
286 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
287 do {
288 if (status & (UTSR0_RFS | UTSR0_RID)) {
289 /* Clear the receiver idle bit, if set */
290 if (status & UTSR0_RID)
291 UART_PUT_UTSR0(sport, UTSR0_RID);
292 sa1100_rx_chars(sport);
293 }
294
295 /* Clear the relevant break bits */
296 if (status & (UTSR0_RBB | UTSR0_REB))
297 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
298
299 if (status & UTSR0_RBB)
300 sport->port.icount.brk++;
301
302 if (status & UTSR0_REB)
303 uart_handle_break(&sport->port);
304
305 if (status & UTSR0_TFS)
306 sa1100_tx_chars(sport);
307 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
308 break;
309 status = UART_GET_UTSR0(sport);
310 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
311 ~UTSR0_TFS;
312 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
313 spin_unlock(&sport->port.lock);
314
315 return IRQ_HANDLED;
316}
317
318/*
319 * Return TIOCSER_TEMT when transmitter is not busy.
320 */
321static unsigned int sa1100_tx_empty(struct uart_port *port)
322{
323 struct sa1100_port *sport = (struct sa1100_port *)port;
324
325 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
326}
327
328static unsigned int sa1100_get_mctrl(struct uart_port *port)
329{
330 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
331}
332
333static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
334{
335}
336
337/*
338 * Interrupts always disabled.
339 */
340static void sa1100_break_ctl(struct uart_port *port, int break_state)
341{
342 struct sa1100_port *sport = (struct sa1100_port *)port;
343 unsigned long flags;
344 unsigned int utcr3;
345
346 spin_lock_irqsave(&sport->port.lock, flags);
347 utcr3 = UART_GET_UTCR3(sport);
348 if (break_state == -1)
349 utcr3 |= UTCR3_BRK;
350 else
351 utcr3 &= ~UTCR3_BRK;
352 UART_PUT_UTCR3(sport, utcr3);
353 spin_unlock_irqrestore(&sport->port.lock, flags);
354}
355
356static int sa1100_startup(struct uart_port *port)
357{
358 struct sa1100_port *sport = (struct sa1100_port *)port;
359 int retval;
360
361 /*
362 * Allocate the IRQ
363 */
364 retval = request_irq(sport->port.irq, sa1100_int, 0,
365 "sa11x0-uart", sport);
366 if (retval)
367 return retval;
368
369 /*
370 * Finally, clear and enable interrupts
371 */
372 UART_PUT_UTSR0(sport, -1);
373 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
374
375 /*
376 * Enable modem status interrupts
377 */
378 spin_lock_irq(&sport->port.lock);
379 sa1100_enable_ms(&sport->port);
380 spin_unlock_irq(&sport->port.lock);
381
382 return 0;
383}
384
385static void sa1100_shutdown(struct uart_port *port)
386{
387 struct sa1100_port *sport = (struct sa1100_port *)port;
388
389 /*
390 * Stop our timer.
391 */
392 del_timer_sync(&sport->timer);
393
394 /*
395 * Free the interrupt
396 */
397 free_irq(sport->port.irq, sport);
398
399 /*
400 * Disable all interrupts, port and break condition.
401 */
402 UART_PUT_UTCR3(sport, 0);
403}
404
405static void
406sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
407 struct ktermios *old)
408{
409 struct sa1100_port *sport = (struct sa1100_port *)port;
410 unsigned long flags;
411 unsigned int utcr0, old_utcr3, baud, quot;
412 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
413
414 /*
415 * We only support CS7 and CS8.
416 */
417 while ((termios->c_cflag & CSIZE) != CS7 &&
418 (termios->c_cflag & CSIZE) != CS8) {
419 termios->c_cflag &= ~CSIZE;
420 termios->c_cflag |= old_csize;
421 old_csize = CS8;
422 }
423
424 if ((termios->c_cflag & CSIZE) == CS8)
425 utcr0 = UTCR0_DSS;
426 else
427 utcr0 = 0;
428
429 if (termios->c_cflag & CSTOPB)
430 utcr0 |= UTCR0_SBS;
431 if (termios->c_cflag & PARENB) {
432 utcr0 |= UTCR0_PE;
433 if (!(termios->c_cflag & PARODD))
434 utcr0 |= UTCR0_OES;
435 }
436
437 /*
438 * Ask the core to calculate the divisor for us.
439 */
440 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
441 quot = uart_get_divisor(port, baud);
442
443 spin_lock_irqsave(&sport->port.lock, flags);
444
445 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
446 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
447 if (termios->c_iflag & INPCK)
448 sport->port.read_status_mask |=
449 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
450 if (termios->c_iflag & (BRKINT | PARMRK))
451 sport->port.read_status_mask |=
452 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
453
454 /*
455 * Characters to ignore
456 */
457 sport->port.ignore_status_mask = 0;
458 if (termios->c_iflag & IGNPAR)
459 sport->port.ignore_status_mask |=
460 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
461 if (termios->c_iflag & IGNBRK) {
462 sport->port.ignore_status_mask |=
463 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
464 /*
465 * If we're ignoring parity and break indicators,
466 * ignore overruns too (for real raw support).
467 */
468 if (termios->c_iflag & IGNPAR)
469 sport->port.ignore_status_mask |=
470 UTSR1_TO_SM(UTSR1_ROR);
471 }
472
473 del_timer_sync(&sport->timer);
474
475 /*
476 * Update the per-port timeout.
477 */
478 uart_update_timeout(port, termios->c_cflag, baud);
479
480 /*
481 * disable interrupts and drain transmitter
482 */
483 old_utcr3 = UART_GET_UTCR3(sport);
484 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
485
486 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
487 barrier();
488
489 /* then, disable everything */
490 UART_PUT_UTCR3(sport, 0);
491
492 /* set the parity, stop bits and data size */
493 UART_PUT_UTCR0(sport, utcr0);
494
495 /* set the baud rate */
496 quot -= 1;
497 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
498 UART_PUT_UTCR2(sport, (quot & 0xff));
499
500 UART_PUT_UTSR0(sport, -1);
501
502 UART_PUT_UTCR3(sport, old_utcr3);
503
504 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
505 sa1100_enable_ms(&sport->port);
506
507 spin_unlock_irqrestore(&sport->port.lock, flags);
508}
509
510static const char *sa1100_type(struct uart_port *port)
511{
512 struct sa1100_port *sport = (struct sa1100_port *)port;
513
514 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
515}
516
517/*
518 * Release the memory region(s) being used by 'port'.
519 */
520static void sa1100_release_port(struct uart_port *port)
521{
522 struct sa1100_port *sport = (struct sa1100_port *)port;
523
524 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
525}
526
527/*
528 * Request the memory region(s) being used by 'port'.
529 */
530static int sa1100_request_port(struct uart_port *port)
531{
532 struct sa1100_port *sport = (struct sa1100_port *)port;
533
534 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
535 "sa11x0-uart") != NULL ? 0 : -EBUSY;
536}
537
538/*
539 * Configure/autoconfigure the port.
540 */
541static void sa1100_config_port(struct uart_port *port, int flags)
542{
543 struct sa1100_port *sport = (struct sa1100_port *)port;
544
545 if (flags & UART_CONFIG_TYPE &&
546 sa1100_request_port(&sport->port) == 0)
547 sport->port.type = PORT_SA1100;
548}
549
550/*
551 * Verify the new serial_struct (for TIOCSSERIAL).
552 * The only change we allow are to the flags and type, and
553 * even then only between PORT_SA1100 and PORT_UNKNOWN
554 */
555static int
556sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
557{
558 struct sa1100_port *sport = (struct sa1100_port *)port;
559 int ret = 0;
560
561 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
562 ret = -EINVAL;
563 if (sport->port.irq != ser->irq)
564 ret = -EINVAL;
565 if (ser->io_type != SERIAL_IO_MEM)
566 ret = -EINVAL;
567 if (sport->port.uartclk / 16 != ser->baud_base)
568 ret = -EINVAL;
569 if ((void *)sport->port.mapbase != ser->iomem_base)
570 ret = -EINVAL;
571 if (sport->port.iobase != ser->port)
572 ret = -EINVAL;
573 if (ser->hub6 != 0)
574 ret = -EINVAL;
575 return ret;
576}
577
578static struct uart_ops sa1100_pops = {
579 .tx_empty = sa1100_tx_empty,
580 .set_mctrl = sa1100_set_mctrl,
581 .get_mctrl = sa1100_get_mctrl,
582 .stop_tx = sa1100_stop_tx,
583 .start_tx = sa1100_start_tx,
584 .stop_rx = sa1100_stop_rx,
585 .enable_ms = sa1100_enable_ms,
586 .break_ctl = sa1100_break_ctl,
587 .startup = sa1100_startup,
588 .shutdown = sa1100_shutdown,
589 .set_termios = sa1100_set_termios,
590 .type = sa1100_type,
591 .release_port = sa1100_release_port,
592 .request_port = sa1100_request_port,
593 .config_port = sa1100_config_port,
594 .verify_port = sa1100_verify_port,
595};
596
597static struct sa1100_port sa1100_ports[NR_PORTS];
598
599/*
600 * Setup the SA1100 serial ports. Note that we don't include the IrDA
601 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
602 *
603 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
604 * Which serial port this ends up being depends on the machine you're
605 * running this kernel on. I'm not convinced that this is a good idea,
606 * but that's the way it traditionally works.
607 *
608 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
609 * used here.
610 */
611static void __init sa1100_init_ports(void)
612{
613 static int first = 1;
614 int i;
615
616 if (!first)
617 return;
618 first = 0;
619
620 for (i = 0; i < NR_PORTS; i++) {
621 sa1100_ports[i].port.uartclk = 3686400;
622 sa1100_ports[i].port.ops = &sa1100_pops;
623 sa1100_ports[i].port.fifosize = 8;
624 sa1100_ports[i].port.line = i;
625 sa1100_ports[i].port.iotype = UPIO_MEM;
626 init_timer(&sa1100_ports[i].timer);
627 sa1100_ports[i].timer.function = sa1100_timeout;
628 sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
629 }
630
631 /*
632 * make transmit lines outputs, so that when the port
633 * is closed, the output is in the MARK state.
634 */
635 PPDR |= PPC_TXD1 | PPC_TXD3;
636 PPSR |= PPC_TXD1 | PPC_TXD3;
637}
638
639void __devinit sa1100_register_uart_fns(struct sa1100_port_fns *fns)
640{
641 if (fns->get_mctrl)
642 sa1100_pops.get_mctrl = fns->get_mctrl;
643 if (fns->set_mctrl)
644 sa1100_pops.set_mctrl = fns->set_mctrl;
645
646 sa1100_pops.pm = fns->pm;
647 sa1100_pops.set_wake = fns->set_wake;
648}
649
650void __init sa1100_register_uart(int idx, int port)
651{
652 if (idx >= NR_PORTS) {
653 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
654 return;
655 }
656
657 switch (port) {
658 case 1:
659 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
660 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
661 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
662 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
663 break;
664
665 case 2:
666 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
667 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
668 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
669 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
670 break;
671
672 case 3:
673 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
674 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
675 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
676 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
677 break;
678
679 default:
680 printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
681 }
682}
683
684
685#ifdef CONFIG_SERIAL_SA1100_CONSOLE
686static void sa1100_console_putchar(struct uart_port *port, int ch)
687{
688 struct sa1100_port *sport = (struct sa1100_port *)port;
689
690 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
691 barrier();
692 UART_PUT_CHAR(sport, ch);
693}
694
695/*
696 * Interrupts are disabled on entering
697 */
698static void
699sa1100_console_write(struct console *co, const char *s, unsigned int count)
700{
701 struct sa1100_port *sport = &sa1100_ports[co->index];
702 unsigned int old_utcr3, status;
703
704 /*
705 * First, save UTCR3 and then disable interrupts
706 */
707 old_utcr3 = UART_GET_UTCR3(sport);
708 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
709 UTCR3_TXE);
710
711 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
712
713 /*
714 * Finally, wait for transmitter to become empty
715 * and restore UTCR3
716 */
717 do {
718 status = UART_GET_UTSR1(sport);
719 } while (status & UTSR1_TBY);
720 UART_PUT_UTCR3(sport, old_utcr3);
721}
722
723/*
724 * If the port was already initialised (eg, by a boot loader),
725 * try to determine the current setup.
726 */
727static void __init
728sa1100_console_get_options(struct sa1100_port *sport, int *baud,
729 int *parity, int *bits)
730{
731 unsigned int utcr3;
732
733 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
734 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
735 /* ok, the port was enabled */
736 unsigned int utcr0, quot;
737
738 utcr0 = UART_GET_UTCR0(sport);
739
740 *parity = 'n';
741 if (utcr0 & UTCR0_PE) {
742 if (utcr0 & UTCR0_OES)
743 *parity = 'e';
744 else
745 *parity = 'o';
746 }
747
748 if (utcr0 & UTCR0_DSS)
749 *bits = 8;
750 else
751 *bits = 7;
752
753 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
754 quot &= 0xfff;
755 *baud = sport->port.uartclk / (16 * (quot + 1));
756 }
757}
758
759static int __init
760sa1100_console_setup(struct console *co, char *options)
761{
762 struct sa1100_port *sport;
763 int baud = 9600;
764 int bits = 8;
765 int parity = 'n';
766 int flow = 'n';
767
768 /*
769 * Check whether an invalid uart number has been specified, and
770 * if so, search for the first available port that does have
771 * console support.
772 */
773 if (co->index == -1 || co->index >= NR_PORTS)
774 co->index = 0;
775 sport = &sa1100_ports[co->index];
776
777 if (options)
778 uart_parse_options(options, &baud, &parity, &bits, &flow);
779 else
780 sa1100_console_get_options(sport, &baud, &parity, &bits);
781
782 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
783}
784
785static struct uart_driver sa1100_reg;
786static struct console sa1100_console = {
787 .name = "ttySA",
788 .write = sa1100_console_write,
789 .device = uart_console_device,
790 .setup = sa1100_console_setup,
791 .flags = CON_PRINTBUFFER,
792 .index = -1,
793 .data = &sa1100_reg,
794};
795
796static int __init sa1100_rs_console_init(void)
797{
798 sa1100_init_ports();
799 register_console(&sa1100_console);
800 return 0;
801}
802console_initcall(sa1100_rs_console_init);
803
804#define SA1100_CONSOLE &sa1100_console
805#else
806#define SA1100_CONSOLE NULL
807#endif
808
809static struct uart_driver sa1100_reg = {
810 .owner = THIS_MODULE,
811 .driver_name = "ttySA",
812 .dev_name = "ttySA",
813 .major = SERIAL_SA1100_MAJOR,
814 .minor = MINOR_START,
815 .nr = NR_PORTS,
816 .cons = SA1100_CONSOLE,
817};
818
819static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
820{
821 struct sa1100_port *sport = platform_get_drvdata(dev);
822
823 if (sport)
824 uart_suspend_port(&sa1100_reg, &sport->port);
825
826 return 0;
827}
828
829static int sa1100_serial_resume(struct platform_device *dev)
830{
831 struct sa1100_port *sport = platform_get_drvdata(dev);
832
833 if (sport)
834 uart_resume_port(&sa1100_reg, &sport->port);
835
836 return 0;
837}
838
839static int sa1100_serial_probe(struct platform_device *dev)
840{
841 struct resource *res = dev->resource;
842 int i;
843
844 for (i = 0; i < dev->num_resources; i++, res++)
845 if (res->flags & IORESOURCE_MEM)
846 break;
847
848 if (i < dev->num_resources) {
849 for (i = 0; i < NR_PORTS; i++) {
850 if (sa1100_ports[i].port.mapbase != res->start)
851 continue;
852
853 sa1100_ports[i].port.dev = &dev->dev;
854 uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
855 platform_set_drvdata(dev, &sa1100_ports[i]);
856 break;
857 }
858 }
859
860 return 0;
861}
862
863static int sa1100_serial_remove(struct platform_device *pdev)
864{
865 struct sa1100_port *sport = platform_get_drvdata(pdev);
866
867 platform_set_drvdata(pdev, NULL);
868
869 if (sport)
870 uart_remove_one_port(&sa1100_reg, &sport->port);
871
872 return 0;
873}
874
875static struct platform_driver sa11x0_serial_driver = {
876 .probe = sa1100_serial_probe,
877 .remove = sa1100_serial_remove,
878 .suspend = sa1100_serial_suspend,
879 .resume = sa1100_serial_resume,
880 .driver = {
881 .name = "sa11x0-uart",
882 .owner = THIS_MODULE,
883 },
884};
885
886static int __init sa1100_serial_init(void)
887{
888 int ret;
889
890 printk(KERN_INFO "Serial: SA11x0 driver\n");
891
892 sa1100_init_ports();
893
894 ret = uart_register_driver(&sa1100_reg);
895 if (ret == 0) {
896 ret = platform_driver_register(&sa11x0_serial_driver);
897 if (ret)
898 uart_unregister_driver(&sa1100_reg);
899 }
900 return ret;
901}
902
903static void __exit sa1100_serial_exit(void)
904{
905 platform_driver_unregister(&sa11x0_serial_driver);
906 uart_unregister_driver(&sa1100_reg);
907}
908
909module_init(sa1100_serial_init);
910module_exit(sa1100_serial_exit);
911
912MODULE_AUTHOR("Deep Blue Solutions Ltd");
913MODULE_DESCRIPTION("SA1100 generic serial port driver");
914MODULE_LICENSE("GPL");
915MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
916MODULE_ALIAS("platform:sa11x0-uart");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for SA11x0 serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 */
9
10#include <linux/module.h>
11#include <linux/ioport.h>
12#include <linux/init.h>
13#include <linux/console.h>
14#include <linux/sysrq.h>
15#include <linux/platform_data/sa11x0-serial.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/io.h>
22
23#include <asm/irq.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26
27#include "serial_mctrl_gpio.h"
28
29/* We've been assigned a range on the "Low-density serial ports" major */
30#define SERIAL_SA1100_MAJOR 204
31#define MINOR_START 5
32
33#define NR_PORTS 3
34
35#define SA1100_ISR_PASS_LIMIT 256
36
37/*
38 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
39 */
40#define SM_TO_UTSR0(x) ((x) & 0xff)
41#define SM_TO_UTSR1(x) ((x) >> 8)
42#define UTSR0_TO_SM(x) ((x))
43#define UTSR1_TO_SM(x) ((x) << 8)
44
45#define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
46#define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
47#define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
48#define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
49#define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
50#define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
51#define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
52
53#define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
54#define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
55#define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
56#define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
57#define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
58#define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
59#define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
60
61/*
62 * This is the size of our serial port register set.
63 */
64#define UART_PORT_SIZE 0x24
65
66/*
67 * This determines how often we check the modem status signals
68 * for any change. They generally aren't connected to an IRQ
69 * so we have to poll them. We also check immediately before
70 * filling the TX fifo incase CTS has been dropped.
71 */
72#define MCTRL_TIMEOUT (250*HZ/1000)
73
74struct sa1100_port {
75 struct uart_port port;
76 struct timer_list timer;
77 unsigned int old_status;
78 struct mctrl_gpios *gpios;
79};
80
81/*
82 * Handle any change of modem status signal since we were last called.
83 */
84static void sa1100_mctrl_check(struct sa1100_port *sport)
85{
86 unsigned int status, changed;
87
88 status = sport->port.ops->get_mctrl(&sport->port);
89 changed = status ^ sport->old_status;
90
91 if (changed == 0)
92 return;
93
94 sport->old_status = status;
95
96 if (changed & TIOCM_RI)
97 sport->port.icount.rng++;
98 if (changed & TIOCM_DSR)
99 sport->port.icount.dsr++;
100 if (changed & TIOCM_CAR)
101 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
102 if (changed & TIOCM_CTS)
103 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
104
105 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
106}
107
108/*
109 * This is our per-port timeout handler, for checking the
110 * modem status signals.
111 */
112static void sa1100_timeout(struct timer_list *t)
113{
114 struct sa1100_port *sport = from_timer(sport, t, timer);
115 unsigned long flags;
116
117 if (sport->port.state) {
118 spin_lock_irqsave(&sport->port.lock, flags);
119 sa1100_mctrl_check(sport);
120 spin_unlock_irqrestore(&sport->port.lock, flags);
121
122 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
123 }
124}
125
126/*
127 * interrupts disabled on entry
128 */
129static void sa1100_stop_tx(struct uart_port *port)
130{
131 struct sa1100_port *sport =
132 container_of(port, struct sa1100_port, port);
133 u32 utcr3;
134
135 utcr3 = UART_GET_UTCR3(sport);
136 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
137 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
138}
139
140/*
141 * port locked and interrupts disabled
142 */
143static void sa1100_start_tx(struct uart_port *port)
144{
145 struct sa1100_port *sport =
146 container_of(port, struct sa1100_port, port);
147 u32 utcr3;
148
149 utcr3 = UART_GET_UTCR3(sport);
150 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
151 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
152}
153
154/*
155 * Interrupts enabled
156 */
157static void sa1100_stop_rx(struct uart_port *port)
158{
159 struct sa1100_port *sport =
160 container_of(port, struct sa1100_port, port);
161 u32 utcr3;
162
163 utcr3 = UART_GET_UTCR3(sport);
164 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
165}
166
167/*
168 * Set the modem control timer to fire immediately.
169 */
170static void sa1100_enable_ms(struct uart_port *port)
171{
172 struct sa1100_port *sport =
173 container_of(port, struct sa1100_port, port);
174
175 mod_timer(&sport->timer, jiffies);
176
177 mctrl_gpio_enable_ms(sport->gpios);
178}
179
180static void
181sa1100_rx_chars(struct sa1100_port *sport)
182{
183 unsigned int status, ch, flg;
184
185 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
186 UTSR0_TO_SM(UART_GET_UTSR0(sport));
187 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
188 ch = UART_GET_CHAR(sport);
189
190 sport->port.icount.rx++;
191
192 flg = TTY_NORMAL;
193
194 /*
195 * note that the error handling code is
196 * out of the main execution path
197 */
198 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
199 if (status & UTSR1_TO_SM(UTSR1_PRE))
200 sport->port.icount.parity++;
201 else if (status & UTSR1_TO_SM(UTSR1_FRE))
202 sport->port.icount.frame++;
203 if (status & UTSR1_TO_SM(UTSR1_ROR))
204 sport->port.icount.overrun++;
205
206 status &= sport->port.read_status_mask;
207
208 if (status & UTSR1_TO_SM(UTSR1_PRE))
209 flg = TTY_PARITY;
210 else if (status & UTSR1_TO_SM(UTSR1_FRE))
211 flg = TTY_FRAME;
212
213 sport->port.sysrq = 0;
214 }
215
216 if (uart_handle_sysrq_char(&sport->port, ch))
217 goto ignore_char;
218
219 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
220
221 ignore_char:
222 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
223 UTSR0_TO_SM(UART_GET_UTSR0(sport));
224 }
225
226 tty_flip_buffer_push(&sport->port.state->port);
227}
228
229static void sa1100_tx_chars(struct sa1100_port *sport)
230{
231 u8 ch;
232
233 /*
234 * Check the modem control lines before
235 * transmitting anything.
236 */
237 sa1100_mctrl_check(sport);
238
239 uart_port_tx(&sport->port, ch,
240 UART_GET_UTSR1(sport) & UTSR1_TNF,
241 UART_PUT_CHAR(sport, ch));
242}
243
244static irqreturn_t sa1100_int(int irq, void *dev_id)
245{
246 struct sa1100_port *sport = dev_id;
247 unsigned int status, pass_counter = 0;
248
249 spin_lock(&sport->port.lock);
250 status = UART_GET_UTSR0(sport);
251 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
252 do {
253 if (status & (UTSR0_RFS | UTSR0_RID)) {
254 /* Clear the receiver idle bit, if set */
255 if (status & UTSR0_RID)
256 UART_PUT_UTSR0(sport, UTSR0_RID);
257 sa1100_rx_chars(sport);
258 }
259
260 /* Clear the relevant break bits */
261 if (status & (UTSR0_RBB | UTSR0_REB))
262 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
263
264 if (status & UTSR0_RBB)
265 sport->port.icount.brk++;
266
267 if (status & UTSR0_REB)
268 uart_handle_break(&sport->port);
269
270 if (status & UTSR0_TFS)
271 sa1100_tx_chars(sport);
272 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
273 break;
274 status = UART_GET_UTSR0(sport);
275 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
276 ~UTSR0_TFS;
277 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
278 spin_unlock(&sport->port.lock);
279
280 return IRQ_HANDLED;
281}
282
283/*
284 * Return TIOCSER_TEMT when transmitter is not busy.
285 */
286static unsigned int sa1100_tx_empty(struct uart_port *port)
287{
288 struct sa1100_port *sport =
289 container_of(port, struct sa1100_port, port);
290
291 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
292}
293
294static unsigned int sa1100_get_mctrl(struct uart_port *port)
295{
296 struct sa1100_port *sport =
297 container_of(port, struct sa1100_port, port);
298 int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
299
300 mctrl_gpio_get(sport->gpios, &ret);
301
302 return ret;
303}
304
305static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
306{
307 struct sa1100_port *sport =
308 container_of(port, struct sa1100_port, port);
309
310 mctrl_gpio_set(sport->gpios, mctrl);
311}
312
313/*
314 * Interrupts always disabled.
315 */
316static void sa1100_break_ctl(struct uart_port *port, int break_state)
317{
318 struct sa1100_port *sport =
319 container_of(port, struct sa1100_port, port);
320 unsigned long flags;
321 unsigned int utcr3;
322
323 spin_lock_irqsave(&sport->port.lock, flags);
324 utcr3 = UART_GET_UTCR3(sport);
325 if (break_state == -1)
326 utcr3 |= UTCR3_BRK;
327 else
328 utcr3 &= ~UTCR3_BRK;
329 UART_PUT_UTCR3(sport, utcr3);
330 spin_unlock_irqrestore(&sport->port.lock, flags);
331}
332
333static int sa1100_startup(struct uart_port *port)
334{
335 struct sa1100_port *sport =
336 container_of(port, struct sa1100_port, port);
337 int retval;
338
339 /*
340 * Allocate the IRQ
341 */
342 retval = request_irq(sport->port.irq, sa1100_int, 0,
343 "sa11x0-uart", sport);
344 if (retval)
345 return retval;
346
347 /*
348 * Finally, clear and enable interrupts
349 */
350 UART_PUT_UTSR0(sport, -1);
351 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
352
353 /*
354 * Enable modem status interrupts
355 */
356 spin_lock_irq(&sport->port.lock);
357 sa1100_enable_ms(&sport->port);
358 spin_unlock_irq(&sport->port.lock);
359
360 return 0;
361}
362
363static void sa1100_shutdown(struct uart_port *port)
364{
365 struct sa1100_port *sport =
366 container_of(port, struct sa1100_port, port);
367
368 /*
369 * Stop our timer.
370 */
371 del_timer_sync(&sport->timer);
372
373 /*
374 * Free the interrupt
375 */
376 free_irq(sport->port.irq, sport);
377
378 /*
379 * Disable all interrupts, port and break condition.
380 */
381 UART_PUT_UTCR3(sport, 0);
382}
383
384static void
385sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
386 const struct ktermios *old)
387{
388 struct sa1100_port *sport =
389 container_of(port, struct sa1100_port, port);
390 unsigned long flags;
391 unsigned int utcr0, old_utcr3, baud, quot;
392 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
393
394 /*
395 * We only support CS7 and CS8.
396 */
397 while ((termios->c_cflag & CSIZE) != CS7 &&
398 (termios->c_cflag & CSIZE) != CS8) {
399 termios->c_cflag &= ~CSIZE;
400 termios->c_cflag |= old_csize;
401 old_csize = CS8;
402 }
403
404 if ((termios->c_cflag & CSIZE) == CS8)
405 utcr0 = UTCR0_DSS;
406 else
407 utcr0 = 0;
408
409 if (termios->c_cflag & CSTOPB)
410 utcr0 |= UTCR0_SBS;
411 if (termios->c_cflag & PARENB) {
412 utcr0 |= UTCR0_PE;
413 if (!(termios->c_cflag & PARODD))
414 utcr0 |= UTCR0_OES;
415 }
416
417 /*
418 * Ask the core to calculate the divisor for us.
419 */
420 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
421 quot = uart_get_divisor(port, baud);
422
423 del_timer_sync(&sport->timer);
424
425 spin_lock_irqsave(&sport->port.lock, flags);
426
427 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
428 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
429 if (termios->c_iflag & INPCK)
430 sport->port.read_status_mask |=
431 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
432 if (termios->c_iflag & (BRKINT | PARMRK))
433 sport->port.read_status_mask |=
434 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
435
436 /*
437 * Characters to ignore
438 */
439 sport->port.ignore_status_mask = 0;
440 if (termios->c_iflag & IGNPAR)
441 sport->port.ignore_status_mask |=
442 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
443 if (termios->c_iflag & IGNBRK) {
444 sport->port.ignore_status_mask |=
445 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
446 /*
447 * If we're ignoring parity and break indicators,
448 * ignore overruns too (for real raw support).
449 */
450 if (termios->c_iflag & IGNPAR)
451 sport->port.ignore_status_mask |=
452 UTSR1_TO_SM(UTSR1_ROR);
453 }
454
455 /*
456 * Update the per-port timeout.
457 */
458 uart_update_timeout(port, termios->c_cflag, baud);
459
460 /*
461 * disable interrupts and drain transmitter
462 */
463 old_utcr3 = UART_GET_UTCR3(sport);
464 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
465
466 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
467 barrier();
468
469 /* then, disable everything */
470 UART_PUT_UTCR3(sport, 0);
471
472 /* set the parity, stop bits and data size */
473 UART_PUT_UTCR0(sport, utcr0);
474
475 /* set the baud rate */
476 quot -= 1;
477 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
478 UART_PUT_UTCR2(sport, (quot & 0xff));
479
480 UART_PUT_UTSR0(sport, -1);
481
482 UART_PUT_UTCR3(sport, old_utcr3);
483
484 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
485 sa1100_enable_ms(&sport->port);
486
487 spin_unlock_irqrestore(&sport->port.lock, flags);
488}
489
490static const char *sa1100_type(struct uart_port *port)
491{
492 struct sa1100_port *sport =
493 container_of(port, struct sa1100_port, port);
494
495 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
496}
497
498/*
499 * Release the memory region(s) being used by 'port'.
500 */
501static void sa1100_release_port(struct uart_port *port)
502{
503 struct sa1100_port *sport =
504 container_of(port, struct sa1100_port, port);
505
506 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
507}
508
509/*
510 * Request the memory region(s) being used by 'port'.
511 */
512static int sa1100_request_port(struct uart_port *port)
513{
514 struct sa1100_port *sport =
515 container_of(port, struct sa1100_port, port);
516
517 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
518 "sa11x0-uart") != NULL ? 0 : -EBUSY;
519}
520
521/*
522 * Configure/autoconfigure the port.
523 */
524static void sa1100_config_port(struct uart_port *port, int flags)
525{
526 struct sa1100_port *sport =
527 container_of(port, struct sa1100_port, port);
528
529 if (flags & UART_CONFIG_TYPE &&
530 sa1100_request_port(&sport->port) == 0)
531 sport->port.type = PORT_SA1100;
532}
533
534/*
535 * Verify the new serial_struct (for TIOCSSERIAL).
536 * The only change we allow are to the flags and type, and
537 * even then only between PORT_SA1100 and PORT_UNKNOWN
538 */
539static int
540sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
541{
542 struct sa1100_port *sport =
543 container_of(port, struct sa1100_port, port);
544 int ret = 0;
545
546 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
547 ret = -EINVAL;
548 if (sport->port.irq != ser->irq)
549 ret = -EINVAL;
550 if (ser->io_type != SERIAL_IO_MEM)
551 ret = -EINVAL;
552 if (sport->port.uartclk / 16 != ser->baud_base)
553 ret = -EINVAL;
554 if ((void *)sport->port.mapbase != ser->iomem_base)
555 ret = -EINVAL;
556 if (sport->port.iobase != ser->port)
557 ret = -EINVAL;
558 if (ser->hub6 != 0)
559 ret = -EINVAL;
560 return ret;
561}
562
563static struct uart_ops sa1100_pops = {
564 .tx_empty = sa1100_tx_empty,
565 .set_mctrl = sa1100_set_mctrl,
566 .get_mctrl = sa1100_get_mctrl,
567 .stop_tx = sa1100_stop_tx,
568 .start_tx = sa1100_start_tx,
569 .stop_rx = sa1100_stop_rx,
570 .enable_ms = sa1100_enable_ms,
571 .break_ctl = sa1100_break_ctl,
572 .startup = sa1100_startup,
573 .shutdown = sa1100_shutdown,
574 .set_termios = sa1100_set_termios,
575 .type = sa1100_type,
576 .release_port = sa1100_release_port,
577 .request_port = sa1100_request_port,
578 .config_port = sa1100_config_port,
579 .verify_port = sa1100_verify_port,
580};
581
582static struct sa1100_port sa1100_ports[NR_PORTS];
583
584/*
585 * Setup the SA1100 serial ports. Note that we don't include the IrDA
586 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
587 *
588 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
589 * Which serial port this ends up being depends on the machine you're
590 * running this kernel on. I'm not convinced that this is a good idea,
591 * but that's the way it traditionally works.
592 *
593 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
594 * used here.
595 */
596static void __init sa1100_init_ports(void)
597{
598 static int first = 1;
599 int i;
600
601 if (!first)
602 return;
603 first = 0;
604
605 for (i = 0; i < NR_PORTS; i++) {
606 sa1100_ports[i].port.uartclk = 3686400;
607 sa1100_ports[i].port.ops = &sa1100_pops;
608 sa1100_ports[i].port.fifosize = 8;
609 sa1100_ports[i].port.line = i;
610 sa1100_ports[i].port.iotype = UPIO_MEM;
611 timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0);
612 }
613
614 /*
615 * make transmit lines outputs, so that when the port
616 * is closed, the output is in the MARK state.
617 */
618 PPDR |= PPC_TXD1 | PPC_TXD3;
619 PPSR |= PPC_TXD1 | PPC_TXD3;
620}
621
622void sa1100_register_uart_fns(struct sa1100_port_fns *fns)
623{
624 if (fns->get_mctrl)
625 sa1100_pops.get_mctrl = fns->get_mctrl;
626 if (fns->set_mctrl)
627 sa1100_pops.set_mctrl = fns->set_mctrl;
628
629 sa1100_pops.pm = fns->pm;
630 /*
631 * FIXME: fns->set_wake is unused - this should be called from
632 * the suspend() callback if device_may_wakeup(dev)) is set.
633 */
634}
635
636void __init sa1100_register_uart(int idx, int port)
637{
638 if (idx >= NR_PORTS) {
639 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
640 return;
641 }
642
643 switch (port) {
644 case 1:
645 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
646 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
647 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
648 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
649 break;
650
651 case 2:
652 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
653 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
654 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
655 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
656 break;
657
658 case 3:
659 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
660 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
661 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
662 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
663 break;
664
665 default:
666 printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
667 }
668}
669
670
671#ifdef CONFIG_SERIAL_SA1100_CONSOLE
672static void sa1100_console_putchar(struct uart_port *port, unsigned char ch)
673{
674 struct sa1100_port *sport =
675 container_of(port, struct sa1100_port, port);
676
677 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
678 barrier();
679 UART_PUT_CHAR(sport, ch);
680}
681
682/*
683 * Interrupts are disabled on entering
684 */
685static void
686sa1100_console_write(struct console *co, const char *s, unsigned int count)
687{
688 struct sa1100_port *sport = &sa1100_ports[co->index];
689 unsigned int old_utcr3, status;
690
691 /*
692 * First, save UTCR3 and then disable interrupts
693 */
694 old_utcr3 = UART_GET_UTCR3(sport);
695 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
696 UTCR3_TXE);
697
698 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
699
700 /*
701 * Finally, wait for transmitter to become empty
702 * and restore UTCR3
703 */
704 do {
705 status = UART_GET_UTSR1(sport);
706 } while (status & UTSR1_TBY);
707 UART_PUT_UTCR3(sport, old_utcr3);
708}
709
710/*
711 * If the port was already initialised (eg, by a boot loader),
712 * try to determine the current setup.
713 */
714static void __init
715sa1100_console_get_options(struct sa1100_port *sport, int *baud,
716 int *parity, int *bits)
717{
718 unsigned int utcr3;
719
720 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
721 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
722 /* ok, the port was enabled */
723 unsigned int utcr0, quot;
724
725 utcr0 = UART_GET_UTCR0(sport);
726
727 *parity = 'n';
728 if (utcr0 & UTCR0_PE) {
729 if (utcr0 & UTCR0_OES)
730 *parity = 'e';
731 else
732 *parity = 'o';
733 }
734
735 if (utcr0 & UTCR0_DSS)
736 *bits = 8;
737 else
738 *bits = 7;
739
740 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
741 quot &= 0xfff;
742 *baud = sport->port.uartclk / (16 * (quot + 1));
743 }
744}
745
746static int __init
747sa1100_console_setup(struct console *co, char *options)
748{
749 struct sa1100_port *sport;
750 int baud = 9600;
751 int bits = 8;
752 int parity = 'n';
753 int flow = 'n';
754
755 /*
756 * Check whether an invalid uart number has been specified, and
757 * if so, search for the first available port that does have
758 * console support.
759 */
760 if (co->index == -1 || co->index >= NR_PORTS)
761 co->index = 0;
762 sport = &sa1100_ports[co->index];
763
764 if (options)
765 uart_parse_options(options, &baud, &parity, &bits, &flow);
766 else
767 sa1100_console_get_options(sport, &baud, &parity, &bits);
768
769 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
770}
771
772static struct uart_driver sa1100_reg;
773static struct console sa1100_console = {
774 .name = "ttySA",
775 .write = sa1100_console_write,
776 .device = uart_console_device,
777 .setup = sa1100_console_setup,
778 .flags = CON_PRINTBUFFER,
779 .index = -1,
780 .data = &sa1100_reg,
781};
782
783static int __init sa1100_rs_console_init(void)
784{
785 sa1100_init_ports();
786 register_console(&sa1100_console);
787 return 0;
788}
789console_initcall(sa1100_rs_console_init);
790
791#define SA1100_CONSOLE &sa1100_console
792#else
793#define SA1100_CONSOLE NULL
794#endif
795
796static struct uart_driver sa1100_reg = {
797 .owner = THIS_MODULE,
798 .driver_name = "ttySA",
799 .dev_name = "ttySA",
800 .major = SERIAL_SA1100_MAJOR,
801 .minor = MINOR_START,
802 .nr = NR_PORTS,
803 .cons = SA1100_CONSOLE,
804};
805
806static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
807{
808 struct sa1100_port *sport = platform_get_drvdata(dev);
809
810 if (sport)
811 uart_suspend_port(&sa1100_reg, &sport->port);
812
813 return 0;
814}
815
816static int sa1100_serial_resume(struct platform_device *dev)
817{
818 struct sa1100_port *sport = platform_get_drvdata(dev);
819
820 if (sport)
821 uart_resume_port(&sa1100_reg, &sport->port);
822
823 return 0;
824}
825
826static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev)
827{
828 sport->port.dev = &dev->dev;
829 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE);
830
831 // mctrl_gpio_init() requires that the GPIO driver supports interrupts,
832 // but we need to support GPIO drivers for hardware that has no such
833 // interrupts. Use mctrl_gpio_init_noauto() instead.
834 sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0);
835 if (IS_ERR(sport->gpios)) {
836 int err = PTR_ERR(sport->gpios);
837
838 dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n",
839 err);
840
841 if (err == -EPROBE_DEFER)
842 return err;
843
844 sport->gpios = NULL;
845 }
846
847 platform_set_drvdata(dev, sport);
848
849 return uart_add_one_port(&sa1100_reg, &sport->port);
850}
851
852static int sa1100_serial_probe(struct platform_device *dev)
853{
854 struct resource *res;
855 int i;
856
857 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
858 if (!res)
859 return -EINVAL;
860
861 for (i = 0; i < NR_PORTS; i++)
862 if (sa1100_ports[i].port.mapbase == res->start)
863 break;
864 if (i == NR_PORTS)
865 return -ENODEV;
866
867 sa1100_serial_add_one_port(&sa1100_ports[i], dev);
868
869 return 0;
870}
871
872static int sa1100_serial_remove(struct platform_device *pdev)
873{
874 struct sa1100_port *sport = platform_get_drvdata(pdev);
875
876 if (sport)
877 uart_remove_one_port(&sa1100_reg, &sport->port);
878
879 return 0;
880}
881
882static struct platform_driver sa11x0_serial_driver = {
883 .probe = sa1100_serial_probe,
884 .remove = sa1100_serial_remove,
885 .suspend = sa1100_serial_suspend,
886 .resume = sa1100_serial_resume,
887 .driver = {
888 .name = "sa11x0-uart",
889 },
890};
891
892static int __init sa1100_serial_init(void)
893{
894 int ret;
895
896 printk(KERN_INFO "Serial: SA11x0 driver\n");
897
898 sa1100_init_ports();
899
900 ret = uart_register_driver(&sa1100_reg);
901 if (ret == 0) {
902 ret = platform_driver_register(&sa11x0_serial_driver);
903 if (ret)
904 uart_unregister_driver(&sa1100_reg);
905 }
906 return ret;
907}
908
909static void __exit sa1100_serial_exit(void)
910{
911 platform_driver_unregister(&sa11x0_serial_driver);
912 uart_unregister_driver(&sa1100_reg);
913}
914
915module_init(sa1100_serial_init);
916module_exit(sa1100_serial_exit);
917
918MODULE_AUTHOR("Deep Blue Solutions Ltd");
919MODULE_DESCRIPTION("SA1100 generic serial port driver");
920MODULE_LICENSE("GPL");
921MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
922MODULE_ALIAS("platform:sa11x0-uart");