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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2017-2019, Linaro Ltd.
5 */
6
7#include <linux/debugfs.h>
8#include <linux/err.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/random.h>
12#include <linux/slab.h>
13#include <linux/soc/qcom/smem.h>
14#include <linux/string.h>
15#include <linux/stringify.h>
16#include <linux/sys_soc.h>
17#include <linux/types.h>
18
19#include <asm/unaligned.h>
20
21#include <dt-bindings/arm/qcom,ids.h>
22
23/*
24 * SoC version type with major number in the upper 16 bits and minor
25 * number in the lower 16 bits.
26 */
27#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
28#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
29#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
30
31/* Helper macros to create soc_id table */
32#define qcom_board_id(id) QCOM_ID_ ## id, __stringify(id)
33#define qcom_board_id_named(id, name) QCOM_ID_ ## id, (name)
34
35#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
36#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
37
38/*
39 * SMEM item id, used to acquire handles to respective
40 * SMEM region.
41 */
42#define SMEM_HW_SW_BUILD_ID 137
43
44#ifdef CONFIG_DEBUG_FS
45#define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32
46#define SMEM_IMAGE_VERSION_SIZE 4096
47#define SMEM_IMAGE_VERSION_NAME_SIZE 75
48#define SMEM_IMAGE_VERSION_VARIANT_SIZE 20
49#define SMEM_IMAGE_VERSION_OEM_SIZE 32
50
51/*
52 * SMEM Image table indices
53 */
54#define SMEM_IMAGE_TABLE_BOOT_INDEX 0
55#define SMEM_IMAGE_TABLE_TZ_INDEX 1
56#define SMEM_IMAGE_TABLE_RPM_INDEX 3
57#define SMEM_IMAGE_TABLE_APPS_INDEX 10
58#define SMEM_IMAGE_TABLE_MPSS_INDEX 11
59#define SMEM_IMAGE_TABLE_ADSP_INDEX 12
60#define SMEM_IMAGE_TABLE_CNSS_INDEX 13
61#define SMEM_IMAGE_TABLE_VIDEO_INDEX 14
62#define SMEM_IMAGE_VERSION_TABLE 469
63
64/*
65 * SMEM Image table names
66 */
67static const char *const socinfo_image_names[] = {
68 [SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp",
69 [SMEM_IMAGE_TABLE_APPS_INDEX] = "apps",
70 [SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot",
71 [SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
72 [SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
73 [SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
74 [SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
75 [SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
76};
77
78static const char *const pmic_models[] = {
79 [0] = "Unknown PMIC model",
80 [1] = "PM8941",
81 [2] = "PM8841",
82 [3] = "PM8019",
83 [4] = "PM8226",
84 [5] = "PM8110",
85 [6] = "PMA8084",
86 [7] = "PMI8962",
87 [8] = "PMD9635",
88 [9] = "PM8994",
89 [10] = "PMI8994",
90 [11] = "PM8916",
91 [12] = "PM8004",
92 [13] = "PM8909/PM8058",
93 [14] = "PM8028",
94 [15] = "PM8901",
95 [16] = "PM8950/PM8027",
96 [17] = "PMI8950/ISL9519",
97 [18] = "PMK8001/PM8921",
98 [19] = "PMI8996/PM8018",
99 [20] = "PM8998/PM8015",
100 [21] = "PMI8998/PM8014",
101 [22] = "PM8821",
102 [23] = "PM8038",
103 [24] = "PM8005/PM8922",
104 [25] = "PM8917",
105 [26] = "PM660L",
106 [27] = "PM660",
107 [30] = "PM8150",
108 [31] = "PM8150L",
109 [32] = "PM8150B",
110 [33] = "PMK8002",
111 [36] = "PM8009",
112 [38] = "PM8150C",
113 [41] = "SMB2351",
114 [45] = "PM6125",
115 [47] = "PMK8350",
116 [48] = "PM8350",
117 [49] = "PM8350C",
118 [50] = "PM8350B",
119 [51] = "PMR735A",
120 [52] = "PMR735B",
121 [58] = "PM8450",
122 [65] = "PM8010",
123};
124#endif /* CONFIG_DEBUG_FS */
125
126/* Socinfo SMEM item structure */
127struct socinfo {
128 __le32 fmt;
129 __le32 id;
130 __le32 ver;
131 char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
132 /* Version 2 */
133 __le32 raw_id;
134 __le32 raw_ver;
135 /* Version 3 */
136 __le32 hw_plat;
137 /* Version 4 */
138 __le32 plat_ver;
139 /* Version 5 */
140 __le32 accessory_chip;
141 /* Version 6 */
142 __le32 hw_plat_subtype;
143 /* Version 7 */
144 __le32 pmic_model;
145 __le32 pmic_die_rev;
146 /* Version 8 */
147 __le32 pmic_model_1;
148 __le32 pmic_die_rev_1;
149 __le32 pmic_model_2;
150 __le32 pmic_die_rev_2;
151 /* Version 9 */
152 __le32 foundry_id;
153 /* Version 10 */
154 __le32 serial_num;
155 /* Version 11 */
156 __le32 num_pmics;
157 __le32 pmic_array_offset;
158 /* Version 12 */
159 __le32 chip_family;
160 __le32 raw_device_family;
161 __le32 raw_device_num;
162 /* Version 13 */
163 __le32 nproduct_id;
164 char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
165 /* Version 14 */
166 __le32 num_clusters;
167 __le32 ncluster_array_offset;
168 __le32 num_defective_parts;
169 __le32 ndefective_parts_array_offset;
170 /* Version 15 */
171 __le32 nmodem_supported;
172};
173
174#ifdef CONFIG_DEBUG_FS
175struct socinfo_params {
176 u32 raw_device_family;
177 u32 hw_plat_subtype;
178 u32 accessory_chip;
179 u32 raw_device_num;
180 u32 chip_family;
181 u32 foundry_id;
182 u32 plat_ver;
183 u32 raw_ver;
184 u32 hw_plat;
185 u32 fmt;
186 u32 nproduct_id;
187 u32 num_clusters;
188 u32 ncluster_array_offset;
189 u32 num_defective_parts;
190 u32 ndefective_parts_array_offset;
191 u32 nmodem_supported;
192};
193
194struct smem_image_version {
195 char name[SMEM_IMAGE_VERSION_NAME_SIZE];
196 char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE];
197 char pad;
198 char oem[SMEM_IMAGE_VERSION_OEM_SIZE];
199};
200#endif /* CONFIG_DEBUG_FS */
201
202struct qcom_socinfo {
203 struct soc_device *soc_dev;
204 struct soc_device_attribute attr;
205#ifdef CONFIG_DEBUG_FS
206 struct dentry *dbg_root;
207 struct socinfo_params info;
208#endif /* CONFIG_DEBUG_FS */
209};
210
211struct soc_id {
212 unsigned int id;
213 const char *name;
214};
215
216static const struct soc_id soc_id[] = {
217 { qcom_board_id(MSM8960) },
218 { qcom_board_id(APQ8064) },
219 { qcom_board_id(MSM8660A) },
220 { qcom_board_id(MSM8260A) },
221 { qcom_board_id(APQ8060A) },
222 { qcom_board_id(MSM8974) },
223 { qcom_board_id(MPQ8064) },
224 { qcom_board_id(MSM8960AB) },
225 { qcom_board_id(APQ8060AB) },
226 { qcom_board_id(MSM8260AB) },
227 { qcom_board_id(MSM8660AB) },
228 { qcom_board_id(MSM8626) },
229 { qcom_board_id(MSM8610) },
230 { qcom_board_id(APQ8064AB) },
231 { qcom_board_id(MSM8226) },
232 { qcom_board_id(MSM8526) },
233 { qcom_board_id(MSM8110) },
234 { qcom_board_id(MSM8210) },
235 { qcom_board_id(MSM8810) },
236 { qcom_board_id(MSM8212) },
237 { qcom_board_id(MSM8612) },
238 { qcom_board_id(MSM8112) },
239 { qcom_board_id(MSM8225Q) },
240 { qcom_board_id(MSM8625Q) },
241 { qcom_board_id(MSM8125Q) },
242 { qcom_board_id(APQ8064AA) },
243 { qcom_board_id(APQ8084) },
244 { qcom_board_id(APQ8074) },
245 { qcom_board_id(MSM8274) },
246 { qcom_board_id(MSM8674) },
247 { qcom_board_id_named(MSM8974PRO_AC, "MSM8974PRO-AC") },
248 { qcom_board_id(MSM8126) },
249 { qcom_board_id(APQ8026) },
250 { qcom_board_id(MSM8926) },
251 { qcom_board_id(MSM8326) },
252 { qcom_board_id(MSM8916) },
253 { qcom_board_id(MSM8956) },
254 { qcom_board_id(MSM8976) },
255 { qcom_board_id(MSM8994) },
256 { qcom_board_id_named(APQ8074PRO_AA, "APQ8074PRO-AA") },
257 { qcom_board_id_named(APQ8074PRO_AB, "APQ8074PRO-AB") },
258 { qcom_board_id_named(APQ8074PRO_AC, "APQ8074PRO-AC") },
259 { qcom_board_id_named(MSM8274PRO_AA, "MSM8274PRO-AA") },
260 { qcom_board_id_named(MSM8274PRO_AB, "MSM8274PRO-AB") },
261 { qcom_board_id_named(MSM8274PRO_AC, "MSM8274PRO-AC") },
262 { qcom_board_id_named(MSM8674PRO_AA, "MSM8674PRO-AA") },
263 { qcom_board_id_named(MSM8674PRO_AB, "MSM8674PRO-AB") },
264 { qcom_board_id_named(MSM8674PRO_AC, "MSM8674PRO-AC") },
265 { qcom_board_id_named(MSM8974PRO_AA, "MSM8974PRO-AA") },
266 { qcom_board_id_named(MSM8974PRO_AB, "MSM8974PRO-AB") },
267 { qcom_board_id(APQ8028) },
268 { qcom_board_id(MSM8128) },
269 { qcom_board_id(MSM8228) },
270 { qcom_board_id(MSM8528) },
271 { qcom_board_id(MSM8628) },
272 { qcom_board_id(MSM8928) },
273 { qcom_board_id(MSM8510) },
274 { qcom_board_id(MSM8512) },
275 { qcom_board_id(MSM8936) },
276 { qcom_board_id(MSM8939) },
277 { qcom_board_id(APQ8036) },
278 { qcom_board_id(APQ8039) },
279 { qcom_board_id(MSM8996) },
280 { qcom_board_id(APQ8016) },
281 { qcom_board_id(MSM8216) },
282 { qcom_board_id(MSM8116) },
283 { qcom_board_id(MSM8616) },
284 { qcom_board_id(MSM8992) },
285 { qcom_board_id(APQ8094) },
286 { qcom_board_id(MDM9607) },
287 { qcom_board_id(APQ8096) },
288 { qcom_board_id(MSM8998) },
289 { qcom_board_id(MSM8953) },
290 { qcom_board_id(MDM8207) },
291 { qcom_board_id(MDM9207) },
292 { qcom_board_id(MDM9307) },
293 { qcom_board_id(MDM9628) },
294 { qcom_board_id(APQ8053) },
295 { qcom_board_id(MSM8996SG) },
296 { qcom_board_id(MSM8996AU) },
297 { qcom_board_id(APQ8096AU) },
298 { qcom_board_id(APQ8096SG) },
299 { qcom_board_id(SDM660) },
300 { qcom_board_id(SDM630) },
301 { qcom_board_id(APQ8098) },
302 { qcom_board_id(SDM845) },
303 { qcom_board_id(MDM9206) },
304 { qcom_board_id(IPQ8074) },
305 { qcom_board_id(SDA660) },
306 { qcom_board_id(SDM658) },
307 { qcom_board_id(SDA658) },
308 { qcom_board_id(SDA630) },
309 { qcom_board_id(SDM450) },
310 { qcom_board_id(SM8150) },
311 { qcom_board_id(SDA845) },
312 { qcom_board_id(IPQ8072) },
313 { qcom_board_id(IPQ8076) },
314 { qcom_board_id(IPQ8078) },
315 { qcom_board_id(SDM636) },
316 { qcom_board_id(SDA636) },
317 { qcom_board_id(SDM632) },
318 { qcom_board_id(SDA632) },
319 { qcom_board_id(SDA450) },
320 { qcom_board_id(SM8250) },
321 { qcom_board_id(SA8155) },
322 { qcom_board_id(IPQ8070) },
323 { qcom_board_id(IPQ8071) },
324 { qcom_board_id(IPQ8072A) },
325 { qcom_board_id(IPQ8074A) },
326 { qcom_board_id(IPQ8076A) },
327 { qcom_board_id(IPQ8078A) },
328 { qcom_board_id(SM6125) },
329 { qcom_board_id(IPQ8070A) },
330 { qcom_board_id(IPQ8071A) },
331 { qcom_board_id(IPQ6018) },
332 { qcom_board_id(IPQ6028) },
333 { qcom_board_id(SM4250) },
334 { qcom_board_id(IPQ6000) },
335 { qcom_board_id(IPQ6010) },
336 { qcom_board_id(SC7180) },
337 { qcom_board_id(SM6350) },
338 { qcom_board_id(SM8350) },
339 { qcom_board_id(SM6115) },
340 { qcom_board_id(SC8280XP) },
341 { qcom_board_id(IPQ6005) },
342 { qcom_board_id(QRB5165) },
343 { qcom_board_id(SM8450) },
344 { qcom_board_id(SM8550) },
345 { qcom_board_id(SM7225) },
346 { qcom_board_id(SA8295P) },
347 { qcom_board_id(SA8540P) },
348 { qcom_board_id(QCM4290) },
349 { qcom_board_id(QCS4290) },
350 { qcom_board_id_named(SM8450_2, "SM8450") },
351 { qcom_board_id_named(SM8450_3, "SM8450") },
352 { qcom_board_id(SC7280) },
353 { qcom_board_id(SC7180P) },
354 { qcom_board_id(SM6375) },
355 { qcom_board_id(QRU1000) },
356 { qcom_board_id(QDU1000) },
357 { qcom_board_id(QDU1010) },
358 { qcom_board_id(QRU1032) },
359 { qcom_board_id(QRU1052) },
360 { qcom_board_id(QRU1062) },
361};
362
363static const char *socinfo_machine(struct device *dev, unsigned int id)
364{
365 int idx;
366
367 for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) {
368 if (soc_id[idx].id == id)
369 return soc_id[idx].name;
370 }
371
372 return NULL;
373}
374
375#ifdef CONFIG_DEBUG_FS
376
377#define QCOM_OPEN(name, _func) \
378static int qcom_open_##name(struct inode *inode, struct file *file) \
379{ \
380 return single_open(file, _func, inode->i_private); \
381} \
382 \
383static const struct file_operations qcom_ ##name## _ops = { \
384 .open = qcom_open_##name, \
385 .read = seq_read, \
386 .llseek = seq_lseek, \
387 .release = single_release, \
388}
389
390#define DEBUGFS_ADD(info, name) \
391 debugfs_create_file(__stringify(name), 0444, \
392 qcom_socinfo->dbg_root, \
393 info, &qcom_ ##name## _ops)
394
395
396static int qcom_show_build_id(struct seq_file *seq, void *p)
397{
398 struct socinfo *socinfo = seq->private;
399
400 seq_printf(seq, "%s\n", socinfo->build_id);
401
402 return 0;
403}
404
405static int qcom_show_pmic_model(struct seq_file *seq, void *p)
406{
407 struct socinfo *socinfo = seq->private;
408 int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model));
409
410 if (model < 0)
411 return -EINVAL;
412
413 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
414 seq_printf(seq, "%s\n", pmic_models[model]);
415 else
416 seq_printf(seq, "unknown (%d)\n", model);
417
418 return 0;
419}
420
421static int qcom_show_pmic_model_array(struct seq_file *seq, void *p)
422{
423 struct socinfo *socinfo = seq->private;
424 unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics);
425 unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset);
426 int i;
427 void *ptr = socinfo;
428
429 ptr += pmic_array_offset;
430
431 /* No need for bounds checking, it happened at socinfo_debugfs_init */
432 for (i = 0; i < num_pmics; i++) {
433 unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32)));
434 unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32));
435
436 if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
437 seq_printf(seq, "%s %u.%u\n", pmic_models[model],
438 SOCINFO_MAJOR(die_rev),
439 SOCINFO_MINOR(die_rev));
440 else
441 seq_printf(seq, "unknown (%d)\n", model);
442 }
443
444 return 0;
445}
446
447static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p)
448{
449 struct socinfo *socinfo = seq->private;
450
451 seq_printf(seq, "%u.%u\n",
452 SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)),
453 SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev)));
454
455 return 0;
456}
457
458static int qcom_show_chip_id(struct seq_file *seq, void *p)
459{
460 struct socinfo *socinfo = seq->private;
461
462 seq_printf(seq, "%s\n", socinfo->chip_id);
463
464 return 0;
465}
466
467QCOM_OPEN(build_id, qcom_show_build_id);
468QCOM_OPEN(pmic_model, qcom_show_pmic_model);
469QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array);
470QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision);
471QCOM_OPEN(chip_id, qcom_show_chip_id);
472
473#define DEFINE_IMAGE_OPS(type) \
474static int show_image_##type(struct seq_file *seq, void *p) \
475{ \
476 struct smem_image_version *image_version = seq->private; \
477 if (image_version->type[0] != '\0') \
478 seq_printf(seq, "%s\n", image_version->type); \
479 return 0; \
480} \
481static int open_image_##type(struct inode *inode, struct file *file) \
482{ \
483 return single_open(file, show_image_##type, inode->i_private); \
484} \
485 \
486static const struct file_operations qcom_image_##type##_ops = { \
487 .open = open_image_##type, \
488 .read = seq_read, \
489 .llseek = seq_lseek, \
490 .release = single_release, \
491}
492
493DEFINE_IMAGE_OPS(name);
494DEFINE_IMAGE_OPS(variant);
495DEFINE_IMAGE_OPS(oem);
496
497static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
498 struct socinfo *info, size_t info_size)
499{
500 struct smem_image_version *versions;
501 struct dentry *dentry;
502 size_t size;
503 int i;
504 unsigned int num_pmics;
505 unsigned int pmic_array_offset;
506
507 qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL);
508
509 qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt);
510
511 debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root,
512 &qcom_socinfo->info.fmt);
513
514 switch (qcom_socinfo->info.fmt) {
515 case SOCINFO_VERSION(0, 15):
516 qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported);
517
518 debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root,
519 &qcom_socinfo->info.nmodem_supported);
520 fallthrough;
521 case SOCINFO_VERSION(0, 14):
522 qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
523 qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
524 qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
525 qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
526
527 debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
528 &qcom_socinfo->info.num_clusters);
529 debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
530 &qcom_socinfo->info.ncluster_array_offset);
531 debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
532 &qcom_socinfo->info.num_defective_parts);
533 debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
534 &qcom_socinfo->info.ndefective_parts_array_offset);
535 fallthrough;
536 case SOCINFO_VERSION(0, 13):
537 qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);
538
539 debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root,
540 &qcom_socinfo->info.nproduct_id);
541 DEBUGFS_ADD(info, chip_id);
542 fallthrough;
543 case SOCINFO_VERSION(0, 12):
544 qcom_socinfo->info.chip_family =
545 __le32_to_cpu(info->chip_family);
546 qcom_socinfo->info.raw_device_family =
547 __le32_to_cpu(info->raw_device_family);
548 qcom_socinfo->info.raw_device_num =
549 __le32_to_cpu(info->raw_device_num);
550
551 debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root,
552 &qcom_socinfo->info.chip_family);
553 debugfs_create_x32("raw_device_family", 0444,
554 qcom_socinfo->dbg_root,
555 &qcom_socinfo->info.raw_device_family);
556 debugfs_create_x32("raw_device_number", 0444,
557 qcom_socinfo->dbg_root,
558 &qcom_socinfo->info.raw_device_num);
559 fallthrough;
560 case SOCINFO_VERSION(0, 11):
561 num_pmics = le32_to_cpu(info->num_pmics);
562 pmic_array_offset = le32_to_cpu(info->pmic_array_offset);
563 if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size)
564 DEBUGFS_ADD(info, pmic_model_array);
565 fallthrough;
566 case SOCINFO_VERSION(0, 10):
567 case SOCINFO_VERSION(0, 9):
568 qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id);
569
570 debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root,
571 &qcom_socinfo->info.foundry_id);
572 fallthrough;
573 case SOCINFO_VERSION(0, 8):
574 case SOCINFO_VERSION(0, 7):
575 DEBUGFS_ADD(info, pmic_model);
576 DEBUGFS_ADD(info, pmic_die_rev);
577 fallthrough;
578 case SOCINFO_VERSION(0, 6):
579 qcom_socinfo->info.hw_plat_subtype =
580 __le32_to_cpu(info->hw_plat_subtype);
581
582 debugfs_create_u32("hardware_platform_subtype", 0444,
583 qcom_socinfo->dbg_root,
584 &qcom_socinfo->info.hw_plat_subtype);
585 fallthrough;
586 case SOCINFO_VERSION(0, 5):
587 qcom_socinfo->info.accessory_chip =
588 __le32_to_cpu(info->accessory_chip);
589
590 debugfs_create_u32("accessory_chip", 0444,
591 qcom_socinfo->dbg_root,
592 &qcom_socinfo->info.accessory_chip);
593 fallthrough;
594 case SOCINFO_VERSION(0, 4):
595 qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver);
596
597 debugfs_create_u32("platform_version", 0444,
598 qcom_socinfo->dbg_root,
599 &qcom_socinfo->info.plat_ver);
600 fallthrough;
601 case SOCINFO_VERSION(0, 3):
602 qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat);
603
604 debugfs_create_u32("hardware_platform", 0444,
605 qcom_socinfo->dbg_root,
606 &qcom_socinfo->info.hw_plat);
607 fallthrough;
608 case SOCINFO_VERSION(0, 2):
609 qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
610
611 debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
612 &qcom_socinfo->info.raw_ver);
613 fallthrough;
614 case SOCINFO_VERSION(0, 1):
615 DEBUGFS_ADD(info, build_id);
616 break;
617 }
618
619 versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE,
620 &size);
621
622 for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) {
623 if (!socinfo_image_names[i])
624 continue;
625
626 dentry = debugfs_create_dir(socinfo_image_names[i],
627 qcom_socinfo->dbg_root);
628 debugfs_create_file("name", 0444, dentry, &versions[i],
629 &qcom_image_name_ops);
630 debugfs_create_file("variant", 0444, dentry, &versions[i],
631 &qcom_image_variant_ops);
632 debugfs_create_file("oem", 0444, dentry, &versions[i],
633 &qcom_image_oem_ops);
634 }
635}
636
637static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo)
638{
639 debugfs_remove_recursive(qcom_socinfo->dbg_root);
640}
641#else
642static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
643 struct socinfo *info, size_t info_size)
644{
645}
646static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { }
647#endif /* CONFIG_DEBUG_FS */
648
649static int qcom_socinfo_probe(struct platform_device *pdev)
650{
651 struct qcom_socinfo *qs;
652 struct socinfo *info;
653 size_t item_size;
654
655 info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID,
656 &item_size);
657 if (IS_ERR(info)) {
658 dev_err(&pdev->dev, "Couldn't find socinfo\n");
659 return PTR_ERR(info);
660 }
661
662 qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL);
663 if (!qs)
664 return -ENOMEM;
665
666 qs->attr.family = "Snapdragon";
667 qs->attr.machine = socinfo_machine(&pdev->dev,
668 le32_to_cpu(info->id));
669 qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u",
670 le32_to_cpu(info->id));
671 qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u",
672 SOCINFO_MAJOR(le32_to_cpu(info->ver)),
673 SOCINFO_MINOR(le32_to_cpu(info->ver)));
674 if (offsetof(struct socinfo, serial_num) <= item_size)
675 qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL,
676 "%u",
677 le32_to_cpu(info->serial_num));
678
679 qs->soc_dev = soc_device_register(&qs->attr);
680 if (IS_ERR(qs->soc_dev))
681 return PTR_ERR(qs->soc_dev);
682
683 socinfo_debugfs_init(qs, info, item_size);
684
685 /* Feed the soc specific unique data into entropy pool */
686 add_device_randomness(info, item_size);
687
688 platform_set_drvdata(pdev, qs);
689
690 return 0;
691}
692
693static int qcom_socinfo_remove(struct platform_device *pdev)
694{
695 struct qcom_socinfo *qs = platform_get_drvdata(pdev);
696
697 soc_device_unregister(qs->soc_dev);
698
699 socinfo_debugfs_exit(qs);
700
701 return 0;
702}
703
704static struct platform_driver qcom_socinfo_driver = {
705 .probe = qcom_socinfo_probe,
706 .remove = qcom_socinfo_remove,
707 .driver = {
708 .name = "qcom-socinfo",
709 },
710};
711
712module_platform_driver(qcom_socinfo_driver);
713
714MODULE_DESCRIPTION("Qualcomm SoCinfo driver");
715MODULE_LICENSE("GPL v2");
716MODULE_ALIAS("platform:qcom-socinfo");