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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 MediaTek Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/iopoll.h>
8#include <linux/module.h>
9#include <linux/of_device.h>
10#include <linux/of_address.h>
11#include <linux/platform_device.h>
12#include <linux/regmap.h>
13#include <linux/soc/mediatek/mtk-mmsys.h>
14#include <linux/soc/mediatek/mtk-mutex.h>
15#include <linux/soc/mediatek/mtk-cmdq.h>
16
17#define MT2701_MUTEX0_MOD0 0x2c
18#define MT2701_MUTEX0_SOF0 0x30
19#define MT8183_MUTEX0_MOD0 0x30
20#define MT8183_MUTEX0_SOF0 0x2c
21
22#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
23#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
24#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
25#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
26#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
27#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
28
29#define INT_MUTEX BIT(1)
30
31#define MT8186_MUTEX_MOD_DISP_OVL0 0
32#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
33#define MT8186_MUTEX_MOD_DISP_RDMA0 2
34#define MT8186_MUTEX_MOD_DISP_COLOR0 4
35#define MT8186_MUTEX_MOD_DISP_CCORR0 5
36#define MT8186_MUTEX_MOD_DISP_AAL0 7
37#define MT8186_MUTEX_MOD_DISP_GAMMA0 8
38#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
39#define MT8186_MUTEX_MOD_DISP_DITHER0 10
40#define MT8186_MUTEX_MOD_DISP_RDMA1 17
41
42#define MT8186_MUTEX_SOF_SINGLE_MODE 0
43#define MT8186_MUTEX_SOF_DSI0 1
44#define MT8186_MUTEX_SOF_DPI0 2
45#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
46#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
47
48#define MT8167_MUTEX_MOD_DISP_PWM 1
49#define MT8167_MUTEX_MOD_DISP_OVL0 6
50#define MT8167_MUTEX_MOD_DISP_OVL1 7
51#define MT8167_MUTEX_MOD_DISP_RDMA0 8
52#define MT8167_MUTEX_MOD_DISP_RDMA1 9
53#define MT8167_MUTEX_MOD_DISP_WDMA0 10
54#define MT8167_MUTEX_MOD_DISP_CCORR 11
55#define MT8167_MUTEX_MOD_DISP_COLOR 12
56#define MT8167_MUTEX_MOD_DISP_AAL 13
57#define MT8167_MUTEX_MOD_DISP_GAMMA 14
58#define MT8167_MUTEX_MOD_DISP_DITHER 15
59#define MT8167_MUTEX_MOD_DISP_UFOE 16
60
61#define MT8192_MUTEX_MOD_DISP_OVL0 0
62#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
63#define MT8192_MUTEX_MOD_DISP_RDMA0 2
64#define MT8192_MUTEX_MOD_DISP_COLOR0 4
65#define MT8192_MUTEX_MOD_DISP_CCORR0 5
66#define MT8192_MUTEX_MOD_DISP_AAL0 6
67#define MT8192_MUTEX_MOD_DISP_GAMMA0 7
68#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
69#define MT8192_MUTEX_MOD_DISP_DITHER0 9
70#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
71#define MT8192_MUTEX_MOD_DISP_RDMA4 17
72
73#define MT8183_MUTEX_MOD_DISP_RDMA0 0
74#define MT8183_MUTEX_MOD_DISP_RDMA1 1
75#define MT8183_MUTEX_MOD_DISP_OVL0 9
76#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
77#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
78#define MT8183_MUTEX_MOD_DISP_WDMA0 12
79#define MT8183_MUTEX_MOD_DISP_COLOR0 13
80#define MT8183_MUTEX_MOD_DISP_CCORR0 14
81#define MT8183_MUTEX_MOD_DISP_AAL0 15
82#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
83#define MT8183_MUTEX_MOD_DISP_DITHER0 17
84
85#define MT8183_MUTEX_MOD_MDP_RDMA0 2
86#define MT8183_MUTEX_MOD_MDP_RSZ0 4
87#define MT8183_MUTEX_MOD_MDP_RSZ1 5
88#define MT8183_MUTEX_MOD_MDP_TDSHP0 6
89#define MT8183_MUTEX_MOD_MDP_WROT0 7
90#define MT8183_MUTEX_MOD_MDP_WDMA 8
91#define MT8183_MUTEX_MOD_MDP_AAL0 23
92#define MT8183_MUTEX_MOD_MDP_CCORR0 24
93
94#define MT8186_MUTEX_MOD_MDP_RDMA0 0
95#define MT8186_MUTEX_MOD_MDP_AAL0 2
96#define MT8186_MUTEX_MOD_MDP_HDR0 4
97#define MT8186_MUTEX_MOD_MDP_RSZ0 5
98#define MT8186_MUTEX_MOD_MDP_RSZ1 6
99#define MT8186_MUTEX_MOD_MDP_WROT0 7
100#define MT8186_MUTEX_MOD_MDP_TDSHP0 9
101#define MT8186_MUTEX_MOD_MDP_COLOR0 14
102
103#define MT8173_MUTEX_MOD_DISP_OVL0 11
104#define MT8173_MUTEX_MOD_DISP_OVL1 12
105#define MT8173_MUTEX_MOD_DISP_RDMA0 13
106#define MT8173_MUTEX_MOD_DISP_RDMA1 14
107#define MT8173_MUTEX_MOD_DISP_RDMA2 15
108#define MT8173_MUTEX_MOD_DISP_WDMA0 16
109#define MT8173_MUTEX_MOD_DISP_WDMA1 17
110#define MT8173_MUTEX_MOD_DISP_COLOR0 18
111#define MT8173_MUTEX_MOD_DISP_COLOR1 19
112#define MT8173_MUTEX_MOD_DISP_AAL 20
113#define MT8173_MUTEX_MOD_DISP_GAMMA 21
114#define MT8173_MUTEX_MOD_DISP_UFOE 22
115#define MT8173_MUTEX_MOD_DISP_PWM0 23
116#define MT8173_MUTEX_MOD_DISP_PWM1 24
117#define MT8173_MUTEX_MOD_DISP_OD 25
118
119#define MT8195_MUTEX_MOD_DISP_OVL0 0
120#define MT8195_MUTEX_MOD_DISP_WDMA0 1
121#define MT8195_MUTEX_MOD_DISP_RDMA0 2
122#define MT8195_MUTEX_MOD_DISP_COLOR0 3
123#define MT8195_MUTEX_MOD_DISP_CCORR0 4
124#define MT8195_MUTEX_MOD_DISP_AAL0 5
125#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
126#define MT8195_MUTEX_MOD_DISP_DITHER0 7
127#define MT8195_MUTEX_MOD_DISP_DSI0 8
128#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
129#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
130#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
131#define MT8195_MUTEX_MOD_DISP_PWM0 27
132
133#define MT8365_MUTEX_MOD_DISP_OVL0 7
134#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
135#define MT8365_MUTEX_MOD_DISP_RDMA0 9
136#define MT8365_MUTEX_MOD_DISP_RDMA1 10
137#define MT8365_MUTEX_MOD_DISP_WDMA0 11
138#define MT8365_MUTEX_MOD_DISP_COLOR0 12
139#define MT8365_MUTEX_MOD_DISP_CCORR 13
140#define MT8365_MUTEX_MOD_DISP_AAL 14
141#define MT8365_MUTEX_MOD_DISP_GAMMA 15
142#define MT8365_MUTEX_MOD_DISP_DITHER 16
143#define MT8365_MUTEX_MOD_DISP_DSI0 17
144#define MT8365_MUTEX_MOD_DISP_PWM0 20
145#define MT8365_MUTEX_MOD_DISP_DPI0 22
146
147#define MT2712_MUTEX_MOD_DISP_PWM2 10
148#define MT2712_MUTEX_MOD_DISP_OVL0 11
149#define MT2712_MUTEX_MOD_DISP_OVL1 12
150#define MT2712_MUTEX_MOD_DISP_RDMA0 13
151#define MT2712_MUTEX_MOD_DISP_RDMA1 14
152#define MT2712_MUTEX_MOD_DISP_RDMA2 15
153#define MT2712_MUTEX_MOD_DISP_WDMA0 16
154#define MT2712_MUTEX_MOD_DISP_WDMA1 17
155#define MT2712_MUTEX_MOD_DISP_COLOR0 18
156#define MT2712_MUTEX_MOD_DISP_COLOR1 19
157#define MT2712_MUTEX_MOD_DISP_AAL0 20
158#define MT2712_MUTEX_MOD_DISP_UFOE 22
159#define MT2712_MUTEX_MOD_DISP_PWM0 23
160#define MT2712_MUTEX_MOD_DISP_PWM1 24
161#define MT2712_MUTEX_MOD_DISP_OD0 25
162#define MT2712_MUTEX_MOD2_DISP_AAL1 33
163#define MT2712_MUTEX_MOD2_DISP_OD1 34
164
165#define MT2701_MUTEX_MOD_DISP_OVL 3
166#define MT2701_MUTEX_MOD_DISP_WDMA 6
167#define MT2701_MUTEX_MOD_DISP_COLOR 7
168#define MT2701_MUTEX_MOD_DISP_BLS 9
169#define MT2701_MUTEX_MOD_DISP_RDMA0 10
170#define MT2701_MUTEX_MOD_DISP_RDMA1 12
171
172#define MT2712_MUTEX_SOF_SINGLE_MODE 0
173#define MT2712_MUTEX_SOF_DSI0 1
174#define MT2712_MUTEX_SOF_DSI1 2
175#define MT2712_MUTEX_SOF_DPI0 3
176#define MT2712_MUTEX_SOF_DPI1 4
177#define MT2712_MUTEX_SOF_DSI2 5
178#define MT2712_MUTEX_SOF_DSI3 6
179#define MT8167_MUTEX_SOF_DPI0 2
180#define MT8167_MUTEX_SOF_DPI1 3
181#define MT8183_MUTEX_SOF_DSI0 1
182#define MT8183_MUTEX_SOF_DPI0 2
183#define MT8195_MUTEX_SOF_DSI0 1
184#define MT8195_MUTEX_SOF_DSI1 2
185#define MT8195_MUTEX_SOF_DP_INTF0 3
186#define MT8195_MUTEX_SOF_DP_INTF1 4
187#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
188#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
189
190#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
191#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
192#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
193#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
194#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
195#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
196#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
197#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
198
199struct mtk_mutex {
200 int id;
201 bool claimed;
202};
203
204enum mtk_mutex_sof_id {
205 MUTEX_SOF_SINGLE_MODE,
206 MUTEX_SOF_DSI0,
207 MUTEX_SOF_DSI1,
208 MUTEX_SOF_DPI0,
209 MUTEX_SOF_DPI1,
210 MUTEX_SOF_DSI2,
211 MUTEX_SOF_DSI3,
212 MUTEX_SOF_DP_INTF0,
213 MUTEX_SOF_DP_INTF1,
214 DDP_MUTEX_SOF_MAX,
215};
216
217struct mtk_mutex_data {
218 const unsigned int *mutex_mod;
219 const unsigned int *mutex_sof;
220 const unsigned int mutex_mod_reg;
221 const unsigned int mutex_sof_reg;
222 const unsigned int *mutex_table_mod;
223 const bool no_clk;
224};
225
226struct mtk_mutex_ctx {
227 struct device *dev;
228 struct clk *clk;
229 void __iomem *regs;
230 struct mtk_mutex mutex[10];
231 const struct mtk_mutex_data *data;
232 phys_addr_t addr;
233 struct cmdq_client_reg cmdq_reg;
234};
235
236static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
237 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
238 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
239 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
240 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
241 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
242 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
243};
244
245static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
246 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
247 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
248 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
249 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
250 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
251 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
252 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
253 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
254 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
255 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
256 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
257 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
258 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
259 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
260 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
261 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
262 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
263};
264
265static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
266 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
267 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
268 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
269 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
270 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
271 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
272 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
273 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
274 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
275 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
276 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
277 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
278};
279
280static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
281 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
282 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
283 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
284 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
285 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
286 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
287 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
288 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
289 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
290 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
291 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
292 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
293 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
294 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
295 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
296};
297
298static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
299 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
300 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
301 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
302 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
303 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
304 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
305 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
306 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
307 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
308 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
309 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
310};
311
312static const unsigned int mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
313 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
314 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
315 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
316 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
317 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
318 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
319 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
320 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
321};
322
323static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
324 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
325 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
326 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
327 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
328 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
329 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
330 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
331 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
332 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
333 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
334};
335
336static const unsigned int mt8186_mdp_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
337 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8186_MUTEX_MOD_MDP_RDMA0,
338 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8186_MUTEX_MOD_MDP_RSZ0,
339 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8186_MUTEX_MOD_MDP_RSZ1,
340 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8186_MUTEX_MOD_MDP_TDSHP0,
341 [MUTEX_MOD_IDX_MDP_WROT0] = MT8186_MUTEX_MOD_MDP_WROT0,
342 [MUTEX_MOD_IDX_MDP_HDR0] = MT8186_MUTEX_MOD_MDP_HDR0,
343 [MUTEX_MOD_IDX_MDP_AAL0] = MT8186_MUTEX_MOD_MDP_AAL0,
344 [MUTEX_MOD_IDX_MDP_COLOR0] = MT8186_MUTEX_MOD_MDP_COLOR0,
345};
346
347static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
348 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
349 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
350 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
351 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
352 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
353 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
354 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
355 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
356 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
357 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
358 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
359};
360
361static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
362 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
363 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
364 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
365 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
366 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
367 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
368 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
369 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
370 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
371 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
372 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
373 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
374 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
375};
376
377static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
378 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
379 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
380 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
381 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER,
382 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
383 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
384 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
385 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
386 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
387 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
388 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
389 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
390 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
391};
392
393static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
394 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
395 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
396 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
397 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
398 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1,
399 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
400 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
401};
402
403static const unsigned int mt6795_mutex_sof[DDP_MUTEX_SOF_MAX] = {
404 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
405 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
406 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
407 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
408};
409
410static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
411 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
412 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
413 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
414 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
415};
416
417/* Add EOF setting so overlay hardware can receive frame done irq */
418static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
419 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
420 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
421 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
422};
423
424static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
425 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
426 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
427 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
428};
429
430/*
431 * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
432 * select the EOF source and configure the EOF plus timing from the
433 * module that provides the timing signal.
434 * So that MUTEX can not only send a STREAM_DONE event to GCE
435 * but also detect the error at end of frame(EAEOF) when EOF signal
436 * arrives.
437 */
438static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
439 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
440 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
441 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
442 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
443 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
444 [MUTEX_SOF_DP_INTF0] =
445 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
446 [MUTEX_SOF_DP_INTF1] =
447 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
448};
449
450static const struct mtk_mutex_data mt2701_mutex_driver_data = {
451 .mutex_mod = mt2701_mutex_mod,
452 .mutex_sof = mt2712_mutex_sof,
453 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
454 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
455};
456
457static const struct mtk_mutex_data mt2712_mutex_driver_data = {
458 .mutex_mod = mt2712_mutex_mod,
459 .mutex_sof = mt2712_mutex_sof,
460 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
461 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
462};
463
464static const struct mtk_mutex_data mt6795_mutex_driver_data = {
465 .mutex_mod = mt8173_mutex_mod,
466 .mutex_sof = mt6795_mutex_sof,
467 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
468 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
469};
470
471static const struct mtk_mutex_data mt8167_mutex_driver_data = {
472 .mutex_mod = mt8167_mutex_mod,
473 .mutex_sof = mt8167_mutex_sof,
474 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
475 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
476 .no_clk = true,
477};
478
479static const struct mtk_mutex_data mt8173_mutex_driver_data = {
480 .mutex_mod = mt8173_mutex_mod,
481 .mutex_sof = mt2712_mutex_sof,
482 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
483 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
484};
485
486static const struct mtk_mutex_data mt8183_mutex_driver_data = {
487 .mutex_mod = mt8183_mutex_mod,
488 .mutex_sof = mt8183_mutex_sof,
489 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
490 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
491 .mutex_table_mod = mt8183_mutex_table_mod,
492 .no_clk = true,
493};
494
495static const struct mtk_mutex_data mt8186_mdp_mutex_driver_data = {
496 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
497 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
498 .mutex_table_mod = mt8186_mdp_mutex_table_mod,
499};
500
501static const struct mtk_mutex_data mt8186_mutex_driver_data = {
502 .mutex_mod = mt8186_mutex_mod,
503 .mutex_sof = mt8186_mutex_sof,
504 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
505 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
506};
507
508static const struct mtk_mutex_data mt8192_mutex_driver_data = {
509 .mutex_mod = mt8192_mutex_mod,
510 .mutex_sof = mt8183_mutex_sof,
511 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
512 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
513};
514
515static const struct mtk_mutex_data mt8195_mutex_driver_data = {
516 .mutex_mod = mt8195_mutex_mod,
517 .mutex_sof = mt8195_mutex_sof,
518 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
519 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
520};
521
522static const struct mtk_mutex_data mt8365_mutex_driver_data = {
523 .mutex_mod = mt8365_mutex_mod,
524 .mutex_sof = mt8183_mutex_sof,
525 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
526 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
527 .no_clk = true,
528};
529
530struct mtk_mutex *mtk_mutex_get(struct device *dev)
531{
532 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
533 int i;
534
535 for (i = 0; i < 10; i++)
536 if (!mtx->mutex[i].claimed) {
537 mtx->mutex[i].claimed = true;
538 return &mtx->mutex[i];
539 }
540
541 return ERR_PTR(-EBUSY);
542}
543EXPORT_SYMBOL_GPL(mtk_mutex_get);
544
545void mtk_mutex_put(struct mtk_mutex *mutex)
546{
547 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
548 mutex[mutex->id]);
549
550 WARN_ON(&mtx->mutex[mutex->id] != mutex);
551
552 mutex->claimed = false;
553}
554EXPORT_SYMBOL_GPL(mtk_mutex_put);
555
556int mtk_mutex_prepare(struct mtk_mutex *mutex)
557{
558 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
559 mutex[mutex->id]);
560 return clk_prepare_enable(mtx->clk);
561}
562EXPORT_SYMBOL_GPL(mtk_mutex_prepare);
563
564void mtk_mutex_unprepare(struct mtk_mutex *mutex)
565{
566 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
567 mutex[mutex->id]);
568 clk_disable_unprepare(mtx->clk);
569}
570EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
571
572void mtk_mutex_add_comp(struct mtk_mutex *mutex,
573 enum mtk_ddp_comp_id id)
574{
575 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
576 mutex[mutex->id]);
577 unsigned int reg;
578 unsigned int sof_id;
579 unsigned int offset;
580
581 WARN_ON(&mtx->mutex[mutex->id] != mutex);
582
583 switch (id) {
584 case DDP_COMPONENT_DSI0:
585 sof_id = MUTEX_SOF_DSI0;
586 break;
587 case DDP_COMPONENT_DSI1:
588 sof_id = MUTEX_SOF_DSI0;
589 break;
590 case DDP_COMPONENT_DSI2:
591 sof_id = MUTEX_SOF_DSI2;
592 break;
593 case DDP_COMPONENT_DSI3:
594 sof_id = MUTEX_SOF_DSI3;
595 break;
596 case DDP_COMPONENT_DPI0:
597 sof_id = MUTEX_SOF_DPI0;
598 break;
599 case DDP_COMPONENT_DPI1:
600 sof_id = MUTEX_SOF_DPI1;
601 break;
602 case DDP_COMPONENT_DP_INTF0:
603 sof_id = MUTEX_SOF_DP_INTF0;
604 break;
605 default:
606 if (mtx->data->mutex_mod[id] < 32) {
607 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
608 mutex->id);
609 reg = readl_relaxed(mtx->regs + offset);
610 reg |= 1 << mtx->data->mutex_mod[id];
611 writel_relaxed(reg, mtx->regs + offset);
612 } else {
613 offset = DISP_REG_MUTEX_MOD2(mutex->id);
614 reg = readl_relaxed(mtx->regs + offset);
615 reg |= 1 << (mtx->data->mutex_mod[id] - 32);
616 writel_relaxed(reg, mtx->regs + offset);
617 }
618 return;
619 }
620
621 writel_relaxed(mtx->data->mutex_sof[sof_id],
622 mtx->regs +
623 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
624}
625EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
626
627void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
628 enum mtk_ddp_comp_id id)
629{
630 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
631 mutex[mutex->id]);
632 unsigned int reg;
633 unsigned int offset;
634
635 WARN_ON(&mtx->mutex[mutex->id] != mutex);
636
637 switch (id) {
638 case DDP_COMPONENT_DSI0:
639 case DDP_COMPONENT_DSI1:
640 case DDP_COMPONENT_DSI2:
641 case DDP_COMPONENT_DSI3:
642 case DDP_COMPONENT_DPI0:
643 case DDP_COMPONENT_DPI1:
644 case DDP_COMPONENT_DP_INTF0:
645 writel_relaxed(MUTEX_SOF_SINGLE_MODE,
646 mtx->regs +
647 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
648 mutex->id));
649 break;
650 default:
651 if (mtx->data->mutex_mod[id] < 32) {
652 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
653 mutex->id);
654 reg = readl_relaxed(mtx->regs + offset);
655 reg &= ~(1 << mtx->data->mutex_mod[id]);
656 writel_relaxed(reg, mtx->regs + offset);
657 } else {
658 offset = DISP_REG_MUTEX_MOD2(mutex->id);
659 reg = readl_relaxed(mtx->regs + offset);
660 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
661 writel_relaxed(reg, mtx->regs + offset);
662 }
663 break;
664 }
665}
666EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
667
668void mtk_mutex_enable(struct mtk_mutex *mutex)
669{
670 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
671 mutex[mutex->id]);
672
673 WARN_ON(&mtx->mutex[mutex->id] != mutex);
674
675 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
676}
677EXPORT_SYMBOL_GPL(mtk_mutex_enable);
678
679int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
680{
681 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
682 mutex[mutex->id]);
683#if IS_REACHABLE(CONFIG_MTK_CMDQ)
684 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;
685
686 WARN_ON(&mtx->mutex[mutex->id] != mutex);
687
688 if (!mtx->cmdq_reg.size) {
689 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set");
690 return -EINVAL;
691 }
692
693 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,
694 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1);
695 return 0;
696#else
697 dev_err(mtx->dev, "Not support for enable MUTEX by CMDQ");
698 return -ENODEV;
699#endif
700}
701EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
702
703void mtk_mutex_disable(struct mtk_mutex *mutex)
704{
705 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
706 mutex[mutex->id]);
707
708 WARN_ON(&mtx->mutex[mutex->id] != mutex);
709
710 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
711}
712EXPORT_SYMBOL_GPL(mtk_mutex_disable);
713
714void mtk_mutex_acquire(struct mtk_mutex *mutex)
715{
716 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
717 mutex[mutex->id]);
718 u32 tmp;
719
720 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
721 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id));
722 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id),
723 tmp, tmp & INT_MUTEX, 1, 10000))
724 pr_err("could not acquire mutex %d\n", mutex->id);
725}
726EXPORT_SYMBOL_GPL(mtk_mutex_acquire);
727
728void mtk_mutex_release(struct mtk_mutex *mutex)
729{
730 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
731 mutex[mutex->id]);
732
733 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id));
734}
735EXPORT_SYMBOL_GPL(mtk_mutex_release);
736
737int mtk_mutex_write_mod(struct mtk_mutex *mutex,
738 enum mtk_mutex_mod_index idx, bool clear)
739{
740 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
741 mutex[mutex->id]);
742 unsigned int reg;
743 unsigned int offset;
744
745 WARN_ON(&mtx->mutex[mutex->id] != mutex);
746
747 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 ||
748 idx >= MUTEX_MOD_IDX_MAX) {
749 dev_err(mtx->dev, "Not supported MOD table index : %d", idx);
750 return -EINVAL;
751 }
752
753 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
754 mutex->id);
755 reg = readl_relaxed(mtx->regs + offset);
756
757 if (clear)
758 reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
759 else
760 reg |= BIT(mtx->data->mutex_table_mod[idx]);
761
762 writel_relaxed(reg, mtx->regs + offset);
763
764 return 0;
765}
766EXPORT_SYMBOL_GPL(mtk_mutex_write_mod);
767
768int mtk_mutex_write_sof(struct mtk_mutex *mutex,
769 enum mtk_mutex_sof_index idx)
770{
771 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
772 mutex[mutex->id]);
773
774 WARN_ON(&mtx->mutex[mutex->id] != mutex);
775
776 if (idx < MUTEX_SOF_IDX_SINGLE_MODE ||
777 idx >= MUTEX_SOF_IDX_MAX) {
778 dev_err(mtx->dev, "Not supported SOF index : %d", idx);
779 return -EINVAL;
780 }
781
782 writel_relaxed(idx, mtx->regs +
783 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
784
785 return 0;
786}
787EXPORT_SYMBOL_GPL(mtk_mutex_write_sof);
788
789static int mtk_mutex_probe(struct platform_device *pdev)
790{
791 struct device *dev = &pdev->dev;
792 struct mtk_mutex_ctx *mtx;
793 struct resource *regs;
794 int i;
795#if IS_REACHABLE(CONFIG_MTK_CMDQ)
796 int ret;
797#endif
798
799 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
800 if (!mtx)
801 return -ENOMEM;
802
803 for (i = 0; i < 10; i++)
804 mtx->mutex[i].id = i;
805
806 mtx->data = of_device_get_match_data(dev);
807
808 if (!mtx->data->no_clk) {
809 mtx->clk = devm_clk_get(dev, NULL);
810 if (IS_ERR(mtx->clk)) {
811 if (PTR_ERR(mtx->clk) != -EPROBE_DEFER)
812 dev_err(dev, "Failed to get clock\n");
813 return PTR_ERR(mtx->clk);
814 }
815 }
816
817 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
818 if (IS_ERR(mtx->regs)) {
819 dev_err(dev, "Failed to map mutex registers\n");
820 return PTR_ERR(mtx->regs);
821 }
822 mtx->addr = regs->start;
823
824#if IS_REACHABLE(CONFIG_MTK_CMDQ)
825 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
826 if (ret)
827 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
828#endif
829
830 platform_set_drvdata(pdev, mtx);
831
832 return 0;
833}
834
835static int mtk_mutex_remove(struct platform_device *pdev)
836{
837 return 0;
838}
839
840static const struct of_device_id mutex_driver_dt_match[] = {
841 { .compatible = "mediatek,mt2701-disp-mutex",
842 .data = &mt2701_mutex_driver_data},
843 { .compatible = "mediatek,mt2712-disp-mutex",
844 .data = &mt2712_mutex_driver_data},
845 { .compatible = "mediatek,mt6795-disp-mutex",
846 .data = &mt6795_mutex_driver_data},
847 { .compatible = "mediatek,mt8167-disp-mutex",
848 .data = &mt8167_mutex_driver_data},
849 { .compatible = "mediatek,mt8173-disp-mutex",
850 .data = &mt8173_mutex_driver_data},
851 { .compatible = "mediatek,mt8183-disp-mutex",
852 .data = &mt8183_mutex_driver_data},
853 { .compatible = "mediatek,mt8186-disp-mutex",
854 .data = &mt8186_mutex_driver_data},
855 { .compatible = "mediatek,mt8186-mdp3-mutex",
856 .data = &mt8186_mdp_mutex_driver_data},
857 { .compatible = "mediatek,mt8192-disp-mutex",
858 .data = &mt8192_mutex_driver_data},
859 { .compatible = "mediatek,mt8195-disp-mutex",
860 .data = &mt8195_mutex_driver_data},
861 { .compatible = "mediatek,mt8365-disp-mutex",
862 .data = &mt8365_mutex_driver_data},
863 {},
864};
865MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
866
867static struct platform_driver mtk_mutex_driver = {
868 .probe = mtk_mutex_probe,
869 .remove = mtk_mutex_remove,
870 .driver = {
871 .name = "mediatek-mutex",
872 .owner = THIS_MODULE,
873 .of_match_table = mutex_driver_dt_match,
874 },
875};
876
877builtin_platform_driver(mtk_mutex_driver);