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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2022 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10#include "mpi3mr.h"
11#include <linux/io-64-nonatomic-lo-hi.h>
12
13static int
14mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type, u32 reset_reason);
15static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc);
16static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
17 struct mpi3_ioc_facts_data *facts_data);
18static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
19 struct mpi3mr_drv_cmd *drv_cmd);
20
21static int poll_queues;
22module_param(poll_queues, int, 0444);
23MODULE_PARM_DESC(poll_queues, "Number of queues for io_uring poll mode. (Range 1 - 126)");
24
25#if defined(writeq) && defined(CONFIG_64BIT)
26static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
27{
28 writeq(b, addr);
29}
30#else
31static inline void mpi3mr_writeq(__u64 b, volatile void __iomem *addr)
32{
33 __u64 data_out = b;
34
35 writel((u32)(data_out), addr);
36 writel((u32)(data_out >> 32), (addr + 4));
37}
38#endif
39
40static inline bool
41mpi3mr_check_req_qfull(struct op_req_qinfo *op_req_q)
42{
43 u16 pi, ci, max_entries;
44 bool is_qfull = false;
45
46 pi = op_req_q->pi;
47 ci = READ_ONCE(op_req_q->ci);
48 max_entries = op_req_q->num_requests;
49
50 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1))))
51 is_qfull = true;
52
53 return is_qfull;
54}
55
56static void mpi3mr_sync_irqs(struct mpi3mr_ioc *mrioc)
57{
58 u16 i, max_vectors;
59
60 max_vectors = mrioc->intr_info_count;
61
62 for (i = 0; i < max_vectors; i++)
63 synchronize_irq(pci_irq_vector(mrioc->pdev, i));
64}
65
66void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc)
67{
68 mrioc->intr_enabled = 0;
69 mpi3mr_sync_irqs(mrioc);
70}
71
72void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc)
73{
74 mrioc->intr_enabled = 1;
75}
76
77static void mpi3mr_cleanup_isr(struct mpi3mr_ioc *mrioc)
78{
79 u16 i;
80
81 mpi3mr_ioc_disable_intr(mrioc);
82
83 if (!mrioc->intr_info)
84 return;
85
86 for (i = 0; i < mrioc->intr_info_count; i++)
87 free_irq(pci_irq_vector(mrioc->pdev, i),
88 (mrioc->intr_info + i));
89
90 kfree(mrioc->intr_info);
91 mrioc->intr_info = NULL;
92 mrioc->intr_info_count = 0;
93 mrioc->is_intr_info_set = false;
94 pci_free_irq_vectors(mrioc->pdev);
95}
96
97void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
98 dma_addr_t dma_addr)
99{
100 struct mpi3_sge_common *sgel = paddr;
101
102 sgel->flags = flags;
103 sgel->length = cpu_to_le32(length);
104 sgel->address = cpu_to_le64(dma_addr);
105}
106
107void mpi3mr_build_zero_len_sge(void *paddr)
108{
109 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
110
111 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1);
112}
113
114void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
115 dma_addr_t phys_addr)
116{
117 if (!phys_addr)
118 return NULL;
119
120 if ((phys_addr < mrioc->reply_buf_dma) ||
121 (phys_addr > mrioc->reply_buf_dma_max_address))
122 return NULL;
123
124 return mrioc->reply_buf + (phys_addr - mrioc->reply_buf_dma);
125}
126
127void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
128 dma_addr_t phys_addr)
129{
130 if (!phys_addr)
131 return NULL;
132
133 return mrioc->sense_buf + (phys_addr - mrioc->sense_buf_dma);
134}
135
136static void mpi3mr_repost_reply_buf(struct mpi3mr_ioc *mrioc,
137 u64 reply_dma)
138{
139 u32 old_idx = 0;
140 unsigned long flags;
141
142 spin_lock_irqsave(&mrioc->reply_free_queue_lock, flags);
143 old_idx = mrioc->reply_free_queue_host_index;
144 mrioc->reply_free_queue_host_index = (
145 (mrioc->reply_free_queue_host_index ==
146 (mrioc->reply_free_qsz - 1)) ? 0 :
147 (mrioc->reply_free_queue_host_index + 1));
148 mrioc->reply_free_q[old_idx] = cpu_to_le64(reply_dma);
149 writel(mrioc->reply_free_queue_host_index,
150 &mrioc->sysif_regs->reply_free_host_index);
151 spin_unlock_irqrestore(&mrioc->reply_free_queue_lock, flags);
152}
153
154void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
155 u64 sense_buf_dma)
156{
157 u32 old_idx = 0;
158 unsigned long flags;
159
160 spin_lock_irqsave(&mrioc->sbq_lock, flags);
161 old_idx = mrioc->sbq_host_index;
162 mrioc->sbq_host_index = ((mrioc->sbq_host_index ==
163 (mrioc->sense_buf_q_sz - 1)) ? 0 :
164 (mrioc->sbq_host_index + 1));
165 mrioc->sense_buf_q[old_idx] = cpu_to_le64(sense_buf_dma);
166 writel(mrioc->sbq_host_index,
167 &mrioc->sysif_regs->sense_buffer_free_host_index);
168 spin_unlock_irqrestore(&mrioc->sbq_lock, flags);
169}
170
171static void mpi3mr_print_event_data(struct mpi3mr_ioc *mrioc,
172 struct mpi3_event_notification_reply *event_reply)
173{
174 char *desc = NULL;
175 u16 event;
176
177 event = event_reply->event;
178
179 switch (event) {
180 case MPI3_EVENT_LOG_DATA:
181 desc = "Log Data";
182 break;
183 case MPI3_EVENT_CHANGE:
184 desc = "Event Change";
185 break;
186 case MPI3_EVENT_GPIO_INTERRUPT:
187 desc = "GPIO Interrupt";
188 break;
189 case MPI3_EVENT_CABLE_MGMT:
190 desc = "Cable Management";
191 break;
192 case MPI3_EVENT_ENERGY_PACK_CHANGE:
193 desc = "Energy Pack Change";
194 break;
195 case MPI3_EVENT_DEVICE_ADDED:
196 {
197 struct mpi3_device_page0 *event_data =
198 (struct mpi3_device_page0 *)event_reply->event_data;
199 ioc_info(mrioc, "Device Added: dev=0x%04x Form=0x%x\n",
200 event_data->dev_handle, event_data->device_form);
201 return;
202 }
203 case MPI3_EVENT_DEVICE_INFO_CHANGED:
204 {
205 struct mpi3_device_page0 *event_data =
206 (struct mpi3_device_page0 *)event_reply->event_data;
207 ioc_info(mrioc, "Device Info Changed: dev=0x%04x Form=0x%x\n",
208 event_data->dev_handle, event_data->device_form);
209 return;
210 }
211 case MPI3_EVENT_DEVICE_STATUS_CHANGE:
212 {
213 struct mpi3_event_data_device_status_change *event_data =
214 (struct mpi3_event_data_device_status_change *)event_reply->event_data;
215 ioc_info(mrioc, "Device status Change: dev=0x%04x RC=0x%x\n",
216 event_data->dev_handle, event_data->reason_code);
217 return;
218 }
219 case MPI3_EVENT_SAS_DISCOVERY:
220 {
221 struct mpi3_event_data_sas_discovery *event_data =
222 (struct mpi3_event_data_sas_discovery *)event_reply->event_data;
223 ioc_info(mrioc, "SAS Discovery: (%s) status (0x%08x)\n",
224 (event_data->reason_code == MPI3_EVENT_SAS_DISC_RC_STARTED) ?
225 "start" : "stop",
226 le32_to_cpu(event_data->discovery_status));
227 return;
228 }
229 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE:
230 desc = "SAS Broadcast Primitive";
231 break;
232 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE:
233 desc = "SAS Notify Primitive";
234 break;
235 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
236 desc = "SAS Init Device Status Change";
237 break;
238 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW:
239 desc = "SAS Init Table Overflow";
240 break;
241 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
242 desc = "SAS Topology Change List";
243 break;
244 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE:
245 desc = "Enclosure Device Status Change";
246 break;
247 case MPI3_EVENT_ENCL_DEVICE_ADDED:
248 desc = "Enclosure Added";
249 break;
250 case MPI3_EVENT_HARD_RESET_RECEIVED:
251 desc = "Hard Reset Received";
252 break;
253 case MPI3_EVENT_SAS_PHY_COUNTER:
254 desc = "SAS PHY Counter";
255 break;
256 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
257 desc = "SAS Device Discovery Error";
258 break;
259 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
260 desc = "PCIE Topology Change List";
261 break;
262 case MPI3_EVENT_PCIE_ENUMERATION:
263 {
264 struct mpi3_event_data_pcie_enumeration *event_data =
265 (struct mpi3_event_data_pcie_enumeration *)event_reply->event_data;
266 ioc_info(mrioc, "PCIE Enumeration: (%s)",
267 (event_data->reason_code ==
268 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : "stop");
269 if (event_data->enumeration_status)
270 ioc_info(mrioc, "enumeration_status(0x%08x)\n",
271 le32_to_cpu(event_data->enumeration_status));
272 return;
273 }
274 case MPI3_EVENT_PREPARE_FOR_RESET:
275 desc = "Prepare For Reset";
276 break;
277 }
278
279 if (!desc)
280 return;
281
282 ioc_info(mrioc, "%s\n", desc);
283}
284
285static void mpi3mr_handle_events(struct mpi3mr_ioc *mrioc,
286 struct mpi3_default_reply *def_reply)
287{
288 struct mpi3_event_notification_reply *event_reply =
289 (struct mpi3_event_notification_reply *)def_reply;
290
291 mrioc->change_count = le16_to_cpu(event_reply->ioc_change_count);
292 mpi3mr_print_event_data(mrioc, event_reply);
293 mpi3mr_os_handle_events(mrioc, event_reply);
294}
295
296static struct mpi3mr_drv_cmd *
297mpi3mr_get_drv_cmd(struct mpi3mr_ioc *mrioc, u16 host_tag,
298 struct mpi3_default_reply *def_reply)
299{
300 u16 idx;
301
302 switch (host_tag) {
303 case MPI3MR_HOSTTAG_INITCMDS:
304 return &mrioc->init_cmds;
305 case MPI3MR_HOSTTAG_CFG_CMDS:
306 return &mrioc->cfg_cmds;
307 case MPI3MR_HOSTTAG_BSG_CMDS:
308 return &mrioc->bsg_cmds;
309 case MPI3MR_HOSTTAG_BLK_TMS:
310 return &mrioc->host_tm_cmds;
311 case MPI3MR_HOSTTAG_PEL_ABORT:
312 return &mrioc->pel_abort_cmd;
313 case MPI3MR_HOSTTAG_PEL_WAIT:
314 return &mrioc->pel_cmds;
315 case MPI3MR_HOSTTAG_TRANSPORT_CMDS:
316 return &mrioc->transport_cmds;
317 case MPI3MR_HOSTTAG_INVALID:
318 if (def_reply && def_reply->function ==
319 MPI3_FUNCTION_EVENT_NOTIFICATION)
320 mpi3mr_handle_events(mrioc, def_reply);
321 return NULL;
322 default:
323 break;
324 }
325 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN &&
326 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX) {
327 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN;
328 return &mrioc->dev_rmhs_cmds[idx];
329 }
330
331 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN &&
332 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) {
333 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN;
334 return &mrioc->evtack_cmds[idx];
335 }
336
337 return NULL;
338}
339
340static void mpi3mr_process_admin_reply_desc(struct mpi3mr_ioc *mrioc,
341 struct mpi3_default_reply_descriptor *reply_desc, u64 *reply_dma)
342{
343 u16 reply_desc_type, host_tag = 0;
344 u16 ioc_status = MPI3_IOCSTATUS_SUCCESS;
345 u32 ioc_loginfo = 0;
346 struct mpi3_status_reply_descriptor *status_desc;
347 struct mpi3_address_reply_descriptor *addr_desc;
348 struct mpi3_success_reply_descriptor *success_desc;
349 struct mpi3_default_reply *def_reply = NULL;
350 struct mpi3mr_drv_cmd *cmdptr = NULL;
351 struct mpi3_scsi_io_reply *scsi_reply;
352 u8 *sense_buf = NULL;
353
354 *reply_dma = 0;
355 reply_desc_type = le16_to_cpu(reply_desc->reply_flags) &
356 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK;
357 switch (reply_desc_type) {
358 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS:
359 status_desc = (struct mpi3_status_reply_descriptor *)reply_desc;
360 host_tag = le16_to_cpu(status_desc->host_tag);
361 ioc_status = le16_to_cpu(status_desc->ioc_status);
362 if (ioc_status &
363 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
364 ioc_loginfo = le32_to_cpu(status_desc->ioc_log_info);
365 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
366 break;
367 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY:
368 addr_desc = (struct mpi3_address_reply_descriptor *)reply_desc;
369 *reply_dma = le64_to_cpu(addr_desc->reply_frame_address);
370 def_reply = mpi3mr_get_reply_virt_addr(mrioc, *reply_dma);
371 if (!def_reply)
372 goto out;
373 host_tag = le16_to_cpu(def_reply->host_tag);
374 ioc_status = le16_to_cpu(def_reply->ioc_status);
375 if (ioc_status &
376 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL)
377 ioc_loginfo = le32_to_cpu(def_reply->ioc_log_info);
378 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK;
379 if (def_reply->function == MPI3_FUNCTION_SCSI_IO) {
380 scsi_reply = (struct mpi3_scsi_io_reply *)def_reply;
381 sense_buf = mpi3mr_get_sensebuf_virt_addr(mrioc,
382 le64_to_cpu(scsi_reply->sense_data_buffer_address));
383 }
384 break;
385 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS:
386 success_desc = (struct mpi3_success_reply_descriptor *)reply_desc;
387 host_tag = le16_to_cpu(success_desc->host_tag);
388 break;
389 default:
390 break;
391 }
392
393 cmdptr = mpi3mr_get_drv_cmd(mrioc, host_tag, def_reply);
394 if (cmdptr) {
395 if (cmdptr->state & MPI3MR_CMD_PENDING) {
396 cmdptr->state |= MPI3MR_CMD_COMPLETE;
397 cmdptr->ioc_loginfo = ioc_loginfo;
398 cmdptr->ioc_status = ioc_status;
399 cmdptr->state &= ~MPI3MR_CMD_PENDING;
400 if (def_reply) {
401 cmdptr->state |= MPI3MR_CMD_REPLY_VALID;
402 memcpy((u8 *)cmdptr->reply, (u8 *)def_reply,
403 mrioc->reply_sz);
404 }
405 if (cmdptr->is_waiting) {
406 complete(&cmdptr->done);
407 cmdptr->is_waiting = 0;
408 } else if (cmdptr->callback)
409 cmdptr->callback(mrioc, cmdptr);
410 }
411 }
412out:
413 if (sense_buf)
414 mpi3mr_repost_sense_buf(mrioc,
415 le64_to_cpu(scsi_reply->sense_data_buffer_address));
416}
417
418static int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc)
419{
420 u32 exp_phase = mrioc->admin_reply_ephase;
421 u32 admin_reply_ci = mrioc->admin_reply_ci;
422 u32 num_admin_replies = 0;
423 u64 reply_dma = 0;
424 struct mpi3_default_reply_descriptor *reply_desc;
425
426 reply_desc = (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
427 admin_reply_ci;
428
429 if ((le16_to_cpu(reply_desc->reply_flags) &
430 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
431 return 0;
432
433 do {
434 if (mrioc->unrecoverable)
435 break;
436
437 mrioc->admin_req_ci = le16_to_cpu(reply_desc->request_queue_ci);
438 mpi3mr_process_admin_reply_desc(mrioc, reply_desc, &reply_dma);
439 if (reply_dma)
440 mpi3mr_repost_reply_buf(mrioc, reply_dma);
441 num_admin_replies++;
442 if (++admin_reply_ci == mrioc->num_admin_replies) {
443 admin_reply_ci = 0;
444 exp_phase ^= 1;
445 }
446 reply_desc =
447 (struct mpi3_default_reply_descriptor *)mrioc->admin_reply_base +
448 admin_reply_ci;
449 if ((le16_to_cpu(reply_desc->reply_flags) &
450 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
451 break;
452 } while (1);
453
454 writel(admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
455 mrioc->admin_reply_ci = admin_reply_ci;
456 mrioc->admin_reply_ephase = exp_phase;
457
458 return num_admin_replies;
459}
460
461/**
462 * mpi3mr_get_reply_desc - get reply descriptor frame corresponding to
463 * queue's consumer index from operational reply descriptor queue.
464 * @op_reply_q: op_reply_qinfo object
465 * @reply_ci: operational reply descriptor's queue consumer index
466 *
467 * Returns reply descriptor frame address
468 */
469static inline struct mpi3_default_reply_descriptor *
470mpi3mr_get_reply_desc(struct op_reply_qinfo *op_reply_q, u32 reply_ci)
471{
472 void *segment_base_addr;
473 struct segments *segments = op_reply_q->q_segments;
474 struct mpi3_default_reply_descriptor *reply_desc = NULL;
475
476 segment_base_addr =
477 segments[reply_ci / op_reply_q->segment_qd].segment;
478 reply_desc = (struct mpi3_default_reply_descriptor *)segment_base_addr +
479 (reply_ci % op_reply_q->segment_qd);
480 return reply_desc;
481}
482
483/**
484 * mpi3mr_process_op_reply_q - Operational reply queue handler
485 * @mrioc: Adapter instance reference
486 * @op_reply_q: Operational reply queue info
487 *
488 * Checks the specific operational reply queue and drains the
489 * reply queue entries until the queue is empty and process the
490 * individual reply descriptors.
491 *
492 * Return: 0 if queue is already processed,or number of reply
493 * descriptors processed.
494 */
495int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
496 struct op_reply_qinfo *op_reply_q)
497{
498 struct op_req_qinfo *op_req_q;
499 u32 exp_phase;
500 u32 reply_ci;
501 u32 num_op_reply = 0;
502 u64 reply_dma = 0;
503 struct mpi3_default_reply_descriptor *reply_desc;
504 u16 req_q_idx = 0, reply_qidx;
505
506 reply_qidx = op_reply_q->qid - 1;
507
508 if (!atomic_add_unless(&op_reply_q->in_use, 1, 1))
509 return 0;
510
511 exp_phase = op_reply_q->ephase;
512 reply_ci = op_reply_q->ci;
513
514 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
515 if ((le16_to_cpu(reply_desc->reply_flags) &
516 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) {
517 atomic_dec(&op_reply_q->in_use);
518 return 0;
519 }
520
521 do {
522 if (mrioc->unrecoverable)
523 break;
524
525 req_q_idx = le16_to_cpu(reply_desc->request_queue_id) - 1;
526 op_req_q = &mrioc->req_qinfo[req_q_idx];
527
528 WRITE_ONCE(op_req_q->ci, le16_to_cpu(reply_desc->request_queue_ci));
529 mpi3mr_process_op_reply_desc(mrioc, reply_desc, &reply_dma,
530 reply_qidx);
531 atomic_dec(&op_reply_q->pend_ios);
532 if (reply_dma)
533 mpi3mr_repost_reply_buf(mrioc, reply_dma);
534 num_op_reply++;
535
536 if (++reply_ci == op_reply_q->num_replies) {
537 reply_ci = 0;
538 exp_phase ^= 1;
539 }
540
541 reply_desc = mpi3mr_get_reply_desc(op_reply_q, reply_ci);
542
543 if ((le16_to_cpu(reply_desc->reply_flags) &
544 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase)
545 break;
546#ifndef CONFIG_PREEMPT_RT
547 /*
548 * Exit completion loop to avoid CPU lockup
549 * Ensure remaining completion happens from threaded ISR.
550 */
551 if (num_op_reply > mrioc->max_host_ios) {
552 op_reply_q->enable_irq_poll = true;
553 break;
554 }
555#endif
556 } while (1);
557
558 writel(reply_ci,
559 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].consumer_index);
560 op_reply_q->ci = reply_ci;
561 op_reply_q->ephase = exp_phase;
562
563 atomic_dec(&op_reply_q->in_use);
564 return num_op_reply;
565}
566
567/**
568 * mpi3mr_blk_mq_poll - Operational reply queue handler
569 * @shost: SCSI Host reference
570 * @queue_num: Request queue number (w.r.t OS it is hardware context number)
571 *
572 * Checks the specific operational reply queue and drains the
573 * reply queue entries until the queue is empty and process the
574 * individual reply descriptors.
575 *
576 * Return: 0 if queue is already processed,or number of reply
577 * descriptors processed.
578 */
579int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num)
580{
581 int num_entries = 0;
582 struct mpi3mr_ioc *mrioc;
583
584 mrioc = (struct mpi3mr_ioc *)shost->hostdata;
585
586 if ((mrioc->reset_in_progress || mrioc->prepare_for_reset ||
587 mrioc->unrecoverable))
588 return 0;
589
590 num_entries = mpi3mr_process_op_reply_q(mrioc,
591 &mrioc->op_reply_qinfo[queue_num]);
592
593 return num_entries;
594}
595
596static irqreturn_t mpi3mr_isr_primary(int irq, void *privdata)
597{
598 struct mpi3mr_intr_info *intr_info = privdata;
599 struct mpi3mr_ioc *mrioc;
600 u16 midx;
601 u32 num_admin_replies = 0, num_op_reply = 0;
602
603 if (!intr_info)
604 return IRQ_NONE;
605
606 mrioc = intr_info->mrioc;
607
608 if (!mrioc->intr_enabled)
609 return IRQ_NONE;
610
611 midx = intr_info->msix_index;
612
613 if (!midx)
614 num_admin_replies = mpi3mr_process_admin_reply_q(mrioc);
615 if (intr_info->op_reply_q)
616 num_op_reply = mpi3mr_process_op_reply_q(mrioc,
617 intr_info->op_reply_q);
618
619 if (num_admin_replies || num_op_reply)
620 return IRQ_HANDLED;
621 else
622 return IRQ_NONE;
623}
624
625#ifndef CONFIG_PREEMPT_RT
626
627static irqreturn_t mpi3mr_isr(int irq, void *privdata)
628{
629 struct mpi3mr_intr_info *intr_info = privdata;
630 int ret;
631
632 if (!intr_info)
633 return IRQ_NONE;
634
635 /* Call primary ISR routine */
636 ret = mpi3mr_isr_primary(irq, privdata);
637
638 /*
639 * If more IOs are expected, schedule IRQ polling thread.
640 * Otherwise exit from ISR.
641 */
642 if (!intr_info->op_reply_q)
643 return ret;
644
645 if (!intr_info->op_reply_q->enable_irq_poll ||
646 !atomic_read(&intr_info->op_reply_q->pend_ios))
647 return ret;
648
649 disable_irq_nosync(intr_info->os_irq);
650
651 return IRQ_WAKE_THREAD;
652}
653
654/**
655 * mpi3mr_isr_poll - Reply queue polling routine
656 * @irq: IRQ
657 * @privdata: Interrupt info
658 *
659 * poll for pending I/O completions in a loop until pending I/Os
660 * present or controller queue depth I/Os are processed.
661 *
662 * Return: IRQ_NONE or IRQ_HANDLED
663 */
664static irqreturn_t mpi3mr_isr_poll(int irq, void *privdata)
665{
666 struct mpi3mr_intr_info *intr_info = privdata;
667 struct mpi3mr_ioc *mrioc;
668 u16 midx;
669 u32 num_op_reply = 0;
670
671 if (!intr_info || !intr_info->op_reply_q)
672 return IRQ_NONE;
673
674 mrioc = intr_info->mrioc;
675 midx = intr_info->msix_index;
676
677 /* Poll for pending IOs completions */
678 do {
679 if (!mrioc->intr_enabled || mrioc->unrecoverable)
680 break;
681
682 if (!midx)
683 mpi3mr_process_admin_reply_q(mrioc);
684 if (intr_info->op_reply_q)
685 num_op_reply +=
686 mpi3mr_process_op_reply_q(mrioc,
687 intr_info->op_reply_q);
688
689 usleep_range(MPI3MR_IRQ_POLL_SLEEP, 10 * MPI3MR_IRQ_POLL_SLEEP);
690
691 } while (atomic_read(&intr_info->op_reply_q->pend_ios) &&
692 (num_op_reply < mrioc->max_host_ios));
693
694 intr_info->op_reply_q->enable_irq_poll = false;
695 enable_irq(intr_info->os_irq);
696
697 return IRQ_HANDLED;
698}
699
700#endif
701
702/**
703 * mpi3mr_request_irq - Request IRQ and register ISR
704 * @mrioc: Adapter instance reference
705 * @index: IRQ vector index
706 *
707 * Request threaded ISR with primary ISR and secondary
708 *
709 * Return: 0 on success and non zero on failures.
710 */
711static inline int mpi3mr_request_irq(struct mpi3mr_ioc *mrioc, u16 index)
712{
713 struct pci_dev *pdev = mrioc->pdev;
714 struct mpi3mr_intr_info *intr_info = mrioc->intr_info + index;
715 int retval = 0;
716
717 intr_info->mrioc = mrioc;
718 intr_info->msix_index = index;
719 intr_info->op_reply_q = NULL;
720
721 snprintf(intr_info->name, MPI3MR_NAME_LENGTH, "%s%d-msix%d",
722 mrioc->driver_name, mrioc->id, index);
723
724#ifndef CONFIG_PREEMPT_RT
725 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr,
726 mpi3mr_isr_poll, IRQF_SHARED, intr_info->name, intr_info);
727#else
728 retval = request_threaded_irq(pci_irq_vector(pdev, index), mpi3mr_isr_primary,
729 NULL, IRQF_SHARED, intr_info->name, intr_info);
730#endif
731 if (retval) {
732 ioc_err(mrioc, "%s: Unable to allocate interrupt %d!\n",
733 intr_info->name, pci_irq_vector(pdev, index));
734 return retval;
735 }
736
737 intr_info->os_irq = pci_irq_vector(pdev, index);
738 return retval;
739}
740
741static void mpi3mr_calc_poll_queues(struct mpi3mr_ioc *mrioc, u16 max_vectors)
742{
743 if (!mrioc->requested_poll_qcount)
744 return;
745
746 /* Reserved for Admin and Default Queue */
747 if (max_vectors > 2 &&
748 (mrioc->requested_poll_qcount < max_vectors - 2)) {
749 ioc_info(mrioc,
750 "enabled polled queues (%d) msix (%d)\n",
751 mrioc->requested_poll_qcount, max_vectors);
752 } else {
753 ioc_info(mrioc,
754 "disabled polled queues (%d) msix (%d) because of no resources for default queue\n",
755 mrioc->requested_poll_qcount, max_vectors);
756 mrioc->requested_poll_qcount = 0;
757 }
758}
759
760/**
761 * mpi3mr_setup_isr - Setup ISR for the controller
762 * @mrioc: Adapter instance reference
763 * @setup_one: Request one IRQ or more
764 *
765 * Allocate IRQ vectors and call mpi3mr_request_irq to setup ISR
766 *
767 * Return: 0 on success and non zero on failures.
768 */
769static int mpi3mr_setup_isr(struct mpi3mr_ioc *mrioc, u8 setup_one)
770{
771 unsigned int irq_flags = PCI_IRQ_MSIX;
772 int max_vectors, min_vec;
773 int retval;
774 int i;
775 struct irq_affinity desc = { .pre_vectors = 1, .post_vectors = 1 };
776
777 if (mrioc->is_intr_info_set)
778 return 0;
779
780 mpi3mr_cleanup_isr(mrioc);
781
782 if (setup_one || reset_devices) {
783 max_vectors = 1;
784 retval = pci_alloc_irq_vectors(mrioc->pdev,
785 1, max_vectors, irq_flags);
786 if (retval < 0) {
787 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
788 retval);
789 goto out_failed;
790 }
791 } else {
792 max_vectors =
793 min_t(int, mrioc->cpu_count + 1 +
794 mrioc->requested_poll_qcount, mrioc->msix_count);
795
796 mpi3mr_calc_poll_queues(mrioc, max_vectors);
797
798 ioc_info(mrioc,
799 "MSI-X vectors supported: %d, no of cores: %d,",
800 mrioc->msix_count, mrioc->cpu_count);
801 ioc_info(mrioc,
802 "MSI-x vectors requested: %d poll_queues %d\n",
803 max_vectors, mrioc->requested_poll_qcount);
804
805 desc.post_vectors = mrioc->requested_poll_qcount;
806 min_vec = desc.pre_vectors + desc.post_vectors;
807 irq_flags |= PCI_IRQ_AFFINITY | PCI_IRQ_ALL_TYPES;
808
809 retval = pci_alloc_irq_vectors_affinity(mrioc->pdev,
810 min_vec, max_vectors, irq_flags, &desc);
811
812 if (retval < 0) {
813 ioc_err(mrioc, "cannot allocate irq vectors, ret %d\n",
814 retval);
815 goto out_failed;
816 }
817
818
819 /*
820 * If only one MSI-x is allocated, then MSI-x 0 will be shared
821 * between Admin queue and operational queue
822 */
823 if (retval == min_vec)
824 mrioc->op_reply_q_offset = 0;
825 else if (retval != (max_vectors)) {
826 ioc_info(mrioc,
827 "allocated vectors (%d) are less than configured (%d)\n",
828 retval, max_vectors);
829 }
830
831 max_vectors = retval;
832 mrioc->op_reply_q_offset = (max_vectors > 1) ? 1 : 0;
833
834 mpi3mr_calc_poll_queues(mrioc, max_vectors);
835
836 }
837
838 mrioc->intr_info = kzalloc(sizeof(struct mpi3mr_intr_info) * max_vectors,
839 GFP_KERNEL);
840 if (!mrioc->intr_info) {
841 retval = -ENOMEM;
842 pci_free_irq_vectors(mrioc->pdev);
843 goto out_failed;
844 }
845 for (i = 0; i < max_vectors; i++) {
846 retval = mpi3mr_request_irq(mrioc, i);
847 if (retval) {
848 mrioc->intr_info_count = i;
849 goto out_failed;
850 }
851 }
852 if (reset_devices || !setup_one)
853 mrioc->is_intr_info_set = true;
854 mrioc->intr_info_count = max_vectors;
855 mpi3mr_ioc_enable_intr(mrioc);
856 return 0;
857
858out_failed:
859 mpi3mr_cleanup_isr(mrioc);
860
861 return retval;
862}
863
864static const struct {
865 enum mpi3mr_iocstate value;
866 char *name;
867} mrioc_states[] = {
868 { MRIOC_STATE_READY, "ready" },
869 { MRIOC_STATE_FAULT, "fault" },
870 { MRIOC_STATE_RESET, "reset" },
871 { MRIOC_STATE_BECOMING_READY, "becoming ready" },
872 { MRIOC_STATE_RESET_REQUESTED, "reset requested" },
873 { MRIOC_STATE_UNRECOVERABLE, "unrecoverable error" },
874};
875
876static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state)
877{
878 int i;
879 char *name = NULL;
880
881 for (i = 0; i < ARRAY_SIZE(mrioc_states); i++) {
882 if (mrioc_states[i].value == mrioc_state) {
883 name = mrioc_states[i].name;
884 break;
885 }
886 }
887 return name;
888}
889
890/* Reset reason to name mapper structure*/
891static const struct {
892 enum mpi3mr_reset_reason value;
893 char *name;
894} mpi3mr_reset_reason_codes[] = {
895 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" },
896 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" },
897 { MPI3MR_RESET_FROM_APP, "application invocation" },
898 { MPI3MR_RESET_FROM_EH_HOS, "error handling" },
899 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" },
900 { MPI3MR_RESET_FROM_APP_TIMEOUT, "application command timeout" },
901 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" },
902 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" },
903 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" },
904 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" },
905 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" },
906 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" },
907 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" },
908 {
909 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT,
910 "create request queue timeout"
911 },
912 {
913 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT,
914 "create reply queue timeout"
915 },
916 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" },
917 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" },
918 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" },
919 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" },
920 {
921 MPI3MR_RESET_FROM_CIACTVRST_TIMER,
922 "component image activation timeout"
923 },
924 {
925 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT,
926 "get package version timeout"
927 },
928 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" },
929 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" },
930 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronous reset" },
931 { MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT, "configuration request timeout"},
932 { MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT, "timeout of a SAS transport layer request" },
933};
934
935/**
936 * mpi3mr_reset_rc_name - get reset reason code name
937 * @reason_code: reset reason code value
938 *
939 * Map reset reason to an NULL terminated ASCII string
940 *
941 * Return: name corresponding to reset reason value or NULL.
942 */
943static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code)
944{
945 int i;
946 char *name = NULL;
947
948 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_reason_codes); i++) {
949 if (mpi3mr_reset_reason_codes[i].value == reason_code) {
950 name = mpi3mr_reset_reason_codes[i].name;
951 break;
952 }
953 }
954 return name;
955}
956
957/* Reset type to name mapper structure*/
958static const struct {
959 u16 reset_type;
960 char *name;
961} mpi3mr_reset_types[] = {
962 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" },
963 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" },
964};
965
966/**
967 * mpi3mr_reset_type_name - get reset type name
968 * @reset_type: reset type value
969 *
970 * Map reset type to an NULL terminated ASCII string
971 *
972 * Return: name corresponding to reset type value or NULL.
973 */
974static const char *mpi3mr_reset_type_name(u16 reset_type)
975{
976 int i;
977 char *name = NULL;
978
979 for (i = 0; i < ARRAY_SIZE(mpi3mr_reset_types); i++) {
980 if (mpi3mr_reset_types[i].reset_type == reset_type) {
981 name = mpi3mr_reset_types[i].name;
982 break;
983 }
984 }
985 return name;
986}
987
988/**
989 * mpi3mr_print_fault_info - Display fault information
990 * @mrioc: Adapter instance reference
991 *
992 * Display the controller fault information if there is a
993 * controller fault.
994 *
995 * Return: Nothing.
996 */
997void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc)
998{
999 u32 ioc_status, code, code1, code2, code3;
1000
1001 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1002
1003 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1004 code = readl(&mrioc->sysif_regs->fault);
1005 code1 = readl(&mrioc->sysif_regs->fault_info[0]);
1006 code2 = readl(&mrioc->sysif_regs->fault_info[1]);
1007 code3 = readl(&mrioc->sysif_regs->fault_info[2]);
1008
1009 ioc_info(mrioc,
1010 "fault code(0x%08X): Additional code: (0x%08X:0x%08X:0x%08X)\n",
1011 code, code1, code2, code3);
1012 }
1013}
1014
1015/**
1016 * mpi3mr_get_iocstate - Get IOC State
1017 * @mrioc: Adapter instance reference
1018 *
1019 * Return a proper IOC state enum based on the IOC status and
1020 * IOC configuration and unrcoverable state of the controller.
1021 *
1022 * Return: Current IOC state.
1023 */
1024enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc)
1025{
1026 u32 ioc_status, ioc_config;
1027 u8 ready, enabled;
1028
1029 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1030 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1031
1032 if (mrioc->unrecoverable)
1033 return MRIOC_STATE_UNRECOVERABLE;
1034 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)
1035 return MRIOC_STATE_FAULT;
1036
1037 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY);
1038 enabled = (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC);
1039
1040 if (ready && enabled)
1041 return MRIOC_STATE_READY;
1042 if ((!ready) && (!enabled))
1043 return MRIOC_STATE_RESET;
1044 if ((!ready) && (enabled))
1045 return MRIOC_STATE_BECOMING_READY;
1046
1047 return MRIOC_STATE_RESET_REQUESTED;
1048}
1049
1050/**
1051 * mpi3mr_clear_reset_history - clear reset history
1052 * @mrioc: Adapter instance reference
1053 *
1054 * Write the reset history bit in IOC status to clear the bit,
1055 * if it is already set.
1056 *
1057 * Return: Nothing.
1058 */
1059static inline void mpi3mr_clear_reset_history(struct mpi3mr_ioc *mrioc)
1060{
1061 u32 ioc_status;
1062
1063 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1064 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1065 writel(ioc_status, &mrioc->sysif_regs->ioc_status);
1066}
1067
1068/**
1069 * mpi3mr_issue_and_process_mur - Message unit Reset handler
1070 * @mrioc: Adapter instance reference
1071 * @reset_reason: Reset reason code
1072 *
1073 * Issue Message unit Reset to the controller and wait for it to
1074 * be complete.
1075 *
1076 * Return: 0 on success, -1 on failure.
1077 */
1078static int mpi3mr_issue_and_process_mur(struct mpi3mr_ioc *mrioc,
1079 u32 reset_reason)
1080{
1081 u32 ioc_config, timeout, ioc_status;
1082 int retval = -1;
1083
1084 ioc_info(mrioc, "Issuing Message unit Reset(MUR)\n");
1085 if (mrioc->unrecoverable) {
1086 ioc_info(mrioc, "IOC is unrecoverable MUR not issued\n");
1087 return retval;
1088 }
1089 mpi3mr_clear_reset_history(mrioc);
1090 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1091 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1092 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1093 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1094
1095 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1096 do {
1097 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1098 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) {
1099 mpi3mr_clear_reset_history(mrioc);
1100 break;
1101 }
1102 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) {
1103 mpi3mr_print_fault_info(mrioc);
1104 break;
1105 }
1106 msleep(100);
1107 } while (--timeout);
1108
1109 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1110 if (timeout && !((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1111 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) ||
1112 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1113 retval = 0;
1114
1115 ioc_info(mrioc, "Base IOC Sts/Config after %s MUR is (0x%x)/(0x%x)\n",
1116 (!retval) ? "successful" : "failed", ioc_status, ioc_config);
1117 return retval;
1118}
1119
1120/**
1121 * mpi3mr_revalidate_factsdata - validate IOCFacts parameters
1122 * during reset/resume
1123 * @mrioc: Adapter instance reference
1124 *
1125 * Return zero if the new IOCFacts parameters value is compatible with
1126 * older values else return -EPERM
1127 */
1128static int
1129mpi3mr_revalidate_factsdata(struct mpi3mr_ioc *mrioc)
1130{
1131 u16 dev_handle_bitmap_sz;
1132 void *removepend_bitmap;
1133
1134 if (mrioc->facts.reply_sz > mrioc->reply_sz) {
1135 ioc_err(mrioc,
1136 "cannot increase reply size from %d to %d\n",
1137 mrioc->reply_sz, mrioc->facts.reply_sz);
1138 return -EPERM;
1139 }
1140
1141 if (mrioc->facts.max_op_reply_q < mrioc->num_op_reply_q) {
1142 ioc_err(mrioc,
1143 "cannot reduce number of operational reply queues from %d to %d\n",
1144 mrioc->num_op_reply_q,
1145 mrioc->facts.max_op_reply_q);
1146 return -EPERM;
1147 }
1148
1149 if (mrioc->facts.max_op_req_q < mrioc->num_op_req_q) {
1150 ioc_err(mrioc,
1151 "cannot reduce number of operational request queues from %d to %d\n",
1152 mrioc->num_op_req_q, mrioc->facts.max_op_req_q);
1153 return -EPERM;
1154 }
1155
1156 if ((mrioc->sas_transport_enabled) && (mrioc->facts.ioc_capabilities &
1157 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED))
1158 ioc_err(mrioc,
1159 "critical error: multipath capability is enabled at the\n"
1160 "\tcontroller while sas transport support is enabled at the\n"
1161 "\tdriver, please reboot the system or reload the driver\n");
1162
1163 dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8;
1164 if (mrioc->facts.max_devhandle % 8)
1165 dev_handle_bitmap_sz++;
1166 if (dev_handle_bitmap_sz > mrioc->dev_handle_bitmap_sz) {
1167 removepend_bitmap = krealloc(mrioc->removepend_bitmap,
1168 dev_handle_bitmap_sz, GFP_KERNEL);
1169 if (!removepend_bitmap) {
1170 ioc_err(mrioc,
1171 "failed to increase removepend_bitmap sz from: %d to %d\n",
1172 mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz);
1173 return -EPERM;
1174 }
1175 memset(removepend_bitmap + mrioc->dev_handle_bitmap_sz, 0,
1176 dev_handle_bitmap_sz - mrioc->dev_handle_bitmap_sz);
1177 mrioc->removepend_bitmap = removepend_bitmap;
1178 ioc_info(mrioc,
1179 "increased dev_handle_bitmap_sz from %d to %d\n",
1180 mrioc->dev_handle_bitmap_sz, dev_handle_bitmap_sz);
1181 mrioc->dev_handle_bitmap_sz = dev_handle_bitmap_sz;
1182 }
1183
1184 return 0;
1185}
1186
1187/**
1188 * mpi3mr_bring_ioc_ready - Bring controller to ready state
1189 * @mrioc: Adapter instance reference
1190 *
1191 * Set Enable IOC bit in IOC configuration register and wait for
1192 * the controller to become ready.
1193 *
1194 * Return: 0 on success, appropriate error on failure.
1195 */
1196static int mpi3mr_bring_ioc_ready(struct mpi3mr_ioc *mrioc)
1197{
1198 u32 ioc_config, ioc_status, timeout;
1199 int retval = 0;
1200 enum mpi3mr_iocstate ioc_state;
1201 u64 base_info;
1202
1203 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1204 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1205 base_info = lo_hi_readq(&mrioc->sysif_regs->ioc_information);
1206 ioc_info(mrioc, "ioc_status(0x%08x), ioc_config(0x%08x), ioc_info(0x%016llx) at the bringup\n",
1207 ioc_status, ioc_config, base_info);
1208
1209 /*The timeout value is in 2sec unit, changing it to seconds*/
1210 mrioc->ready_timeout =
1211 ((base_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >>
1212 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2;
1213
1214 ioc_info(mrioc, "ready timeout: %d seconds\n", mrioc->ready_timeout);
1215
1216 ioc_state = mpi3mr_get_iocstate(mrioc);
1217 ioc_info(mrioc, "controller is in %s state during detection\n",
1218 mpi3mr_iocstate_name(ioc_state));
1219
1220 if (ioc_state == MRIOC_STATE_BECOMING_READY ||
1221 ioc_state == MRIOC_STATE_RESET_REQUESTED) {
1222 timeout = mrioc->ready_timeout * 10;
1223 do {
1224 msleep(100);
1225 } while (--timeout);
1226
1227 if (!pci_device_is_present(mrioc->pdev)) {
1228 mrioc->unrecoverable = 1;
1229 ioc_err(mrioc,
1230 "controller is not present while waiting to reset\n");
1231 retval = -1;
1232 goto out_device_not_present;
1233 }
1234
1235 ioc_state = mpi3mr_get_iocstate(mrioc);
1236 ioc_info(mrioc,
1237 "controller is in %s state after waiting to reset\n",
1238 mpi3mr_iocstate_name(ioc_state));
1239 }
1240
1241 if (ioc_state == MRIOC_STATE_READY) {
1242 ioc_info(mrioc, "issuing message unit reset (MUR) to bring to reset state\n");
1243 retval = mpi3mr_issue_and_process_mur(mrioc,
1244 MPI3MR_RESET_FROM_BRINGUP);
1245 ioc_state = mpi3mr_get_iocstate(mrioc);
1246 if (retval)
1247 ioc_err(mrioc,
1248 "message unit reset failed with error %d current state %s\n",
1249 retval, mpi3mr_iocstate_name(ioc_state));
1250 }
1251 if (ioc_state != MRIOC_STATE_RESET) {
1252 mpi3mr_print_fault_info(mrioc);
1253 ioc_info(mrioc, "issuing soft reset to bring to reset state\n");
1254 retval = mpi3mr_issue_reset(mrioc,
1255 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
1256 MPI3MR_RESET_FROM_BRINGUP);
1257 if (retval) {
1258 ioc_err(mrioc,
1259 "soft reset failed with error %d\n", retval);
1260 goto out_failed;
1261 }
1262 }
1263 ioc_state = mpi3mr_get_iocstate(mrioc);
1264 if (ioc_state != MRIOC_STATE_RESET) {
1265 ioc_err(mrioc,
1266 "cannot bring controller to reset state, current state: %s\n",
1267 mpi3mr_iocstate_name(ioc_state));
1268 goto out_failed;
1269 }
1270 mpi3mr_clear_reset_history(mrioc);
1271 retval = mpi3mr_setup_admin_qpair(mrioc);
1272 if (retval) {
1273 ioc_err(mrioc, "failed to setup admin queues: error %d\n",
1274 retval);
1275 goto out_failed;
1276 }
1277
1278 ioc_info(mrioc, "bringing controller to ready state\n");
1279 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1280 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC;
1281 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1282
1283 timeout = mrioc->ready_timeout * 10;
1284 do {
1285 ioc_state = mpi3mr_get_iocstate(mrioc);
1286 if (ioc_state == MRIOC_STATE_READY) {
1287 ioc_info(mrioc,
1288 "successfully transitioned to %s state\n",
1289 mpi3mr_iocstate_name(ioc_state));
1290 return 0;
1291 }
1292 if (!pci_device_is_present(mrioc->pdev)) {
1293 mrioc->unrecoverable = 1;
1294 ioc_err(mrioc,
1295 "controller is not present at the bringup\n");
1296 retval = -1;
1297 goto out_device_not_present;
1298 }
1299 msleep(100);
1300 } while (--timeout);
1301
1302out_failed:
1303 ioc_state = mpi3mr_get_iocstate(mrioc);
1304 ioc_err(mrioc,
1305 "failed to bring to ready state, current state: %s\n",
1306 mpi3mr_iocstate_name(ioc_state));
1307out_device_not_present:
1308 return retval;
1309}
1310
1311/**
1312 * mpi3mr_soft_reset_success - Check softreset is success or not
1313 * @ioc_status: IOC status register value
1314 * @ioc_config: IOC config register value
1315 *
1316 * Check whether the soft reset is successful or not based on
1317 * IOC status and IOC config register values.
1318 *
1319 * Return: True when the soft reset is success, false otherwise.
1320 */
1321static inline bool
1322mpi3mr_soft_reset_success(u32 ioc_status, u32 ioc_config)
1323{
1324 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) ||
1325 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC)))
1326 return true;
1327 return false;
1328}
1329
1330/**
1331 * mpi3mr_diagfault_success - Check diag fault is success or not
1332 * @mrioc: Adapter reference
1333 * @ioc_status: IOC status register value
1334 *
1335 * Check whether the controller hit diag reset fault code.
1336 *
1337 * Return: True when there is diag fault, false otherwise.
1338 */
1339static inline bool mpi3mr_diagfault_success(struct mpi3mr_ioc *mrioc,
1340 u32 ioc_status)
1341{
1342 u32 fault;
1343
1344 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT))
1345 return false;
1346 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
1347 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) {
1348 mpi3mr_print_fault_info(mrioc);
1349 return true;
1350 }
1351 return false;
1352}
1353
1354/**
1355 * mpi3mr_set_diagsave - Set diag save bit for snapdump
1356 * @mrioc: Adapter reference
1357 *
1358 * Set diag save bit in IOC configuration register to enable
1359 * snapdump.
1360 *
1361 * Return: Nothing.
1362 */
1363static inline void mpi3mr_set_diagsave(struct mpi3mr_ioc *mrioc)
1364{
1365 u32 ioc_config;
1366
1367 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1368 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE;
1369 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
1370}
1371
1372/**
1373 * mpi3mr_issue_reset - Issue reset to the controller
1374 * @mrioc: Adapter reference
1375 * @reset_type: Reset type
1376 * @reset_reason: Reset reason code
1377 *
1378 * Unlock the host diagnostic registers and write the specific
1379 * reset type to that, wait for reset acknowledgment from the
1380 * controller, if the reset is not successful retry for the
1381 * predefined number of times.
1382 *
1383 * Return: 0 on success, non-zero on failure.
1384 */
1385static int mpi3mr_issue_reset(struct mpi3mr_ioc *mrioc, u16 reset_type,
1386 u32 reset_reason)
1387{
1388 int retval = -1;
1389 u8 unlock_retry_count = 0;
1390 u32 host_diagnostic, ioc_status, ioc_config;
1391 u32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10;
1392
1393 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) &&
1394 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT))
1395 return retval;
1396 if (mrioc->unrecoverable)
1397 return retval;
1398 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) {
1399 retval = 0;
1400 return retval;
1401 }
1402
1403 ioc_info(mrioc, "%s reset due to %s(0x%x)\n",
1404 mpi3mr_reset_type_name(reset_type),
1405 mpi3mr_reset_rc_name(reset_reason), reset_reason);
1406
1407 mpi3mr_clear_reset_history(mrioc);
1408 do {
1409 ioc_info(mrioc,
1410 "Write magic sequence to unlock host diag register (retry=%d)\n",
1411 ++unlock_retry_count);
1412 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) {
1413 ioc_err(mrioc,
1414 "%s reset failed due to unlock failure, host_diagnostic(0x%08x)\n",
1415 mpi3mr_reset_type_name(reset_type),
1416 host_diagnostic);
1417 mrioc->unrecoverable = 1;
1418 return retval;
1419 }
1420
1421 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH,
1422 &mrioc->sysif_regs->write_sequence);
1423 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST,
1424 &mrioc->sysif_regs->write_sequence);
1425 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1426 &mrioc->sysif_regs->write_sequence);
1427 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD,
1428 &mrioc->sysif_regs->write_sequence);
1429 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH,
1430 &mrioc->sysif_regs->write_sequence);
1431 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH,
1432 &mrioc->sysif_regs->write_sequence);
1433 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH,
1434 &mrioc->sysif_regs->write_sequence);
1435 usleep_range(1000, 1100);
1436 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
1437 ioc_info(mrioc,
1438 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n",
1439 unlock_retry_count, host_diagnostic);
1440 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE));
1441
1442 writel(reset_reason, &mrioc->sysif_regs->scratchpad[0]);
1443 writel(host_diagnostic | reset_type,
1444 &mrioc->sysif_regs->host_diagnostic);
1445 switch (reset_type) {
1446 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET:
1447 do {
1448 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1449 ioc_config =
1450 readl(&mrioc->sysif_regs->ioc_configuration);
1451 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)
1452 && mpi3mr_soft_reset_success(ioc_status, ioc_config)
1453 ) {
1454 mpi3mr_clear_reset_history(mrioc);
1455 retval = 0;
1456 break;
1457 }
1458 msleep(100);
1459 } while (--timeout);
1460 mpi3mr_print_fault_info(mrioc);
1461 break;
1462 case MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT:
1463 do {
1464 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1465 if (mpi3mr_diagfault_success(mrioc, ioc_status)) {
1466 retval = 0;
1467 break;
1468 }
1469 msleep(100);
1470 } while (--timeout);
1471 break;
1472 default:
1473 break;
1474 }
1475
1476 writel(MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND,
1477 &mrioc->sysif_regs->write_sequence);
1478
1479 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
1480 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
1481 ioc_info(mrioc,
1482 "ioc_status/ioc_onfig after %s reset is (0x%x)/(0x%x)\n",
1483 (!retval)?"successful":"failed", ioc_status,
1484 ioc_config);
1485 if (retval)
1486 mrioc->unrecoverable = 1;
1487 return retval;
1488}
1489
1490/**
1491 * mpi3mr_admin_request_post - Post request to admin queue
1492 * @mrioc: Adapter reference
1493 * @admin_req: MPI3 request
1494 * @admin_req_sz: Request size
1495 * @ignore_reset: Ignore reset in process
1496 *
1497 * Post the MPI3 request into admin request queue and
1498 * inform the controller, if the queue is full return
1499 * appropriate error.
1500 *
1501 * Return: 0 on success, non-zero on failure.
1502 */
1503int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1504 u16 admin_req_sz, u8 ignore_reset)
1505{
1506 u16 areq_pi = 0, areq_ci = 0, max_entries = 0;
1507 int retval = 0;
1508 unsigned long flags;
1509 u8 *areq_entry;
1510
1511 if (mrioc->unrecoverable) {
1512 ioc_err(mrioc, "%s : Unrecoverable controller\n", __func__);
1513 return -EFAULT;
1514 }
1515
1516 spin_lock_irqsave(&mrioc->admin_req_lock, flags);
1517 areq_pi = mrioc->admin_req_pi;
1518 areq_ci = mrioc->admin_req_ci;
1519 max_entries = mrioc->num_admin_req;
1520 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) &&
1521 (areq_pi == (max_entries - 1)))) {
1522 ioc_err(mrioc, "AdminReqQ full condition detected\n");
1523 retval = -EAGAIN;
1524 goto out;
1525 }
1526 if (!ignore_reset && mrioc->reset_in_progress) {
1527 ioc_err(mrioc, "AdminReqQ submit reset in progress\n");
1528 retval = -EAGAIN;
1529 goto out;
1530 }
1531 areq_entry = (u8 *)mrioc->admin_req_base +
1532 (areq_pi * MPI3MR_ADMIN_REQ_FRAME_SZ);
1533 memset(areq_entry, 0, MPI3MR_ADMIN_REQ_FRAME_SZ);
1534 memcpy(areq_entry, (u8 *)admin_req, admin_req_sz);
1535
1536 if (++areq_pi == max_entries)
1537 areq_pi = 0;
1538 mrioc->admin_req_pi = areq_pi;
1539
1540 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
1541
1542out:
1543 spin_unlock_irqrestore(&mrioc->admin_req_lock, flags);
1544
1545 return retval;
1546}
1547
1548/**
1549 * mpi3mr_free_op_req_q_segments - free request memory segments
1550 * @mrioc: Adapter instance reference
1551 * @q_idx: operational request queue index
1552 *
1553 * Free memory segments allocated for operational request queue
1554 *
1555 * Return: Nothing.
1556 */
1557static void mpi3mr_free_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1558{
1559 u16 j;
1560 int size;
1561 struct segments *segments;
1562
1563 segments = mrioc->req_qinfo[q_idx].q_segments;
1564 if (!segments)
1565 return;
1566
1567 if (mrioc->enable_segqueue) {
1568 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1569 if (mrioc->req_qinfo[q_idx].q_segment_list) {
1570 dma_free_coherent(&mrioc->pdev->dev,
1571 MPI3MR_MAX_SEG_LIST_SIZE,
1572 mrioc->req_qinfo[q_idx].q_segment_list,
1573 mrioc->req_qinfo[q_idx].q_segment_list_dma);
1574 mrioc->req_qinfo[q_idx].q_segment_list = NULL;
1575 }
1576 } else
1577 size = mrioc->req_qinfo[q_idx].segment_qd *
1578 mrioc->facts.op_req_sz;
1579
1580 for (j = 0; j < mrioc->req_qinfo[q_idx].num_segments; j++) {
1581 if (!segments[j].segment)
1582 continue;
1583 dma_free_coherent(&mrioc->pdev->dev,
1584 size, segments[j].segment, segments[j].segment_dma);
1585 segments[j].segment = NULL;
1586 }
1587 kfree(mrioc->req_qinfo[q_idx].q_segments);
1588 mrioc->req_qinfo[q_idx].q_segments = NULL;
1589 mrioc->req_qinfo[q_idx].qid = 0;
1590}
1591
1592/**
1593 * mpi3mr_free_op_reply_q_segments - free reply memory segments
1594 * @mrioc: Adapter instance reference
1595 * @q_idx: operational reply queue index
1596 *
1597 * Free memory segments allocated for operational reply queue
1598 *
1599 * Return: Nothing.
1600 */
1601static void mpi3mr_free_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 q_idx)
1602{
1603 u16 j;
1604 int size;
1605 struct segments *segments;
1606
1607 segments = mrioc->op_reply_qinfo[q_idx].q_segments;
1608 if (!segments)
1609 return;
1610
1611 if (mrioc->enable_segqueue) {
1612 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1613 if (mrioc->op_reply_qinfo[q_idx].q_segment_list) {
1614 dma_free_coherent(&mrioc->pdev->dev,
1615 MPI3MR_MAX_SEG_LIST_SIZE,
1616 mrioc->op_reply_qinfo[q_idx].q_segment_list,
1617 mrioc->op_reply_qinfo[q_idx].q_segment_list_dma);
1618 mrioc->op_reply_qinfo[q_idx].q_segment_list = NULL;
1619 }
1620 } else
1621 size = mrioc->op_reply_qinfo[q_idx].segment_qd *
1622 mrioc->op_reply_desc_sz;
1623
1624 for (j = 0; j < mrioc->op_reply_qinfo[q_idx].num_segments; j++) {
1625 if (!segments[j].segment)
1626 continue;
1627 dma_free_coherent(&mrioc->pdev->dev,
1628 size, segments[j].segment, segments[j].segment_dma);
1629 segments[j].segment = NULL;
1630 }
1631
1632 kfree(mrioc->op_reply_qinfo[q_idx].q_segments);
1633 mrioc->op_reply_qinfo[q_idx].q_segments = NULL;
1634 mrioc->op_reply_qinfo[q_idx].qid = 0;
1635}
1636
1637/**
1638 * mpi3mr_delete_op_reply_q - delete operational reply queue
1639 * @mrioc: Adapter instance reference
1640 * @qidx: operational reply queue index
1641 *
1642 * Delete operatinal reply queue by issuing MPI request
1643 * through admin queue.
1644 *
1645 * Return: 0 on success, non-zero on failure.
1646 */
1647static int mpi3mr_delete_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1648{
1649 struct mpi3_delete_reply_queue_request delq_req;
1650 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1651 int retval = 0;
1652 u16 reply_qid = 0, midx;
1653
1654 reply_qid = op_reply_q->qid;
1655
1656 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1657
1658 if (!reply_qid) {
1659 retval = -1;
1660 ioc_err(mrioc, "Issue DelRepQ: called with invalid ReqQID\n");
1661 goto out;
1662 }
1663
1664 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount-- :
1665 mrioc->active_poll_qcount--;
1666
1667 memset(&delq_req, 0, sizeof(delq_req));
1668 mutex_lock(&mrioc->init_cmds.mutex);
1669 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1670 retval = -1;
1671 ioc_err(mrioc, "Issue DelRepQ: Init command is in use\n");
1672 mutex_unlock(&mrioc->init_cmds.mutex);
1673 goto out;
1674 }
1675 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1676 mrioc->init_cmds.is_waiting = 1;
1677 mrioc->init_cmds.callback = NULL;
1678 delq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1679 delq_req.function = MPI3_FUNCTION_DELETE_REPLY_QUEUE;
1680 delq_req.queue_id = cpu_to_le16(reply_qid);
1681
1682 init_completion(&mrioc->init_cmds.done);
1683 retval = mpi3mr_admin_request_post(mrioc, &delq_req, sizeof(delq_req),
1684 1);
1685 if (retval) {
1686 ioc_err(mrioc, "Issue DelRepQ: Admin Post failed\n");
1687 goto out_unlock;
1688 }
1689 wait_for_completion_timeout(&mrioc->init_cmds.done,
1690 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1691 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1692 ioc_err(mrioc, "delete reply queue timed out\n");
1693 mpi3mr_check_rh_fault_ioc(mrioc,
1694 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT);
1695 retval = -1;
1696 goto out_unlock;
1697 }
1698 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1699 != MPI3_IOCSTATUS_SUCCESS) {
1700 ioc_err(mrioc,
1701 "Issue DelRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1702 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1703 mrioc->init_cmds.ioc_loginfo);
1704 retval = -1;
1705 goto out_unlock;
1706 }
1707 mrioc->intr_info[midx].op_reply_q = NULL;
1708
1709 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1710out_unlock:
1711 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1712 mutex_unlock(&mrioc->init_cmds.mutex);
1713out:
1714
1715 return retval;
1716}
1717
1718/**
1719 * mpi3mr_alloc_op_reply_q_segments -Alloc segmented reply pool
1720 * @mrioc: Adapter instance reference
1721 * @qidx: request queue index
1722 *
1723 * Allocate segmented memory pools for operational reply
1724 * queue.
1725 *
1726 * Return: 0 on success, non-zero on failure.
1727 */
1728static int mpi3mr_alloc_op_reply_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1729{
1730 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1731 int i, size;
1732 u64 *q_segment_list_entry = NULL;
1733 struct segments *segments;
1734
1735 if (mrioc->enable_segqueue) {
1736 op_reply_q->segment_qd =
1737 MPI3MR_OP_REP_Q_SEG_SIZE / mrioc->op_reply_desc_sz;
1738
1739 size = MPI3MR_OP_REP_Q_SEG_SIZE;
1740
1741 op_reply_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1742 MPI3MR_MAX_SEG_LIST_SIZE, &op_reply_q->q_segment_list_dma,
1743 GFP_KERNEL);
1744 if (!op_reply_q->q_segment_list)
1745 return -ENOMEM;
1746 q_segment_list_entry = (u64 *)op_reply_q->q_segment_list;
1747 } else {
1748 op_reply_q->segment_qd = op_reply_q->num_replies;
1749 size = op_reply_q->num_replies * mrioc->op_reply_desc_sz;
1750 }
1751
1752 op_reply_q->num_segments = DIV_ROUND_UP(op_reply_q->num_replies,
1753 op_reply_q->segment_qd);
1754
1755 op_reply_q->q_segments = kcalloc(op_reply_q->num_segments,
1756 sizeof(struct segments), GFP_KERNEL);
1757 if (!op_reply_q->q_segments)
1758 return -ENOMEM;
1759
1760 segments = op_reply_q->q_segments;
1761 for (i = 0; i < op_reply_q->num_segments; i++) {
1762 segments[i].segment =
1763 dma_alloc_coherent(&mrioc->pdev->dev,
1764 size, &segments[i].segment_dma, GFP_KERNEL);
1765 if (!segments[i].segment)
1766 return -ENOMEM;
1767 if (mrioc->enable_segqueue)
1768 q_segment_list_entry[i] =
1769 (unsigned long)segments[i].segment_dma;
1770 }
1771
1772 return 0;
1773}
1774
1775/**
1776 * mpi3mr_alloc_op_req_q_segments - Alloc segmented req pool.
1777 * @mrioc: Adapter instance reference
1778 * @qidx: request queue index
1779 *
1780 * Allocate segmented memory pools for operational request
1781 * queue.
1782 *
1783 * Return: 0 on success, non-zero on failure.
1784 */
1785static int mpi3mr_alloc_op_req_q_segments(struct mpi3mr_ioc *mrioc, u16 qidx)
1786{
1787 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
1788 int i, size;
1789 u64 *q_segment_list_entry = NULL;
1790 struct segments *segments;
1791
1792 if (mrioc->enable_segqueue) {
1793 op_req_q->segment_qd =
1794 MPI3MR_OP_REQ_Q_SEG_SIZE / mrioc->facts.op_req_sz;
1795
1796 size = MPI3MR_OP_REQ_Q_SEG_SIZE;
1797
1798 op_req_q->q_segment_list = dma_alloc_coherent(&mrioc->pdev->dev,
1799 MPI3MR_MAX_SEG_LIST_SIZE, &op_req_q->q_segment_list_dma,
1800 GFP_KERNEL);
1801 if (!op_req_q->q_segment_list)
1802 return -ENOMEM;
1803 q_segment_list_entry = (u64 *)op_req_q->q_segment_list;
1804
1805 } else {
1806 op_req_q->segment_qd = op_req_q->num_requests;
1807 size = op_req_q->num_requests * mrioc->facts.op_req_sz;
1808 }
1809
1810 op_req_q->num_segments = DIV_ROUND_UP(op_req_q->num_requests,
1811 op_req_q->segment_qd);
1812
1813 op_req_q->q_segments = kcalloc(op_req_q->num_segments,
1814 sizeof(struct segments), GFP_KERNEL);
1815 if (!op_req_q->q_segments)
1816 return -ENOMEM;
1817
1818 segments = op_req_q->q_segments;
1819 for (i = 0; i < op_req_q->num_segments; i++) {
1820 segments[i].segment =
1821 dma_alloc_coherent(&mrioc->pdev->dev,
1822 size, &segments[i].segment_dma, GFP_KERNEL);
1823 if (!segments[i].segment)
1824 return -ENOMEM;
1825 if (mrioc->enable_segqueue)
1826 q_segment_list_entry[i] =
1827 (unsigned long)segments[i].segment_dma;
1828 }
1829
1830 return 0;
1831}
1832
1833/**
1834 * mpi3mr_create_op_reply_q - create operational reply queue
1835 * @mrioc: Adapter instance reference
1836 * @qidx: operational reply queue index
1837 *
1838 * Create operatinal reply queue by issuing MPI request
1839 * through admin queue.
1840 *
1841 * Return: 0 on success, non-zero on failure.
1842 */
1843static int mpi3mr_create_op_reply_q(struct mpi3mr_ioc *mrioc, u16 qidx)
1844{
1845 struct mpi3_create_reply_queue_request create_req;
1846 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
1847 int retval = 0;
1848 u16 reply_qid = 0, midx;
1849
1850 reply_qid = op_reply_q->qid;
1851
1852 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, mrioc->op_reply_q_offset);
1853
1854 if (reply_qid) {
1855 retval = -1;
1856 ioc_err(mrioc, "CreateRepQ: called for duplicate qid %d\n",
1857 reply_qid);
1858
1859 return retval;
1860 }
1861
1862 reply_qid = qidx + 1;
1863 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD;
1864 if (!mrioc->pdev->revision)
1865 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD4K;
1866 op_reply_q->ci = 0;
1867 op_reply_q->ephase = 1;
1868 atomic_set(&op_reply_q->pend_ios, 0);
1869 atomic_set(&op_reply_q->in_use, 0);
1870 op_reply_q->enable_irq_poll = false;
1871
1872 if (!op_reply_q->q_segments) {
1873 retval = mpi3mr_alloc_op_reply_q_segments(mrioc, qidx);
1874 if (retval) {
1875 mpi3mr_free_op_reply_q_segments(mrioc, qidx);
1876 goto out;
1877 }
1878 }
1879
1880 memset(&create_req, 0, sizeof(create_req));
1881 mutex_lock(&mrioc->init_cmds.mutex);
1882 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
1883 retval = -1;
1884 ioc_err(mrioc, "CreateRepQ: Init command is in use\n");
1885 goto out_unlock;
1886 }
1887 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
1888 mrioc->init_cmds.is_waiting = 1;
1889 mrioc->init_cmds.callback = NULL;
1890 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
1891 create_req.function = MPI3_FUNCTION_CREATE_REPLY_QUEUE;
1892 create_req.queue_id = cpu_to_le16(reply_qid);
1893
1894 if (midx < (mrioc->intr_info_count - mrioc->requested_poll_qcount))
1895 op_reply_q->qtype = MPI3MR_DEFAULT_QUEUE;
1896 else
1897 op_reply_q->qtype = MPI3MR_POLL_QUEUE;
1898
1899 if (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) {
1900 create_req.flags =
1901 MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE;
1902 create_req.msix_index =
1903 cpu_to_le16(mrioc->intr_info[midx].msix_index);
1904 } else {
1905 create_req.msix_index = cpu_to_le16(mrioc->intr_info_count - 1);
1906 ioc_info(mrioc, "create reply queue(polled): for qid(%d), midx(%d)\n",
1907 reply_qid, midx);
1908 if (!mrioc->active_poll_qcount)
1909 disable_irq_nosync(pci_irq_vector(mrioc->pdev,
1910 mrioc->intr_info_count - 1));
1911 }
1912
1913 if (mrioc->enable_segqueue) {
1914 create_req.flags |=
1915 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
1916 create_req.base_address = cpu_to_le64(
1917 op_reply_q->q_segment_list_dma);
1918 } else
1919 create_req.base_address = cpu_to_le64(
1920 op_reply_q->q_segments[0].segment_dma);
1921
1922 create_req.size = cpu_to_le16(op_reply_q->num_replies);
1923
1924 init_completion(&mrioc->init_cmds.done);
1925 retval = mpi3mr_admin_request_post(mrioc, &create_req,
1926 sizeof(create_req), 1);
1927 if (retval) {
1928 ioc_err(mrioc, "CreateRepQ: Admin Post failed\n");
1929 goto out_unlock;
1930 }
1931 wait_for_completion_timeout(&mrioc->init_cmds.done,
1932 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
1933 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
1934 ioc_err(mrioc, "create reply queue timed out\n");
1935 mpi3mr_check_rh_fault_ioc(mrioc,
1936 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT);
1937 retval = -1;
1938 goto out_unlock;
1939 }
1940 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
1941 != MPI3_IOCSTATUS_SUCCESS) {
1942 ioc_err(mrioc,
1943 "CreateRepQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
1944 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
1945 mrioc->init_cmds.ioc_loginfo);
1946 retval = -1;
1947 goto out_unlock;
1948 }
1949 op_reply_q->qid = reply_qid;
1950 if (midx < mrioc->intr_info_count)
1951 mrioc->intr_info[midx].op_reply_q = op_reply_q;
1952
1953 (op_reply_q->qtype == MPI3MR_DEFAULT_QUEUE) ? mrioc->default_qcount++ :
1954 mrioc->active_poll_qcount++;
1955
1956out_unlock:
1957 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
1958 mutex_unlock(&mrioc->init_cmds.mutex);
1959out:
1960
1961 return retval;
1962}
1963
1964/**
1965 * mpi3mr_create_op_req_q - create operational request queue
1966 * @mrioc: Adapter instance reference
1967 * @idx: operational request queue index
1968 * @reply_qid: Reply queue ID
1969 *
1970 * Create operatinal request queue by issuing MPI request
1971 * through admin queue.
1972 *
1973 * Return: 0 on success, non-zero on failure.
1974 */
1975static int mpi3mr_create_op_req_q(struct mpi3mr_ioc *mrioc, u16 idx,
1976 u16 reply_qid)
1977{
1978 struct mpi3_create_request_queue_request create_req;
1979 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + idx;
1980 int retval = 0;
1981 u16 req_qid = 0;
1982
1983 req_qid = op_req_q->qid;
1984
1985 if (req_qid) {
1986 retval = -1;
1987 ioc_err(mrioc, "CreateReqQ: called for duplicate qid %d\n",
1988 req_qid);
1989
1990 return retval;
1991 }
1992 req_qid = idx + 1;
1993
1994 op_req_q->num_requests = MPI3MR_OP_REQ_Q_QD;
1995 op_req_q->ci = 0;
1996 op_req_q->pi = 0;
1997 op_req_q->reply_qid = reply_qid;
1998 spin_lock_init(&op_req_q->q_lock);
1999
2000 if (!op_req_q->q_segments) {
2001 retval = mpi3mr_alloc_op_req_q_segments(mrioc, idx);
2002 if (retval) {
2003 mpi3mr_free_op_req_q_segments(mrioc, idx);
2004 goto out;
2005 }
2006 }
2007
2008 memset(&create_req, 0, sizeof(create_req));
2009 mutex_lock(&mrioc->init_cmds.mutex);
2010 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2011 retval = -1;
2012 ioc_err(mrioc, "CreateReqQ: Init command is in use\n");
2013 goto out_unlock;
2014 }
2015 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2016 mrioc->init_cmds.is_waiting = 1;
2017 mrioc->init_cmds.callback = NULL;
2018 create_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2019 create_req.function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE;
2020 create_req.queue_id = cpu_to_le16(req_qid);
2021 if (mrioc->enable_segqueue) {
2022 create_req.flags =
2023 MPI3_CREATE_REQUEST_QUEUE_FLAGS_SEGMENTED_SEGMENTED;
2024 create_req.base_address = cpu_to_le64(
2025 op_req_q->q_segment_list_dma);
2026 } else
2027 create_req.base_address = cpu_to_le64(
2028 op_req_q->q_segments[0].segment_dma);
2029 create_req.reply_queue_id = cpu_to_le16(reply_qid);
2030 create_req.size = cpu_to_le16(op_req_q->num_requests);
2031
2032 init_completion(&mrioc->init_cmds.done);
2033 retval = mpi3mr_admin_request_post(mrioc, &create_req,
2034 sizeof(create_req), 1);
2035 if (retval) {
2036 ioc_err(mrioc, "CreateReqQ: Admin Post failed\n");
2037 goto out_unlock;
2038 }
2039 wait_for_completion_timeout(&mrioc->init_cmds.done,
2040 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2041 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2042 ioc_err(mrioc, "create request queue timed out\n");
2043 mpi3mr_check_rh_fault_ioc(mrioc,
2044 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT);
2045 retval = -1;
2046 goto out_unlock;
2047 }
2048 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2049 != MPI3_IOCSTATUS_SUCCESS) {
2050 ioc_err(mrioc,
2051 "CreateReqQ: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2052 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2053 mrioc->init_cmds.ioc_loginfo);
2054 retval = -1;
2055 goto out_unlock;
2056 }
2057 op_req_q->qid = req_qid;
2058
2059out_unlock:
2060 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2061 mutex_unlock(&mrioc->init_cmds.mutex);
2062out:
2063
2064 return retval;
2065}
2066
2067/**
2068 * mpi3mr_create_op_queues - create operational queue pairs
2069 * @mrioc: Adapter instance reference
2070 *
2071 * Allocate memory for operational queue meta data and call
2072 * create request and reply queue functions.
2073 *
2074 * Return: 0 on success, non-zero on failures.
2075 */
2076static int mpi3mr_create_op_queues(struct mpi3mr_ioc *mrioc)
2077{
2078 int retval = 0;
2079 u16 num_queues = 0, i = 0, msix_count_op_q = 1;
2080
2081 num_queues = min_t(int, mrioc->facts.max_op_reply_q,
2082 mrioc->facts.max_op_req_q);
2083
2084 msix_count_op_q =
2085 mrioc->intr_info_count - mrioc->op_reply_q_offset;
2086 if (!mrioc->num_queues)
2087 mrioc->num_queues = min_t(int, num_queues, msix_count_op_q);
2088 /*
2089 * During reset set the num_queues to the number of queues
2090 * that was set before the reset.
2091 */
2092 num_queues = mrioc->num_op_reply_q ?
2093 mrioc->num_op_reply_q : mrioc->num_queues;
2094 ioc_info(mrioc, "trying to create %d operational queue pairs\n",
2095 num_queues);
2096
2097 if (!mrioc->req_qinfo) {
2098 mrioc->req_qinfo = kcalloc(num_queues,
2099 sizeof(struct op_req_qinfo), GFP_KERNEL);
2100 if (!mrioc->req_qinfo) {
2101 retval = -1;
2102 goto out_failed;
2103 }
2104
2105 mrioc->op_reply_qinfo = kzalloc(sizeof(struct op_reply_qinfo) *
2106 num_queues, GFP_KERNEL);
2107 if (!mrioc->op_reply_qinfo) {
2108 retval = -1;
2109 goto out_failed;
2110 }
2111 }
2112
2113 if (mrioc->enable_segqueue)
2114 ioc_info(mrioc,
2115 "allocating operational queues through segmented queues\n");
2116
2117 for (i = 0; i < num_queues; i++) {
2118 if (mpi3mr_create_op_reply_q(mrioc, i)) {
2119 ioc_err(mrioc, "Cannot create OP RepQ %d\n", i);
2120 break;
2121 }
2122 if (mpi3mr_create_op_req_q(mrioc, i,
2123 mrioc->op_reply_qinfo[i].qid)) {
2124 ioc_err(mrioc, "Cannot create OP ReqQ %d\n", i);
2125 mpi3mr_delete_op_reply_q(mrioc, i);
2126 break;
2127 }
2128 }
2129
2130 if (i == 0) {
2131 /* Not even one queue is created successfully*/
2132 retval = -1;
2133 goto out_failed;
2134 }
2135 mrioc->num_op_reply_q = mrioc->num_op_req_q = i;
2136 ioc_info(mrioc,
2137 "successfully created %d operational queue pairs(default/polled) queue = (%d/%d)\n",
2138 mrioc->num_op_reply_q, mrioc->default_qcount,
2139 mrioc->active_poll_qcount);
2140
2141 return retval;
2142out_failed:
2143 kfree(mrioc->req_qinfo);
2144 mrioc->req_qinfo = NULL;
2145
2146 kfree(mrioc->op_reply_qinfo);
2147 mrioc->op_reply_qinfo = NULL;
2148
2149 return retval;
2150}
2151
2152/**
2153 * mpi3mr_op_request_post - Post request to operational queue
2154 * @mrioc: Adapter reference
2155 * @op_req_q: Operational request queue info
2156 * @req: MPI3 request
2157 *
2158 * Post the MPI3 request into operational request queue and
2159 * inform the controller, if the queue is full return
2160 * appropriate error.
2161 *
2162 * Return: 0 on success, non-zero on failure.
2163 */
2164int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
2165 struct op_req_qinfo *op_req_q, u8 *req)
2166{
2167 u16 pi = 0, max_entries, reply_qidx = 0, midx;
2168 int retval = 0;
2169 unsigned long flags;
2170 u8 *req_entry;
2171 void *segment_base_addr;
2172 u16 req_sz = mrioc->facts.op_req_sz;
2173 struct segments *segments = op_req_q->q_segments;
2174
2175 reply_qidx = op_req_q->reply_qid - 1;
2176
2177 if (mrioc->unrecoverable)
2178 return -EFAULT;
2179
2180 spin_lock_irqsave(&op_req_q->q_lock, flags);
2181 pi = op_req_q->pi;
2182 max_entries = op_req_q->num_requests;
2183
2184 if (mpi3mr_check_req_qfull(op_req_q)) {
2185 midx = REPLY_QUEUE_IDX_TO_MSIX_IDX(
2186 reply_qidx, mrioc->op_reply_q_offset);
2187 mpi3mr_process_op_reply_q(mrioc, mrioc->intr_info[midx].op_reply_q);
2188
2189 if (mpi3mr_check_req_qfull(op_req_q)) {
2190 retval = -EAGAIN;
2191 goto out;
2192 }
2193 }
2194
2195 if (mrioc->reset_in_progress) {
2196 ioc_err(mrioc, "OpReqQ submit reset in progress\n");
2197 retval = -EAGAIN;
2198 goto out;
2199 }
2200
2201 segment_base_addr = segments[pi / op_req_q->segment_qd].segment;
2202 req_entry = (u8 *)segment_base_addr +
2203 ((pi % op_req_q->segment_qd) * req_sz);
2204
2205 memset(req_entry, 0, req_sz);
2206 memcpy(req_entry, req, MPI3MR_ADMIN_REQ_FRAME_SZ);
2207
2208 if (++pi == max_entries)
2209 pi = 0;
2210 op_req_q->pi = pi;
2211
2212#ifndef CONFIG_PREEMPT_RT
2213 if (atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios)
2214 > MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT)
2215 mrioc->op_reply_qinfo[reply_qidx].enable_irq_poll = true;
2216#else
2217 atomic_inc_return(&mrioc->op_reply_qinfo[reply_qidx].pend_ios);
2218#endif
2219
2220 writel(op_req_q->pi,
2221 &mrioc->sysif_regs->oper_queue_indexes[reply_qidx].producer_index);
2222
2223out:
2224 spin_unlock_irqrestore(&op_req_q->q_lock, flags);
2225 return retval;
2226}
2227
2228/**
2229 * mpi3mr_check_rh_fault_ioc - check reset history and fault
2230 * controller
2231 * @mrioc: Adapter instance reference
2232 * @reason_code: reason code for the fault.
2233 *
2234 * This routine will save snapdump and fault the controller with
2235 * the given reason code if it is not already in the fault or
2236 * not asynchronosuly reset. This will be used to handle
2237 * initilaization time faults/resets/timeout as in those cases
2238 * immediate soft reset invocation is not required.
2239 *
2240 * Return: None.
2241 */
2242void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code)
2243{
2244 u32 ioc_status, host_diagnostic, timeout;
2245
2246 if (mrioc->unrecoverable) {
2247 ioc_err(mrioc, "controller is unrecoverable\n");
2248 return;
2249 }
2250
2251 if (!pci_device_is_present(mrioc->pdev)) {
2252 mrioc->unrecoverable = 1;
2253 ioc_err(mrioc, "controller is not present\n");
2254 return;
2255 }
2256
2257 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2258 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
2259 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
2260 mpi3mr_print_fault_info(mrioc);
2261 return;
2262 }
2263 mpi3mr_set_diagsave(mrioc);
2264 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
2265 reason_code);
2266 timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
2267 do {
2268 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2269 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
2270 break;
2271 msleep(100);
2272 } while (--timeout);
2273}
2274
2275/**
2276 * mpi3mr_sync_timestamp - Issue time stamp sync request
2277 * @mrioc: Adapter reference
2278 *
2279 * Issue IO unit control MPI request to synchornize firmware
2280 * timestamp with host time.
2281 *
2282 * Return: 0 on success, non-zero on failure.
2283 */
2284static int mpi3mr_sync_timestamp(struct mpi3mr_ioc *mrioc)
2285{
2286 ktime_t current_time;
2287 struct mpi3_iounit_control_request iou_ctrl;
2288 int retval = 0;
2289
2290 memset(&iou_ctrl, 0, sizeof(iou_ctrl));
2291 mutex_lock(&mrioc->init_cmds.mutex);
2292 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2293 retval = -1;
2294 ioc_err(mrioc, "Issue IOUCTL time_stamp: command is in use\n");
2295 mutex_unlock(&mrioc->init_cmds.mutex);
2296 goto out;
2297 }
2298 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2299 mrioc->init_cmds.is_waiting = 1;
2300 mrioc->init_cmds.callback = NULL;
2301 iou_ctrl.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2302 iou_ctrl.function = MPI3_FUNCTION_IO_UNIT_CONTROL;
2303 iou_ctrl.operation = MPI3_CTRL_OP_UPDATE_TIMESTAMP;
2304 current_time = ktime_get_real();
2305 iou_ctrl.param64[0] = cpu_to_le64(ktime_to_ms(current_time));
2306
2307 init_completion(&mrioc->init_cmds.done);
2308 retval = mpi3mr_admin_request_post(mrioc, &iou_ctrl,
2309 sizeof(iou_ctrl), 0);
2310 if (retval) {
2311 ioc_err(mrioc, "Issue IOUCTL time_stamp: Admin Post failed\n");
2312 goto out_unlock;
2313 }
2314
2315 wait_for_completion_timeout(&mrioc->init_cmds.done,
2316 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2317 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2318 ioc_err(mrioc, "Issue IOUCTL time_stamp: command timed out\n");
2319 mrioc->init_cmds.is_waiting = 0;
2320 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
2321 mpi3mr_soft_reset_handler(mrioc,
2322 MPI3MR_RESET_FROM_TSU_TIMEOUT, 1);
2323 retval = -1;
2324 goto out_unlock;
2325 }
2326 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2327 != MPI3_IOCSTATUS_SUCCESS) {
2328 ioc_err(mrioc,
2329 "Issue IOUCTL time_stamp: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2330 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2331 mrioc->init_cmds.ioc_loginfo);
2332 retval = -1;
2333 goto out_unlock;
2334 }
2335
2336out_unlock:
2337 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2338 mutex_unlock(&mrioc->init_cmds.mutex);
2339
2340out:
2341 return retval;
2342}
2343
2344/**
2345 * mpi3mr_print_pkg_ver - display controller fw package version
2346 * @mrioc: Adapter reference
2347 *
2348 * Retrieve firmware package version from the component image
2349 * header of the controller flash and display it.
2350 *
2351 * Return: 0 on success and non-zero on failure.
2352 */
2353static int mpi3mr_print_pkg_ver(struct mpi3mr_ioc *mrioc)
2354{
2355 struct mpi3_ci_upload_request ci_upload;
2356 int retval = -1;
2357 void *data = NULL;
2358 dma_addr_t data_dma;
2359 struct mpi3_ci_manifest_mpi *manifest;
2360 u32 data_len = sizeof(struct mpi3_ci_manifest_mpi);
2361 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2362
2363 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2364 GFP_KERNEL);
2365 if (!data)
2366 return -ENOMEM;
2367
2368 memset(&ci_upload, 0, sizeof(ci_upload));
2369 mutex_lock(&mrioc->init_cmds.mutex);
2370 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2371 ioc_err(mrioc, "sending get package version failed due to command in use\n");
2372 mutex_unlock(&mrioc->init_cmds.mutex);
2373 goto out;
2374 }
2375 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2376 mrioc->init_cmds.is_waiting = 1;
2377 mrioc->init_cmds.callback = NULL;
2378 ci_upload.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2379 ci_upload.function = MPI3_FUNCTION_CI_UPLOAD;
2380 ci_upload.msg_flags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY;
2381 ci_upload.signature1 = cpu_to_le32(MPI3_IMAGE_HEADER_SIGNATURE1_MANIFEST);
2382 ci_upload.image_offset = cpu_to_le32(MPI3_IMAGE_HEADER_SIZE);
2383 ci_upload.segment_size = cpu_to_le32(data_len);
2384
2385 mpi3mr_add_sg_single(&ci_upload.sgl, sgl_flags, data_len,
2386 data_dma);
2387 init_completion(&mrioc->init_cmds.done);
2388 retval = mpi3mr_admin_request_post(mrioc, &ci_upload,
2389 sizeof(ci_upload), 1);
2390 if (retval) {
2391 ioc_err(mrioc, "posting get package version failed\n");
2392 goto out_unlock;
2393 }
2394 wait_for_completion_timeout(&mrioc->init_cmds.done,
2395 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2396 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2397 ioc_err(mrioc, "get package version timed out\n");
2398 mpi3mr_check_rh_fault_ioc(mrioc,
2399 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT);
2400 retval = -1;
2401 goto out_unlock;
2402 }
2403 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2404 == MPI3_IOCSTATUS_SUCCESS) {
2405 manifest = (struct mpi3_ci_manifest_mpi *) data;
2406 if (manifest->manifest_type == MPI3_CI_MANIFEST_TYPE_MPI) {
2407 ioc_info(mrioc,
2408 "firmware package version(%d.%d.%d.%d.%05d-%05d)\n",
2409 manifest->package_version.gen_major,
2410 manifest->package_version.gen_minor,
2411 manifest->package_version.phase_major,
2412 manifest->package_version.phase_minor,
2413 manifest->package_version.customer_id,
2414 manifest->package_version.build_num);
2415 }
2416 }
2417 retval = 0;
2418out_unlock:
2419 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2420 mutex_unlock(&mrioc->init_cmds.mutex);
2421
2422out:
2423 if (data)
2424 dma_free_coherent(&mrioc->pdev->dev, data_len, data,
2425 data_dma);
2426 return retval;
2427}
2428
2429/**
2430 * mpi3mr_watchdog_work - watchdog thread to monitor faults
2431 * @work: work struct
2432 *
2433 * Watch dog work periodically executed (1 second interval) to
2434 * monitor firmware fault and to issue periodic timer sync to
2435 * the firmware.
2436 *
2437 * Return: Nothing.
2438 */
2439static void mpi3mr_watchdog_work(struct work_struct *work)
2440{
2441 struct mpi3mr_ioc *mrioc =
2442 container_of(work, struct mpi3mr_ioc, watchdog_work.work);
2443 unsigned long flags;
2444 enum mpi3mr_iocstate ioc_state;
2445 u32 fault, host_diagnostic, ioc_status;
2446 u32 reset_reason = MPI3MR_RESET_FROM_FAULT_WATCH;
2447
2448 if (mrioc->reset_in_progress)
2449 return;
2450
2451 if (!mrioc->unrecoverable && !pci_device_is_present(mrioc->pdev)) {
2452 ioc_err(mrioc, "watchdog could not detect the controller\n");
2453 mrioc->unrecoverable = 1;
2454 }
2455
2456 if (mrioc->unrecoverable) {
2457 ioc_err(mrioc,
2458 "flush pending commands for unrecoverable controller\n");
2459 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
2460 return;
2461 }
2462
2463 if (mrioc->ts_update_counter++ >= MPI3MR_TSUPDATE_INTERVAL) {
2464 mrioc->ts_update_counter = 0;
2465 mpi3mr_sync_timestamp(mrioc);
2466 }
2467
2468 if ((mrioc->prepare_for_reset) &&
2469 ((mrioc->prepare_for_reset_timeout_counter++) >=
2470 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) {
2471 mpi3mr_soft_reset_handler(mrioc,
2472 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1);
2473 return;
2474 }
2475
2476 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
2477 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) {
2478 mpi3mr_soft_reset_handler(mrioc, MPI3MR_RESET_FROM_FIRMWARE, 0);
2479 return;
2480 }
2481
2482 /*Check for fault state every one second and issue Soft reset*/
2483 ioc_state = mpi3mr_get_iocstate(mrioc);
2484 if (ioc_state != MRIOC_STATE_FAULT)
2485 goto schedule_work;
2486
2487 fault = readl(&mrioc->sysif_regs->fault) & MPI3_SYSIF_FAULT_CODE_MASK;
2488 host_diagnostic = readl(&mrioc->sysif_regs->host_diagnostic);
2489 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) {
2490 if (!mrioc->diagsave_timeout) {
2491 mpi3mr_print_fault_info(mrioc);
2492 ioc_warn(mrioc, "diag save in progress\n");
2493 }
2494 if ((mrioc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT)
2495 goto schedule_work;
2496 }
2497
2498 mpi3mr_print_fault_info(mrioc);
2499 mrioc->diagsave_timeout = 0;
2500
2501 switch (fault) {
2502 case MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED:
2503 case MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED:
2504 ioc_warn(mrioc,
2505 "controller requires system power cycle, marking controller as unrecoverable\n");
2506 mrioc->unrecoverable = 1;
2507 goto schedule_work;
2508 case MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS:
2509 return;
2510 case MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET:
2511 reset_reason = MPI3MR_RESET_FROM_CIACTIV_FAULT;
2512 break;
2513 default:
2514 break;
2515 }
2516 mpi3mr_soft_reset_handler(mrioc, reset_reason, 0);
2517 return;
2518
2519schedule_work:
2520 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2521 if (mrioc->watchdog_work_q)
2522 queue_delayed_work(mrioc->watchdog_work_q,
2523 &mrioc->watchdog_work,
2524 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2525 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2526 return;
2527}
2528
2529/**
2530 * mpi3mr_start_watchdog - Start watchdog
2531 * @mrioc: Adapter instance reference
2532 *
2533 * Create and start the watchdog thread to monitor controller
2534 * faults.
2535 *
2536 * Return: Nothing.
2537 */
2538void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc)
2539{
2540 if (mrioc->watchdog_work_q)
2541 return;
2542
2543 INIT_DELAYED_WORK(&mrioc->watchdog_work, mpi3mr_watchdog_work);
2544 snprintf(mrioc->watchdog_work_q_name,
2545 sizeof(mrioc->watchdog_work_q_name), "watchdog_%s%d", mrioc->name,
2546 mrioc->id);
2547 mrioc->watchdog_work_q =
2548 create_singlethread_workqueue(mrioc->watchdog_work_q_name);
2549 if (!mrioc->watchdog_work_q) {
2550 ioc_err(mrioc, "%s: failed (line=%d)\n", __func__, __LINE__);
2551 return;
2552 }
2553
2554 if (mrioc->watchdog_work_q)
2555 queue_delayed_work(mrioc->watchdog_work_q,
2556 &mrioc->watchdog_work,
2557 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
2558}
2559
2560/**
2561 * mpi3mr_stop_watchdog - Stop watchdog
2562 * @mrioc: Adapter instance reference
2563 *
2564 * Stop the watchdog thread created to monitor controller
2565 * faults.
2566 *
2567 * Return: Nothing.
2568 */
2569void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc)
2570{
2571 unsigned long flags;
2572 struct workqueue_struct *wq;
2573
2574 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
2575 wq = mrioc->watchdog_work_q;
2576 mrioc->watchdog_work_q = NULL;
2577 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
2578 if (wq) {
2579 if (!cancel_delayed_work_sync(&mrioc->watchdog_work))
2580 flush_workqueue(wq);
2581 destroy_workqueue(wq);
2582 }
2583}
2584
2585/**
2586 * mpi3mr_setup_admin_qpair - Setup admin queue pair
2587 * @mrioc: Adapter instance reference
2588 *
2589 * Allocate memory for admin queue pair if required and register
2590 * the admin queue with the controller.
2591 *
2592 * Return: 0 on success, non-zero on failures.
2593 */
2594static int mpi3mr_setup_admin_qpair(struct mpi3mr_ioc *mrioc)
2595{
2596 int retval = 0;
2597 u32 num_admin_entries = 0;
2598
2599 mrioc->admin_req_q_sz = MPI3MR_ADMIN_REQ_Q_SIZE;
2600 mrioc->num_admin_req = mrioc->admin_req_q_sz /
2601 MPI3MR_ADMIN_REQ_FRAME_SZ;
2602 mrioc->admin_req_ci = mrioc->admin_req_pi = 0;
2603 mrioc->admin_req_base = NULL;
2604
2605 mrioc->admin_reply_q_sz = MPI3MR_ADMIN_REPLY_Q_SIZE;
2606 mrioc->num_admin_replies = mrioc->admin_reply_q_sz /
2607 MPI3MR_ADMIN_REPLY_FRAME_SZ;
2608 mrioc->admin_reply_ci = 0;
2609 mrioc->admin_reply_ephase = 1;
2610 mrioc->admin_reply_base = NULL;
2611
2612 if (!mrioc->admin_req_base) {
2613 mrioc->admin_req_base = dma_alloc_coherent(&mrioc->pdev->dev,
2614 mrioc->admin_req_q_sz, &mrioc->admin_req_dma, GFP_KERNEL);
2615
2616 if (!mrioc->admin_req_base) {
2617 retval = -1;
2618 goto out_failed;
2619 }
2620
2621 mrioc->admin_reply_base = dma_alloc_coherent(&mrioc->pdev->dev,
2622 mrioc->admin_reply_q_sz, &mrioc->admin_reply_dma,
2623 GFP_KERNEL);
2624
2625 if (!mrioc->admin_reply_base) {
2626 retval = -1;
2627 goto out_failed;
2628 }
2629 }
2630
2631 num_admin_entries = (mrioc->num_admin_replies << 16) |
2632 (mrioc->num_admin_req);
2633 writel(num_admin_entries, &mrioc->sysif_regs->admin_queue_num_entries);
2634 mpi3mr_writeq(mrioc->admin_req_dma,
2635 &mrioc->sysif_regs->admin_request_queue_address);
2636 mpi3mr_writeq(mrioc->admin_reply_dma,
2637 &mrioc->sysif_regs->admin_reply_queue_address);
2638 writel(mrioc->admin_req_pi, &mrioc->sysif_regs->admin_request_queue_pi);
2639 writel(mrioc->admin_reply_ci, &mrioc->sysif_regs->admin_reply_queue_ci);
2640 return retval;
2641
2642out_failed:
2643
2644 if (mrioc->admin_reply_base) {
2645 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
2646 mrioc->admin_reply_base, mrioc->admin_reply_dma);
2647 mrioc->admin_reply_base = NULL;
2648 }
2649 if (mrioc->admin_req_base) {
2650 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
2651 mrioc->admin_req_base, mrioc->admin_req_dma);
2652 mrioc->admin_req_base = NULL;
2653 }
2654 return retval;
2655}
2656
2657/**
2658 * mpi3mr_issue_iocfacts - Send IOC Facts
2659 * @mrioc: Adapter instance reference
2660 * @facts_data: Cached IOC facts data
2661 *
2662 * Issue IOC Facts MPI request through admin queue and wait for
2663 * the completion of it or time out.
2664 *
2665 * Return: 0 on success, non-zero on failures.
2666 */
2667static int mpi3mr_issue_iocfacts(struct mpi3mr_ioc *mrioc,
2668 struct mpi3_ioc_facts_data *facts_data)
2669{
2670 struct mpi3_ioc_facts_request iocfacts_req;
2671 void *data = NULL;
2672 dma_addr_t data_dma;
2673 u32 data_len = sizeof(*facts_data);
2674 int retval = 0;
2675 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
2676
2677 data = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
2678 GFP_KERNEL);
2679
2680 if (!data) {
2681 retval = -1;
2682 goto out;
2683 }
2684
2685 memset(&iocfacts_req, 0, sizeof(iocfacts_req));
2686 mutex_lock(&mrioc->init_cmds.mutex);
2687 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
2688 retval = -1;
2689 ioc_err(mrioc, "Issue IOCFacts: Init command is in use\n");
2690 mutex_unlock(&mrioc->init_cmds.mutex);
2691 goto out;
2692 }
2693 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
2694 mrioc->init_cmds.is_waiting = 1;
2695 mrioc->init_cmds.callback = NULL;
2696 iocfacts_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
2697 iocfacts_req.function = MPI3_FUNCTION_IOC_FACTS;
2698
2699 mpi3mr_add_sg_single(&iocfacts_req.sgl, sgl_flags, data_len,
2700 data_dma);
2701
2702 init_completion(&mrioc->init_cmds.done);
2703 retval = mpi3mr_admin_request_post(mrioc, &iocfacts_req,
2704 sizeof(iocfacts_req), 1);
2705 if (retval) {
2706 ioc_err(mrioc, "Issue IOCFacts: Admin Post failed\n");
2707 goto out_unlock;
2708 }
2709 wait_for_completion_timeout(&mrioc->init_cmds.done,
2710 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
2711 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
2712 ioc_err(mrioc, "ioc_facts timed out\n");
2713 mpi3mr_check_rh_fault_ioc(mrioc,
2714 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT);
2715 retval = -1;
2716 goto out_unlock;
2717 }
2718 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
2719 != MPI3_IOCSTATUS_SUCCESS) {
2720 ioc_err(mrioc,
2721 "Issue IOCFacts: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
2722 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
2723 mrioc->init_cmds.ioc_loginfo);
2724 retval = -1;
2725 goto out_unlock;
2726 }
2727 memcpy(facts_data, (u8 *)data, data_len);
2728 mpi3mr_process_factsdata(mrioc, facts_data);
2729out_unlock:
2730 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
2731 mutex_unlock(&mrioc->init_cmds.mutex);
2732
2733out:
2734 if (data)
2735 dma_free_coherent(&mrioc->pdev->dev, data_len, data, data_dma);
2736
2737 return retval;
2738}
2739
2740/**
2741 * mpi3mr_check_reset_dma_mask - Process IOC facts data
2742 * @mrioc: Adapter instance reference
2743 *
2744 * Check whether the new DMA mask requested through IOCFacts by
2745 * firmware needs to be set, if so set it .
2746 *
2747 * Return: 0 on success, non-zero on failure.
2748 */
2749static inline int mpi3mr_check_reset_dma_mask(struct mpi3mr_ioc *mrioc)
2750{
2751 struct pci_dev *pdev = mrioc->pdev;
2752 int r;
2753 u64 facts_dma_mask = DMA_BIT_MASK(mrioc->facts.dma_mask);
2754
2755 if (!mrioc->facts.dma_mask || (mrioc->dma_mask <= facts_dma_mask))
2756 return 0;
2757
2758 ioc_info(mrioc, "Changing DMA mask from 0x%016llx to 0x%016llx\n",
2759 mrioc->dma_mask, facts_dma_mask);
2760
2761 r = dma_set_mask_and_coherent(&pdev->dev, facts_dma_mask);
2762 if (r) {
2763 ioc_err(mrioc, "Setting DMA mask to 0x%016llx failed: %d\n",
2764 facts_dma_mask, r);
2765 return r;
2766 }
2767 mrioc->dma_mask = facts_dma_mask;
2768 return r;
2769}
2770
2771/**
2772 * mpi3mr_process_factsdata - Process IOC facts data
2773 * @mrioc: Adapter instance reference
2774 * @facts_data: Cached IOC facts data
2775 *
2776 * Convert IOC facts data into cpu endianness and cache it in
2777 * the driver .
2778 *
2779 * Return: Nothing.
2780 */
2781static void mpi3mr_process_factsdata(struct mpi3mr_ioc *mrioc,
2782 struct mpi3_ioc_facts_data *facts_data)
2783{
2784 u32 ioc_config, req_sz, facts_flags;
2785
2786 if ((le16_to_cpu(facts_data->ioc_facts_data_length)) !=
2787 (sizeof(*facts_data) / 4)) {
2788 ioc_warn(mrioc,
2789 "IOCFactsdata length mismatch driver_sz(%zu) firmware_sz(%d)\n",
2790 sizeof(*facts_data),
2791 le16_to_cpu(facts_data->ioc_facts_data_length) * 4);
2792 }
2793
2794 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
2795 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >>
2796 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT);
2797 if (le16_to_cpu(facts_data->ioc_request_frame_size) != (req_sz / 4)) {
2798 ioc_err(mrioc,
2799 "IOCFacts data reqFrameSize mismatch hw_size(%d) firmware_sz(%d)\n",
2800 req_sz / 4, le16_to_cpu(facts_data->ioc_request_frame_size));
2801 }
2802
2803 memset(&mrioc->facts, 0, sizeof(mrioc->facts));
2804
2805 facts_flags = le32_to_cpu(facts_data->flags);
2806 mrioc->facts.op_req_sz = req_sz;
2807 mrioc->op_reply_desc_sz = 1 << ((ioc_config &
2808 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >>
2809 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT);
2810
2811 mrioc->facts.ioc_num = facts_data->ioc_number;
2812 mrioc->facts.who_init = facts_data->who_init;
2813 mrioc->facts.max_msix_vectors = le16_to_cpu(facts_data->max_msix_vectors);
2814 mrioc->facts.personality = (facts_flags &
2815 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK);
2816 mrioc->facts.dma_mask = (facts_flags &
2817 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >>
2818 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT;
2819 mrioc->facts.protocol_flags = facts_data->protocol_flags;
2820 mrioc->facts.mpi_version = le32_to_cpu(facts_data->mpi_version.word);
2821 mrioc->facts.max_reqs = le16_to_cpu(facts_data->max_outstanding_requests);
2822 mrioc->facts.product_id = le16_to_cpu(facts_data->product_id);
2823 mrioc->facts.reply_sz = le16_to_cpu(facts_data->reply_frame_size) * 4;
2824 mrioc->facts.exceptions = le16_to_cpu(facts_data->ioc_exceptions);
2825 mrioc->facts.max_perids = le16_to_cpu(facts_data->max_persistent_id);
2826 mrioc->facts.max_vds = le16_to_cpu(facts_data->max_vds);
2827 mrioc->facts.max_hpds = le16_to_cpu(facts_data->max_host_pds);
2828 mrioc->facts.max_advhpds = le16_to_cpu(facts_data->max_adv_host_pds);
2829 mrioc->facts.max_raid_pds = le16_to_cpu(facts_data->max_raid_pds);
2830 mrioc->facts.max_nvme = le16_to_cpu(facts_data->max_nvme);
2831 mrioc->facts.max_pcie_switches =
2832 le16_to_cpu(facts_data->max_pcie_switches);
2833 mrioc->facts.max_sasexpanders =
2834 le16_to_cpu(facts_data->max_sas_expanders);
2835 mrioc->facts.max_sasinitiators =
2836 le16_to_cpu(facts_data->max_sas_initiators);
2837 mrioc->facts.max_enclosures = le16_to_cpu(facts_data->max_enclosures);
2838 mrioc->facts.min_devhandle = le16_to_cpu(facts_data->min_dev_handle);
2839 mrioc->facts.max_devhandle = le16_to_cpu(facts_data->max_dev_handle);
2840 mrioc->facts.max_op_req_q =
2841 le16_to_cpu(facts_data->max_operational_request_queues);
2842 mrioc->facts.max_op_reply_q =
2843 le16_to_cpu(facts_data->max_operational_reply_queues);
2844 mrioc->facts.ioc_capabilities =
2845 le32_to_cpu(facts_data->ioc_capabilities);
2846 mrioc->facts.fw_ver.build_num =
2847 le16_to_cpu(facts_data->fw_version.build_num);
2848 mrioc->facts.fw_ver.cust_id =
2849 le16_to_cpu(facts_data->fw_version.customer_id);
2850 mrioc->facts.fw_ver.ph_minor = facts_data->fw_version.phase_minor;
2851 mrioc->facts.fw_ver.ph_major = facts_data->fw_version.phase_major;
2852 mrioc->facts.fw_ver.gen_minor = facts_data->fw_version.gen_minor;
2853 mrioc->facts.fw_ver.gen_major = facts_data->fw_version.gen_major;
2854 mrioc->msix_count = min_t(int, mrioc->msix_count,
2855 mrioc->facts.max_msix_vectors);
2856 mrioc->facts.sge_mod_mask = facts_data->sge_modifier_mask;
2857 mrioc->facts.sge_mod_value = facts_data->sge_modifier_value;
2858 mrioc->facts.sge_mod_shift = facts_data->sge_modifier_shift;
2859 mrioc->facts.shutdown_timeout =
2860 le16_to_cpu(facts_data->shutdown_timeout);
2861
2862 mrioc->facts.max_dev_per_tg =
2863 facts_data->max_devices_per_throttle_group;
2864 mrioc->facts.io_throttle_data_length =
2865 le16_to_cpu(facts_data->io_throttle_data_length);
2866 mrioc->facts.max_io_throttle_group =
2867 le16_to_cpu(facts_data->max_io_throttle_group);
2868 mrioc->facts.io_throttle_low = le16_to_cpu(facts_data->io_throttle_low);
2869 mrioc->facts.io_throttle_high =
2870 le16_to_cpu(facts_data->io_throttle_high);
2871
2872 /* Store in 512b block count */
2873 if (mrioc->facts.io_throttle_data_length)
2874 mrioc->io_throttle_data_length =
2875 (mrioc->facts.io_throttle_data_length * 2 * 4);
2876 else
2877 /* set the length to 1MB + 1K to disable throttle */
2878 mrioc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2;
2879
2880 mrioc->io_throttle_high = (mrioc->facts.io_throttle_high * 2 * 1024);
2881 mrioc->io_throttle_low = (mrioc->facts.io_throttle_low * 2 * 1024);
2882
2883 ioc_info(mrioc, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d),",
2884 mrioc->facts.ioc_num, mrioc->facts.max_op_req_q,
2885 mrioc->facts.max_op_reply_q, mrioc->facts.max_devhandle);
2886 ioc_info(mrioc,
2887 "maxreqs(%d), mindh(%d) maxvectors(%d) maxperids(%d)\n",
2888 mrioc->facts.max_reqs, mrioc->facts.min_devhandle,
2889 mrioc->facts.max_msix_vectors, mrioc->facts.max_perids);
2890 ioc_info(mrioc, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x ",
2891 mrioc->facts.sge_mod_mask, mrioc->facts.sge_mod_value,
2892 mrioc->facts.sge_mod_shift);
2893 ioc_info(mrioc, "DMA mask %d InitialPE status 0x%x\n",
2894 mrioc->facts.dma_mask, (facts_flags &
2895 MPI3_IOCFACTS_FLAGS_INITIAL_PORT_ENABLE_MASK));
2896 ioc_info(mrioc,
2897 "max_dev_per_throttle_group(%d), max_throttle_groups(%d)\n",
2898 mrioc->facts.max_dev_per_tg, mrioc->facts.max_io_throttle_group);
2899 ioc_info(mrioc,
2900 "io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n",
2901 mrioc->facts.io_throttle_data_length * 4,
2902 mrioc->facts.io_throttle_high, mrioc->facts.io_throttle_low);
2903}
2904
2905/**
2906 * mpi3mr_alloc_reply_sense_bufs - Send IOC Init
2907 * @mrioc: Adapter instance reference
2908 *
2909 * Allocate and initialize the reply free buffers, sense
2910 * buffers, reply free queue and sense buffer queue.
2911 *
2912 * Return: 0 on success, non-zero on failures.
2913 */
2914static int mpi3mr_alloc_reply_sense_bufs(struct mpi3mr_ioc *mrioc)
2915{
2916 int retval = 0;
2917 u32 sz, i;
2918
2919 if (mrioc->init_cmds.reply)
2920 return retval;
2921
2922 mrioc->init_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2923 if (!mrioc->init_cmds.reply)
2924 goto out_failed;
2925
2926 mrioc->bsg_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2927 if (!mrioc->bsg_cmds.reply)
2928 goto out_failed;
2929
2930 mrioc->transport_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2931 if (!mrioc->transport_cmds.reply)
2932 goto out_failed;
2933
2934 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
2935 mrioc->dev_rmhs_cmds[i].reply = kzalloc(mrioc->reply_sz,
2936 GFP_KERNEL);
2937 if (!mrioc->dev_rmhs_cmds[i].reply)
2938 goto out_failed;
2939 }
2940
2941 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
2942 mrioc->evtack_cmds[i].reply = kzalloc(mrioc->reply_sz,
2943 GFP_KERNEL);
2944 if (!mrioc->evtack_cmds[i].reply)
2945 goto out_failed;
2946 }
2947
2948 mrioc->host_tm_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2949 if (!mrioc->host_tm_cmds.reply)
2950 goto out_failed;
2951
2952 mrioc->pel_cmds.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2953 if (!mrioc->pel_cmds.reply)
2954 goto out_failed;
2955
2956 mrioc->pel_abort_cmd.reply = kzalloc(mrioc->reply_sz, GFP_KERNEL);
2957 if (!mrioc->pel_abort_cmd.reply)
2958 goto out_failed;
2959
2960 mrioc->dev_handle_bitmap_sz = mrioc->facts.max_devhandle / 8;
2961 if (mrioc->facts.max_devhandle % 8)
2962 mrioc->dev_handle_bitmap_sz++;
2963 mrioc->removepend_bitmap = kzalloc(mrioc->dev_handle_bitmap_sz,
2964 GFP_KERNEL);
2965 if (!mrioc->removepend_bitmap)
2966 goto out_failed;
2967
2968 mrioc->devrem_bitmap_sz = MPI3MR_NUM_DEVRMCMD / 8;
2969 if (MPI3MR_NUM_DEVRMCMD % 8)
2970 mrioc->devrem_bitmap_sz++;
2971 mrioc->devrem_bitmap = kzalloc(mrioc->devrem_bitmap_sz,
2972 GFP_KERNEL);
2973 if (!mrioc->devrem_bitmap)
2974 goto out_failed;
2975
2976 mrioc->evtack_cmds_bitmap_sz = MPI3MR_NUM_EVTACKCMD / 8;
2977 if (MPI3MR_NUM_EVTACKCMD % 8)
2978 mrioc->evtack_cmds_bitmap_sz++;
2979 mrioc->evtack_cmds_bitmap = kzalloc(mrioc->evtack_cmds_bitmap_sz,
2980 GFP_KERNEL);
2981 if (!mrioc->evtack_cmds_bitmap)
2982 goto out_failed;
2983
2984 mrioc->num_reply_bufs = mrioc->facts.max_reqs + MPI3MR_NUM_EVT_REPLIES;
2985 mrioc->reply_free_qsz = mrioc->num_reply_bufs + 1;
2986 mrioc->num_sense_bufs = mrioc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR;
2987 mrioc->sense_buf_q_sz = mrioc->num_sense_bufs + 1;
2988
2989 /* reply buffer pool, 16 byte align */
2990 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
2991 mrioc->reply_buf_pool = dma_pool_create("reply_buf pool",
2992 &mrioc->pdev->dev, sz, 16, 0);
2993 if (!mrioc->reply_buf_pool) {
2994 ioc_err(mrioc, "reply buf pool: dma_pool_create failed\n");
2995 goto out_failed;
2996 }
2997
2998 mrioc->reply_buf = dma_pool_zalloc(mrioc->reply_buf_pool, GFP_KERNEL,
2999 &mrioc->reply_buf_dma);
3000 if (!mrioc->reply_buf)
3001 goto out_failed;
3002
3003 mrioc->reply_buf_dma_max_address = mrioc->reply_buf_dma + sz;
3004
3005 /* reply free queue, 8 byte align */
3006 sz = mrioc->reply_free_qsz * 8;
3007 mrioc->reply_free_q_pool = dma_pool_create("reply_free_q pool",
3008 &mrioc->pdev->dev, sz, 8, 0);
3009 if (!mrioc->reply_free_q_pool) {
3010 ioc_err(mrioc, "reply_free_q pool: dma_pool_create failed\n");
3011 goto out_failed;
3012 }
3013 mrioc->reply_free_q = dma_pool_zalloc(mrioc->reply_free_q_pool,
3014 GFP_KERNEL, &mrioc->reply_free_q_dma);
3015 if (!mrioc->reply_free_q)
3016 goto out_failed;
3017
3018 /* sense buffer pool, 4 byte align */
3019 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3020 mrioc->sense_buf_pool = dma_pool_create("sense_buf pool",
3021 &mrioc->pdev->dev, sz, 4, 0);
3022 if (!mrioc->sense_buf_pool) {
3023 ioc_err(mrioc, "sense_buf pool: dma_pool_create failed\n");
3024 goto out_failed;
3025 }
3026 mrioc->sense_buf = dma_pool_zalloc(mrioc->sense_buf_pool, GFP_KERNEL,
3027 &mrioc->sense_buf_dma);
3028 if (!mrioc->sense_buf)
3029 goto out_failed;
3030
3031 /* sense buffer queue, 8 byte align */
3032 sz = mrioc->sense_buf_q_sz * 8;
3033 mrioc->sense_buf_q_pool = dma_pool_create("sense_buf_q pool",
3034 &mrioc->pdev->dev, sz, 8, 0);
3035 if (!mrioc->sense_buf_q_pool) {
3036 ioc_err(mrioc, "sense_buf_q pool: dma_pool_create failed\n");
3037 goto out_failed;
3038 }
3039 mrioc->sense_buf_q = dma_pool_zalloc(mrioc->sense_buf_q_pool,
3040 GFP_KERNEL, &mrioc->sense_buf_q_dma);
3041 if (!mrioc->sense_buf_q)
3042 goto out_failed;
3043
3044 return retval;
3045
3046out_failed:
3047 retval = -1;
3048 return retval;
3049}
3050
3051/**
3052 * mpimr_initialize_reply_sbuf_queues - initialize reply sense
3053 * buffers
3054 * @mrioc: Adapter instance reference
3055 *
3056 * Helper function to initialize reply and sense buffers along
3057 * with some debug prints.
3058 *
3059 * Return: None.
3060 */
3061static void mpimr_initialize_reply_sbuf_queues(struct mpi3mr_ioc *mrioc)
3062{
3063 u32 sz, i;
3064 dma_addr_t phy_addr;
3065
3066 sz = mrioc->num_reply_bufs * mrioc->reply_sz;
3067 ioc_info(mrioc,
3068 "reply buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3069 mrioc->reply_buf, mrioc->num_reply_bufs, mrioc->reply_sz,
3070 (sz / 1024), (unsigned long long)mrioc->reply_buf_dma);
3071 sz = mrioc->reply_free_qsz * 8;
3072 ioc_info(mrioc,
3073 "reply_free_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), reply_dma(0x%llx)\n",
3074 mrioc->reply_free_q, mrioc->reply_free_qsz, 8, (sz / 1024),
3075 (unsigned long long)mrioc->reply_free_q_dma);
3076 sz = mrioc->num_sense_bufs * MPI3MR_SENSE_BUF_SZ;
3077 ioc_info(mrioc,
3078 "sense_buf pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3079 mrioc->sense_buf, mrioc->num_sense_bufs, MPI3MR_SENSE_BUF_SZ,
3080 (sz / 1024), (unsigned long long)mrioc->sense_buf_dma);
3081 sz = mrioc->sense_buf_q_sz * 8;
3082 ioc_info(mrioc,
3083 "sense_buf_q pool(0x%p): depth(%d), frame_size(%d), pool_size(%d kB), sense_dma(0x%llx)\n",
3084 mrioc->sense_buf_q, mrioc->sense_buf_q_sz, 8, (sz / 1024),
3085 (unsigned long long)mrioc->sense_buf_q_dma);
3086
3087 /* initialize Reply buffer Queue */
3088 for (i = 0, phy_addr = mrioc->reply_buf_dma;
3089 i < mrioc->num_reply_bufs; i++, phy_addr += mrioc->reply_sz)
3090 mrioc->reply_free_q[i] = cpu_to_le64(phy_addr);
3091 mrioc->reply_free_q[i] = cpu_to_le64(0);
3092
3093 /* initialize Sense Buffer Queue */
3094 for (i = 0, phy_addr = mrioc->sense_buf_dma;
3095 i < mrioc->num_sense_bufs; i++, phy_addr += MPI3MR_SENSE_BUF_SZ)
3096 mrioc->sense_buf_q[i] = cpu_to_le64(phy_addr);
3097 mrioc->sense_buf_q[i] = cpu_to_le64(0);
3098}
3099
3100/**
3101 * mpi3mr_issue_iocinit - Send IOC Init
3102 * @mrioc: Adapter instance reference
3103 *
3104 * Issue IOC Init MPI request through admin queue and wait for
3105 * the completion of it or time out.
3106 *
3107 * Return: 0 on success, non-zero on failures.
3108 */
3109static int mpi3mr_issue_iocinit(struct mpi3mr_ioc *mrioc)
3110{
3111 struct mpi3_ioc_init_request iocinit_req;
3112 struct mpi3_driver_info_layout *drv_info;
3113 dma_addr_t data_dma;
3114 u32 data_len = sizeof(*drv_info);
3115 int retval = 0;
3116 ktime_t current_time;
3117
3118 drv_info = dma_alloc_coherent(&mrioc->pdev->dev, data_len, &data_dma,
3119 GFP_KERNEL);
3120 if (!drv_info) {
3121 retval = -1;
3122 goto out;
3123 }
3124 mpimr_initialize_reply_sbuf_queues(mrioc);
3125
3126 drv_info->information_length = cpu_to_le32(data_len);
3127 strscpy(drv_info->driver_signature, "Broadcom", sizeof(drv_info->driver_signature));
3128 strscpy(drv_info->os_name, utsname()->sysname, sizeof(drv_info->os_name));
3129 strscpy(drv_info->os_version, utsname()->release, sizeof(drv_info->os_version));
3130 strscpy(drv_info->driver_name, MPI3MR_DRIVER_NAME, sizeof(drv_info->driver_name));
3131 strscpy(drv_info->driver_version, MPI3MR_DRIVER_VERSION, sizeof(drv_info->driver_version));
3132 strscpy(drv_info->driver_release_date, MPI3MR_DRIVER_RELDATE,
3133 sizeof(drv_info->driver_release_date));
3134 drv_info->driver_capabilities = 0;
3135 memcpy((u8 *)&mrioc->driver_info, (u8 *)drv_info,
3136 sizeof(mrioc->driver_info));
3137
3138 memset(&iocinit_req, 0, sizeof(iocinit_req));
3139 mutex_lock(&mrioc->init_cmds.mutex);
3140 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3141 retval = -1;
3142 ioc_err(mrioc, "Issue IOCInit: Init command is in use\n");
3143 mutex_unlock(&mrioc->init_cmds.mutex);
3144 goto out;
3145 }
3146 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3147 mrioc->init_cmds.is_waiting = 1;
3148 mrioc->init_cmds.callback = NULL;
3149 iocinit_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3150 iocinit_req.function = MPI3_FUNCTION_IOC_INIT;
3151 iocinit_req.mpi_version.mpi3_version.dev = MPI3_VERSION_DEV;
3152 iocinit_req.mpi_version.mpi3_version.unit = MPI3_VERSION_UNIT;
3153 iocinit_req.mpi_version.mpi3_version.major = MPI3_VERSION_MAJOR;
3154 iocinit_req.mpi_version.mpi3_version.minor = MPI3_VERSION_MINOR;
3155 iocinit_req.who_init = MPI3_WHOINIT_HOST_DRIVER;
3156 iocinit_req.reply_free_queue_depth = cpu_to_le16(mrioc->reply_free_qsz);
3157 iocinit_req.reply_free_queue_address =
3158 cpu_to_le64(mrioc->reply_free_q_dma);
3159 iocinit_req.sense_buffer_length = cpu_to_le16(MPI3MR_SENSE_BUF_SZ);
3160 iocinit_req.sense_buffer_free_queue_depth =
3161 cpu_to_le16(mrioc->sense_buf_q_sz);
3162 iocinit_req.sense_buffer_free_queue_address =
3163 cpu_to_le64(mrioc->sense_buf_q_dma);
3164 iocinit_req.driver_information_address = cpu_to_le64(data_dma);
3165
3166 current_time = ktime_get_real();
3167 iocinit_req.time_stamp = cpu_to_le64(ktime_to_ms(current_time));
3168
3169 init_completion(&mrioc->init_cmds.done);
3170 retval = mpi3mr_admin_request_post(mrioc, &iocinit_req,
3171 sizeof(iocinit_req), 1);
3172 if (retval) {
3173 ioc_err(mrioc, "Issue IOCInit: Admin Post failed\n");
3174 goto out_unlock;
3175 }
3176 wait_for_completion_timeout(&mrioc->init_cmds.done,
3177 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3178 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3179 mpi3mr_check_rh_fault_ioc(mrioc,
3180 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT);
3181 ioc_err(mrioc, "ioc_init timed out\n");
3182 retval = -1;
3183 goto out_unlock;
3184 }
3185 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3186 != MPI3_IOCSTATUS_SUCCESS) {
3187 ioc_err(mrioc,
3188 "Issue IOCInit: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3189 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3190 mrioc->init_cmds.ioc_loginfo);
3191 retval = -1;
3192 goto out_unlock;
3193 }
3194
3195 mrioc->reply_free_queue_host_index = mrioc->num_reply_bufs;
3196 writel(mrioc->reply_free_queue_host_index,
3197 &mrioc->sysif_regs->reply_free_host_index);
3198
3199 mrioc->sbq_host_index = mrioc->num_sense_bufs;
3200 writel(mrioc->sbq_host_index,
3201 &mrioc->sysif_regs->sense_buffer_free_host_index);
3202out_unlock:
3203 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3204 mutex_unlock(&mrioc->init_cmds.mutex);
3205
3206out:
3207 if (drv_info)
3208 dma_free_coherent(&mrioc->pdev->dev, data_len, drv_info,
3209 data_dma);
3210
3211 return retval;
3212}
3213
3214/**
3215 * mpi3mr_unmask_events - Unmask events in event mask bitmap
3216 * @mrioc: Adapter instance reference
3217 * @event: MPI event ID
3218 *
3219 * Un mask the specific event by resetting the event_mask
3220 * bitmap.
3221 *
3222 * Return: 0 on success, non-zero on failures.
3223 */
3224static void mpi3mr_unmask_events(struct mpi3mr_ioc *mrioc, u16 event)
3225{
3226 u32 desired_event;
3227 u8 word;
3228
3229 if (event >= 128)
3230 return;
3231
3232 desired_event = (1 << (event % 32));
3233 word = event / 32;
3234
3235 mrioc->event_masks[word] &= ~desired_event;
3236}
3237
3238/**
3239 * mpi3mr_issue_event_notification - Send event notification
3240 * @mrioc: Adapter instance reference
3241 *
3242 * Issue event notification MPI request through admin queue and
3243 * wait for the completion of it or time out.
3244 *
3245 * Return: 0 on success, non-zero on failures.
3246 */
3247static int mpi3mr_issue_event_notification(struct mpi3mr_ioc *mrioc)
3248{
3249 struct mpi3_event_notification_request evtnotify_req;
3250 int retval = 0;
3251 u8 i;
3252
3253 memset(&evtnotify_req, 0, sizeof(evtnotify_req));
3254 mutex_lock(&mrioc->init_cmds.mutex);
3255 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3256 retval = -1;
3257 ioc_err(mrioc, "Issue EvtNotify: Init command is in use\n");
3258 mutex_unlock(&mrioc->init_cmds.mutex);
3259 goto out;
3260 }
3261 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3262 mrioc->init_cmds.is_waiting = 1;
3263 mrioc->init_cmds.callback = NULL;
3264 evtnotify_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3265 evtnotify_req.function = MPI3_FUNCTION_EVENT_NOTIFICATION;
3266 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3267 evtnotify_req.event_masks[i] =
3268 cpu_to_le32(mrioc->event_masks[i]);
3269 init_completion(&mrioc->init_cmds.done);
3270 retval = mpi3mr_admin_request_post(mrioc, &evtnotify_req,
3271 sizeof(evtnotify_req), 1);
3272 if (retval) {
3273 ioc_err(mrioc, "Issue EvtNotify: Admin Post failed\n");
3274 goto out_unlock;
3275 }
3276 wait_for_completion_timeout(&mrioc->init_cmds.done,
3277 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3278 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3279 ioc_err(mrioc, "event notification timed out\n");
3280 mpi3mr_check_rh_fault_ioc(mrioc,
3281 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT);
3282 retval = -1;
3283 goto out_unlock;
3284 }
3285 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3286 != MPI3_IOCSTATUS_SUCCESS) {
3287 ioc_err(mrioc,
3288 "Issue EvtNotify: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3289 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3290 mrioc->init_cmds.ioc_loginfo);
3291 retval = -1;
3292 goto out_unlock;
3293 }
3294
3295out_unlock:
3296 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3297 mutex_unlock(&mrioc->init_cmds.mutex);
3298out:
3299 return retval;
3300}
3301
3302/**
3303 * mpi3mr_process_event_ack - Process event acknowledgment
3304 * @mrioc: Adapter instance reference
3305 * @event: MPI3 event ID
3306 * @event_ctx: event context
3307 *
3308 * Send event acknowledgment through admin queue and wait for
3309 * it to complete.
3310 *
3311 * Return: 0 on success, non-zero on failures.
3312 */
3313int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
3314 u32 event_ctx)
3315{
3316 struct mpi3_event_ack_request evtack_req;
3317 int retval = 0;
3318
3319 memset(&evtack_req, 0, sizeof(evtack_req));
3320 mutex_lock(&mrioc->init_cmds.mutex);
3321 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3322 retval = -1;
3323 ioc_err(mrioc, "Send EvtAck: Init command is in use\n");
3324 mutex_unlock(&mrioc->init_cmds.mutex);
3325 goto out;
3326 }
3327 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3328 mrioc->init_cmds.is_waiting = 1;
3329 mrioc->init_cmds.callback = NULL;
3330 evtack_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3331 evtack_req.function = MPI3_FUNCTION_EVENT_ACK;
3332 evtack_req.event = event;
3333 evtack_req.event_context = cpu_to_le32(event_ctx);
3334
3335 init_completion(&mrioc->init_cmds.done);
3336 retval = mpi3mr_admin_request_post(mrioc, &evtack_req,
3337 sizeof(evtack_req), 1);
3338 if (retval) {
3339 ioc_err(mrioc, "Send EvtAck: Admin Post failed\n");
3340 goto out_unlock;
3341 }
3342 wait_for_completion_timeout(&mrioc->init_cmds.done,
3343 (MPI3MR_INTADMCMD_TIMEOUT * HZ));
3344 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3345 ioc_err(mrioc, "Issue EvtNotify: command timed out\n");
3346 if (!(mrioc->init_cmds.state & MPI3MR_CMD_RESET))
3347 mpi3mr_soft_reset_handler(mrioc,
3348 MPI3MR_RESET_FROM_EVTACK_TIMEOUT, 1);
3349 retval = -1;
3350 goto out_unlock;
3351 }
3352 if ((mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK)
3353 != MPI3_IOCSTATUS_SUCCESS) {
3354 ioc_err(mrioc,
3355 "Send EvtAck: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
3356 (mrioc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK),
3357 mrioc->init_cmds.ioc_loginfo);
3358 retval = -1;
3359 goto out_unlock;
3360 }
3361
3362out_unlock:
3363 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3364 mutex_unlock(&mrioc->init_cmds.mutex);
3365out:
3366 return retval;
3367}
3368
3369/**
3370 * mpi3mr_alloc_chain_bufs - Allocate chain buffers
3371 * @mrioc: Adapter instance reference
3372 *
3373 * Allocate chain buffers and set a bitmap to indicate free
3374 * chain buffers. Chain buffers are used to pass the SGE
3375 * information along with MPI3 SCSI IO requests for host I/O.
3376 *
3377 * Return: 0 on success, non-zero on failure
3378 */
3379static int mpi3mr_alloc_chain_bufs(struct mpi3mr_ioc *mrioc)
3380{
3381 int retval = 0;
3382 u32 sz, i;
3383 u16 num_chains;
3384
3385 if (mrioc->chain_sgl_list)
3386 return retval;
3387
3388 num_chains = mrioc->max_host_ios / MPI3MR_CHAINBUF_FACTOR;
3389
3390 if (prot_mask & (SHOST_DIX_TYPE0_PROTECTION
3391 | SHOST_DIX_TYPE1_PROTECTION
3392 | SHOST_DIX_TYPE2_PROTECTION
3393 | SHOST_DIX_TYPE3_PROTECTION))
3394 num_chains += (num_chains / MPI3MR_CHAINBUFDIX_FACTOR);
3395
3396 mrioc->chain_buf_count = num_chains;
3397 sz = sizeof(struct chain_element) * num_chains;
3398 mrioc->chain_sgl_list = kzalloc(sz, GFP_KERNEL);
3399 if (!mrioc->chain_sgl_list)
3400 goto out_failed;
3401
3402 sz = MPI3MR_PAGE_SIZE_4K;
3403 mrioc->chain_buf_pool = dma_pool_create("chain_buf pool",
3404 &mrioc->pdev->dev, sz, 16, 0);
3405 if (!mrioc->chain_buf_pool) {
3406 ioc_err(mrioc, "chain buf pool: dma_pool_create failed\n");
3407 goto out_failed;
3408 }
3409
3410 for (i = 0; i < num_chains; i++) {
3411 mrioc->chain_sgl_list[i].addr =
3412 dma_pool_zalloc(mrioc->chain_buf_pool, GFP_KERNEL,
3413 &mrioc->chain_sgl_list[i].dma_addr);
3414
3415 if (!mrioc->chain_sgl_list[i].addr)
3416 goto out_failed;
3417 }
3418 mrioc->chain_bitmap_sz = num_chains / 8;
3419 if (num_chains % 8)
3420 mrioc->chain_bitmap_sz++;
3421 mrioc->chain_bitmap = kzalloc(mrioc->chain_bitmap_sz, GFP_KERNEL);
3422 if (!mrioc->chain_bitmap)
3423 goto out_failed;
3424 return retval;
3425out_failed:
3426 retval = -1;
3427 return retval;
3428}
3429
3430/**
3431 * mpi3mr_port_enable_complete - Mark port enable complete
3432 * @mrioc: Adapter instance reference
3433 * @drv_cmd: Internal command tracker
3434 *
3435 * Call back for asynchronous port enable request sets the
3436 * driver command to indicate port enable request is complete.
3437 *
3438 * Return: Nothing
3439 */
3440static void mpi3mr_port_enable_complete(struct mpi3mr_ioc *mrioc,
3441 struct mpi3mr_drv_cmd *drv_cmd)
3442{
3443 drv_cmd->callback = NULL;
3444 mrioc->scan_started = 0;
3445 if (drv_cmd->state & MPI3MR_CMD_RESET)
3446 mrioc->scan_failed = MPI3_IOCSTATUS_INTERNAL_ERROR;
3447 else
3448 mrioc->scan_failed = drv_cmd->ioc_status;
3449 drv_cmd->state = MPI3MR_CMD_NOTUSED;
3450}
3451
3452/**
3453 * mpi3mr_issue_port_enable - Issue Port Enable
3454 * @mrioc: Adapter instance reference
3455 * @async: Flag to wait for completion or not
3456 *
3457 * Issue Port Enable MPI request through admin queue and if the
3458 * async flag is not set wait for the completion of the port
3459 * enable or time out.
3460 *
3461 * Return: 0 on success, non-zero on failures.
3462 */
3463int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async)
3464{
3465 struct mpi3_port_enable_request pe_req;
3466 int retval = 0;
3467 u32 pe_timeout = MPI3MR_PORTENABLE_TIMEOUT;
3468
3469 memset(&pe_req, 0, sizeof(pe_req));
3470 mutex_lock(&mrioc->init_cmds.mutex);
3471 if (mrioc->init_cmds.state & MPI3MR_CMD_PENDING) {
3472 retval = -1;
3473 ioc_err(mrioc, "Issue PortEnable: Init command is in use\n");
3474 mutex_unlock(&mrioc->init_cmds.mutex);
3475 goto out;
3476 }
3477 mrioc->init_cmds.state = MPI3MR_CMD_PENDING;
3478 if (async) {
3479 mrioc->init_cmds.is_waiting = 0;
3480 mrioc->init_cmds.callback = mpi3mr_port_enable_complete;
3481 } else {
3482 mrioc->init_cmds.is_waiting = 1;
3483 mrioc->init_cmds.callback = NULL;
3484 init_completion(&mrioc->init_cmds.done);
3485 }
3486 pe_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_INITCMDS);
3487 pe_req.function = MPI3_FUNCTION_PORT_ENABLE;
3488
3489 retval = mpi3mr_admin_request_post(mrioc, &pe_req, sizeof(pe_req), 1);
3490 if (retval) {
3491 ioc_err(mrioc, "Issue PortEnable: Admin Post failed\n");
3492 goto out_unlock;
3493 }
3494 if (async) {
3495 mutex_unlock(&mrioc->init_cmds.mutex);
3496 goto out;
3497 }
3498
3499 wait_for_completion_timeout(&mrioc->init_cmds.done, (pe_timeout * HZ));
3500 if (!(mrioc->init_cmds.state & MPI3MR_CMD_COMPLETE)) {
3501 ioc_err(mrioc, "port enable timed out\n");
3502 retval = -1;
3503 mpi3mr_check_rh_fault_ioc(mrioc, MPI3MR_RESET_FROM_PE_TIMEOUT);
3504 goto out_unlock;
3505 }
3506 mpi3mr_port_enable_complete(mrioc, &mrioc->init_cmds);
3507
3508out_unlock:
3509 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
3510 mutex_unlock(&mrioc->init_cmds.mutex);
3511out:
3512 return retval;
3513}
3514
3515/* Protocol type to name mapper structure */
3516static const struct {
3517 u8 protocol;
3518 char *name;
3519} mpi3mr_protocols[] = {
3520 { MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR, "Initiator" },
3521 { MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET, "Target" },
3522 { MPI3_IOCFACTS_PROTOCOL_NVME, "NVMe attachment" },
3523};
3524
3525/* Capability to name mapper structure*/
3526static const struct {
3527 u32 capability;
3528 char *name;
3529} mpi3mr_capabilities[] = {
3530 { MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE, "RAID" },
3531 { MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED, "MultiPath" },
3532};
3533
3534/**
3535 * mpi3mr_print_ioc_info - Display controller information
3536 * @mrioc: Adapter instance reference
3537 *
3538 * Display controller personalit, capability, supported
3539 * protocols etc.
3540 *
3541 * Return: Nothing
3542 */
3543static void
3544mpi3mr_print_ioc_info(struct mpi3mr_ioc *mrioc)
3545{
3546 int i = 0, bytes_written = 0;
3547 char personality[16];
3548 char protocol[50] = {0};
3549 char capabilities[100] = {0};
3550 struct mpi3mr_compimg_ver *fwver = &mrioc->facts.fw_ver;
3551
3552 switch (mrioc->facts.personality) {
3553 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA:
3554 strncpy(personality, "Enhanced HBA", sizeof(personality));
3555 break;
3556 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR:
3557 strncpy(personality, "RAID", sizeof(personality));
3558 break;
3559 default:
3560 strncpy(personality, "Unknown", sizeof(personality));
3561 break;
3562 }
3563
3564 ioc_info(mrioc, "Running in %s Personality", personality);
3565
3566 ioc_info(mrioc, "FW version(%d.%d.%d.%d.%d.%d)\n",
3567 fwver->gen_major, fwver->gen_minor, fwver->ph_major,
3568 fwver->ph_minor, fwver->cust_id, fwver->build_num);
3569
3570 for (i = 0; i < ARRAY_SIZE(mpi3mr_protocols); i++) {
3571 if (mrioc->facts.protocol_flags &
3572 mpi3mr_protocols[i].protocol) {
3573 bytes_written += scnprintf(protocol + bytes_written,
3574 sizeof(protocol) - bytes_written, "%s%s",
3575 bytes_written ? "," : "",
3576 mpi3mr_protocols[i].name);
3577 }
3578 }
3579
3580 bytes_written = 0;
3581 for (i = 0; i < ARRAY_SIZE(mpi3mr_capabilities); i++) {
3582 if (mrioc->facts.protocol_flags &
3583 mpi3mr_capabilities[i].capability) {
3584 bytes_written += scnprintf(capabilities + bytes_written,
3585 sizeof(capabilities) - bytes_written, "%s%s",
3586 bytes_written ? "," : "",
3587 mpi3mr_capabilities[i].name);
3588 }
3589 }
3590
3591 ioc_info(mrioc, "Protocol=(%s), Capabilities=(%s)\n",
3592 protocol, capabilities);
3593}
3594
3595/**
3596 * mpi3mr_cleanup_resources - Free PCI resources
3597 * @mrioc: Adapter instance reference
3598 *
3599 * Unmap PCI device memory and disable PCI device.
3600 *
3601 * Return: 0 on success and non-zero on failure.
3602 */
3603void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc)
3604{
3605 struct pci_dev *pdev = mrioc->pdev;
3606
3607 mpi3mr_cleanup_isr(mrioc);
3608
3609 if (mrioc->sysif_regs) {
3610 iounmap((void __iomem *)mrioc->sysif_regs);
3611 mrioc->sysif_regs = NULL;
3612 }
3613
3614 if (pci_is_enabled(pdev)) {
3615 if (mrioc->bars)
3616 pci_release_selected_regions(pdev, mrioc->bars);
3617 pci_disable_device(pdev);
3618 }
3619}
3620
3621/**
3622 * mpi3mr_setup_resources - Enable PCI resources
3623 * @mrioc: Adapter instance reference
3624 *
3625 * Enable PCI device memory, MSI-x registers and set DMA mask.
3626 *
3627 * Return: 0 on success and non-zero on failure.
3628 */
3629int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc)
3630{
3631 struct pci_dev *pdev = mrioc->pdev;
3632 u32 memap_sz = 0;
3633 int i, retval = 0, capb = 0;
3634 u16 message_control;
3635 u64 dma_mask = mrioc->dma_mask ? mrioc->dma_mask :
3636 ((sizeof(dma_addr_t) > 4) ? DMA_BIT_MASK(64) : DMA_BIT_MASK(32));
3637
3638 if (pci_enable_device_mem(pdev)) {
3639 ioc_err(mrioc, "pci_enable_device_mem: failed\n");
3640 retval = -ENODEV;
3641 goto out_failed;
3642 }
3643
3644 capb = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3645 if (!capb) {
3646 ioc_err(mrioc, "Unable to find MSI-X Capabilities\n");
3647 retval = -ENODEV;
3648 goto out_failed;
3649 }
3650 mrioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3651
3652 if (pci_request_selected_regions(pdev, mrioc->bars,
3653 mrioc->driver_name)) {
3654 ioc_err(mrioc, "pci_request_selected_regions: failed\n");
3655 retval = -ENODEV;
3656 goto out_failed;
3657 }
3658
3659 for (i = 0; (i < DEVICE_COUNT_RESOURCE); i++) {
3660 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3661 mrioc->sysif_regs_phys = pci_resource_start(pdev, i);
3662 memap_sz = pci_resource_len(pdev, i);
3663 mrioc->sysif_regs =
3664 ioremap(mrioc->sysif_regs_phys, memap_sz);
3665 break;
3666 }
3667 }
3668
3669 pci_set_master(pdev);
3670
3671 retval = dma_set_mask_and_coherent(&pdev->dev, dma_mask);
3672 if (retval) {
3673 if (dma_mask != DMA_BIT_MASK(32)) {
3674 ioc_warn(mrioc, "Setting 64 bit DMA mask failed\n");
3675 dma_mask = DMA_BIT_MASK(32);
3676 retval = dma_set_mask_and_coherent(&pdev->dev,
3677 dma_mask);
3678 }
3679 if (retval) {
3680 mrioc->dma_mask = 0;
3681 ioc_err(mrioc, "Setting 32 bit DMA mask also failed\n");
3682 goto out_failed;
3683 }
3684 }
3685 mrioc->dma_mask = dma_mask;
3686
3687 if (!mrioc->sysif_regs) {
3688 ioc_err(mrioc,
3689 "Unable to map adapter memory or resource not found\n");
3690 retval = -EINVAL;
3691 goto out_failed;
3692 }
3693
3694 pci_read_config_word(pdev, capb + 2, &message_control);
3695 mrioc->msix_count = (message_control & 0x3FF) + 1;
3696
3697 pci_save_state(pdev);
3698
3699 pci_set_drvdata(pdev, mrioc->shost);
3700
3701 mpi3mr_ioc_disable_intr(mrioc);
3702
3703 ioc_info(mrioc, "iomem(0x%016llx), mapped(0x%p), size(%d)\n",
3704 (unsigned long long)mrioc->sysif_regs_phys,
3705 mrioc->sysif_regs, memap_sz);
3706 ioc_info(mrioc, "Number of MSI-X vectors found in capabilities: (%d)\n",
3707 mrioc->msix_count);
3708
3709 if (!reset_devices && poll_queues > 0)
3710 mrioc->requested_poll_qcount = min_t(int, poll_queues,
3711 mrioc->msix_count - 2);
3712 return retval;
3713
3714out_failed:
3715 mpi3mr_cleanup_resources(mrioc);
3716 return retval;
3717}
3718
3719/**
3720 * mpi3mr_enable_events - Enable required events
3721 * @mrioc: Adapter instance reference
3722 *
3723 * This routine unmasks the events required by the driver by
3724 * sennding appropriate event mask bitmapt through an event
3725 * notification request.
3726 *
3727 * Return: 0 on success and non-zero on failure.
3728 */
3729static int mpi3mr_enable_events(struct mpi3mr_ioc *mrioc)
3730{
3731 int retval = 0;
3732 u32 i;
3733
3734 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
3735 mrioc->event_masks[i] = -1;
3736
3737 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_ADDED);
3738 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_INFO_CHANGED);
3739 mpi3mr_unmask_events(mrioc, MPI3_EVENT_DEVICE_STATUS_CHANGE);
3740 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE);
3741 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENCL_DEVICE_ADDED);
3742 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST);
3743 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DISCOVERY);
3744 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR);
3745 mpi3mr_unmask_events(mrioc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE);
3746 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST);
3747 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PCIE_ENUMERATION);
3748 mpi3mr_unmask_events(mrioc, MPI3_EVENT_PREPARE_FOR_RESET);
3749 mpi3mr_unmask_events(mrioc, MPI3_EVENT_CABLE_MGMT);
3750 mpi3mr_unmask_events(mrioc, MPI3_EVENT_ENERGY_PACK_CHANGE);
3751
3752 retval = mpi3mr_issue_event_notification(mrioc);
3753 if (retval)
3754 ioc_err(mrioc, "failed to issue event notification %d\n",
3755 retval);
3756 return retval;
3757}
3758
3759/**
3760 * mpi3mr_init_ioc - Initialize the controller
3761 * @mrioc: Adapter instance reference
3762 *
3763 * This the controller initialization routine, executed either
3764 * after soft reset or from pci probe callback.
3765 * Setup the required resources, memory map the controller
3766 * registers, create admin and operational reply queue pairs,
3767 * allocate required memory for reply pool, sense buffer pool,
3768 * issue IOC init request to the firmware, unmask the events and
3769 * issue port enable to discover SAS/SATA/NVMe devies and RAID
3770 * volumes.
3771 *
3772 * Return: 0 on success and non-zero on failure.
3773 */
3774int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc)
3775{
3776 int retval = 0;
3777 u8 retry = 0;
3778 struct mpi3_ioc_facts_data facts_data;
3779 u32 sz;
3780
3781retry_init:
3782 retval = mpi3mr_bring_ioc_ready(mrioc);
3783 if (retval) {
3784 ioc_err(mrioc, "Failed to bring ioc ready: error %d\n",
3785 retval);
3786 goto out_failed_noretry;
3787 }
3788
3789 retval = mpi3mr_setup_isr(mrioc, 1);
3790 if (retval) {
3791 ioc_err(mrioc, "Failed to setup ISR error %d\n",
3792 retval);
3793 goto out_failed_noretry;
3794 }
3795
3796 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3797 if (retval) {
3798 ioc_err(mrioc, "Failed to Issue IOC Facts %d\n",
3799 retval);
3800 goto out_failed;
3801 }
3802
3803 mrioc->max_host_ios = mrioc->facts.max_reqs - MPI3MR_INTERNAL_CMDS_RESVD;
3804
3805 mrioc->num_io_throttle_group = mrioc->facts.max_io_throttle_group;
3806 atomic_set(&mrioc->pend_large_data_sz, 0);
3807
3808 if (reset_devices)
3809 mrioc->max_host_ios = min_t(int, mrioc->max_host_ios,
3810 MPI3MR_HOST_IOS_KDUMP);
3811
3812 if (!(mrioc->facts.ioc_capabilities &
3813 MPI3_IOCFACTS_CAPABILITY_MULTIPATH_ENABLED)) {
3814 mrioc->sas_transport_enabled = 1;
3815 mrioc->scsi_device_channel = 1;
3816 mrioc->shost->max_channel = 1;
3817 mrioc->shost->transportt = mpi3mr_transport_template;
3818 }
3819
3820 mrioc->reply_sz = mrioc->facts.reply_sz;
3821
3822 retval = mpi3mr_check_reset_dma_mask(mrioc);
3823 if (retval) {
3824 ioc_err(mrioc, "Resetting dma mask failed %d\n",
3825 retval);
3826 goto out_failed_noretry;
3827 }
3828
3829 mpi3mr_print_ioc_info(mrioc);
3830
3831 dprint_init(mrioc, "allocating config page buffers\n");
3832 mrioc->cfg_page = dma_alloc_coherent(&mrioc->pdev->dev,
3833 MPI3MR_DEFAULT_CFG_PAGE_SZ, &mrioc->cfg_page_dma, GFP_KERNEL);
3834 if (!mrioc->cfg_page)
3835 goto out_failed_noretry;
3836
3837 mrioc->cfg_page_sz = MPI3MR_DEFAULT_CFG_PAGE_SZ;
3838
3839 retval = mpi3mr_alloc_reply_sense_bufs(mrioc);
3840 if (retval) {
3841 ioc_err(mrioc,
3842 "%s :Failed to allocated reply sense buffers %d\n",
3843 __func__, retval);
3844 goto out_failed_noretry;
3845 }
3846
3847 retval = mpi3mr_alloc_chain_bufs(mrioc);
3848 if (retval) {
3849 ioc_err(mrioc, "Failed to allocated chain buffers %d\n",
3850 retval);
3851 goto out_failed_noretry;
3852 }
3853
3854 retval = mpi3mr_issue_iocinit(mrioc);
3855 if (retval) {
3856 ioc_err(mrioc, "Failed to Issue IOC Init %d\n",
3857 retval);
3858 goto out_failed;
3859 }
3860
3861 retval = mpi3mr_print_pkg_ver(mrioc);
3862 if (retval) {
3863 ioc_err(mrioc, "failed to get package version\n");
3864 goto out_failed;
3865 }
3866
3867 retval = mpi3mr_setup_isr(mrioc, 0);
3868 if (retval) {
3869 ioc_err(mrioc, "Failed to re-setup ISR, error %d\n",
3870 retval);
3871 goto out_failed_noretry;
3872 }
3873
3874 retval = mpi3mr_create_op_queues(mrioc);
3875 if (retval) {
3876 ioc_err(mrioc, "Failed to create OpQueues error %d\n",
3877 retval);
3878 goto out_failed;
3879 }
3880
3881 if (!mrioc->pel_seqnum_virt) {
3882 dprint_init(mrioc, "allocating memory for pel_seqnum_virt\n");
3883 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
3884 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
3885 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
3886 GFP_KERNEL);
3887 if (!mrioc->pel_seqnum_virt) {
3888 retval = -ENOMEM;
3889 goto out_failed_noretry;
3890 }
3891 }
3892
3893 if (!mrioc->throttle_groups && mrioc->num_io_throttle_group) {
3894 dprint_init(mrioc, "allocating memory for throttle groups\n");
3895 sz = sizeof(struct mpi3mr_throttle_group_info);
3896 mrioc->throttle_groups = kcalloc(mrioc->num_io_throttle_group, sz, GFP_KERNEL);
3897 if (!mrioc->throttle_groups)
3898 goto out_failed_noretry;
3899 }
3900
3901 retval = mpi3mr_enable_events(mrioc);
3902 if (retval) {
3903 ioc_err(mrioc, "failed to enable events %d\n",
3904 retval);
3905 goto out_failed;
3906 }
3907
3908 ioc_info(mrioc, "controller initialization completed successfully\n");
3909 return retval;
3910out_failed:
3911 if (retry < 2) {
3912 retry++;
3913 ioc_warn(mrioc, "retrying controller initialization, retry_count:%d\n",
3914 retry);
3915 mpi3mr_memset_buffers(mrioc);
3916 goto retry_init;
3917 }
3918out_failed_noretry:
3919 ioc_err(mrioc, "controller initialization failed\n");
3920 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
3921 MPI3MR_RESET_FROM_CTLR_CLEANUP);
3922 mrioc->unrecoverable = 1;
3923 return retval;
3924}
3925
3926/**
3927 * mpi3mr_reinit_ioc - Re-Initialize the controller
3928 * @mrioc: Adapter instance reference
3929 * @is_resume: Called from resume or reset path
3930 *
3931 * This the controller re-initialization routine, executed from
3932 * the soft reset handler or resume callback. Creates
3933 * operational reply queue pairs, allocate required memory for
3934 * reply pool, sense buffer pool, issue IOC init request to the
3935 * firmware, unmask the events and issue port enable to discover
3936 * SAS/SATA/NVMe devices and RAID volumes.
3937 *
3938 * Return: 0 on success and non-zero on failure.
3939 */
3940int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume)
3941{
3942 int retval = 0;
3943 u8 retry = 0;
3944 struct mpi3_ioc_facts_data facts_data;
3945 u32 pe_timeout, ioc_status;
3946
3947retry_init:
3948 pe_timeout =
3949 (MPI3MR_PORTENABLE_TIMEOUT / MPI3MR_PORTENABLE_POLL_INTERVAL);
3950
3951 dprint_reset(mrioc, "bringing up the controller to ready state\n");
3952 retval = mpi3mr_bring_ioc_ready(mrioc);
3953 if (retval) {
3954 ioc_err(mrioc, "failed to bring to ready state\n");
3955 goto out_failed_noretry;
3956 }
3957
3958 if (is_resume) {
3959 dprint_reset(mrioc, "setting up single ISR\n");
3960 retval = mpi3mr_setup_isr(mrioc, 1);
3961 if (retval) {
3962 ioc_err(mrioc, "failed to setup ISR\n");
3963 goto out_failed_noretry;
3964 }
3965 } else
3966 mpi3mr_ioc_enable_intr(mrioc);
3967
3968 dprint_reset(mrioc, "getting ioc_facts\n");
3969 retval = mpi3mr_issue_iocfacts(mrioc, &facts_data);
3970 if (retval) {
3971 ioc_err(mrioc, "failed to get ioc_facts\n");
3972 goto out_failed;
3973 }
3974
3975 dprint_reset(mrioc, "validating ioc_facts\n");
3976 retval = mpi3mr_revalidate_factsdata(mrioc);
3977 if (retval) {
3978 ioc_err(mrioc, "failed to revalidate ioc_facts data\n");
3979 goto out_failed_noretry;
3980 }
3981
3982 mpi3mr_print_ioc_info(mrioc);
3983
3984 dprint_reset(mrioc, "sending ioc_init\n");
3985 retval = mpi3mr_issue_iocinit(mrioc);
3986 if (retval) {
3987 ioc_err(mrioc, "failed to send ioc_init\n");
3988 goto out_failed;
3989 }
3990
3991 dprint_reset(mrioc, "getting package version\n");
3992 retval = mpi3mr_print_pkg_ver(mrioc);
3993 if (retval) {
3994 ioc_err(mrioc, "failed to get package version\n");
3995 goto out_failed;
3996 }
3997
3998 if (is_resume) {
3999 dprint_reset(mrioc, "setting up multiple ISR\n");
4000 retval = mpi3mr_setup_isr(mrioc, 0);
4001 if (retval) {
4002 ioc_err(mrioc, "failed to re-setup ISR\n");
4003 goto out_failed_noretry;
4004 }
4005 }
4006
4007 dprint_reset(mrioc, "creating operational queue pairs\n");
4008 retval = mpi3mr_create_op_queues(mrioc);
4009 if (retval) {
4010 ioc_err(mrioc, "failed to create operational queue pairs\n");
4011 goto out_failed;
4012 }
4013
4014 if (!mrioc->pel_seqnum_virt) {
4015 dprint_reset(mrioc, "allocating memory for pel_seqnum_virt\n");
4016 mrioc->pel_seqnum_sz = sizeof(struct mpi3_pel_seq);
4017 mrioc->pel_seqnum_virt = dma_alloc_coherent(&mrioc->pdev->dev,
4018 mrioc->pel_seqnum_sz, &mrioc->pel_seqnum_dma,
4019 GFP_KERNEL);
4020 if (!mrioc->pel_seqnum_virt) {
4021 retval = -ENOMEM;
4022 goto out_failed_noretry;
4023 }
4024 }
4025
4026 if (mrioc->shost->nr_hw_queues > mrioc->num_op_reply_q) {
4027 ioc_err(mrioc,
4028 "cannot create minimum number of operational queues expected:%d created:%d\n",
4029 mrioc->shost->nr_hw_queues, mrioc->num_op_reply_q);
4030 goto out_failed_noretry;
4031 }
4032
4033 dprint_reset(mrioc, "enabling events\n");
4034 retval = mpi3mr_enable_events(mrioc);
4035 if (retval) {
4036 ioc_err(mrioc, "failed to enable events\n");
4037 goto out_failed;
4038 }
4039
4040 mrioc->device_refresh_on = 1;
4041 mpi3mr_add_event_wait_for_device_refresh(mrioc);
4042
4043 ioc_info(mrioc, "sending port enable\n");
4044 retval = mpi3mr_issue_port_enable(mrioc, 1);
4045 if (retval) {
4046 ioc_err(mrioc, "failed to issue port enable\n");
4047 goto out_failed;
4048 }
4049 do {
4050 ssleep(MPI3MR_PORTENABLE_POLL_INTERVAL);
4051 if (mrioc->init_cmds.state == MPI3MR_CMD_NOTUSED)
4052 break;
4053 if (!pci_device_is_present(mrioc->pdev))
4054 mrioc->unrecoverable = 1;
4055 if (mrioc->unrecoverable) {
4056 retval = -1;
4057 goto out_failed_noretry;
4058 }
4059 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4060 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) ||
4061 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) {
4062 mpi3mr_print_fault_info(mrioc);
4063 mrioc->init_cmds.is_waiting = 0;
4064 mrioc->init_cmds.callback = NULL;
4065 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4066 goto out_failed;
4067 }
4068 } while (--pe_timeout);
4069
4070 if (!pe_timeout) {
4071 ioc_err(mrioc, "port enable timed out\n");
4072 mpi3mr_check_rh_fault_ioc(mrioc,
4073 MPI3MR_RESET_FROM_PE_TIMEOUT);
4074 mrioc->init_cmds.is_waiting = 0;
4075 mrioc->init_cmds.callback = NULL;
4076 mrioc->init_cmds.state = MPI3MR_CMD_NOTUSED;
4077 goto out_failed;
4078 } else if (mrioc->scan_failed) {
4079 ioc_err(mrioc,
4080 "port enable failed with status=0x%04x\n",
4081 mrioc->scan_failed);
4082 } else
4083 ioc_info(mrioc, "port enable completed successfully\n");
4084
4085 ioc_info(mrioc, "controller %s completed successfully\n",
4086 (is_resume)?"resume":"re-initialization");
4087 return retval;
4088out_failed:
4089 if (retry < 2) {
4090 retry++;
4091 ioc_warn(mrioc, "retrying controller %s, retry_count:%d\n",
4092 (is_resume)?"resume":"re-initialization", retry);
4093 mpi3mr_memset_buffers(mrioc);
4094 goto retry_init;
4095 }
4096out_failed_noretry:
4097 ioc_err(mrioc, "controller %s is failed\n",
4098 (is_resume)?"resume":"re-initialization");
4099 mpi3mr_issue_reset(mrioc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT,
4100 MPI3MR_RESET_FROM_CTLR_CLEANUP);
4101 mrioc->unrecoverable = 1;
4102 return retval;
4103}
4104
4105/**
4106 * mpi3mr_memset_op_reply_q_buffers - memset the operational reply queue's
4107 * segments
4108 * @mrioc: Adapter instance reference
4109 * @qidx: Operational reply queue index
4110 *
4111 * Return: Nothing.
4112 */
4113static void mpi3mr_memset_op_reply_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4114{
4115 struct op_reply_qinfo *op_reply_q = mrioc->op_reply_qinfo + qidx;
4116 struct segments *segments;
4117 int i, size;
4118
4119 if (!op_reply_q->q_segments)
4120 return;
4121
4122 size = op_reply_q->segment_qd * mrioc->op_reply_desc_sz;
4123 segments = op_reply_q->q_segments;
4124 for (i = 0; i < op_reply_q->num_segments; i++)
4125 memset(segments[i].segment, 0, size);
4126}
4127
4128/**
4129 * mpi3mr_memset_op_req_q_buffers - memset the operational request queue's
4130 * segments
4131 * @mrioc: Adapter instance reference
4132 * @qidx: Operational request queue index
4133 *
4134 * Return: Nothing.
4135 */
4136static void mpi3mr_memset_op_req_q_buffers(struct mpi3mr_ioc *mrioc, u16 qidx)
4137{
4138 struct op_req_qinfo *op_req_q = mrioc->req_qinfo + qidx;
4139 struct segments *segments;
4140 int i, size;
4141
4142 if (!op_req_q->q_segments)
4143 return;
4144
4145 size = op_req_q->segment_qd * mrioc->facts.op_req_sz;
4146 segments = op_req_q->q_segments;
4147 for (i = 0; i < op_req_q->num_segments; i++)
4148 memset(segments[i].segment, 0, size);
4149}
4150
4151/**
4152 * mpi3mr_memset_buffers - memset memory for a controller
4153 * @mrioc: Adapter instance reference
4154 *
4155 * clear all the memory allocated for a controller, typically
4156 * called post reset to reuse the memory allocated during the
4157 * controller init.
4158 *
4159 * Return: Nothing.
4160 */
4161void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc)
4162{
4163 u16 i;
4164 struct mpi3mr_throttle_group_info *tg;
4165
4166 mrioc->change_count = 0;
4167 mrioc->active_poll_qcount = 0;
4168 mrioc->default_qcount = 0;
4169 if (mrioc->admin_req_base)
4170 memset(mrioc->admin_req_base, 0, mrioc->admin_req_q_sz);
4171 if (mrioc->admin_reply_base)
4172 memset(mrioc->admin_reply_base, 0, mrioc->admin_reply_q_sz);
4173
4174 if (mrioc->init_cmds.reply) {
4175 memset(mrioc->init_cmds.reply, 0, sizeof(*mrioc->init_cmds.reply));
4176 memset(mrioc->bsg_cmds.reply, 0,
4177 sizeof(*mrioc->bsg_cmds.reply));
4178 memset(mrioc->host_tm_cmds.reply, 0,
4179 sizeof(*mrioc->host_tm_cmds.reply));
4180 memset(mrioc->pel_cmds.reply, 0,
4181 sizeof(*mrioc->pel_cmds.reply));
4182 memset(mrioc->pel_abort_cmd.reply, 0,
4183 sizeof(*mrioc->pel_abort_cmd.reply));
4184 memset(mrioc->transport_cmds.reply, 0,
4185 sizeof(*mrioc->transport_cmds.reply));
4186 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++)
4187 memset(mrioc->dev_rmhs_cmds[i].reply, 0,
4188 sizeof(*mrioc->dev_rmhs_cmds[i].reply));
4189 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++)
4190 memset(mrioc->evtack_cmds[i].reply, 0,
4191 sizeof(*mrioc->evtack_cmds[i].reply));
4192 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
4193 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
4194 memset(mrioc->evtack_cmds_bitmap, 0,
4195 mrioc->evtack_cmds_bitmap_sz);
4196 }
4197
4198 for (i = 0; i < mrioc->num_queues; i++) {
4199 mrioc->op_reply_qinfo[i].qid = 0;
4200 mrioc->op_reply_qinfo[i].ci = 0;
4201 mrioc->op_reply_qinfo[i].num_replies = 0;
4202 mrioc->op_reply_qinfo[i].ephase = 0;
4203 atomic_set(&mrioc->op_reply_qinfo[i].pend_ios, 0);
4204 atomic_set(&mrioc->op_reply_qinfo[i].in_use, 0);
4205 mpi3mr_memset_op_reply_q_buffers(mrioc, i);
4206
4207 mrioc->req_qinfo[i].ci = 0;
4208 mrioc->req_qinfo[i].pi = 0;
4209 mrioc->req_qinfo[i].num_requests = 0;
4210 mrioc->req_qinfo[i].qid = 0;
4211 mrioc->req_qinfo[i].reply_qid = 0;
4212 spin_lock_init(&mrioc->req_qinfo[i].q_lock);
4213 mpi3mr_memset_op_req_q_buffers(mrioc, i);
4214 }
4215
4216 atomic_set(&mrioc->pend_large_data_sz, 0);
4217 if (mrioc->throttle_groups) {
4218 tg = mrioc->throttle_groups;
4219 for (i = 0; i < mrioc->num_io_throttle_group; i++, tg++) {
4220 tg->id = 0;
4221 tg->fw_qd = 0;
4222 tg->modified_qd = 0;
4223 tg->io_divert = 0;
4224 tg->need_qd_reduction = 0;
4225 tg->high = 0;
4226 tg->low = 0;
4227 tg->qd_reduction = 0;
4228 atomic_set(&tg->pend_large_data_sz, 0);
4229 }
4230 }
4231}
4232
4233/**
4234 * mpi3mr_free_mem - Free memory allocated for a controller
4235 * @mrioc: Adapter instance reference
4236 *
4237 * Free all the memory allocated for a controller.
4238 *
4239 * Return: Nothing.
4240 */
4241void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc)
4242{
4243 u16 i;
4244 struct mpi3mr_intr_info *intr_info;
4245
4246 mpi3mr_free_enclosure_list(mrioc);
4247
4248 if (mrioc->sense_buf_pool) {
4249 if (mrioc->sense_buf)
4250 dma_pool_free(mrioc->sense_buf_pool, mrioc->sense_buf,
4251 mrioc->sense_buf_dma);
4252 dma_pool_destroy(mrioc->sense_buf_pool);
4253 mrioc->sense_buf = NULL;
4254 mrioc->sense_buf_pool = NULL;
4255 }
4256 if (mrioc->sense_buf_q_pool) {
4257 if (mrioc->sense_buf_q)
4258 dma_pool_free(mrioc->sense_buf_q_pool,
4259 mrioc->sense_buf_q, mrioc->sense_buf_q_dma);
4260 dma_pool_destroy(mrioc->sense_buf_q_pool);
4261 mrioc->sense_buf_q = NULL;
4262 mrioc->sense_buf_q_pool = NULL;
4263 }
4264
4265 if (mrioc->reply_buf_pool) {
4266 if (mrioc->reply_buf)
4267 dma_pool_free(mrioc->reply_buf_pool, mrioc->reply_buf,
4268 mrioc->reply_buf_dma);
4269 dma_pool_destroy(mrioc->reply_buf_pool);
4270 mrioc->reply_buf = NULL;
4271 mrioc->reply_buf_pool = NULL;
4272 }
4273 if (mrioc->reply_free_q_pool) {
4274 if (mrioc->reply_free_q)
4275 dma_pool_free(mrioc->reply_free_q_pool,
4276 mrioc->reply_free_q, mrioc->reply_free_q_dma);
4277 dma_pool_destroy(mrioc->reply_free_q_pool);
4278 mrioc->reply_free_q = NULL;
4279 mrioc->reply_free_q_pool = NULL;
4280 }
4281
4282 for (i = 0; i < mrioc->num_op_req_q; i++)
4283 mpi3mr_free_op_req_q_segments(mrioc, i);
4284
4285 for (i = 0; i < mrioc->num_op_reply_q; i++)
4286 mpi3mr_free_op_reply_q_segments(mrioc, i);
4287
4288 for (i = 0; i < mrioc->intr_info_count; i++) {
4289 intr_info = mrioc->intr_info + i;
4290 intr_info->op_reply_q = NULL;
4291 }
4292
4293 kfree(mrioc->req_qinfo);
4294 mrioc->req_qinfo = NULL;
4295 mrioc->num_op_req_q = 0;
4296
4297 kfree(mrioc->op_reply_qinfo);
4298 mrioc->op_reply_qinfo = NULL;
4299 mrioc->num_op_reply_q = 0;
4300
4301 kfree(mrioc->init_cmds.reply);
4302 mrioc->init_cmds.reply = NULL;
4303
4304 kfree(mrioc->bsg_cmds.reply);
4305 mrioc->bsg_cmds.reply = NULL;
4306
4307 kfree(mrioc->host_tm_cmds.reply);
4308 mrioc->host_tm_cmds.reply = NULL;
4309
4310 kfree(mrioc->pel_cmds.reply);
4311 mrioc->pel_cmds.reply = NULL;
4312
4313 kfree(mrioc->pel_abort_cmd.reply);
4314 mrioc->pel_abort_cmd.reply = NULL;
4315
4316 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4317 kfree(mrioc->evtack_cmds[i].reply);
4318 mrioc->evtack_cmds[i].reply = NULL;
4319 }
4320
4321 kfree(mrioc->removepend_bitmap);
4322 mrioc->removepend_bitmap = NULL;
4323
4324 kfree(mrioc->devrem_bitmap);
4325 mrioc->devrem_bitmap = NULL;
4326
4327 kfree(mrioc->evtack_cmds_bitmap);
4328 mrioc->evtack_cmds_bitmap = NULL;
4329
4330 kfree(mrioc->chain_bitmap);
4331 mrioc->chain_bitmap = NULL;
4332
4333 kfree(mrioc->transport_cmds.reply);
4334 mrioc->transport_cmds.reply = NULL;
4335
4336 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4337 kfree(mrioc->dev_rmhs_cmds[i].reply);
4338 mrioc->dev_rmhs_cmds[i].reply = NULL;
4339 }
4340
4341 if (mrioc->chain_buf_pool) {
4342 for (i = 0; i < mrioc->chain_buf_count; i++) {
4343 if (mrioc->chain_sgl_list[i].addr) {
4344 dma_pool_free(mrioc->chain_buf_pool,
4345 mrioc->chain_sgl_list[i].addr,
4346 mrioc->chain_sgl_list[i].dma_addr);
4347 mrioc->chain_sgl_list[i].addr = NULL;
4348 }
4349 }
4350 dma_pool_destroy(mrioc->chain_buf_pool);
4351 mrioc->chain_buf_pool = NULL;
4352 }
4353
4354 kfree(mrioc->chain_sgl_list);
4355 mrioc->chain_sgl_list = NULL;
4356
4357 if (mrioc->admin_reply_base) {
4358 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_reply_q_sz,
4359 mrioc->admin_reply_base, mrioc->admin_reply_dma);
4360 mrioc->admin_reply_base = NULL;
4361 }
4362 if (mrioc->admin_req_base) {
4363 dma_free_coherent(&mrioc->pdev->dev, mrioc->admin_req_q_sz,
4364 mrioc->admin_req_base, mrioc->admin_req_dma);
4365 mrioc->admin_req_base = NULL;
4366 }
4367
4368 if (mrioc->pel_seqnum_virt) {
4369 dma_free_coherent(&mrioc->pdev->dev, mrioc->pel_seqnum_sz,
4370 mrioc->pel_seqnum_virt, mrioc->pel_seqnum_dma);
4371 mrioc->pel_seqnum_virt = NULL;
4372 }
4373
4374 kfree(mrioc->logdata_buf);
4375 mrioc->logdata_buf = NULL;
4376
4377}
4378
4379/**
4380 * mpi3mr_issue_ioc_shutdown - shutdown controller
4381 * @mrioc: Adapter instance reference
4382 *
4383 * Send shutodwn notification to the controller and wait for the
4384 * shutdown_timeout for it to be completed.
4385 *
4386 * Return: Nothing.
4387 */
4388static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_ioc *mrioc)
4389{
4390 u32 ioc_config, ioc_status;
4391 u8 retval = 1;
4392 u32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10;
4393
4394 ioc_info(mrioc, "Issuing shutdown Notification\n");
4395 if (mrioc->unrecoverable) {
4396 ioc_warn(mrioc,
4397 "IOC is unrecoverable shutdown is not issued\n");
4398 return;
4399 }
4400 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4401 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4402 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) {
4403 ioc_info(mrioc, "shutdown already in progress\n");
4404 return;
4405 }
4406
4407 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4408 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL;
4409 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ;
4410
4411 writel(ioc_config, &mrioc->sysif_regs->ioc_configuration);
4412
4413 if (mrioc->facts.shutdown_timeout)
4414 timeout = mrioc->facts.shutdown_timeout * 10;
4415
4416 do {
4417 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4418 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4419 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) {
4420 retval = 0;
4421 break;
4422 }
4423 msleep(100);
4424 } while (--timeout);
4425
4426 ioc_status = readl(&mrioc->sysif_regs->ioc_status);
4427 ioc_config = readl(&mrioc->sysif_regs->ioc_configuration);
4428
4429 if (retval) {
4430 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK)
4431 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS)
4432 ioc_warn(mrioc,
4433 "shutdown still in progress after timeout\n");
4434 }
4435
4436 ioc_info(mrioc,
4437 "Base IOC Sts/Config after %s shutdown is (0x%x)/(0x%x)\n",
4438 (!retval) ? "successful" : "failed", ioc_status,
4439 ioc_config);
4440}
4441
4442/**
4443 * mpi3mr_cleanup_ioc - Cleanup controller
4444 * @mrioc: Adapter instance reference
4445 *
4446 * controller cleanup handler, Message unit reset or soft reset
4447 * and shutdown notification is issued to the controller.
4448 *
4449 * Return: Nothing.
4450 */
4451void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc)
4452{
4453 enum mpi3mr_iocstate ioc_state;
4454
4455 dprint_exit(mrioc, "cleaning up the controller\n");
4456 mpi3mr_ioc_disable_intr(mrioc);
4457
4458 ioc_state = mpi3mr_get_iocstate(mrioc);
4459
4460 if ((!mrioc->unrecoverable) && (!mrioc->reset_in_progress) &&
4461 (ioc_state == MRIOC_STATE_READY)) {
4462 if (mpi3mr_issue_and_process_mur(mrioc,
4463 MPI3MR_RESET_FROM_CTLR_CLEANUP))
4464 mpi3mr_issue_reset(mrioc,
4465 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET,
4466 MPI3MR_RESET_FROM_MUR_FAILURE);
4467 mpi3mr_issue_ioc_shutdown(mrioc);
4468 }
4469 dprint_exit(mrioc, "controller cleanup completed\n");
4470}
4471
4472/**
4473 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command
4474 * @mrioc: Adapter instance reference
4475 * @cmdptr: Internal command tracker
4476 *
4477 * Complete an internal driver commands with state indicating it
4478 * is completed due to reset.
4479 *
4480 * Return: Nothing.
4481 */
4482static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_ioc *mrioc,
4483 struct mpi3mr_drv_cmd *cmdptr)
4484{
4485 if (cmdptr->state & MPI3MR_CMD_PENDING) {
4486 cmdptr->state |= MPI3MR_CMD_RESET;
4487 cmdptr->state &= ~MPI3MR_CMD_PENDING;
4488 if (cmdptr->is_waiting) {
4489 complete(&cmdptr->done);
4490 cmdptr->is_waiting = 0;
4491 } else if (cmdptr->callback)
4492 cmdptr->callback(mrioc, cmdptr);
4493 }
4494}
4495
4496/**
4497 * mpi3mr_flush_drv_cmds - Flush internaldriver commands
4498 * @mrioc: Adapter instance reference
4499 *
4500 * Flush all internal driver commands post reset
4501 *
4502 * Return: Nothing.
4503 */
4504void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc)
4505{
4506 struct mpi3mr_drv_cmd *cmdptr;
4507 u8 i;
4508
4509 cmdptr = &mrioc->init_cmds;
4510 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4511
4512 cmdptr = &mrioc->cfg_cmds;
4513 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4514
4515 cmdptr = &mrioc->bsg_cmds;
4516 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4517 cmdptr = &mrioc->host_tm_cmds;
4518 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4519
4520 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) {
4521 cmdptr = &mrioc->dev_rmhs_cmds[i];
4522 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4523 }
4524
4525 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) {
4526 cmdptr = &mrioc->evtack_cmds[i];
4527 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4528 }
4529
4530 cmdptr = &mrioc->pel_cmds;
4531 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4532
4533 cmdptr = &mrioc->pel_abort_cmd;
4534 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4535
4536 cmdptr = &mrioc->transport_cmds;
4537 mpi3mr_drv_cmd_comp_reset(mrioc, cmdptr);
4538}
4539
4540/**
4541 * mpi3mr_pel_wait_post - Issue PEL Wait
4542 * @mrioc: Adapter instance reference
4543 * @drv_cmd: Internal command tracker
4544 *
4545 * Issue PEL Wait MPI request through admin queue and return.
4546 *
4547 * Return: Nothing.
4548 */
4549static void mpi3mr_pel_wait_post(struct mpi3mr_ioc *mrioc,
4550 struct mpi3mr_drv_cmd *drv_cmd)
4551{
4552 struct mpi3_pel_req_action_wait pel_wait;
4553
4554 mrioc->pel_abort_requested = false;
4555
4556 memset(&pel_wait, 0, sizeof(pel_wait));
4557 drv_cmd->state = MPI3MR_CMD_PENDING;
4558 drv_cmd->is_waiting = 0;
4559 drv_cmd->callback = mpi3mr_pel_wait_complete;
4560 drv_cmd->ioc_status = 0;
4561 drv_cmd->ioc_loginfo = 0;
4562 pel_wait.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4563 pel_wait.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4564 pel_wait.action = MPI3_PEL_ACTION_WAIT;
4565 pel_wait.starting_sequence_number = cpu_to_le32(mrioc->pel_newest_seqnum);
4566 pel_wait.locale = cpu_to_le16(mrioc->pel_locale);
4567 pel_wait.class = cpu_to_le16(mrioc->pel_class);
4568 pel_wait.wait_time = MPI3_PEL_WAITTIME_INFINITE_WAIT;
4569 dprint_bsg_info(mrioc, "sending pel_wait seqnum(%d), class(%d), locale(0x%08x)\n",
4570 mrioc->pel_newest_seqnum, mrioc->pel_class, mrioc->pel_locale);
4571
4572 if (mpi3mr_admin_request_post(mrioc, &pel_wait, sizeof(pel_wait), 0)) {
4573 dprint_bsg_err(mrioc,
4574 "Issuing PELWait: Admin post failed\n");
4575 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4576 drv_cmd->callback = NULL;
4577 drv_cmd->retry_count = 0;
4578 mrioc->pel_enabled = false;
4579 }
4580}
4581
4582/**
4583 * mpi3mr_pel_get_seqnum_post - Issue PEL Get Sequence number
4584 * @mrioc: Adapter instance reference
4585 * @drv_cmd: Internal command tracker
4586 *
4587 * Issue PEL get sequence number MPI request through admin queue
4588 * and return.
4589 *
4590 * Return: 0 on success, non-zero on failure.
4591 */
4592int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
4593 struct mpi3mr_drv_cmd *drv_cmd)
4594{
4595 struct mpi3_pel_req_action_get_sequence_numbers pel_getseq_req;
4596 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
4597 int retval = 0;
4598
4599 memset(&pel_getseq_req, 0, sizeof(pel_getseq_req));
4600 mrioc->pel_cmds.state = MPI3MR_CMD_PENDING;
4601 mrioc->pel_cmds.is_waiting = 0;
4602 mrioc->pel_cmds.ioc_status = 0;
4603 mrioc->pel_cmds.ioc_loginfo = 0;
4604 mrioc->pel_cmds.callback = mpi3mr_pel_get_seqnum_complete;
4605 pel_getseq_req.host_tag = cpu_to_le16(MPI3MR_HOSTTAG_PEL_WAIT);
4606 pel_getseq_req.function = MPI3_FUNCTION_PERSISTENT_EVENT_LOG;
4607 pel_getseq_req.action = MPI3_PEL_ACTION_GET_SEQNUM;
4608 mpi3mr_add_sg_single(&pel_getseq_req.sgl, sgl_flags,
4609 mrioc->pel_seqnum_sz, mrioc->pel_seqnum_dma);
4610
4611 retval = mpi3mr_admin_request_post(mrioc, &pel_getseq_req,
4612 sizeof(pel_getseq_req), 0);
4613 if (retval) {
4614 if (drv_cmd) {
4615 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4616 drv_cmd->callback = NULL;
4617 drv_cmd->retry_count = 0;
4618 }
4619 mrioc->pel_enabled = false;
4620 }
4621
4622 return retval;
4623}
4624
4625/**
4626 * mpi3mr_pel_wait_complete - PELWait Completion callback
4627 * @mrioc: Adapter instance reference
4628 * @drv_cmd: Internal command tracker
4629 *
4630 * This is a callback handler for the PELWait request and
4631 * firmware completes a PELWait request when it is aborted or a
4632 * new PEL entry is available. This sends AEN to the application
4633 * and if the PELwait completion is not due to PELAbort then
4634 * this will send a request for new PEL Sequence number
4635 *
4636 * Return: Nothing.
4637 */
4638static void mpi3mr_pel_wait_complete(struct mpi3mr_ioc *mrioc,
4639 struct mpi3mr_drv_cmd *drv_cmd)
4640{
4641 struct mpi3_pel_reply *pel_reply = NULL;
4642 u16 ioc_status, pe_log_status;
4643 bool do_retry = false;
4644
4645 if (drv_cmd->state & MPI3MR_CMD_RESET)
4646 goto cleanup_drv_cmd;
4647
4648 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4649 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4650 ioc_err(mrioc, "%s: Failed ioc_status(0x%04x) Loginfo(0x%08x)\n",
4651 __func__, ioc_status, drv_cmd->ioc_loginfo);
4652 dprint_bsg_err(mrioc,
4653 "pel_wait: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4654 ioc_status, drv_cmd->ioc_loginfo);
4655 do_retry = true;
4656 }
4657
4658 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4659 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4660
4661 if (!pel_reply) {
4662 dprint_bsg_err(mrioc,
4663 "pel_wait: failed due to no reply\n");
4664 goto out_failed;
4665 }
4666
4667 pe_log_status = le16_to_cpu(pel_reply->pe_log_status);
4668 if ((pe_log_status != MPI3_PEL_STATUS_SUCCESS) &&
4669 (pe_log_status != MPI3_PEL_STATUS_ABORTED)) {
4670 ioc_err(mrioc, "%s: Failed pe_log_status(0x%04x)\n",
4671 __func__, pe_log_status);
4672 dprint_bsg_err(mrioc,
4673 "pel_wait: failed due to pel_log_status(0x%04x)\n",
4674 pe_log_status);
4675 do_retry = true;
4676 }
4677
4678 if (do_retry) {
4679 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4680 drv_cmd->retry_count++;
4681 dprint_bsg_err(mrioc, "pel_wait: retrying(%d)\n",
4682 drv_cmd->retry_count);
4683 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4684 return;
4685 }
4686 dprint_bsg_err(mrioc,
4687 "pel_wait: failed after all retries(%d)\n",
4688 drv_cmd->retry_count);
4689 goto out_failed;
4690 }
4691 atomic64_inc(&event_counter);
4692 if (!mrioc->pel_abort_requested) {
4693 mrioc->pel_cmds.retry_count = 0;
4694 mpi3mr_pel_get_seqnum_post(mrioc, &mrioc->pel_cmds);
4695 }
4696
4697 return;
4698out_failed:
4699 mrioc->pel_enabled = false;
4700cleanup_drv_cmd:
4701 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4702 drv_cmd->callback = NULL;
4703 drv_cmd->retry_count = 0;
4704}
4705
4706/**
4707 * mpi3mr_pel_get_seqnum_complete - PELGetSeqNum Completion callback
4708 * @mrioc: Adapter instance reference
4709 * @drv_cmd: Internal command tracker
4710 *
4711 * This is a callback handler for the PEL get sequence number
4712 * request and a new PEL wait request will be issued to the
4713 * firmware from this
4714 *
4715 * Return: Nothing.
4716 */
4717void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
4718 struct mpi3mr_drv_cmd *drv_cmd)
4719{
4720 struct mpi3_pel_reply *pel_reply = NULL;
4721 struct mpi3_pel_seq *pel_seqnum_virt;
4722 u16 ioc_status;
4723 bool do_retry = false;
4724
4725 pel_seqnum_virt = (struct mpi3_pel_seq *)mrioc->pel_seqnum_virt;
4726
4727 if (drv_cmd->state & MPI3MR_CMD_RESET)
4728 goto cleanup_drv_cmd;
4729
4730 ioc_status = drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
4731 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
4732 dprint_bsg_err(mrioc,
4733 "pel_get_seqnum: failed with ioc_status(0x%04x), log_info(0x%08x)\n",
4734 ioc_status, drv_cmd->ioc_loginfo);
4735 do_retry = true;
4736 }
4737
4738 if (drv_cmd->state & MPI3MR_CMD_REPLY_VALID)
4739 pel_reply = (struct mpi3_pel_reply *)drv_cmd->reply;
4740 if (!pel_reply) {
4741 dprint_bsg_err(mrioc,
4742 "pel_get_seqnum: failed due to no reply\n");
4743 goto out_failed;
4744 }
4745
4746 if (le16_to_cpu(pel_reply->pe_log_status) != MPI3_PEL_STATUS_SUCCESS) {
4747 dprint_bsg_err(mrioc,
4748 "pel_get_seqnum: failed due to pel_log_status(0x%04x)\n",
4749 le16_to_cpu(pel_reply->pe_log_status));
4750 do_retry = true;
4751 }
4752
4753 if (do_retry) {
4754 if (drv_cmd->retry_count < MPI3MR_PEL_RETRY_COUNT) {
4755 drv_cmd->retry_count++;
4756 dprint_bsg_err(mrioc,
4757 "pel_get_seqnum: retrying(%d)\n",
4758 drv_cmd->retry_count);
4759 mpi3mr_pel_get_seqnum_post(mrioc, drv_cmd);
4760 return;
4761 }
4762
4763 dprint_bsg_err(mrioc,
4764 "pel_get_seqnum: failed after all retries(%d)\n",
4765 drv_cmd->retry_count);
4766 goto out_failed;
4767 }
4768 mrioc->pel_newest_seqnum = le32_to_cpu(pel_seqnum_virt->newest) + 1;
4769 drv_cmd->retry_count = 0;
4770 mpi3mr_pel_wait_post(mrioc, drv_cmd);
4771
4772 return;
4773out_failed:
4774 mrioc->pel_enabled = false;
4775cleanup_drv_cmd:
4776 drv_cmd->state = MPI3MR_CMD_NOTUSED;
4777 drv_cmd->callback = NULL;
4778 drv_cmd->retry_count = 0;
4779}
4780
4781/**
4782 * mpi3mr_soft_reset_handler - Reset the controller
4783 * @mrioc: Adapter instance reference
4784 * @reset_reason: Reset reason code
4785 * @snapdump: Flag to generate snapdump in firmware or not
4786 *
4787 * This is an handler for recovering controller by issuing soft
4788 * reset are diag fault reset. This is a blocking function and
4789 * when one reset is executed if any other resets they will be
4790 * blocked. All BSG requests will be blocked during the reset. If
4791 * controller reset is successful then the controller will be
4792 * reinitalized, otherwise the controller will be marked as not
4793 * recoverable
4794 *
4795 * In snapdump bit is set, the controller is issued with diag
4796 * fault reset so that the firmware can create a snap dump and
4797 * post that the firmware will result in F000 fault and the
4798 * driver will issue soft reset to recover from that.
4799 *
4800 * Return: 0 on success, non-zero on failure.
4801 */
4802int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
4803 u32 reset_reason, u8 snapdump)
4804{
4805 int retval = 0, i;
4806 unsigned long flags;
4807 u32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10;
4808
4809 /* Block the reset handler until diag save in progress*/
4810 dprint_reset(mrioc,
4811 "soft_reset_handler: check and block on diagsave_timeout(%d)\n",
4812 mrioc->diagsave_timeout);
4813 while (mrioc->diagsave_timeout)
4814 ssleep(1);
4815 /*
4816 * Block new resets until the currently executing one is finished and
4817 * return the status of the existing reset for all blocked resets
4818 */
4819 dprint_reset(mrioc, "soft_reset_handler: acquiring reset_mutex\n");
4820 if (!mutex_trylock(&mrioc->reset_mutex)) {
4821 ioc_info(mrioc,
4822 "controller reset triggered by %s is blocked due to another reset in progress\n",
4823 mpi3mr_reset_rc_name(reset_reason));
4824 do {
4825 ssleep(1);
4826 } while (mrioc->reset_in_progress == 1);
4827 ioc_info(mrioc,
4828 "returning previous reset result(%d) for the reset triggered by %s\n",
4829 mrioc->prev_reset_result,
4830 mpi3mr_reset_rc_name(reset_reason));
4831 return mrioc->prev_reset_result;
4832 }
4833 ioc_info(mrioc, "controller reset is triggered by %s\n",
4834 mpi3mr_reset_rc_name(reset_reason));
4835
4836 mrioc->device_refresh_on = 0;
4837 mrioc->reset_in_progress = 1;
4838 mrioc->stop_bsgs = 1;
4839 mrioc->prev_reset_result = -1;
4840
4841 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) &&
4842 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) &&
4843 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) {
4844 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
4845 mrioc->event_masks[i] = -1;
4846
4847 dprint_reset(mrioc, "soft_reset_handler: masking events\n");
4848 mpi3mr_issue_event_notification(mrioc);
4849 }
4850
4851 mpi3mr_wait_for_host_io(mrioc, MPI3MR_RESET_HOST_IOWAIT_TIMEOUT);
4852
4853 mpi3mr_ioc_disable_intr(mrioc);
4854
4855 if (snapdump) {
4856 mpi3mr_set_diagsave(mrioc);
4857 retval = mpi3mr_issue_reset(mrioc,
4858 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4859 if (!retval) {
4860 do {
4861 host_diagnostic =
4862 readl(&mrioc->sysif_regs->host_diagnostic);
4863 if (!(host_diagnostic &
4864 MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS))
4865 break;
4866 msleep(100);
4867 } while (--timeout);
4868 }
4869 }
4870
4871 retval = mpi3mr_issue_reset(mrioc,
4872 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason);
4873 if (retval) {
4874 ioc_err(mrioc, "Failed to issue soft reset to the ioc\n");
4875 goto out;
4876 }
4877 if (mrioc->num_io_throttle_group !=
4878 mrioc->facts.max_io_throttle_group) {
4879 ioc_err(mrioc,
4880 "max io throttle group doesn't match old(%d), new(%d)\n",
4881 mrioc->num_io_throttle_group,
4882 mrioc->facts.max_io_throttle_group);
4883 retval = -EPERM;
4884 goto out;
4885 }
4886
4887 mpi3mr_flush_delayed_cmd_lists(mrioc);
4888 mpi3mr_flush_drv_cmds(mrioc);
4889 memset(mrioc->devrem_bitmap, 0, mrioc->devrem_bitmap_sz);
4890 memset(mrioc->removepend_bitmap, 0, mrioc->dev_handle_bitmap_sz);
4891 memset(mrioc->evtack_cmds_bitmap, 0, mrioc->evtack_cmds_bitmap_sz);
4892 mpi3mr_flush_host_io(mrioc);
4893 mpi3mr_cleanup_fwevt_list(mrioc);
4894 mpi3mr_invalidate_devhandles(mrioc);
4895 mpi3mr_free_enclosure_list(mrioc);
4896
4897 if (mrioc->prepare_for_reset) {
4898 mrioc->prepare_for_reset = 0;
4899 mrioc->prepare_for_reset_timeout_counter = 0;
4900 }
4901 mpi3mr_memset_buffers(mrioc);
4902 retval = mpi3mr_reinit_ioc(mrioc, 0);
4903 if (retval) {
4904 pr_err(IOCNAME "reinit after soft reset failed: reason %d\n",
4905 mrioc->name, reset_reason);
4906 goto out;
4907 }
4908 ssleep(MPI3MR_RESET_TOPOLOGY_SETTLE_TIME);
4909
4910out:
4911 if (!retval) {
4912 mrioc->diagsave_timeout = 0;
4913 mrioc->reset_in_progress = 0;
4914 mrioc->pel_abort_requested = 0;
4915 if (mrioc->pel_enabled) {
4916 mrioc->pel_cmds.retry_count = 0;
4917 mpi3mr_pel_wait_post(mrioc, &mrioc->pel_cmds);
4918 }
4919
4920 mrioc->device_refresh_on = 0;
4921
4922 mrioc->ts_update_counter = 0;
4923 spin_lock_irqsave(&mrioc->watchdog_lock, flags);
4924 if (mrioc->watchdog_work_q)
4925 queue_delayed_work(mrioc->watchdog_work_q,
4926 &mrioc->watchdog_work,
4927 msecs_to_jiffies(MPI3MR_WATCHDOG_INTERVAL));
4928 spin_unlock_irqrestore(&mrioc->watchdog_lock, flags);
4929 mrioc->stop_bsgs = 0;
4930 if (mrioc->pel_enabled)
4931 atomic64_inc(&event_counter);
4932 } else {
4933 mpi3mr_issue_reset(mrioc,
4934 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason);
4935 mrioc->device_refresh_on = 0;
4936 mrioc->unrecoverable = 1;
4937 mrioc->reset_in_progress = 0;
4938 retval = -1;
4939 mpi3mr_flush_cmds_for_unrecovered_controller(mrioc);
4940 }
4941 mrioc->prev_reset_result = retval;
4942 mutex_unlock(&mrioc->reset_mutex);
4943 ioc_info(mrioc, "controller reset is %s\n",
4944 ((retval == 0) ? "successful" : "failed"));
4945 return retval;
4946}
4947
4948
4949/**
4950 * mpi3mr_free_config_dma_memory - free memory for config page
4951 * @mrioc: Adapter instance reference
4952 * @mem_desc: memory descriptor structure
4953 *
4954 * Check whether the size of the buffer specified by the memory
4955 * descriptor is greater than the default page size if so then
4956 * free the memory pointed by the descriptor.
4957 *
4958 * Return: Nothing.
4959 */
4960static void mpi3mr_free_config_dma_memory(struct mpi3mr_ioc *mrioc,
4961 struct dma_memory_desc *mem_desc)
4962{
4963 if ((mem_desc->size > mrioc->cfg_page_sz) && mem_desc->addr) {
4964 dma_free_coherent(&mrioc->pdev->dev, mem_desc->size,
4965 mem_desc->addr, mem_desc->dma_addr);
4966 mem_desc->addr = NULL;
4967 }
4968}
4969
4970/**
4971 * mpi3mr_alloc_config_dma_memory - Alloc memory for config page
4972 * @mrioc: Adapter instance reference
4973 * @mem_desc: Memory descriptor to hold dma memory info
4974 *
4975 * This function allocates new dmaable memory or provides the
4976 * default config page dmaable memory based on the memory size
4977 * described by the descriptor.
4978 *
4979 * Return: 0 on success, non-zero on failure.
4980 */
4981static int mpi3mr_alloc_config_dma_memory(struct mpi3mr_ioc *mrioc,
4982 struct dma_memory_desc *mem_desc)
4983{
4984 if (mem_desc->size > mrioc->cfg_page_sz) {
4985 mem_desc->addr = dma_alloc_coherent(&mrioc->pdev->dev,
4986 mem_desc->size, &mem_desc->dma_addr, GFP_KERNEL);
4987 if (!mem_desc->addr)
4988 return -ENOMEM;
4989 } else {
4990 mem_desc->addr = mrioc->cfg_page;
4991 mem_desc->dma_addr = mrioc->cfg_page_dma;
4992 memset(mem_desc->addr, 0, mrioc->cfg_page_sz);
4993 }
4994 return 0;
4995}
4996
4997/**
4998 * mpi3mr_post_cfg_req - Issue config requests and wait
4999 * @mrioc: Adapter instance reference
5000 * @cfg_req: Configuration request
5001 * @timeout: Timeout in seconds
5002 * @ioc_status: Pointer to return ioc status
5003 *
5004 * A generic function for posting MPI3 configuration request to
5005 * the firmware. This blocks for the completion of request for
5006 * timeout seconds and if the request times out this function
5007 * faults the controller with proper reason code.
5008 *
5009 * On successful completion of the request this function returns
5010 * appropriate ioc status from the firmware back to the caller.
5011 *
5012 * Return: 0 on success, non-zero on failure.
5013 */
5014static int mpi3mr_post_cfg_req(struct mpi3mr_ioc *mrioc,
5015 struct mpi3_config_request *cfg_req, int timeout, u16 *ioc_status)
5016{
5017 int retval = 0;
5018
5019 mutex_lock(&mrioc->cfg_cmds.mutex);
5020 if (mrioc->cfg_cmds.state & MPI3MR_CMD_PENDING) {
5021 retval = -1;
5022 ioc_err(mrioc, "sending config request failed due to command in use\n");
5023 mutex_unlock(&mrioc->cfg_cmds.mutex);
5024 goto out;
5025 }
5026 mrioc->cfg_cmds.state = MPI3MR_CMD_PENDING;
5027 mrioc->cfg_cmds.is_waiting = 1;
5028 mrioc->cfg_cmds.callback = NULL;
5029 mrioc->cfg_cmds.ioc_status = 0;
5030 mrioc->cfg_cmds.ioc_loginfo = 0;
5031
5032 cfg_req->host_tag = cpu_to_le16(MPI3MR_HOSTTAG_CFG_CMDS);
5033 cfg_req->function = MPI3_FUNCTION_CONFIG;
5034
5035 init_completion(&mrioc->cfg_cmds.done);
5036 dprint_cfg_info(mrioc, "posting config request\n");
5037 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5038 dprint_dump(cfg_req, sizeof(struct mpi3_config_request),
5039 "mpi3_cfg_req");
5040 retval = mpi3mr_admin_request_post(mrioc, cfg_req, sizeof(*cfg_req), 1);
5041 if (retval) {
5042 ioc_err(mrioc, "posting config request failed\n");
5043 goto out_unlock;
5044 }
5045 wait_for_completion_timeout(&mrioc->cfg_cmds.done, (timeout * HZ));
5046 if (!(mrioc->cfg_cmds.state & MPI3MR_CMD_COMPLETE)) {
5047 mpi3mr_check_rh_fault_ioc(mrioc,
5048 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT);
5049 ioc_err(mrioc, "config request timed out\n");
5050 retval = -1;
5051 goto out_unlock;
5052 }
5053 *ioc_status = mrioc->cfg_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK;
5054 if ((*ioc_status) != MPI3_IOCSTATUS_SUCCESS)
5055 dprint_cfg_err(mrioc,
5056 "cfg_page request returned with ioc_status(0x%04x), log_info(0x%08x)\n",
5057 *ioc_status, mrioc->cfg_cmds.ioc_loginfo);
5058
5059out_unlock:
5060 mrioc->cfg_cmds.state = MPI3MR_CMD_NOTUSED;
5061 mutex_unlock(&mrioc->cfg_cmds.mutex);
5062
5063out:
5064 return retval;
5065}
5066
5067/**
5068 * mpi3mr_process_cfg_req - config page request processor
5069 * @mrioc: Adapter instance reference
5070 * @cfg_req: Configuration request
5071 * @cfg_hdr: Configuration page header
5072 * @timeout: Timeout in seconds
5073 * @ioc_status: Pointer to return ioc status
5074 * @cfg_buf: Memory pointer to copy config page or header
5075 * @cfg_buf_sz: Size of the memory to get config page or header
5076 *
5077 * This is handler for config page read, write and config page
5078 * header read operations.
5079 *
5080 * This function expects the cfg_req to be populated with page
5081 * type, page number, action for the header read and with page
5082 * address for all other operations.
5083 *
5084 * The cfg_hdr can be passed as null for reading required header
5085 * details for read/write pages the cfg_hdr should point valid
5086 * configuration page header.
5087 *
5088 * This allocates dmaable memory based on the size of the config
5089 * buffer and set the SGE of the cfg_req.
5090 *
5091 * For write actions, the config page data has to be passed in
5092 * the cfg_buf and size of the data has to be mentioned in the
5093 * cfg_buf_sz.
5094 *
5095 * For read/header actions, on successful completion of the
5096 * request with successful ioc_status the data will be copied
5097 * into the cfg_buf limited to a minimum of actual page size and
5098 * cfg_buf_sz
5099 *
5100 *
5101 * Return: 0 on success, non-zero on failure.
5102 */
5103static int mpi3mr_process_cfg_req(struct mpi3mr_ioc *mrioc,
5104 struct mpi3_config_request *cfg_req,
5105 struct mpi3_config_page_header *cfg_hdr, int timeout, u16 *ioc_status,
5106 void *cfg_buf, u32 cfg_buf_sz)
5107{
5108 struct dma_memory_desc mem_desc;
5109 int retval = -1;
5110 u8 invalid_action = 0;
5111 u8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST;
5112
5113 memset(&mem_desc, 0, sizeof(struct dma_memory_desc));
5114
5115 if (cfg_req->action == MPI3_CONFIG_ACTION_PAGE_HEADER)
5116 mem_desc.size = sizeof(struct mpi3_config_page_header);
5117 else {
5118 if (!cfg_hdr) {
5119 ioc_err(mrioc, "null config header passed for config action(%d), page_type(0x%02x), page_num(%d)\n",
5120 cfg_req->action, cfg_req->page_type,
5121 cfg_req->page_number);
5122 goto out;
5123 }
5124 switch (cfg_hdr->page_attribute & MPI3_CONFIG_PAGEATTR_MASK) {
5125 case MPI3_CONFIG_PAGEATTR_READ_ONLY:
5126 if (cfg_req->action
5127 != MPI3_CONFIG_ACTION_READ_CURRENT)
5128 invalid_action = 1;
5129 break;
5130 case MPI3_CONFIG_PAGEATTR_CHANGEABLE:
5131 if ((cfg_req->action ==
5132 MPI3_CONFIG_ACTION_READ_PERSISTENT) ||
5133 (cfg_req->action ==
5134 MPI3_CONFIG_ACTION_WRITE_PERSISTENT))
5135 invalid_action = 1;
5136 break;
5137 case MPI3_CONFIG_PAGEATTR_PERSISTENT:
5138 default:
5139 break;
5140 }
5141 if (invalid_action) {
5142 ioc_err(mrioc,
5143 "config action(%d) is not allowed for page_type(0x%02x), page_num(%d) with page_attribute(0x%02x)\n",
5144 cfg_req->action, cfg_req->page_type,
5145 cfg_req->page_number, cfg_hdr->page_attribute);
5146 goto out;
5147 }
5148 mem_desc.size = le16_to_cpu(cfg_hdr->page_length) * 4;
5149 cfg_req->page_length = cfg_hdr->page_length;
5150 cfg_req->page_version = cfg_hdr->page_version;
5151 }
5152 if (mpi3mr_alloc_config_dma_memory(mrioc, &mem_desc))
5153 goto out;
5154
5155 mpi3mr_add_sg_single(&cfg_req->sgl, sgl_flags, mem_desc.size,
5156 mem_desc.dma_addr);
5157
5158 if ((cfg_req->action == MPI3_CONFIG_ACTION_WRITE_PERSISTENT) ||
5159 (cfg_req->action == MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5160 memcpy(mem_desc.addr, cfg_buf, min_t(u16, mem_desc.size,
5161 cfg_buf_sz));
5162 dprint_cfg_info(mrioc, "config buffer to be written\n");
5163 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5164 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5165 }
5166
5167 if (mpi3mr_post_cfg_req(mrioc, cfg_req, timeout, ioc_status))
5168 goto out;
5169
5170 retval = 0;
5171 if ((*ioc_status == MPI3_IOCSTATUS_SUCCESS) &&
5172 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_PERSISTENT) &&
5173 (cfg_req->action != MPI3_CONFIG_ACTION_WRITE_CURRENT)) {
5174 memcpy(cfg_buf, mem_desc.addr, min_t(u16, mem_desc.size,
5175 cfg_buf_sz));
5176 dprint_cfg_info(mrioc, "config buffer read\n");
5177 if (mrioc->logging_level & MPI3_DEBUG_CFG_INFO)
5178 dprint_dump(mem_desc.addr, mem_desc.size, "cfg_buf");
5179 }
5180
5181out:
5182 mpi3mr_free_config_dma_memory(mrioc, &mem_desc);
5183 return retval;
5184}
5185
5186/**
5187 * mpi3mr_cfg_get_dev_pg0 - Read current device page0
5188 * @mrioc: Adapter instance reference
5189 * @ioc_status: Pointer to return ioc status
5190 * @dev_pg0: Pointer to return device page 0
5191 * @pg_sz: Size of the memory allocated to the page pointer
5192 * @form: The form to be used for addressing the page
5193 * @form_spec: Form specific information like device handle
5194 *
5195 * This is handler for config page read for a specific device
5196 * page0. The ioc_status has the controller returned ioc_status.
5197 * This routine doesn't check ioc_status to decide whether the
5198 * page read is success or not and it is the callers
5199 * responsibility.
5200 *
5201 * Return: 0 on success, non-zero on failure.
5202 */
5203int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5204 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec)
5205{
5206 struct mpi3_config_page_header cfg_hdr;
5207 struct mpi3_config_request cfg_req;
5208 u32 page_address;
5209
5210 memset(dev_pg0, 0, pg_sz);
5211 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5212 memset(&cfg_req, 0, sizeof(cfg_req));
5213
5214 cfg_req.function = MPI3_FUNCTION_CONFIG;
5215 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5216 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DEVICE;
5217 cfg_req.page_number = 0;
5218 cfg_req.page_address = 0;
5219
5220 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5221 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5222 ioc_err(mrioc, "device page0 header read failed\n");
5223 goto out_failed;
5224 }
5225 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5226 ioc_err(mrioc, "device page0 header read failed with ioc_status(0x%04x)\n",
5227 *ioc_status);
5228 goto out_failed;
5229 }
5230 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5231 page_address = ((form & MPI3_DEVICE_PGAD_FORM_MASK) |
5232 (form_spec & MPI3_DEVICE_PGAD_HANDLE_MASK));
5233 cfg_req.page_address = cpu_to_le32(page_address);
5234 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5235 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, dev_pg0, pg_sz)) {
5236 ioc_err(mrioc, "device page0 read failed\n");
5237 goto out_failed;
5238 }
5239 return 0;
5240out_failed:
5241 return -1;
5242}
5243
5244
5245/**
5246 * mpi3mr_cfg_get_sas_phy_pg0 - Read current SAS Phy page0
5247 * @mrioc: Adapter instance reference
5248 * @ioc_status: Pointer to return ioc status
5249 * @phy_pg0: Pointer to return SAS Phy page 0
5250 * @pg_sz: Size of the memory allocated to the page pointer
5251 * @form: The form to be used for addressing the page
5252 * @form_spec: Form specific information like phy number
5253 *
5254 * This is handler for config page read for a specific SAS Phy
5255 * page0. The ioc_status has the controller returned ioc_status.
5256 * This routine doesn't check ioc_status to decide whether the
5257 * page read is success or not and it is the callers
5258 * responsibility.
5259 *
5260 * Return: 0 on success, non-zero on failure.
5261 */
5262int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5263 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
5264 u32 form_spec)
5265{
5266 struct mpi3_config_page_header cfg_hdr;
5267 struct mpi3_config_request cfg_req;
5268 u32 page_address;
5269
5270 memset(phy_pg0, 0, pg_sz);
5271 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5272 memset(&cfg_req, 0, sizeof(cfg_req));
5273
5274 cfg_req.function = MPI3_FUNCTION_CONFIG;
5275 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5276 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5277 cfg_req.page_number = 0;
5278 cfg_req.page_address = 0;
5279
5280 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5281 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5282 ioc_err(mrioc, "sas phy page0 header read failed\n");
5283 goto out_failed;
5284 }
5285 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5286 ioc_err(mrioc, "sas phy page0 header read failed with ioc_status(0x%04x)\n",
5287 *ioc_status);
5288 goto out_failed;
5289 }
5290 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5291 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5292 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5293 cfg_req.page_address = cpu_to_le32(page_address);
5294 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5295 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg0, pg_sz)) {
5296 ioc_err(mrioc, "sas phy page0 read failed\n");
5297 goto out_failed;
5298 }
5299 return 0;
5300out_failed:
5301 return -1;
5302}
5303
5304/**
5305 * mpi3mr_cfg_get_sas_phy_pg1 - Read current SAS Phy page1
5306 * @mrioc: Adapter instance reference
5307 * @ioc_status: Pointer to return ioc status
5308 * @phy_pg1: Pointer to return SAS Phy page 1
5309 * @pg_sz: Size of the memory allocated to the page pointer
5310 * @form: The form to be used for addressing the page
5311 * @form_spec: Form specific information like phy number
5312 *
5313 * This is handler for config page read for a specific SAS Phy
5314 * page1. The ioc_status has the controller returned ioc_status.
5315 * This routine doesn't check ioc_status to decide whether the
5316 * page read is success or not and it is the callers
5317 * responsibility.
5318 *
5319 * Return: 0 on success, non-zero on failure.
5320 */
5321int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5322 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
5323 u32 form_spec)
5324{
5325 struct mpi3_config_page_header cfg_hdr;
5326 struct mpi3_config_request cfg_req;
5327 u32 page_address;
5328
5329 memset(phy_pg1, 0, pg_sz);
5330 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5331 memset(&cfg_req, 0, sizeof(cfg_req));
5332
5333 cfg_req.function = MPI3_FUNCTION_CONFIG;
5334 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5335 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_PHY;
5336 cfg_req.page_number = 1;
5337 cfg_req.page_address = 0;
5338
5339 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5340 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5341 ioc_err(mrioc, "sas phy page1 header read failed\n");
5342 goto out_failed;
5343 }
5344 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5345 ioc_err(mrioc, "sas phy page1 header read failed with ioc_status(0x%04x)\n",
5346 *ioc_status);
5347 goto out_failed;
5348 }
5349 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5350 page_address = ((form & MPI3_SAS_PHY_PGAD_FORM_MASK) |
5351 (form_spec & MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK));
5352 cfg_req.page_address = cpu_to_le32(page_address);
5353 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5354 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, phy_pg1, pg_sz)) {
5355 ioc_err(mrioc, "sas phy page1 read failed\n");
5356 goto out_failed;
5357 }
5358 return 0;
5359out_failed:
5360 return -1;
5361}
5362
5363
5364/**
5365 * mpi3mr_cfg_get_sas_exp_pg0 - Read current SAS Expander page0
5366 * @mrioc: Adapter instance reference
5367 * @ioc_status: Pointer to return ioc status
5368 * @exp_pg0: Pointer to return SAS Expander page 0
5369 * @pg_sz: Size of the memory allocated to the page pointer
5370 * @form: The form to be used for addressing the page
5371 * @form_spec: Form specific information like device handle
5372 *
5373 * This is handler for config page read for a specific SAS
5374 * Expander page0. The ioc_status has the controller returned
5375 * ioc_status. This routine doesn't check ioc_status to decide
5376 * whether the page read is success or not and it is the callers
5377 * responsibility.
5378 *
5379 * Return: 0 on success, non-zero on failure.
5380 */
5381int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5382 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
5383 u32 form_spec)
5384{
5385 struct mpi3_config_page_header cfg_hdr;
5386 struct mpi3_config_request cfg_req;
5387 u32 page_address;
5388
5389 memset(exp_pg0, 0, pg_sz);
5390 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5391 memset(&cfg_req, 0, sizeof(cfg_req));
5392
5393 cfg_req.function = MPI3_FUNCTION_CONFIG;
5394 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5395 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5396 cfg_req.page_number = 0;
5397 cfg_req.page_address = 0;
5398
5399 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5400 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5401 ioc_err(mrioc, "expander page0 header read failed\n");
5402 goto out_failed;
5403 }
5404 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5405 ioc_err(mrioc, "expander page0 header read failed with ioc_status(0x%04x)\n",
5406 *ioc_status);
5407 goto out_failed;
5408 }
5409 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5410 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5411 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5412 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5413 cfg_req.page_address = cpu_to_le32(page_address);
5414 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5415 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg0, pg_sz)) {
5416 ioc_err(mrioc, "expander page0 read failed\n");
5417 goto out_failed;
5418 }
5419 return 0;
5420out_failed:
5421 return -1;
5422}
5423
5424/**
5425 * mpi3mr_cfg_get_sas_exp_pg1 - Read current SAS Expander page1
5426 * @mrioc: Adapter instance reference
5427 * @ioc_status: Pointer to return ioc status
5428 * @exp_pg1: Pointer to return SAS Expander page 1
5429 * @pg_sz: Size of the memory allocated to the page pointer
5430 * @form: The form to be used for addressing the page
5431 * @form_spec: Form specific information like phy number
5432 *
5433 * This is handler for config page read for a specific SAS
5434 * Expander page1. The ioc_status has the controller returned
5435 * ioc_status. This routine doesn't check ioc_status to decide
5436 * whether the page read is success or not and it is the callers
5437 * responsibility.
5438 *
5439 * Return: 0 on success, non-zero on failure.
5440 */
5441int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5442 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
5443 u32 form_spec)
5444{
5445 struct mpi3_config_page_header cfg_hdr;
5446 struct mpi3_config_request cfg_req;
5447 u32 page_address;
5448
5449 memset(exp_pg1, 0, pg_sz);
5450 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5451 memset(&cfg_req, 0, sizeof(cfg_req));
5452
5453 cfg_req.function = MPI3_FUNCTION_CONFIG;
5454 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5455 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_EXPANDER;
5456 cfg_req.page_number = 1;
5457 cfg_req.page_address = 0;
5458
5459 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5460 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5461 ioc_err(mrioc, "expander page1 header read failed\n");
5462 goto out_failed;
5463 }
5464 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5465 ioc_err(mrioc, "expander page1 header read failed with ioc_status(0x%04x)\n",
5466 *ioc_status);
5467 goto out_failed;
5468 }
5469 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5470 page_address = ((form & MPI3_SAS_EXPAND_PGAD_FORM_MASK) |
5471 (form_spec & (MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK |
5472 MPI3_SAS_EXPAND_PGAD_HANDLE_MASK)));
5473 cfg_req.page_address = cpu_to_le32(page_address);
5474 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5475 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, exp_pg1, pg_sz)) {
5476 ioc_err(mrioc, "expander page1 read failed\n");
5477 goto out_failed;
5478 }
5479 return 0;
5480out_failed:
5481 return -1;
5482}
5483
5484/**
5485 * mpi3mr_cfg_get_enclosure_pg0 - Read current Enclosure page0
5486 * @mrioc: Adapter instance reference
5487 * @ioc_status: Pointer to return ioc status
5488 * @encl_pg0: Pointer to return Enclosure page 0
5489 * @pg_sz: Size of the memory allocated to the page pointer
5490 * @form: The form to be used for addressing the page
5491 * @form_spec: Form specific information like device handle
5492 *
5493 * This is handler for config page read for a specific Enclosure
5494 * page0. The ioc_status has the controller returned ioc_status.
5495 * This routine doesn't check ioc_status to decide whether the
5496 * page read is success or not and it is the callers
5497 * responsibility.
5498 *
5499 * Return: 0 on success, non-zero on failure.
5500 */
5501int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
5502 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
5503 u32 form_spec)
5504{
5505 struct mpi3_config_page_header cfg_hdr;
5506 struct mpi3_config_request cfg_req;
5507 u32 page_address;
5508
5509 memset(encl_pg0, 0, pg_sz);
5510 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5511 memset(&cfg_req, 0, sizeof(cfg_req));
5512
5513 cfg_req.function = MPI3_FUNCTION_CONFIG;
5514 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5515 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_ENCLOSURE;
5516 cfg_req.page_number = 0;
5517 cfg_req.page_address = 0;
5518
5519 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5520 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5521 ioc_err(mrioc, "enclosure page0 header read failed\n");
5522 goto out_failed;
5523 }
5524 if (*ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5525 ioc_err(mrioc, "enclosure page0 header read failed with ioc_status(0x%04x)\n",
5526 *ioc_status);
5527 goto out_failed;
5528 }
5529 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5530 page_address = ((form & MPI3_ENCLOS_PGAD_FORM_MASK) |
5531 (form_spec & MPI3_ENCLOS_PGAD_HANDLE_MASK));
5532 cfg_req.page_address = cpu_to_le32(page_address);
5533 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5534 MPI3MR_INTADMCMD_TIMEOUT, ioc_status, encl_pg0, pg_sz)) {
5535 ioc_err(mrioc, "enclosure page0 read failed\n");
5536 goto out_failed;
5537 }
5538 return 0;
5539out_failed:
5540 return -1;
5541}
5542
5543
5544/**
5545 * mpi3mr_cfg_get_sas_io_unit_pg0 - Read current SASIOUnit page0
5546 * @mrioc: Adapter instance reference
5547 * @sas_io_unit_pg0: Pointer to return SAS IO Unit page 0
5548 * @pg_sz: Size of the memory allocated to the page pointer
5549 *
5550 * This is handler for config page read for the SAS IO Unit
5551 * page0. This routine checks ioc_status to decide whether the
5552 * page read is success or not.
5553 *
5554 * Return: 0 on success, non-zero on failure.
5555 */
5556int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
5557 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz)
5558{
5559 struct mpi3_config_page_header cfg_hdr;
5560 struct mpi3_config_request cfg_req;
5561 u16 ioc_status = 0;
5562
5563 memset(sas_io_unit_pg0, 0, pg_sz);
5564 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5565 memset(&cfg_req, 0, sizeof(cfg_req));
5566
5567 cfg_req.function = MPI3_FUNCTION_CONFIG;
5568 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5569 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5570 cfg_req.page_number = 0;
5571 cfg_req.page_address = 0;
5572
5573 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5574 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5575 ioc_err(mrioc, "sas io unit page0 header read failed\n");
5576 goto out_failed;
5577 }
5578 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5579 ioc_err(mrioc, "sas io unit page0 header read failed with ioc_status(0x%04x)\n",
5580 ioc_status);
5581 goto out_failed;
5582 }
5583 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5584
5585 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5586 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg0, pg_sz)) {
5587 ioc_err(mrioc, "sas io unit page0 read failed\n");
5588 goto out_failed;
5589 }
5590 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5591 ioc_err(mrioc, "sas io unit page0 read failed with ioc_status(0x%04x)\n",
5592 ioc_status);
5593 goto out_failed;
5594 }
5595 return 0;
5596out_failed:
5597 return -1;
5598}
5599
5600/**
5601 * mpi3mr_cfg_get_sas_io_unit_pg1 - Read current SASIOUnit page1
5602 * @mrioc: Adapter instance reference
5603 * @sas_io_unit_pg1: Pointer to return SAS IO Unit page 1
5604 * @pg_sz: Size of the memory allocated to the page pointer
5605 *
5606 * This is handler for config page read for the SAS IO Unit
5607 * page1. This routine checks ioc_status to decide whether the
5608 * page read is success or not.
5609 *
5610 * Return: 0 on success, non-zero on failure.
5611 */
5612int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5613 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5614{
5615 struct mpi3_config_page_header cfg_hdr;
5616 struct mpi3_config_request cfg_req;
5617 u16 ioc_status = 0;
5618
5619 memset(sas_io_unit_pg1, 0, pg_sz);
5620 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5621 memset(&cfg_req, 0, sizeof(cfg_req));
5622
5623 cfg_req.function = MPI3_FUNCTION_CONFIG;
5624 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5625 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5626 cfg_req.page_number = 1;
5627 cfg_req.page_address = 0;
5628
5629 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5630 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5631 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5632 goto out_failed;
5633 }
5634 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5635 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5636 ioc_status);
5637 goto out_failed;
5638 }
5639 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5640
5641 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5642 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5643 ioc_err(mrioc, "sas io unit page1 read failed\n");
5644 goto out_failed;
5645 }
5646 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5647 ioc_err(mrioc, "sas io unit page1 read failed with ioc_status(0x%04x)\n",
5648 ioc_status);
5649 goto out_failed;
5650 }
5651 return 0;
5652out_failed:
5653 return -1;
5654}
5655
5656/**
5657 * mpi3mr_cfg_set_sas_io_unit_pg1 - Write SASIOUnit page1
5658 * @mrioc: Adapter instance reference
5659 * @sas_io_unit_pg1: Pointer to the SAS IO Unit page 1 to write
5660 * @pg_sz: Size of the memory allocated to the page pointer
5661 *
5662 * This is handler for config page write for the SAS IO Unit
5663 * page1. This routine checks ioc_status to decide whether the
5664 * page read is success or not. This will modify both current
5665 * and persistent page.
5666 *
5667 * Return: 0 on success, non-zero on failure.
5668 */
5669int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
5670 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz)
5671{
5672 struct mpi3_config_page_header cfg_hdr;
5673 struct mpi3_config_request cfg_req;
5674 u16 ioc_status = 0;
5675
5676 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5677 memset(&cfg_req, 0, sizeof(cfg_req));
5678
5679 cfg_req.function = MPI3_FUNCTION_CONFIG;
5680 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5681 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT;
5682 cfg_req.page_number = 1;
5683 cfg_req.page_address = 0;
5684
5685 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5686 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5687 ioc_err(mrioc, "sas io unit page1 header read failed\n");
5688 goto out_failed;
5689 }
5690 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5691 ioc_err(mrioc, "sas io unit page1 header read failed with ioc_status(0x%04x)\n",
5692 ioc_status);
5693 goto out_failed;
5694 }
5695 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_CURRENT;
5696
5697 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5698 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5699 ioc_err(mrioc, "sas io unit page1 write current failed\n");
5700 goto out_failed;
5701 }
5702 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5703 ioc_err(mrioc, "sas io unit page1 write current failed with ioc_status(0x%04x)\n",
5704 ioc_status);
5705 goto out_failed;
5706 }
5707
5708 cfg_req.action = MPI3_CONFIG_ACTION_WRITE_PERSISTENT;
5709
5710 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5711 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, sas_io_unit_pg1, pg_sz)) {
5712 ioc_err(mrioc, "sas io unit page1 write persistent failed\n");
5713 goto out_failed;
5714 }
5715 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5716 ioc_err(mrioc, "sas io unit page1 write persistent failed with ioc_status(0x%04x)\n",
5717 ioc_status);
5718 goto out_failed;
5719 }
5720 return 0;
5721out_failed:
5722 return -1;
5723}
5724
5725/**
5726 * mpi3mr_cfg_get_driver_pg1 - Read current Driver page1
5727 * @mrioc: Adapter instance reference
5728 * @driver_pg1: Pointer to return Driver page 1
5729 * @pg_sz: Size of the memory allocated to the page pointer
5730 *
5731 * This is handler for config page read for the Driver page1.
5732 * This routine checks ioc_status to decide whether the page
5733 * read is success or not.
5734 *
5735 * Return: 0 on success, non-zero on failure.
5736 */
5737int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
5738 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz)
5739{
5740 struct mpi3_config_page_header cfg_hdr;
5741 struct mpi3_config_request cfg_req;
5742 u16 ioc_status = 0;
5743
5744 memset(driver_pg1, 0, pg_sz);
5745 memset(&cfg_hdr, 0, sizeof(cfg_hdr));
5746 memset(&cfg_req, 0, sizeof(cfg_req));
5747
5748 cfg_req.function = MPI3_FUNCTION_CONFIG;
5749 cfg_req.action = MPI3_CONFIG_ACTION_PAGE_HEADER;
5750 cfg_req.page_type = MPI3_CONFIG_PAGETYPE_DRIVER;
5751 cfg_req.page_number = 1;
5752 cfg_req.page_address = 0;
5753
5754 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, NULL,
5755 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, &cfg_hdr, sizeof(cfg_hdr))) {
5756 ioc_err(mrioc, "driver page1 header read failed\n");
5757 goto out_failed;
5758 }
5759 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5760 ioc_err(mrioc, "driver page1 header read failed with ioc_status(0x%04x)\n",
5761 ioc_status);
5762 goto out_failed;
5763 }
5764 cfg_req.action = MPI3_CONFIG_ACTION_READ_CURRENT;
5765
5766 if (mpi3mr_process_cfg_req(mrioc, &cfg_req, &cfg_hdr,
5767 MPI3MR_INTADMCMD_TIMEOUT, &ioc_status, driver_pg1, pg_sz)) {
5768 ioc_err(mrioc, "driver page1 read failed\n");
5769 goto out_failed;
5770 }
5771 if (ioc_status != MPI3_IOCSTATUS_SUCCESS) {
5772 ioc_err(mrioc, "driver page1 read failed with ioc_status(0x%04x)\n",
5773 ioc_status);
5774 goto out_failed;
5775 }
5776 return 0;
5777out_failed:
5778 return -1;
5779}