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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi SoCs pinctrl driver
4 *
5 * Author: <alexandre.belloni@free-electrons.com>
6 * License: Dual MIT/GPL
7 * Copyright (c) 2017 Microsemi Corporation
8 */
9
10#include <linux/gpio/driver.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/mfd/ocelot.h>
14#include <linux/of_device.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <linux/platform_device.h>
18#include <linux/regmap.h>
19#include <linux/reset.h>
20#include <linux/slab.h>
21
22#include <linux/pinctrl/consumer.h>
23#include <linux/pinctrl/pinconf-generic.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinctrl.h>
26#include <linux/pinctrl/pinmux.h>
27
28#include "core.h"
29#include "pinconf.h"
30#include "pinmux.h"
31
32#define ocelot_clrsetbits(addr, clear, set) \
33 writel((readl(addr) & ~(clear)) | (set), (addr))
34
35enum {
36 PINCONF_BIAS,
37 PINCONF_SCHMITT,
38 PINCONF_DRIVE_STRENGTH,
39};
40
41/* GPIO standard registers */
42#define OCELOT_GPIO_OUT_SET 0x0
43#define OCELOT_GPIO_OUT_CLR 0x4
44#define OCELOT_GPIO_OUT 0x8
45#define OCELOT_GPIO_IN 0xc
46#define OCELOT_GPIO_OE 0x10
47#define OCELOT_GPIO_INTR 0x14
48#define OCELOT_GPIO_INTR_ENA 0x18
49#define OCELOT_GPIO_INTR_IDENT 0x1c
50#define OCELOT_GPIO_ALT0 0x20
51#define OCELOT_GPIO_ALT1 0x24
52#define OCELOT_GPIO_SD_MAP 0x28
53
54#define OCELOT_FUNC_PER_PIN 4
55
56enum {
57 FUNC_CAN0_a,
58 FUNC_CAN0_b,
59 FUNC_CAN1,
60 FUNC_CLKMON,
61 FUNC_NONE,
62 FUNC_FC0_a,
63 FUNC_FC0_b,
64 FUNC_FC0_c,
65 FUNC_FC1_a,
66 FUNC_FC1_b,
67 FUNC_FC1_c,
68 FUNC_FC2_a,
69 FUNC_FC2_b,
70 FUNC_FC3_a,
71 FUNC_FC3_b,
72 FUNC_FC3_c,
73 FUNC_FC4_a,
74 FUNC_FC4_b,
75 FUNC_FC4_c,
76 FUNC_FC_SHRD0,
77 FUNC_FC_SHRD1,
78 FUNC_FC_SHRD2,
79 FUNC_FC_SHRD3,
80 FUNC_FC_SHRD4,
81 FUNC_FC_SHRD5,
82 FUNC_FC_SHRD6,
83 FUNC_FC_SHRD7,
84 FUNC_FC_SHRD8,
85 FUNC_FC_SHRD9,
86 FUNC_FC_SHRD10,
87 FUNC_FC_SHRD11,
88 FUNC_FC_SHRD12,
89 FUNC_FC_SHRD13,
90 FUNC_FC_SHRD14,
91 FUNC_FC_SHRD15,
92 FUNC_FC_SHRD16,
93 FUNC_FC_SHRD17,
94 FUNC_FC_SHRD18,
95 FUNC_FC_SHRD19,
96 FUNC_FC_SHRD20,
97 FUNC_GPIO,
98 FUNC_IB_TRG_a,
99 FUNC_IB_TRG_b,
100 FUNC_IB_TRG_c,
101 FUNC_IRQ0,
102 FUNC_IRQ_IN_a,
103 FUNC_IRQ_IN_b,
104 FUNC_IRQ_IN_c,
105 FUNC_IRQ0_IN,
106 FUNC_IRQ_OUT_a,
107 FUNC_IRQ_OUT_b,
108 FUNC_IRQ_OUT_c,
109 FUNC_IRQ0_OUT,
110 FUNC_IRQ1,
111 FUNC_IRQ1_IN,
112 FUNC_IRQ1_OUT,
113 FUNC_EXT_IRQ,
114 FUNC_MIIM,
115 FUNC_MIIM_a,
116 FUNC_MIIM_b,
117 FUNC_MIIM_c,
118 FUNC_MIIM_Sa,
119 FUNC_MIIM_Sb,
120 FUNC_OB_TRG,
121 FUNC_OB_TRG_a,
122 FUNC_OB_TRG_b,
123 FUNC_PHY_LED,
124 FUNC_PCI_WAKE,
125 FUNC_MD,
126 FUNC_PTP0,
127 FUNC_PTP1,
128 FUNC_PTP2,
129 FUNC_PTP3,
130 FUNC_PTPSYNC_0,
131 FUNC_PTPSYNC_1,
132 FUNC_PTPSYNC_2,
133 FUNC_PTPSYNC_3,
134 FUNC_PTPSYNC_4,
135 FUNC_PTPSYNC_5,
136 FUNC_PTPSYNC_6,
137 FUNC_PTPSYNC_7,
138 FUNC_PWM,
139 FUNC_PWM_a,
140 FUNC_PWM_b,
141 FUNC_QSPI1,
142 FUNC_QSPI2,
143 FUNC_R,
144 FUNC_RECO_a,
145 FUNC_RECO_b,
146 FUNC_RECO_CLK,
147 FUNC_SD,
148 FUNC_SFP,
149 FUNC_SFP_SD,
150 FUNC_SG0,
151 FUNC_SG1,
152 FUNC_SG2,
153 FUNC_SGPIO_a,
154 FUNC_SGPIO_b,
155 FUNC_SI,
156 FUNC_SI2,
157 FUNC_TACHO,
158 FUNC_TACHO_a,
159 FUNC_TACHO_b,
160 FUNC_TWI,
161 FUNC_TWI2,
162 FUNC_TWI3,
163 FUNC_TWI_SCL_M,
164 FUNC_TWI_SLC_GATE,
165 FUNC_TWI_SLC_GATE_AD,
166 FUNC_UART,
167 FUNC_UART2,
168 FUNC_UART3,
169 FUNC_USB_H_a,
170 FUNC_USB_H_b,
171 FUNC_USB_H_c,
172 FUNC_USB_S_a,
173 FUNC_USB_S_b,
174 FUNC_USB_S_c,
175 FUNC_PLL_STAT,
176 FUNC_EMMC,
177 FUNC_EMMC_SD,
178 FUNC_REF_CLK,
179 FUNC_RCVRD_CLK,
180 FUNC_MAX
181};
182
183static const char *const ocelot_function_names[] = {
184 [FUNC_CAN0_a] = "can0_a",
185 [FUNC_CAN0_b] = "can0_b",
186 [FUNC_CAN1] = "can1",
187 [FUNC_CLKMON] = "clkmon",
188 [FUNC_NONE] = "none",
189 [FUNC_FC0_a] = "fc0_a",
190 [FUNC_FC0_b] = "fc0_b",
191 [FUNC_FC0_c] = "fc0_c",
192 [FUNC_FC1_a] = "fc1_a",
193 [FUNC_FC1_b] = "fc1_b",
194 [FUNC_FC1_c] = "fc1_c",
195 [FUNC_FC2_a] = "fc2_a",
196 [FUNC_FC2_b] = "fc2_b",
197 [FUNC_FC3_a] = "fc3_a",
198 [FUNC_FC3_b] = "fc3_b",
199 [FUNC_FC3_c] = "fc3_c",
200 [FUNC_FC4_a] = "fc4_a",
201 [FUNC_FC4_b] = "fc4_b",
202 [FUNC_FC4_c] = "fc4_c",
203 [FUNC_FC_SHRD0] = "fc_shrd0",
204 [FUNC_FC_SHRD1] = "fc_shrd1",
205 [FUNC_FC_SHRD2] = "fc_shrd2",
206 [FUNC_FC_SHRD3] = "fc_shrd3",
207 [FUNC_FC_SHRD4] = "fc_shrd4",
208 [FUNC_FC_SHRD5] = "fc_shrd5",
209 [FUNC_FC_SHRD6] = "fc_shrd6",
210 [FUNC_FC_SHRD7] = "fc_shrd7",
211 [FUNC_FC_SHRD8] = "fc_shrd8",
212 [FUNC_FC_SHRD9] = "fc_shrd9",
213 [FUNC_FC_SHRD10] = "fc_shrd10",
214 [FUNC_FC_SHRD11] = "fc_shrd11",
215 [FUNC_FC_SHRD12] = "fc_shrd12",
216 [FUNC_FC_SHRD13] = "fc_shrd13",
217 [FUNC_FC_SHRD14] = "fc_shrd14",
218 [FUNC_FC_SHRD15] = "fc_shrd15",
219 [FUNC_FC_SHRD16] = "fc_shrd16",
220 [FUNC_FC_SHRD17] = "fc_shrd17",
221 [FUNC_FC_SHRD18] = "fc_shrd18",
222 [FUNC_FC_SHRD19] = "fc_shrd19",
223 [FUNC_FC_SHRD20] = "fc_shrd20",
224 [FUNC_GPIO] = "gpio",
225 [FUNC_IB_TRG_a] = "ib_trig_a",
226 [FUNC_IB_TRG_b] = "ib_trig_b",
227 [FUNC_IB_TRG_c] = "ib_trig_c",
228 [FUNC_IRQ0] = "irq0",
229 [FUNC_IRQ_IN_a] = "irq_in_a",
230 [FUNC_IRQ_IN_b] = "irq_in_b",
231 [FUNC_IRQ_IN_c] = "irq_in_c",
232 [FUNC_IRQ0_IN] = "irq0_in",
233 [FUNC_IRQ_OUT_a] = "irq_out_a",
234 [FUNC_IRQ_OUT_b] = "irq_out_b",
235 [FUNC_IRQ_OUT_c] = "irq_out_c",
236 [FUNC_IRQ0_OUT] = "irq0_out",
237 [FUNC_IRQ1] = "irq1",
238 [FUNC_IRQ1_IN] = "irq1_in",
239 [FUNC_IRQ1_OUT] = "irq1_out",
240 [FUNC_EXT_IRQ] = "ext_irq",
241 [FUNC_MIIM] = "miim",
242 [FUNC_MIIM_a] = "miim_a",
243 [FUNC_MIIM_b] = "miim_b",
244 [FUNC_MIIM_c] = "miim_c",
245 [FUNC_MIIM_Sa] = "miim_slave_a",
246 [FUNC_MIIM_Sb] = "miim_slave_b",
247 [FUNC_PHY_LED] = "phy_led",
248 [FUNC_PCI_WAKE] = "pci_wake",
249 [FUNC_MD] = "md",
250 [FUNC_OB_TRG] = "ob_trig",
251 [FUNC_OB_TRG_a] = "ob_trig_a",
252 [FUNC_OB_TRG_b] = "ob_trig_b",
253 [FUNC_PTP0] = "ptp0",
254 [FUNC_PTP1] = "ptp1",
255 [FUNC_PTP2] = "ptp2",
256 [FUNC_PTP3] = "ptp3",
257 [FUNC_PTPSYNC_0] = "ptpsync_0",
258 [FUNC_PTPSYNC_1] = "ptpsync_1",
259 [FUNC_PTPSYNC_2] = "ptpsync_2",
260 [FUNC_PTPSYNC_3] = "ptpsync_3",
261 [FUNC_PTPSYNC_4] = "ptpsync_4",
262 [FUNC_PTPSYNC_5] = "ptpsync_5",
263 [FUNC_PTPSYNC_6] = "ptpsync_6",
264 [FUNC_PTPSYNC_7] = "ptpsync_7",
265 [FUNC_PWM] = "pwm",
266 [FUNC_PWM_a] = "pwm_a",
267 [FUNC_PWM_b] = "pwm_b",
268 [FUNC_QSPI1] = "qspi1",
269 [FUNC_QSPI2] = "qspi2",
270 [FUNC_R] = "reserved",
271 [FUNC_RECO_a] = "reco_a",
272 [FUNC_RECO_b] = "reco_b",
273 [FUNC_RECO_CLK] = "reco_clk",
274 [FUNC_SD] = "sd",
275 [FUNC_SFP] = "sfp",
276 [FUNC_SFP_SD] = "sfp_sd",
277 [FUNC_SG0] = "sg0",
278 [FUNC_SG1] = "sg1",
279 [FUNC_SG2] = "sg2",
280 [FUNC_SGPIO_a] = "sgpio_a",
281 [FUNC_SGPIO_b] = "sgpio_b",
282 [FUNC_SI] = "si",
283 [FUNC_SI2] = "si2",
284 [FUNC_TACHO] = "tacho",
285 [FUNC_TACHO_a] = "tacho_a",
286 [FUNC_TACHO_b] = "tacho_b",
287 [FUNC_TWI] = "twi",
288 [FUNC_TWI2] = "twi2",
289 [FUNC_TWI3] = "twi3",
290 [FUNC_TWI_SCL_M] = "twi_scl_m",
291 [FUNC_TWI_SLC_GATE] = "twi_slc_gate",
292 [FUNC_TWI_SLC_GATE_AD] = "twi_slc_gate_ad",
293 [FUNC_USB_H_a] = "usb_host_a",
294 [FUNC_USB_H_b] = "usb_host_b",
295 [FUNC_USB_H_c] = "usb_host_c",
296 [FUNC_USB_S_a] = "usb_slave_a",
297 [FUNC_USB_S_b] = "usb_slave_b",
298 [FUNC_USB_S_c] = "usb_slave_c",
299 [FUNC_UART] = "uart",
300 [FUNC_UART2] = "uart2",
301 [FUNC_UART3] = "uart3",
302 [FUNC_PLL_STAT] = "pll_stat",
303 [FUNC_EMMC] = "emmc",
304 [FUNC_EMMC_SD] = "emmc_sd",
305 [FUNC_REF_CLK] = "ref_clk",
306 [FUNC_RCVRD_CLK] = "rcvrd_clk",
307};
308
309struct ocelot_pmx_func {
310 const char **groups;
311 unsigned int ngroups;
312};
313
314struct ocelot_pin_caps {
315 unsigned int pin;
316 unsigned char functions[OCELOT_FUNC_PER_PIN];
317 unsigned char a_functions[OCELOT_FUNC_PER_PIN]; /* Additional functions */
318};
319
320struct ocelot_pincfg_data {
321 u8 pd_bit;
322 u8 pu_bit;
323 u8 drive_bits;
324 u8 schmitt_bit;
325};
326
327struct ocelot_pinctrl {
328 struct device *dev;
329 struct pinctrl_dev *pctl;
330 struct gpio_chip gpio_chip;
331 struct regmap *map;
332 struct regmap *pincfg;
333 struct pinctrl_desc *desc;
334 const struct ocelot_pincfg_data *pincfg_data;
335 struct ocelot_pmx_func func[FUNC_MAX];
336 u8 stride;
337 struct workqueue_struct *wq;
338};
339
340struct ocelot_match_data {
341 struct pinctrl_desc desc;
342 struct ocelot_pincfg_data pincfg_data;
343};
344
345struct ocelot_irq_work {
346 struct work_struct irq_work;
347 struct irq_desc *irq_desc;
348};
349
350#define LUTON_P(p, f0, f1) \
351static struct ocelot_pin_caps luton_pin_##p = { \
352 .pin = p, \
353 .functions = { \
354 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE, \
355 }, \
356}
357
358LUTON_P(0, SG0, NONE);
359LUTON_P(1, SG0, NONE);
360LUTON_P(2, SG0, NONE);
361LUTON_P(3, SG0, NONE);
362LUTON_P(4, TACHO, NONE);
363LUTON_P(5, TWI, PHY_LED);
364LUTON_P(6, TWI, PHY_LED);
365LUTON_P(7, NONE, PHY_LED);
366LUTON_P(8, EXT_IRQ, PHY_LED);
367LUTON_P(9, EXT_IRQ, PHY_LED);
368LUTON_P(10, SFP, PHY_LED);
369LUTON_P(11, SFP, PHY_LED);
370LUTON_P(12, SFP, PHY_LED);
371LUTON_P(13, SFP, PHY_LED);
372LUTON_P(14, SI, PHY_LED);
373LUTON_P(15, SI, PHY_LED);
374LUTON_P(16, SI, PHY_LED);
375LUTON_P(17, SFP, PHY_LED);
376LUTON_P(18, SFP, PHY_LED);
377LUTON_P(19, SFP, PHY_LED);
378LUTON_P(20, SFP, PHY_LED);
379LUTON_P(21, SFP, PHY_LED);
380LUTON_P(22, SFP, PHY_LED);
381LUTON_P(23, SFP, PHY_LED);
382LUTON_P(24, SFP, PHY_LED);
383LUTON_P(25, SFP, PHY_LED);
384LUTON_P(26, SFP, PHY_LED);
385LUTON_P(27, SFP, PHY_LED);
386LUTON_P(28, SFP, PHY_LED);
387LUTON_P(29, PWM, NONE);
388LUTON_P(30, UART, NONE);
389LUTON_P(31, UART, NONE);
390
391#define LUTON_PIN(n) { \
392 .number = n, \
393 .name = "GPIO_"#n, \
394 .drv_data = &luton_pin_##n \
395}
396
397static const struct pinctrl_pin_desc luton_pins[] = {
398 LUTON_PIN(0),
399 LUTON_PIN(1),
400 LUTON_PIN(2),
401 LUTON_PIN(3),
402 LUTON_PIN(4),
403 LUTON_PIN(5),
404 LUTON_PIN(6),
405 LUTON_PIN(7),
406 LUTON_PIN(8),
407 LUTON_PIN(9),
408 LUTON_PIN(10),
409 LUTON_PIN(11),
410 LUTON_PIN(12),
411 LUTON_PIN(13),
412 LUTON_PIN(14),
413 LUTON_PIN(15),
414 LUTON_PIN(16),
415 LUTON_PIN(17),
416 LUTON_PIN(18),
417 LUTON_PIN(19),
418 LUTON_PIN(20),
419 LUTON_PIN(21),
420 LUTON_PIN(22),
421 LUTON_PIN(23),
422 LUTON_PIN(24),
423 LUTON_PIN(25),
424 LUTON_PIN(26),
425 LUTON_PIN(27),
426 LUTON_PIN(28),
427 LUTON_PIN(29),
428 LUTON_PIN(30),
429 LUTON_PIN(31),
430};
431
432#define SERVAL_P(p, f0, f1, f2) \
433static struct ocelot_pin_caps serval_pin_##p = { \
434 .pin = p, \
435 .functions = { \
436 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
437 }, \
438}
439
440SERVAL_P(0, SG0, NONE, NONE);
441SERVAL_P(1, SG0, NONE, NONE);
442SERVAL_P(2, SG0, NONE, NONE);
443SERVAL_P(3, SG0, NONE, NONE);
444SERVAL_P(4, TACHO, NONE, NONE);
445SERVAL_P(5, PWM, NONE, NONE);
446SERVAL_P(6, TWI, NONE, NONE);
447SERVAL_P(7, TWI, NONE, NONE);
448SERVAL_P(8, SI, NONE, NONE);
449SERVAL_P(9, SI, MD, NONE);
450SERVAL_P(10, SI, MD, NONE);
451SERVAL_P(11, SFP, MD, TWI_SCL_M);
452SERVAL_P(12, SFP, MD, TWI_SCL_M);
453SERVAL_P(13, SFP, UART2, TWI_SCL_M);
454SERVAL_P(14, SFP, UART2, TWI_SCL_M);
455SERVAL_P(15, SFP, PTP0, TWI_SCL_M);
456SERVAL_P(16, SFP, PTP0, TWI_SCL_M);
457SERVAL_P(17, SFP, PCI_WAKE, TWI_SCL_M);
458SERVAL_P(18, SFP, NONE, TWI_SCL_M);
459SERVAL_P(19, SFP, NONE, TWI_SCL_M);
460SERVAL_P(20, SFP, NONE, TWI_SCL_M);
461SERVAL_P(21, SFP, NONE, TWI_SCL_M);
462SERVAL_P(22, NONE, NONE, NONE);
463SERVAL_P(23, NONE, NONE, NONE);
464SERVAL_P(24, NONE, NONE, NONE);
465SERVAL_P(25, NONE, NONE, NONE);
466SERVAL_P(26, UART, NONE, NONE);
467SERVAL_P(27, UART, NONE, NONE);
468SERVAL_P(28, IRQ0, NONE, NONE);
469SERVAL_P(29, IRQ1, NONE, NONE);
470SERVAL_P(30, PTP0, NONE, NONE);
471SERVAL_P(31, PTP0, NONE, NONE);
472
473#define SERVAL_PIN(n) { \
474 .number = n, \
475 .name = "GPIO_"#n, \
476 .drv_data = &serval_pin_##n \
477}
478
479static const struct pinctrl_pin_desc serval_pins[] = {
480 SERVAL_PIN(0),
481 SERVAL_PIN(1),
482 SERVAL_PIN(2),
483 SERVAL_PIN(3),
484 SERVAL_PIN(4),
485 SERVAL_PIN(5),
486 SERVAL_PIN(6),
487 SERVAL_PIN(7),
488 SERVAL_PIN(8),
489 SERVAL_PIN(9),
490 SERVAL_PIN(10),
491 SERVAL_PIN(11),
492 SERVAL_PIN(12),
493 SERVAL_PIN(13),
494 SERVAL_PIN(14),
495 SERVAL_PIN(15),
496 SERVAL_PIN(16),
497 SERVAL_PIN(17),
498 SERVAL_PIN(18),
499 SERVAL_PIN(19),
500 SERVAL_PIN(20),
501 SERVAL_PIN(21),
502 SERVAL_PIN(22),
503 SERVAL_PIN(23),
504 SERVAL_PIN(24),
505 SERVAL_PIN(25),
506 SERVAL_PIN(26),
507 SERVAL_PIN(27),
508 SERVAL_PIN(28),
509 SERVAL_PIN(29),
510 SERVAL_PIN(30),
511 SERVAL_PIN(31),
512};
513
514#define OCELOT_P(p, f0, f1, f2) \
515static struct ocelot_pin_caps ocelot_pin_##p = { \
516 .pin = p, \
517 .functions = { \
518 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2, \
519 }, \
520}
521
522OCELOT_P(0, SG0, NONE, NONE);
523OCELOT_P(1, SG0, NONE, NONE);
524OCELOT_P(2, SG0, NONE, NONE);
525OCELOT_P(3, SG0, NONE, NONE);
526OCELOT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
527OCELOT_P(5, IRQ1_IN, IRQ1_OUT, PCI_WAKE);
528OCELOT_P(6, UART, TWI_SCL_M, NONE);
529OCELOT_P(7, UART, TWI_SCL_M, NONE);
530OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT);
531OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT);
532OCELOT_P(10, PTP2, TWI_SCL_M, SFP);
533OCELOT_P(11, PTP3, TWI_SCL_M, SFP);
534OCELOT_P(12, UART2, TWI_SCL_M, SFP);
535OCELOT_P(13, UART2, TWI_SCL_M, SFP);
536OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
537OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
538OCELOT_P(16, TWI, NONE, SI);
539OCELOT_P(17, TWI, TWI_SCL_M, SI);
540OCELOT_P(18, PTP0, TWI_SCL_M, NONE);
541OCELOT_P(19, PTP1, TWI_SCL_M, NONE);
542OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M);
543OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M);
544
545#define OCELOT_PIN(n) { \
546 .number = n, \
547 .name = "GPIO_"#n, \
548 .drv_data = &ocelot_pin_##n \
549}
550
551static const struct pinctrl_pin_desc ocelot_pins[] = {
552 OCELOT_PIN(0),
553 OCELOT_PIN(1),
554 OCELOT_PIN(2),
555 OCELOT_PIN(3),
556 OCELOT_PIN(4),
557 OCELOT_PIN(5),
558 OCELOT_PIN(6),
559 OCELOT_PIN(7),
560 OCELOT_PIN(8),
561 OCELOT_PIN(9),
562 OCELOT_PIN(10),
563 OCELOT_PIN(11),
564 OCELOT_PIN(12),
565 OCELOT_PIN(13),
566 OCELOT_PIN(14),
567 OCELOT_PIN(15),
568 OCELOT_PIN(16),
569 OCELOT_PIN(17),
570 OCELOT_PIN(18),
571 OCELOT_PIN(19),
572 OCELOT_PIN(20),
573 OCELOT_PIN(21),
574};
575
576#define JAGUAR2_P(p, f0, f1) \
577static struct ocelot_pin_caps jaguar2_pin_##p = { \
578 .pin = p, \
579 .functions = { \
580 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_NONE \
581 }, \
582}
583
584JAGUAR2_P(0, SG0, NONE);
585JAGUAR2_P(1, SG0, NONE);
586JAGUAR2_P(2, SG0, NONE);
587JAGUAR2_P(3, SG0, NONE);
588JAGUAR2_P(4, SG1, NONE);
589JAGUAR2_P(5, SG1, NONE);
590JAGUAR2_P(6, IRQ0_IN, IRQ0_OUT);
591JAGUAR2_P(7, IRQ1_IN, IRQ1_OUT);
592JAGUAR2_P(8, PTP0, NONE);
593JAGUAR2_P(9, PTP1, NONE);
594JAGUAR2_P(10, UART, NONE);
595JAGUAR2_P(11, UART, NONE);
596JAGUAR2_P(12, SG1, NONE);
597JAGUAR2_P(13, SG1, NONE);
598JAGUAR2_P(14, TWI, TWI_SCL_M);
599JAGUAR2_P(15, TWI, NONE);
600JAGUAR2_P(16, SI, TWI_SCL_M);
601JAGUAR2_P(17, SI, TWI_SCL_M);
602JAGUAR2_P(18, SI, TWI_SCL_M);
603JAGUAR2_P(19, PCI_WAKE, NONE);
604JAGUAR2_P(20, IRQ0_OUT, TWI_SCL_M);
605JAGUAR2_P(21, IRQ1_OUT, TWI_SCL_M);
606JAGUAR2_P(22, TACHO, NONE);
607JAGUAR2_P(23, PWM, NONE);
608JAGUAR2_P(24, UART2, NONE);
609JAGUAR2_P(25, UART2, SI);
610JAGUAR2_P(26, PTP2, SI);
611JAGUAR2_P(27, PTP3, SI);
612JAGUAR2_P(28, TWI2, SI);
613JAGUAR2_P(29, TWI2, SI);
614JAGUAR2_P(30, SG2, SI);
615JAGUAR2_P(31, SG2, SI);
616JAGUAR2_P(32, SG2, SI);
617JAGUAR2_P(33, SG2, SI);
618JAGUAR2_P(34, NONE, TWI_SCL_M);
619JAGUAR2_P(35, NONE, TWI_SCL_M);
620JAGUAR2_P(36, NONE, TWI_SCL_M);
621JAGUAR2_P(37, NONE, TWI_SCL_M);
622JAGUAR2_P(38, NONE, TWI_SCL_M);
623JAGUAR2_P(39, NONE, TWI_SCL_M);
624JAGUAR2_P(40, NONE, TWI_SCL_M);
625JAGUAR2_P(41, NONE, TWI_SCL_M);
626JAGUAR2_P(42, NONE, TWI_SCL_M);
627JAGUAR2_P(43, NONE, TWI_SCL_M);
628JAGUAR2_P(44, NONE, SFP);
629JAGUAR2_P(45, NONE, SFP);
630JAGUAR2_P(46, NONE, SFP);
631JAGUAR2_P(47, NONE, SFP);
632JAGUAR2_P(48, SFP, NONE);
633JAGUAR2_P(49, SFP, SI);
634JAGUAR2_P(50, SFP, SI);
635JAGUAR2_P(51, SFP, SI);
636JAGUAR2_P(52, SFP, NONE);
637JAGUAR2_P(53, SFP, NONE);
638JAGUAR2_P(54, SFP, NONE);
639JAGUAR2_P(55, SFP, NONE);
640JAGUAR2_P(56, MIIM, SFP);
641JAGUAR2_P(57, MIIM, SFP);
642JAGUAR2_P(58, MIIM, SFP);
643JAGUAR2_P(59, MIIM, SFP);
644JAGUAR2_P(60, NONE, NONE);
645JAGUAR2_P(61, NONE, NONE);
646JAGUAR2_P(62, NONE, NONE);
647JAGUAR2_P(63, NONE, NONE);
648
649#define JAGUAR2_PIN(n) { \
650 .number = n, \
651 .name = "GPIO_"#n, \
652 .drv_data = &jaguar2_pin_##n \
653}
654
655static const struct pinctrl_pin_desc jaguar2_pins[] = {
656 JAGUAR2_PIN(0),
657 JAGUAR2_PIN(1),
658 JAGUAR2_PIN(2),
659 JAGUAR2_PIN(3),
660 JAGUAR2_PIN(4),
661 JAGUAR2_PIN(5),
662 JAGUAR2_PIN(6),
663 JAGUAR2_PIN(7),
664 JAGUAR2_PIN(8),
665 JAGUAR2_PIN(9),
666 JAGUAR2_PIN(10),
667 JAGUAR2_PIN(11),
668 JAGUAR2_PIN(12),
669 JAGUAR2_PIN(13),
670 JAGUAR2_PIN(14),
671 JAGUAR2_PIN(15),
672 JAGUAR2_PIN(16),
673 JAGUAR2_PIN(17),
674 JAGUAR2_PIN(18),
675 JAGUAR2_PIN(19),
676 JAGUAR2_PIN(20),
677 JAGUAR2_PIN(21),
678 JAGUAR2_PIN(22),
679 JAGUAR2_PIN(23),
680 JAGUAR2_PIN(24),
681 JAGUAR2_PIN(25),
682 JAGUAR2_PIN(26),
683 JAGUAR2_PIN(27),
684 JAGUAR2_PIN(28),
685 JAGUAR2_PIN(29),
686 JAGUAR2_PIN(30),
687 JAGUAR2_PIN(31),
688 JAGUAR2_PIN(32),
689 JAGUAR2_PIN(33),
690 JAGUAR2_PIN(34),
691 JAGUAR2_PIN(35),
692 JAGUAR2_PIN(36),
693 JAGUAR2_PIN(37),
694 JAGUAR2_PIN(38),
695 JAGUAR2_PIN(39),
696 JAGUAR2_PIN(40),
697 JAGUAR2_PIN(41),
698 JAGUAR2_PIN(42),
699 JAGUAR2_PIN(43),
700 JAGUAR2_PIN(44),
701 JAGUAR2_PIN(45),
702 JAGUAR2_PIN(46),
703 JAGUAR2_PIN(47),
704 JAGUAR2_PIN(48),
705 JAGUAR2_PIN(49),
706 JAGUAR2_PIN(50),
707 JAGUAR2_PIN(51),
708 JAGUAR2_PIN(52),
709 JAGUAR2_PIN(53),
710 JAGUAR2_PIN(54),
711 JAGUAR2_PIN(55),
712 JAGUAR2_PIN(56),
713 JAGUAR2_PIN(57),
714 JAGUAR2_PIN(58),
715 JAGUAR2_PIN(59),
716 JAGUAR2_PIN(60),
717 JAGUAR2_PIN(61),
718 JAGUAR2_PIN(62),
719 JAGUAR2_PIN(63),
720};
721
722#define SERVALT_P(p, f0, f1, f2) \
723static struct ocelot_pin_caps servalt_pin_##p = { \
724 .pin = p, \
725 .functions = { \
726 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
727 }, \
728}
729
730SERVALT_P(0, SG0, NONE, NONE);
731SERVALT_P(1, SG0, NONE, NONE);
732SERVALT_P(2, SG0, NONE, NONE);
733SERVALT_P(3, SG0, NONE, NONE);
734SERVALT_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
735SERVALT_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
736SERVALT_P(6, UART, NONE, NONE);
737SERVALT_P(7, UART, NONE, NONE);
738SERVALT_P(8, SI, SFP, TWI_SCL_M);
739SERVALT_P(9, PCI_WAKE, SFP, SI);
740SERVALT_P(10, PTP0, SFP, TWI_SCL_M);
741SERVALT_P(11, PTP1, SFP, TWI_SCL_M);
742SERVALT_P(12, REF_CLK, SFP, TWI_SCL_M);
743SERVALT_P(13, REF_CLK, SFP, TWI_SCL_M);
744SERVALT_P(14, REF_CLK, IRQ0_OUT, SI);
745SERVALT_P(15, REF_CLK, IRQ1_OUT, SI);
746SERVALT_P(16, TACHO, SFP, SI);
747SERVALT_P(17, PWM, NONE, TWI_SCL_M);
748SERVALT_P(18, PTP2, SFP, SI);
749SERVALT_P(19, PTP3, SFP, SI);
750SERVALT_P(20, UART2, SFP, SI);
751SERVALT_P(21, UART2, NONE, NONE);
752SERVALT_P(22, MIIM, SFP, TWI2);
753SERVALT_P(23, MIIM, SFP, TWI2);
754SERVALT_P(24, TWI, NONE, NONE);
755SERVALT_P(25, TWI, SFP, TWI_SCL_M);
756SERVALT_P(26, TWI_SCL_M, SFP, SI);
757SERVALT_P(27, TWI_SCL_M, SFP, SI);
758SERVALT_P(28, TWI_SCL_M, SFP, SI);
759SERVALT_P(29, TWI_SCL_M, NONE, NONE);
760SERVALT_P(30, TWI_SCL_M, NONE, NONE);
761SERVALT_P(31, TWI_SCL_M, NONE, NONE);
762SERVALT_P(32, TWI_SCL_M, NONE, NONE);
763SERVALT_P(33, RCVRD_CLK, NONE, NONE);
764SERVALT_P(34, RCVRD_CLK, NONE, NONE);
765SERVALT_P(35, RCVRD_CLK, NONE, NONE);
766SERVALT_P(36, RCVRD_CLK, NONE, NONE);
767
768#define SERVALT_PIN(n) { \
769 .number = n, \
770 .name = "GPIO_"#n, \
771 .drv_data = &servalt_pin_##n \
772}
773
774static const struct pinctrl_pin_desc servalt_pins[] = {
775 SERVALT_PIN(0),
776 SERVALT_PIN(1),
777 SERVALT_PIN(2),
778 SERVALT_PIN(3),
779 SERVALT_PIN(4),
780 SERVALT_PIN(5),
781 SERVALT_PIN(6),
782 SERVALT_PIN(7),
783 SERVALT_PIN(8),
784 SERVALT_PIN(9),
785 SERVALT_PIN(10),
786 SERVALT_PIN(11),
787 SERVALT_PIN(12),
788 SERVALT_PIN(13),
789 SERVALT_PIN(14),
790 SERVALT_PIN(15),
791 SERVALT_PIN(16),
792 SERVALT_PIN(17),
793 SERVALT_PIN(18),
794 SERVALT_PIN(19),
795 SERVALT_PIN(20),
796 SERVALT_PIN(21),
797 SERVALT_PIN(22),
798 SERVALT_PIN(23),
799 SERVALT_PIN(24),
800 SERVALT_PIN(25),
801 SERVALT_PIN(26),
802 SERVALT_PIN(27),
803 SERVALT_PIN(28),
804 SERVALT_PIN(29),
805 SERVALT_PIN(30),
806 SERVALT_PIN(31),
807 SERVALT_PIN(32),
808 SERVALT_PIN(33),
809 SERVALT_PIN(34),
810 SERVALT_PIN(35),
811 SERVALT_PIN(36),
812};
813
814#define SPARX5_P(p, f0, f1, f2) \
815static struct ocelot_pin_caps sparx5_pin_##p = { \
816 .pin = p, \
817 .functions = { \
818 FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
819 }, \
820}
821
822SPARX5_P(0, SG0, PLL_STAT, NONE);
823SPARX5_P(1, SG0, NONE, NONE);
824SPARX5_P(2, SG0, NONE, NONE);
825SPARX5_P(3, SG0, NONE, NONE);
826SPARX5_P(4, SG1, NONE, NONE);
827SPARX5_P(5, SG1, NONE, NONE);
828SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
829SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
830SPARX5_P(8, PTP0, NONE, SFP);
831SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
832SPARX5_P(10, UART, NONE, NONE);
833SPARX5_P(11, UART, NONE, NONE);
834SPARX5_P(12, SG1, NONE, NONE);
835SPARX5_P(13, SG1, NONE, NONE);
836SPARX5_P(14, TWI, TWI_SCL_M, NONE);
837SPARX5_P(15, TWI, NONE, NONE);
838SPARX5_P(16, SI, TWI_SCL_M, SFP);
839SPARX5_P(17, SI, TWI_SCL_M, SFP);
840SPARX5_P(18, SI, TWI_SCL_M, SFP);
841SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
842SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
843SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
844SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
845SPARX5_P(23, PWM, UART3, TWI_SCL_M);
846SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
847SPARX5_P(25, PTP3, SI, TWI_SCL_M);
848SPARX5_P(26, UART2, SI, TWI_SCL_M);
849SPARX5_P(27, UART2, SI, TWI_SCL_M);
850SPARX5_P(28, TWI2, SI, SFP);
851SPARX5_P(29, TWI2, SI, SFP);
852SPARX5_P(30, SG2, SI, PWM);
853SPARX5_P(31, SG2, SI, TWI_SCL_M);
854SPARX5_P(32, SG2, SI, TWI_SCL_M);
855SPARX5_P(33, SG2, SI, SFP);
856SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
857SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
858SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
859SPARX5_P(37, SFP, NONE, EMMC);
860SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
861SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
862SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
863SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
864SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
865SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
866SPARX5_P(44, SI, SFP, EMMC);
867SPARX5_P(45, SI, SFP, EMMC);
868SPARX5_P(46, NONE, SFP, EMMC);
869SPARX5_P(47, NONE, SFP, EMMC);
870SPARX5_P(48, TWI3, SI, SFP);
871SPARX5_P(49, TWI3, NONE, SFP);
872SPARX5_P(50, SFP, NONE, TWI_SCL_M);
873SPARX5_P(51, SFP, SI, TWI_SCL_M);
874SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
875SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
876SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
877SPARX5_P(55, SFP, PTP3, PCI_WAKE);
878SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
879SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
880SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
881SPARX5_P(59, MIIM, SFP, NONE);
882SPARX5_P(60, RECO_CLK, NONE, NONE);
883SPARX5_P(61, RECO_CLK, NONE, NONE);
884SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
885SPARX5_P(63, RECO_CLK, NONE, NONE);
886
887#define SPARX5_PIN(n) { \
888 .number = n, \
889 .name = "GPIO_"#n, \
890 .drv_data = &sparx5_pin_##n \
891}
892
893static const struct pinctrl_pin_desc sparx5_pins[] = {
894 SPARX5_PIN(0),
895 SPARX5_PIN(1),
896 SPARX5_PIN(2),
897 SPARX5_PIN(3),
898 SPARX5_PIN(4),
899 SPARX5_PIN(5),
900 SPARX5_PIN(6),
901 SPARX5_PIN(7),
902 SPARX5_PIN(8),
903 SPARX5_PIN(9),
904 SPARX5_PIN(10),
905 SPARX5_PIN(11),
906 SPARX5_PIN(12),
907 SPARX5_PIN(13),
908 SPARX5_PIN(14),
909 SPARX5_PIN(15),
910 SPARX5_PIN(16),
911 SPARX5_PIN(17),
912 SPARX5_PIN(18),
913 SPARX5_PIN(19),
914 SPARX5_PIN(20),
915 SPARX5_PIN(21),
916 SPARX5_PIN(22),
917 SPARX5_PIN(23),
918 SPARX5_PIN(24),
919 SPARX5_PIN(25),
920 SPARX5_PIN(26),
921 SPARX5_PIN(27),
922 SPARX5_PIN(28),
923 SPARX5_PIN(29),
924 SPARX5_PIN(30),
925 SPARX5_PIN(31),
926 SPARX5_PIN(32),
927 SPARX5_PIN(33),
928 SPARX5_PIN(34),
929 SPARX5_PIN(35),
930 SPARX5_PIN(36),
931 SPARX5_PIN(37),
932 SPARX5_PIN(38),
933 SPARX5_PIN(39),
934 SPARX5_PIN(40),
935 SPARX5_PIN(41),
936 SPARX5_PIN(42),
937 SPARX5_PIN(43),
938 SPARX5_PIN(44),
939 SPARX5_PIN(45),
940 SPARX5_PIN(46),
941 SPARX5_PIN(47),
942 SPARX5_PIN(48),
943 SPARX5_PIN(49),
944 SPARX5_PIN(50),
945 SPARX5_PIN(51),
946 SPARX5_PIN(52),
947 SPARX5_PIN(53),
948 SPARX5_PIN(54),
949 SPARX5_PIN(55),
950 SPARX5_PIN(56),
951 SPARX5_PIN(57),
952 SPARX5_PIN(58),
953 SPARX5_PIN(59),
954 SPARX5_PIN(60),
955 SPARX5_PIN(61),
956 SPARX5_PIN(62),
957 SPARX5_PIN(63),
958};
959
960#define LAN966X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \
961static struct ocelot_pin_caps lan966x_pin_##p = { \
962 .pin = p, \
963 .functions = { \
964 FUNC_##f0, FUNC_##f1, FUNC_##f2, \
965 FUNC_##f3 \
966 }, \
967 .a_functions = { \
968 FUNC_##f4, FUNC_##f5, FUNC_##f6, \
969 FUNC_##f7 \
970 }, \
971}
972
973/* Pinmuxing table taken from data sheet */
974/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */
975LAN966X_P(0, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
976LAN966X_P(1, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
977LAN966X_P(2, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
978LAN966X_P(3, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
979LAN966X_P(4, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
980LAN966X_P(5, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
981LAN966X_P(6, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
982LAN966X_P(7, GPIO, NONE, NONE, NONE, NONE, NONE, NONE, R);
983LAN966X_P(8, GPIO, FC0_a, USB_H_b, NONE, USB_S_b, NONE, NONE, R);
984LAN966X_P(9, GPIO, FC0_a, USB_H_b, NONE, NONE, NONE, NONE, R);
985LAN966X_P(10, GPIO, FC0_a, NONE, NONE, NONE, NONE, NONE, R);
986LAN966X_P(11, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
987LAN966X_P(12, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
988LAN966X_P(13, GPIO, FC1_a, NONE, NONE, NONE, NONE, NONE, R);
989LAN966X_P(14, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
990LAN966X_P(15, GPIO, FC2_a, NONE, NONE, NONE, NONE, NONE, R);
991LAN966X_P(16, GPIO, FC2_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
992LAN966X_P(17, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
993LAN966X_P(18, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
994LAN966X_P(19, GPIO, FC3_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, IRQ_OUT_c, R);
995LAN966X_P(20, GPIO, FC4_a, IB_TRG_a, NONE, OB_TRG_a, IRQ_IN_c, NONE, R);
996LAN966X_P(21, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
997LAN966X_P(22, GPIO, FC4_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
998LAN966X_P(23, GPIO, NONE, NONE, NONE, OB_TRG_a, NONE, NONE, R);
999LAN966X_P(24, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_IN_c, TACHO_a, R);
1000LAN966X_P(25, GPIO, FC0_b, IB_TRG_a, USB_H_c, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
1001LAN966X_P(26, GPIO, FC0_b, IB_TRG_a, USB_S_c, OB_TRG_a, CAN0_a, SFP_SD, R);
1002LAN966X_P(27, GPIO, NONE, NONE, NONE, OB_TRG_a, CAN0_a, PWM_a, R);
1003LAN966X_P(28, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, IRQ_OUT_c, SFP_SD, R);
1004LAN966X_P(29, GPIO, MIIM_a, NONE, NONE, OB_TRG_a, NONE, NONE, R);
1005LAN966X_P(30, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
1006LAN966X_P(31, GPIO, FC3_c, CAN1, CLKMON, OB_TRG, RECO_b, NONE, R);
1007LAN966X_P(32, GPIO, FC3_c, NONE, SGPIO_a, NONE, MIIM_Sa, NONE, R);
1008LAN966X_P(33, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
1009LAN966X_P(34, GPIO, FC1_b, NONE, SGPIO_a, NONE, MIIM_Sa, MIIM_b, R);
1010LAN966X_P(35, GPIO, FC1_b, PTPSYNC_0, SGPIO_a, CAN0_b, NONE, NONE, R);
1011LAN966X_P(36, GPIO, NONE, PTPSYNC_1, NONE, CAN0_b, NONE, NONE, R);
1012LAN966X_P(37, GPIO, FC_SHRD0, PTPSYNC_2, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1013LAN966X_P(38, GPIO, NONE, PTPSYNC_3, NONE, NONE, NONE, NONE, R);
1014LAN966X_P(39, GPIO, NONE, PTPSYNC_4, NONE, NONE, NONE, NONE, R);
1015LAN966X_P(40, GPIO, FC_SHRD1, PTPSYNC_5, NONE, NONE, NONE, NONE, R);
1016LAN966X_P(41, GPIO, FC_SHRD2, PTPSYNC_6, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1017LAN966X_P(42, GPIO, FC_SHRD3, PTPSYNC_7, TWI_SLC_GATE_AD, NONE, NONE, NONE, R);
1018LAN966X_P(43, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
1019LAN966X_P(44, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, RECO_a, IRQ_IN_a, R);
1020LAN966X_P(45, GPIO, FC2_b, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, NONE, IRQ_IN_a, R);
1021LAN966X_P(46, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD4, IRQ_IN_a, R);
1022LAN966X_P(47, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD5, IRQ_IN_a, R);
1023LAN966X_P(48, GPIO, FC1_c, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, FC_SHRD6, IRQ_IN_a, R);
1024LAN966X_P(49, GPIO, FC_SHRD7, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, IRQ_IN_a, R);
1025LAN966X_P(50, GPIO, FC_SHRD16, OB_TRG_b, IB_TRG_b, IRQ_OUT_a, TWI_SLC_GATE, NONE, R);
1026LAN966X_P(51, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, PWM_b, IRQ_IN_b, R);
1027LAN966X_P(52, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TACHO_b, IRQ_IN_b, R);
1028LAN966X_P(53, GPIO, FC3_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, NONE, IRQ_IN_b, R);
1029LAN966X_P(54, GPIO, FC_SHRD8, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
1030LAN966X_P(55, GPIO, FC_SHRD9, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, TWI_SLC_GATE, IRQ_IN_b, R);
1031LAN966X_P(56, GPIO, FC4_b, OB_TRG_b, IB_TRG_c, IRQ_OUT_b, FC_SHRD10, IRQ_IN_b, R);
1032LAN966X_P(57, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD11, IRQ_IN_b, R);
1033LAN966X_P(58, GPIO, FC4_b, TWI_SLC_GATE, IB_TRG_c, IRQ_OUT_b, FC_SHRD12, IRQ_IN_b, R);
1034LAN966X_P(59, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
1035LAN966X_P(60, GPIO, QSPI1, MIIM_c, NONE, NONE, MIIM_Sb, NONE, R);
1036LAN966X_P(61, GPIO, QSPI1, NONE, SGPIO_b, FC0_c, MIIM_Sb, NONE, R);
1037LAN966X_P(62, GPIO, QSPI1, FC_SHRD13, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
1038LAN966X_P(63, GPIO, QSPI1, FC_SHRD14, SGPIO_b, FC0_c, TWI_SLC_GATE, SFP_SD, R);
1039LAN966X_P(64, GPIO, QSPI1, FC4_c, SGPIO_b, FC_SHRD15, TWI_SLC_GATE, SFP_SD, R);
1040LAN966X_P(65, GPIO, USB_H_a, FC4_c, NONE, IRQ_OUT_c, TWI_SLC_GATE_AD, NONE, R);
1041LAN966X_P(66, GPIO, USB_H_a, FC4_c, USB_S_a, IRQ_OUT_c, IRQ_IN_c, NONE, R);
1042LAN966X_P(67, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1043LAN966X_P(68, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1044LAN966X_P(69, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1045LAN966X_P(70, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1046LAN966X_P(71, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1047LAN966X_P(72, GPIO, EMMC_SD, NONE, QSPI2, NONE, NONE, NONE, R);
1048LAN966X_P(73, GPIO, EMMC, NONE, NONE, SD, NONE, NONE, R);
1049LAN966X_P(74, GPIO, EMMC, NONE, FC_SHRD17, SD, TWI_SLC_GATE, NONE, R);
1050LAN966X_P(75, GPIO, EMMC, NONE, FC_SHRD18, SD, TWI_SLC_GATE, NONE, R);
1051LAN966X_P(76, GPIO, EMMC, NONE, FC_SHRD19, SD, TWI_SLC_GATE, NONE, R);
1052LAN966X_P(77, GPIO, EMMC_SD, NONE, FC_SHRD20, NONE, TWI_SLC_GATE, NONE, R);
1053
1054#define LAN966X_PIN(n) { \
1055 .number = n, \
1056 .name = "GPIO_"#n, \
1057 .drv_data = &lan966x_pin_##n \
1058}
1059
1060static const struct pinctrl_pin_desc lan966x_pins[] = {
1061 LAN966X_PIN(0),
1062 LAN966X_PIN(1),
1063 LAN966X_PIN(2),
1064 LAN966X_PIN(3),
1065 LAN966X_PIN(4),
1066 LAN966X_PIN(5),
1067 LAN966X_PIN(6),
1068 LAN966X_PIN(7),
1069 LAN966X_PIN(8),
1070 LAN966X_PIN(9),
1071 LAN966X_PIN(10),
1072 LAN966X_PIN(11),
1073 LAN966X_PIN(12),
1074 LAN966X_PIN(13),
1075 LAN966X_PIN(14),
1076 LAN966X_PIN(15),
1077 LAN966X_PIN(16),
1078 LAN966X_PIN(17),
1079 LAN966X_PIN(18),
1080 LAN966X_PIN(19),
1081 LAN966X_PIN(20),
1082 LAN966X_PIN(21),
1083 LAN966X_PIN(22),
1084 LAN966X_PIN(23),
1085 LAN966X_PIN(24),
1086 LAN966X_PIN(25),
1087 LAN966X_PIN(26),
1088 LAN966X_PIN(27),
1089 LAN966X_PIN(28),
1090 LAN966X_PIN(29),
1091 LAN966X_PIN(30),
1092 LAN966X_PIN(31),
1093 LAN966X_PIN(32),
1094 LAN966X_PIN(33),
1095 LAN966X_PIN(34),
1096 LAN966X_PIN(35),
1097 LAN966X_PIN(36),
1098 LAN966X_PIN(37),
1099 LAN966X_PIN(38),
1100 LAN966X_PIN(39),
1101 LAN966X_PIN(40),
1102 LAN966X_PIN(41),
1103 LAN966X_PIN(42),
1104 LAN966X_PIN(43),
1105 LAN966X_PIN(44),
1106 LAN966X_PIN(45),
1107 LAN966X_PIN(46),
1108 LAN966X_PIN(47),
1109 LAN966X_PIN(48),
1110 LAN966X_PIN(49),
1111 LAN966X_PIN(50),
1112 LAN966X_PIN(51),
1113 LAN966X_PIN(52),
1114 LAN966X_PIN(53),
1115 LAN966X_PIN(54),
1116 LAN966X_PIN(55),
1117 LAN966X_PIN(56),
1118 LAN966X_PIN(57),
1119 LAN966X_PIN(58),
1120 LAN966X_PIN(59),
1121 LAN966X_PIN(60),
1122 LAN966X_PIN(61),
1123 LAN966X_PIN(62),
1124 LAN966X_PIN(63),
1125 LAN966X_PIN(64),
1126 LAN966X_PIN(65),
1127 LAN966X_PIN(66),
1128 LAN966X_PIN(67),
1129 LAN966X_PIN(68),
1130 LAN966X_PIN(69),
1131 LAN966X_PIN(70),
1132 LAN966X_PIN(71),
1133 LAN966X_PIN(72),
1134 LAN966X_PIN(73),
1135 LAN966X_PIN(74),
1136 LAN966X_PIN(75),
1137 LAN966X_PIN(76),
1138 LAN966X_PIN(77),
1139};
1140
1141static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
1142{
1143 return ARRAY_SIZE(ocelot_function_names);
1144}
1145
1146static const char *ocelot_get_function_name(struct pinctrl_dev *pctldev,
1147 unsigned int function)
1148{
1149 return ocelot_function_names[function];
1150}
1151
1152static int ocelot_get_function_groups(struct pinctrl_dev *pctldev,
1153 unsigned int function,
1154 const char *const **groups,
1155 unsigned *const num_groups)
1156{
1157 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1158
1159 *groups = info->func[function].groups;
1160 *num_groups = info->func[function].ngroups;
1161
1162 return 0;
1163}
1164
1165static int ocelot_pin_function_idx(struct ocelot_pinctrl *info,
1166 unsigned int pin, unsigned int function)
1167{
1168 struct ocelot_pin_caps *p = info->desc->pins[pin].drv_data;
1169 int i;
1170
1171 for (i = 0; i < OCELOT_FUNC_PER_PIN; i++) {
1172 if (function == p->functions[i])
1173 return i;
1174
1175 if (function == p->a_functions[i])
1176 return i + OCELOT_FUNC_PER_PIN;
1177 }
1178
1179 return -1;
1180}
1181
1182#define REG_ALT(msb, info, p) (OCELOT_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))
1183
1184static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
1185 unsigned int selector, unsigned int group)
1186{
1187 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1188 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1189 unsigned int p = pin->pin % 32;
1190 int f;
1191
1192 f = ocelot_pin_function_idx(info, group, selector);
1193 if (f < 0)
1194 return -EINVAL;
1195
1196 /*
1197 * f is encoded on two bits.
1198 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1199 * ALT[1]
1200 * This is racy because both registers can't be updated at the same time
1201 * but it doesn't matter much for now.
1202 * Note: ALT0/ALT1 are organized specially for 64 gpio targets
1203 */
1204 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1205 BIT(p), f << p);
1206 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1207 BIT(p), f << (p - 1));
1208
1209 return 0;
1210}
1211
1212static int lan966x_pinmux_set_mux(struct pinctrl_dev *pctldev,
1213 unsigned int selector, unsigned int group)
1214{
1215 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1216 struct ocelot_pin_caps *pin = info->desc->pins[group].drv_data;
1217 unsigned int p = pin->pin % 32;
1218 int f;
1219
1220 f = ocelot_pin_function_idx(info, group, selector);
1221 if (f < 0)
1222 return -EINVAL;
1223
1224 /*
1225 * f is encoded on three bits.
1226 * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of
1227 * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]
1228 * This is racy because three registers can't be updated at the same time
1229 * but it doesn't matter much for now.
1230 * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets
1231 */
1232 regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
1233 BIT(p), f << p);
1234 regmap_update_bits(info->map, REG_ALT(1, info, pin->pin),
1235 BIT(p), (f >> 1) << p);
1236 regmap_update_bits(info->map, REG_ALT(2, info, pin->pin),
1237 BIT(p), (f >> 2) << p);
1238
1239 return 0;
1240}
1241
1242#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
1243
1244static int ocelot_gpio_set_direction(struct pinctrl_dev *pctldev,
1245 struct pinctrl_gpio_range *range,
1246 unsigned int pin, bool input)
1247{
1248 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1249 unsigned int p = pin % 32;
1250
1251 regmap_update_bits(info->map, REG(OCELOT_GPIO_OE, info, pin), BIT(p),
1252 input ? 0 : BIT(p));
1253
1254 return 0;
1255}
1256
1257static int ocelot_gpio_request_enable(struct pinctrl_dev *pctldev,
1258 struct pinctrl_gpio_range *range,
1259 unsigned int offset)
1260{
1261 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1262 unsigned int p = offset % 32;
1263
1264 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1265 BIT(p), 0);
1266 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1267 BIT(p), 0);
1268
1269 return 0;
1270}
1271
1272static int lan966x_gpio_request_enable(struct pinctrl_dev *pctldev,
1273 struct pinctrl_gpio_range *range,
1274 unsigned int offset)
1275{
1276 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1277 unsigned int p = offset % 32;
1278
1279 regmap_update_bits(info->map, REG_ALT(0, info, offset),
1280 BIT(p), 0);
1281 regmap_update_bits(info->map, REG_ALT(1, info, offset),
1282 BIT(p), 0);
1283 regmap_update_bits(info->map, REG_ALT(2, info, offset),
1284 BIT(p), 0);
1285
1286 return 0;
1287}
1288
1289static const struct pinmux_ops ocelot_pmx_ops = {
1290 .get_functions_count = ocelot_get_functions_count,
1291 .get_function_name = ocelot_get_function_name,
1292 .get_function_groups = ocelot_get_function_groups,
1293 .set_mux = ocelot_pinmux_set_mux,
1294 .gpio_set_direction = ocelot_gpio_set_direction,
1295 .gpio_request_enable = ocelot_gpio_request_enable,
1296};
1297
1298static const struct pinmux_ops lan966x_pmx_ops = {
1299 .get_functions_count = ocelot_get_functions_count,
1300 .get_function_name = ocelot_get_function_name,
1301 .get_function_groups = ocelot_get_function_groups,
1302 .set_mux = lan966x_pinmux_set_mux,
1303 .gpio_set_direction = ocelot_gpio_set_direction,
1304 .gpio_request_enable = lan966x_gpio_request_enable,
1305};
1306
1307static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev)
1308{
1309 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1310
1311 return info->desc->npins;
1312}
1313
1314static const char *ocelot_pctl_get_group_name(struct pinctrl_dev *pctldev,
1315 unsigned int group)
1316{
1317 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1318
1319 return info->desc->pins[group].name;
1320}
1321
1322static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
1323 unsigned int group,
1324 const unsigned int **pins,
1325 unsigned int *num_pins)
1326{
1327 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1328
1329 *pins = &info->desc->pins[group].number;
1330 *num_pins = 1;
1331
1332 return 0;
1333}
1334
1335static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
1336 unsigned int pin,
1337 unsigned int reg,
1338 int *val)
1339{
1340 int ret = -EOPNOTSUPP;
1341
1342 if (info->pincfg) {
1343 const struct ocelot_pincfg_data *opd = info->pincfg_data;
1344 u32 regcfg;
1345
1346 ret = regmap_read(info->pincfg,
1347 pin * regmap_get_reg_stride(info->pincfg),
1348 ®cfg);
1349 if (ret)
1350 return ret;
1351
1352 ret = 0;
1353 switch (reg) {
1354 case PINCONF_BIAS:
1355 *val = regcfg & (opd->pd_bit | opd->pu_bit);
1356 break;
1357
1358 case PINCONF_SCHMITT:
1359 *val = regcfg & opd->schmitt_bit;
1360 break;
1361
1362 case PINCONF_DRIVE_STRENGTH:
1363 *val = regcfg & opd->drive_bits;
1364 break;
1365
1366 default:
1367 ret = -EOPNOTSUPP;
1368 break;
1369 }
1370 }
1371 return ret;
1372}
1373
1374static int ocelot_pincfg_clrsetbits(struct ocelot_pinctrl *info, u32 regaddr,
1375 u32 clrbits, u32 setbits)
1376{
1377 u32 val;
1378 int ret;
1379
1380 ret = regmap_read(info->pincfg,
1381 regaddr * regmap_get_reg_stride(info->pincfg),
1382 &val);
1383 if (ret)
1384 return ret;
1385
1386 val &= ~clrbits;
1387 val |= setbits;
1388
1389 ret = regmap_write(info->pincfg,
1390 regaddr * regmap_get_reg_stride(info->pincfg),
1391 val);
1392
1393 return ret;
1394}
1395
1396static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
1397 unsigned int pin,
1398 unsigned int reg,
1399 int val)
1400{
1401 int ret = -EOPNOTSUPP;
1402
1403 if (info->pincfg) {
1404 const struct ocelot_pincfg_data *opd = info->pincfg_data;
1405
1406 ret = 0;
1407 switch (reg) {
1408 case PINCONF_BIAS:
1409 ret = ocelot_pincfg_clrsetbits(info, pin,
1410 opd->pd_bit | opd->pu_bit,
1411 val);
1412 break;
1413
1414 case PINCONF_SCHMITT:
1415 ret = ocelot_pincfg_clrsetbits(info, pin,
1416 opd->schmitt_bit,
1417 val);
1418 break;
1419
1420 case PINCONF_DRIVE_STRENGTH:
1421 if (val <= 3)
1422 ret = ocelot_pincfg_clrsetbits(info, pin,
1423 opd->drive_bits,
1424 val);
1425 else
1426 ret = -EINVAL;
1427 break;
1428
1429 default:
1430 ret = -EOPNOTSUPP;
1431 break;
1432 }
1433 }
1434 return ret;
1435}
1436
1437static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
1438 unsigned int pin, unsigned long *config)
1439{
1440 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1441 u32 param = pinconf_to_config_param(*config);
1442 int val, err;
1443
1444 switch (param) {
1445 case PIN_CONFIG_BIAS_DISABLE:
1446 case PIN_CONFIG_BIAS_PULL_UP:
1447 case PIN_CONFIG_BIAS_PULL_DOWN:
1448 err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
1449 if (err)
1450 return err;
1451 if (param == PIN_CONFIG_BIAS_DISABLE)
1452 val = (val == 0);
1453 else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
1454 val = !!(val & info->pincfg_data->pd_bit);
1455 else /* PIN_CONFIG_BIAS_PULL_UP */
1456 val = !!(val & info->pincfg_data->pu_bit);
1457 break;
1458
1459 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1460 if (!info->pincfg_data->schmitt_bit)
1461 return -EOPNOTSUPP;
1462
1463 err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
1464 if (err)
1465 return err;
1466
1467 val = !!(val & info->pincfg_data->schmitt_bit);
1468 break;
1469
1470 case PIN_CONFIG_DRIVE_STRENGTH:
1471 err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
1472 &val);
1473 if (err)
1474 return err;
1475 break;
1476
1477 case PIN_CONFIG_OUTPUT:
1478 err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
1479 &val);
1480 if (err)
1481 return err;
1482 val = !!(val & BIT(pin % 32));
1483 break;
1484
1485 case PIN_CONFIG_INPUT_ENABLE:
1486 case PIN_CONFIG_OUTPUT_ENABLE:
1487 err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
1488 &val);
1489 if (err)
1490 return err;
1491 val = val & BIT(pin % 32);
1492 if (param == PIN_CONFIG_OUTPUT_ENABLE)
1493 val = !!val;
1494 else
1495 val = !val;
1496 break;
1497
1498 default:
1499 return -EOPNOTSUPP;
1500 }
1501
1502 *config = pinconf_to_config_packed(param, val);
1503
1504 return 0;
1505}
1506
1507static int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1508 unsigned long *configs, unsigned int num_configs)
1509{
1510 struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1511 const struct ocelot_pincfg_data *opd = info->pincfg_data;
1512 u32 param, arg, p;
1513 int cfg, err = 0;
1514
1515 for (cfg = 0; cfg < num_configs; cfg++) {
1516 param = pinconf_to_config_param(configs[cfg]);
1517 arg = pinconf_to_config_argument(configs[cfg]);
1518
1519 switch (param) {
1520 case PIN_CONFIG_BIAS_DISABLE:
1521 case PIN_CONFIG_BIAS_PULL_UP:
1522 case PIN_CONFIG_BIAS_PULL_DOWN:
1523 arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
1524 (param == PIN_CONFIG_BIAS_PULL_UP) ?
1525 opd->pu_bit : opd->pd_bit;
1526
1527 err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
1528 if (err)
1529 goto err;
1530
1531 break;
1532
1533 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1534 if (!opd->schmitt_bit)
1535 return -EOPNOTSUPP;
1536
1537 arg = arg ? opd->schmitt_bit : 0;
1538 err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
1539 arg);
1540 if (err)
1541 goto err;
1542
1543 break;
1544
1545 case PIN_CONFIG_DRIVE_STRENGTH:
1546 err = ocelot_hw_set_value(info, pin,
1547 PINCONF_DRIVE_STRENGTH,
1548 arg);
1549 if (err)
1550 goto err;
1551
1552 break;
1553
1554 case PIN_CONFIG_OUTPUT_ENABLE:
1555 case PIN_CONFIG_INPUT_ENABLE:
1556 case PIN_CONFIG_OUTPUT:
1557 p = pin % 32;
1558 if (arg)
1559 regmap_write(info->map,
1560 REG(OCELOT_GPIO_OUT_SET, info,
1561 pin),
1562 BIT(p));
1563 else
1564 regmap_write(info->map,
1565 REG(OCELOT_GPIO_OUT_CLR, info,
1566 pin),
1567 BIT(p));
1568 regmap_update_bits(info->map,
1569 REG(OCELOT_GPIO_OE, info, pin),
1570 BIT(p),
1571 param == PIN_CONFIG_INPUT_ENABLE ?
1572 0 : BIT(p));
1573 break;
1574
1575 default:
1576 err = -EOPNOTSUPP;
1577 }
1578 }
1579err:
1580 return err;
1581}
1582
1583static const struct pinconf_ops ocelot_confops = {
1584 .is_generic = true,
1585 .pin_config_get = ocelot_pinconf_get,
1586 .pin_config_set = ocelot_pinconf_set,
1587 .pin_config_config_dbg_show = pinconf_generic_dump_config,
1588};
1589
1590static const struct pinctrl_ops ocelot_pctl_ops = {
1591 .get_groups_count = ocelot_pctl_get_groups_count,
1592 .get_group_name = ocelot_pctl_get_group_name,
1593 .get_group_pins = ocelot_pctl_get_group_pins,
1594 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1595 .dt_free_map = pinconf_generic_dt_free_map,
1596};
1597
1598static struct ocelot_match_data luton_desc = {
1599 .desc = {
1600 .name = "luton-pinctrl",
1601 .pins = luton_pins,
1602 .npins = ARRAY_SIZE(luton_pins),
1603 .pctlops = &ocelot_pctl_ops,
1604 .pmxops = &ocelot_pmx_ops,
1605 .owner = THIS_MODULE,
1606 },
1607};
1608
1609static struct ocelot_match_data serval_desc = {
1610 .desc = {
1611 .name = "serval-pinctrl",
1612 .pins = serval_pins,
1613 .npins = ARRAY_SIZE(serval_pins),
1614 .pctlops = &ocelot_pctl_ops,
1615 .pmxops = &ocelot_pmx_ops,
1616 .owner = THIS_MODULE,
1617 },
1618};
1619
1620static struct ocelot_match_data ocelot_desc = {
1621 .desc = {
1622 .name = "ocelot-pinctrl",
1623 .pins = ocelot_pins,
1624 .npins = ARRAY_SIZE(ocelot_pins),
1625 .pctlops = &ocelot_pctl_ops,
1626 .pmxops = &ocelot_pmx_ops,
1627 .owner = THIS_MODULE,
1628 },
1629};
1630
1631static struct ocelot_match_data jaguar2_desc = {
1632 .desc = {
1633 .name = "jaguar2-pinctrl",
1634 .pins = jaguar2_pins,
1635 .npins = ARRAY_SIZE(jaguar2_pins),
1636 .pctlops = &ocelot_pctl_ops,
1637 .pmxops = &ocelot_pmx_ops,
1638 .owner = THIS_MODULE,
1639 },
1640};
1641
1642static struct ocelot_match_data servalt_desc = {
1643 .desc = {
1644 .name = "servalt-pinctrl",
1645 .pins = servalt_pins,
1646 .npins = ARRAY_SIZE(servalt_pins),
1647 .pctlops = &ocelot_pctl_ops,
1648 .pmxops = &ocelot_pmx_ops,
1649 .owner = THIS_MODULE,
1650 },
1651};
1652
1653static struct ocelot_match_data sparx5_desc = {
1654 .desc = {
1655 .name = "sparx5-pinctrl",
1656 .pins = sparx5_pins,
1657 .npins = ARRAY_SIZE(sparx5_pins),
1658 .pctlops = &ocelot_pctl_ops,
1659 .pmxops = &ocelot_pmx_ops,
1660 .confops = &ocelot_confops,
1661 .owner = THIS_MODULE,
1662 },
1663 .pincfg_data = {
1664 .pd_bit = BIT(4),
1665 .pu_bit = BIT(3),
1666 .drive_bits = GENMASK(1, 0),
1667 .schmitt_bit = BIT(2),
1668 },
1669};
1670
1671static struct ocelot_match_data lan966x_desc = {
1672 .desc = {
1673 .name = "lan966x-pinctrl",
1674 .pins = lan966x_pins,
1675 .npins = ARRAY_SIZE(lan966x_pins),
1676 .pctlops = &ocelot_pctl_ops,
1677 .pmxops = &lan966x_pmx_ops,
1678 .confops = &ocelot_confops,
1679 .owner = THIS_MODULE,
1680 },
1681 .pincfg_data = {
1682 .pd_bit = BIT(3),
1683 .pu_bit = BIT(2),
1684 .drive_bits = GENMASK(1, 0),
1685 },
1686};
1687
1688static int ocelot_create_group_func_map(struct device *dev,
1689 struct ocelot_pinctrl *info)
1690{
1691 int f, npins, i;
1692 u8 *pins = kcalloc(info->desc->npins, sizeof(u8), GFP_KERNEL);
1693
1694 if (!pins)
1695 return -ENOMEM;
1696
1697 for (f = 0; f < FUNC_MAX; f++) {
1698 for (npins = 0, i = 0; i < info->desc->npins; i++) {
1699 if (ocelot_pin_function_idx(info, i, f) >= 0)
1700 pins[npins++] = i;
1701 }
1702
1703 if (!npins)
1704 continue;
1705
1706 info->func[f].ngroups = npins;
1707 info->func[f].groups = devm_kcalloc(dev, npins, sizeof(char *),
1708 GFP_KERNEL);
1709 if (!info->func[f].groups) {
1710 kfree(pins);
1711 return -ENOMEM;
1712 }
1713
1714 for (i = 0; i < npins; i++)
1715 info->func[f].groups[i] =
1716 info->desc->pins[pins[i]].name;
1717 }
1718
1719 kfree(pins);
1720
1721 return 0;
1722}
1723
1724static int ocelot_pinctrl_register(struct platform_device *pdev,
1725 struct ocelot_pinctrl *info)
1726{
1727 int ret;
1728
1729 ret = ocelot_create_group_func_map(&pdev->dev, info);
1730 if (ret) {
1731 dev_err(&pdev->dev, "Unable to create group func map.\n");
1732 return ret;
1733 }
1734
1735 info->pctl = devm_pinctrl_register(&pdev->dev, info->desc, info);
1736 if (IS_ERR(info->pctl)) {
1737 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1738 return PTR_ERR(info->pctl);
1739 }
1740
1741 return 0;
1742}
1743
1744static int ocelot_gpio_get(struct gpio_chip *chip, unsigned int offset)
1745{
1746 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1747 unsigned int val;
1748
1749 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, offset), &val);
1750
1751 return !!(val & BIT(offset % 32));
1752}
1753
1754static void ocelot_gpio_set(struct gpio_chip *chip, unsigned int offset,
1755 int value)
1756{
1757 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1758
1759 if (value)
1760 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1761 BIT(offset % 32));
1762 else
1763 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1764 BIT(offset % 32));
1765}
1766
1767static int ocelot_gpio_get_direction(struct gpio_chip *chip,
1768 unsigned int offset)
1769{
1770 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1771 unsigned int val;
1772
1773 regmap_read(info->map, REG(OCELOT_GPIO_OE, info, offset), &val);
1774
1775 if (val & BIT(offset % 32))
1776 return GPIO_LINE_DIRECTION_OUT;
1777
1778 return GPIO_LINE_DIRECTION_IN;
1779}
1780
1781static int ocelot_gpio_direction_input(struct gpio_chip *chip,
1782 unsigned int offset)
1783{
1784 return pinctrl_gpio_direction_input(chip->base + offset);
1785}
1786
1787static int ocelot_gpio_direction_output(struct gpio_chip *chip,
1788 unsigned int offset, int value)
1789{
1790 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1791 unsigned int pin = BIT(offset % 32);
1792
1793 if (value)
1794 regmap_write(info->map, REG(OCELOT_GPIO_OUT_SET, info, offset),
1795 pin);
1796 else
1797 regmap_write(info->map, REG(OCELOT_GPIO_OUT_CLR, info, offset),
1798 pin);
1799
1800 return pinctrl_gpio_direction_output(chip->base + offset);
1801}
1802
1803static const struct gpio_chip ocelot_gpiolib_chip = {
1804 .request = gpiochip_generic_request,
1805 .free = gpiochip_generic_free,
1806 .set = ocelot_gpio_set,
1807 .get = ocelot_gpio_get,
1808 .get_direction = ocelot_gpio_get_direction,
1809 .direction_input = ocelot_gpio_direction_input,
1810 .direction_output = ocelot_gpio_direction_output,
1811 .owner = THIS_MODULE,
1812};
1813
1814static void ocelot_irq_mask(struct irq_data *data)
1815{
1816 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1817 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1818 unsigned int gpio = irqd_to_hwirq(data);
1819
1820 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1821 BIT(gpio % 32), 0);
1822 gpiochip_disable_irq(chip, gpio);
1823}
1824
1825static void ocelot_irq_work(struct work_struct *work)
1826{
1827 struct ocelot_irq_work *w = container_of(work, struct ocelot_irq_work, irq_work);
1828 struct irq_chip *parent_chip = irq_desc_get_chip(w->irq_desc);
1829 struct gpio_chip *chip = irq_desc_get_chip_data(w->irq_desc);
1830 struct irq_data *data = irq_desc_get_irq_data(w->irq_desc);
1831 unsigned int gpio = irqd_to_hwirq(data);
1832
1833 local_irq_disable();
1834 chained_irq_enter(parent_chip, w->irq_desc);
1835 generic_handle_domain_irq(chip->irq.domain, gpio);
1836 chained_irq_exit(parent_chip, w->irq_desc);
1837 local_irq_enable();
1838
1839 kfree(w);
1840}
1841
1842static void ocelot_irq_unmask_level(struct irq_data *data)
1843{
1844 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1845 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1846 struct irq_desc *desc = irq_data_to_desc(data);
1847 unsigned int gpio = irqd_to_hwirq(data);
1848 unsigned int bit = BIT(gpio % 32);
1849 bool ack = false, active = false;
1850 u8 trigger_level;
1851 int val;
1852
1853 trigger_level = irqd_get_trigger_type(data);
1854
1855 /* Check if the interrupt line is still active. */
1856 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
1857 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||
1858 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))
1859 active = true;
1860
1861 /*
1862 * Check if the interrupt controller has seen any changes in the
1863 * interrupt line.
1864 */
1865 regmap_read(info->map, REG(OCELOT_GPIO_INTR, info, gpio), &val);
1866 if (val & bit)
1867 ack = true;
1868
1869 /* Try to clear any rising edges */
1870 if (!active && ack)
1871 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1872 bit, bit);
1873
1874 /* Enable the interrupt now */
1875 gpiochip_enable_irq(chip, gpio);
1876 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1877 bit, bit);
1878
1879 /*
1880 * In case the interrupt line is still active then it means that
1881 * there happen another interrupt while the line was active.
1882 * So we missed that one, so we need to kick the interrupt again
1883 * handler.
1884 */
1885 regmap_read(info->map, REG(OCELOT_GPIO_IN, info, gpio), &val);
1886 if ((!(val & bit) && trigger_level == IRQ_TYPE_LEVEL_LOW) ||
1887 (val & bit && trigger_level == IRQ_TYPE_LEVEL_HIGH))
1888 active = true;
1889
1890 if (active) {
1891 struct ocelot_irq_work *work;
1892
1893 work = kmalloc(sizeof(*work), GFP_ATOMIC);
1894 if (!work)
1895 return;
1896
1897 work->irq_desc = desc;
1898 INIT_WORK(&work->irq_work, ocelot_irq_work);
1899 queue_work(info->wq, &work->irq_work);
1900 }
1901}
1902
1903static void ocelot_irq_unmask(struct irq_data *data)
1904{
1905 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1906 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1907 unsigned int gpio = irqd_to_hwirq(data);
1908
1909 gpiochip_enable_irq(chip, gpio);
1910 regmap_update_bits(info->map, REG(OCELOT_GPIO_INTR_ENA, info, gpio),
1911 BIT(gpio % 32), BIT(gpio % 32));
1912}
1913
1914static void ocelot_irq_ack(struct irq_data *data)
1915{
1916 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
1917 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1918 unsigned int gpio = irqd_to_hwirq(data);
1919
1920 regmap_write_bits(info->map, REG(OCELOT_GPIO_INTR, info, gpio),
1921 BIT(gpio % 32), BIT(gpio % 32));
1922}
1923
1924static int ocelot_irq_set_type(struct irq_data *data, unsigned int type);
1925
1926static struct irq_chip ocelot_level_irqchip = {
1927 .name = "gpio",
1928 .irq_mask = ocelot_irq_mask,
1929 .irq_ack = ocelot_irq_ack,
1930 .irq_unmask = ocelot_irq_unmask_level,
1931 .flags = IRQCHIP_IMMUTABLE,
1932 .irq_set_type = ocelot_irq_set_type,
1933 GPIOCHIP_IRQ_RESOURCE_HELPERS
1934};
1935
1936static struct irq_chip ocelot_irqchip = {
1937 .name = "gpio",
1938 .irq_mask = ocelot_irq_mask,
1939 .irq_ack = ocelot_irq_ack,
1940 .irq_unmask = ocelot_irq_unmask,
1941 .irq_set_type = ocelot_irq_set_type,
1942 .flags = IRQCHIP_IMMUTABLE,
1943 GPIOCHIP_IRQ_RESOURCE_HELPERS
1944};
1945
1946static int ocelot_irq_set_type(struct irq_data *data, unsigned int type)
1947{
1948 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
1949 irq_set_chip_handler_name_locked(data, &ocelot_level_irqchip,
1950 handle_level_irq, NULL);
1951 if (type & IRQ_TYPE_EDGE_BOTH)
1952 irq_set_chip_handler_name_locked(data, &ocelot_irqchip,
1953 handle_edge_irq, NULL);
1954
1955 return 0;
1956}
1957
1958static void ocelot_irq_handler(struct irq_desc *desc)
1959{
1960 struct irq_chip *parent_chip = irq_desc_get_chip(desc);
1961 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
1962 struct ocelot_pinctrl *info = gpiochip_get_data(chip);
1963 unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride;
1964 unsigned int reg = 0, irq, i;
1965 unsigned long irqs;
1966
1967 for (i = 0; i < info->stride; i++) {
1968 regmap_read(info->map, id_reg + 4 * i, ®);
1969 if (!reg)
1970 continue;
1971
1972 chained_irq_enter(parent_chip, desc);
1973
1974 irqs = reg;
1975
1976 for_each_set_bit(irq, &irqs,
1977 min(32U, info->desc->npins - 32 * i))
1978 generic_handle_domain_irq(chip->irq.domain, irq + 32 * i);
1979
1980 chained_irq_exit(parent_chip, desc);
1981 }
1982}
1983
1984static int ocelot_gpiochip_register(struct platform_device *pdev,
1985 struct ocelot_pinctrl *info)
1986{
1987 struct gpio_chip *gc;
1988 struct gpio_irq_chip *girq;
1989 int irq;
1990
1991 info->gpio_chip = ocelot_gpiolib_chip;
1992
1993 gc = &info->gpio_chip;
1994 gc->ngpio = info->desc->npins;
1995 gc->parent = &pdev->dev;
1996 gc->base = -1;
1997 gc->label = "ocelot-gpio";
1998
1999 irq = platform_get_irq_optional(pdev, 0);
2000 if (irq > 0) {
2001 girq = &gc->irq;
2002 gpio_irq_chip_set_chip(girq, &ocelot_irqchip);
2003 girq->parent_handler = ocelot_irq_handler;
2004 girq->num_parents = 1;
2005 girq->parents = devm_kcalloc(&pdev->dev, 1,
2006 sizeof(*girq->parents),
2007 GFP_KERNEL);
2008 if (!girq->parents)
2009 return -ENOMEM;
2010 girq->parents[0] = irq;
2011 girq->default_type = IRQ_TYPE_NONE;
2012 girq->handler = handle_edge_irq;
2013 }
2014
2015 return devm_gpiochip_add_data(&pdev->dev, gc, info);
2016}
2017
2018static const struct of_device_id ocelot_pinctrl_of_match[] = {
2019 { .compatible = "mscc,luton-pinctrl", .data = &luton_desc },
2020 { .compatible = "mscc,serval-pinctrl", .data = &serval_desc },
2021 { .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
2022 { .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
2023 { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc },
2024 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
2025 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc },
2026 {},
2027};
2028MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);
2029
2030static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev,
2031 const struct ocelot_pinctrl *info)
2032{
2033 void __iomem *base;
2034
2035 const struct regmap_config regmap_config = {
2036 .reg_bits = 32,
2037 .val_bits = 32,
2038 .reg_stride = 4,
2039 .max_register = info->desc->npins * 4,
2040 .name = "pincfg",
2041 };
2042
2043 base = devm_platform_ioremap_resource(pdev, 1);
2044 if (IS_ERR(base)) {
2045 dev_dbg(&pdev->dev, "Failed to ioremap config registers (no extended pinconf)\n");
2046 return NULL;
2047 }
2048
2049 return devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
2050}
2051
2052static void ocelot_destroy_workqueue(void *data)
2053{
2054 destroy_workqueue(data);
2055}
2056
2057static int ocelot_pinctrl_probe(struct platform_device *pdev)
2058{
2059 const struct ocelot_match_data *data;
2060 struct device *dev = &pdev->dev;
2061 struct ocelot_pinctrl *info;
2062 struct reset_control *reset;
2063 struct regmap *pincfg;
2064 int ret;
2065 struct regmap_config regmap_config = {
2066 .reg_bits = 32,
2067 .val_bits = 32,
2068 .reg_stride = 4,
2069 };
2070
2071 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
2072 if (!info)
2073 return -ENOMEM;
2074
2075 data = device_get_match_data(dev);
2076 if (!data)
2077 return -EINVAL;
2078
2079 info->desc = devm_kmemdup(dev, &data->desc, sizeof(*info->desc),
2080 GFP_KERNEL);
2081 if (!info->desc)
2082 return -ENOMEM;
2083
2084 info->wq = alloc_ordered_workqueue("ocelot_ordered", 0);
2085 if (!info->wq)
2086 return -ENOMEM;
2087
2088 ret = devm_add_action_or_reset(dev, ocelot_destroy_workqueue,
2089 info->wq);
2090 if (ret)
2091 return ret;
2092
2093 info->pincfg_data = &data->pincfg_data;
2094
2095 reset = devm_reset_control_get_optional_shared(dev, "switch");
2096 if (IS_ERR(reset))
2097 return dev_err_probe(dev, PTR_ERR(reset),
2098 "Failed to get reset\n");
2099 reset_control_reset(reset);
2100
2101 info->stride = 1 + (info->desc->npins - 1) / 32;
2102
2103 regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
2104
2105 info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config);
2106 if (IS_ERR(info->map))
2107 return dev_err_probe(dev, PTR_ERR(info->map),
2108 "Failed to create regmap\n");
2109 dev_set_drvdata(dev, info);
2110 info->dev = dev;
2111
2112 /* Pinconf registers */
2113 if (info->desc->confops) {
2114 pincfg = ocelot_pinctrl_create_pincfg(pdev, info);
2115 if (IS_ERR(pincfg))
2116 dev_dbg(dev, "Failed to create pincfg regmap\n");
2117 else
2118 info->pincfg = pincfg;
2119 }
2120
2121 ret = ocelot_pinctrl_register(pdev, info);
2122 if (ret)
2123 return ret;
2124
2125 ret = ocelot_gpiochip_register(pdev, info);
2126 if (ret)
2127 return ret;
2128
2129 dev_info(dev, "driver registered\n");
2130
2131 return 0;
2132}
2133
2134static struct platform_driver ocelot_pinctrl_driver = {
2135 .driver = {
2136 .name = "pinctrl-ocelot",
2137 .of_match_table = of_match_ptr(ocelot_pinctrl_of_match),
2138 .suppress_bind_attrs = true,
2139 },
2140 .probe = ocelot_pinctrl_probe,
2141};
2142module_platform_driver(ocelot_pinctrl_driver);
2143
2144MODULE_DESCRIPTION("Ocelot Chip Pinctrl Driver");
2145MODULE_LICENSE("Dual MIT/GPL");