Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Rockchip AXI PCIe endpoint controller driver
4 *
5 * Copyright (c) 2018 Rockchip, Inc.
6 *
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
9 */
10
11#include <linux/configfs.h>
12#include <linux/delay.h>
13#include <linux/kernel.h>
14#include <linux/of.h>
15#include <linux/pci-epc.h>
16#include <linux/platform_device.h>
17#include <linux/pci-epf.h>
18#include <linux/sizes.h>
19
20#include "pcie-rockchip.h"
21
22/**
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
25 * @epc: PCI EPC device
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
29 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
30 * dedicated outbound regions is mapped.
31 * @irq_cpu_addr: base address in the CPU space where a write access triggers
32 * the sending of a memory write (MSI) / normal message (legacy
33 * IRQ) TLP through the PCIe bus.
34 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
35 * dedicated outbound region.
36 * @irq_pci_fn: the latest PCI function that has updated the mapping of
37 * the MSI/legacy IRQ dedicated outbound region.
38 * @irq_pending: bitmask of asserted legacy IRQs.
39 */
40struct rockchip_pcie_ep {
41 struct rockchip_pcie rockchip;
42 struct pci_epc *epc;
43 u32 max_regions;
44 unsigned long ob_region_map;
45 phys_addr_t *ob_addr;
46 phys_addr_t irq_phys_addr;
47 void __iomem *irq_cpu_addr;
48 u64 irq_pci_addr;
49 u8 irq_pci_fn;
50 u8 irq_pending;
51};
52
53static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
54 u32 region)
55{
56 rockchip_pcie_write(rockchip, 0,
57 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
58 rockchip_pcie_write(rockchip, 0,
59 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
60 rockchip_pcie_write(rockchip, 0,
61 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
62 rockchip_pcie_write(rockchip, 0,
63 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
64 rockchip_pcie_write(rockchip, 0,
65 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region));
66 rockchip_pcie_write(rockchip, 0,
67 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region));
68}
69
70static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
71 u32 r, u32 type, u64 cpu_addr,
72 u64 pci_addr, size_t size)
73{
74 u64 sz = 1ULL << fls64(size - 1);
75 int num_pass_bits = ilog2(sz);
76 u32 addr0, addr1, desc0, desc1;
77 bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG);
78
79 /* The minimal region size is 1MB */
80 if (num_pass_bits < 8)
81 num_pass_bits = 8;
82
83 cpu_addr -= rockchip->mem_res->start;
84 addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) &
85 PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
86 (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
87 addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr);
88 desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type;
89 desc1 = 0;
90
91 if (is_nor_msg) {
92 rockchip_pcie_write(rockchip, 0,
93 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
94 rockchip_pcie_write(rockchip, 0,
95 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
96 rockchip_pcie_write(rockchip, desc0,
97 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
98 rockchip_pcie_write(rockchip, desc1,
99 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
100 } else {
101 /* PCI bus address region */
102 rockchip_pcie_write(rockchip, addr0,
103 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
104 rockchip_pcie_write(rockchip, addr1,
105 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
106 rockchip_pcie_write(rockchip, desc0,
107 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
108 rockchip_pcie_write(rockchip, desc1,
109 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
110
111 addr0 =
112 ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
113 (lower_32_bits(cpu_addr) &
114 PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
115 addr1 = upper_32_bits(cpu_addr);
116 }
117
118 /* CPU bus address region */
119 rockchip_pcie_write(rockchip, addr0,
120 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r));
121 rockchip_pcie_write(rockchip, addr1,
122 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r));
123}
124
125static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
126 struct pci_epf_header *hdr)
127{
128 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
129 struct rockchip_pcie *rockchip = &ep->rockchip;
130
131 /* All functions share the same vendor ID with function 0 */
132 if (fn == 0) {
133 u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
134 (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
135
136 rockchip_pcie_write(rockchip, vid_regs,
137 PCIE_CORE_CONFIG_VENDOR);
138 }
139
140 rockchip_pcie_write(rockchip, hdr->deviceid << 16,
141 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID);
142
143 rockchip_pcie_write(rockchip,
144 hdr->revid |
145 hdr->progif_code << 8 |
146 hdr->subclass_code << 16 |
147 hdr->baseclass_code << 24,
148 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID);
149 rockchip_pcie_write(rockchip, hdr->cache_line_size,
150 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
151 PCI_CACHE_LINE_SIZE);
152 rockchip_pcie_write(rockchip, hdr->subsys_id << 16,
153 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
154 PCI_SUBSYSTEM_VENDOR_ID);
155 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8,
156 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
157 PCI_INTERRUPT_LINE);
158
159 return 0;
160}
161
162static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn,
163 struct pci_epf_bar *epf_bar)
164{
165 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
166 struct rockchip_pcie *rockchip = &ep->rockchip;
167 dma_addr_t bar_phys = epf_bar->phys_addr;
168 enum pci_barno bar = epf_bar->barno;
169 int flags = epf_bar->flags;
170 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
171 u64 sz;
172
173 /* BAR size is 2^(aperture + 7) */
174 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE);
175
176 /*
177 * roundup_pow_of_two() returns an unsigned long, which is not suited
178 * for 64bit values.
179 */
180 sz = 1ULL << fls64(sz - 1);
181 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
182
183 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
184 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
185 } else {
186 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
187 bool is_64bits = sz > SZ_2G;
188
189 if (is_64bits && (bar & 1))
190 return -EINVAL;
191
192 if (is_64bits && is_prefetch)
193 ctrl =
194 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
195 else if (is_prefetch)
196 ctrl =
197 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
198 else if (is_64bits)
199 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
200 else
201 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
202 }
203
204 if (bar < BAR_4) {
205 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
206 b = bar;
207 } else {
208 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
209 b = bar - BAR_4;
210 }
211
212 addr0 = lower_32_bits(bar_phys);
213 addr1 = upper_32_bits(bar_phys);
214
215 cfg = rockchip_pcie_read(rockchip, reg);
216 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
217 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
218 cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
219 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
220
221 rockchip_pcie_write(rockchip, cfg, reg);
222 rockchip_pcie_write(rockchip, addr0,
223 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
224 rockchip_pcie_write(rockchip, addr1,
225 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
226
227 return 0;
228}
229
230static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
231 struct pci_epf_bar *epf_bar)
232{
233 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
234 struct rockchip_pcie *rockchip = &ep->rockchip;
235 u32 reg, cfg, b, ctrl;
236 enum pci_barno bar = epf_bar->barno;
237
238 if (bar < BAR_4) {
239 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
240 b = bar;
241 } else {
242 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
243 b = bar - BAR_4;
244 }
245
246 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED;
247 cfg = rockchip_pcie_read(rockchip, reg);
248 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
249 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
250 cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
251
252 rockchip_pcie_write(rockchip, cfg, reg);
253 rockchip_pcie_write(rockchip, 0x0,
254 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
255 rockchip_pcie_write(rockchip, 0x0,
256 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
257}
258
259static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
260 phys_addr_t addr, u64 pci_addr,
261 size_t size)
262{
263 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
264 struct rockchip_pcie *pcie = &ep->rockchip;
265 u32 r;
266
267 r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
268 /*
269 * Region 0 is reserved for configuration space and shouldn't
270 * be used elsewhere per TRM, so leave it out.
271 */
272 if (r >= ep->max_regions - 1) {
273 dev_err(&epc->dev, "no free outbound region\n");
274 return -EINVAL;
275 }
276
277 rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr,
278 pci_addr, size);
279
280 set_bit(r, &ep->ob_region_map);
281 ep->ob_addr[r] = addr;
282
283 return 0;
284}
285
286static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
287 phys_addr_t addr)
288{
289 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
290 struct rockchip_pcie *rockchip = &ep->rockchip;
291 u32 r;
292
293 for (r = 0; r < ep->max_regions - 1; r++)
294 if (ep->ob_addr[r] == addr)
295 break;
296
297 /*
298 * Region 0 is reserved for configuration space and shouldn't
299 * be used elsewhere per TRM, so leave it out.
300 */
301 if (r == ep->max_regions - 1)
302 return;
303
304 rockchip_pcie_clear_ep_ob_atu(rockchip, r);
305
306 ep->ob_addr[r] = 0;
307 clear_bit(r, &ep->ob_region_map);
308}
309
310static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
311 u8 multi_msg_cap)
312{
313 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
314 struct rockchip_pcie *rockchip = &ep->rockchip;
315 u16 flags;
316
317 flags = rockchip_pcie_read(rockchip,
318 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
319 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
320 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
321 flags |=
322 ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
323 PCI_MSI_FLAGS_64BIT;
324 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
325 rockchip_pcie_write(rockchip, flags,
326 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
327 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
328 return 0;
329}
330
331static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
332{
333 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
334 struct rockchip_pcie *rockchip = &ep->rockchip;
335 u16 flags;
336
337 flags = rockchip_pcie_read(rockchip,
338 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
339 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
340 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
341 return -EINVAL;
342
343 return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
344 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
345}
346
347static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
348 u8 intx, bool is_asserted)
349{
350 struct rockchip_pcie *rockchip = &ep->rockchip;
351 u32 r = ep->max_regions - 1;
352 u32 offset;
353 u32 status;
354 u8 msg_code;
355
356 if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
357 ep->irq_pci_fn != fn)) {
358 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
359 AXI_WRAPPER_NOR_MSG,
360 ep->irq_phys_addr, 0, 0);
361 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
362 ep->irq_pci_fn = fn;
363 }
364
365 intx &= 3;
366 if (is_asserted) {
367 ep->irq_pending |= BIT(intx);
368 msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx;
369 } else {
370 ep->irq_pending &= ~BIT(intx);
371 msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
372 }
373
374 status = rockchip_pcie_read(rockchip,
375 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
376 ROCKCHIP_PCIE_EP_CMD_STATUS);
377 status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
378
379 if ((status != 0) ^ (ep->irq_pending != 0)) {
380 status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
381 rockchip_pcie_write(rockchip, status,
382 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
383 ROCKCHIP_PCIE_EP_CMD_STATUS);
384 }
385
386 offset =
387 ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
388 ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
389 writel(0, ep->irq_cpu_addr + offset);
390}
391
392static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
393 u8 intx)
394{
395 u16 cmd;
396
397 cmd = rockchip_pcie_read(&ep->rockchip,
398 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
399 ROCKCHIP_PCIE_EP_CMD_STATUS);
400
401 if (cmd & PCI_COMMAND_INTX_DISABLE)
402 return -EINVAL;
403
404 /*
405 * Should add some delay between toggling INTx per TRM vaguely saying
406 * it depends on some cycles of the AHB bus clock to function it. So
407 * add sufficient 1ms here.
408 */
409 rockchip_pcie_ep_assert_intx(ep, fn, intx, true);
410 mdelay(1);
411 rockchip_pcie_ep_assert_intx(ep, fn, intx, false);
412 return 0;
413}
414
415static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
416 u8 interrupt_num)
417{
418 struct rockchip_pcie *rockchip = &ep->rockchip;
419 u16 flags, mme, data, data_mask;
420 u8 msi_count;
421 u64 pci_addr, pci_addr_mask = 0xff;
422
423 /* Check MSI enable bit */
424 flags = rockchip_pcie_read(&ep->rockchip,
425 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
426 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
427 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
428 return -EINVAL;
429
430 /* Get MSI numbers from MME */
431 mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
432 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
433 msi_count = 1 << mme;
434 if (!interrupt_num || interrupt_num > msi_count)
435 return -EINVAL;
436
437 /* Set MSI private data */
438 data_mask = msi_count - 1;
439 data = rockchip_pcie_read(rockchip,
440 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
441 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
442 PCI_MSI_DATA_64);
443 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
444
445 /* Get MSI PCI address */
446 pci_addr = rockchip_pcie_read(rockchip,
447 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
448 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
449 PCI_MSI_ADDRESS_HI);
450 pci_addr <<= 32;
451 pci_addr |= rockchip_pcie_read(rockchip,
452 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
453 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
454 PCI_MSI_ADDRESS_LO);
455 pci_addr &= GENMASK_ULL(63, 2);
456
457 /* Set the outbound region if needed. */
458 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
459 ep->irq_pci_fn != fn)) {
460 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1,
461 AXI_WRAPPER_MEM_WRITE,
462 ep->irq_phys_addr,
463 pci_addr & ~pci_addr_mask,
464 pci_addr_mask + 1);
465 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
466 ep->irq_pci_fn = fn;
467 }
468
469 writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
470 return 0;
471}
472
473static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn,
474 enum pci_epc_irq_type type,
475 u16 interrupt_num)
476{
477 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
478
479 switch (type) {
480 case PCI_EPC_IRQ_LEGACY:
481 return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
482 case PCI_EPC_IRQ_MSI:
483 return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
484 default:
485 return -EINVAL;
486 }
487}
488
489static int rockchip_pcie_ep_start(struct pci_epc *epc)
490{
491 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
492 struct rockchip_pcie *rockchip = &ep->rockchip;
493 struct pci_epf *epf;
494 u32 cfg;
495
496 cfg = BIT(0);
497 list_for_each_entry(epf, &epc->pci_epf, list)
498 cfg |= BIT(epf->func_no);
499
500 rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
501
502 return 0;
503}
504
505static const struct pci_epc_features rockchip_pcie_epc_features = {
506 .linkup_notifier = false,
507 .msi_capable = true,
508 .msix_capable = false,
509};
510
511static const struct pci_epc_features*
512rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no)
513{
514 return &rockchip_pcie_epc_features;
515}
516
517static const struct pci_epc_ops rockchip_pcie_epc_ops = {
518 .write_header = rockchip_pcie_ep_write_header,
519 .set_bar = rockchip_pcie_ep_set_bar,
520 .clear_bar = rockchip_pcie_ep_clear_bar,
521 .map_addr = rockchip_pcie_ep_map_addr,
522 .unmap_addr = rockchip_pcie_ep_unmap_addr,
523 .set_msi = rockchip_pcie_ep_set_msi,
524 .get_msi = rockchip_pcie_ep_get_msi,
525 .raise_irq = rockchip_pcie_ep_raise_irq,
526 .start = rockchip_pcie_ep_start,
527 .get_features = rockchip_pcie_ep_get_features,
528};
529
530static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
531 struct rockchip_pcie_ep *ep)
532{
533 struct device *dev = rockchip->dev;
534 int err;
535
536 err = rockchip_pcie_parse_dt(rockchip);
537 if (err)
538 return err;
539
540 err = rockchip_pcie_get_phys(rockchip);
541 if (err)
542 return err;
543
544 err = of_property_read_u32(dev->of_node,
545 "rockchip,max-outbound-regions",
546 &ep->max_regions);
547 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
548 ep->max_regions = MAX_REGION_LIMIT;
549
550 err = of_property_read_u8(dev->of_node, "max-functions",
551 &ep->epc->max_functions);
552 if (err < 0)
553 ep->epc->max_functions = 1;
554
555 return 0;
556}
557
558static const struct of_device_id rockchip_pcie_ep_of_match[] = {
559 { .compatible = "rockchip,rk3399-pcie-ep"},
560 {},
561};
562
563static int rockchip_pcie_ep_probe(struct platform_device *pdev)
564{
565 struct device *dev = &pdev->dev;
566 struct rockchip_pcie_ep *ep;
567 struct rockchip_pcie *rockchip;
568 struct pci_epc *epc;
569 size_t max_regions;
570 int err;
571
572 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
573 if (!ep)
574 return -ENOMEM;
575
576 rockchip = &ep->rockchip;
577 rockchip->is_rc = false;
578 rockchip->dev = dev;
579
580 epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
581 if (IS_ERR(epc)) {
582 dev_err(dev, "failed to create epc device\n");
583 return PTR_ERR(epc);
584 }
585
586 ep->epc = epc;
587 epc_set_drvdata(epc, ep);
588
589 err = rockchip_pcie_parse_ep_dt(rockchip, ep);
590 if (err)
591 return err;
592
593 err = rockchip_pcie_enable_clocks(rockchip);
594 if (err)
595 return err;
596
597 err = rockchip_pcie_init_port(rockchip);
598 if (err)
599 goto err_disable_clocks;
600
601 /* Establish the link automatically */
602 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
603 PCIE_CLIENT_CONFIG);
604
605 max_regions = ep->max_regions;
606 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr),
607 GFP_KERNEL);
608
609 if (!ep->ob_addr) {
610 err = -ENOMEM;
611 goto err_uninit_port;
612 }
613
614 /* Only enable function 0 by default */
615 rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
616
617 err = pci_epc_mem_init(epc, rockchip->mem_res->start,
618 resource_size(rockchip->mem_res), PAGE_SIZE);
619 if (err < 0) {
620 dev_err(dev, "failed to initialize the memory space\n");
621 goto err_uninit_port;
622 }
623
624 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
625 SZ_128K);
626 if (!ep->irq_cpu_addr) {
627 dev_err(dev, "failed to reserve memory space for MSI\n");
628 err = -ENOMEM;
629 goto err_epc_mem_exit;
630 }
631
632 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
633
634 return 0;
635err_epc_mem_exit:
636 pci_epc_mem_exit(epc);
637err_uninit_port:
638 rockchip_pcie_deinit_phys(rockchip);
639err_disable_clocks:
640 rockchip_pcie_disable_clocks(rockchip);
641 return err;
642}
643
644static struct platform_driver rockchip_pcie_ep_driver = {
645 .driver = {
646 .name = "rockchip-pcie-ep",
647 .of_match_table = rockchip_pcie_ep_of_match,
648 },
649 .probe = rockchip_pcie_ep_probe,
650};
651
652builtin_platform_driver(rockchip_pcie_ep_driver);