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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Qualcomm PCIe Endpoint controller driver
4 *
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org
7 *
8 * Copyright (c) 2021, Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
10 */
11
12#include <linux/clk.h>
13#include <linux/debugfs.h>
14#include <linux/delay.h>
15#include <linux/gpio/consumer.h>
16#include <linux/mfd/syscon.h>
17#include <linux/phy/pcie.h>
18#include <linux/phy/phy.h>
19#include <linux/platform_device.h>
20#include <linux/pm_domain.h>
21#include <linux/regmap.h>
22#include <linux/reset.h>
23#include <linux/module.h>
24
25#include "pcie-designware.h"
26
27/* PARF registers */
28#define PARF_SYS_CTRL 0x00
29#define PARF_DB_CTRL 0x10
30#define PARF_PM_CTRL 0x20
31#define PARF_MHI_CLOCK_RESET_CTRL 0x174
32#define PARF_MHI_BASE_ADDR_LOWER 0x178
33#define PARF_MHI_BASE_ADDR_UPPER 0x17c
34#define PARF_DEBUG_INT_EN 0x190
35#define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
36#define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
37#define PARF_Q2A_FLUSH 0x1ac
38#define PARF_LTSSM 0x1b0
39#define PARF_CFG_BITS 0x210
40#define PARF_INT_ALL_STATUS 0x224
41#define PARF_INT_ALL_CLEAR 0x228
42#define PARF_INT_ALL_MASK 0x22c
43#define PARF_SLV_ADDR_MSB_CTRL 0x2c0
44#define PARF_DBI_BASE_ADDR 0x350
45#define PARF_DBI_BASE_ADDR_HI 0x354
46#define PARF_SLV_ADDR_SPACE_SIZE 0x358
47#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
48#define PARF_ATU_BASE_ADDR 0x634
49#define PARF_ATU_BASE_ADDR_HI 0x638
50#define PARF_SRIS_MODE 0x644
51#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
52#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
53#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
54#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
55#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
56#define PARF_DEVICE_TYPE 0x1000
57#define PARF_BDF_TO_SID_CFG 0x2c00
58
59/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
60#define PARF_INT_ALL_LINK_DOWN BIT(1)
61#define PARF_INT_ALL_BME BIT(2)
62#define PARF_INT_ALL_PM_TURNOFF BIT(3)
63#define PARF_INT_ALL_DEBUG BIT(4)
64#define PARF_INT_ALL_LTR BIT(5)
65#define PARF_INT_ALL_MHI_Q6 BIT(6)
66#define PARF_INT_ALL_MHI_A7 BIT(7)
67#define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
68#define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
69#define PARF_INT_ALL_MMIO_WRITE BIT(10)
70#define PARF_INT_ALL_CFG_WRITE BIT(11)
71#define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
72#define PARF_INT_ALL_LINK_UP BIT(13)
73#define PARF_INT_ALL_AER_LEGACY BIT(14)
74#define PARF_INT_ALL_PLS_ERR BIT(15)
75#define PARF_INT_ALL_PME_LEGACY BIT(16)
76#define PARF_INT_ALL_PLS_PME BIT(17)
77
78/* PARF_BDF_TO_SID_CFG register fields */
79#define PARF_BDF_TO_SID_BYPASS BIT(0)
80
81/* PARF_DEBUG_INT_EN register fields */
82#define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
83#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
84#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
85
86/* PARF_DEVICE_TYPE register fields */
87#define PARF_DEVICE_TYPE_EP 0x0
88
89/* PARF_PM_CTRL register fields */
90#define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
91#define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
92#define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
93
94/* PARF_MHI_CLOCK_RESET_CTRL fields */
95#define PARF_MSTR_AXI_CLK_EN BIT(1)
96
97/* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
98#define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
99
100/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
101#define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
102
103/* PARF_Q2A_FLUSH register fields */
104#define PARF_Q2A_FLUSH_EN BIT(16)
105
106/* PARF_SYS_CTRL register fields */
107#define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
108#define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
109#define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
110#define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
111
112/* PARF_DB_CTRL register fields */
113#define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
114#define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
115#define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
116#define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
117#define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
118
119/* PARF_CFG_BITS register fields */
120#define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
121
122/* ELBI registers */
123#define ELBI_SYS_STTS 0x08
124
125/* DBI registers */
126#define DBI_CON_STATUS 0x44
127
128/* DBI register fields */
129#define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
130
131#define XMLH_LINK_UP 0x400
132#define CORE_RESET_TIME_US_MIN 1000
133#define CORE_RESET_TIME_US_MAX 1005
134#define WAKE_DELAY_US 2000 /* 2 ms */
135
136#define to_pcie_ep(x) dev_get_drvdata((x)->dev)
137
138enum qcom_pcie_ep_link_status {
139 QCOM_PCIE_EP_LINK_DISABLED,
140 QCOM_PCIE_EP_LINK_ENABLED,
141 QCOM_PCIE_EP_LINK_UP,
142 QCOM_PCIE_EP_LINK_DOWN,
143};
144
145/**
146 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
147 * @pci: Designware PCIe controller struct
148 * @parf: Qualcomm PCIe specific PARF register base
149 * @elbi: Designware PCIe specific ELBI register base
150 * @mmio: MMIO register base
151 * @perst_map: PERST regmap
152 * @mmio_res: MMIO region resource
153 * @core_reset: PCIe Endpoint core reset
154 * @reset: PERST# GPIO
155 * @wake: WAKE# GPIO
156 * @phy: PHY controller block
157 * @debugfs: PCIe Endpoint Debugfs directory
158 * @clks: PCIe clocks
159 * @num_clks: PCIe clocks count
160 * @perst_en: Flag for PERST enable
161 * @perst_sep_en: Flag for PERST separation enable
162 * @link_status: PCIe Link status
163 * @global_irq: Qualcomm PCIe specific Global IRQ
164 * @perst_irq: PERST# IRQ
165 */
166struct qcom_pcie_ep {
167 struct dw_pcie pci;
168
169 void __iomem *parf;
170 void __iomem *elbi;
171 void __iomem *mmio;
172 struct regmap *perst_map;
173 struct resource *mmio_res;
174
175 struct reset_control *core_reset;
176 struct gpio_desc *reset;
177 struct gpio_desc *wake;
178 struct phy *phy;
179 struct dentry *debugfs;
180
181 struct clk_bulk_data *clks;
182 int num_clks;
183
184 u32 perst_en;
185 u32 perst_sep_en;
186
187 enum qcom_pcie_ep_link_status link_status;
188 int global_irq;
189 int perst_irq;
190};
191
192static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
193{
194 struct dw_pcie *pci = &pcie_ep->pci;
195 struct device *dev = pci->dev;
196 int ret;
197
198 ret = reset_control_assert(pcie_ep->core_reset);
199 if (ret) {
200 dev_err(dev, "Cannot assert core reset\n");
201 return ret;
202 }
203
204 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
205
206 ret = reset_control_deassert(pcie_ep->core_reset);
207 if (ret) {
208 dev_err(dev, "Cannot de-assert core reset\n");
209 return ret;
210 }
211
212 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
213
214 return 0;
215}
216
217/*
218 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
219 * device reset during host reboot and hibernation. The driver is
220 * expected to handle this situation.
221 */
222static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
223{
224 if (pcie_ep->perst_map) {
225 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
226 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
227 }
228}
229
230static int qcom_pcie_dw_link_up(struct dw_pcie *pci)
231{
232 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
233 u32 reg;
234
235 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);
236
237 return reg & XMLH_LINK_UP;
238}
239
240static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
241{
242 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
243
244 enable_irq(pcie_ep->perst_irq);
245
246 return 0;
247}
248
249static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
250{
251 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
252
253 disable_irq(pcie_ep->perst_irq);
254}
255
256static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
257{
258 int ret;
259
260 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
261 if (ret)
262 return ret;
263
264 ret = qcom_pcie_ep_core_reset(pcie_ep);
265 if (ret)
266 goto err_disable_clk;
267
268 ret = phy_init(pcie_ep->phy);
269 if (ret)
270 goto err_disable_clk;
271
272 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);
273 if (ret)
274 goto err_phy_exit;
275
276 ret = phy_power_on(pcie_ep->phy);
277 if (ret)
278 goto err_phy_exit;
279
280 return 0;
281
282err_phy_exit:
283 phy_exit(pcie_ep->phy);
284err_disable_clk:
285 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
286
287 return ret;
288}
289
290static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
291{
292 phy_power_off(pcie_ep->phy);
293 phy_exit(pcie_ep->phy);
294 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
295}
296
297static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
298{
299 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
300 struct device *dev = pci->dev;
301 u32 val, offset;
302 int ret;
303
304 ret = qcom_pcie_enable_resources(pcie_ep);
305 if (ret) {
306 dev_err(dev, "Failed to enable resources: %d\n", ret);
307 return ret;
308 }
309
310 /* Assert WAKE# to RC to indicate device is ready */
311 gpiod_set_value_cansleep(pcie_ep->wake, 1);
312 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
313 gpiod_set_value_cansleep(pcie_ep->wake, 0);
314
315 qcom_pcie_ep_configure_tcsr(pcie_ep);
316
317 /* Disable BDF to SID mapping */
318 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
319 val |= PARF_BDF_TO_SID_BYPASS;
320 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
321
322 /* Enable debug IRQ */
323 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
324 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
325 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
326 PARF_DEBUG_INT_PM_DSTATE_CHANGE;
327 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
328
329 /* Configure PCIe to endpoint mode */
330 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
331
332 /* Allow entering L1 state */
333 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
334 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
335 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
336
337 /* Read halts write */
338 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
339 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
340 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
341
342 /* Write after write halt */
343 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
344 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
345 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
346
347 /* Q2A flush disable */
348 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
349 val &= ~PARF_Q2A_FLUSH_EN;
350 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
351
352 /*
353 * Disable Master AXI clock during idle. Do not allow DBI access
354 * to take the core out of L1. Disable core clock gating that
355 * gates PIPE clock from propagating to core clock. Report to the
356 * host that Vaux is present.
357 */
358 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
359 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
360 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
361 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
362 PARF_SYS_CTRL_AUX_PWR_DET;
363 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
364
365 /* Disable the debouncers */
366 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
367 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
368 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
369 PARF_DB_CTRL_MST_WKP_BLOCK;
370 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
371
372 /* Request to exit from L1SS for MSI and LTR MSG */
373 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
374 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
375 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
376
377 dw_pcie_dbi_ro_wr_en(pci);
378
379 /* Set the L0s Exit Latency to 2us-4us = 0x6 */
380 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
381 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
382 val &= ~PCI_EXP_LNKCAP_L0SEL;
383 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
384 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
385
386 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
387 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
388 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
389 val &= ~PCI_EXP_LNKCAP_L1EL;
390 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
391 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
392
393 dw_pcie_dbi_ro_wr_dis(pci);
394
395 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
396 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
397 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
398 PARF_INT_ALL_LINK_UP;
399 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
400
401 ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep);
402 if (ret) {
403 dev_err(dev, "Failed to complete initialization: %d\n", ret);
404 goto err_disable_resources;
405 }
406
407 /*
408 * The physical address of the MMIO region which is exposed as the BAR
409 * should be written to MHI BASE registers.
410 */
411 writel_relaxed(pcie_ep->mmio_res->start,
412 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
413 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
414
415 /* Gate Master AXI clock to MHI bus during L1SS */
416 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
417 val &= ~PARF_MSTR_AXI_CLK_EN;
418 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
419
420 dw_pcie_ep_init_notify(&pcie_ep->pci.ep);
421
422 /* Enable LTSSM */
423 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
424 val |= BIT(8);
425 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
426
427 return 0;
428
429err_disable_resources:
430 qcom_pcie_disable_resources(pcie_ep);
431
432 return ret;
433}
434
435static void qcom_pcie_perst_assert(struct dw_pcie *pci)
436{
437 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
438 struct device *dev = pci->dev;
439
440 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED) {
441 dev_dbg(dev, "Link is already disabled\n");
442 return;
443 }
444
445 qcom_pcie_disable_resources(pcie_ep);
446 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
447}
448
449/* Common DWC controller ops */
450static const struct dw_pcie_ops pci_ops = {
451 .link_up = qcom_pcie_dw_link_up,
452 .start_link = qcom_pcie_dw_start_link,
453 .stop_link = qcom_pcie_dw_stop_link,
454};
455
456static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
457 struct qcom_pcie_ep *pcie_ep)
458{
459 struct device *dev = &pdev->dev;
460 struct dw_pcie *pci = &pcie_ep->pci;
461 struct device_node *syscon;
462 struct resource *res;
463 int ret;
464
465 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
466 if (IS_ERR(pcie_ep->parf))
467 return PTR_ERR(pcie_ep->parf);
468
469 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
470 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
471 if (IS_ERR(pci->dbi_base))
472 return PTR_ERR(pci->dbi_base);
473 pci->dbi_base2 = pci->dbi_base;
474
475 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
476 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);
477 if (IS_ERR(pcie_ep->elbi))
478 return PTR_ERR(pcie_ep->elbi);
479
480 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
481 "mmio");
482 if (!pcie_ep->mmio_res) {
483 dev_err(dev, "Failed to get mmio resource\n");
484 return -EINVAL;
485 }
486
487 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
488 if (IS_ERR(pcie_ep->mmio))
489 return PTR_ERR(pcie_ep->mmio);
490
491 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
492 if (!syscon) {
493 dev_dbg(dev, "PERST separation not available\n");
494 return 0;
495 }
496
497 pcie_ep->perst_map = syscon_node_to_regmap(syscon);
498 of_node_put(syscon);
499 if (IS_ERR(pcie_ep->perst_map))
500 return PTR_ERR(pcie_ep->perst_map);
501
502 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
503 1, &pcie_ep->perst_en);
504 if (ret < 0) {
505 dev_err(dev, "No Perst Enable offset in syscon\n");
506 return ret;
507 }
508
509 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
510 2, &pcie_ep->perst_sep_en);
511 if (ret < 0) {
512 dev_err(dev, "No Perst Separation Enable offset in syscon\n");
513 return ret;
514 }
515
516 return 0;
517}
518
519static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
520 struct qcom_pcie_ep *pcie_ep)
521{
522 struct device *dev = &pdev->dev;
523 int ret;
524
525 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
526 if (ret) {
527 dev_err(dev, "Failed to get io resources %d\n", ret);
528 return ret;
529 }
530
531 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
532 if (pcie_ep->num_clks < 0) {
533 dev_err(dev, "Failed to get clocks\n");
534 return pcie_ep->num_clks;
535 }
536
537 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
538 if (IS_ERR(pcie_ep->core_reset))
539 return PTR_ERR(pcie_ep->core_reset);
540
541 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
542 if (IS_ERR(pcie_ep->reset))
543 return PTR_ERR(pcie_ep->reset);
544
545 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
546 if (IS_ERR(pcie_ep->wake))
547 return PTR_ERR(pcie_ep->wake);
548
549 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
550 if (IS_ERR(pcie_ep->phy))
551 ret = PTR_ERR(pcie_ep->phy);
552
553 return ret;
554}
555
556/* TODO: Notify clients about PCIe state change */
557static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
558{
559 struct qcom_pcie_ep *pcie_ep = data;
560 struct dw_pcie *pci = &pcie_ep->pci;
561 struct device *dev = pci->dev;
562 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
563 u32 mask = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_MASK);
564 u32 dstate, val;
565
566 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
567 status &= mask;
568
569 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
570 dev_dbg(dev, "Received Linkdown event\n");
571 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
572 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
573 dev_dbg(dev, "Received BME event. Link is enabled!\n");
574 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
575 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
576 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
577 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
578 val |= PARF_PM_CTRL_READY_ENTR_L23;
579 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
580 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
581 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
582 DBI_CON_STATUS_POWER_STATE_MASK;
583 dev_dbg(dev, "Received D%d state event\n", dstate);
584 if (dstate == 3) {
585 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
586 val |= PARF_PM_CTRL_REQ_EXIT_L1;
587 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
588 }
589 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
590 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
591 dw_pcie_ep_linkup(&pci->ep);
592 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
593 } else {
594 dev_dbg(dev, "Received unknown event: %d\n", status);
595 }
596
597 return IRQ_HANDLED;
598}
599
600static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
601{
602 struct qcom_pcie_ep *pcie_ep = data;
603 struct dw_pcie *pci = &pcie_ep->pci;
604 struct device *dev = pci->dev;
605 u32 perst;
606
607 perst = gpiod_get_value(pcie_ep->reset);
608 if (perst) {
609 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
610 qcom_pcie_perst_assert(pci);
611 } else {
612 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
613 qcom_pcie_perst_deassert(pci);
614 }
615
616 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
617 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
618
619 return IRQ_HANDLED;
620}
621
622static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
623 struct qcom_pcie_ep *pcie_ep)
624{
625 int ret;
626
627 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
628 if (pcie_ep->global_irq < 0)
629 return pcie_ep->global_irq;
630
631 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
632 qcom_pcie_ep_global_irq_thread,
633 IRQF_ONESHOT,
634 "global_irq", pcie_ep);
635 if (ret) {
636 dev_err(&pdev->dev, "Failed to request Global IRQ\n");
637 return ret;
638 }
639
640 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
641 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
642 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
643 qcom_pcie_ep_perst_irq_thread,
644 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
645 "perst_irq", pcie_ep);
646 if (ret) {
647 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
648 disable_irq(pcie_ep->global_irq);
649 return ret;
650 }
651
652 return 0;
653}
654
655static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
656 enum pci_epc_irq_type type, u16 interrupt_num)
657{
658 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
659
660 switch (type) {
661 case PCI_EPC_IRQ_LEGACY:
662 return dw_pcie_ep_raise_legacy_irq(ep, func_no);
663 case PCI_EPC_IRQ_MSI:
664 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
665 default:
666 dev_err(pci->dev, "Unknown IRQ type\n");
667 return -EINVAL;
668 }
669}
670
671static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
672{
673 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)
674 dev_get_drvdata(s->private);
675
676 seq_printf(s, "L0s transition count: %u\n",
677 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
678
679 seq_printf(s, "L1 transition count: %u\n",
680 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
681
682 seq_printf(s, "L1.1 transition count: %u\n",
683 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
684
685 seq_printf(s, "L1.2 transition count: %u\n",
686 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
687
688 seq_printf(s, "L2 transition count: %u\n",
689 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
690
691 return 0;
692}
693
694static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
695{
696 struct dw_pcie *pci = &pcie_ep->pci;
697
698 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,
699 qcom_pcie_ep_link_transition_count);
700}
701
702static const struct pci_epc_features qcom_pcie_epc_features = {
703 .linkup_notifier = true,
704 .core_init_notifier = true,
705 .msi_capable = true,
706 .msix_capable = false,
707};
708
709static const struct pci_epc_features *
710qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
711{
712 return &qcom_pcie_epc_features;
713}
714
715static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
716{
717 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
718 enum pci_barno bar;
719
720 for (bar = BAR_0; bar <= BAR_5; bar++)
721 dw_pcie_ep_reset_bar(pci, bar);
722}
723
724static const struct dw_pcie_ep_ops pci_ep_ops = {
725 .ep_init = qcom_pcie_ep_init,
726 .raise_irq = qcom_pcie_ep_raise_irq,
727 .get_features = qcom_pcie_epc_get_features,
728};
729
730static int qcom_pcie_ep_probe(struct platform_device *pdev)
731{
732 struct device *dev = &pdev->dev;
733 struct qcom_pcie_ep *pcie_ep;
734 char *name;
735 int ret;
736
737 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
738 if (!pcie_ep)
739 return -ENOMEM;
740
741 pcie_ep->pci.dev = dev;
742 pcie_ep->pci.ops = &pci_ops;
743 pcie_ep->pci.ep.ops = &pci_ep_ops;
744 platform_set_drvdata(pdev, pcie_ep);
745
746 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
747 if (ret)
748 return ret;
749
750 ret = qcom_pcie_enable_resources(pcie_ep);
751 if (ret) {
752 dev_err(dev, "Failed to enable resources: %d\n", ret);
753 return ret;
754 }
755
756 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
757 if (ret) {
758 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
759 goto err_disable_resources;
760 }
761
762 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
763 if (ret)
764 goto err_disable_resources;
765
766 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
767 if (!name) {
768 ret = -ENOMEM;
769 goto err_disable_irqs;
770 }
771
772 pcie_ep->debugfs = debugfs_create_dir(name, NULL);
773 qcom_pcie_ep_init_debugfs(pcie_ep);
774
775 return 0;
776
777err_disable_irqs:
778 disable_irq(pcie_ep->global_irq);
779 disable_irq(pcie_ep->perst_irq);
780
781err_disable_resources:
782 qcom_pcie_disable_resources(pcie_ep);
783
784 return ret;
785}
786
787static int qcom_pcie_ep_remove(struct platform_device *pdev)
788{
789 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
790
791 disable_irq(pcie_ep->global_irq);
792 disable_irq(pcie_ep->perst_irq);
793
794 debugfs_remove_recursive(pcie_ep->debugfs);
795
796 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
797 return 0;
798
799 qcom_pcie_disable_resources(pcie_ep);
800
801 return 0;
802}
803
804static const struct of_device_id qcom_pcie_ep_match[] = {
805 { .compatible = "qcom,sdx55-pcie-ep", },
806 { .compatible = "qcom,sm8450-pcie-ep", },
807 { }
808};
809MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
810
811static struct platform_driver qcom_pcie_ep_driver = {
812 .probe = qcom_pcie_ep_probe,
813 .remove = qcom_pcie_ep_remove,
814 .driver = {
815 .name = "qcom-pcie-ep",
816 .of_match_table = qcom_pcie_ep_match,
817 },
818};
819builtin_platform_driver(qcom_pcie_ep_driver);
820
821MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
822MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
823MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
824MODULE_LICENSE("GPL v2");