1// SPDX-License-Identifier: GPL-2.0-only
  2// Copyright (C) 2016 Broadcom
  3
  4#include <linux/acpi.h>
  5#include <linux/delay.h>
  6#include <linux/device.h>
  7#include <linux/io.h>
  8#include <linux/module.h>
  9#include <linux/nvmem-provider.h>
 10#include <linux/of.h>
 11#include <linux/of_device.h>
 12#include <linux/platform_device.h>
 13
 14/*
 15 * # of tries for OTP Status. The time to execute a command varies. The slowest
 16 * commands are writes which also vary based on the # of bits turned on. Writing
 17 * 0xffffffff takes ~3800 us.
 18 */
 19#define OTPC_RETRIES                 5000
 20
 21/* Sequence to enable OTP program */
 22#define OTPC_PROG_EN_SEQ             { 0xf, 0x4, 0x8, 0xd }
 23
 24/* OTPC Commands */
 25#define OTPC_CMD_READ                0x0
 26#define OTPC_CMD_OTP_PROG_ENABLE     0x2
 27#define OTPC_CMD_OTP_PROG_DISABLE    0x3
 28#define OTPC_CMD_PROGRAM             0x8
 29
 30/* OTPC Status Bits */
 31#define OTPC_STAT_CMD_DONE           BIT(1)
 32#define OTPC_STAT_PROG_OK            BIT(2)
 33
 34/* OTPC register definition */
 35#define OTPC_MODE_REG_OFFSET         0x0
 36#define OTPC_MODE_REG_OTPC_MODE      0
 37#define OTPC_COMMAND_OFFSET          0x4
 38#define OTPC_COMMAND_COMMAND_WIDTH   6
 39#define OTPC_CMD_START_OFFSET        0x8
 40#define OTPC_CMD_START_START         0
 41#define OTPC_CPU_STATUS_OFFSET       0xc
 42#define OTPC_CPUADDR_REG_OFFSET      0x28
 43#define OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH 16
 44#define OTPC_CPU_WRITE_REG_OFFSET    0x2c
 45
 46#define OTPC_CMD_MASK  (BIT(OTPC_COMMAND_COMMAND_WIDTH) - 1)
 47#define OTPC_ADDR_MASK (BIT(OTPC_CPUADDR_REG_OTPC_CPU_ADDRESS_WIDTH) - 1)
 48
 49
 50struct otpc_map {
 51	/* in words. */
 52	u32 otpc_row_size;
 53	/* 128 bit row / 4 words support. */
 54	u16 data_r_offset[4];
 55	/* 128 bit row / 4 words support. */
 56	u16 data_w_offset[4];
 57};
 58
 59static struct otpc_map otp_map = {
 60	.otpc_row_size = 1,
 61	.data_r_offset = {0x10},
 62	.data_w_offset = {0x2c},
 63};
 64
 65static struct otpc_map otp_map_v2 = {
 66	.otpc_row_size = 2,
 67	.data_r_offset = {0x10, 0x5c},
 68	.data_w_offset = {0x2c, 0x64},
 69};
 70
 71struct otpc_priv {
 72	struct device *dev;
 73	void __iomem *base;
 74	const struct otpc_map *map;
 75	struct nvmem_config *config;
 76};
 77
 78static inline void set_command(void __iomem *base, u32 command)
 79{
 80	writel(command & OTPC_CMD_MASK, base + OTPC_COMMAND_OFFSET);
 81}
 82
 83static inline void set_cpu_address(void __iomem *base, u32 addr)
 84{
 85	writel(addr & OTPC_ADDR_MASK, base + OTPC_CPUADDR_REG_OFFSET);
 86}
 87
 88static inline void set_start_bit(void __iomem *base)
 89{
 90	writel(1 << OTPC_CMD_START_START, base + OTPC_CMD_START_OFFSET);
 91}
 92
 93static inline void reset_start_bit(void __iomem *base)
 94{
 95	writel(0, base + OTPC_CMD_START_OFFSET);
 96}
 97
 98static inline void write_cpu_data(void __iomem *base, u32 value)
 99{
100	writel(value, base + OTPC_CPU_WRITE_REG_OFFSET);
101}
102
103static int poll_cpu_status(void __iomem *base, u32 value)
104{
105	u32 status;
106	u32 retries;
107
108	for (retries = 0; retries < OTPC_RETRIES; retries++) {
109		status = readl(base + OTPC_CPU_STATUS_OFFSET);
110		if (status & value)
111			break;
112		udelay(1);
113	}
114	if (retries == OTPC_RETRIES)
115		return -EAGAIN;
116
117	return 0;
118}
119
120static int enable_ocotp_program(void __iomem *base)
121{
122	static const u32 vals[] = OTPC_PROG_EN_SEQ;
123	int i;
124	int ret;
125
126	/* Write the magic sequence to enable programming */
127	set_command(base, OTPC_CMD_OTP_PROG_ENABLE);
128	for (i = 0; i < ARRAY_SIZE(vals); i++) {
129		write_cpu_data(base, vals[i]);
130		set_start_bit(base);
131		ret = poll_cpu_status(base, OTPC_STAT_CMD_DONE);
132		reset_start_bit(base);
133		if (ret)
134			return ret;
135	}
136
137	return poll_cpu_status(base, OTPC_STAT_PROG_OK);
138}
139
140static int disable_ocotp_program(void __iomem *base)
141{
142	int ret;
143
144	set_command(base, OTPC_CMD_OTP_PROG_DISABLE);
145	set_start_bit(base);
146	ret = poll_cpu_status(base, OTPC_STAT_PROG_OK);
147	reset_start_bit(base);
148
149	return ret;
150}
151
152static int bcm_otpc_read(void *context, unsigned int offset, void *val,
153	size_t bytes)
154{
155	struct otpc_priv *priv = context;
156	u32 *buf = val;
157	u32 bytes_read;
158	u32 address = offset / priv->config->word_size;
159	int i, ret;
160
161	for (bytes_read = 0; bytes_read < bytes;) {
162		set_command(priv->base, OTPC_CMD_READ);
163		set_cpu_address(priv->base, address++);
164		set_start_bit(priv->base);
165		ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
166		if (ret) {
167			dev_err(priv->dev, "otp read error: 0x%x", ret);
168			return -EIO;
169		}
170
171		for (i = 0; i < priv->map->otpc_row_size; i++) {
172			*buf++ = readl(priv->base +
173					priv->map->data_r_offset[i]);
174			bytes_read += sizeof(*buf);
175		}
176
177		reset_start_bit(priv->base);
178	}
179
180	return 0;
181}
182
183static int bcm_otpc_write(void *context, unsigned int offset, void *val,
184	size_t bytes)
185{
186	struct otpc_priv *priv = context;
187	u32 *buf = val;
188	u32 bytes_written;
189	u32 address = offset / priv->config->word_size;
190	int i, ret;
191
192	if (offset % priv->config->word_size)
193		return -EINVAL;
194
195	ret = enable_ocotp_program(priv->base);
196	if (ret)
197		return -EIO;
198
199	for (bytes_written = 0; bytes_written < bytes;) {
200		set_command(priv->base, OTPC_CMD_PROGRAM);
201		set_cpu_address(priv->base, address++);
202		for (i = 0; i < priv->map->otpc_row_size; i++) {
203			writel(*buf, priv->base + priv->map->data_w_offset[i]);
204			buf++;
205			bytes_written += sizeof(*buf);
206		}
207		set_start_bit(priv->base);
208		ret = poll_cpu_status(priv->base, OTPC_STAT_CMD_DONE);
209		reset_start_bit(priv->base);
210		if (ret) {
211			dev_err(priv->dev, "otp write error: 0x%x", ret);
212			return -EIO;
213		}
214	}
215
216	disable_ocotp_program(priv->base);
217
218	return 0;
219}
220
221static struct nvmem_config bcm_otpc_nvmem_config = {
222	.name = "bcm-ocotp",
223	.read_only = false,
224	.word_size = 4,
225	.stride = 4,
226	.reg_read = bcm_otpc_read,
227	.reg_write = bcm_otpc_write,
228};
229
230static const struct of_device_id bcm_otpc_dt_ids[] = {
231	{ .compatible = "brcm,ocotp", .data = &otp_map },
232	{ .compatible = "brcm,ocotp-v2", .data = &otp_map_v2 },
233	{ },
234};
235MODULE_DEVICE_TABLE(of, bcm_otpc_dt_ids);
236
237static const struct acpi_device_id bcm_otpc_acpi_ids[] __maybe_unused = {
238	{ .id = "BRCM0700", .driver_data = (kernel_ulong_t)&otp_map },
239	{ .id = "BRCM0701", .driver_data = (kernel_ulong_t)&otp_map_v2 },
240	{ /* sentinel */ }
241};
242MODULE_DEVICE_TABLE(acpi, bcm_otpc_acpi_ids);
243
244static int bcm_otpc_probe(struct platform_device *pdev)
245{
246	struct device *dev = &pdev->dev;
247	struct resource *res;
248	struct otpc_priv *priv;
249	struct nvmem_device *nvmem;
250	int err;
251	u32 num_words;
252
253	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
254	if (!priv)
255		return -ENOMEM;
256
257	priv->map = device_get_match_data(dev);
258	if (!priv->map)
259		return -ENODEV;
260
261	/* Get OTP base address register. */
262	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
263	priv->base = devm_ioremap_resource(dev, res);
264	if (IS_ERR(priv->base)) {
265		dev_err(dev, "unable to map I/O memory\n");
266		return PTR_ERR(priv->base);
267	}
268
269	/* Enable CPU access to OTPC. */
270	writel(readl(priv->base + OTPC_MODE_REG_OFFSET) |
271		BIT(OTPC_MODE_REG_OTPC_MODE),
272		priv->base + OTPC_MODE_REG_OFFSET);
273	reset_start_bit(priv->base);
274
275	/* Read size of memory in words. */
276	err = device_property_read_u32(dev, "brcm,ocotp-size", &num_words);
277	if (err) {
278		dev_err(dev, "size parameter not specified\n");
279		return -EINVAL;
280	} else if (num_words == 0) {
281		dev_err(dev, "size must be > 0\n");
282		return -EINVAL;
283	}
284
285	bcm_otpc_nvmem_config.size = 4 * num_words;
286	bcm_otpc_nvmem_config.dev = dev;
287	bcm_otpc_nvmem_config.priv = priv;
288
289	if (priv->map == &otp_map_v2) {
290		bcm_otpc_nvmem_config.word_size = 8;
291		bcm_otpc_nvmem_config.stride = 8;
292	}
293
294	priv->config = &bcm_otpc_nvmem_config;
295
296	nvmem = devm_nvmem_register(dev, &bcm_otpc_nvmem_config);
297	if (IS_ERR(nvmem)) {
298		dev_err(dev, "error registering nvmem config\n");
299		return PTR_ERR(nvmem);
300	}
301
302	return 0;
303}
304
305static struct platform_driver bcm_otpc_driver = {
306	.probe	= bcm_otpc_probe,
307	.driver = {
308		.name	= "brcm-otpc",
309		.of_match_table = bcm_otpc_dt_ids,
310		.acpi_match_table = ACPI_PTR(bcm_otpc_acpi_ids),
311	},
312};
313module_platform_driver(bcm_otpc_driver);
314
315MODULE_DESCRIPTION("Broadcom OTPC driver");
316MODULE_LICENSE("GPL v2");