1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
 2/* Copyright(c) 2019-2022  Realtek Corporation
 3 */
 4
 5#ifndef __RTW89_8852C_H__
 6#define __RTW89_8852C_H__
 7
 8#include "core.h"
 9
10#define RF_PATH_NUM_8852C 2
11#define BB_PATH_NUM_8852C 2
12
13struct rtw8852c_u_efuse {
14	u8 rsvd[0x38];
15	u8 mac_addr[ETH_ALEN];
16};
17
18struct rtw8852c_e_efuse {
19	u8 mac_addr[ETH_ALEN];
20};
21
22struct rtw8852c_tssi_offset {
23	u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM];
24	u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM];
25	u8 rsvd[7];
26	u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM];
27} __packed;
28
29struct rtw8852c_efuse {
30	u8 rsvd[0x210];
31	struct rtw8852c_tssi_offset path_a_tssi;
32	u8 rsvd1[10];
33	struct rtw8852c_tssi_offset path_b_tssi;
34	u8 rsvd2[94];
35	u8 channel_plan;
36	u8 xtal_k;
37	u8 rsvd3;
38	u8 iqk_lck;
39	u8 rsvd4[5];
40	u8 reg_setting:2;
41	u8 tx_diversity:1;
42	u8 rx_diversity:2;
43	u8 ac_mode:1;
44	u8 module_type:2;
45	u8 rsvd5;
46	u8 shared_ant:1;
47	u8 coex_type:3;
48	u8 ant_iso:1;
49	u8 radio_on_off:1;
50	u8 rsvd6:2;
51	u8 eeprom_version;
52	u8 customer_id;
53	u8 tx_bb_swing_2g;
54	u8 tx_bb_swing_5g;
55	u8 tx_cali_pwr_trk_mode;
56	u8 trx_path_selection;
57	u8 rfe_type;
58	u8 country_code[2];
59	u8 rsvd7[3];
60	u8 path_a_therm;
61	u8 path_b_therm;
62	u8 rsvd8[2];
63	u8 rx_gain_2g_ofdm;
64	u8 rsvd9;
65	u8 rx_gain_2g_cck;
66	u8 rsvd10;
67	u8 rx_gain_5g_low;
68	u8 rsvd11;
69	u8 rx_gain_5g_mid;
70	u8 rsvd12;
71	u8 rx_gain_5g_high;
72	u8 rsvd13[35];
73	u8 bw40_1s_tssi_6g_a[TSSI_MCS_6G_CH_GROUP_NUM];
74	u8 rsvd14[10];
75	u8 bw40_1s_tssi_6g_b[TSSI_MCS_6G_CH_GROUP_NUM];
76	u8 rsvd15[110];
77	u8 channel_plan_6g;
78	u8 rsvd16[71];
79	union {
80		struct rtw8852c_u_efuse u;
81		struct rtw8852c_e_efuse e;
82	};
83} __packed;
84
85extern const struct rtw89_chip_info rtw8852c_chip_info;
86
87#endif