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1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2/* Copyright(c) 2019-2022 Realtek Corporation
3 */
4
5#include "coex.h"
6#include "fw.h"
7#include "mac.h"
8#include "phy.h"
9#include "reg.h"
10#include "rtw8852b.h"
11#include "rtw8852b_rfk.h"
12#include "rtw8852b_table.h"
13#include "txrx.h"
14
15static const struct rtw89_hfc_ch_cfg rtw8852b_hfc_chcfg_pcie[] = {
16 {5, 343, grp_0}, /* ACH 0 */
17 {5, 343, grp_0}, /* ACH 1 */
18 {5, 343, grp_0}, /* ACH 2 */
19 {5, 343, grp_0}, /* ACH 3 */
20 {0, 0, grp_0}, /* ACH 4 */
21 {0, 0, grp_0}, /* ACH 5 */
22 {0, 0, grp_0}, /* ACH 6 */
23 {0, 0, grp_0}, /* ACH 7 */
24 {4, 344, grp_0}, /* B0MGQ */
25 {4, 344, grp_0}, /* B0HIQ */
26 {0, 0, grp_0}, /* B1MGQ */
27 {0, 0, grp_0}, /* B1HIQ */
28 {40, 0, 0} /* FWCMDQ */
29};
30
31static const struct rtw89_hfc_pub_cfg rtw8852b_hfc_pubcfg_pcie = {
32 448, /* Group 0 */
33 0, /* Group 1 */
34 448, /* Public Max */
35 0 /* WP threshold */
36};
37
38static const struct rtw89_hfc_param_ini rtw8852b_hfc_param_ini_pcie[] = {
39 [RTW89_QTA_SCC] = {rtw8852b_hfc_chcfg_pcie, &rtw8852b_hfc_pubcfg_pcie,
40 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH},
41 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie,
42 RTW89_HCIFC_POH},
43 [RTW89_QTA_INVALID] = {NULL},
44};
45
46static const struct rtw89_dle_mem rtw8852b_dle_mem_pcie[] = {
47 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size6,
48 &rtw89_mac_size.ple_size6, &rtw89_mac_size.wde_qt6,
49 &rtw89_mac_size.wde_qt6, &rtw89_mac_size.ple_qt18,
50 &rtw89_mac_size.ple_qt58},
51 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size9,
52 &rtw89_mac_size.ple_size8, &rtw89_mac_size.wde_qt4,
53 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13,
54 &rtw89_mac_size.ple_qt13},
55 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL,
56 NULL},
57};
58
59static const struct rtw89_reg3_def rtw8852b_pmac_ht20_mcs7_tbl[] = {
60 {0x4580, 0x0000ffff, 0x0},
61 {0x4580, 0xffff0000, 0x0},
62 {0x4584, 0x0000ffff, 0x0},
63 {0x4584, 0xffff0000, 0x0},
64 {0x4580, 0x0000ffff, 0x1},
65 {0x4578, 0x00ffffff, 0x2018b},
66 {0x4570, 0x03ffffff, 0x7},
67 {0x4574, 0x03ffffff, 0x32407},
68 {0x45b8, 0x00000010, 0x0},
69 {0x45b8, 0x00000100, 0x0},
70 {0x45b8, 0x00000080, 0x0},
71 {0x45b8, 0x00000008, 0x0},
72 {0x45a0, 0x0000ff00, 0x0},
73 {0x45a0, 0xff000000, 0x1},
74 {0x45a4, 0x0000ff00, 0x2},
75 {0x45a4, 0xff000000, 0x3},
76 {0x45b8, 0x00000020, 0x0},
77 {0x4568, 0xe0000000, 0x0},
78 {0x45b8, 0x00000002, 0x1},
79 {0x456c, 0xe0000000, 0x0},
80 {0x45b4, 0x00006000, 0x0},
81 {0x45b4, 0x00001800, 0x1},
82 {0x45b8, 0x00000040, 0x0},
83 {0x45b8, 0x00000004, 0x0},
84 {0x45b8, 0x00000200, 0x0},
85 {0x4598, 0xf8000000, 0x0},
86 {0x45b8, 0x00100000, 0x0},
87 {0x45a8, 0x00000fc0, 0x0},
88 {0x45b8, 0x00200000, 0x0},
89 {0x45b0, 0x00000038, 0x0},
90 {0x45b0, 0x000001c0, 0x0},
91 {0x45a0, 0x000000ff, 0x0},
92 {0x45b8, 0x00400000, 0x0},
93 {0x4590, 0x000007ff, 0x0},
94 {0x45b0, 0x00000e00, 0x0},
95 {0x45ac, 0x0000001f, 0x0},
96 {0x45b8, 0x00800000, 0x0},
97 {0x45a8, 0x0003f000, 0x0},
98 {0x45b8, 0x01000000, 0x0},
99 {0x45b0, 0x00007000, 0x0},
100 {0x45b0, 0x00038000, 0x0},
101 {0x45a0, 0x00ff0000, 0x0},
102 {0x45b8, 0x02000000, 0x0},
103 {0x4590, 0x003ff800, 0x0},
104 {0x45b0, 0x001c0000, 0x0},
105 {0x45ac, 0x000003e0, 0x0},
106 {0x45b8, 0x04000000, 0x0},
107 {0x45a8, 0x00fc0000, 0x0},
108 {0x45b8, 0x08000000, 0x0},
109 {0x45b0, 0x00e00000, 0x0},
110 {0x45b0, 0x07000000, 0x0},
111 {0x45a4, 0x000000ff, 0x0},
112 {0x45b8, 0x10000000, 0x0},
113 {0x4594, 0x000007ff, 0x0},
114 {0x45b0, 0x38000000, 0x0},
115 {0x45ac, 0x00007c00, 0x0},
116 {0x45b8, 0x20000000, 0x0},
117 {0x45a8, 0x3f000000, 0x0},
118 {0x45b8, 0x40000000, 0x0},
119 {0x45b4, 0x00000007, 0x0},
120 {0x45b4, 0x00000038, 0x0},
121 {0x45a4, 0x00ff0000, 0x0},
122 {0x45b8, 0x80000000, 0x0},
123 {0x4594, 0x003ff800, 0x0},
124 {0x45b4, 0x000001c0, 0x0},
125 {0x4598, 0xf8000000, 0x0},
126 {0x45b8, 0x00100000, 0x0},
127 {0x45a8, 0x00000fc0, 0x7},
128 {0x45b8, 0x00200000, 0x0},
129 {0x45b0, 0x00000038, 0x0},
130 {0x45b0, 0x000001c0, 0x0},
131 {0x45a0, 0x000000ff, 0x0},
132 {0x45b4, 0x06000000, 0x0},
133 {0x45b0, 0x00000007, 0x0},
134 {0x45b8, 0x00080000, 0x0},
135 {0x45a8, 0x0000003f, 0x0},
136 {0x457c, 0xffe00000, 0x1},
137 {0x4530, 0xffffffff, 0x0},
138 {0x4588, 0x00003fff, 0x0},
139 {0x4598, 0x000001ff, 0x0},
140 {0x4534, 0xffffffff, 0x0},
141 {0x4538, 0xffffffff, 0x0},
142 {0x453c, 0xffffffff, 0x0},
143 {0x4588, 0x0fffc000, 0x0},
144 {0x4598, 0x0003fe00, 0x0},
145 {0x4540, 0xffffffff, 0x0},
146 {0x4544, 0xffffffff, 0x0},
147 {0x4548, 0xffffffff, 0x0},
148 {0x458c, 0x00003fff, 0x0},
149 {0x4598, 0x07fc0000, 0x0},
150 {0x454c, 0xffffffff, 0x0},
151 {0x4550, 0xffffffff, 0x0},
152 {0x4554, 0xffffffff, 0x0},
153 {0x458c, 0x0fffc000, 0x0},
154 {0x459c, 0x000001ff, 0x0},
155 {0x4558, 0xffffffff, 0x0},
156 {0x455c, 0xffffffff, 0x0},
157 {0x4530, 0xffffffff, 0x4e790001},
158 {0x4588, 0x00003fff, 0x0},
159 {0x4598, 0x000001ff, 0x1},
160 {0x4534, 0xffffffff, 0x0},
161 {0x4538, 0xffffffff, 0x4b},
162 {0x45ac, 0x38000000, 0x7},
163 {0x4588, 0xf0000000, 0x0},
164 {0x459c, 0x7e000000, 0x0},
165 {0x45b8, 0x00040000, 0x0},
166 {0x45b8, 0x00020000, 0x0},
167 {0x4590, 0xffc00000, 0x0},
168 {0x45b8, 0x00004000, 0x0},
169 {0x4578, 0xff000000, 0x0},
170 {0x45b8, 0x00000400, 0x0},
171 {0x45b8, 0x00000800, 0x0},
172 {0x45b8, 0x00001000, 0x0},
173 {0x45b8, 0x00002000, 0x0},
174 {0x45b4, 0x00018000, 0x0},
175 {0x45ac, 0x07800000, 0x0},
176 {0x45b4, 0x00000600, 0x2},
177 {0x459c, 0x0001fe00, 0x80},
178 {0x45ac, 0x00078000, 0x3},
179 {0x459c, 0x01fe0000, 0x1},
180};
181
182static const struct rtw89_reg3_def rtw8852b_btc_preagc_en_defs[] = {
183 {0x46D0, GENMASK(1, 0), 0x3},
184 {0x4790, GENMASK(1, 0), 0x3},
185 {0x4AD4, GENMASK(31, 0), 0xf},
186 {0x4AE0, GENMASK(31, 0), 0xf},
187 {0x4688, GENMASK(31, 24), 0x80},
188 {0x476C, GENMASK(31, 24), 0x80},
189 {0x4694, GENMASK(7, 0), 0x80},
190 {0x4694, GENMASK(15, 8), 0x80},
191 {0x4778, GENMASK(7, 0), 0x80},
192 {0x4778, GENMASK(15, 8), 0x80},
193 {0x4AE4, GENMASK(23, 0), 0x780D1E},
194 {0x4AEC, GENMASK(23, 0), 0x780D1E},
195 {0x469C, GENMASK(31, 26), 0x34},
196 {0x49F0, GENMASK(31, 26), 0x34},
197};
198
199static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_en_defs);
200
201static const struct rtw89_reg3_def rtw8852b_btc_preagc_dis_defs[] = {
202 {0x46D0, GENMASK(1, 0), 0x0},
203 {0x4790, GENMASK(1, 0), 0x0},
204 {0x4AD4, GENMASK(31, 0), 0x60},
205 {0x4AE0, GENMASK(31, 0), 0x60},
206 {0x4688, GENMASK(31, 24), 0x1a},
207 {0x476C, GENMASK(31, 24), 0x1a},
208 {0x4694, GENMASK(7, 0), 0x2a},
209 {0x4694, GENMASK(15, 8), 0x2a},
210 {0x4778, GENMASK(7, 0), 0x2a},
211 {0x4778, GENMASK(15, 8), 0x2a},
212 {0x4AE4, GENMASK(23, 0), 0x79E99E},
213 {0x4AEC, GENMASK(23, 0), 0x79E99E},
214 {0x469C, GENMASK(31, 26), 0x26},
215 {0x49F0, GENMASK(31, 26), 0x26},
216};
217
218static DECLARE_PHY_REG3_TBL(rtw8852b_btc_preagc_dis_defs);
219
220static const u32 rtw8852b_h2c_regs[RTW89_H2CREG_MAX] = {
221 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2,
222 R_AX_H2CREG_DATA3
223};
224
225static const u32 rtw8852b_c2h_regs[RTW89_C2HREG_MAX] = {
226 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2,
227 R_AX_C2HREG_DATA3
228};
229
230static const struct rtw89_page_regs rtw8852b_page_regs = {
231 .hci_fc_ctrl = R_AX_HCI_FC_CTRL,
232 .ch_page_ctrl = R_AX_CH_PAGE_CTRL,
233 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL,
234 .ach_page_info = R_AX_ACH0_PAGE_INFO,
235 .pub_page_info3 = R_AX_PUB_PAGE_INFO3,
236 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1,
237 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2,
238 .pub_page_info1 = R_AX_PUB_PAGE_INFO1,
239 .pub_page_info2 = R_AX_PUB_PAGE_INFO2,
240 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1,
241 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2,
242 .wp_page_info1 = R_AX_WP_PAGE_INFO1,
243};
244
245static const struct rtw89_reg_def rtw8852b_dcfo_comp = {
246 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK
247};
248
249static const struct rtw89_imr_info rtw8852b_imr_info = {
250 .wdrls_imr_set = B_AX_WDRLS_IMR_SET,
251 .wsec_imr_reg = R_AX_SEC_DEBUG,
252 .wsec_imr_set = B_AX_IMR_ERROR,
253 .mpdu_tx_imr_set = 0,
254 .mpdu_rx_imr_set = 0,
255 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET,
256 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR,
257 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR,
258 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET,
259 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1,
260 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR,
261 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET,
262 .wde_imr_clr = B_AX_WDE_IMR_CLR,
263 .wde_imr_set = B_AX_WDE_IMR_SET,
264 .ple_imr_clr = B_AX_PLE_IMR_CLR,
265 .ple_imr_set = B_AX_PLE_IMR_SET,
266 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR,
267 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET,
268 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR,
269 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET,
270 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR,
271 .other_disp_imr_set = 0,
272 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR,
273 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR,
274 .bbrpt_err_imr_set = 0,
275 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR,
276 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_ALL,
277 .ptcl_imr_set = B_AX_PTCL_IMR_SET,
278 .cdma_imr_0_reg = R_AX_DLE_CTRL,
279 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR,
280 .cdma_imr_0_set = B_AX_DLE_IMR_SET,
281 .cdma_imr_1_reg = 0,
282 .cdma_imr_1_clr = 0,
283 .cdma_imr_1_set = 0,
284 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR,
285 .phy_intf_imr_clr = 0,
286 .phy_intf_imr_set = 0,
287 .rmac_imr_reg = R_AX_RMAC_ERR_ISR,
288 .rmac_imr_clr = B_AX_RMAC_IMR_CLR,
289 .rmac_imr_set = B_AX_RMAC_IMR_SET,
290 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR,
291 .tmac_imr_clr = B_AX_TMAC_IMR_CLR,
292 .tmac_imr_set = B_AX_TMAC_IMR_SET,
293};
294
295static const struct rtw89_rrsr_cfgs rtw8852b_rrsr_cfgs = {
296 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
297 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
298};
299
300static const struct rtw89_dig_regs rtw8852b_dig_regs = {
301 .seg0_pd_reg = R_SEG0R_PD_V1,
302 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
303 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK_V1,
304 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK},
305 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK},
306 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1},
307 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1},
308 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1},
309 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1},
310 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V2,
311 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
312 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V2,
313 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
314 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V2,
315 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK},
316 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V2,
317 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK},
318};
319
320static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_ul[] = {
321 {255, 0, 0, 7}, /* 0 -> original */
322 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
323 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
324 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
325 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
326 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
327 {6, 1, 0, 7},
328 {13, 1, 0, 7},
329 {13, 1, 0, 7}
330};
331
332static const struct rtw89_btc_rf_trx_para rtw89_btc_8852b_rf_dl[] = {
333 {255, 0, 0, 7}, /* 0 -> original */
334 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
335 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
336 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
337 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
338 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */
339 {255, 1, 0, 7},
340 {255, 1, 0, 7},
341 {255, 1, 0, 7}
342};
343
344static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852b_mon_reg[] = {
345 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24),
346 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28),
347 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c),
348 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30),
349 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c),
350 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10),
351 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20),
352 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34),
353 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4),
354 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424),
355 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200),
356 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220),
357 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
358 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178),
359};
360
361static const u8 rtw89_btc_8852b_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {70, 60, 50, 40};
362static const u8 rtw89_btc_8852b_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {50, 40, 30, 20};
363
364static int rtw8852b_pwr_on_func(struct rtw89_dev *rtwdev)
365{
366 u32 val32;
367 u32 ret;
368
369 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN |
370 B_AX_AFSM_PCIE_SUS_EN);
371 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC);
372 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC);
373 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN);
374 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
375
376 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR,
377 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
378 if (ret)
379 return ret;
380
381 rtw89_write32_set(rtwdev, R_AX_AFE_LDO_CTRL, B_AX_AON_OFF_PC_EN);
382 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_AON_OFF_PC_EN,
383 1000, 20000, false, rtwdev, R_AX_AFE_LDO_CTRL);
384 if (ret)
385 return ret;
386
387 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C1_L1_MASK, 0x1);
388 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_OFF_CTRL0, B_AX_C3_L1_MASK, 0x3);
389 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
390 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC);
391
392 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC),
393 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
394 if (ret)
395 return ret;
396
397 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
398 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
399 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
400 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
401
402 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN);
403 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1);
404
405 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
406
407 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
408 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL);
409 if (ret)
410 return ret;
411
412 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
413
414 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL,
415 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL);
416 if (ret)
417 return ret;
418 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI,
419 XTAL_SI_OFF_WEI);
420 if (ret)
421 return ret;
422 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI,
423 XTAL_SI_OFF_EI);
424 if (ret)
425 return ret;
426 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF);
427 if (ret)
428 return ret;
429 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI,
430 XTAL_SI_PON_WEI);
431 if (ret)
432 return ret;
433 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI,
434 XTAL_SI_PON_EI);
435 if (ret)
436 return ret;
437 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC);
438 if (ret)
439 return ret;
440 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_SRAM_CTRL, 0, XTAL_SI_SRAM_DIS);
441 if (ret)
442 return ret;
443 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS);
444 if (ret)
445 return ret;
446 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP);
447 if (ret)
448 return ret;
449
450 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
451 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE);
452 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15);
453
454 fsleep(1000);
455
456 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14);
457 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
458
459 if (!rtwdev->efuse.valid || rtwdev->efuse.power_k_valid)
460 goto func_en;
461
462 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VOL_L1_MASK, 0x9);
463 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_VREFPFM_L_MASK, 0xA);
464
465 if (rtwdev->hal.cv == CHIP_CBV) {
466 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
467 rtw89_write16_mask(rtwdev, R_AX_HCI_LDO_CTRL, B_AX_R_AX_VADJ_MASK, 0xA);
468 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK);
469 }
470
471func_en:
472 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN,
473 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN |
474 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN |
475 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN |
476 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN |
477 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN |
478 B_AX_DMACREG_GCKEN);
479 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN,
480 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN |
481 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN |
482 B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | B_AX_TMAC_EN |
483 B_AX_RMAC_EN);
484
485 rtw89_write32_mask(rtwdev, R_AX_EECS_EESK_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_MASK,
486 PINMUX_EESK_FUNC_SEL_BT_LOG);
487
488 return 0;
489}
490
491static int rtw8852b_pwr_off_func(struct rtw89_dev *rtwdev)
492{
493 u32 val32;
494 u32 ret;
495
496 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF,
497 XTAL_SI_RFC2RF);
498 if (ret)
499 return ret;
500 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI);
501 if (ret)
502 return ret;
503 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI);
504 if (ret)
505 return ret;
506 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00);
507 if (ret)
508 return ret;
509 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10);
510 if (ret)
511 return ret;
512 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC,
513 XTAL_SI_SRAM2RFC);
514 if (ret)
515 return ret;
516 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI);
517 if (ret)
518 return ret;
519 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI);
520 if (ret)
521 return ret;
522
523 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON);
524 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB);
525 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3);
526
527 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL);
528 if (ret)
529 return ret;
530
531 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3);
532
533 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL);
534 if (ret)
535 return ret;
536
537 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC);
538
539 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC),
540 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL);
541 if (ret)
542 return ret;
543
544 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION);
545 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ);
546 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x3);
547 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS);
548
549 return 0;
550}
551
552static void rtw8852be_efuse_parsing(struct rtw89_efuse *efuse,
553 struct rtw8852b_efuse *map)
554{
555 ether_addr_copy(efuse->addr, map->e.mac_addr);
556 efuse->rfe_type = map->rfe_type;
557 efuse->xtal_cap = map->xtal_k;
558}
559
560static void rtw8852b_efuse_parsing_tssi(struct rtw89_dev *rtwdev,
561 struct rtw8852b_efuse *map)
562{
563 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
564 struct rtw8852b_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi};
565 u8 i, j;
566
567 tssi->thermal[RF_PATH_A] = map->path_a_therm;
568 tssi->thermal[RF_PATH_B] = map->path_b_therm;
569
570 for (i = 0; i < RF_PATH_NUM_8852B; i++) {
571 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi,
572 sizeof(ofst[i]->cck_tssi));
573
574 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++)
575 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
576 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n",
577 i, j, tssi->tssi_cck[i][j]);
578
579 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi,
580 sizeof(ofst[i]->bw40_tssi));
581 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM,
582 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g));
583
584 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++)
585 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
586 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n",
587 i, j, tssi->tssi_mcs[i][j]);
588 }
589}
590
591static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low)
592{
593 if (high)
594 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3);
595 if (low)
596 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3);
597
598 return data != 0xff;
599}
600
601static void rtw8852b_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev,
602 struct rtw8852b_efuse *map)
603{
604 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
605 bool valid = false;
606
607 valid |= _decode_efuse_gain(map->rx_gain_2g_cck,
608 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK],
609 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]);
610 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm,
611 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM],
612 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]);
613 valid |= _decode_efuse_gain(map->rx_gain_5g_low,
614 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW],
615 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]);
616 valid |= _decode_efuse_gain(map->rx_gain_5g_mid,
617 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID],
618 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]);
619 valid |= _decode_efuse_gain(map->rx_gain_5g_high,
620 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH],
621 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]);
622
623 gain->offset_valid = valid;
624}
625
626static int rtw8852b_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map)
627{
628 struct rtw89_efuse *efuse = &rtwdev->efuse;
629 struct rtw8852b_efuse *map;
630
631 map = (struct rtw8852b_efuse *)log_map;
632
633 efuse->country_code[0] = map->country_code[0];
634 efuse->country_code[1] = map->country_code[1];
635 rtw8852b_efuse_parsing_tssi(rtwdev, map);
636 rtw8852b_efuse_parsing_gain_offset(rtwdev, map);
637
638 switch (rtwdev->hci.type) {
639 case RTW89_HCI_TYPE_PCIE:
640 rtw8852be_efuse_parsing(efuse, map);
641 break;
642 default:
643 return -EOPNOTSUPP;
644 }
645
646 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type);
647
648 return 0;
649}
650
651static void rtw8852b_phycap_parsing_power_cal(struct rtw89_dev *rtwdev, u8 *phycap_map)
652{
653#define PWR_K_CHK_OFFSET 0x5E9
654#define PWR_K_CHK_VALUE 0xAA
655 u32 offset = PWR_K_CHK_OFFSET - rtwdev->chip->phycap_addr;
656
657 if (phycap_map[offset] == PWR_K_CHK_VALUE)
658 rtwdev->efuse.power_k_valid = true;
659}
660
661static void rtw8852b_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
662{
663 struct rtw89_tssi_info *tssi = &rtwdev->tssi;
664 static const u32 tssi_trim_addr[RF_PATH_NUM_8852B] = {0x5D6, 0x5AB};
665 u32 addr = rtwdev->chip->phycap_addr;
666 bool pg = false;
667 u32 ofst;
668 u8 i, j;
669
670 for (i = 0; i < RF_PATH_NUM_8852B; i++) {
671 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
672 /* addrs are in decreasing order */
673 ofst = tssi_trim_addr[i] - addr - j;
674 tssi->tssi_trim[i][j] = phycap_map[ofst];
675
676 if (phycap_map[ofst] != 0xff)
677 pg = true;
678 }
679 }
680
681 if (!pg) {
682 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
683 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
684 "[TSSI][TRIM] no PG, set all trim info to 0\n");
685 }
686
687 for (i = 0; i < RF_PATH_NUM_8852B; i++)
688 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
689 rtw89_debug(rtwdev, RTW89_DBG_TSSI,
690 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
691 i, j, tssi->tssi_trim[i][j],
692 tssi_trim_addr[i] - j);
693}
694
695static void rtw8852b_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
696 u8 *phycap_map)
697{
698 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
699 static const u32 thm_trim_addr[RF_PATH_NUM_8852B] = {0x5DF, 0x5DC};
700 u32 addr = rtwdev->chip->phycap_addr;
701 u8 i;
702
703 for (i = 0; i < RF_PATH_NUM_8852B; i++) {
704 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
705
706 rtw89_debug(rtwdev, RTW89_DBG_RFK,
707 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
708 i, info->thermal_trim[i]);
709
710 if (info->thermal_trim[i] != 0xff)
711 info->pg_thermal_trim = true;
712 }
713}
714
715static void rtw8852b_thermal_trim(struct rtw89_dev *rtwdev)
716{
717#define __thm_setting(raw) \
718({ \
719 u8 __v = (raw); \
720 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
721})
722 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
723 u8 i, val;
724
725 if (!info->pg_thermal_trim) {
726 rtw89_debug(rtwdev, RTW89_DBG_RFK,
727 "[THERMAL][TRIM] no PG, do nothing\n");
728
729 return;
730 }
731
732 for (i = 0; i < RF_PATH_NUM_8852B; i++) {
733 val = __thm_setting(info->thermal_trim[i]);
734 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
735
736 rtw89_debug(rtwdev, RTW89_DBG_RFK,
737 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
738 i, val);
739 }
740#undef __thm_setting
741}
742
743static void rtw8852b_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
744 u8 *phycap_map)
745{
746 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
747 static const u32 pabias_trim_addr[RF_PATH_NUM_8852B] = {0x5DE, 0x5DB};
748 u32 addr = rtwdev->chip->phycap_addr;
749 u8 i;
750
751 for (i = 0; i < RF_PATH_NUM_8852B; i++) {
752 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
753
754 rtw89_debug(rtwdev, RTW89_DBG_RFK,
755 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
756 i, info->pa_bias_trim[i]);
757
758 if (info->pa_bias_trim[i] != 0xff)
759 info->pg_pa_bias_trim = true;
760 }
761}
762
763static void rtw8852b_pa_bias_trim(struct rtw89_dev *rtwdev)
764{
765 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
766 u8 pabias_2g, pabias_5g;
767 u8 i;
768
769 if (!info->pg_pa_bias_trim) {
770 rtw89_debug(rtwdev, RTW89_DBG_RFK,
771 "[PA_BIAS][TRIM] no PG, do nothing\n");
772
773 return;
774 }
775
776 for (i = 0; i < RF_PATH_NUM_8852B; i++) {
777 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
778 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
779
780 rtw89_debug(rtwdev, RTW89_DBG_RFK,
781 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
782 i, pabias_2g, pabias_5g);
783
784 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
785 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
786 }
787}
788
789static void rtw8852b_phycap_parsing_gain_comp(struct rtw89_dev *rtwdev, u8 *phycap_map)
790{
791 static const u32 comp_addrs[][RTW89_SUBBAND_2GHZ_5GHZ_NR] = {
792 {0x5BB, 0x5BA, 0, 0x5B9, 0x5B8},
793 {0x590, 0x58F, 0, 0x58E, 0x58D},
794 };
795 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
796 u32 phycap_addr = rtwdev->chip->phycap_addr;
797 bool valid = false;
798 int path, i;
799 u8 data;
800
801 for (path = 0; path < 2; path++)
802 for (i = 0; i < RTW89_SUBBAND_2GHZ_5GHZ_NR; i++) {
803 if (comp_addrs[path][i] == 0)
804 continue;
805
806 data = phycap_map[comp_addrs[path][i] - phycap_addr];
807 valid |= _decode_efuse_gain(data, NULL,
808 &gain->comp[path][i]);
809 }
810
811 gain->comp_valid = valid;
812}
813
814static int rtw8852b_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
815{
816 rtw8852b_phycap_parsing_power_cal(rtwdev, phycap_map);
817 rtw8852b_phycap_parsing_tssi(rtwdev, phycap_map);
818 rtw8852b_phycap_parsing_thermal_trim(rtwdev, phycap_map);
819 rtw8852b_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
820 rtw8852b_phycap_parsing_gain_comp(rtwdev, phycap_map);
821
822 return 0;
823}
824
825static void rtw8852b_power_trim(struct rtw89_dev *rtwdev)
826{
827 rtw8852b_thermal_trim(rtwdev);
828 rtw8852b_pa_bias_trim(rtwdev);
829}
830
831static void rtw8852b_set_channel_mac(struct rtw89_dev *rtwdev,
832 const struct rtw89_chan *chan,
833 u8 mac_idx)
834{
835 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx);
836 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, mac_idx);
837 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx);
838 u8 txsc20 = 0, txsc40 = 0;
839
840 switch (chan->band_width) {
841 case RTW89_CHANNEL_WIDTH_80:
842 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_40);
843 fallthrough;
844 case RTW89_CHANNEL_WIDTH_40:
845 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, RTW89_CHANNEL_WIDTH_20);
846 break;
847 default:
848 break;
849 }
850
851 switch (chan->band_width) {
852 case RTW89_CHANNEL_WIDTH_80:
853 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1));
854 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4));
855 break;
856 case RTW89_CHANNEL_WIDTH_40:
857 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0));
858 rtw89_write32(rtwdev, sub_carr, txsc20);
859 break;
860 case RTW89_CHANNEL_WIDTH_20:
861 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK);
862 rtw89_write32(rtwdev, sub_carr, 0);
863 break;
864 default:
865 break;
866 }
867
868 if (chan->channel > 14) {
869 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE);
870 rtw89_write8_set(rtwdev, chk_rate,
871 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
872 } else {
873 rtw89_write8_set(rtwdev, chk_rate, B_AX_BAND_MODE);
874 rtw89_write8_clr(rtwdev, chk_rate,
875 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6);
876 }
877}
878
879static const u32 rtw8852b_sco_barker_threshold[14] = {
880 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6,
881 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4
882};
883
884static const u32 rtw8852b_sco_cck_threshold[14] = {
885 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724,
886 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed
887};
888
889static void rtw8852b_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 primary_ch)
890{
891 u8 ch_element = primary_ch - 1;
892
893 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH,
894 rtw8852b_sco_barker_threshold[ch_element]);
895 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH,
896 rtw8852b_sco_cck_threshold[ch_element]);
897}
898
899static u8 rtw8852b_sco_mapping(u8 central_ch)
900{
901 if (central_ch == 1)
902 return 109;
903 else if (central_ch >= 2 && central_ch <= 6)
904 return 108;
905 else if (central_ch >= 7 && central_ch <= 10)
906 return 107;
907 else if (central_ch >= 11 && central_ch <= 14)
908 return 106;
909 else if (central_ch == 36 || central_ch == 38)
910 return 51;
911 else if (central_ch >= 40 && central_ch <= 58)
912 return 50;
913 else if (central_ch >= 60 && central_ch <= 64)
914 return 49;
915 else if (central_ch == 100 || central_ch == 102)
916 return 48;
917 else if (central_ch >= 104 && central_ch <= 126)
918 return 47;
919 else if (central_ch >= 128 && central_ch <= 151)
920 return 46;
921 else if (central_ch >= 153 && central_ch <= 177)
922 return 45;
923 else
924 return 0;
925}
926
927struct rtw8852b_bb_gain {
928 u32 gain_g[BB_PATH_NUM_8852B];
929 u32 gain_a[BB_PATH_NUM_8852B];
930 u32 gain_mask;
931};
932
933static const struct rtw8852b_bb_gain bb_gain_lna[LNA_GAIN_NUM] = {
934 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
935 .gain_mask = 0x00ff0000 },
936 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740},
937 .gain_mask = 0xff000000 },
938 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
939 .gain_mask = 0x000000ff },
940 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
941 .gain_mask = 0x0000ff00 },
942 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
943 .gain_mask = 0x00ff0000 },
944 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744},
945 .gain_mask = 0xff000000 },
946 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
947 .gain_mask = 0x000000ff },
948};
949
950static const struct rtw8852b_bb_gain bb_gain_tia[TIA_GAIN_NUM] = {
951 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
952 .gain_mask = 0x00ff0000 },
953 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748},
954 .gain_mask = 0xff000000 },
955};
956
957static void rtw8852b_set_gain_error(struct rtw89_dev *rtwdev,
958 enum rtw89_subband subband,
959 enum rtw89_rf_path path)
960{
961 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
962 u8 gain_band = rtw89_subband_to_bb_gain_band(subband);
963 s32 val;
964 u32 reg;
965 u32 mask;
966 int i;
967
968 for (i = 0; i < LNA_GAIN_NUM; i++) {
969 if (subband == RTW89_CH_2G)
970 reg = bb_gain_lna[i].gain_g[path];
971 else
972 reg = bb_gain_lna[i].gain_a[path];
973
974 mask = bb_gain_lna[i].gain_mask;
975 val = gain->lna_gain[gain_band][path][i];
976 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
977 }
978
979 for (i = 0; i < TIA_GAIN_NUM; i++) {
980 if (subband == RTW89_CH_2G)
981 reg = bb_gain_tia[i].gain_g[path];
982 else
983 reg = bb_gain_tia[i].gain_a[path];
984
985 mask = bb_gain_tia[i].gain_mask;
986 val = gain->tia_gain[gain_band][path][i];
987 rtw89_phy_write32_mask(rtwdev, reg, mask, val);
988 }
989}
990
991static void rtw8852b_set_gain_offset(struct rtw89_dev *rtwdev,
992 enum rtw89_subband subband,
993 enum rtw89_phy_idx phy_idx)
994{
995 static const u32 gain_err_addr[2] = {R_P0_AGC_RSVD, R_P1_AGC_RSVD};
996 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA1_LNA6_OP1DB_V1,
997 R_PATH1_G_TIA1_LNA6_OP1DB_V1};
998 struct rtw89_hal *hal = &rtwdev->hal;
999 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain;
1000 enum rtw89_gain_offset gain_ofdm_band;
1001 s32 offset_a, offset_b;
1002 s32 offset_ofdm, offset_cck;
1003 s32 tmp;
1004 u8 path;
1005
1006 if (!efuse_gain->comp_valid)
1007 goto next;
1008
1009 for (path = RF_PATH_A; path < BB_PATH_NUM_8852B; path++) {
1010 tmp = efuse_gain->comp[path][subband];
1011 tmp = clamp_t(s32, tmp << 2, S8_MIN, S8_MAX);
1012 rtw89_phy_write32_mask(rtwdev, gain_err_addr[path], MASKBYTE0, tmp);
1013 }
1014
1015next:
1016 if (!efuse_gain->offset_valid)
1017 return;
1018
1019 gain_ofdm_band = rtw89_subband_to_gain_offset_band_of_ofdm(subband);
1020
1021 offset_a = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
1022 offset_b = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
1023
1024 tmp = -((offset_a << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
1025 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
1026 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_A], B_PATH0_R_G_OFST_MASK, tmp);
1027
1028 tmp = -((offset_b << 2) + (efuse_gain->offset_base[RTW89_PHY_0] >> 2));
1029 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
1030 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[RF_PATH_B], B_PATH0_R_G_OFST_MASK, tmp);
1031
1032 if (hal->antenna_rx == RF_B) {
1033 offset_ofdm = -efuse_gain->offset[RF_PATH_B][gain_ofdm_band];
1034 offset_cck = -efuse_gain->offset[RF_PATH_B][0];
1035 } else {
1036 offset_ofdm = -efuse_gain->offset[RF_PATH_A][gain_ofdm_band];
1037 offset_cck = -efuse_gain->offset[RF_PATH_A][0];
1038 }
1039
1040 tmp = (offset_ofdm << 4) + efuse_gain->offset_base[RTW89_PHY_0];
1041 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
1042 rtw89_phy_write32_idx(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
1043
1044 tmp = (offset_ofdm << 4) + efuse_gain->rssi_base[RTW89_PHY_0];
1045 tmp = clamp_t(s32, tmp, S8_MIN, S8_MAX);
1046 rtw89_phy_write32_idx(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK, tmp, phy_idx);
1047
1048 if (subband == RTW89_CH_2G) {
1049 tmp = (offset_cck << 3) + (efuse_gain->offset_base[RTW89_PHY_0] >> 1);
1050 tmp = clamp_t(s32, tmp, S8_MIN >> 1, S8_MAX >> 1);
1051 rtw89_phy_write32_mask(rtwdev, R_RX_RPL_OFST,
1052 B_RX_RPL_OFST_CCK_MASK, tmp);
1053 }
1054}
1055
1056static
1057void rtw8852b_set_rxsc_rpl_comp(struct rtw89_dev *rtwdev, enum rtw89_subband subband)
1058{
1059 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain;
1060 u8 band = rtw89_subband_to_bb_gain_band(subband);
1061 u32 val;
1062
1063 val = FIELD_PREP(B_P0_RPL1_20_MASK, (gain->rpl_ofst_20[band][RF_PATH_A] +
1064 gain->rpl_ofst_20[band][RF_PATH_B]) / 2) |
1065 FIELD_PREP(B_P0_RPL1_40_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][0] +
1066 gain->rpl_ofst_40[band][RF_PATH_B][0]) / 2) |
1067 FIELD_PREP(B_P0_RPL1_41_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][1] +
1068 gain->rpl_ofst_40[band][RF_PATH_B][1]) / 2);
1069 val >>= B_P0_RPL1_SHIFT;
1070 rtw89_phy_write32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_MASK, val);
1071 rtw89_phy_write32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_MASK, val);
1072
1073 val = FIELD_PREP(B_P0_RTL2_42_MASK, (gain->rpl_ofst_40[band][RF_PATH_A][2] +
1074 gain->rpl_ofst_40[band][RF_PATH_B][2]) / 2) |
1075 FIELD_PREP(B_P0_RTL2_80_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][0] +
1076 gain->rpl_ofst_80[band][RF_PATH_B][0]) / 2) |
1077 FIELD_PREP(B_P0_RTL2_81_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][1] +
1078 gain->rpl_ofst_80[band][RF_PATH_B][1]) / 2) |
1079 FIELD_PREP(B_P0_RTL2_8A_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][10] +
1080 gain->rpl_ofst_80[band][RF_PATH_B][10]) / 2);
1081 rtw89_phy_write32(rtwdev, R_P0_RPL2, val);
1082 rtw89_phy_write32(rtwdev, R_P1_RPL2, val);
1083
1084 val = FIELD_PREP(B_P0_RTL3_82_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][2] +
1085 gain->rpl_ofst_80[band][RF_PATH_B][2]) / 2) |
1086 FIELD_PREP(B_P0_RTL3_83_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][3] +
1087 gain->rpl_ofst_80[band][RF_PATH_B][3]) / 2) |
1088 FIELD_PREP(B_P0_RTL3_84_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][4] +
1089 gain->rpl_ofst_80[band][RF_PATH_B][4]) / 2) |
1090 FIELD_PREP(B_P0_RTL3_89_MASK, (gain->rpl_ofst_80[band][RF_PATH_A][9] +
1091 gain->rpl_ofst_80[band][RF_PATH_B][9]) / 2);
1092 rtw89_phy_write32(rtwdev, R_P0_RPL3, val);
1093 rtw89_phy_write32(rtwdev, R_P1_RPL3, val);
1094}
1095
1096static void rtw8852b_ctrl_ch(struct rtw89_dev *rtwdev,
1097 const struct rtw89_chan *chan,
1098 enum rtw89_phy_idx phy_idx)
1099{
1100 u8 central_ch = chan->channel;
1101 u8 subband = chan->subband_type;
1102 u8 sco_comp;
1103 bool is_2g = central_ch <= 14;
1104
1105 /* Path A */
1106 if (is_2g)
1107 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1108 B_PATH0_BAND_SEL_MSK_V1, 1, phy_idx);
1109 else
1110 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1,
1111 B_PATH0_BAND_SEL_MSK_V1, 0, phy_idx);
1112
1113 /* Path B */
1114 if (is_2g)
1115 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1116 B_PATH1_BAND_SEL_MSK_V1, 1, phy_idx);
1117 else
1118 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1,
1119 B_PATH1_BAND_SEL_MSK_V1, 0, phy_idx);
1120
1121 /* SCO compensate FC setting */
1122 sco_comp = rtw8852b_sco_mapping(central_ch);
1123 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_INV, sco_comp, phy_idx);
1124
1125 if (chan->band_type == RTW89_BAND_6G)
1126 return;
1127
1128 /* CCK parameters */
1129 if (central_ch == 14) {
1130 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3b13ff);
1131 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x1c42de);
1132 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfdb0ad);
1133 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xf60f6e);
1134 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xfd8f92);
1135 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011);
1136 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c);
1137 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xfff00a);
1138 } else {
1139 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 0x3d23ff);
1140 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 0x29b354);
1141 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8);
1142 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 0xfdb053);
1143 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 0xf86f9a);
1144 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0xfaef92);
1145 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0xfe5fcc);
1146 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 0xffdff5);
1147 }
1148
1149 rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_A);
1150 rtw8852b_set_gain_error(rtwdev, subband, RF_PATH_B);
1151 rtw8852b_set_gain_offset(rtwdev, subband, phy_idx);
1152 rtw8852b_set_rxsc_rpl_comp(rtwdev, subband);
1153}
1154
1155static void rtw8852b_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path)
1156{
1157 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC};
1158 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4};
1159
1160 switch (bw) {
1161 case RTW89_CHANNEL_WIDTH_5:
1162 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1);
1163 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0);
1164 break;
1165 case RTW89_CHANNEL_WIDTH_10:
1166 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2);
1167 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1);
1168 break;
1169 case RTW89_CHANNEL_WIDTH_20:
1170 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1171 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1172 break;
1173 case RTW89_CHANNEL_WIDTH_40:
1174 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1175 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1176 break;
1177 case RTW89_CHANNEL_WIDTH_80:
1178 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0);
1179 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2);
1180 break;
1181 default:
1182 rtw89_warn(rtwdev, "Fail to set ADC\n");
1183 }
1184}
1185
1186static void rtw8852b_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw,
1187 enum rtw89_phy_idx phy_idx)
1188{
1189 u32 rx_path_0;
1190
1191 switch (bw) {
1192 case RTW89_CHANNEL_WIDTH_5:
1193 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1194 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x1, phy_idx);
1195 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1196
1197 /*Set RF mode at 3 */
1198 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1199 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1200 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1201 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1202 break;
1203 case RTW89_CHANNEL_WIDTH_10:
1204 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1205 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x2, phy_idx);
1206 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1207
1208 /*Set RF mode at 3 */
1209 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1210 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1211 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1212 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1213 break;
1214 case RTW89_CHANNEL_WIDTH_20:
1215 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x0, phy_idx);
1216 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1217 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH, 0x0, phy_idx);
1218
1219 /*Set RF mode at 3 */
1220 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1221 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1222 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1223 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1224 break;
1225 case RTW89_CHANNEL_WIDTH_40:
1226 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x1, phy_idx);
1227 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1228 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1229 pri_ch, phy_idx);
1230
1231 /*Set RF mode at 3 */
1232 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1233 B_P0_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1234 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1235 B_P1_RFMODE_ORI_RX_ALL, 0x333, phy_idx);
1236 /*CCK primary channel */
1237 if (pri_ch == RTW89_SC_20_UPPER)
1238 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1);
1239 else
1240 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0);
1241
1242 break;
1243 case RTW89_CHANNEL_WIDTH_80:
1244 rtw89_phy_write32_idx(rtwdev, R_FC0_BW_V1, B_FC0_BW_SET, 0x2, phy_idx);
1245 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_SBW, 0x0, phy_idx);
1246 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_CHBW_MOD_PRICH,
1247 pri_ch, phy_idx);
1248
1249 /*Set RF mode at A */
1250 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1251 B_P0_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx);
1252 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1253 B_P1_RFMODE_ORI_RX_ALL, 0xaaa, phy_idx);
1254 break;
1255 default:
1256 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw,
1257 pri_ch);
1258 }
1259
1260 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_A);
1261 rtw8852b_bw_setting(rtwdev, bw, RF_PATH_B);
1262
1263 rx_path_0 = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0,
1264 phy_idx);
1265 if (rx_path_0 == 0x1)
1266 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_ORI_RX,
1267 B_P1_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
1268 else if (rx_path_0 == 0x2)
1269 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_ORI_RX,
1270 B_P0_RFMODE_ORI_RX_ALL, 0x111, phy_idx);
1271}
1272
1273static void rtw8852b_ctrl_cck_en(struct rtw89_dev *rtwdev, bool cck_en)
1274{
1275 if (cck_en) {
1276 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1);
1277 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0);
1278 } else {
1279 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0);
1280 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1);
1281 }
1282}
1283
1284static void rtw8852b_5m_mask(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1285 enum rtw89_phy_idx phy_idx)
1286{
1287 u8 pri_ch = chan->primary_channel;
1288 bool mask_5m_low;
1289 bool mask_5m_en;
1290
1291 switch (chan->band_width) {
1292 case RTW89_CHANNEL_WIDTH_40:
1293 /* Prich=1: Mask 5M High, Prich=2: Mask 5M Low */
1294 mask_5m_en = true;
1295 mask_5m_low = pri_ch == 2;
1296 break;
1297 case RTW89_CHANNEL_WIDTH_80:
1298 /* Prich=3: Mask 5M High, Prich=4: Mask 5M Low, Else: Disable */
1299 mask_5m_en = pri_ch == 3 || pri_ch == 4;
1300 mask_5m_low = pri_ch == 4;
1301 break;
1302 default:
1303 mask_5m_en = false;
1304 break;
1305 }
1306
1307 if (!mask_5m_en) {
1308 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x0);
1309 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x0);
1310 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1311 B_ASSIGN_SBD_OPT_EN_V1, 0x0, phy_idx);
1312 return;
1313 }
1314
1315 if (mask_5m_low) {
1316 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
1317 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1318 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x0);
1319 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x1);
1320 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
1321 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
1322 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x0);
1323 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x1);
1324 } else {
1325 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_TH, 0x4);
1326 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_EN, 0x1);
1327 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB2, 0x1);
1328 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET_V1, B_PATH0_5MDET_SB0, 0x0);
1329 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_TH, 0x4);
1330 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_EN, 0x1);
1331 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB2, 0x1);
1332 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET_V1, B_PATH1_5MDET_SB0, 0x0);
1333 }
1334 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT_V1,
1335 B_ASSIGN_SBD_OPT_EN_V1, 0x1, phy_idx);
1336}
1337
1338static void rtw8852b_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1339{
1340 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1341 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1342 fsleep(1);
1343 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1344 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1345 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1346 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1347 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1348}
1349
1350static void rtw8852b_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band,
1351 enum rtw89_phy_idx phy_idx, bool en)
1352{
1353 if (en) {
1354 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1355 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1356 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1357 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx);
1358 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, phy_idx);
1359 if (band == RTW89_BAND_2G)
1360 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x0);
1361 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0);
1362 } else {
1363 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0x1);
1364 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1);
1365 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS,
1366 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1367 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS,
1368 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx);
1369 fsleep(1);
1370 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx);
1371 }
1372}
1373
1374static void rtw8852b_bb_reset(struct rtw89_dev *rtwdev,
1375 enum rtw89_phy_idx phy_idx)
1376{
1377 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1378 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1379 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1380 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1381 rtw8852b_bb_reset_all(rtwdev, phy_idx);
1382 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON);
1383 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN);
1384 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON);
1385 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN);
1386}
1387
1388static void rtw8852b_bb_macid_ctrl_init(struct rtw89_dev *rtwdev,
1389 enum rtw89_phy_idx phy_idx)
1390{
1391 u32 addr;
1392
1393 for (addr = R_AX_PWR_MACID_LMT_TABLE0;
1394 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4)
1395 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0);
1396}
1397
1398static void rtw8852b_bb_sethw(struct rtw89_dev *rtwdev)
1399{
1400 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain;
1401
1402 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP);
1403 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP);
1404
1405 rtw8852b_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0);
1406
1407 /* read these registers after loading BB parameters */
1408 gain->offset_base[RTW89_PHY_0] =
1409 rtw89_phy_read32_mask(rtwdev, R_P0_RPL1, B_P0_RPL1_BIAS_MASK);
1410 gain->rssi_base[RTW89_PHY_0] =
1411 rtw89_phy_read32_mask(rtwdev, R_P1_RPL1, B_P0_RPL1_BIAS_MASK);
1412}
1413
1414static void rtw8852b_bb_set_pop(struct rtw89_dev *rtwdev)
1415{
1416 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)
1417 rtw89_phy_write32_clr(rtwdev, R_PKT_CTRL, B_PKT_POP_EN);
1418}
1419
1420static void rtw8852b_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
1421 enum rtw89_phy_idx phy_idx)
1422{
1423 bool cck_en = chan->channel <= 14;
1424 u8 pri_ch_idx = chan->pri_ch_idx;
1425
1426 if (cck_en)
1427 rtw8852b_ctrl_sco_cck(rtwdev, chan->primary_channel);
1428
1429 rtw8852b_ctrl_ch(rtwdev, chan, phy_idx);
1430 rtw8852b_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx);
1431 rtw8852b_ctrl_cck_en(rtwdev, cck_en);
1432 if (chan->band_type == RTW89_BAND_5G) {
1433 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1434 B_PATH0_BT_SHARE_V1, 0x0);
1435 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1436 B_PATH0_BTG_PATH_V1, 0x0);
1437 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1438 B_PATH1_BT_SHARE_V1, 0x0);
1439 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1440 B_PATH1_BTG_PATH_V1, 0x0);
1441 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1442 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1443 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1444 B_BT_DYN_DC_EST_EN_MSK, 0x0);
1445 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1446 }
1447 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0,
1448 chan->primary_channel);
1449 rtw8852b_5m_mask(rtwdev, chan, phy_idx);
1450 rtw8852b_bb_set_pop(rtwdev);
1451 rtw8852b_bb_reset_all(rtwdev, phy_idx);
1452}
1453
1454static void rtw8852b_set_channel(struct rtw89_dev *rtwdev,
1455 const struct rtw89_chan *chan,
1456 enum rtw89_mac_idx mac_idx,
1457 enum rtw89_phy_idx phy_idx)
1458{
1459 rtw8852b_set_channel_mac(rtwdev, chan, mac_idx);
1460 rtw8852b_set_channel_bb(rtwdev, chan, phy_idx);
1461 rtw8852b_set_channel_rf(rtwdev, chan, phy_idx);
1462}
1463
1464static void rtw8852b_tssi_cont_en(struct rtw89_dev *rtwdev, bool en,
1465 enum rtw89_rf_path path)
1466{
1467 static const u32 tssi_trk[2] = {R_P0_TSSI_TRK, R_P1_TSSI_TRK};
1468 static const u32 ctrl_bbrst[2] = {R_P0_TXPW_RSTB, R_P1_TXPW_RSTB};
1469
1470 if (en) {
1471 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x0);
1472 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x0);
1473 } else {
1474 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], B_P0_TXPW_RSTB_MANON, 0x1);
1475 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], B_P0_TSSI_TRK_EN, 0x1);
1476 }
1477}
1478
1479static void rtw8852b_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en,
1480 u8 phy_idx)
1481{
1482 if (!rtwdev->dbcc_en) {
1483 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1484 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
1485 } else {
1486 if (phy_idx == RTW89_PHY_0)
1487 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_A);
1488 else
1489 rtw8852b_tssi_cont_en(rtwdev, en, RF_PATH_B);
1490 }
1491}
1492
1493static void rtw8852b_adc_en(struct rtw89_dev *rtwdev, bool en)
1494{
1495 if (en)
1496 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0x0);
1497 else
1498 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 0xf);
1499}
1500
1501static void rtw8852b_set_channel_help(struct rtw89_dev *rtwdev, bool enter,
1502 struct rtw89_channel_help_params *p,
1503 const struct rtw89_chan *chan,
1504 enum rtw89_mac_idx mac_idx,
1505 enum rtw89_phy_idx phy_idx)
1506{
1507 if (enter) {
1508 rtw89_chip_stop_sch_tx(rtwdev, RTW89_MAC_0, &p->tx_en, RTW89_SCH_TX_SEL_ALL);
1509 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false);
1510 rtw8852b_tssi_cont_en_phyidx(rtwdev, false, RTW89_PHY_0);
1511 rtw8852b_adc_en(rtwdev, false);
1512 fsleep(40);
1513 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, false);
1514 } else {
1515 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true);
1516 rtw8852b_adc_en(rtwdev, true);
1517 rtw8852b_tssi_cont_en_phyidx(rtwdev, true, RTW89_PHY_0);
1518 rtw8852b_bb_reset_en(rtwdev, chan->band_type, phy_idx, true);
1519 rtw89_chip_resume_sch_tx(rtwdev, RTW89_MAC_0, p->tx_en);
1520 }
1521}
1522
1523static void rtw8852b_rfk_init(struct rtw89_dev *rtwdev)
1524{
1525 rtwdev->is_tssi_mode[RF_PATH_A] = false;
1526 rtwdev->is_tssi_mode[RF_PATH_B] = false;
1527
1528 rtw8852b_dpk_init(rtwdev);
1529 rtw8852b_rck(rtwdev);
1530 rtw8852b_dack(rtwdev);
1531 rtw8852b_rx_dck(rtwdev, RTW89_PHY_0);
1532}
1533
1534static void rtw8852b_rfk_channel(struct rtw89_dev *rtwdev)
1535{
1536 enum rtw89_phy_idx phy_idx = RTW89_PHY_0;
1537
1538 rtw8852b_rx_dck(rtwdev, phy_idx);
1539 rtw8852b_iqk(rtwdev, phy_idx);
1540 rtw8852b_tssi(rtwdev, phy_idx, true);
1541 rtw8852b_dpk(rtwdev, phy_idx);
1542}
1543
1544static void rtw8852b_rfk_band_changed(struct rtw89_dev *rtwdev,
1545 enum rtw89_phy_idx phy_idx)
1546{
1547 rtw8852b_tssi_scan(rtwdev, phy_idx);
1548}
1549
1550static void rtw8852b_rfk_scan(struct rtw89_dev *rtwdev, bool start)
1551{
1552 rtw8852b_wifi_scan_notify(rtwdev, start, RTW89_PHY_0);
1553}
1554
1555static void rtw8852b_rfk_track(struct rtw89_dev *rtwdev)
1556{
1557 rtw8852b_dpk_track(rtwdev);
1558}
1559
1560static u32 rtw8852b_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev,
1561 enum rtw89_phy_idx phy_idx, s16 ref)
1562{
1563 const u16 tssi_16dbm_cw = 0x12c;
1564 const u8 base_cw_0db = 0x27;
1565 const s8 ofst_int = 0;
1566 s16 pwr_s10_3;
1567 s16 rf_pwr_cw;
1568 u16 bb_pwr_cw;
1569 u32 pwr_cw;
1570 u32 tssi_ofst_cw;
1571
1572 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3);
1573 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3);
1574 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3);
1575 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63);
1576 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw;
1577
1578 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3));
1579 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1580 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n",
1581 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw);
1582
1583 return FIELD_PREP(B_DPD_TSSI_CW, tssi_ofst_cw) |
1584 FIELD_PREP(B_DPD_PWR_CW, pwr_cw) |
1585 FIELD_PREP(B_DPD_REF, ref);
1586}
1587
1588static void rtw8852b_set_txpwr_ref(struct rtw89_dev *rtwdev,
1589 enum rtw89_phy_idx phy_idx)
1590{
1591 static const u32 addr[RF_PATH_NUM_8852B] = {0x5800, 0x7800};
1592 const u32 mask = B_DPD_TSSI_CW | B_DPD_PWR_CW | B_DPD_REF;
1593 const u8 ofst_ofdm = 0x4;
1594 const u8 ofst_cck = 0x8;
1595 const s16 ref_ofdm = 0;
1596 const s16 ref_cck = 0;
1597 u32 val;
1598 u8 i;
1599
1600 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n");
1601
1602 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL,
1603 B_AX_PWR_REF, 0x0);
1604
1605 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n");
1606 val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm);
1607
1608 for (i = 0; i < RF_PATH_NUM_8852B; i++)
1609 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val,
1610 phy_idx);
1611
1612 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n");
1613 val = rtw8852b_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck);
1614
1615 for (i = 0; i < RF_PATH_NUM_8852B; i++)
1616 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val,
1617 phy_idx);
1618}
1619
1620static void rtw8852b_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev,
1621 u8 tx_shape_idx,
1622 enum rtw89_phy_idx phy_idx)
1623{
1624#define __DFIR_CFG_ADDR(i) (R_TXFIR0 + ((i) << 2))
1625#define __DFIR_CFG_MASK 0xffffffff
1626#define __DFIR_CFG_NR 8
1627#define __DECL_DFIR_PARAM(_name, _val...) \
1628 static const u32 param_ ## _name[] = {_val}; \
1629 static_assert(ARRAY_SIZE(param_ ## _name) == __DFIR_CFG_NR)
1630
1631 __DECL_DFIR_PARAM(flat,
1632 0x023D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053,
1633 0x00F86F9A, 0x06FAEF92, 0x00FE5FCC, 0x00FFDFF5);
1634 __DECL_DFIR_PARAM(sharp,
1635 0x023D83FF, 0x002C636A, 0x0013F204, 0x00008090,
1636 0x00F87FB0, 0x06F99F83, 0x00FDBFBA, 0x00003FF5);
1637 __DECL_DFIR_PARAM(sharp_14,
1638 0x023B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E,
1639 0x00FD8F92, 0x0602D011, 0x0001C02C, 0x00FFF00A);
1640 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1641 u8 ch = chan->channel;
1642 const u32 *param;
1643 u32 addr;
1644 int i;
1645
1646 if (ch > 14) {
1647 rtw89_warn(rtwdev,
1648 "set tx shape dfir by unknown ch: %d on 2G\n", ch);
1649 return;
1650 }
1651
1652 if (ch == 14)
1653 param = param_sharp_14;
1654 else
1655 param = tx_shape_idx == 0 ? param_flat : param_sharp;
1656
1657 for (i = 0; i < __DFIR_CFG_NR; i++) {
1658 addr = __DFIR_CFG_ADDR(i);
1659 rtw89_debug(rtwdev, RTW89_DBG_TXPWR,
1660 "set tx shape dfir: 0x%x: 0x%x\n", addr, param[i]);
1661 rtw89_phy_write32_idx(rtwdev, addr, __DFIR_CFG_MASK, param[i],
1662 phy_idx);
1663 }
1664
1665#undef __DECL_DFIR_PARAM
1666#undef __DFIR_CFG_NR
1667#undef __DFIR_CFG_MASK
1668#undef __DECL_CFG_ADDR
1669}
1670
1671static void rtw8852b_set_tx_shape(struct rtw89_dev *rtwdev,
1672 const struct rtw89_chan *chan,
1673 enum rtw89_phy_idx phy_idx)
1674{
1675 u8 band = chan->band_type;
1676 u8 regd = rtw89_regd_get(rtwdev, band);
1677 u8 tx_shape_cck = rtw89_8852b_tx_shape[band][RTW89_RS_CCK][regd];
1678 u8 tx_shape_ofdm = rtw89_8852b_tx_shape[band][RTW89_RS_OFDM][regd];
1679
1680 if (band == RTW89_BAND_2G)
1681 rtw8852b_bb_set_tx_shape_dfir(rtwdev, tx_shape_cck, phy_idx);
1682
1683 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG,
1684 tx_shape_ofdm);
1685}
1686
1687static void rtw8852b_set_txpwr(struct rtw89_dev *rtwdev,
1688 const struct rtw89_chan *chan,
1689 enum rtw89_phy_idx phy_idx)
1690{
1691 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx);
1692 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx);
1693 rtw8852b_set_tx_shape(rtwdev, chan, phy_idx);
1694 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx);
1695 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1696}
1697
1698static void rtw8852b_set_txpwr_ctrl(struct rtw89_dev *rtwdev,
1699 enum rtw89_phy_idx phy_idx)
1700{
1701 rtw8852b_set_txpwr_ref(rtwdev, phy_idx);
1702}
1703
1704static
1705void rtw8852b_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
1706 s8 pw_ofst, enum rtw89_mac_idx mac_idx)
1707{
1708 u32 reg;
1709
1710 if (pw_ofst < -16 || pw_ofst > 15) {
1711 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst);
1712 return;
1713 }
1714
1715 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_CTRL, mac_idx);
1716 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN);
1717
1718 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx);
1719 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1720
1721 pw_ofst = max_t(s8, pw_ofst - 3, -16);
1722 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx);
1723 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, pw_ofst);
1724}
1725
1726static int
1727rtw8852b_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
1728{
1729 int ret;
1730
1731 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333);
1732 if (ret)
1733 return ret;
1734
1735 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000);
1736 if (ret)
1737 return ret;
1738
1739 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff);
1740 if (ret)
1741 return ret;
1742
1743 rtw8852b_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ?
1744 RTW89_MAC_1 : RTW89_MAC_0);
1745
1746 return 0;
1747}
1748
1749void rtw8852b_bb_set_plcp_tx(struct rtw89_dev *rtwdev)
1750{
1751 const struct rtw89_reg3_def *def = rtw8852b_pmac_ht20_mcs7_tbl;
1752 u8 i;
1753
1754 for (i = 0; i < ARRAY_SIZE(rtw8852b_pmac_ht20_mcs7_tbl); i++, def++)
1755 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data);
1756}
1757
1758static void rtw8852b_stop_pmac_tx(struct rtw89_dev *rtwdev,
1759 struct rtw8852b_bb_pmac_info *tx_info,
1760 enum rtw89_phy_idx idx)
1761{
1762 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx");
1763 if (tx_info->mode == CONT_TX)
1764 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, idx);
1765 else if (tx_info->mode == PKTS_TX)
1766 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, idx);
1767}
1768
1769static void rtw8852b_start_pmac_tx(struct rtw89_dev *rtwdev,
1770 struct rtw8852b_bb_pmac_info *tx_info,
1771 enum rtw89_phy_idx idx)
1772{
1773 enum rtw8852b_pmac_mode mode = tx_info->mode;
1774 u32 pkt_cnt = tx_info->tx_cnt;
1775 u16 period = tx_info->period;
1776
1777 if (mode == CONT_TX && !tx_info->is_cck) {
1778 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, idx);
1779 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start");
1780 } else if (mode == PKTS_TX) {
1781 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, idx);
1782 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD,
1783 B_PMAC_TX_PRD_MSK, period, idx);
1784 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK,
1785 pkt_cnt, idx);
1786 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start");
1787 }
1788
1789 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx);
1790 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx);
1791}
1792
1793void rtw8852b_bb_set_pmac_tx(struct rtw89_dev *rtwdev,
1794 struct rtw8852b_bb_pmac_info *tx_info,
1795 enum rtw89_phy_idx idx)
1796{
1797 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1798
1799 if (!tx_info->en_pmac_tx) {
1800 rtw8852b_stop_pmac_tx(rtwdev, tx_info, idx);
1801 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx);
1802 if (chan->band_type == RTW89_BAND_2G)
1803 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS);
1804 return;
1805 }
1806
1807 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable");
1808
1809 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx);
1810 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx);
1811 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, idx);
1812 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx);
1813 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx);
1814 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS);
1815 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx);
1816
1817 rtw8852b_start_pmac_tx(rtwdev, tx_info, idx);
1818}
1819
1820void rtw8852b_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable,
1821 u16 tx_cnt, u16 period, u16 tx_time,
1822 enum rtw89_phy_idx idx)
1823{
1824 struct rtw8852b_bb_pmac_info tx_info = {0};
1825
1826 tx_info.en_pmac_tx = enable;
1827 tx_info.is_cck = 0;
1828 tx_info.mode = PKTS_TX;
1829 tx_info.tx_cnt = tx_cnt;
1830 tx_info.period = period;
1831 tx_info.tx_time = tx_time;
1832
1833 rtw8852b_bb_set_pmac_tx(rtwdev, &tx_info, idx);
1834}
1835
1836void rtw8852b_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm,
1837 enum rtw89_phy_idx idx)
1838{
1839 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm);
1840
1841 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1842 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx);
1843}
1844
1845void rtw8852b_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path)
1846{
1847 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0);
1848
1849 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path);
1850
1851 if (tx_path == RF_PATH_A) {
1852 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1);
1853 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
1854 } else if (tx_path == RF_PATH_B) {
1855 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2);
1856 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0);
1857 } else if (tx_path == RF_PATH_AB) {
1858 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 3);
1859 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4);
1860 } else {
1861 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path");
1862 }
1863}
1864
1865void rtw8852b_bb_tx_mode_switch(struct rtw89_dev *rtwdev,
1866 enum rtw89_phy_idx idx, u8 mode)
1867{
1868 if (mode != 0)
1869 return;
1870
1871 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch");
1872
1873 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx);
1874 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx);
1875 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx);
1876 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx);
1877 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx);
1878 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx);
1879 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx);
1880}
1881
1882void rtw8852b_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
1883 struct rtw8852b_bb_tssi_bak *bak)
1884{
1885 s32 tmp;
1886
1887 bak->tx_path = rtw89_phy_read32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, idx);
1888 bak->rx_path = rtw89_phy_read32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, idx);
1889 bak->p0_rfmode = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, idx);
1890 bak->p0_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, idx);
1891 bak->p1_rfmode = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, idx);
1892 bak->p1_rfmode_ftm = rtw89_phy_read32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, idx);
1893 tmp = rtw89_phy_read32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, idx);
1894 bak->tx_pwr = sign_extend32(tmp, 8);
1895}
1896
1897void rtw8852b_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx,
1898 const struct rtw8852b_bb_tssi_bak *bak)
1899{
1900 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, bak->tx_path, idx);
1901 if (bak->tx_path == RF_AB)
1902 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x4);
1903 else
1904 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 0x0);
1905 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, bak->rx_path, idx);
1906 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx);
1907 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE, MASKDWORD, bak->p0_rfmode, idx);
1908 rtw89_phy_write32_idx(rtwdev, R_P0_RFMODE_FTM_RX, MASKDWORD, bak->p0_rfmode_ftm, idx);
1909 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE, MASKDWORD, bak->p1_rfmode, idx);
1910 rtw89_phy_write32_idx(rtwdev, R_P1_RFMODE_FTM_RX, MASKDWORD, bak->p1_rfmode_ftm, idx);
1911 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, bak->tx_pwr, idx);
1912}
1913
1914static void rtw8852b_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en)
1915{
1916 rtw89_phy_write_reg3_tbl(rtwdev, bt_en ? &rtw8852b_btc_preagc_en_defs_tbl :
1917 &rtw8852b_btc_preagc_dis_defs_tbl);
1918}
1919
1920static void rtw8852b_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
1921{
1922 if (btg) {
1923 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1924 B_PATH0_BT_SHARE_V1, 0x1);
1925 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1926 B_PATH0_BTG_PATH_V1, 0x0);
1927 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
1928 B_PATH1_G_LNA6_OP1DB_V1, 0x20);
1929 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
1930 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30);
1931 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1932 B_PATH1_BT_SHARE_V1, 0x1);
1933 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1934 B_PATH1_BTG_PATH_V1, 0x1);
1935 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0);
1936 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x1);
1937 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x2);
1938 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1939 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1940 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x1);
1941 } else {
1942 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1,
1943 B_PATH0_BT_SHARE_V1, 0x0);
1944 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1,
1945 B_PATH0_BTG_PATH_V1, 0x0);
1946 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1,
1947 B_PATH1_G_LNA6_OP1DB_V1, 0x1a);
1948 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1,
1949 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a);
1950 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1,
1951 B_PATH1_BT_SHARE_V1, 0x0);
1952 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1,
1953 B_PATH1_BTG_PATH_V1, 0x0);
1954 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc);
1955 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_BT_SHARE, 0x0);
1956 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_BT_SEG0, 0x0);
1957 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN_V1,
1958 B_BT_DYN_DC_EST_EN_MSK, 0x1);
1959 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 0x0);
1960 }
1961}
1962
1963void rtw8852b_bb_ctrl_rx_path(struct rtw89_dev *rtwdev,
1964 enum rtw89_rf_path_bit rx_path)
1965{
1966 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
1967 u32 rst_mask0;
1968 u32 rst_mask1;
1969
1970 if (rx_path == RF_A) {
1971 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 1);
1972 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 1);
1973 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 1);
1974 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1975 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1976 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1977 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1978 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1979 } else if (rx_path == RF_B) {
1980 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 2);
1981 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 2);
1982 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 2);
1983 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
1984 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
1985 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1986 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
1987 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
1988 } else if (rx_path == RF_AB) {
1989 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD_V1, B_ANT_RX_SEG0, 3);
1990 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG0, 3);
1991 rtw89_phy_write32_mask(rtwdev, R_FC0_BW_V1, B_ANT_RX_1RCCA_SEG1, 3);
1992 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
1993 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
1994 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 4);
1995 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
1996 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
1997 }
1998
1999 rtw8852b_set_gain_offset(rtwdev, chan->subband_type, RTW89_PHY_0);
2000
2001 if (chan->band_type == RTW89_BAND_2G &&
2002 (rx_path == RF_B || rx_path == RF_AB))
2003 rtw8852b_ctrl_btg(rtwdev, true);
2004 else
2005 rtw8852b_ctrl_btg(rtwdev, false);
2006
2007 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI;
2008 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI;
2009 if (rx_path == RF_A) {
2010 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1);
2011 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3);
2012 } else {
2013 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1);
2014 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3);
2015 }
2016}
2017
2018static void rtw8852b_bb_ctrl_rf_mode_rx_path(struct rtw89_dev *rtwdev,
2019 enum rtw89_rf_path_bit rx_path)
2020{
2021 if (rx_path == RF_A) {
2022 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
2023 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
2024 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
2025 B_P0_RFMODE_FTM_RX, 0x333);
2026 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
2027 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
2028 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
2029 B_P1_RFMODE_FTM_RX, 0x111);
2030 } else if (rx_path == RF_B) {
2031 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
2032 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1111111);
2033 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
2034 B_P0_RFMODE_FTM_RX, 0x111);
2035 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
2036 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
2037 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
2038 B_P1_RFMODE_FTM_RX, 0x333);
2039 } else if (rx_path == RF_AB) {
2040 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE,
2041 B_P0_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
2042 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE_FTM_RX,
2043 B_P0_RFMODE_FTM_RX, 0x333);
2044 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE,
2045 B_P1_RFMODE_ORI_TXRX_FTM_TX, 0x1233312);
2046 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE_FTM_RX,
2047 B_P1_RFMODE_FTM_RX, 0x333);
2048 }
2049}
2050
2051static void rtw8852b_bb_cfg_txrx_path(struct rtw89_dev *rtwdev)
2052{
2053 struct rtw89_hal *hal = &rtwdev->hal;
2054 enum rtw89_rf_path_bit rx_path = hal->antenna_rx ? hal->antenna_rx : RF_AB;
2055
2056 rtw8852b_bb_ctrl_rx_path(rtwdev, rx_path);
2057 rtw8852b_bb_ctrl_rf_mode_rx_path(rtwdev, rx_path);
2058
2059 if (rtwdev->hal.rx_nss == 1) {
2060 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0);
2061 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0);
2062 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0);
2063 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0);
2064 } else {
2065 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1);
2066 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1);
2067 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1);
2068 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1);
2069 }
2070
2071 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0);
2072}
2073
2074static u8 rtw8852b_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path)
2075{
2076 if (rtwdev->is_tssi_mode[rf_path]) {
2077 u32 addr = 0x1c10 + (rf_path << 13);
2078
2079 return rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000);
2080 }
2081
2082 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2083 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0);
2084 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1);
2085
2086 fsleep(200);
2087
2088 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL);
2089}
2090
2091static void rtw8852b_btc_set_rfe(struct rtw89_dev *rtwdev)
2092{
2093 struct rtw89_btc *btc = &rtwdev->btc;
2094 struct rtw89_btc_module *module = &btc->mdinfo;
2095
2096 module->rfe_type = rtwdev->efuse.rfe_type;
2097 module->cv = rtwdev->hal.cv;
2098 module->bt_solo = 0;
2099 module->switch_type = BTC_SWITCH_INTERNAL;
2100
2101 if (module->rfe_type > 0)
2102 module->ant.num = module->rfe_type % 2 ? 2 : 3;
2103 else
2104 module->ant.num = 2;
2105
2106 module->ant.diversity = 0;
2107 module->ant.isolation = 10;
2108
2109 if (module->ant.num == 3) {
2110 module->ant.type = BTC_ANT_DEDICATED;
2111 module->bt_pos = BTC_BT_ALONE;
2112 } else {
2113 module->ant.type = BTC_ANT_SHARED;
2114 module->bt_pos = BTC_BT_BTG;
2115 }
2116}
2117
2118static
2119void rtw8852b_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val)
2120{
2121 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000);
2122 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group);
2123 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val);
2124 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0);
2125}
2126
2127static void rtw8852b_btc_init_cfg(struct rtw89_dev *rtwdev)
2128{
2129 struct rtw89_btc *btc = &rtwdev->btc;
2130 struct rtw89_btc_module *module = &btc->mdinfo;
2131 const struct rtw89_chip_info *chip = rtwdev->chip;
2132 const struct rtw89_mac_ax_coex coex_params = {
2133 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE,
2134 .direction = RTW89_MAC_AX_COEX_INNER,
2135 };
2136
2137 /* PTA init */
2138 rtw89_mac_coex_init(rtwdev, &coex_params);
2139
2140 /* set WL Tx response = Hi-Pri */
2141 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true);
2142 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true);
2143
2144 /* set rf gnt debug off */
2145 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0);
2146 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0);
2147
2148 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */
2149 if (module->ant.type == BTC_ANT_SHARED) {
2150 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff);
2151 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff);
2152 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */
2153 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
2154 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x55f);
2155 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */
2156 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_SS_GROUP, 0x5df);
2157 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_SS_GROUP, 0x5df);
2158 rtw8852b_set_trx_mask(rtwdev, RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff);
2159 rtw8852b_set_trx_mask(rtwdev, RF_PATH_B, BTC_BT_TX_GROUP, 0x5ff);
2160 }
2161
2162 /* set PTA break table */
2163 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM);
2164
2165 /* enable BT counter 0xda40[16,2] = 2b'11 */
2166 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN);
2167 btc->cx.wl.status.map.init_ok = true;
2168}
2169
2170static
2171void rtw8852b_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state)
2172{
2173 u32 bitmap;
2174 u32 reg;
2175
2176 switch (map) {
2177 case BTC_PRI_MASK_TX_RESP:
2178 reg = R_BTC_BT_COEX_MSK_TABLE;
2179 bitmap = B_BTC_PRI_MASK_TX_RESP_V1;
2180 break;
2181 case BTC_PRI_MASK_BEACON:
2182 reg = R_AX_WL_PRI_MSK;
2183 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ;
2184 break;
2185 case BTC_PRI_MASK_RX_CCK:
2186 reg = R_BTC_BT_COEX_MSK_TABLE;
2187 bitmap = B_BTC_PRI_MASK_RXCCK_V1;
2188 break;
2189 default:
2190 return;
2191 }
2192
2193 if (state)
2194 rtw89_write32_set(rtwdev, reg, bitmap);
2195 else
2196 rtw89_write32_clr(rtwdev, reg, bitmap);
2197}
2198
2199union rtw8852b_btc_wl_txpwr_ctrl {
2200 u32 txpwr_val;
2201 struct {
2202 union {
2203 u16 ctrl_all_time;
2204 struct {
2205 s16 data:9;
2206 u16 rsvd:6;
2207 u16 flag:1;
2208 } all_time;
2209 };
2210 union {
2211 u16 ctrl_gnt_bt;
2212 struct {
2213 s16 data:9;
2214 u16 rsvd:7;
2215 } gnt_bt;
2216 };
2217 };
2218} __packed;
2219
2220static void
2221rtw8852b_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val)
2222{
2223 union rtw8852b_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val };
2224 s32 val;
2225
2226#define __write_ctrl(_reg, _msk, _val, _en, _cond) \
2227do { \
2228 u32 _wrt = FIELD_PREP(_msk, _val); \
2229 BUILD_BUG_ON(!!(_msk & _en)); \
2230 if (_cond) \
2231 _wrt |= _en; \
2232 else \
2233 _wrt &= ~_en; \
2234 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \
2235 _msk | _en, _wrt); \
2236} while (0)
2237
2238 switch (arg.ctrl_all_time) {
2239 case 0xffff:
2240 val = 0;
2241 break;
2242 default:
2243 val = arg.all_time.data;
2244 break;
2245 }
2246
2247 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK,
2248 val, B_AX_FORCE_PWR_BY_RATE_EN,
2249 arg.ctrl_all_time != 0xffff);
2250
2251 switch (arg.ctrl_gnt_bt) {
2252 case 0xffff:
2253 val = 0;
2254 break;
2255 default:
2256 val = arg.gnt_bt.data;
2257 break;
2258 }
2259
2260 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val,
2261 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff);
2262
2263#undef __write_ctrl
2264}
2265
2266static
2267s8 rtw8852b_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val)
2268{
2269 return clamp_t(s8, val, -100, 0) + 100;
2270}
2271
2272static
2273void rtw8852b_btc_update_bt_cnt(struct rtw89_dev *rtwdev)
2274{
2275 /* Feature move to firmware */
2276}
2277
2278static void rtw8852b_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state)
2279{
2280 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000);
2281 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1);
2282 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x31);
2283
2284 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */
2285 if (state)
2286 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x579);
2287 else
2288 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x20);
2289
2290 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0);
2291}
2292
2293static void rtw8852b_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level)
2294{
2295}
2296
2297static void rtw8852b_fill_freq_with_ppdu(struct rtw89_dev *rtwdev,
2298 struct rtw89_rx_phy_ppdu *phy_ppdu,
2299 struct ieee80211_rx_status *status)
2300{
2301 u16 chan = phy_ppdu->chan_idx;
2302 u8 band;
2303
2304 if (chan == 0)
2305 return;
2306
2307 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
2308 status->freq = ieee80211_channel_to_frequency(chan, band);
2309 status->band = band;
2310}
2311
2312static void rtw8852b_query_ppdu(struct rtw89_dev *rtwdev,
2313 struct rtw89_rx_phy_ppdu *phy_ppdu,
2314 struct ieee80211_rx_status *status)
2315{
2316 u8 path;
2317 u8 *rx_power = phy_ppdu->rssi;
2318
2319 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B]));
2320 for (path = 0; path < rtwdev->chip->rf_path_num; path++) {
2321 status->chains |= BIT(path);
2322 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]);
2323 }
2324 if (phy_ppdu->valid)
2325 rtw8852b_fill_freq_with_ppdu(rtwdev, phy_ppdu, status);
2326}
2327
2328static int rtw8852b_mac_enable_bb_rf(struct rtw89_dev *rtwdev)
2329{
2330 int ret;
2331
2332 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN,
2333 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2334 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, B_AX_REG_ZCDC_H_MASK, 0x1);
2335 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2336 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2337 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG);
2338
2339 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC7,
2340 FULL_BIT_MASK);
2341 if (ret)
2342 return ret;
2343
2344 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC7,
2345 FULL_BIT_MASK);
2346 if (ret)
2347 return ret;
2348
2349 rtw89_write8(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_XYN_CYCLE);
2350
2351 return 0;
2352}
2353
2354static int rtw8852b_mac_disable_bb_rf(struct rtw89_dev *rtwdev)
2355{
2356 u8 wl_rfc_s0;
2357 u8 wl_rfc_s1;
2358 int ret;
2359
2360 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN,
2361 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN);
2362
2363 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, &wl_rfc_s0);
2364 if (ret)
2365 return ret;
2366 wl_rfc_s0 &= ~XTAL_SI_RF00S_EN;
2367 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, wl_rfc_s0,
2368 FULL_BIT_MASK);
2369 if (ret)
2370 return ret;
2371
2372 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, &wl_rfc_s1);
2373 if (ret)
2374 return ret;
2375 wl_rfc_s1 &= ~XTAL_SI_RF10S_EN;
2376 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, wl_rfc_s1,
2377 FULL_BIT_MASK);
2378 return ret;
2379}
2380
2381static const struct rtw89_chip_ops rtw8852b_chip_ops = {
2382 .enable_bb_rf = rtw8852b_mac_enable_bb_rf,
2383 .disable_bb_rf = rtw8852b_mac_disable_bb_rf,
2384 .bb_reset = rtw8852b_bb_reset,
2385 .bb_sethw = rtw8852b_bb_sethw,
2386 .read_rf = rtw89_phy_read_rf_v1,
2387 .write_rf = rtw89_phy_write_rf_v1,
2388 .set_channel = rtw8852b_set_channel,
2389 .set_channel_help = rtw8852b_set_channel_help,
2390 .read_efuse = rtw8852b_read_efuse,
2391 .read_phycap = rtw8852b_read_phycap,
2392 .fem_setup = NULL,
2393 .rfk_init = rtw8852b_rfk_init,
2394 .rfk_channel = rtw8852b_rfk_channel,
2395 .rfk_band_changed = rtw8852b_rfk_band_changed,
2396 .rfk_scan = rtw8852b_rfk_scan,
2397 .rfk_track = rtw8852b_rfk_track,
2398 .power_trim = rtw8852b_power_trim,
2399 .set_txpwr = rtw8852b_set_txpwr,
2400 .set_txpwr_ctrl = rtw8852b_set_txpwr_ctrl,
2401 .init_txpwr_unit = rtw8852b_init_txpwr_unit,
2402 .get_thermal = rtw8852b_get_thermal,
2403 .ctrl_btg = rtw8852b_ctrl_btg,
2404 .query_ppdu = rtw8852b_query_ppdu,
2405 .bb_ctrl_btc_preagc = rtw8852b_bb_ctrl_btc_preagc,
2406 .cfg_txrx_path = rtw8852b_bb_cfg_txrx_path,
2407 .set_txpwr_ul_tb_offset = rtw8852b_set_txpwr_ul_tb_offset,
2408 .pwr_on_func = rtw8852b_pwr_on_func,
2409 .pwr_off_func = rtw8852b_pwr_off_func,
2410 .fill_txdesc = rtw89_core_fill_txdesc,
2411 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc,
2412 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path,
2413 .mac_cfg_gnt = rtw89_mac_cfg_gnt,
2414 .stop_sch_tx = rtw89_mac_stop_sch_tx,
2415 .resume_sch_tx = rtw89_mac_resume_sch_tx,
2416 .h2c_dctl_sec_cam = NULL,
2417
2418 .btc_set_rfe = rtw8852b_btc_set_rfe,
2419 .btc_init_cfg = rtw8852b_btc_init_cfg,
2420 .btc_set_wl_pri = rtw8852b_btc_set_wl_pri,
2421 .btc_set_wl_txpwr_ctrl = rtw8852b_btc_set_wl_txpwr_ctrl,
2422 .btc_get_bt_rssi = rtw8852b_btc_get_bt_rssi,
2423 .btc_update_bt_cnt = rtw8852b_btc_update_bt_cnt,
2424 .btc_wl_s1_standby = rtw8852b_btc_wl_s1_standby,
2425 .btc_set_wl_rx_gain = rtw8852b_btc_set_wl_rx_gain,
2426 .btc_set_policy = rtw89_btc_set_policy,
2427};
2428
2429const struct rtw89_chip_info rtw8852b_chip_info = {
2430 .chip_id = RTL8852B,
2431 .ops = &rtw8852b_chip_ops,
2432 .fw_name = "rtw89/rtw8852b_fw.bin",
2433 .fifo_size = 196608,
2434 .dle_scc_rsvd_size = 98304,
2435 .max_amsdu_limit = 3500,
2436 .dis_2g_40m_ul_ofdma = true,
2437 .rsvd_ple_ofst = 0x2f800,
2438 .hfc_param_ini = rtw8852b_hfc_param_ini_pcie,
2439 .dle_mem = rtw8852b_dle_mem_pcie,
2440 .rf_base_addr = {0xe000, 0xf000},
2441 .pwr_on_seq = NULL,
2442 .pwr_off_seq = NULL,
2443 .bb_table = &rtw89_8852b_phy_bb_table,
2444 .bb_gain_table = &rtw89_8852b_phy_bb_gain_table,
2445 .rf_table = {&rtw89_8852b_phy_radioa_table,
2446 &rtw89_8852b_phy_radiob_table,},
2447 .nctl_table = &rtw89_8852b_phy_nctl_table,
2448 .byr_table = &rtw89_8852b_byr_table,
2449 .txpwr_lmt_2g = &rtw89_8852b_txpwr_lmt_2g,
2450 .txpwr_lmt_5g = &rtw89_8852b_txpwr_lmt_5g,
2451 .txpwr_lmt_ru_2g = &rtw89_8852b_txpwr_lmt_ru_2g,
2452 .txpwr_lmt_ru_5g = &rtw89_8852b_txpwr_lmt_ru_5g,
2453 .txpwr_factor_rf = 2,
2454 .txpwr_factor_mac = 1,
2455 .dig_table = NULL,
2456 .dig_regs = &rtw8852b_dig_regs,
2457 .tssi_dbw_table = NULL,
2458 .support_chanctx_num = 0,
2459 .support_bands = BIT(NL80211_BAND_2GHZ) |
2460 BIT(NL80211_BAND_5GHZ),
2461 .support_bw160 = false,
2462 .support_ul_tb_ctrl = true,
2463 .hw_sec_hdr = false,
2464 .rf_path_num = 2,
2465 .tx_nss = 2,
2466 .rx_nss = 2,
2467 .acam_num = 128,
2468 .bcam_num = 10,
2469 .scam_num = 128,
2470 .bacam_num = 2,
2471 .bacam_dynamic_num = 4,
2472 .bacam_v1 = false,
2473 .sec_ctrl_efuse_size = 4,
2474 .physical_efuse_size = 1216,
2475 .logical_efuse_size = 2048,
2476 .limit_efuse_size = 1280,
2477 .dav_phy_efuse_size = 96,
2478 .dav_log_efuse_size = 16,
2479 .phycap_addr = 0x580,
2480 .phycap_size = 128,
2481 .para_ver = 0,
2482 .wlcx_desired = 0x05050000,
2483 .btcx_desired = 0x5,
2484 .scbd = 0x1,
2485 .mailbox = 0x1,
2486 .btc_fwinfo_buf = 1024,
2487
2488 .fcxbtcrpt_ver = 1,
2489 .fcxtdma_ver = 1,
2490 .fcxslots_ver = 1,
2491 .fcxcysta_ver = 2,
2492 .fcxstep_ver = 2,
2493 .fcxnullsta_ver = 1,
2494 .fcxmreg_ver = 1,
2495 .fcxgpiodbg_ver = 1,
2496 .fcxbtver_ver = 1,
2497 .fcxbtscan_ver = 1,
2498 .fcxbtafh_ver = 1,
2499 .fcxbtdevinfo_ver = 1,
2500 .afh_guard_ch = 6,
2501 .wl_rssi_thres = rtw89_btc_8852b_wl_rssi_thres,
2502 .bt_rssi_thres = rtw89_btc_8852b_bt_rssi_thres,
2503 .rssi_tol = 2,
2504 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852b_mon_reg),
2505 .mon_reg = rtw89_btc_8852b_mon_reg,
2506 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_ul),
2507 .rf_para_ulink = rtw89_btc_8852b_rf_ul,
2508 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852b_rf_dl),
2509 .rf_para_dlink = rtw89_btc_8852b_rf_dl,
2510 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) |
2511 BIT(RTW89_PS_MODE_CLK_GATED) |
2512 BIT(RTW89_PS_MODE_PWR_GATED),
2513 .low_power_hci_modes = 0,
2514 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD,
2515 .hci_func_en_addr = R_AX_HCI_FUNC_EN,
2516 .h2c_desc_size = sizeof(struct rtw89_txwd_body),
2517 .txwd_body_size = sizeof(struct rtw89_txwd_body),
2518 .h2c_ctrl_reg = R_AX_H2CREG_CTRL,
2519 .h2c_regs = rtw8852b_h2c_regs,
2520 .c2h_ctrl_reg = R_AX_C2HREG_CTRL,
2521 .c2h_regs = rtw8852b_c2h_regs,
2522 .page_regs = &rtw8852b_page_regs,
2523 .cfo_src_fd = true,
2524 .dcfo_comp = &rtw8852b_dcfo_comp,
2525 .dcfo_comp_sft = 3,
2526 .imr_info = &rtw8852b_imr_info,
2527 .rrsr_cfgs = &rtw8852b_rrsr_cfgs,
2528 .dma_ch_mask = BIT(RTW89_DMA_ACH4) | BIT(RTW89_DMA_ACH5) |
2529 BIT(RTW89_DMA_ACH6) | BIT(RTW89_DMA_ACH7) |
2530 BIT(RTW89_DMA_B1MG) | BIT(RTW89_DMA_B1HI),
2531};
2532EXPORT_SYMBOL(rtw8852b_chip_info);
2533
2534MODULE_FIRMWARE("rtw89/rtw8852b_fw.bin");
2535MODULE_AUTHOR("Realtek Corporation");
2536MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852B driver");
2537MODULE_LICENSE("Dual BSD/GPL");