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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5#ifndef __RTW89_CORE_H__
6#define __RTW89_CORE_H__
7
8#include <linux/average.h>
9#include <linux/bitfield.h>
10#include <linux/firmware.h>
11#include <linux/iopoll.h>
12#include <linux/workqueue.h>
13#include <net/mac80211.h>
14
15struct rtw89_dev;
16struct rtw89_pci_info;
17
18extern const struct ieee80211_ops rtw89_ops;
19
20#define MASKBYTE0 0xff
21#define MASKBYTE1 0xff00
22#define MASKBYTE2 0xff0000
23#define MASKBYTE3 0xff000000
24#define MASKBYTE4 0xff00000000ULL
25#define MASKHWORD 0xffff0000
26#define MASKLWORD 0x0000ffff
27#define MASKDWORD 0xffffffff
28#define RFREG_MASK 0xfffff
29#define INV_RF_DATA 0xffffffff
30
31#define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2)
32#define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
33#define CFO_TRACK_MAX_USER 64
34#define MAX_RSSI 110
35#define RSSI_FACTOR 1
36#define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
37#define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
38#define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64)
39
40#define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
41#define RTW89_HTC_VARIANT_HE 3
42#define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
43#define RTW89_HTC_VARIANT_HE_CID_OM 1
44#define RTW89_HTC_VARIANT_HE_CID_CAS 6
45#define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
46
47#define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
48enum htc_om_channel_width {
49 HTC_OM_CHANNEL_WIDTH_20 = 0,
50 HTC_OM_CHANNEL_WIDTH_40 = 1,
51 HTC_OM_CHANNEL_WIDTH_80 = 2,
52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
53};
54#define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
55#define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
56#define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
57#define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
58#define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
59#define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
60
61#define RTW89_TF_PAD GENMASK(11, 0)
62#define RTW89_TF_BASIC_USER_INFO_SZ 6
63
64#define RTW89_GET_TF_USER_INFO_AID12(data) \
65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
66#define RTW89_GET_TF_USER_INFO_RUA(data) \
67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
68#define RTW89_GET_TF_USER_INFO_UL_MCS(data) \
69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
70
71enum rtw89_subband {
72 RTW89_CH_2G = 0,
73 RTW89_CH_5G_BAND_1 = 1,
74 /* RTW89_CH_5G_BAND_2 = 2, unused */
75 RTW89_CH_5G_BAND_3 = 3,
76 RTW89_CH_5G_BAND_4 = 4,
77
78 RTW89_CH_6G_BAND_IDX0, /* Low */
79 RTW89_CH_6G_BAND_IDX1, /* Low */
80 RTW89_CH_6G_BAND_IDX2, /* Mid */
81 RTW89_CH_6G_BAND_IDX3, /* Mid */
82 RTW89_CH_6G_BAND_IDX4, /* High */
83 RTW89_CH_6G_BAND_IDX5, /* High */
84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
86
87 RTW89_SUBBAND_NR,
88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
89};
90
91enum rtw89_gain_offset {
92 RTW89_GAIN_OFFSET_2G_CCK,
93 RTW89_GAIN_OFFSET_2G_OFDM,
94 RTW89_GAIN_OFFSET_5G_LOW,
95 RTW89_GAIN_OFFSET_5G_MID,
96 RTW89_GAIN_OFFSET_5G_HIGH,
97
98 RTW89_GAIN_OFFSET_NR,
99};
100
101enum rtw89_hci_type {
102 RTW89_HCI_TYPE_PCIE,
103 RTW89_HCI_TYPE_USB,
104 RTW89_HCI_TYPE_SDIO,
105};
106
107enum rtw89_core_chip_id {
108 RTL8852A,
109 RTL8852B,
110 RTL8852C,
111};
112
113enum rtw89_cv {
114 CHIP_CAV,
115 CHIP_CBV,
116 CHIP_CCV,
117 CHIP_CDV,
118 CHIP_CEV,
119 CHIP_CFV,
120 CHIP_CV_MAX,
121 CHIP_CV_INVALID = CHIP_CV_MAX,
122};
123
124enum rtw89_core_tx_type {
125 RTW89_CORE_TX_TYPE_DATA,
126 RTW89_CORE_TX_TYPE_MGMT,
127 RTW89_CORE_TX_TYPE_FWCMD,
128};
129
130enum rtw89_core_rx_type {
131 RTW89_CORE_RX_TYPE_WIFI = 0,
132 RTW89_CORE_RX_TYPE_PPDU_STAT = 1,
133 RTW89_CORE_RX_TYPE_CHAN_INFO = 2,
134 RTW89_CORE_RX_TYPE_BB_SCOPE = 3,
135 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4,
136 RTW89_CORE_RX_TYPE_SS2FW = 5,
137 RTW89_CORE_RX_TYPE_TX_REPORT = 6,
138 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7,
139 RTW89_CORE_RX_TYPE_DFS_REPORT = 8,
140 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9,
141 RTW89_CORE_RX_TYPE_C2H = 10,
142 RTW89_CORE_RX_TYPE_CSI = 11,
143 RTW89_CORE_RX_TYPE_CQI = 12,
144 RTW89_CORE_RX_TYPE_H2C = 13,
145 RTW89_CORE_RX_TYPE_FWDL = 14,
146};
147
148enum rtw89_txq_flags {
149 RTW89_TXQ_F_AMPDU = 0,
150 RTW89_TXQ_F_BLOCK_BA = 1,
151 RTW89_TXQ_F_FORBID_BA = 2,
152};
153
154enum rtw89_net_type {
155 RTW89_NET_TYPE_NO_LINK = 0,
156 RTW89_NET_TYPE_AD_HOC = 1,
157 RTW89_NET_TYPE_INFRA = 2,
158 RTW89_NET_TYPE_AP_MODE = 3,
159};
160
161enum rtw89_wifi_role {
162 RTW89_WIFI_ROLE_NONE,
163 RTW89_WIFI_ROLE_STATION,
164 RTW89_WIFI_ROLE_AP,
165 RTW89_WIFI_ROLE_AP_VLAN,
166 RTW89_WIFI_ROLE_ADHOC,
167 RTW89_WIFI_ROLE_ADHOC_MASTER,
168 RTW89_WIFI_ROLE_MESH_POINT,
169 RTW89_WIFI_ROLE_MONITOR,
170 RTW89_WIFI_ROLE_P2P_DEVICE,
171 RTW89_WIFI_ROLE_P2P_CLIENT,
172 RTW89_WIFI_ROLE_P2P_GO,
173 RTW89_WIFI_ROLE_NAN,
174 RTW89_WIFI_ROLE_MLME_MAX
175};
176
177enum rtw89_upd_mode {
178 RTW89_ROLE_CREATE,
179 RTW89_ROLE_REMOVE,
180 RTW89_ROLE_TYPE_CHANGE,
181 RTW89_ROLE_INFO_CHANGE,
182 RTW89_ROLE_CON_DISCONN,
183 RTW89_ROLE_BAND_SW,
184 RTW89_ROLE_FW_RESTORE,
185};
186
187enum rtw89_self_role {
188 RTW89_SELF_ROLE_CLIENT,
189 RTW89_SELF_ROLE_AP,
190 RTW89_SELF_ROLE_AP_CLIENT
191};
192
193enum rtw89_msk_sO_el {
194 RTW89_NO_MSK,
195 RTW89_SMA,
196 RTW89_TMA,
197 RTW89_BSSID
198};
199
200enum rtw89_sch_tx_sel {
201 RTW89_SCH_TX_SEL_ALL,
202 RTW89_SCH_TX_SEL_HIQ,
203 RTW89_SCH_TX_SEL_MG0,
204 RTW89_SCH_TX_SEL_MACID,
205};
206
207/* RTW89_ADDR_CAM_SEC_NONE : not enabled
208 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
209 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
210 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
211 */
212enum rtw89_add_cam_sec_mode {
213 RTW89_ADDR_CAM_SEC_NONE = 0,
214 RTW89_ADDR_CAM_SEC_ALL_UNI = 1,
215 RTW89_ADDR_CAM_SEC_NORMAL = 2,
216 RTW89_ADDR_CAM_SEC_4GROUP = 3,
217};
218
219enum rtw89_sec_key_type {
220 RTW89_SEC_KEY_TYPE_NONE = 0,
221 RTW89_SEC_KEY_TYPE_WEP40 = 1,
222 RTW89_SEC_KEY_TYPE_WEP104 = 2,
223 RTW89_SEC_KEY_TYPE_TKIP = 3,
224 RTW89_SEC_KEY_TYPE_WAPI = 4,
225 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5,
226 RTW89_SEC_KEY_TYPE_CCMP128 = 6,
227 RTW89_SEC_KEY_TYPE_CCMP256 = 7,
228 RTW89_SEC_KEY_TYPE_GCMP128 = 8,
229 RTW89_SEC_KEY_TYPE_GCMP256 = 9,
230 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10,
231};
232
233enum rtw89_port {
234 RTW89_PORT_0 = 0,
235 RTW89_PORT_1 = 1,
236 RTW89_PORT_2 = 2,
237 RTW89_PORT_3 = 3,
238 RTW89_PORT_4 = 4,
239 RTW89_PORT_NUM
240};
241
242enum rtw89_band {
243 RTW89_BAND_2G = 0,
244 RTW89_BAND_5G = 1,
245 RTW89_BAND_6G = 2,
246 RTW89_BAND_MAX,
247};
248
249enum rtw89_hw_rate {
250 RTW89_HW_RATE_CCK1 = 0x0,
251 RTW89_HW_RATE_CCK2 = 0x1,
252 RTW89_HW_RATE_CCK5_5 = 0x2,
253 RTW89_HW_RATE_CCK11 = 0x3,
254 RTW89_HW_RATE_OFDM6 = 0x4,
255 RTW89_HW_RATE_OFDM9 = 0x5,
256 RTW89_HW_RATE_OFDM12 = 0x6,
257 RTW89_HW_RATE_OFDM18 = 0x7,
258 RTW89_HW_RATE_OFDM24 = 0x8,
259 RTW89_HW_RATE_OFDM36 = 0x9,
260 RTW89_HW_RATE_OFDM48 = 0xA,
261 RTW89_HW_RATE_OFDM54 = 0xB,
262 RTW89_HW_RATE_MCS0 = 0x80,
263 RTW89_HW_RATE_MCS1 = 0x81,
264 RTW89_HW_RATE_MCS2 = 0x82,
265 RTW89_HW_RATE_MCS3 = 0x83,
266 RTW89_HW_RATE_MCS4 = 0x84,
267 RTW89_HW_RATE_MCS5 = 0x85,
268 RTW89_HW_RATE_MCS6 = 0x86,
269 RTW89_HW_RATE_MCS7 = 0x87,
270 RTW89_HW_RATE_MCS8 = 0x88,
271 RTW89_HW_RATE_MCS9 = 0x89,
272 RTW89_HW_RATE_MCS10 = 0x8A,
273 RTW89_HW_RATE_MCS11 = 0x8B,
274 RTW89_HW_RATE_MCS12 = 0x8C,
275 RTW89_HW_RATE_MCS13 = 0x8D,
276 RTW89_HW_RATE_MCS14 = 0x8E,
277 RTW89_HW_RATE_MCS15 = 0x8F,
278 RTW89_HW_RATE_MCS16 = 0x90,
279 RTW89_HW_RATE_MCS17 = 0x91,
280 RTW89_HW_RATE_MCS18 = 0x92,
281 RTW89_HW_RATE_MCS19 = 0x93,
282 RTW89_HW_RATE_MCS20 = 0x94,
283 RTW89_HW_RATE_MCS21 = 0x95,
284 RTW89_HW_RATE_MCS22 = 0x96,
285 RTW89_HW_RATE_MCS23 = 0x97,
286 RTW89_HW_RATE_MCS24 = 0x98,
287 RTW89_HW_RATE_MCS25 = 0x99,
288 RTW89_HW_RATE_MCS26 = 0x9A,
289 RTW89_HW_RATE_MCS27 = 0x9B,
290 RTW89_HW_RATE_MCS28 = 0x9C,
291 RTW89_HW_RATE_MCS29 = 0x9D,
292 RTW89_HW_RATE_MCS30 = 0x9E,
293 RTW89_HW_RATE_MCS31 = 0x9F,
294 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100,
295 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101,
296 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102,
297 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103,
298 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104,
299 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105,
300 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106,
301 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107,
302 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108,
303 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109,
304 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110,
305 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111,
306 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112,
307 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113,
308 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114,
309 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115,
310 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116,
311 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117,
312 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118,
313 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119,
314 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120,
315 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121,
316 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122,
317 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123,
318 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124,
319 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125,
320 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126,
321 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127,
322 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128,
323 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129,
324 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130,
325 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131,
326 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132,
327 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133,
328 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134,
329 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135,
330 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136,
331 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137,
332 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138,
333 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139,
334 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180,
335 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181,
336 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182,
337 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183,
338 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184,
339 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185,
340 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186,
341 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187,
342 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188,
343 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189,
344 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A,
345 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B,
346 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190,
347 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191,
348 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192,
349 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193,
350 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194,
351 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195,
352 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196,
353 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197,
354 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198,
355 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199,
356 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A,
357 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B,
358 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0,
359 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1,
360 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2,
361 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3,
362 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4,
363 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5,
364 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6,
365 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7,
366 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8,
367 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9,
368 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA,
369 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB,
370 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0,
371 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1,
372 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2,
373 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3,
374 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4,
375 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5,
376 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6,
377 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7,
378 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8,
379 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9,
380 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA,
381 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB,
382 RTW89_HW_RATE_NR,
383
384 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
385 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
386};
387
388/* 2G channels,
389 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
390 */
391#define RTW89_2G_CH_NUM 14
392
393/* 5G channels,
394 * 36, 38, 40, 42, 44, 46, 48, 50,
395 * 52, 54, 56, 58, 60, 62, 64,
396 * 100, 102, 104, 106, 108, 110, 112, 114,
397 * 116, 118, 120, 122, 124, 126, 128, 130,
398 * 132, 134, 136, 138, 140, 142, 144,
399 * 149, 151, 153, 155, 157, 159, 161, 163,
400 * 165, 167, 169, 171, 173, 175, 177
401 */
402#define RTW89_5G_CH_NUM 53
403
404/* 6G channels,
405 * 1, 3, 5, 7, 9, 11, 13, 15,
406 * 17, 19, 21, 23, 25, 27, 29, 33,
407 * 35, 37, 39, 41, 43, 45, 47, 49,
408 * 51, 53, 55, 57, 59, 61, 65, 67,
409 * 69, 71, 73, 75, 77, 79, 81, 83,
410 * 85, 87, 89, 91, 93, 97, 99, 101,
411 * 103, 105, 107, 109, 111, 113, 115, 117,
412 * 119, 121, 123, 125, 129, 131, 133, 135,
413 * 137, 139, 141, 143, 145, 147, 149, 151,
414 * 153, 155, 157, 161, 163, 165, 167, 169,
415 * 171, 173, 175, 177, 179, 181, 183, 185,
416 * 187, 189, 193, 195, 197, 199, 201, 203,
417 * 205, 207, 209, 211, 213, 215, 217, 219,
418 * 221, 225, 227, 229, 231, 233, 235, 237,
419 * 239, 241, 243, 245, 247, 249, 251, 253,
420 */
421#define RTW89_6G_CH_NUM 120
422
423enum rtw89_rate_section {
424 RTW89_RS_CCK,
425 RTW89_RS_OFDM,
426 RTW89_RS_MCS, /* for HT/VHT/HE */
427 RTW89_RS_HEDCM,
428 RTW89_RS_OFFSET,
429 RTW89_RS_MAX,
430 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
431 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
432};
433
434enum rtw89_rate_max {
435 RTW89_RATE_CCK_MAX = 4,
436 RTW89_RATE_OFDM_MAX = 8,
437 RTW89_RATE_MCS_MAX = 12,
438 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */
439 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
440};
441
442enum rtw89_nss {
443 RTW89_NSS_1 = 0,
444 RTW89_NSS_2 = 1,
445 /* HE DCM only support 1ss and 2ss */
446 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1,
447 RTW89_NSS_3 = 2,
448 RTW89_NSS_4 = 3,
449 RTW89_NSS_MAX,
450};
451
452enum rtw89_ntx {
453 RTW89_1TX = 0,
454 RTW89_2TX = 1,
455 RTW89_NTX_NUM,
456};
457
458enum rtw89_beamforming_type {
459 RTW89_NONBF = 0,
460 RTW89_BF = 1,
461 RTW89_BF_NUM,
462};
463
464enum rtw89_regulation_type {
465 RTW89_WW = 0,
466 RTW89_ETSI = 1,
467 RTW89_FCC = 2,
468 RTW89_MKK = 3,
469 RTW89_NA = 4,
470 RTW89_IC = 5,
471 RTW89_KCC = 6,
472 RTW89_ACMA = 7,
473 RTW89_NCC = 8,
474 RTW89_MEXICO = 9,
475 RTW89_CHILE = 10,
476 RTW89_UKRAINE = 11,
477 RTW89_CN = 12,
478 RTW89_QATAR = 13,
479 RTW89_UK = 14,
480 RTW89_REGD_NUM,
481};
482
483enum rtw89_fw_pkt_ofld_type {
484 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
485 RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
486 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
487 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
488 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
489 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
490 RTW89_PKT_OFLD_TYPE_NDP = 6,
491 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
492 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
493 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
494 RTW89_PKT_OFLD_TYPE_NUM,
495};
496
497struct rtw89_txpwr_byrate {
498 s8 cck[RTW89_RATE_CCK_MAX];
499 s8 ofdm[RTW89_RATE_OFDM_MAX];
500 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
501 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
502 s8 offset[RTW89_RATE_OFFSET_MAX];
503};
504
505enum rtw89_bandwidth_section_num {
506 RTW89_BW20_SEC_NUM = 8,
507 RTW89_BW40_SEC_NUM = 4,
508 RTW89_BW80_SEC_NUM = 2,
509};
510
511#define RTW89_TXPWR_LMT_PAGE_SIZE 40
512
513struct rtw89_txpwr_limit {
514 s8 cck_20m[RTW89_BF_NUM];
515 s8 cck_40m[RTW89_BF_NUM];
516 s8 ofdm[RTW89_BF_NUM];
517 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
518 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
519 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
520 s8 mcs_160m[RTW89_BF_NUM];
521 s8 mcs_40m_0p5[RTW89_BF_NUM];
522 s8 mcs_40m_2p5[RTW89_BF_NUM];
523};
524
525#define RTW89_RU_SEC_NUM 8
526
527#define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24
528
529struct rtw89_txpwr_limit_ru {
530 s8 ru26[RTW89_RU_SEC_NUM];
531 s8 ru52[RTW89_RU_SEC_NUM];
532 s8 ru106[RTW89_RU_SEC_NUM];
533};
534
535struct rtw89_rate_desc {
536 enum rtw89_nss nss;
537 enum rtw89_rate_section rs;
538 u8 idx;
539};
540
541#define PHY_STS_HDR_LEN 8
542#define RF_PATH_MAX 4
543#define RTW89_MAX_PPDU_CNT 8
544struct rtw89_rx_phy_ppdu {
545 u8 *buf;
546 u32 len;
547 u8 rssi_avg;
548 u8 rssi[RF_PATH_MAX];
549 u8 mac_id;
550 u8 chan_idx;
551 u8 ie;
552 u16 rate;
553 bool to_self;
554 bool valid;
555};
556
557enum rtw89_mac_idx {
558 RTW89_MAC_0 = 0,
559 RTW89_MAC_1 = 1,
560};
561
562enum rtw89_phy_idx {
563 RTW89_PHY_0 = 0,
564 RTW89_PHY_1 = 1,
565 RTW89_PHY_MAX
566};
567
568enum rtw89_sub_entity_idx {
569 RTW89_SUB_ENTITY_0 = 0,
570
571 NUM_OF_RTW89_SUB_ENTITY,
572};
573
574enum rtw89_rf_path {
575 RF_PATH_A = 0,
576 RF_PATH_B = 1,
577 RF_PATH_C = 2,
578 RF_PATH_D = 3,
579 RF_PATH_AB,
580 RF_PATH_AC,
581 RF_PATH_AD,
582 RF_PATH_BC,
583 RF_PATH_BD,
584 RF_PATH_CD,
585 RF_PATH_ABC,
586 RF_PATH_ABD,
587 RF_PATH_ACD,
588 RF_PATH_BCD,
589 RF_PATH_ABCD,
590};
591
592enum rtw89_rf_path_bit {
593 RF_A = BIT(0),
594 RF_B = BIT(1),
595 RF_C = BIT(2),
596 RF_D = BIT(3),
597
598 RF_AB = (RF_A | RF_B),
599 RF_AC = (RF_A | RF_C),
600 RF_AD = (RF_A | RF_D),
601 RF_BC = (RF_B | RF_C),
602 RF_BD = (RF_B | RF_D),
603 RF_CD = (RF_C | RF_D),
604
605 RF_ABC = (RF_A | RF_B | RF_C),
606 RF_ABD = (RF_A | RF_B | RF_D),
607 RF_ACD = (RF_A | RF_C | RF_D),
608 RF_BCD = (RF_B | RF_C | RF_D),
609
610 RF_ABCD = (RF_A | RF_B | RF_C | RF_D),
611};
612
613enum rtw89_bandwidth {
614 RTW89_CHANNEL_WIDTH_20 = 0,
615 RTW89_CHANNEL_WIDTH_40 = 1,
616 RTW89_CHANNEL_WIDTH_80 = 2,
617 RTW89_CHANNEL_WIDTH_160 = 3,
618 RTW89_CHANNEL_WIDTH_80_80 = 4,
619 RTW89_CHANNEL_WIDTH_5 = 5,
620 RTW89_CHANNEL_WIDTH_10 = 6,
621};
622
623enum rtw89_ps_mode {
624 RTW89_PS_MODE_NONE = 0,
625 RTW89_PS_MODE_RFOFF = 1,
626 RTW89_PS_MODE_CLK_GATED = 2,
627 RTW89_PS_MODE_PWR_GATED = 3,
628};
629
630#define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
631#define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
632#define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
633#define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
634
635enum rtw89_ru_bandwidth {
636 RTW89_RU26 = 0,
637 RTW89_RU52 = 1,
638 RTW89_RU106 = 2,
639 RTW89_RU_NUM,
640};
641
642enum rtw89_sc_offset {
643 RTW89_SC_DONT_CARE = 0,
644 RTW89_SC_20_UPPER = 1,
645 RTW89_SC_20_LOWER = 2,
646 RTW89_SC_20_UPMOST = 3,
647 RTW89_SC_20_LOWEST = 4,
648 RTW89_SC_20_UP2X = 5,
649 RTW89_SC_20_LOW2X = 6,
650 RTW89_SC_20_UP3X = 7,
651 RTW89_SC_20_LOW3X = 8,
652 RTW89_SC_40_UPPER = 9,
653 RTW89_SC_40_LOWER = 10,
654};
655
656enum rtw89_wow_flags {
657 RTW89_WOW_FLAG_EN_MAGIC_PKT,
658 RTW89_WOW_FLAG_EN_REKEY_PKT,
659 RTW89_WOW_FLAG_EN_DISCONNECT,
660 RTW89_WOW_FLAG_NUM,
661};
662
663struct rtw89_chan {
664 u8 channel;
665 u8 primary_channel;
666 enum rtw89_band band_type;
667 enum rtw89_bandwidth band_width;
668
669 /* The follow-up are derived from the above. We must ensure that it
670 * is assigned correctly in rtw89_chan_create() if new one is added.
671 */
672 u32 freq;
673 enum rtw89_subband subband_type;
674 enum rtw89_sc_offset pri_ch_idx;
675};
676
677struct rtw89_chan_rcd {
678 u8 prev_primary_channel;
679 enum rtw89_band prev_band_type;
680};
681
682struct rtw89_channel_help_params {
683 u32 tx_en;
684};
685
686struct rtw89_port_reg {
687 u32 port_cfg;
688 u32 tbtt_prohib;
689 u32 bcn_area;
690 u32 bcn_early;
691 u32 tbtt_early;
692 u32 tbtt_agg;
693 u32 bcn_space;
694 u32 bcn_forcetx;
695 u32 bcn_err_cnt;
696 u32 bcn_err_flag;
697 u32 dtim_ctrl;
698 u32 tbtt_shift;
699 u32 bcn_cnt_tmr;
700 u32 tsftr_l;
701 u32 tsftr_h;
702};
703
704struct rtw89_txwd_body {
705 __le32 dword0;
706 __le32 dword1;
707 __le32 dword2;
708 __le32 dword3;
709 __le32 dword4;
710 __le32 dword5;
711} __packed;
712
713struct rtw89_txwd_body_v1 {
714 __le32 dword0;
715 __le32 dword1;
716 __le32 dword2;
717 __le32 dword3;
718 __le32 dword4;
719 __le32 dword5;
720 __le32 dword6;
721 __le32 dword7;
722} __packed;
723
724struct rtw89_txwd_info {
725 __le32 dword0;
726 __le32 dword1;
727 __le32 dword2;
728 __le32 dword3;
729 __le32 dword4;
730 __le32 dword5;
731} __packed;
732
733struct rtw89_rx_desc_info {
734 u16 pkt_size;
735 u8 pkt_type;
736 u8 drv_info_size;
737 u8 shift;
738 u8 wl_hd_iv_len;
739 bool long_rxdesc;
740 bool bb_sel;
741 bool mac_info_valid;
742 u16 data_rate;
743 u8 gi_ltf;
744 u8 bw;
745 u32 free_run_cnt;
746 u8 user_id;
747 bool sr_en;
748 u8 ppdu_cnt;
749 u8 ppdu_type;
750 bool icv_err;
751 bool crc32_err;
752 bool hw_dec;
753 bool sw_dec;
754 bool addr1_match;
755 u8 frag;
756 u16 seq;
757 u8 frame_type;
758 u8 rx_pl_id;
759 bool addr_cam_valid;
760 u8 addr_cam_id;
761 u8 sec_cam_id;
762 u8 mac_id;
763 u16 offset;
764 bool ready;
765};
766
767struct rtw89_rxdesc_short {
768 __le32 dword0;
769 __le32 dword1;
770 __le32 dword2;
771 __le32 dword3;
772} __packed;
773
774struct rtw89_rxdesc_long {
775 __le32 dword0;
776 __le32 dword1;
777 __le32 dword2;
778 __le32 dword3;
779 __le32 dword4;
780 __le32 dword5;
781 __le32 dword6;
782 __le32 dword7;
783} __packed;
784
785struct rtw89_tx_desc_info {
786 u16 pkt_size;
787 u8 wp_offset;
788 u8 mac_id;
789 u8 qsel;
790 u8 ch_dma;
791 u8 hdr_llc_len;
792 bool is_bmc;
793 bool en_wd_info;
794 bool wd_page;
795 bool use_rate;
796 bool dis_data_fb;
797 bool tid_indicate;
798 bool agg_en;
799 bool bk;
800 u8 ampdu_density;
801 u8 ampdu_num;
802 bool sec_en;
803 u8 addr_info_nr;
804 u8 sec_keyid;
805 u8 sec_type;
806 u8 sec_cam_idx;
807 u8 sec_seq[6];
808 u16 data_rate;
809 u16 data_retry_lowest_rate;
810 bool fw_dl;
811 u16 seq;
812 bool a_ctrl_bsr;
813 u8 hw_ssn_sel;
814#define RTW89_MGMT_HW_SSN_SEL 1
815 u8 hw_seq_mode;
816#define RTW89_MGMT_HW_SEQ_MODE 1
817 bool hiq;
818 u8 port;
819};
820
821struct rtw89_core_tx_request {
822 enum rtw89_core_tx_type tx_type;
823
824 struct sk_buff *skb;
825 struct ieee80211_vif *vif;
826 struct ieee80211_sta *sta;
827 struct rtw89_tx_desc_info desc_info;
828};
829
830struct rtw89_txq {
831 struct list_head list;
832 unsigned long flags;
833 int wait_cnt;
834};
835
836struct rtw89_mac_ax_gnt {
837 u8 gnt_bt_sw_en;
838 u8 gnt_bt;
839 u8 gnt_wl_sw_en;
840 u8 gnt_wl;
841} __packed;
842
843#define RTW89_MAC_AX_COEX_GNT_NR 2
844struct rtw89_mac_ax_coex_gnt {
845 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
846};
847
848enum rtw89_btc_ncnt {
849 BTC_NCNT_POWER_ON = 0x0,
850 BTC_NCNT_POWER_OFF,
851 BTC_NCNT_INIT_COEX,
852 BTC_NCNT_SCAN_START,
853 BTC_NCNT_SCAN_FINISH,
854 BTC_NCNT_SPECIAL_PACKET,
855 BTC_NCNT_SWITCH_BAND,
856 BTC_NCNT_RFK_TIMEOUT,
857 BTC_NCNT_SHOW_COEX_INFO,
858 BTC_NCNT_ROLE_INFO,
859 BTC_NCNT_CONTROL,
860 BTC_NCNT_RADIO_STATE,
861 BTC_NCNT_CUSTOMERIZE,
862 BTC_NCNT_WL_RFK,
863 BTC_NCNT_WL_STA,
864 BTC_NCNT_FWINFO,
865 BTC_NCNT_TIMER,
866 BTC_NCNT_NUM
867};
868
869enum rtw89_btc_btinfo {
870 BTC_BTINFO_L0 = 0,
871 BTC_BTINFO_L1,
872 BTC_BTINFO_L2,
873 BTC_BTINFO_L3,
874 BTC_BTINFO_H0,
875 BTC_BTINFO_H1,
876 BTC_BTINFO_H2,
877 BTC_BTINFO_H3,
878 BTC_BTINFO_MAX
879};
880
881enum rtw89_btc_dcnt {
882 BTC_DCNT_RUN = 0x0,
883 BTC_DCNT_CX_RUNINFO,
884 BTC_DCNT_RPT,
885 BTC_DCNT_RPT_FREEZE,
886 BTC_DCNT_CYCLE,
887 BTC_DCNT_CYCLE_FREEZE,
888 BTC_DCNT_W1,
889 BTC_DCNT_W1_FREEZE,
890 BTC_DCNT_B1,
891 BTC_DCNT_B1_FREEZE,
892 BTC_DCNT_TDMA_NONSYNC,
893 BTC_DCNT_SLOT_NONSYNC,
894 BTC_DCNT_BTCNT_FREEZE,
895 BTC_DCNT_WL_SLOT_DRIFT,
896 BTC_DCNT_BT_SLOT_DRIFT,
897 BTC_DCNT_WL_STA_LAST,
898 BTC_DCNT_NUM,
899};
900
901enum rtw89_btc_wl_state_cnt {
902 BTC_WCNT_SCANAP = 0x0,
903 BTC_WCNT_DHCP,
904 BTC_WCNT_EAPOL,
905 BTC_WCNT_ARP,
906 BTC_WCNT_SCBDUPDATE,
907 BTC_WCNT_RFK_REQ,
908 BTC_WCNT_RFK_GO,
909 BTC_WCNT_RFK_REJECT,
910 BTC_WCNT_RFK_TIMEOUT,
911 BTC_WCNT_CH_UPDATE,
912 BTC_WCNT_NUM
913};
914
915enum rtw89_btc_bt_state_cnt {
916 BTC_BCNT_RETRY = 0x0,
917 BTC_BCNT_REINIT,
918 BTC_BCNT_REENABLE,
919 BTC_BCNT_SCBDREAD,
920 BTC_BCNT_RELINK,
921 BTC_BCNT_IGNOWL,
922 BTC_BCNT_INQPAG,
923 BTC_BCNT_INQ,
924 BTC_BCNT_PAGE,
925 BTC_BCNT_ROLESW,
926 BTC_BCNT_AFH,
927 BTC_BCNT_INFOUPDATE,
928 BTC_BCNT_INFOSAME,
929 BTC_BCNT_SCBDUPDATE,
930 BTC_BCNT_HIPRI_TX,
931 BTC_BCNT_HIPRI_RX,
932 BTC_BCNT_LOPRI_TX,
933 BTC_BCNT_LOPRI_RX,
934 BTC_BCNT_POLUT,
935 BTC_BCNT_RATECHG,
936 BTC_BCNT_NUM
937};
938
939enum rtw89_btc_bt_profile {
940 BTC_BT_NOPROFILE = 0,
941 BTC_BT_HFP = BIT(0),
942 BTC_BT_HID = BIT(1),
943 BTC_BT_A2DP = BIT(2),
944 BTC_BT_PAN = BIT(3),
945 BTC_PROFILE_MAX = 4,
946};
947
948struct rtw89_btc_ant_info {
949 u8 type; /* shared, dedicated */
950 u8 num;
951 u8 isolation;
952
953 u8 single_pos: 1;/* Single antenna at S0 or S1 */
954 u8 diversity: 1;
955};
956
957enum rtw89_tfc_dir {
958 RTW89_TFC_UL,
959 RTW89_TFC_DL,
960};
961
962struct rtw89_btc_wl_smap {
963 u32 busy: 1;
964 u32 scan: 1;
965 u32 connecting: 1;
966 u32 roaming: 1;
967 u32 _4way: 1;
968 u32 rf_off: 1;
969 u32 lps: 2;
970 u32 ips: 1;
971 u32 init_ok: 1;
972 u32 traffic_dir : 2;
973 u32 rf_off_pre: 1;
974 u32 lps_pre: 2;
975};
976
977enum rtw89_tfc_lv {
978 RTW89_TFC_IDLE,
979 RTW89_TFC_ULTRA_LOW,
980 RTW89_TFC_LOW,
981 RTW89_TFC_MID,
982 RTW89_TFC_HIGH,
983};
984
985#define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
986DECLARE_EWMA(tp, 10, 2);
987
988struct rtw89_traffic_stats {
989 /* units in bytes */
990 u64 tx_unicast;
991 u64 rx_unicast;
992 u32 tx_avg_len;
993 u32 rx_avg_len;
994
995 /* count for packets */
996 u64 tx_cnt;
997 u64 rx_cnt;
998
999 /* units in Mbps */
1000 u32 tx_throughput;
1001 u32 rx_throughput;
1002 u32 tx_throughput_raw;
1003 u32 rx_throughput_raw;
1004
1005 u32 rx_tf_acc;
1006 u32 rx_tf_periodic;
1007
1008 enum rtw89_tfc_lv tx_tfc_lv;
1009 enum rtw89_tfc_lv rx_tfc_lv;
1010 struct ewma_tp tx_ewma_tp;
1011 struct ewma_tp rx_ewma_tp;
1012
1013 u16 tx_rate;
1014 u16 rx_rate;
1015};
1016
1017struct rtw89_btc_statistic {
1018 u8 rssi; /* 0%~110% (dBm = rssi -110) */
1019 struct rtw89_traffic_stats traffic;
1020};
1021
1022#define BTC_WL_RSSI_THMAX 4
1023
1024struct rtw89_btc_wl_link_info {
1025 struct rtw89_btc_statistic stat;
1026 enum rtw89_tfc_dir dir;
1027 u8 rssi_state[BTC_WL_RSSI_THMAX];
1028 u8 mac_addr[ETH_ALEN];
1029 u8 busy;
1030 u8 ch;
1031 u8 bw;
1032 u8 band;
1033 u8 role;
1034 u8 pid;
1035 u8 phy;
1036 u8 dtim_period;
1037 u8 mode;
1038
1039 u8 mac_id;
1040 u8 tx_retry;
1041
1042 u32 bcn_period;
1043 u32 busy_t;
1044 u32 tx_time;
1045 u32 client_cnt;
1046 u32 rx_rate_drop_cnt;
1047
1048 u32 active: 1;
1049 u32 noa: 1;
1050 u32 client_ps: 1;
1051 u32 connected: 2;
1052};
1053
1054union rtw89_btc_wl_state_map {
1055 u32 val;
1056 struct rtw89_btc_wl_smap map;
1057};
1058
1059struct rtw89_btc_bt_hfp_desc {
1060 u32 exist: 1;
1061 u32 type: 2;
1062 u32 rsvd: 29;
1063};
1064
1065struct rtw89_btc_bt_hid_desc {
1066 u32 exist: 1;
1067 u32 slot_info: 2;
1068 u32 pair_cnt: 2;
1069 u32 type: 8;
1070 u32 rsvd: 19;
1071};
1072
1073struct rtw89_btc_bt_a2dp_desc {
1074 u8 exist: 1;
1075 u8 exist_last: 1;
1076 u8 play_latency: 1;
1077 u8 type: 3;
1078 u8 active: 1;
1079 u8 sink: 1;
1080
1081 u8 bitpool;
1082 u16 vendor_id;
1083 u32 device_name;
1084 u32 flush_time;
1085};
1086
1087struct rtw89_btc_bt_pan_desc {
1088 u32 exist: 1;
1089 u32 type: 1;
1090 u32 active: 1;
1091 u32 rsvd: 29;
1092};
1093
1094struct rtw89_btc_bt_rfk_info {
1095 u32 run: 1;
1096 u32 req: 1;
1097 u32 timeout: 1;
1098 u32 rsvd: 29;
1099};
1100
1101union rtw89_btc_bt_rfk_info_map {
1102 u32 val;
1103 struct rtw89_btc_bt_rfk_info map;
1104};
1105
1106struct rtw89_btc_bt_ver_info {
1107 u32 fw_coex; /* match with which coex_ver */
1108 u32 fw;
1109};
1110
1111struct rtw89_btc_bool_sta_chg {
1112 u32 now: 1;
1113 u32 last: 1;
1114 u32 remain: 1;
1115 u32 srvd: 29;
1116};
1117
1118struct rtw89_btc_u8_sta_chg {
1119 u8 now;
1120 u8 last;
1121 u8 remain;
1122 u8 rsvd;
1123};
1124
1125struct rtw89_btc_wl_scan_info {
1126 u8 band[RTW89_PHY_MAX];
1127 u8 phy_map;
1128 u8 rsvd;
1129};
1130
1131struct rtw89_btc_wl_dbcc_info {
1132 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1133 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */
1134 u8 real_band[RTW89_PHY_MAX];
1135 u8 role[RTW89_PHY_MAX]; /* role in each phy */
1136};
1137
1138struct rtw89_btc_wl_active_role {
1139 u8 connected: 1;
1140 u8 pid: 3;
1141 u8 phy: 1;
1142 u8 noa: 1;
1143 u8 band: 2;
1144
1145 u8 client_ps: 1;
1146 u8 bw: 7;
1147
1148 u8 role;
1149 u8 ch;
1150
1151 u16 tx_lvl;
1152 u16 rx_lvl;
1153 u16 tx_rate;
1154 u16 rx_rate;
1155};
1156
1157struct rtw89_btc_wl_active_role_v1 {
1158 u8 connected: 1;
1159 u8 pid: 3;
1160 u8 phy: 1;
1161 u8 noa: 1;
1162 u8 band: 2;
1163
1164 u8 client_ps: 1;
1165 u8 bw: 7;
1166
1167 u8 role;
1168 u8 ch;
1169
1170 u16 tx_lvl;
1171 u16 rx_lvl;
1172 u16 tx_rate;
1173 u16 rx_rate;
1174
1175 u32 noa_duration; /* ms */
1176};
1177
1178struct rtw89_btc_wl_role_info_bpos {
1179 u16 none: 1;
1180 u16 station: 1;
1181 u16 ap: 1;
1182 u16 vap: 1;
1183 u16 adhoc: 1;
1184 u16 adhoc_master: 1;
1185 u16 mesh: 1;
1186 u16 moniter: 1;
1187 u16 p2p_device: 1;
1188 u16 p2p_gc: 1;
1189 u16 p2p_go: 1;
1190 u16 nan: 1;
1191};
1192
1193struct rtw89_btc_wl_scc_ctrl {
1194 u8 null_role1;
1195 u8 null_role2;
1196 u8 ebt_null; /* if tx null at EBT slot */
1197};
1198
1199union rtw89_btc_wl_role_info_map {
1200 u16 val;
1201 struct rtw89_btc_wl_role_info_bpos role;
1202};
1203
1204struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1205 u8 connect_cnt;
1206 u8 link_mode;
1207 union rtw89_btc_wl_role_info_map role_map;
1208 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1209};
1210
1211struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1212 u8 connect_cnt;
1213 u8 link_mode;
1214 union rtw89_btc_wl_role_info_map role_map;
1215 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1216 u32 mrole_type; /* btc_wl_mrole_type */
1217 u32 mrole_noa_duration; /* ms */
1218
1219 u32 dbcc_en: 1;
1220 u32 dbcc_chg: 1;
1221 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1222 u32 link_mode_chg: 1;
1223 u32 rsvd: 27;
1224};
1225
1226struct rtw89_btc_wl_ver_info {
1227 u32 fw_coex; /* match with which coex_ver */
1228 u32 fw;
1229 u32 mac;
1230 u32 bb;
1231 u32 rf;
1232};
1233
1234struct rtw89_btc_wl_afh_info {
1235 u8 en;
1236 u8 ch;
1237 u8 bw;
1238 u8 rsvd;
1239} __packed;
1240
1241struct rtw89_btc_wl_rfk_info {
1242 u32 state: 2;
1243 u32 path_map: 4;
1244 u32 phy_map: 2;
1245 u32 band: 2;
1246 u32 type: 8;
1247 u32 rsvd: 14;
1248};
1249
1250struct rtw89_btc_bt_smap {
1251 u32 connect: 1;
1252 u32 ble_connect: 1;
1253 u32 acl_busy: 1;
1254 u32 sco_busy: 1;
1255 u32 mesh_busy: 1;
1256 u32 inq_pag: 1;
1257};
1258
1259union rtw89_btc_bt_state_map {
1260 u32 val;
1261 struct rtw89_btc_bt_smap map;
1262};
1263
1264#define BTC_BT_RSSI_THMAX 4
1265#define BTC_BT_AFH_GROUP 12
1266
1267struct rtw89_btc_bt_link_info {
1268 struct rtw89_btc_u8_sta_chg profile_cnt;
1269 struct rtw89_btc_bool_sta_chg multi_link;
1270 struct rtw89_btc_bool_sta_chg relink;
1271 struct rtw89_btc_bt_hfp_desc hfp_desc;
1272 struct rtw89_btc_bt_hid_desc hid_desc;
1273 struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1274 struct rtw89_btc_bt_pan_desc pan_desc;
1275 union rtw89_btc_bt_state_map status;
1276
1277 u8 sut_pwr_level[BTC_PROFILE_MAX];
1278 u8 golden_rx_shift[BTC_PROFILE_MAX];
1279 u8 rssi_state[BTC_BT_RSSI_THMAX];
1280 u8 afh_map[BTC_BT_AFH_GROUP];
1281
1282 u32 role_sw: 1;
1283 u32 slave_role: 1;
1284 u32 afh_update: 1;
1285 u32 cqddr: 1;
1286 u32 rssi: 8;
1287 u32 tx_3m: 1;
1288 u32 rsvd: 19;
1289};
1290
1291struct rtw89_btc_3rdcx_info {
1292 u8 type; /* 0: none, 1:zigbee, 2:LTE */
1293 u8 hw_coex;
1294 u16 rsvd;
1295};
1296
1297struct rtw89_btc_dm_emap {
1298 u32 init: 1;
1299 u32 pta_owner: 1;
1300 u32 wl_rfk_timeout: 1;
1301 u32 bt_rfk_timeout: 1;
1302
1303 u32 wl_fw_hang: 1;
1304 u32 offload_mismatch: 1;
1305 u32 cycle_hang: 1;
1306 u32 w1_hang: 1;
1307
1308 u32 b1_hang: 1;
1309 u32 tdma_no_sync: 1;
1310 u32 wl_slot_drift: 1;
1311};
1312
1313union rtw89_btc_dm_error_map {
1314 u32 val;
1315 struct rtw89_btc_dm_emap map;
1316};
1317
1318struct rtw89_btc_rf_para {
1319 u32 tx_pwr_freerun;
1320 u32 rx_gain_freerun;
1321 u32 tx_pwr_perpkt;
1322 u32 rx_gain_perpkt;
1323};
1324
1325struct rtw89_btc_wl_info {
1326 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1327 struct rtw89_btc_wl_rfk_info rfk_info;
1328 struct rtw89_btc_wl_ver_info ver_info;
1329 struct rtw89_btc_wl_afh_info afh_info;
1330 struct rtw89_btc_wl_role_info role_info;
1331 struct rtw89_btc_wl_role_info_v1 role_info_v1;
1332 struct rtw89_btc_wl_scan_info scan_info;
1333 struct rtw89_btc_wl_dbcc_info dbcc_info;
1334 struct rtw89_btc_rf_para rf_para;
1335 union rtw89_btc_wl_state_map status;
1336
1337 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1338 u8 rssi_level;
1339
1340 bool scbd_change;
1341 u32 scbd;
1342};
1343
1344struct rtw89_btc_module {
1345 struct rtw89_btc_ant_info ant;
1346 u8 rfe_type;
1347 u8 cv;
1348
1349 u8 bt_solo: 1;
1350 u8 bt_pos: 1;
1351 u8 switch_type: 1;
1352
1353 u8 rsvd;
1354};
1355
1356#define RTW89_BTC_DM_MAXSTEP 30
1357#define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1358
1359struct rtw89_btc_dm_step {
1360 u16 step[RTW89_BTC_DM_MAXSTEP];
1361 u8 step_pos;
1362 bool step_ov;
1363};
1364
1365struct rtw89_btc_init_info {
1366 struct rtw89_btc_module module;
1367 u8 wl_guard_ch;
1368
1369 u8 wl_only: 1;
1370 u8 wl_init_ok: 1;
1371 u8 dbcc_en: 1;
1372 u8 cx_other: 1;
1373 u8 bt_only: 1;
1374
1375 u16 rsvd;
1376};
1377
1378struct rtw89_btc_wl_tx_limit_para {
1379 u16 enable;
1380 u32 tx_time; /* unit: us */
1381 u16 tx_retry;
1382};
1383
1384struct rtw89_btc_bt_scan_info {
1385 u16 win;
1386 u16 intvl;
1387 u32 enable: 1;
1388 u32 interlace: 1;
1389 u32 rsvd: 30;
1390};
1391
1392enum rtw89_btc_bt_scan_type {
1393 BTC_SCAN_INQ = 0,
1394 BTC_SCAN_PAGE,
1395 BTC_SCAN_BLE,
1396 BTC_SCAN_INIT,
1397 BTC_SCAN_TV,
1398 BTC_SCAN_ADV,
1399 BTC_SCAN_MAX1,
1400};
1401
1402struct rtw89_btc_bt_info {
1403 struct rtw89_btc_bt_link_info link_info;
1404 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1];
1405 struct rtw89_btc_bt_ver_info ver_info;
1406 struct rtw89_btc_bool_sta_chg enable;
1407 struct rtw89_btc_bool_sta_chg inq_pag;
1408 struct rtw89_btc_rf_para rf_para;
1409 union rtw89_btc_bt_rfk_info_map rfk_info;
1410
1411 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1412
1413 u32 scbd;
1414 u32 feature;
1415
1416 u32 mbx_avl: 1;
1417 u32 whql_test: 1;
1418 u32 igno_wl: 1;
1419 u32 reinit: 1;
1420 u32 ble_scan_en: 1;
1421 u32 btg_type: 1;
1422 u32 inq: 1;
1423 u32 pag: 1;
1424 u32 run_patch_code: 1;
1425 u32 hi_lna_rx: 1;
1426 u32 scan_rx_low_pri: 1;
1427 u32 rsvd: 21;
1428};
1429
1430struct rtw89_btc_cx {
1431 struct rtw89_btc_wl_info wl;
1432 struct rtw89_btc_bt_info bt;
1433 struct rtw89_btc_3rdcx_info other;
1434 u32 state_map;
1435 u32 cnt_bt[BTC_BCNT_NUM];
1436 u32 cnt_wl[BTC_WCNT_NUM];
1437};
1438
1439struct rtw89_btc_fbtc_tdma {
1440 u8 type; /* chip_info::fcxtdma_ver */
1441 u8 rxflctrl;
1442 u8 txpause;
1443 u8 wtgle_n;
1444 u8 leak_n;
1445 u8 ext_ctrl;
1446 u8 rxflctrl_role;
1447 u8 option_ctrl;
1448} __packed;
1449
1450struct rtw89_btc_fbtc_tdma_v1 {
1451 u8 fver; /* chip_info::fcxtdma_ver */
1452 u8 rsvd;
1453 __le16 rsvd1;
1454 struct rtw89_btc_fbtc_tdma tdma;
1455} __packed;
1456
1457#define CXMREG_MAX 30
1458#define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1459#define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1460
1461enum rtw89_btc_bt_sta_counter {
1462 BTC_BCNT_RFK_REQ = 0,
1463 BTC_BCNT_RFK_GO = 1,
1464 BTC_BCNT_RFK_REJECT = 2,
1465 BTC_BCNT_RFK_FAIL = 3,
1466 BTC_BCNT_RFK_TIMEOUT = 4,
1467 BTC_BCNT_HI_TX = 5,
1468 BTC_BCNT_HI_RX = 6,
1469 BTC_BCNT_LO_TX = 7,
1470 BTC_BCNT_LO_RX = 8,
1471 BTC_BCNT_POLLUTED = 9,
1472 BTC_BCNT_STA_MAX
1473};
1474
1475struct rtw89_btc_fbtc_rpt_ctrl {
1476 u16 fver; /* chip_info::fcxbtcrpt_ver */
1477 u16 rpt_cnt; /* tmr counters */
1478 u32 wl_fw_coex_ver; /* match which driver's coex version */
1479 u32 wl_fw_cx_offload;
1480 u32 wl_fw_ver;
1481 u32 rpt_enable;
1482 u32 rpt_para; /* ms */
1483 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1484 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1485 u32 mb_recv_cnt; /* fw recv mailbox counter */
1486 u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1487 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1488 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1489 u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
1490 u32 c2h_cnt; /* fw send c2h counter */
1491 u32 h2c_cnt; /* fw recv h2c counter */
1492} __packed;
1493
1494struct rtw89_btc_fbtc_rpt_ctrl_info {
1495 __le32 cnt; /* fw report counter */
1496 __le32 en; /* report map */
1497 __le32 para; /* not used */
1498
1499 __le32 cnt_c2h; /* fw send c2h counter */
1500 __le32 cnt_h2c; /* fw recv h2c counter */
1501 __le32 len_c2h; /* The total length of the last C2H */
1502
1503 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */
1504 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1505} __packed;
1506
1507struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
1508 __le32 cx_ver; /* match which driver's coex version */
1509 __le32 cx_offload;
1510 __le32 fw_ver;
1511} __packed;
1512
1513struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
1514 __le32 cnt_empty; /* a2dp empty count */
1515 __le32 cnt_flowctrl; /* a2dp empty flow control counter */
1516 __le32 cnt_tx;
1517 __le32 cnt_ack;
1518 __le32 cnt_nack;
1519} __packed;
1520
1521struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
1522 __le32 cnt_send_ok; /* fw send mailbox ok counter */
1523 __le32 cnt_send_fail; /* fw send mailbox fail counter */
1524 __le32 cnt_recv; /* fw recv mailbox counter */
1525 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
1526} __packed;
1527
1528struct rtw89_btc_fbtc_rpt_ctrl_v1 {
1529 u8 fver;
1530 u8 rsvd;
1531 __le16 rsvd1;
1532 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
1533 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
1534 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1535 __le32 bt_cnt[BTC_BCNT_STA_MAX];
1536 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
1537} __packed;
1538
1539enum rtw89_fbtc_ext_ctrl_type {
1540 CXECTL_OFF = 0x0, /* tdma off */
1541 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1542 CXECTL_EXT = 0x2,
1543 CXECTL_MAX
1544};
1545
1546union rtw89_btc_fbtc_rxflct {
1547 u8 val;
1548 u8 type: 3;
1549 u8 tgln_n: 5;
1550};
1551
1552enum rtw89_btc_cxst_state {
1553 CXST_OFF = 0x0,
1554 CXST_B2W = 0x1,
1555 CXST_W1 = 0x2,
1556 CXST_W2 = 0x3,
1557 CXST_W2B = 0x4,
1558 CXST_B1 = 0x5,
1559 CXST_B2 = 0x6,
1560 CXST_B3 = 0x7,
1561 CXST_B4 = 0x8,
1562 CXST_LK = 0x9,
1563 CXST_BLK = 0xa,
1564 CXST_E2G = 0xb,
1565 CXST_E5G = 0xc,
1566 CXST_EBT = 0xd,
1567 CXST_ENULL = 0xe,
1568 CXST_WLK = 0xf,
1569 CXST_W1FDD = 0x10,
1570 CXST_B1FDD = 0x11,
1571 CXST_MAX = 0x12,
1572};
1573
1574enum {
1575 CXBCN_ALL = 0x0,
1576 CXBCN_ALL_OK,
1577 CXBCN_BT_SLOT,
1578 CXBCN_BT_OK,
1579 CXBCN_MAX
1580};
1581
1582enum btc_slot_type {
1583 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
1584 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
1585 CXSTYPE_NUM,
1586};
1587
1588enum { /* TIME */
1589 CXT_BT = 0x0,
1590 CXT_WL = 0x1,
1591 CXT_MAX
1592};
1593
1594enum { /* TIME-A2DP */
1595 CXT_FLCTRL_OFF = 0x0,
1596 CXT_FLCTRL_ON = 0x1,
1597 CXT_FLCTRL_MAX
1598};
1599
1600enum { /* STEP TYPE */
1601 CXSTEP_NONE = 0x0,
1602 CXSTEP_EVNT = 0x1,
1603 CXSTEP_SLOT = 0x2,
1604 CXSTEP_MAX,
1605};
1606
1607#define BTC_DBG_MAX1 32
1608struct rtw89_btc_fbtc_gpio_dbg {
1609 u8 fver; /* chip_info::fcxgpiodbg_ver */
1610 u8 rsvd;
1611 u16 rsvd2;
1612 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
1613 u32 pre_state; /* the debug signal is 1 or 0 */
1614 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
1615} __packed;
1616
1617struct rtw89_btc_fbtc_mreg_val {
1618 u8 fver; /* chip_info::fcxmreg_ver */
1619 u8 reg_num;
1620 __le16 rsvd;
1621 __le32 mreg_val[CXMREG_MAX];
1622} __packed;
1623
1624#define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
1625 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
1626 .offset = cpu_to_le32(__offset), }
1627
1628struct rtw89_btc_fbtc_mreg {
1629 __le16 type;
1630 __le16 bytes;
1631 __le32 offset;
1632} __packed;
1633
1634struct rtw89_btc_fbtc_slot {
1635 __le16 dur;
1636 __le32 cxtbl;
1637 __le16 cxtype;
1638} __packed;
1639
1640struct rtw89_btc_fbtc_slots {
1641 u8 fver; /* chip_info::fcxslots_ver */
1642 u8 tbl_num;
1643 __le16 rsvd;
1644 __le32 update_map;
1645 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1646} __packed;
1647
1648struct rtw89_btc_fbtc_step {
1649 u8 type;
1650 u8 val;
1651 __le16 difft;
1652} __packed;
1653
1654struct rtw89_btc_fbtc_steps {
1655 u8 fver; /* chip_info::fcxstep_ver */
1656 u8 rsvd;
1657 __le16 cnt;
1658 __le16 pos_old;
1659 __le16 pos_new;
1660 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1661} __packed;
1662
1663struct rtw89_btc_fbtc_steps_v1 {
1664 u8 fver;
1665 u8 en;
1666 __le16 rsvd;
1667 __le32 cnt;
1668 struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1669} __packed;
1670
1671struct rtw89_btc_fbtc_cysta { /* statistics for cycles */
1672 u8 fver; /* chip_info::fcxcysta_ver */
1673 u8 rsvd;
1674 __le16 cycles; /* total cycle number */
1675 __le16 cycles_a2dp[CXT_FLCTRL_MAX];
1676 __le16 a2dpept; /* a2dp empty cnt */
1677 __le16 a2dpeptto; /* a2dp empty timeout cnt*/
1678 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
1679 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
1680 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1681 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
1682 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
1683 __le16 tavg_a2dpept; /* avg a2dp empty time */
1684 __le16 tmax_a2dpept; /* max a2dp empty time */
1685 __le16 tavg_lk; /* avg leak-slot time */
1686 __le16 tmax_lk; /* max leak-slot time */
1687 __le32 slot_cnt[CXST_MAX]; /* slot count */
1688 __le32 bcn_cnt[CXBCN_MAX];
1689 __le32 leakrx_cnt; /* the rximr occur at leak slot */
1690 __le32 collision_cnt; /* counter for event/timer occur at same time */
1691 __le32 skip_cnt;
1692 __le32 exception;
1693 __le32 except_cnt;
1694 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
1695} __packed;
1696
1697struct rtw89_btc_fbtc_fdd_try_info {
1698 __le16 cycles[CXT_FLCTRL_MAX];
1699 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
1700 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
1701} __packed;
1702
1703struct rtw89_btc_fbtc_cycle_time_info {
1704 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
1705 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
1706 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1707} __packed;
1708
1709struct rtw89_btc_fbtc_a2dp_trx_stat {
1710 u8 empty_cnt;
1711 u8 retry_cnt;
1712 u8 tx_rate;
1713 u8 tx_cnt;
1714 u8 ack_cnt;
1715 u8 nack_cnt;
1716 u8 rsvd1;
1717 u8 rsvd2;
1718} __packed;
1719
1720struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
1721 __le16 cnt; /* a2dp empty cnt */
1722 __le16 cnt_timeout; /* a2dp empty timeout cnt*/
1723 __le16 tavg; /* avg a2dp empty time */
1724 __le16 tmax; /* max a2dp empty time */
1725} __packed;
1726
1727struct rtw89_btc_fbtc_cycle_leak_info {
1728 __le32 cnt_rximr; /* the rximr occur at leak slot */
1729 __le16 tavg; /* avg leak-slot time */
1730 __le16 tmax; /* max leak-slot time */
1731} __packed;
1732
1733struct rtw89_btc_fbtc_cysta_v1 { /* statistics for cycles */
1734 u8 fver;
1735 u8 rsvd;
1736 __le16 cycles; /* total cycle number */
1737 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
1738 struct rtw89_btc_fbtc_cycle_time_info cycle_time;
1739 struct rtw89_btc_fbtc_fdd_try_info fdd_try;
1740 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
1741 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
1742 struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
1743 __le32 slot_cnt[CXST_MAX]; /* slot count */
1744 __le32 bcn_cnt[CXBCN_MAX];
1745 __le32 collision_cnt; /* counter for event/timer occur at the same time */
1746 __le32 skip_cnt;
1747 __le32 except_cnt;
1748 __le32 except_map;
1749} __packed;
1750
1751struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */
1752 u8 fver; /* chip_info::fcxnullsta_ver */
1753 u8 rsvd;
1754 __le16 rsvd2;
1755 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
1756 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
1757 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
1758} __packed;
1759
1760struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
1761 u8 fver; /* chip_info::fcxnullsta_ver */
1762 u8 rsvd;
1763 __le16 rsvd2;
1764 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */
1765 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
1766 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
1767} __packed;
1768
1769struct rtw89_btc_fbtc_btver {
1770 u8 fver; /* chip_info::fcxbtver_ver */
1771 u8 rsvd;
1772 __le16 rsvd2;
1773 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
1774 __le32 fw_ver;
1775 __le32 feature;
1776} __packed;
1777
1778struct rtw89_btc_fbtc_btscan {
1779 u8 fver; /* chip_info::fcxbtscan_ver */
1780 u8 rsvd;
1781 __le16 rsvd2;
1782 u8 scan[6];
1783} __packed;
1784
1785struct rtw89_btc_fbtc_btafh {
1786 u8 fver; /* chip_info::fcxbtafh_ver */
1787 u8 rsvd;
1788 __le16 rsvd2;
1789 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
1790 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
1791 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
1792} __packed;
1793
1794struct rtw89_btc_fbtc_btdevinfo {
1795 u8 fver; /* chip_info::fcxbtdevinfo_ver */
1796 u8 rsvd;
1797 __le16 vendor_id;
1798 __le32 dev_name; /* only 24 bits valid */
1799 __le32 flush_time;
1800} __packed;
1801
1802#define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
1803struct rtw89_btc_rf_trx_para {
1804 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
1805 u32 wl_rx_gain; /* rx gain table index (TBD.) */
1806 u8 bt_tx_power; /* decrease Tx power (dB) */
1807 u8 bt_rx_gain; /* LNA constrain level */
1808};
1809
1810struct rtw89_btc_dm {
1811 struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1812 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
1813 struct rtw89_btc_fbtc_tdma tdma;
1814 struct rtw89_btc_fbtc_tdma tdma_now;
1815 struct rtw89_mac_ax_coex_gnt gnt;
1816 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
1817 struct rtw89_btc_rf_trx_para rf_trx_para;
1818 struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
1819 struct rtw89_btc_dm_step dm_step;
1820 struct rtw89_btc_wl_scc_ctrl wl_scc;
1821 union rtw89_btc_dm_error_map error;
1822 u32 cnt_dm[BTC_DCNT_NUM];
1823 u32 cnt_notify[BTC_NCNT_NUM];
1824
1825 u32 update_slot_map;
1826 u32 set_ant_path;
1827
1828 u32 wl_only: 1;
1829 u32 wl_fw_cx_offload: 1;
1830 u32 freerun: 1;
1831 u32 wl_ps_ctrl: 2;
1832 u32 wl_mimo_ps: 1;
1833 u32 leak_ap: 1;
1834 u32 noisy_level: 3;
1835 u32 coex_info_map: 8;
1836 u32 bt_only: 1;
1837 u32 wl_btg_rx: 1;
1838 u32 trx_para_level: 8;
1839 u32 wl_stb_chg: 1;
1840 u32 pta_owner: 1;
1841 u32 tdma_instant_excute: 1;
1842 u32 rsvd: 1;
1843
1844 u16 slot_dur[CXST_MAX];
1845
1846 u8 run_reason;
1847 u8 run_action;
1848};
1849
1850struct rtw89_btc_ctrl {
1851 u32 manual: 1;
1852 u32 igno_bt: 1;
1853 u32 always_freerun: 1;
1854 u32 trace_step: 16;
1855 u32 rsvd: 12;
1856};
1857
1858struct rtw89_btc_dbg {
1859 /* cmd "rb" */
1860 bool rb_done;
1861 u32 rb_val;
1862};
1863
1864enum rtw89_btc_btf_fw_event {
1865 BTF_EVNT_RPT = 0,
1866 BTF_EVNT_BT_INFO = 1,
1867 BTF_EVNT_BT_SCBD = 2,
1868 BTF_EVNT_BT_REG = 3,
1869 BTF_EVNT_CX_RUNINFO = 4,
1870 BTF_EVNT_BT_PSD = 5,
1871 BTF_EVNT_BUF_OVERFLOW,
1872 BTF_EVNT_C2H_LOOPBACK,
1873 BTF_EVNT_MAX,
1874};
1875
1876enum btf_fw_event_report {
1877 BTC_RPT_TYPE_CTRL = 0x0,
1878 BTC_RPT_TYPE_TDMA,
1879 BTC_RPT_TYPE_SLOT,
1880 BTC_RPT_TYPE_CYSTA,
1881 BTC_RPT_TYPE_STEP,
1882 BTC_RPT_TYPE_NULLSTA,
1883 BTC_RPT_TYPE_MREG,
1884 BTC_RPT_TYPE_GPIO_DBG,
1885 BTC_RPT_TYPE_BT_VER,
1886 BTC_RPT_TYPE_BT_SCAN,
1887 BTC_RPT_TYPE_BT_AFH,
1888 BTC_RPT_TYPE_BT_DEVICE,
1889 BTC_RPT_TYPE_TEST,
1890 BTC_RPT_TYPE_MAX = 31
1891};
1892
1893enum rtw_btc_btf_reg_type {
1894 REG_MAC = 0x0,
1895 REG_BB = 0x1,
1896 REG_RF = 0x2,
1897 REG_BT_RF = 0x3,
1898 REG_BT_MODEM = 0x4,
1899 REG_BT_BLUEWIZE = 0x5,
1900 REG_BT_VENDOR = 0x6,
1901 REG_BT_LE = 0x7,
1902 REG_MAX_TYPE,
1903};
1904
1905struct rtw89_btc_rpt_cmn_info {
1906 u32 rx_cnt;
1907 u32 rx_len;
1908 u32 req_len; /* expected rsp len */
1909 u8 req_fver; /* expected rsp fver */
1910 u8 rsp_fver; /* fver from fw */
1911 u8 valid;
1912} __packed;
1913
1914struct rtw89_btc_report_ctrl_state {
1915 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1916 union {
1917 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw for 52A*/
1918 struct rtw89_btc_fbtc_rpt_ctrl_v1 finfo_v1; /* info from fw for 52C*/
1919 };
1920};
1921
1922struct rtw89_btc_rpt_fbtc_tdma {
1923 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1924 union {
1925 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */
1926 struct rtw89_btc_fbtc_tdma_v1 finfo_v1; /* info from fw for 52C*/
1927 };
1928};
1929
1930struct rtw89_btc_rpt_fbtc_slots {
1931 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1932 struct rtw89_btc_fbtc_slots finfo; /* info from fw */
1933};
1934
1935struct rtw89_btc_rpt_fbtc_cysta {
1936 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1937 union {
1938 struct rtw89_btc_fbtc_cysta finfo; /* info from fw for 52A*/
1939 struct rtw89_btc_fbtc_cysta_v1 finfo_v1; /* info from fw for 52C*/
1940 };
1941};
1942
1943struct rtw89_btc_rpt_fbtc_step {
1944 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1945 union {
1946 struct rtw89_btc_fbtc_steps finfo; /* info from fw */
1947 struct rtw89_btc_fbtc_steps_v1 finfo_v1; /* info from fw */
1948 };
1949};
1950
1951struct rtw89_btc_rpt_fbtc_nullsta {
1952 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1953 union {
1954 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */
1955 struct rtw89_btc_fbtc_cynullsta_v1 finfo_v1; /* info from fw */
1956 };
1957};
1958
1959struct rtw89_btc_rpt_fbtc_mreg {
1960 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1961 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
1962};
1963
1964struct rtw89_btc_rpt_fbtc_gpio_dbg {
1965 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1966 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
1967};
1968
1969struct rtw89_btc_rpt_fbtc_btver {
1970 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1971 struct rtw89_btc_fbtc_btver finfo; /* info from fw */
1972};
1973
1974struct rtw89_btc_rpt_fbtc_btscan {
1975 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1976 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */
1977};
1978
1979struct rtw89_btc_rpt_fbtc_btafh {
1980 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1981 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */
1982};
1983
1984struct rtw89_btc_rpt_fbtc_btdev {
1985 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1986 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
1987};
1988
1989enum rtw89_btc_btfre_type {
1990 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
1991 BTFRE_UNDEF_TYPE,
1992 BTFRE_EXCEPTION,
1993 BTFRE_MAX,
1994};
1995
1996struct rtw89_btc_btf_fwinfo {
1997 u32 cnt_c2h;
1998 u32 cnt_h2c;
1999 u32 cnt_h2c_fail;
2000 u32 event[BTF_EVNT_MAX];
2001
2002 u32 err[BTFRE_MAX];
2003 u32 len_mismch;
2004 u32 fver_mismch;
2005 u32 rpt_en_map;
2006
2007 struct rtw89_btc_report_ctrl_state rpt_ctrl;
2008 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
2009 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
2010 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
2011 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
2012 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
2013 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
2014 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
2015 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
2016 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
2017 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
2018 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
2019};
2020
2021#define RTW89_BTC_POLICY_MAXLEN 512
2022
2023struct rtw89_btc {
2024 struct rtw89_btc_cx cx;
2025 struct rtw89_btc_dm dm;
2026 struct rtw89_btc_ctrl ctrl;
2027 struct rtw89_btc_module mdinfo;
2028 struct rtw89_btc_btf_fwinfo fwinfo;
2029 struct rtw89_btc_dbg dbg;
2030
2031 struct work_struct eapol_notify_work;
2032 struct work_struct arp_notify_work;
2033 struct work_struct dhcp_notify_work;
2034 struct work_struct icmp_notify_work;
2035
2036 u32 bt_req_len;
2037
2038 u8 policy[RTW89_BTC_POLICY_MAXLEN];
2039 u16 policy_len;
2040 u16 policy_type;
2041 bool bt_req_en;
2042 bool update_policy_force;
2043 bool lps;
2044};
2045
2046enum rtw89_ra_mode {
2047 RTW89_RA_MODE_CCK = BIT(0),
2048 RTW89_RA_MODE_OFDM = BIT(1),
2049 RTW89_RA_MODE_HT = BIT(2),
2050 RTW89_RA_MODE_VHT = BIT(3),
2051 RTW89_RA_MODE_HE = BIT(4),
2052};
2053
2054enum rtw89_ra_report_mode {
2055 RTW89_RA_RPT_MODE_LEGACY,
2056 RTW89_RA_RPT_MODE_HT,
2057 RTW89_RA_RPT_MODE_VHT,
2058 RTW89_RA_RPT_MODE_HE,
2059};
2060
2061enum rtw89_dig_noisy_level {
2062 RTW89_DIG_NOISY_LEVEL0 = -1,
2063 RTW89_DIG_NOISY_LEVEL1 = 0,
2064 RTW89_DIG_NOISY_LEVEL2 = 1,
2065 RTW89_DIG_NOISY_LEVEL3 = 2,
2066 RTW89_DIG_NOISY_LEVEL_MAX = 3,
2067};
2068
2069enum rtw89_gi_ltf {
2070 RTW89_GILTF_LGI_4XHE32 = 0,
2071 RTW89_GILTF_SGI_4XHE08 = 1,
2072 RTW89_GILTF_2XHE16 = 2,
2073 RTW89_GILTF_2XHE08 = 3,
2074 RTW89_GILTF_1XHE16 = 4,
2075 RTW89_GILTF_1XHE08 = 5,
2076 RTW89_GILTF_MAX
2077};
2078
2079enum rtw89_rx_frame_type {
2080 RTW89_RX_TYPE_MGNT = 0,
2081 RTW89_RX_TYPE_CTRL = 1,
2082 RTW89_RX_TYPE_DATA = 2,
2083 RTW89_RX_TYPE_RSVD = 3,
2084};
2085
2086struct rtw89_ra_info {
2087 u8 is_dis_ra:1;
2088 /* Bit0 : CCK
2089 * Bit1 : OFDM
2090 * Bit2 : HT
2091 * Bit3 : VHT
2092 * Bit4 : HE
2093 */
2094 u8 mode_ctrl:5;
2095 u8 bw_cap:2;
2096 u8 macid;
2097 u8 dcm_cap:1;
2098 u8 er_cap:1;
2099 u8 init_rate_lv:2;
2100 u8 upd_all:1;
2101 u8 en_sgi:1;
2102 u8 ldpc_cap:1;
2103 u8 stbc_cap:1;
2104 u8 ss_num:3;
2105 u8 giltf:3;
2106 u8 upd_bw_nss_mask:1;
2107 u8 upd_mask:1;
2108 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
2109 /* BFee CSI */
2110 u8 band_num;
2111 u8 ra_csi_rate_en:1;
2112 u8 fixed_csi_rate_en:1;
2113 u8 cr_tbl_sel:1;
2114 u8 fix_giltf_en:1;
2115 u8 fix_giltf:3;
2116 u8 rsvd2:1;
2117 u8 csi_mcs_ss_idx;
2118 u8 csi_mode:2;
2119 u8 csi_gi_ltf:3;
2120 u8 csi_bw:3;
2121};
2122
2123#define RTW89_PPDU_MAX_USR 4
2124#define RTW89_PPDU_MAC_INFO_USR_SIZE 4
2125#define RTW89_PPDU_MAC_INFO_SIZE 8
2126#define RTW89_PPDU_MAC_RX_CNT_SIZE 96
2127
2128#define RTW89_MAX_RX_AGG_NUM 64
2129#define RTW89_MAX_TX_AGG_NUM 128
2130
2131struct rtw89_ampdu_params {
2132 u16 agg_num;
2133 bool amsdu;
2134};
2135
2136struct rtw89_ra_report {
2137 struct rate_info txrate;
2138 u32 bit_rate;
2139 u16 hw_rate;
2140 bool might_fallback_legacy;
2141};
2142
2143DECLARE_EWMA(rssi, 10, 16);
2144
2145struct rtw89_ba_cam_entry {
2146 struct list_head list;
2147 u8 tid;
2148};
2149
2150#define RTW89_MAX_ADDR_CAM_NUM 128
2151#define RTW89_MAX_BSSID_CAM_NUM 20
2152#define RTW89_MAX_SEC_CAM_NUM 128
2153#define RTW89_MAX_BA_CAM_NUM 8
2154#define RTW89_SEC_CAM_IN_ADDR_CAM 7
2155
2156struct rtw89_addr_cam_entry {
2157 u8 addr_cam_idx;
2158 u8 offset;
2159 u8 len;
2160 u8 valid : 1;
2161 u8 addr_mask : 6;
2162 u8 wapi : 1;
2163 u8 mask_sel : 2;
2164 u8 bssid_cam_idx: 6;
2165
2166 u8 sec_ent_mode;
2167 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
2168 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
2169 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
2170 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
2171};
2172
2173struct rtw89_bssid_cam_entry {
2174 u8 bssid[ETH_ALEN];
2175 u8 phy_idx;
2176 u8 bssid_cam_idx;
2177 u8 offset;
2178 u8 len;
2179 u8 valid : 1;
2180 u8 num;
2181};
2182
2183struct rtw89_sec_cam_entry {
2184 u8 sec_cam_idx;
2185 u8 offset;
2186 u8 len;
2187 u8 type : 4;
2188 u8 ext_key : 1;
2189 u8 spp_mode : 1;
2190 /* 256 bits */
2191 u8 key[32];
2192};
2193
2194struct rtw89_sta {
2195 u8 mac_id;
2196 bool disassoc;
2197 struct rtw89_dev *rtwdev;
2198 struct rtw89_vif *rtwvif;
2199 struct rtw89_ra_info ra;
2200 struct rtw89_ra_report ra_report;
2201 int max_agg_wait;
2202 u8 prev_rssi;
2203 struct ewma_rssi avg_rssi;
2204 struct ewma_rssi rssi[RF_PATH_MAX];
2205 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
2206 struct ieee80211_rx_status rx_status;
2207 u16 rx_hw_rate;
2208 __le32 htc_template;
2209 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
2210 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
2211 struct list_head ba_cam_list;
2212
2213 bool use_cfg_mask;
2214 struct cfg80211_bitrate_mask mask;
2215
2216 bool cctl_tx_time;
2217 u32 ampdu_max_time:4;
2218 bool cctl_tx_retry_limit;
2219 u32 data_tx_cnt_lmt:6;
2220};
2221
2222struct rtw89_efuse {
2223 bool valid;
2224 bool power_k_valid;
2225 u8 xtal_cap;
2226 u8 addr[ETH_ALEN];
2227 u8 rfe_type;
2228 char country_code[2];
2229};
2230
2231struct rtw89_phy_rate_pattern {
2232 u64 ra_mask;
2233 u16 rate;
2234 u8 ra_mode;
2235 bool enable;
2236};
2237
2238#define RTW89_P2P_MAX_NOA_NUM 2
2239
2240struct rtw89_vif {
2241 struct list_head list;
2242 struct rtw89_dev *rtwdev;
2243 enum rtw89_sub_entity_idx sub_entity_idx;
2244
2245 u8 mac_id;
2246 u8 port;
2247 u8 mac_addr[ETH_ALEN];
2248 u8 bssid[ETH_ALEN];
2249 u8 phy_idx;
2250 u8 mac_idx;
2251 u8 net_type;
2252 u8 wifi_role;
2253 u8 self_role;
2254 u8 wmm;
2255 u8 bcn_hit_cond;
2256 u8 hit_rule;
2257 u8 last_noa_nr;
2258 bool trigger;
2259 bool lsig_txop;
2260 u8 tgt_ind;
2261 u8 frm_tgt_ind;
2262 bool wowlan_pattern;
2263 bool wowlan_uc;
2264 bool wowlan_magic;
2265 bool is_hesta;
2266 bool last_a_ctrl;
2267 bool dyn_tb_bedge_en;
2268 u8 def_tri_idx;
2269 struct work_struct update_beacon_work;
2270 struct rtw89_addr_cam_entry addr_cam;
2271 struct rtw89_bssid_cam_entry bssid_cam;
2272 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
2273 struct rtw89_traffic_stats stats;
2274 struct rtw89_phy_rate_pattern rate_pattern;
2275 struct cfg80211_scan_request *scan_req;
2276 struct ieee80211_scan_ies *scan_ies;
2277};
2278
2279enum rtw89_lv1_rcvy_step {
2280 RTW89_LV1_RCVY_STEP_1,
2281 RTW89_LV1_RCVY_STEP_2,
2282};
2283
2284struct rtw89_hci_ops {
2285 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
2286 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
2287 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
2288 void (*reset)(struct rtw89_dev *rtwdev);
2289 int (*start)(struct rtw89_dev *rtwdev);
2290 void (*stop)(struct rtw89_dev *rtwdev);
2291 void (*pause)(struct rtw89_dev *rtwdev, bool pause);
2292 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
2293 void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
2294
2295 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
2296 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
2297 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
2298 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
2299 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
2300 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
2301
2302 int (*mac_pre_init)(struct rtw89_dev *rtwdev);
2303 int (*mac_post_init)(struct rtw89_dev *rtwdev);
2304 int (*deinit)(struct rtw89_dev *rtwdev);
2305
2306 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
2307 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
2308 void (*dump_err_status)(struct rtw89_dev *rtwdev);
2309 int (*napi_poll)(struct napi_struct *napi, int budget);
2310
2311 /* Deal with locks inside recovery_start and recovery_complete callbacks
2312 * by hci instance, and handle things which need to consider under SER.
2313 * e.g. turn on/off interrupts except for the one for halt notification.
2314 */
2315 void (*recovery_start)(struct rtw89_dev *rtwdev);
2316 void (*recovery_complete)(struct rtw89_dev *rtwdev);
2317
2318 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
2319 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
2320 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
2321 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
2322 void (*clr_idx_all)(struct rtw89_dev *rtwdev);
2323 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
2324 void (*disable_intr)(struct rtw89_dev *rtwdev);
2325 void (*enable_intr)(struct rtw89_dev *rtwdev);
2326 int (*rst_bdram)(struct rtw89_dev *rtwdev);
2327};
2328
2329struct rtw89_hci_info {
2330 const struct rtw89_hci_ops *ops;
2331 enum rtw89_hci_type type;
2332 u32 rpwm_addr;
2333 u32 cpwm_addr;
2334 bool paused;
2335};
2336
2337struct rtw89_chip_ops {
2338 int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
2339 int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
2340 void (*bb_reset)(struct rtw89_dev *rtwdev,
2341 enum rtw89_phy_idx phy_idx);
2342 void (*bb_sethw)(struct rtw89_dev *rtwdev);
2343 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2344 u32 addr, u32 mask);
2345 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
2346 u32 addr, u32 mask, u32 data);
2347 void (*set_channel)(struct rtw89_dev *rtwdev,
2348 const struct rtw89_chan *chan,
2349 enum rtw89_mac_idx mac_idx,
2350 enum rtw89_phy_idx phy_idx);
2351 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
2352 struct rtw89_channel_help_params *p,
2353 const struct rtw89_chan *chan,
2354 enum rtw89_mac_idx mac_idx,
2355 enum rtw89_phy_idx phy_idx);
2356 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
2357 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
2358 void (*fem_setup)(struct rtw89_dev *rtwdev);
2359 void (*rfk_init)(struct rtw89_dev *rtwdev);
2360 void (*rfk_channel)(struct rtw89_dev *rtwdev);
2361 void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
2362 enum rtw89_phy_idx phy_idx);
2363 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
2364 void (*rfk_track)(struct rtw89_dev *rtwdev);
2365 void (*power_trim)(struct rtw89_dev *rtwdev);
2366 void (*set_txpwr)(struct rtw89_dev *rtwdev,
2367 const struct rtw89_chan *chan,
2368 enum rtw89_phy_idx phy_idx);
2369 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
2370 enum rtw89_phy_idx phy_idx);
2371 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
2372 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
2373 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
2374 void (*query_ppdu)(struct rtw89_dev *rtwdev,
2375 struct rtw89_rx_phy_ppdu *phy_ppdu,
2376 struct ieee80211_rx_status *status);
2377 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
2378 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
2379 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
2380 s8 pw_ofst, enum rtw89_mac_idx mac_idx);
2381 int (*pwr_on_func)(struct rtw89_dev *rtwdev);
2382 int (*pwr_off_func)(struct rtw89_dev *rtwdev);
2383 void (*fill_txdesc)(struct rtw89_dev *rtwdev,
2384 struct rtw89_tx_desc_info *desc_info,
2385 void *txdesc);
2386 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
2387 struct rtw89_tx_desc_info *desc_info,
2388 void *txdesc);
2389 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
2390 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
2391 const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
2392 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
2393 u32 *tx_en, enum rtw89_sch_tx_sel sel);
2394 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
2395 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
2396 struct rtw89_vif *rtwvif,
2397 struct rtw89_sta *rtwsta);
2398
2399 void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
2400 void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
2401 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
2402 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
2403 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
2404 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
2405 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
2406 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
2407 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
2408};
2409
2410enum rtw89_dma_ch {
2411 RTW89_DMA_ACH0 = 0,
2412 RTW89_DMA_ACH1 = 1,
2413 RTW89_DMA_ACH2 = 2,
2414 RTW89_DMA_ACH3 = 3,
2415 RTW89_DMA_ACH4 = 4,
2416 RTW89_DMA_ACH5 = 5,
2417 RTW89_DMA_ACH6 = 6,
2418 RTW89_DMA_ACH7 = 7,
2419 RTW89_DMA_B0MG = 8,
2420 RTW89_DMA_B0HI = 9,
2421 RTW89_DMA_B1MG = 10,
2422 RTW89_DMA_B1HI = 11,
2423 RTW89_DMA_H2C = 12,
2424 RTW89_DMA_CH_NUM = 13
2425};
2426
2427enum rtw89_qta_mode {
2428 RTW89_QTA_SCC,
2429 RTW89_QTA_DLFW,
2430 RTW89_QTA_WOW,
2431
2432 /* keep last */
2433 RTW89_QTA_INVALID,
2434};
2435
2436struct rtw89_hfc_ch_cfg {
2437 u16 min;
2438 u16 max;
2439#define grp_0 0
2440#define grp_1 1
2441#define grp_num 2
2442 u8 grp;
2443};
2444
2445struct rtw89_hfc_ch_info {
2446 u16 aval;
2447 u16 used;
2448};
2449
2450struct rtw89_hfc_pub_cfg {
2451 u16 grp0;
2452 u16 grp1;
2453 u16 pub_max;
2454 u16 wp_thrd;
2455};
2456
2457struct rtw89_hfc_pub_info {
2458 u16 g0_used;
2459 u16 g1_used;
2460 u16 g0_aval;
2461 u16 g1_aval;
2462 u16 pub_aval;
2463 u16 wp_aval;
2464};
2465
2466struct rtw89_hfc_prec_cfg {
2467 u16 ch011_prec;
2468 u16 h2c_prec;
2469 u16 wp_ch07_prec;
2470 u16 wp_ch811_prec;
2471 u8 ch011_full_cond;
2472 u8 h2c_full_cond;
2473 u8 wp_ch07_full_cond;
2474 u8 wp_ch811_full_cond;
2475};
2476
2477struct rtw89_hfc_param {
2478 bool en;
2479 bool h2c_en;
2480 u8 mode;
2481 const struct rtw89_hfc_ch_cfg *ch_cfg;
2482 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
2483 struct rtw89_hfc_pub_cfg pub_cfg;
2484 struct rtw89_hfc_pub_info pub_info;
2485 struct rtw89_hfc_prec_cfg prec_cfg;
2486};
2487
2488struct rtw89_hfc_param_ini {
2489 const struct rtw89_hfc_ch_cfg *ch_cfg;
2490 const struct rtw89_hfc_pub_cfg *pub_cfg;
2491 const struct rtw89_hfc_prec_cfg *prec_cfg;
2492 u8 mode;
2493};
2494
2495struct rtw89_dle_size {
2496 u16 pge_size;
2497 u16 lnk_pge_num;
2498 u16 unlnk_pge_num;
2499};
2500
2501struct rtw89_wde_quota {
2502 u16 hif;
2503 u16 wcpu;
2504 u16 pkt_in;
2505 u16 cpu_io;
2506};
2507
2508struct rtw89_ple_quota {
2509 u16 cma0_tx;
2510 u16 cma1_tx;
2511 u16 c2h;
2512 u16 h2c;
2513 u16 wcpu;
2514 u16 mpdu_proc;
2515 u16 cma0_dma;
2516 u16 cma1_dma;
2517 u16 bb_rpt;
2518 u16 wd_rel;
2519 u16 cpu_io;
2520 u16 tx_rpt;
2521};
2522
2523struct rtw89_dle_mem {
2524 enum rtw89_qta_mode mode;
2525 const struct rtw89_dle_size *wde_size;
2526 const struct rtw89_dle_size *ple_size;
2527 const struct rtw89_wde_quota *wde_min_qt;
2528 const struct rtw89_wde_quota *wde_max_qt;
2529 const struct rtw89_ple_quota *ple_min_qt;
2530 const struct rtw89_ple_quota *ple_max_qt;
2531};
2532
2533struct rtw89_reg_def {
2534 u32 addr;
2535 u32 mask;
2536};
2537
2538struct rtw89_reg2_def {
2539 u32 addr;
2540 u32 data;
2541};
2542
2543struct rtw89_reg3_def {
2544 u32 addr;
2545 u32 mask;
2546 u32 data;
2547};
2548
2549struct rtw89_reg5_def {
2550 u8 flag; /* recognized by parsers */
2551 u8 path;
2552 u32 addr;
2553 u32 mask;
2554 u32 data;
2555};
2556
2557struct rtw89_phy_table {
2558 const struct rtw89_reg2_def *regs;
2559 u32 n_regs;
2560 enum rtw89_rf_path rf_path;
2561 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
2562 enum rtw89_rf_path rf_path, void *data);
2563};
2564
2565struct rtw89_txpwr_table {
2566 const void *data;
2567 u32 size;
2568 void (*load)(struct rtw89_dev *rtwdev,
2569 const struct rtw89_txpwr_table *tbl);
2570};
2571
2572struct rtw89_page_regs {
2573 u32 hci_fc_ctrl;
2574 u32 ch_page_ctrl;
2575 u32 ach_page_ctrl;
2576 u32 ach_page_info;
2577 u32 pub_page_info3;
2578 u32 pub_page_ctrl1;
2579 u32 pub_page_ctrl2;
2580 u32 pub_page_info1;
2581 u32 pub_page_info2;
2582 u32 wp_page_ctrl1;
2583 u32 wp_page_ctrl2;
2584 u32 wp_page_info1;
2585};
2586
2587struct rtw89_imr_info {
2588 u32 wdrls_imr_set;
2589 u32 wsec_imr_reg;
2590 u32 wsec_imr_set;
2591 u32 mpdu_tx_imr_set;
2592 u32 mpdu_rx_imr_set;
2593 u32 sta_sch_imr_set;
2594 u32 txpktctl_imr_b0_reg;
2595 u32 txpktctl_imr_b0_clr;
2596 u32 txpktctl_imr_b0_set;
2597 u32 txpktctl_imr_b1_reg;
2598 u32 txpktctl_imr_b1_clr;
2599 u32 txpktctl_imr_b1_set;
2600 u32 wde_imr_clr;
2601 u32 wde_imr_set;
2602 u32 ple_imr_clr;
2603 u32 ple_imr_set;
2604 u32 host_disp_imr_clr;
2605 u32 host_disp_imr_set;
2606 u32 cpu_disp_imr_clr;
2607 u32 cpu_disp_imr_set;
2608 u32 other_disp_imr_clr;
2609 u32 other_disp_imr_set;
2610 u32 bbrpt_com_err_imr_reg;
2611 u32 bbrpt_chinfo_err_imr_reg;
2612 u32 bbrpt_err_imr_set;
2613 u32 bbrpt_dfs_err_imr_reg;
2614 u32 ptcl_imr_clr;
2615 u32 ptcl_imr_set;
2616 u32 cdma_imr_0_reg;
2617 u32 cdma_imr_0_clr;
2618 u32 cdma_imr_0_set;
2619 u32 cdma_imr_1_reg;
2620 u32 cdma_imr_1_clr;
2621 u32 cdma_imr_1_set;
2622 u32 phy_intf_imr_reg;
2623 u32 phy_intf_imr_clr;
2624 u32 phy_intf_imr_set;
2625 u32 rmac_imr_reg;
2626 u32 rmac_imr_clr;
2627 u32 rmac_imr_set;
2628 u32 tmac_imr_reg;
2629 u32 tmac_imr_clr;
2630 u32 tmac_imr_set;
2631};
2632
2633struct rtw89_rrsr_cfgs {
2634 struct rtw89_reg3_def ref_rate;
2635 struct rtw89_reg3_def rsc;
2636};
2637
2638struct rtw89_dig_regs {
2639 u32 seg0_pd_reg;
2640 u32 pd_lower_bound_mask;
2641 u32 pd_spatial_reuse_en;
2642 struct rtw89_reg_def p0_lna_init;
2643 struct rtw89_reg_def p1_lna_init;
2644 struct rtw89_reg_def p0_tia_init;
2645 struct rtw89_reg_def p1_tia_init;
2646 struct rtw89_reg_def p0_rxb_init;
2647 struct rtw89_reg_def p1_rxb_init;
2648 struct rtw89_reg_def p0_p20_pagcugc_en;
2649 struct rtw89_reg_def p0_s20_pagcugc_en;
2650 struct rtw89_reg_def p1_p20_pagcugc_en;
2651 struct rtw89_reg_def p1_s20_pagcugc_en;
2652};
2653
2654struct rtw89_phy_ul_tb_info {
2655 bool dyn_tb_tri_en;
2656 u8 def_if_bandedge;
2657};
2658
2659struct rtw89_chip_info {
2660 enum rtw89_core_chip_id chip_id;
2661 const struct rtw89_chip_ops *ops;
2662 const char *fw_name;
2663 u32 fifo_size;
2664 u32 dle_scc_rsvd_size;
2665 u16 max_amsdu_limit;
2666 bool dis_2g_40m_ul_ofdma;
2667 u32 rsvd_ple_ofst;
2668 const struct rtw89_hfc_param_ini *hfc_param_ini;
2669 const struct rtw89_dle_mem *dle_mem;
2670 u8 wde_qempty_acq_num;
2671 u8 wde_qempty_mgq_sel;
2672 u32 rf_base_addr[2];
2673 u8 support_chanctx_num;
2674 u8 support_bands;
2675 bool support_bw160;
2676 bool support_ul_tb_ctrl;
2677 bool hw_sec_hdr;
2678 u8 rf_path_num;
2679 u8 tx_nss;
2680 u8 rx_nss;
2681 u8 acam_num;
2682 u8 bcam_num;
2683 u8 scam_num;
2684 u8 bacam_num;
2685 u8 bacam_dynamic_num;
2686 bool bacam_v1;
2687
2688 u8 sec_ctrl_efuse_size;
2689 u32 physical_efuse_size;
2690 u32 logical_efuse_size;
2691 u32 limit_efuse_size;
2692 u32 dav_phy_efuse_size;
2693 u32 dav_log_efuse_size;
2694 u32 phycap_addr;
2695 u32 phycap_size;
2696
2697 const struct rtw89_pwr_cfg * const *pwr_on_seq;
2698 const struct rtw89_pwr_cfg * const *pwr_off_seq;
2699 const struct rtw89_phy_table *bb_table;
2700 const struct rtw89_phy_table *bb_gain_table;
2701 const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
2702 const struct rtw89_phy_table *nctl_table;
2703 const struct rtw89_txpwr_table *byr_table;
2704 const struct rtw89_phy_dig_gain_table *dig_table;
2705 const struct rtw89_dig_regs *dig_regs;
2706 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
2707 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
2708 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2709 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2710 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
2711 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2712 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2713 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
2714 [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2715 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
2716 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2717 [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2718 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2719 [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2720 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2721 [RTW89_REGD_NUM][RTW89_6G_CH_NUM];
2722
2723 u8 txpwr_factor_rf;
2724 u8 txpwr_factor_mac;
2725
2726 u32 para_ver;
2727 u32 wlcx_desired;
2728 u8 btcx_desired;
2729 u8 scbd;
2730 u8 mailbox;
2731 u16 btc_fwinfo_buf;
2732
2733 u8 fcxbtcrpt_ver;
2734 u8 fcxtdma_ver;
2735 u8 fcxslots_ver;
2736 u8 fcxcysta_ver;
2737 u8 fcxstep_ver;
2738 u8 fcxnullsta_ver;
2739 u8 fcxmreg_ver;
2740 u8 fcxgpiodbg_ver;
2741 u8 fcxbtver_ver;
2742 u8 fcxbtscan_ver;
2743 u8 fcxbtafh_ver;
2744 u8 fcxbtdevinfo_ver;
2745
2746 u8 afh_guard_ch;
2747 const u8 *wl_rssi_thres;
2748 const u8 *bt_rssi_thres;
2749 u8 rssi_tol;
2750
2751 u8 mon_reg_num;
2752 const struct rtw89_btc_fbtc_mreg *mon_reg;
2753 u8 rf_para_ulink_num;
2754 const struct rtw89_btc_rf_trx_para *rf_para_ulink;
2755 u8 rf_para_dlink_num;
2756 const struct rtw89_btc_rf_trx_para *rf_para_dlink;
2757 u8 ps_mode_supported;
2758 u8 low_power_hci_modes;
2759
2760 u32 h2c_cctl_func_id;
2761 u32 hci_func_en_addr;
2762 u32 h2c_desc_size;
2763 u32 txwd_body_size;
2764 u32 h2c_ctrl_reg;
2765 const u32 *h2c_regs;
2766 u32 c2h_ctrl_reg;
2767 const u32 *c2h_regs;
2768 const struct rtw89_page_regs *page_regs;
2769 bool cfo_src_fd;
2770 const struct rtw89_reg_def *dcfo_comp;
2771 u8 dcfo_comp_sft;
2772 const struct rtw89_imr_info *imr_info;
2773 const struct rtw89_rrsr_cfgs *rrsr_cfgs;
2774 u32 dma_ch_mask;
2775 const struct wiphy_wowlan_support *wowlan_stub;
2776};
2777
2778union rtw89_bus_info {
2779 const struct rtw89_pci_info *pci;
2780};
2781
2782struct rtw89_driver_info {
2783 const struct rtw89_chip_info *chip;
2784 union rtw89_bus_info bus;
2785};
2786
2787enum rtw89_hcifc_mode {
2788 RTW89_HCIFC_POH = 0,
2789 RTW89_HCIFC_STF = 1,
2790 RTW89_HCIFC_SDIO = 2,
2791
2792 /* keep last */
2793 RTW89_HCIFC_MODE_INVALID,
2794};
2795
2796struct rtw89_dle_info {
2797 enum rtw89_qta_mode qta_mode;
2798 u16 wde_pg_size;
2799 u16 ple_pg_size;
2800 u16 c0_rx_qta;
2801 u16 c1_rx_qta;
2802};
2803
2804enum rtw89_host_rpr_mode {
2805 RTW89_RPR_MODE_POH = 0,
2806 RTW89_RPR_MODE_STF
2807};
2808
2809struct rtw89_mac_info {
2810 struct rtw89_dle_info dle_info;
2811 struct rtw89_hfc_param hfc_param;
2812 enum rtw89_qta_mode qta_mode;
2813 u8 rpwm_seq_num;
2814 u8 cpwm_seq_num;
2815};
2816
2817#define RTW89_COMPLETION_BUF_SIZE 24
2818#define RTW89_WAIT_COND_IDLE UINT_MAX
2819
2820struct rtw89_completion_data {
2821 bool err;
2822 u8 buf[RTW89_COMPLETION_BUF_SIZE];
2823};
2824
2825struct rtw89_wait_info {
2826 atomic_t cond;
2827 struct completion completion;
2828 struct rtw89_completion_data data;
2829};
2830
2831#define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
2832
2833static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
2834{
2835 init_completion(&wait->completion);
2836 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
2837}
2838
2839enum rtw89_fw_type {
2840 RTW89_FW_NORMAL = 1,
2841 RTW89_FW_WOWLAN = 3,
2842};
2843
2844enum rtw89_fw_feature {
2845 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
2846 RTW89_FW_FEATURE_SCAN_OFFLOAD,
2847 RTW89_FW_FEATURE_TX_WAKE,
2848 RTW89_FW_FEATURE_CRASH_TRIGGER,
2849 RTW89_FW_FEATURE_PACKET_DROP,
2850 RTW89_FW_FEATURE_NO_DEEP_PS,
2851};
2852
2853struct rtw89_fw_suit {
2854 const u8 *data;
2855 u32 size;
2856 u8 major_ver;
2857 u8 minor_ver;
2858 u8 sub_ver;
2859 u8 sub_idex;
2860 u16 build_year;
2861 u16 build_mon;
2862 u16 build_date;
2863 u16 build_hour;
2864 u16 build_min;
2865 u8 cmd_ver;
2866};
2867
2868#define RTW89_FW_VER_CODE(major, minor, sub, idx) \
2869 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
2870#define RTW89_FW_SUIT_VER_CODE(s) \
2871 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
2872
2873#define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \
2874 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \
2875 (mfw_hdr)->ver.minor, \
2876 (mfw_hdr)->ver.sub, \
2877 (mfw_hdr)->ver.idx)
2878
2879#define RTW89_FW_HDR_VER_CODE(fw_hdr) \
2880 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \
2881 GET_FW_HDR_MINOR_VERSION(fw_hdr), \
2882 GET_FW_HDR_SUBVERSION(fw_hdr), \
2883 GET_FW_HDR_SUBINDEX(fw_hdr))
2884
2885struct rtw89_fw_info {
2886 const struct firmware *firmware;
2887 struct rtw89_dev *rtwdev;
2888 struct completion completion;
2889 u8 h2c_seq;
2890 u8 rec_seq;
2891 struct rtw89_fw_suit normal;
2892 struct rtw89_fw_suit wowlan;
2893 bool fw_log_enable;
2894 u32 feature_map;
2895};
2896
2897#define RTW89_CHK_FW_FEATURE(_feat, _fw) \
2898 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
2899
2900#define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
2901 ((_fw)->feature_map |= BIT(_fw_feature))
2902
2903struct rtw89_cam_info {
2904 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
2905 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
2906 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
2907 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
2908 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
2909};
2910
2911enum rtw89_sar_sources {
2912 RTW89_SAR_SOURCE_NONE,
2913 RTW89_SAR_SOURCE_COMMON,
2914
2915 RTW89_SAR_SOURCE_NR,
2916};
2917
2918enum rtw89_sar_subband {
2919 RTW89_SAR_2GHZ_SUBBAND,
2920 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
2921 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
2922 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */
2923 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
2924 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
2925 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */
2926 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
2927 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
2928 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */
2929
2930 RTW89_SAR_SUBBAND_NR,
2931};
2932
2933struct rtw89_sar_cfg_common {
2934 bool set[RTW89_SAR_SUBBAND_NR];
2935 s32 cfg[RTW89_SAR_SUBBAND_NR];
2936};
2937
2938struct rtw89_sar_info {
2939 /* used to decide how to acces SAR cfg union */
2940 enum rtw89_sar_sources src;
2941
2942 /* reserved for different knids of SAR cfg struct.
2943 * supposed that a single cfg struct cannot handle various SAR sources.
2944 */
2945 union {
2946 struct rtw89_sar_cfg_common cfg_common;
2947 };
2948};
2949
2950struct rtw89_chanctx_cfg {
2951 enum rtw89_sub_entity_idx idx;
2952};
2953
2954enum rtw89_entity_mode {
2955 RTW89_ENTITY_MODE_SCC,
2956};
2957
2958struct rtw89_sub_entity {
2959 struct cfg80211_chan_def chandef;
2960 struct rtw89_chan chan;
2961 struct rtw89_chan_rcd rcd;
2962 struct rtw89_chanctx_cfg *cfg;
2963};
2964
2965struct rtw89_hal {
2966 u32 rx_fltr;
2967 u8 cv;
2968 u32 sw_amsdu_max_size;
2969 u32 antenna_tx;
2970 u32 antenna_rx;
2971 u8 tx_nss;
2972 u8 rx_nss;
2973 bool tx_path_diversity;
2974 bool support_cckpd;
2975 bool support_igi;
2976
2977 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
2978 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
2979
2980 bool entity_active;
2981 enum rtw89_entity_mode entity_mode;
2982};
2983
2984#define RTW89_MAX_MAC_ID_NUM 128
2985#define RTW89_MAX_PKT_OFLD_NUM 255
2986
2987enum rtw89_flags {
2988 RTW89_FLAG_POWERON,
2989 RTW89_FLAG_FW_RDY,
2990 RTW89_FLAG_RUNNING,
2991 RTW89_FLAG_BFEE_MON,
2992 RTW89_FLAG_BFEE_EN,
2993 RTW89_FLAG_NAPI_RUNNING,
2994 RTW89_FLAG_LEISURE_PS,
2995 RTW89_FLAG_LOW_POWER_MODE,
2996 RTW89_FLAG_INACTIVE_PS,
2997 RTW89_FLAG_CRASH_SIMULATING,
2998 RTW89_FLAG_WOWLAN,
2999 RTW89_FLAG_FORBIDDEN_TRACK_WROK,
3000 RTW89_FLAG_CHANGING_INTERFACE,
3001
3002 NUM_OF_RTW89_FLAGS,
3003};
3004
3005enum rtw89_pkt_drop_sel {
3006 RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
3007 RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
3008 RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
3009 RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
3010 RTW89_PKT_DROP_SEL_MACID_ALL,
3011 RTW89_PKT_DROP_SEL_MG0_ONCE,
3012 RTW89_PKT_DROP_SEL_HIQ_ONCE,
3013 RTW89_PKT_DROP_SEL_HIQ_PORT,
3014 RTW89_PKT_DROP_SEL_HIQ_MBSSID,
3015 RTW89_PKT_DROP_SEL_BAND,
3016 RTW89_PKT_DROP_SEL_BAND_ONCE,
3017 RTW89_PKT_DROP_SEL_REL_MACID,
3018 RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
3019 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
3020};
3021
3022struct rtw89_pkt_drop_params {
3023 enum rtw89_pkt_drop_sel sel;
3024 enum rtw89_mac_idx mac_band;
3025 u8 macid;
3026 u8 port;
3027 u8 mbssid;
3028 bool tf_trs;
3029 u32 macid_band_sel[4];
3030};
3031
3032struct rtw89_pkt_stat {
3033 u16 beacon_nr;
3034 u32 rx_rate_cnt[RTW89_HW_RATE_NR];
3035};
3036
3037DECLARE_EWMA(thermal, 4, 4);
3038
3039struct rtw89_phy_stat {
3040 struct ewma_thermal avg_thermal[RF_PATH_MAX];
3041 struct rtw89_pkt_stat cur_pkt_stat;
3042 struct rtw89_pkt_stat last_pkt_stat;
3043};
3044
3045#define RTW89_DACK_PATH_NR 2
3046#define RTW89_DACK_IDX_NR 2
3047#define RTW89_DACK_MSBK_NR 16
3048struct rtw89_dack_info {
3049 bool dack_done;
3050 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
3051 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3052 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3053 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
3054 u32 dack_cnt;
3055 bool addck_timeout[RTW89_DACK_PATH_NR];
3056 bool dadck_timeout[RTW89_DACK_PATH_NR];
3057 bool msbk_timeout[RTW89_DACK_PATH_NR];
3058};
3059
3060#define RTW89_IQK_CHS_NR 2
3061#define RTW89_IQK_PATH_NR 4
3062
3063struct rtw89_rfk_mcc_info {
3064 u8 ch[RTW89_IQK_CHS_NR];
3065 u8 band[RTW89_IQK_CHS_NR];
3066 u8 table_idx;
3067};
3068
3069struct rtw89_lck_info {
3070 u8 thermal[RF_PATH_MAX];
3071};
3072
3073struct rtw89_rx_dck_info {
3074 u8 thermal[RF_PATH_MAX];
3075};
3076
3077struct rtw89_iqk_info {
3078 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3079 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3080 bool lok_fail[RTW89_IQK_PATH_NR];
3081 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3082 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3083 u32 iqk_fail_cnt;
3084 bool is_iqk_init;
3085 u32 iqk_channel[RTW89_IQK_CHS_NR];
3086 u8 iqk_band[RTW89_IQK_PATH_NR];
3087 u8 iqk_ch[RTW89_IQK_PATH_NR];
3088 u8 iqk_bw[RTW89_IQK_PATH_NR];
3089 u8 kcount;
3090 u8 iqk_times;
3091 u8 version;
3092 u32 nb_txcfir[RTW89_IQK_PATH_NR];
3093 u32 nb_rxcfir[RTW89_IQK_PATH_NR];
3094 u32 bp_txkresult[RTW89_IQK_PATH_NR];
3095 u32 bp_rxkresult[RTW89_IQK_PATH_NR];
3096 u32 bp_iqkenable[RTW89_IQK_PATH_NR];
3097 bool is_wb_txiqk[RTW89_IQK_PATH_NR];
3098 bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
3099 bool is_nbiqk;
3100 bool iqk_fft_en;
3101 bool iqk_xym_en;
3102 bool iqk_sram_en;
3103 bool iqk_cfir_en;
3104 u8 thermal[RTW89_IQK_PATH_NR];
3105 bool thermal_rek_en;
3106 u32 syn1to2;
3107 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3108 u8 iqk_table_idx[RTW89_IQK_PATH_NR];
3109 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3110 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
3111};
3112
3113#define RTW89_DPK_RF_PATH 2
3114#define RTW89_DPK_AVG_THERMAL_NUM 8
3115#define RTW89_DPK_BKUP_NUM 2
3116struct rtw89_dpk_bkup_para {
3117 enum rtw89_band band;
3118 enum rtw89_bandwidth bw;
3119 u8 ch;
3120 bool path_ok;
3121 u8 mdpd_en;
3122 u8 txagc_dpk;
3123 u8 ther_dpk;
3124 u8 gs;
3125 u16 pwsf;
3126};
3127
3128struct rtw89_dpk_info {
3129 bool is_dpk_enable;
3130 bool is_dpk_reload_en;
3131 u8 dpk_gs[RTW89_PHY_MAX];
3132 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3133 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3134 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3135 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3136 u8 cur_idx[RTW89_DPK_RF_PATH];
3137 u8 cur_k_set;
3138 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
3139};
3140
3141struct rtw89_fem_info {
3142 bool elna_2g;
3143 bool elna_5g;
3144 bool epa_2g;
3145 bool epa_5g;
3146 bool epa_6g;
3147};
3148
3149struct rtw89_phy_ch_info {
3150 u8 rssi_min;
3151 u16 rssi_min_macid;
3152 u8 pre_rssi_min;
3153 u8 rssi_max;
3154 u16 rssi_max_macid;
3155 u8 rxsc_160;
3156 u8 rxsc_80;
3157 u8 rxsc_40;
3158 u8 rxsc_20;
3159 u8 rxsc_l;
3160 u8 is_noisy;
3161};
3162
3163struct rtw89_agc_gaincode_set {
3164 u8 lna_idx;
3165 u8 tia_idx;
3166 u8 rxb_idx;
3167};
3168
3169#define IGI_RSSI_TH_NUM 5
3170#define FA_TH_NUM 4
3171#define LNA_GAIN_NUM 7
3172#define TIA_GAIN_NUM 2
3173struct rtw89_dig_info {
3174 struct rtw89_agc_gaincode_set cur_gaincode;
3175 bool force_gaincode_idx_en;
3176 struct rtw89_agc_gaincode_set force_gaincode;
3177 u8 igi_rssi_th[IGI_RSSI_TH_NUM];
3178 u16 fa_th[FA_TH_NUM];
3179 u8 igi_rssi;
3180 u8 igi_fa_rssi;
3181 u8 fa_rssi_ofst;
3182 u8 dyn_igi_max;
3183 u8 dyn_igi_min;
3184 bool dyn_pd_th_en;
3185 u8 dyn_pd_th_max;
3186 u8 pd_low_th_ofst;
3187 u8 ib_pbk;
3188 s8 ib_pkpwr;
3189 s8 lna_gain_a[LNA_GAIN_NUM];
3190 s8 lna_gain_g[LNA_GAIN_NUM];
3191 s8 *lna_gain;
3192 s8 tia_gain_a[TIA_GAIN_NUM];
3193 s8 tia_gain_g[TIA_GAIN_NUM];
3194 s8 *tia_gain;
3195 bool is_linked_pre;
3196 bool bypass_dig;
3197};
3198
3199enum rtw89_multi_cfo_mode {
3200 RTW89_PKT_BASED_AVG_MODE = 0,
3201 RTW89_ENTRY_BASED_AVG_MODE = 1,
3202 RTW89_TP_BASED_AVG_MODE = 2,
3203};
3204
3205enum rtw89_phy_cfo_status {
3206 RTW89_PHY_DCFO_STATE_NORMAL = 0,
3207 RTW89_PHY_DCFO_STATE_ENHANCE = 1,
3208 RTW89_PHY_DCFO_STATE_HOLD = 2,
3209 RTW89_PHY_DCFO_STATE_MAX
3210};
3211
3212enum rtw89_phy_cfo_ul_ofdma_acc_mode {
3213 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
3214 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
3215};
3216
3217struct rtw89_cfo_tracking_info {
3218 u16 cfo_timer_ms;
3219 bool cfo_trig_by_timer_en;
3220 enum rtw89_phy_cfo_status phy_cfo_status;
3221 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
3222 u8 phy_cfo_trk_cnt;
3223 bool is_adjust;
3224 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
3225 bool apply_compensation;
3226 u8 crystal_cap;
3227 u8 crystal_cap_default;
3228 u8 def_x_cap;
3229 s8 x_cap_ofst;
3230 u32 sta_cfo_tolerance;
3231 s32 cfo_tail[CFO_TRACK_MAX_USER];
3232 u16 cfo_cnt[CFO_TRACK_MAX_USER];
3233 s32 cfo_avg_pre;
3234 s32 cfo_avg[CFO_TRACK_MAX_USER];
3235 s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
3236 u32 packet_count;
3237 u32 packet_count_pre;
3238 s32 residual_cfo_acc;
3239 u8 phy_cfotrk_state;
3240 u8 phy_cfotrk_cnt;
3241 bool divergence_lock_en;
3242 u8 x_cap_lb;
3243 u8 x_cap_ub;
3244 u8 lock_cnt;
3245};
3246
3247enum rtw89_tssi_alimk_band {
3248 TSSI_ALIMK_2G = 0,
3249 TSSI_ALIMK_5GL,
3250 TSSI_ALIMK_5GM,
3251 TSSI_ALIMK_5GH,
3252 TSSI_ALIMK_MAX
3253};
3254
3255/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
3256#define TSSI_TRIM_CH_GROUP_NUM 8
3257#define TSSI_TRIM_CH_GROUP_NUM_6G 16
3258
3259#define TSSI_CCK_CH_GROUP_NUM 6
3260#define TSSI_MCS_2G_CH_GROUP_NUM 5
3261#define TSSI_MCS_5G_CH_GROUP_NUM 14
3262#define TSSI_MCS_6G_CH_GROUP_NUM 32
3263#define TSSI_MCS_CH_GROUP_NUM \
3264 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
3265#define TSSI_MAX_CH_NUM 67
3266#define TSSI_ALIMK_VALUE_NUM 8
3267
3268struct rtw89_tssi_info {
3269 u8 thermal[RF_PATH_MAX];
3270 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
3271 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
3272 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
3273 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
3274 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
3275 s8 extra_ofst[RF_PATH_MAX];
3276 bool tssi_tracking_check[RF_PATH_MAX];
3277 u8 default_txagc_offset[RF_PATH_MAX];
3278 u32 base_thermal[RF_PATH_MAX];
3279 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
3280 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
3281 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
3282 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
3283 u32 tssi_alimk_time;
3284};
3285
3286struct rtw89_power_trim_info {
3287 bool pg_thermal_trim;
3288 bool pg_pa_bias_trim;
3289 u8 thermal_trim[RF_PATH_MAX];
3290 u8 pa_bias_trim[RF_PATH_MAX];
3291};
3292
3293struct rtw89_regulatory {
3294 char alpha2[3];
3295 u8 txpwr_regd[RTW89_BAND_MAX];
3296};
3297
3298enum rtw89_ifs_clm_application {
3299 RTW89_IFS_CLM_INIT = 0,
3300 RTW89_IFS_CLM_BACKGROUND = 1,
3301 RTW89_IFS_CLM_ACS = 2,
3302 RTW89_IFS_CLM_DIG = 3,
3303 RTW89_IFS_CLM_TDMA_DIG = 4,
3304 RTW89_IFS_CLM_DBG = 5,
3305 RTW89_IFS_CLM_DBG_MANUAL = 6
3306};
3307
3308enum rtw89_env_racing_lv {
3309 RTW89_RAC_RELEASE = 0,
3310 RTW89_RAC_LV_1 = 1,
3311 RTW89_RAC_LV_2 = 2,
3312 RTW89_RAC_LV_3 = 3,
3313 RTW89_RAC_LV_4 = 4,
3314 RTW89_RAC_MAX_NUM = 5
3315};
3316
3317struct rtw89_ccx_para_info {
3318 enum rtw89_env_racing_lv rac_lv;
3319 u16 mntr_time;
3320 u8 nhm_manual_th_ofst;
3321 u8 nhm_manual_th0;
3322 enum rtw89_ifs_clm_application ifs_clm_app;
3323 u32 ifs_clm_manual_th_times;
3324 u32 ifs_clm_manual_th0;
3325 u8 fahm_manual_th_ofst;
3326 u8 fahm_manual_th0;
3327 u8 fahm_numer_opt;
3328 u8 fahm_denom_opt;
3329};
3330
3331enum rtw89_ccx_edcca_opt_sc_idx {
3332 RTW89_CCX_EDCCA_SEG0_P0 = 0,
3333 RTW89_CCX_EDCCA_SEG0_S1 = 1,
3334 RTW89_CCX_EDCCA_SEG0_S2 = 2,
3335 RTW89_CCX_EDCCA_SEG0_S3 = 3,
3336 RTW89_CCX_EDCCA_SEG1_P0 = 4,
3337 RTW89_CCX_EDCCA_SEG1_S1 = 5,
3338 RTW89_CCX_EDCCA_SEG1_S2 = 6,
3339 RTW89_CCX_EDCCA_SEG1_S3 = 7
3340};
3341
3342enum rtw89_ccx_edcca_opt_bw_idx {
3343 RTW89_CCX_EDCCA_BW20_0 = 0,
3344 RTW89_CCX_EDCCA_BW20_1 = 1,
3345 RTW89_CCX_EDCCA_BW20_2 = 2,
3346 RTW89_CCX_EDCCA_BW20_3 = 3,
3347 RTW89_CCX_EDCCA_BW20_4 = 4,
3348 RTW89_CCX_EDCCA_BW20_5 = 5,
3349 RTW89_CCX_EDCCA_BW20_6 = 6,
3350 RTW89_CCX_EDCCA_BW20_7 = 7
3351};
3352
3353#define RTW89_NHM_TH_NUM 11
3354#define RTW89_FAHM_TH_NUM 11
3355#define RTW89_NHM_RPT_NUM 12
3356#define RTW89_FAHM_RPT_NUM 12
3357#define RTW89_IFS_CLM_NUM 4
3358struct rtw89_env_monitor_info {
3359 u32 ccx_trigger_time;
3360 u64 start_time;
3361 u8 ccx_rpt_stamp;
3362 u8 ccx_watchdog_result;
3363 bool ccx_ongoing;
3364 u8 ccx_rac_lv;
3365 bool ccx_manual_ctrl;
3366 u8 ccx_pre_rssi;
3367 u16 clm_mntr_time;
3368 u16 nhm_mntr_time;
3369 u16 ifs_clm_mntr_time;
3370 enum rtw89_ifs_clm_application ifs_clm_app;
3371 u16 fahm_mntr_time;
3372 u16 edcca_clm_mntr_time;
3373 u16 ccx_period;
3374 u8 ccx_unit_idx;
3375 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
3376 u8 nhm_th[RTW89_NHM_TH_NUM];
3377 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
3378 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
3379 u8 fahm_numer_opt;
3380 u8 fahm_denom_opt;
3381 u8 fahm_th[RTW89_FAHM_TH_NUM];
3382 u16 clm_result;
3383 u16 nhm_result[RTW89_NHM_RPT_NUM];
3384 u8 nhm_wgt[RTW89_NHM_RPT_NUM];
3385 u16 nhm_tx_cnt;
3386 u16 nhm_cca_cnt;
3387 u16 nhm_idle_cnt;
3388 u16 ifs_clm_tx;
3389 u16 ifs_clm_edcca_excl_cca;
3390 u16 ifs_clm_ofdmfa;
3391 u16 ifs_clm_ofdmcca_excl_fa;
3392 u16 ifs_clm_cckfa;
3393 u16 ifs_clm_cckcca_excl_fa;
3394 u16 ifs_clm_total_ifs;
3395 u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
3396 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
3397 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
3398 u16 fahm_result[RTW89_FAHM_RPT_NUM];
3399 u16 fahm_denom_result;
3400 u16 edcca_clm_result;
3401 u8 clm_ratio;
3402 u8 nhm_rpt[RTW89_NHM_RPT_NUM];
3403 u8 nhm_tx_ratio;
3404 u8 nhm_cca_ratio;
3405 u8 nhm_idle_ratio;
3406 u8 nhm_ratio;
3407 u16 nhm_result_sum;
3408 u8 nhm_pwr;
3409 u8 ifs_clm_tx_ratio;
3410 u8 ifs_clm_edcca_excl_cca_ratio;
3411 u8 ifs_clm_cck_fa_ratio;
3412 u8 ifs_clm_ofdm_fa_ratio;
3413 u8 ifs_clm_cck_cca_excl_fa_ratio;
3414 u8 ifs_clm_ofdm_cca_excl_fa_ratio;
3415 u16 ifs_clm_cck_fa_permil;
3416 u16 ifs_clm_ofdm_fa_permil;
3417 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
3418 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
3419 u8 fahm_rpt[RTW89_FAHM_RPT_NUM];
3420 u16 fahm_result_sum;
3421 u8 fahm_ratio;
3422 u8 fahm_denom_ratio;
3423 u8 fahm_pwr;
3424 u8 edcca_clm_ratio;
3425};
3426
3427enum rtw89_ser_rcvy_step {
3428 RTW89_SER_DRV_STOP_TX,
3429 RTW89_SER_DRV_STOP_RX,
3430 RTW89_SER_DRV_STOP_RUN,
3431 RTW89_SER_HAL_STOP_DMA,
3432 RTW89_NUM_OF_SER_FLAGS
3433};
3434
3435struct rtw89_ser {
3436 u8 state;
3437 u8 alarm_event;
3438
3439 struct work_struct ser_hdl_work;
3440 struct delayed_work ser_alarm_work;
3441 const struct state_ent *st_tbl;
3442 const struct event_ent *ev_tbl;
3443 struct list_head msg_q;
3444 spinlock_t msg_q_lock; /* lock when read/write ser msg */
3445 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
3446};
3447
3448enum rtw89_mac_ax_ps_mode {
3449 RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
3450 RTW89_MAC_AX_PS_MODE_LEGACY = 1,
3451 RTW89_MAC_AX_PS_MODE_WMMPS = 2,
3452 RTW89_MAC_AX_PS_MODE_MAX = 3,
3453};
3454
3455enum rtw89_last_rpwm_mode {
3456 RTW89_LAST_RPWM_PS = 0x0,
3457 RTW89_LAST_RPWM_ACTIVE = 0x6,
3458};
3459
3460struct rtw89_lps_parm {
3461 u8 macid;
3462 u8 psmode; /* enum rtw89_mac_ax_ps_mode */
3463 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
3464};
3465
3466struct rtw89_ppdu_sts_info {
3467 struct sk_buff_head rx_queue[RTW89_PHY_MAX];
3468 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
3469};
3470
3471struct rtw89_early_h2c {
3472 struct list_head list;
3473 u8 *h2c;
3474 u16 h2c_len;
3475};
3476
3477struct rtw89_hw_scan_info {
3478 struct ieee80211_vif *scanning_vif;
3479 struct list_head pkt_list[NUM_NL80211_BANDS];
3480 u8 op_pri_ch;
3481 u8 op_chan;
3482 u8 op_bw;
3483 u8 op_band;
3484 u32 last_chan_idx;
3485};
3486
3487enum rtw89_phy_bb_gain_band {
3488 RTW89_BB_GAIN_BAND_2G = 0,
3489 RTW89_BB_GAIN_BAND_5G_L = 1,
3490 RTW89_BB_GAIN_BAND_5G_M = 2,
3491 RTW89_BB_GAIN_BAND_5G_H = 3,
3492 RTW89_BB_GAIN_BAND_6G_L = 4,
3493 RTW89_BB_GAIN_BAND_6G_M = 5,
3494 RTW89_BB_GAIN_BAND_6G_H = 6,
3495 RTW89_BB_GAIN_BAND_6G_UH = 7,
3496
3497 RTW89_BB_GAIN_BAND_NR,
3498};
3499
3500enum rtw89_phy_bb_rxsc_num {
3501 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
3502 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
3503 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
3504};
3505
3506struct rtw89_phy_bb_gain_info {
3507 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3508 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
3509 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3510 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
3511 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3512 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
3513 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
3514 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3515 [RTW89_BB_RXSC_NUM_40];
3516 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3517 [RTW89_BB_RXSC_NUM_80];
3518 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
3519 [RTW89_BB_RXSC_NUM_160];
3520};
3521
3522struct rtw89_phy_efuse_gain {
3523 bool offset_valid;
3524 bool comp_valid;
3525 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
3526 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
3527 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
3528 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
3529};
3530
3531#define RTW89_MAX_PATTERN_NUM 18
3532#define RTW89_MAX_PATTERN_MASK_SIZE 4
3533#define RTW89_MAX_PATTERN_SIZE 128
3534
3535struct rtw89_wow_cam_info {
3536 bool r_w;
3537 u8 idx;
3538 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
3539 u16 crc;
3540 bool negative_pattern_match;
3541 bool skip_mac_hdr;
3542 bool uc;
3543 bool mc;
3544 bool bc;
3545 bool valid;
3546};
3547
3548struct rtw89_wow_param {
3549 struct ieee80211_vif *wow_vif;
3550 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
3551 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
3552 u8 pattern_cnt;
3553 struct list_head pkt_list;
3554};
3555
3556struct rtw89_mcc_info {
3557 struct rtw89_wait_info wait;
3558};
3559
3560struct rtw89_dev {
3561 struct ieee80211_hw *hw;
3562 struct device *dev;
3563 const struct ieee80211_ops *ops;
3564
3565 bool dbcc_en;
3566 struct rtw89_hw_scan_info scan_info;
3567 const struct rtw89_chip_info *chip;
3568 const struct rtw89_pci_info *pci_info;
3569 struct rtw89_hal hal;
3570 struct rtw89_mcc_info mcc;
3571 struct rtw89_mac_info mac;
3572 struct rtw89_fw_info fw;
3573 struct rtw89_hci_info hci;
3574 struct rtw89_efuse efuse;
3575 struct rtw89_traffic_stats stats;
3576
3577 /* ensures exclusive access from mac80211 callbacks */
3578 struct mutex mutex;
3579 struct list_head rtwvifs_list;
3580 /* used to protect rf read write */
3581 struct mutex rf_mutex;
3582 struct workqueue_struct *txq_wq;
3583 struct work_struct txq_work;
3584 struct delayed_work txq_reinvoke_work;
3585 /* used to protect ba_list and forbid_ba_list */
3586 spinlock_t ba_lock;
3587 /* txqs to setup ba session */
3588 struct list_head ba_list;
3589 /* txqs to forbid ba session */
3590 struct list_head forbid_ba_list;
3591 struct work_struct ba_work;
3592 /* used to protect rpwm */
3593 spinlock_t rpwm_lock;
3594
3595 struct rtw89_cam_info cam_info;
3596
3597 struct sk_buff_head c2h_queue;
3598 struct work_struct c2h_work;
3599 struct work_struct ips_work;
3600
3601 struct list_head early_h2c_list;
3602
3603 struct rtw89_ser ser;
3604
3605 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
3606 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
3607 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
3608 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
3609
3610 struct rtw89_phy_stat phystat;
3611 struct rtw89_dack_info dack;
3612 struct rtw89_iqk_info iqk;
3613 struct rtw89_dpk_info dpk;
3614 struct rtw89_rfk_mcc_info rfk_mcc;
3615 struct rtw89_lck_info lck;
3616 struct rtw89_rx_dck_info rx_dck;
3617 bool is_tssi_mode[RF_PATH_MAX];
3618 bool is_bt_iqk_timeout;
3619
3620 struct rtw89_fem_info fem;
3621 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
3622 struct rtw89_tssi_info tssi;
3623 struct rtw89_power_trim_info pwr_trim;
3624
3625 struct rtw89_cfo_tracking_info cfo_tracking;
3626 struct rtw89_env_monitor_info env_monitor;
3627 struct rtw89_dig_info dig;
3628 struct rtw89_phy_ch_info ch_info;
3629 struct rtw89_phy_bb_gain_info bb_gain;
3630 struct rtw89_phy_efuse_gain efuse_gain;
3631 struct rtw89_phy_ul_tb_info ul_tb_info;
3632
3633 struct delayed_work track_work;
3634 struct delayed_work coex_act1_work;
3635 struct delayed_work coex_bt_devinfo_work;
3636 struct delayed_work coex_rfk_chk_work;
3637 struct delayed_work cfo_track_work;
3638 struct delayed_work forbid_ba_work;
3639 struct rtw89_ppdu_sts_info ppdu_sts;
3640 u8 total_sta_assoc;
3641 bool scanning;
3642
3643 const struct rtw89_regulatory *regd;
3644 struct rtw89_sar_info sar;
3645
3646 struct rtw89_btc btc;
3647 enum rtw89_ps_mode ps_mode;
3648 bool lps_enabled;
3649
3650 struct rtw89_wow_param wow;
3651
3652 /* napi structure */
3653 struct net_device netdev;
3654 struct napi_struct napi;
3655 int napi_budget_countdown;
3656
3657 /* HCI related data, keep last */
3658 u8 priv[] __aligned(sizeof(void *));
3659};
3660
3661static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
3662 struct rtw89_core_tx_request *tx_req)
3663{
3664 return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
3665}
3666
3667static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
3668{
3669 rtwdev->hci.ops->reset(rtwdev);
3670}
3671
3672static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
3673{
3674 return rtwdev->hci.ops->start(rtwdev);
3675}
3676
3677static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
3678{
3679 rtwdev->hci.ops->stop(rtwdev);
3680}
3681
3682static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
3683{
3684 return rtwdev->hci.ops->deinit(rtwdev);
3685}
3686
3687static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
3688{
3689 rtwdev->hci.ops->pause(rtwdev, pause);
3690}
3691
3692static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
3693{
3694 rtwdev->hci.ops->switch_mode(rtwdev, low_power);
3695}
3696
3697static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
3698{
3699 rtwdev->hci.ops->recalc_int_mit(rtwdev);
3700}
3701
3702static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
3703{
3704 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
3705}
3706
3707static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
3708{
3709 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
3710}
3711
3712static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
3713 bool drop)
3714{
3715 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
3716 return;
3717
3718 if (rtwdev->hci.ops->flush_queues)
3719 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
3720}
3721
3722static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
3723{
3724 if (rtwdev->hci.ops->recovery_start)
3725 rtwdev->hci.ops->recovery_start(rtwdev);
3726}
3727
3728static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
3729{
3730 if (rtwdev->hci.ops->recovery_complete)
3731 rtwdev->hci.ops->recovery_complete(rtwdev);
3732}
3733
3734static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
3735{
3736 if (rtwdev->hci.ops->enable_intr)
3737 rtwdev->hci.ops->enable_intr(rtwdev);
3738}
3739
3740static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
3741{
3742 if (rtwdev->hci.ops->disable_intr)
3743 rtwdev->hci.ops->disable_intr(rtwdev);
3744}
3745
3746static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
3747{
3748 if (rtwdev->hci.ops->ctrl_txdma_ch)
3749 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
3750}
3751
3752static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
3753{
3754 if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
3755 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
3756}
3757
3758static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
3759{
3760 if (rtwdev->hci.ops->ctrl_trxhci)
3761 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
3762}
3763
3764static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
3765{
3766 int ret = 0;
3767
3768 if (rtwdev->hci.ops->poll_txdma_ch)
3769 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
3770 return ret;
3771}
3772
3773static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
3774{
3775 if (rtwdev->hci.ops->clr_idx_all)
3776 rtwdev->hci.ops->clr_idx_all(rtwdev);
3777}
3778
3779static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
3780{
3781 int ret = 0;
3782
3783 if (rtwdev->hci.ops->rst_bdram)
3784 ret = rtwdev->hci.ops->rst_bdram(rtwdev);
3785 return ret;
3786}
3787
3788static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
3789{
3790 if (rtwdev->hci.ops->clear)
3791 rtwdev->hci.ops->clear(rtwdev, pdev);
3792}
3793
3794static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
3795{
3796 return rtwdev->hci.ops->read8(rtwdev, addr);
3797}
3798
3799static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
3800{
3801 return rtwdev->hci.ops->read16(rtwdev, addr);
3802}
3803
3804static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
3805{
3806 return rtwdev->hci.ops->read32(rtwdev, addr);
3807}
3808
3809static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
3810{
3811 rtwdev->hci.ops->write8(rtwdev, addr, data);
3812}
3813
3814static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
3815{
3816 rtwdev->hci.ops->write16(rtwdev, addr, data);
3817}
3818
3819static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
3820{
3821 rtwdev->hci.ops->write32(rtwdev, addr, data);
3822}
3823
3824static inline void
3825rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
3826{
3827 u8 val;
3828
3829 val = rtw89_read8(rtwdev, addr);
3830 rtw89_write8(rtwdev, addr, val | bit);
3831}
3832
3833static inline void
3834rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
3835{
3836 u16 val;
3837
3838 val = rtw89_read16(rtwdev, addr);
3839 rtw89_write16(rtwdev, addr, val | bit);
3840}
3841
3842static inline void
3843rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
3844{
3845 u32 val;
3846
3847 val = rtw89_read32(rtwdev, addr);
3848 rtw89_write32(rtwdev, addr, val | bit);
3849}
3850
3851static inline void
3852rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
3853{
3854 u8 val;
3855
3856 val = rtw89_read8(rtwdev, addr);
3857 rtw89_write8(rtwdev, addr, val & ~bit);
3858}
3859
3860static inline void
3861rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
3862{
3863 u16 val;
3864
3865 val = rtw89_read16(rtwdev, addr);
3866 rtw89_write16(rtwdev, addr, val & ~bit);
3867}
3868
3869static inline void
3870rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
3871{
3872 u32 val;
3873
3874 val = rtw89_read32(rtwdev, addr);
3875 rtw89_write32(rtwdev, addr, val & ~bit);
3876}
3877
3878static inline u32
3879rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3880{
3881 u32 shift = __ffs(mask);
3882 u32 orig;
3883 u32 ret;
3884
3885 orig = rtw89_read32(rtwdev, addr);
3886 ret = (orig & mask) >> shift;
3887
3888 return ret;
3889}
3890
3891static inline u16
3892rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3893{
3894 u32 shift = __ffs(mask);
3895 u32 orig;
3896 u32 ret;
3897
3898 orig = rtw89_read16(rtwdev, addr);
3899 ret = (orig & mask) >> shift;
3900
3901 return ret;
3902}
3903
3904static inline u8
3905rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3906{
3907 u32 shift = __ffs(mask);
3908 u32 orig;
3909 u32 ret;
3910
3911 orig = rtw89_read8(rtwdev, addr);
3912 ret = (orig & mask) >> shift;
3913
3914 return ret;
3915}
3916
3917static inline void
3918rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
3919{
3920 u32 shift = __ffs(mask);
3921 u32 orig;
3922 u32 set;
3923
3924 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
3925
3926 orig = rtw89_read32(rtwdev, addr);
3927 set = (orig & ~mask) | ((data << shift) & mask);
3928 rtw89_write32(rtwdev, addr, set);
3929}
3930
3931static inline void
3932rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
3933{
3934 u32 shift;
3935 u16 orig, set;
3936
3937 mask &= 0xffff;
3938 shift = __ffs(mask);
3939
3940 orig = rtw89_read16(rtwdev, addr);
3941 set = (orig & ~mask) | ((data << shift) & mask);
3942 rtw89_write16(rtwdev, addr, set);
3943}
3944
3945static inline void
3946rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
3947{
3948 u32 shift;
3949 u8 orig, set;
3950
3951 mask &= 0xff;
3952 shift = __ffs(mask);
3953
3954 orig = rtw89_read8(rtwdev, addr);
3955 set = (orig & ~mask) | ((data << shift) & mask);
3956 rtw89_write8(rtwdev, addr, set);
3957}
3958
3959static inline u32
3960rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3961 u32 addr, u32 mask)
3962{
3963 u32 val;
3964
3965 mutex_lock(&rtwdev->rf_mutex);
3966 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
3967 mutex_unlock(&rtwdev->rf_mutex);
3968
3969 return val;
3970}
3971
3972static inline void
3973rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3974 u32 addr, u32 mask, u32 data)
3975{
3976 mutex_lock(&rtwdev->rf_mutex);
3977 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
3978 mutex_unlock(&rtwdev->rf_mutex);
3979}
3980
3981static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
3982{
3983 void *p = rtwtxq;
3984
3985 return container_of(p, struct ieee80211_txq, drv_priv);
3986}
3987
3988static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
3989 struct ieee80211_txq *txq)
3990{
3991 struct rtw89_txq *rtwtxq;
3992
3993 if (!txq)
3994 return;
3995
3996 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3997 INIT_LIST_HEAD(&rtwtxq->list);
3998}
3999
4000static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
4001{
4002 void *p = rtwvif;
4003
4004 return container_of(p, struct ieee80211_vif, drv_priv);
4005}
4006
4007static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
4008{
4009 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
4010}
4011
4012static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
4013{
4014 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
4015}
4016
4017static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
4018{
4019 void *p = rtwsta;
4020
4021 return container_of(p, struct ieee80211_sta, drv_priv);
4022}
4023
4024static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
4025{
4026 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
4027}
4028
4029static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
4030{
4031 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
4032}
4033
4034static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
4035{
4036 if (hw_bw == RTW89_CHANNEL_WIDTH_160)
4037 return RATE_INFO_BW_160;
4038 else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
4039 return RATE_INFO_BW_80;
4040 else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
4041 return RATE_INFO_BW_40;
4042 else
4043 return RATE_INFO_BW_20;
4044}
4045
4046static inline
4047enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
4048{
4049 switch (hw_band) {
4050 default:
4051 case RTW89_BAND_2G:
4052 return NL80211_BAND_2GHZ;
4053 case RTW89_BAND_5G:
4054 return NL80211_BAND_5GHZ;
4055 case RTW89_BAND_6G:
4056 return NL80211_BAND_6GHZ;
4057 }
4058}
4059
4060static inline
4061enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
4062{
4063 switch (nl_band) {
4064 default:
4065 case NL80211_BAND_2GHZ:
4066 return RTW89_BAND_2G;
4067 case NL80211_BAND_5GHZ:
4068 return RTW89_BAND_5G;
4069 case NL80211_BAND_6GHZ:
4070 return RTW89_BAND_6G;
4071 }
4072}
4073
4074static inline
4075enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
4076{
4077 switch (width) {
4078 default:
4079 WARN(1, "Not support bandwidth %d\n", width);
4080 fallthrough;
4081 case NL80211_CHAN_WIDTH_20_NOHT:
4082 case NL80211_CHAN_WIDTH_20:
4083 return RTW89_CHANNEL_WIDTH_20;
4084 case NL80211_CHAN_WIDTH_40:
4085 return RTW89_CHANNEL_WIDTH_40;
4086 case NL80211_CHAN_WIDTH_80:
4087 return RTW89_CHANNEL_WIDTH_80;
4088 case NL80211_CHAN_WIDTH_160:
4089 return RTW89_CHANNEL_WIDTH_160;
4090 }
4091}
4092
4093static inline
4094struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
4095 struct rtw89_sta *rtwsta)
4096{
4097 if (rtwsta) {
4098 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4099
4100 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
4101 return &rtwsta->addr_cam;
4102 }
4103 return &rtwvif->addr_cam;
4104}
4105
4106static inline
4107struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
4108 struct rtw89_sta *rtwsta)
4109{
4110 if (rtwsta) {
4111 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
4112
4113 if (sta->tdls)
4114 return &rtwsta->bssid_cam;
4115 }
4116 return &rtwvif->bssid_cam;
4117}
4118
4119static inline
4120void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
4121 struct rtw89_channel_help_params *p,
4122 const struct rtw89_chan *chan,
4123 enum rtw89_mac_idx mac_idx,
4124 enum rtw89_phy_idx phy_idx)
4125{
4126 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
4127 mac_idx, phy_idx);
4128}
4129
4130static inline
4131void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
4132 struct rtw89_channel_help_params *p,
4133 const struct rtw89_chan *chan,
4134 enum rtw89_mac_idx mac_idx,
4135 enum rtw89_phy_idx phy_idx)
4136{
4137 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
4138 mac_idx, phy_idx);
4139}
4140
4141static inline
4142const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
4143 enum rtw89_sub_entity_idx idx)
4144{
4145 struct rtw89_hal *hal = &rtwdev->hal;
4146
4147 return &hal->sub[idx].chandef;
4148}
4149
4150static inline
4151const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
4152 enum rtw89_sub_entity_idx idx)
4153{
4154 struct rtw89_hal *hal = &rtwdev->hal;
4155
4156 return &hal->sub[idx].chan;
4157}
4158
4159static inline
4160const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
4161 enum rtw89_sub_entity_idx idx)
4162{
4163 struct rtw89_hal *hal = &rtwdev->hal;
4164
4165 return &hal->sub[idx].rcd;
4166}
4167
4168static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
4169{
4170 const struct rtw89_chip_info *chip = rtwdev->chip;
4171
4172 if (chip->ops->fem_setup)
4173 chip->ops->fem_setup(rtwdev);
4174}
4175
4176static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
4177{
4178 const struct rtw89_chip_info *chip = rtwdev->chip;
4179
4180 if (chip->ops->bb_sethw)
4181 chip->ops->bb_sethw(rtwdev);
4182}
4183
4184static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
4185{
4186 const struct rtw89_chip_info *chip = rtwdev->chip;
4187
4188 if (chip->ops->rfk_init)
4189 chip->ops->rfk_init(rtwdev);
4190}
4191
4192static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
4193{
4194 const struct rtw89_chip_info *chip = rtwdev->chip;
4195
4196 if (chip->ops->rfk_channel)
4197 chip->ops->rfk_channel(rtwdev);
4198}
4199
4200static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
4201 enum rtw89_phy_idx phy_idx)
4202{
4203 const struct rtw89_chip_info *chip = rtwdev->chip;
4204
4205 if (chip->ops->rfk_band_changed)
4206 chip->ops->rfk_band_changed(rtwdev, phy_idx);
4207}
4208
4209static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
4210{
4211 const struct rtw89_chip_info *chip = rtwdev->chip;
4212
4213 if (chip->ops->rfk_scan)
4214 chip->ops->rfk_scan(rtwdev, start);
4215}
4216
4217static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
4218{
4219 const struct rtw89_chip_info *chip = rtwdev->chip;
4220
4221 if (chip->ops->rfk_track)
4222 chip->ops->rfk_track(rtwdev);
4223}
4224
4225static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
4226{
4227 const struct rtw89_chip_info *chip = rtwdev->chip;
4228
4229 if (chip->ops->set_txpwr_ctrl)
4230 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0);
4231}
4232
4233static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
4234{
4235 const struct rtw89_chip_info *chip = rtwdev->chip;
4236
4237 if (chip->ops->power_trim)
4238 chip->ops->power_trim(rtwdev);
4239}
4240
4241static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
4242 enum rtw89_phy_idx phy_idx)
4243{
4244 const struct rtw89_chip_info *chip = rtwdev->chip;
4245
4246 if (chip->ops->init_txpwr_unit)
4247 chip->ops->init_txpwr_unit(rtwdev, phy_idx);
4248}
4249
4250static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
4251 enum rtw89_rf_path rf_path)
4252{
4253 const struct rtw89_chip_info *chip = rtwdev->chip;
4254
4255 if (!chip->ops->get_thermal)
4256 return 0x10;
4257
4258 return chip->ops->get_thermal(rtwdev, rf_path);
4259}
4260
4261static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
4262 struct rtw89_rx_phy_ppdu *phy_ppdu,
4263 struct ieee80211_rx_status *status)
4264{
4265 const struct rtw89_chip_info *chip = rtwdev->chip;
4266
4267 if (chip->ops->query_ppdu)
4268 chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
4269}
4270
4271static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
4272 bool bt_en)
4273{
4274 const struct rtw89_chip_info *chip = rtwdev->chip;
4275
4276 if (chip->ops->bb_ctrl_btc_preagc)
4277 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
4278}
4279
4280static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
4281{
4282 const struct rtw89_chip_info *chip = rtwdev->chip;
4283
4284 if (chip->ops->cfg_txrx_path)
4285 chip->ops->cfg_txrx_path(rtwdev);
4286}
4287
4288static inline
4289void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
4290 struct ieee80211_vif *vif)
4291{
4292 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
4293 const struct rtw89_chip_info *chip = rtwdev->chip;
4294
4295 if (!vif->bss_conf.he_support || !vif->cfg.assoc)
4296 return;
4297
4298 if (chip->ops->set_txpwr_ul_tb_offset)
4299 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
4300}
4301
4302static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
4303 const struct rtw89_txpwr_table *tbl)
4304{
4305 tbl->load(rtwdev, tbl);
4306}
4307
4308static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
4309{
4310 return rtwdev->regd->txpwr_regd[band];
4311}
4312
4313static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
4314{
4315 const struct rtw89_chip_info *chip = rtwdev->chip;
4316
4317 if (chip->ops->ctrl_btg)
4318 chip->ops->ctrl_btg(rtwdev, btg);
4319}
4320
4321static inline
4322void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
4323 struct rtw89_tx_desc_info *desc_info,
4324 void *txdesc)
4325{
4326 const struct rtw89_chip_info *chip = rtwdev->chip;
4327
4328 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
4329}
4330
4331static inline
4332void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
4333 struct rtw89_tx_desc_info *desc_info,
4334 void *txdesc)
4335{
4336 const struct rtw89_chip_info *chip = rtwdev->chip;
4337
4338 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
4339}
4340
4341static inline
4342void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
4343 const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
4344{
4345 const struct rtw89_chip_info *chip = rtwdev->chip;
4346
4347 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
4348}
4349
4350static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
4351{
4352 const struct rtw89_chip_info *chip = rtwdev->chip;
4353
4354 chip->ops->cfg_ctrl_path(rtwdev, wl);
4355}
4356
4357static inline
4358int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
4359 u32 *tx_en, enum rtw89_sch_tx_sel sel)
4360{
4361 const struct rtw89_chip_info *chip = rtwdev->chip;
4362
4363 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
4364}
4365
4366static inline
4367int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
4368{
4369 const struct rtw89_chip_info *chip = rtwdev->chip;
4370
4371 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
4372}
4373
4374static inline
4375int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
4376 struct rtw89_vif *rtwvif,
4377 struct rtw89_sta *rtwsta)
4378{
4379 const struct rtw89_chip_info *chip = rtwdev->chip;
4380
4381 if (!chip->ops->h2c_dctl_sec_cam)
4382 return 0;
4383 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
4384}
4385
4386static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
4387{
4388 __le16 fc = hdr->frame_control;
4389
4390 if (ieee80211_has_tods(fc))
4391 return hdr->addr1;
4392 else if (ieee80211_has_fromds(fc))
4393 return hdr->addr2;
4394 else
4395 return hdr->addr3;
4396}
4397
4398static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
4399{
4400 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
4401 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
4402 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
4403 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
4404 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
4405 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
4406 return true;
4407 return false;
4408}
4409
4410static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
4411 enum rtw89_fw_type type)
4412{
4413 struct rtw89_fw_info *fw_info = &rtwdev->fw;
4414
4415 if (type == RTW89_FW_WOWLAN)
4416 return &fw_info->wowlan;
4417 return &fw_info->normal;
4418}
4419
4420static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
4421 unsigned int length)
4422{
4423 struct sk_buff *skb;
4424
4425 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
4426 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
4427 if (!skb)
4428 return NULL;
4429
4430 skb_reserve(skb, RTW89_RADIOTAP_ROOM);
4431 return skb;
4432 }
4433
4434 return dev_alloc_skb(length);
4435}
4436
4437int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
4438 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
4439int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
4440 struct sk_buff *skb, bool fwdl);
4441void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
4442void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
4443 struct rtw89_tx_desc_info *desc_info,
4444 void *txdesc);
4445void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
4446 struct rtw89_tx_desc_info *desc_info,
4447 void *txdesc);
4448void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
4449 struct rtw89_tx_desc_info *desc_info,
4450 void *txdesc);
4451void rtw89_core_rx(struct rtw89_dev *rtwdev,
4452 struct rtw89_rx_desc_info *desc_info,
4453 struct sk_buff *skb);
4454void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
4455 struct rtw89_rx_desc_info *desc_info,
4456 u8 *data, u32 data_offset);
4457void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
4458void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
4459void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
4460void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
4461int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
4462 struct ieee80211_vif *vif,
4463 struct ieee80211_sta *sta);
4464int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
4465 struct ieee80211_vif *vif,
4466 struct ieee80211_sta *sta);
4467int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
4468 struct ieee80211_vif *vif,
4469 struct ieee80211_sta *sta);
4470int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
4471 struct ieee80211_vif *vif,
4472 struct ieee80211_sta *sta);
4473int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
4474 struct ieee80211_vif *vif,
4475 struct ieee80211_sta *sta);
4476void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
4477 struct ieee80211_sta *sta,
4478 struct cfg80211_tid_config *tid_config);
4479int rtw89_core_init(struct rtw89_dev *rtwdev);
4480void rtw89_core_deinit(struct rtw89_dev *rtwdev);
4481int rtw89_core_register(struct rtw89_dev *rtwdev);
4482void rtw89_core_unregister(struct rtw89_dev *rtwdev);
4483struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
4484 u32 bus_data_size,
4485 const struct rtw89_chip_info *chip);
4486void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
4487void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
4488void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
4489void rtw89_set_channel(struct rtw89_dev *rtwdev);
4490u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
4491void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
4492void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
4493int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
4494 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
4495int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
4496 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
4497void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
4498int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
4499bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
4500int rtw89_regd_init(struct rtw89_dev *rtwdev,
4501 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
4502void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
4503void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
4504 struct rtw89_traffic_stats *stats);
4505int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
4506void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
4507 const struct rtw89_completion_data *data);
4508int rtw89_core_start(struct rtw89_dev *rtwdev);
4509void rtw89_core_stop(struct rtw89_dev *rtwdev);
4510void rtw89_core_update_beacon_work(struct work_struct *work);
4511void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
4512 const u8 *mac_addr, bool hw_scan);
4513void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
4514 struct ieee80211_vif *vif, bool hw_scan);
4515
4516#endif