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1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
2/*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#ifndef ATH11K_HW_H
8#define ATH11K_HW_H
9
10#include "hal.h"
11#include "wmi.h"
12
13/* Target configuration defines */
14
15/* Num VDEVS per radio */
16#define TARGET_NUM_VDEVS(ab) (ab->hw_params.num_vdevs)
17
18#define TARGET_NUM_PEERS_PDEV(ab) (ab->hw_params.num_peers + TARGET_NUM_VDEVS(ab))
19
20/* Num of peers for Single Radio mode */
21#define TARGET_NUM_PEERS_SINGLE(ab) (TARGET_NUM_PEERS_PDEV(ab))
22
23/* Num of peers for DBS */
24#define TARGET_NUM_PEERS_DBS(ab) (2 * TARGET_NUM_PEERS_PDEV(ab))
25
26/* Num of peers for DBS_SBS */
27#define TARGET_NUM_PEERS_DBS_SBS(ab) (3 * TARGET_NUM_PEERS_PDEV(ab))
28
29/* Max num of stations (per radio) */
30#define TARGET_NUM_STATIONS(ab) (ab->hw_params.num_peers)
31
32#define TARGET_NUM_PEERS(ab, x) TARGET_NUM_PEERS_##x(ab)
33#define TARGET_NUM_PEER_KEYS 2
34#define TARGET_NUM_TIDS(ab, x) (2 * TARGET_NUM_PEERS(ab, x) + \
35 4 * TARGET_NUM_VDEVS(ab) + 8)
36
37#define TARGET_AST_SKID_LIMIT 16
38#define TARGET_NUM_OFFLD_PEERS 4
39#define TARGET_NUM_OFFLD_REORDER_BUFFS 4
40
41#define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
42#define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
43#define TARGET_RX_TIMEOUT_LO_PRI 100
44#define TARGET_RX_TIMEOUT_HI_PRI 40
45
46#define TARGET_DECAP_MODE_RAW 0
47#define TARGET_DECAP_MODE_NATIVE_WIFI 1
48#define TARGET_DECAP_MODE_ETH 2
49
50#define TARGET_SCAN_MAX_PENDING_REQS 4
51#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
52#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
53#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
54#define TARGET_GTK_OFFLOAD_MAX_VDEV 3
55#define TARGET_NUM_MCAST_GROUPS 12
56#define TARGET_NUM_MCAST_TABLE_ELEMS 64
57#define TARGET_MCAST2UCAST_MODE 2
58#define TARGET_TX_DBG_LOG_SIZE 1024
59#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
60#define TARGET_VOW_CONFIG 0
61#define TARGET_NUM_MSDU_DESC (2500)
62#define TARGET_MAX_FRAG_ENTRIES 6
63#define TARGET_MAX_BCN_OFFLD 16
64#define TARGET_NUM_WDS_ENTRIES 32
65#define TARGET_DMA_BURST_SIZE 1
66#define TARGET_RX_BATCHMODE 1
67
68#define ATH11K_HW_MAX_QUEUES 4
69#define ATH11K_QUEUE_LEN 4096
70
71#define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
72
73#define ATH11K_FW_DIR "ath11k"
74
75#define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD"
76#define ATH11K_BOARD_API2_FILE "board-2.bin"
77#define ATH11K_DEFAULT_BOARD_FILE "board.bin"
78#define ATH11K_DEFAULT_CAL_FILE "caldata.bin"
79#define ATH11K_AMSS_FILE "amss.bin"
80#define ATH11K_M3_FILE "m3.bin"
81#define ATH11K_REGDB_FILE_NAME "regdb.bin"
82
83enum ath11k_hw_rate_cck {
84 ATH11K_HW_RATE_CCK_LP_11M = 0,
85 ATH11K_HW_RATE_CCK_LP_5_5M,
86 ATH11K_HW_RATE_CCK_LP_2M,
87 ATH11K_HW_RATE_CCK_LP_1M,
88 ATH11K_HW_RATE_CCK_SP_11M,
89 ATH11K_HW_RATE_CCK_SP_5_5M,
90 ATH11K_HW_RATE_CCK_SP_2M,
91};
92
93enum ath11k_hw_rate_ofdm {
94 ATH11K_HW_RATE_OFDM_48M = 0,
95 ATH11K_HW_RATE_OFDM_24M,
96 ATH11K_HW_RATE_OFDM_12M,
97 ATH11K_HW_RATE_OFDM_6M,
98 ATH11K_HW_RATE_OFDM_54M,
99 ATH11K_HW_RATE_OFDM_36M,
100 ATH11K_HW_RATE_OFDM_18M,
101 ATH11K_HW_RATE_OFDM_9M,
102};
103
104enum ath11k_bus {
105 ATH11K_BUS_AHB,
106 ATH11K_BUS_PCI,
107};
108
109#define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
110
111struct hal_rx_desc;
112struct hal_tcl_data_cmd;
113
114struct ath11k_hw_ring_mask {
115 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
116 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
117 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
118 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];
119 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];
120 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
121 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];
122 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];
123};
124
125struct ath11k_hw_tcl2wbm_rbm_map {
126 u8 tcl_ring_num;
127 u8 wbm_ring_num;
128 u8 rbm_id;
129};
130
131struct ath11k_hw_hal_params {
132 enum hal_rx_buf_return_buf_manager rx_buf_rbm;
133 const struct ath11k_hw_tcl2wbm_rbm_map *tcl2wbm_rbm_map;
134};
135
136struct ath11k_hw_params {
137 const char *name;
138 u16 hw_rev;
139 u8 max_radios;
140 u32 bdf_addr;
141
142 struct {
143 const char *dir;
144 size_t board_size;
145 size_t cal_offset;
146 } fw;
147
148 const struct ath11k_hw_ops *hw_ops;
149 const struct ath11k_hw_ring_mask *ring_mask;
150
151 bool internal_sleep_clock;
152
153 const struct ath11k_hw_regs *regs;
154 u32 qmi_service_ins_id;
155 const struct ce_attr *host_ce_config;
156 u32 ce_count;
157 const struct ce_pipe_config *target_ce_config;
158 u32 target_ce_count;
159 const struct service_to_pipe *svc_to_ce_map;
160 u32 svc_to_ce_map_len;
161
162 bool single_pdev_only;
163
164 bool rxdma1_enable;
165 int num_rxmda_per_pdev;
166 bool rx_mac_buf_ring;
167 bool vdev_start_delay;
168 bool htt_peer_map_v2;
169
170 struct {
171 u8 fft_sz;
172 u8 fft_pad_sz;
173 u8 summary_pad_sz;
174 u8 fft_hdr_len;
175 u16 max_fft_bins;
176 bool fragment_160mhz;
177 } spectral;
178
179 u16 interface_modes;
180 bool supports_monitor;
181 bool full_monitor_mode;
182 bool supports_shadow_regs;
183 bool idle_ps;
184 bool supports_sta_ps;
185 bool cold_boot_calib;
186 bool cbcal_restart_fw;
187 int fw_mem_mode;
188 u32 num_vdevs;
189 u32 num_peers;
190 bool supports_suspend;
191 u32 hal_desc_sz;
192 bool supports_regdb;
193 bool fix_l1ss;
194 bool credit_flow;
195 u8 max_tx_ring;
196 const struct ath11k_hw_hal_params *hal_params;
197 bool supports_dynamic_smps_6ghz;
198 bool alloc_cacheable_memory;
199 bool supports_rssi_stats;
200 bool fw_wmi_diag_event;
201 bool current_cc_support;
202 bool dbr_debug_support;
203 bool global_reset;
204 const struct cfg80211_sar_capa *bios_sar_capa;
205 bool m3_fw_support;
206 bool fixed_bdf_addr;
207 bool fixed_mem_region;
208 bool static_window_map;
209 bool hybrid_bus_type;
210 bool fixed_fw_mem;
211 bool support_off_channel_tx;
212 bool supports_multi_bssid;
213
214 struct {
215 u32 start;
216 u32 end;
217 } sram_dump;
218
219 bool tcl_ring_retry;
220 u32 tx_ring_size;
221 bool smp2p_wow_exit;
222 bool support_fw_mac_sequence;
223};
224
225struct ath11k_hw_ops {
226 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
227 void (*wmi_init_config)(struct ath11k_base *ab,
228 struct target_resource_config *config);
229 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);
230 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
231 void (*tx_mesh_enable)(struct ath11k_base *ab,
232 struct hal_tcl_data_cmd *tcl_cmd);
233 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
234 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
235 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
236 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
237 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
238 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
239 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
240 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
241 bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc);
242 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
243 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
244 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
245 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
246 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
247 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
248 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
249 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
250 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
251 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
252 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
253 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
254 void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,
255 struct hal_rx_desc *ldesc);
256 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
257 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
258 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
259 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
260 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
261 void (*reo_setup)(struct ath11k_base *ab);
262 u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
263 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
264 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
265 u32 (*get_ring_selector)(struct sk_buff *skb);
266};
267
268extern const struct ath11k_hw_ops ipq8074_ops;
269extern const struct ath11k_hw_ops ipq6018_ops;
270extern const struct ath11k_hw_ops qca6390_ops;
271extern const struct ath11k_hw_ops qcn9074_ops;
272extern const struct ath11k_hw_ops wcn6855_ops;
273extern const struct ath11k_hw_ops wcn6750_ops;
274
275extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
276extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
277extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;
278extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750;
279
280extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074;
281extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390;
282extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750;
283
284static inline
285int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
286 int pdev_idx)
287{
288 if (hw->hw_ops->get_hw_mac_from_pdev_id)
289 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
290
291 return 0;
292}
293
294static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw,
295 int mac_id)
296{
297 if (hw->hw_ops->mac_id_to_pdev_id)
298 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
299
300 return 0;
301}
302
303static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw,
304 int mac_id)
305{
306 if (hw->hw_ops->mac_id_to_srng_id)
307 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
308
309 return 0;
310}
311
312struct ath11k_fw_ie {
313 __le32 id;
314 __le32 len;
315 u8 data[];
316};
317
318enum ath11k_bd_ie_board_type {
319 ATH11K_BD_IE_BOARD_NAME = 0,
320 ATH11K_BD_IE_BOARD_DATA = 1,
321};
322
323enum ath11k_bd_ie_regdb_type {
324 ATH11K_BD_IE_REGDB_NAME = 0,
325 ATH11K_BD_IE_REGDB_DATA = 1,
326};
327
328enum ath11k_bd_ie_type {
329 /* contains sub IEs of enum ath11k_bd_ie_board_type */
330 ATH11K_BD_IE_BOARD = 0,
331 /* contains sub IEs of enum ath11k_bd_ie_regdb_type */
332 ATH11K_BD_IE_REGDB = 1,
333};
334
335struct ath11k_hw_regs {
336 u32 hal_tcl1_ring_base_lsb;
337 u32 hal_tcl1_ring_base_msb;
338 u32 hal_tcl1_ring_id;
339 u32 hal_tcl1_ring_misc;
340 u32 hal_tcl1_ring_tp_addr_lsb;
341 u32 hal_tcl1_ring_tp_addr_msb;
342 u32 hal_tcl1_ring_consumer_int_setup_ix0;
343 u32 hal_tcl1_ring_consumer_int_setup_ix1;
344 u32 hal_tcl1_ring_msi1_base_lsb;
345 u32 hal_tcl1_ring_msi1_base_msb;
346 u32 hal_tcl1_ring_msi1_data;
347 u32 hal_tcl2_ring_base_lsb;
348 u32 hal_tcl_ring_base_lsb;
349
350 u32 hal_tcl_status_ring_base_lsb;
351
352 u32 hal_reo1_ring_base_lsb;
353 u32 hal_reo1_ring_base_msb;
354 u32 hal_reo1_ring_id;
355 u32 hal_reo1_ring_misc;
356 u32 hal_reo1_ring_hp_addr_lsb;
357 u32 hal_reo1_ring_hp_addr_msb;
358 u32 hal_reo1_ring_producer_int_setup;
359 u32 hal_reo1_ring_msi1_base_lsb;
360 u32 hal_reo1_ring_msi1_base_msb;
361 u32 hal_reo1_ring_msi1_data;
362 u32 hal_reo2_ring_base_lsb;
363 u32 hal_reo1_aging_thresh_ix_0;
364 u32 hal_reo1_aging_thresh_ix_1;
365 u32 hal_reo1_aging_thresh_ix_2;
366 u32 hal_reo1_aging_thresh_ix_3;
367
368 u32 hal_reo1_ring_hp;
369 u32 hal_reo1_ring_tp;
370 u32 hal_reo2_ring_hp;
371
372 u32 hal_reo_tcl_ring_base_lsb;
373 u32 hal_reo_tcl_ring_hp;
374
375 u32 hal_reo_status_ring_base_lsb;
376 u32 hal_reo_status_hp;
377
378 u32 hal_reo_cmd_ring_base_lsb;
379 u32 hal_reo_cmd_ring_hp;
380
381 u32 hal_sw2reo_ring_base_lsb;
382 u32 hal_sw2reo_ring_hp;
383
384 u32 hal_seq_wcss_umac_ce0_src_reg;
385 u32 hal_seq_wcss_umac_ce0_dst_reg;
386 u32 hal_seq_wcss_umac_ce1_src_reg;
387 u32 hal_seq_wcss_umac_ce1_dst_reg;
388
389 u32 hal_wbm_idle_link_ring_base_lsb;
390 u32 hal_wbm_idle_link_ring_misc;
391
392 u32 hal_wbm_release_ring_base_lsb;
393
394 u32 hal_wbm0_release_ring_base_lsb;
395 u32 hal_wbm1_release_ring_base_lsb;
396
397 u32 pcie_qserdes_sysclk_en_sel;
398 u32 pcie_pcs_osc_dtct_config_base;
399
400 u32 hal_shadow_base_addr;
401 u32 hal_reo1_misc_ctl;
402};
403
404extern const struct ath11k_hw_regs ipq8074_regs;
405extern const struct ath11k_hw_regs qca6390_regs;
406extern const struct ath11k_hw_regs qcn9074_regs;
407extern const struct ath11k_hw_regs wcn6855_regs;
408extern const struct ath11k_hw_regs wcn6750_regs;
409
410static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
411{
412 switch (type) {
413 case ATH11K_BD_IE_BOARD:
414 return "board data";
415 case ATH11K_BD_IE_REGDB:
416 return "regdb data";
417 }
418
419 return "unknown";
420}
421
422extern const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855;
423
424#endif