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1// SPDX-License-Identifier: ISC
2/*
3 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/bits.h>
7#include <linux/clk.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/of.h>
11#include <linux/of_device.h>
12#include <linux/platform_device.h>
13#include <linux/property.h>
14#include <linux/regulator/consumer.h>
15#include <linux/remoteproc/qcom_rproc.h>
16#include <linux/of_address.h>
17#include <linux/iommu.h>
18
19#include "ce.h"
20#include "coredump.h"
21#include "debug.h"
22#include "hif.h"
23#include "htc.h"
24#include "snoc.h"
25
26#define ATH10K_SNOC_RX_POST_RETRY_MS 50
27#define CE_POLL_PIPE 4
28#define ATH10K_SNOC_WAKE_IRQ 2
29
30static char *const ce_name[] = {
31 "WLAN_CE_0",
32 "WLAN_CE_1",
33 "WLAN_CE_2",
34 "WLAN_CE_3",
35 "WLAN_CE_4",
36 "WLAN_CE_5",
37 "WLAN_CE_6",
38 "WLAN_CE_7",
39 "WLAN_CE_8",
40 "WLAN_CE_9",
41 "WLAN_CE_10",
42 "WLAN_CE_11",
43};
44
45static const char * const ath10k_regulators[] = {
46 "vdd-0.8-cx-mx",
47 "vdd-1.8-xo",
48 "vdd-1.3-rfa",
49 "vdd-3.3-ch0",
50 "vdd-3.3-ch1",
51};
52
53static const char * const ath10k_clocks[] = {
54 "cxo_ref_clk_pin", "qdss",
55};
56
57static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state);
58static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state);
59static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
60static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state);
61static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state);
62static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state);
63
64static const struct ath10k_snoc_drv_priv drv_priv = {
65 .hw_rev = ATH10K_HW_WCN3990,
66 .dma_mask = DMA_BIT_MASK(35),
67 .msa_size = 0x100000,
68};
69
70#define WCN3990_SRC_WR_IDX_OFFSET 0x3C
71#define WCN3990_DST_WR_IDX_OFFSET 0x40
72
73static struct ath10k_shadow_reg_cfg target_shadow_reg_cfg_map[] = {
74 {
75 .ce_id = __cpu_to_le16(0),
76 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
77 },
78
79 {
80 .ce_id = __cpu_to_le16(3),
81 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
82 },
83
84 {
85 .ce_id = __cpu_to_le16(4),
86 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
87 },
88
89 {
90 .ce_id = __cpu_to_le16(5),
91 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
92 },
93
94 {
95 .ce_id = __cpu_to_le16(7),
96 .reg_offset = __cpu_to_le16(WCN3990_SRC_WR_IDX_OFFSET),
97 },
98
99 {
100 .ce_id = __cpu_to_le16(1),
101 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
102 },
103
104 {
105 .ce_id = __cpu_to_le16(2),
106 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
107 },
108
109 {
110 .ce_id = __cpu_to_le16(7),
111 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
112 },
113
114 {
115 .ce_id = __cpu_to_le16(8),
116 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
117 },
118
119 {
120 .ce_id = __cpu_to_le16(9),
121 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
122 },
123
124 {
125 .ce_id = __cpu_to_le16(10),
126 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
127 },
128
129 {
130 .ce_id = __cpu_to_le16(11),
131 .reg_offset = __cpu_to_le16(WCN3990_DST_WR_IDX_OFFSET),
132 },
133};
134
135static struct ce_attr host_ce_config_wlan[] = {
136 /* CE0: host->target HTC control streams */
137 {
138 .flags = CE_ATTR_FLAGS,
139 .src_nentries = 16,
140 .src_sz_max = 2048,
141 .dest_nentries = 0,
142 .send_cb = ath10k_snoc_htc_tx_cb,
143 },
144
145 /* CE1: target->host HTT + HTC control */
146 {
147 .flags = CE_ATTR_FLAGS,
148 .src_nentries = 0,
149 .src_sz_max = 2048,
150 .dest_nentries = 512,
151 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
152 },
153
154 /* CE2: target->host WMI */
155 {
156 .flags = CE_ATTR_FLAGS,
157 .src_nentries = 0,
158 .src_sz_max = 2048,
159 .dest_nentries = 64,
160 .recv_cb = ath10k_snoc_htc_rx_cb,
161 },
162
163 /* CE3: host->target WMI */
164 {
165 .flags = CE_ATTR_FLAGS,
166 .src_nentries = 32,
167 .src_sz_max = 2048,
168 .dest_nentries = 0,
169 .send_cb = ath10k_snoc_htc_tx_cb,
170 },
171
172 /* CE4: host->target HTT */
173 {
174 .flags = CE_ATTR_FLAGS | CE_ATTR_DIS_INTR,
175 .src_nentries = 2048,
176 .src_sz_max = 256,
177 .dest_nentries = 0,
178 .send_cb = ath10k_snoc_htt_tx_cb,
179 },
180
181 /* CE5: target->host HTT (ipa_uc->target ) */
182 {
183 .flags = CE_ATTR_FLAGS,
184 .src_nentries = 0,
185 .src_sz_max = 512,
186 .dest_nentries = 512,
187 .recv_cb = ath10k_snoc_htt_rx_cb,
188 },
189
190 /* CE6: target autonomous hif_memcpy */
191 {
192 .flags = CE_ATTR_FLAGS,
193 .src_nentries = 0,
194 .src_sz_max = 0,
195 .dest_nentries = 0,
196 },
197
198 /* CE7: ce_diag, the Diagnostic Window */
199 {
200 .flags = CE_ATTR_FLAGS,
201 .src_nentries = 2,
202 .src_sz_max = 2048,
203 .dest_nentries = 2,
204 },
205
206 /* CE8: Target to uMC */
207 {
208 .flags = CE_ATTR_FLAGS,
209 .src_nentries = 0,
210 .src_sz_max = 2048,
211 .dest_nentries = 128,
212 },
213
214 /* CE9 target->host HTT */
215 {
216 .flags = CE_ATTR_FLAGS,
217 .src_nentries = 0,
218 .src_sz_max = 2048,
219 .dest_nentries = 512,
220 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
221 },
222
223 /* CE10: target->host HTT */
224 {
225 .flags = CE_ATTR_FLAGS,
226 .src_nentries = 0,
227 .src_sz_max = 2048,
228 .dest_nentries = 512,
229 .recv_cb = ath10k_snoc_htt_htc_rx_cb,
230 },
231
232 /* CE11: target -> host PKTLOG */
233 {
234 .flags = CE_ATTR_FLAGS,
235 .src_nentries = 0,
236 .src_sz_max = 2048,
237 .dest_nentries = 512,
238 .recv_cb = ath10k_snoc_pktlog_rx_cb,
239 },
240};
241
242static struct ce_pipe_config target_ce_config_wlan[] = {
243 /* CE0: host->target HTC control and raw streams */
244 {
245 .pipenum = __cpu_to_le32(0),
246 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
247 .nentries = __cpu_to_le32(32),
248 .nbytes_max = __cpu_to_le32(2048),
249 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
250 .reserved = __cpu_to_le32(0),
251 },
252
253 /* CE1: target->host HTT + HTC control */
254 {
255 .pipenum = __cpu_to_le32(1),
256 .pipedir = __cpu_to_le32(PIPEDIR_IN),
257 .nentries = __cpu_to_le32(32),
258 .nbytes_max = __cpu_to_le32(2048),
259 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
260 .reserved = __cpu_to_le32(0),
261 },
262
263 /* CE2: target->host WMI */
264 {
265 .pipenum = __cpu_to_le32(2),
266 .pipedir = __cpu_to_le32(PIPEDIR_IN),
267 .nentries = __cpu_to_le32(64),
268 .nbytes_max = __cpu_to_le32(2048),
269 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
270 .reserved = __cpu_to_le32(0),
271 },
272
273 /* CE3: host->target WMI */
274 {
275 .pipenum = __cpu_to_le32(3),
276 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
277 .nentries = __cpu_to_le32(32),
278 .nbytes_max = __cpu_to_le32(2048),
279 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
280 .reserved = __cpu_to_le32(0),
281 },
282
283 /* CE4: host->target HTT */
284 {
285 .pipenum = __cpu_to_le32(4),
286 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
287 .nentries = __cpu_to_le32(256),
288 .nbytes_max = __cpu_to_le32(256),
289 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
290 .reserved = __cpu_to_le32(0),
291 },
292
293 /* CE5: target->host HTT (HIF->HTT) */
294 {
295 .pipenum = __cpu_to_le32(5),
296 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
297 .nentries = __cpu_to_le32(1024),
298 .nbytes_max = __cpu_to_le32(64),
299 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
300 .reserved = __cpu_to_le32(0),
301 },
302
303 /* CE6: Reserved for target autonomous hif_memcpy */
304 {
305 .pipenum = __cpu_to_le32(6),
306 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
307 .nentries = __cpu_to_le32(32),
308 .nbytes_max = __cpu_to_le32(16384),
309 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
310 .reserved = __cpu_to_le32(0),
311 },
312
313 /* CE7 used only by Host */
314 {
315 .pipenum = __cpu_to_le32(7),
316 .pipedir = __cpu_to_le32(4),
317 .nentries = __cpu_to_le32(0),
318 .nbytes_max = __cpu_to_le32(0),
319 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
320 .reserved = __cpu_to_le32(0),
321 },
322
323 /* CE8 Target to uMC */
324 {
325 .pipenum = __cpu_to_le32(8),
326 .pipedir = __cpu_to_le32(PIPEDIR_IN),
327 .nentries = __cpu_to_le32(32),
328 .nbytes_max = __cpu_to_le32(2048),
329 .flags = __cpu_to_le32(0),
330 .reserved = __cpu_to_le32(0),
331 },
332
333 /* CE9 target->host HTT */
334 {
335 .pipenum = __cpu_to_le32(9),
336 .pipedir = __cpu_to_le32(PIPEDIR_IN),
337 .nentries = __cpu_to_le32(32),
338 .nbytes_max = __cpu_to_le32(2048),
339 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
340 .reserved = __cpu_to_le32(0),
341 },
342
343 /* CE10 target->host HTT */
344 {
345 .pipenum = __cpu_to_le32(10),
346 .pipedir = __cpu_to_le32(PIPEDIR_IN),
347 .nentries = __cpu_to_le32(32),
348 .nbytes_max = __cpu_to_le32(2048),
349 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
350 .reserved = __cpu_to_le32(0),
351 },
352
353 /* CE11 target autonomous qcache memcpy */
354 {
355 .pipenum = __cpu_to_le32(11),
356 .pipedir = __cpu_to_le32(PIPEDIR_IN),
357 .nentries = __cpu_to_le32(32),
358 .nbytes_max = __cpu_to_le32(2048),
359 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
360 .reserved = __cpu_to_le32(0),
361 },
362};
363
364static struct ce_service_to_pipe target_service_to_ce_map_wlan[] = {
365 {
366 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
367 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
368 __cpu_to_le32(3),
369 },
370 {
371 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VO),
372 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
373 __cpu_to_le32(2),
374 },
375 {
376 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
377 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
378 __cpu_to_le32(3),
379 },
380 {
381 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BK),
382 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
383 __cpu_to_le32(2),
384 },
385 {
386 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
387 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
388 __cpu_to_le32(3),
389 },
390 {
391 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_BE),
392 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
393 __cpu_to_le32(2),
394 },
395 {
396 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
397 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
398 __cpu_to_le32(3),
399 },
400 {
401 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_DATA_VI),
402 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
403 __cpu_to_le32(2),
404 },
405 {
406 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
407 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
408 __cpu_to_le32(3),
409 },
410 {
411 __cpu_to_le32(ATH10K_HTC_SVC_ID_WMI_CONTROL),
412 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
413 __cpu_to_le32(2),
414 },
415 {
416 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
417 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
418 __cpu_to_le32(0),
419 },
420 {
421 __cpu_to_le32(ATH10K_HTC_SVC_ID_RSVD_CTRL),
422 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
423 __cpu_to_le32(2),
424 },
425 { /* not used */
426 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
427 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
428 __cpu_to_le32(0),
429 },
430 { /* not used */
431 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
432 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
433 __cpu_to_le32(2),
434 },
435 {
436 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
437 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
438 __cpu_to_le32(4),
439 },
440 {
441 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA_MSG),
442 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
443 __cpu_to_le32(1),
444 },
445 { /* not used */
446 __cpu_to_le32(ATH10K_HTC_SVC_ID_TEST_RAW_STREAMS),
447 __cpu_to_le32(PIPEDIR_OUT),
448 __cpu_to_le32(5),
449 },
450 { /* in = DL = target -> host */
451 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA2_MSG),
452 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
453 __cpu_to_le32(9),
454 },
455 { /* in = DL = target -> host */
456 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_DATA3_MSG),
457 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
458 __cpu_to_le32(10),
459 },
460 { /* in = DL = target -> host pktlog */
461 __cpu_to_le32(ATH10K_HTC_SVC_ID_HTT_LOG_MSG),
462 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
463 __cpu_to_le32(11),
464 },
465 /* (Additions here) */
466
467 { /* must be last */
468 __cpu_to_le32(0),
469 __cpu_to_le32(0),
470 __cpu_to_le32(0),
471 },
472};
473
474static void ath10k_snoc_write32(struct ath10k *ar, u32 offset, u32 value)
475{
476 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
477
478 iowrite32(value, ar_snoc->mem + offset);
479}
480
481static u32 ath10k_snoc_read32(struct ath10k *ar, u32 offset)
482{
483 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
484 u32 val;
485
486 val = ioread32(ar_snoc->mem + offset);
487
488 return val;
489}
490
491static int __ath10k_snoc_rx_post_buf(struct ath10k_snoc_pipe *pipe)
492{
493 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
494 struct ath10k *ar = pipe->hif_ce_state;
495 struct ath10k_ce *ce = ath10k_ce_priv(ar);
496 struct sk_buff *skb;
497 dma_addr_t paddr;
498 int ret;
499
500 skb = dev_alloc_skb(pipe->buf_sz);
501 if (!skb)
502 return -ENOMEM;
503
504 WARN_ONCE((unsigned long)skb->data & 3, "unaligned skb");
505
506 paddr = dma_map_single(ar->dev, skb->data,
507 skb->len + skb_tailroom(skb),
508 DMA_FROM_DEVICE);
509 if (unlikely(dma_mapping_error(ar->dev, paddr))) {
510 ath10k_warn(ar, "failed to dma map snoc rx buf\n");
511 dev_kfree_skb_any(skb);
512 return -EIO;
513 }
514
515 ATH10K_SKB_RXCB(skb)->paddr = paddr;
516
517 spin_lock_bh(&ce->ce_lock);
518 ret = ce_pipe->ops->ce_rx_post_buf(ce_pipe, skb, paddr);
519 spin_unlock_bh(&ce->ce_lock);
520 if (ret) {
521 dma_unmap_single(ar->dev, paddr, skb->len + skb_tailroom(skb),
522 DMA_FROM_DEVICE);
523 dev_kfree_skb_any(skb);
524 return ret;
525 }
526
527 return 0;
528}
529
530static void ath10k_snoc_rx_post_pipe(struct ath10k_snoc_pipe *pipe)
531{
532 struct ath10k *ar = pipe->hif_ce_state;
533 struct ath10k_ce *ce = ath10k_ce_priv(ar);
534 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
535 struct ath10k_ce_pipe *ce_pipe = pipe->ce_hdl;
536 int ret, num;
537
538 if (pipe->buf_sz == 0)
539 return;
540
541 if (!ce_pipe->dest_ring)
542 return;
543
544 spin_lock_bh(&ce->ce_lock);
545 num = __ath10k_ce_rx_num_free_bufs(ce_pipe);
546 spin_unlock_bh(&ce->ce_lock);
547 while (num--) {
548 ret = __ath10k_snoc_rx_post_buf(pipe);
549 if (ret) {
550 if (ret == -ENOSPC)
551 break;
552 ath10k_warn(ar, "failed to post rx buf: %d\n", ret);
553 mod_timer(&ar_snoc->rx_post_retry, jiffies +
554 ATH10K_SNOC_RX_POST_RETRY_MS);
555 break;
556 }
557 }
558}
559
560static void ath10k_snoc_rx_post(struct ath10k *ar)
561{
562 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
563 int i;
564
565 for (i = 0; i < CE_COUNT; i++)
566 ath10k_snoc_rx_post_pipe(&ar_snoc->pipe_info[i]);
567}
568
569static void ath10k_snoc_process_rx_cb(struct ath10k_ce_pipe *ce_state,
570 void (*callback)(struct ath10k *ar,
571 struct sk_buff *skb))
572{
573 struct ath10k *ar = ce_state->ar;
574 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
575 struct ath10k_snoc_pipe *pipe_info = &ar_snoc->pipe_info[ce_state->id];
576 struct sk_buff *skb;
577 struct sk_buff_head list;
578 void *transfer_context;
579 unsigned int nbytes, max_nbytes;
580
581 __skb_queue_head_init(&list);
582 while (ath10k_ce_completed_recv_next(ce_state, &transfer_context,
583 &nbytes) == 0) {
584 skb = transfer_context;
585 max_nbytes = skb->len + skb_tailroom(skb);
586 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
587 max_nbytes, DMA_FROM_DEVICE);
588
589 if (unlikely(max_nbytes < nbytes)) {
590 ath10k_warn(ar, "rxed more than expected (nbytes %d, max %d)\n",
591 nbytes, max_nbytes);
592 dev_kfree_skb_any(skb);
593 continue;
594 }
595
596 skb_put(skb, nbytes);
597 __skb_queue_tail(&list, skb);
598 }
599
600 while ((skb = __skb_dequeue(&list))) {
601 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc rx ce pipe %d len %d\n",
602 ce_state->id, skb->len);
603
604 callback(ar, skb);
605 }
606
607 ath10k_snoc_rx_post_pipe(pipe_info);
608}
609
610static void ath10k_snoc_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
611{
612 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
613}
614
615static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe *ce_state)
616{
617 /* CE4 polling needs to be done whenever CE pipe which transports
618 * HTT Rx (target->host) is processed.
619 */
620 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
621
622 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
623}
624
625/* Called by lower (CE) layer when data is received from the Target.
626 * WCN3990 firmware uses separate CE(CE11) to transfer pktlog data.
627 */
628static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe *ce_state)
629{
630 ath10k_snoc_process_rx_cb(ce_state, ath10k_htc_rx_completion_handler);
631}
632
633static void ath10k_snoc_htt_rx_deliver(struct ath10k *ar, struct sk_buff *skb)
634{
635 skb_pull(skb, sizeof(struct ath10k_htc_hdr));
636 ath10k_htt_t2h_msg_handler(ar, skb);
637}
638
639static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
640{
641 ath10k_ce_per_engine_service(ce_state->ar, CE_POLL_PIPE);
642 ath10k_snoc_process_rx_cb(ce_state, ath10k_snoc_htt_rx_deliver);
643}
644
645static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
646{
647 struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
648 struct ath10k *ar = ar_snoc->ar;
649
650 ath10k_snoc_rx_post(ar);
651}
652
653static void ath10k_snoc_htc_tx_cb(struct ath10k_ce_pipe *ce_state)
654{
655 struct ath10k *ar = ce_state->ar;
656 struct sk_buff_head list;
657 struct sk_buff *skb;
658
659 __skb_queue_head_init(&list);
660 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
661 if (!skb)
662 continue;
663
664 __skb_queue_tail(&list, skb);
665 }
666
667 while ((skb = __skb_dequeue(&list)))
668 ath10k_htc_tx_completion_handler(ar, skb);
669}
670
671static void ath10k_snoc_htt_tx_cb(struct ath10k_ce_pipe *ce_state)
672{
673 struct ath10k *ar = ce_state->ar;
674 struct sk_buff *skb;
675
676 while (ath10k_ce_completed_send_next(ce_state, (void **)&skb) == 0) {
677 if (!skb)
678 continue;
679
680 dma_unmap_single(ar->dev, ATH10K_SKB_CB(skb)->paddr,
681 skb->len, DMA_TO_DEVICE);
682 ath10k_htt_hif_tx_complete(ar, skb);
683 }
684}
685
686static int ath10k_snoc_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
687 struct ath10k_hif_sg_item *items, int n_items)
688{
689 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
690 struct ath10k_ce *ce = ath10k_ce_priv(ar);
691 struct ath10k_snoc_pipe *snoc_pipe;
692 struct ath10k_ce_pipe *ce_pipe;
693 int err, i = 0;
694
695 snoc_pipe = &ar_snoc->pipe_info[pipe_id];
696 ce_pipe = snoc_pipe->ce_hdl;
697 spin_lock_bh(&ce->ce_lock);
698
699 for (i = 0; i < n_items - 1; i++) {
700 ath10k_dbg(ar, ATH10K_DBG_SNOC,
701 "snoc tx item %d paddr %pad len %d n_items %d\n",
702 i, &items[i].paddr, items[i].len, n_items);
703
704 err = ath10k_ce_send_nolock(ce_pipe,
705 items[i].transfer_context,
706 items[i].paddr,
707 items[i].len,
708 items[i].transfer_id,
709 CE_SEND_FLAG_GATHER);
710 if (err)
711 goto err;
712 }
713
714 ath10k_dbg(ar, ATH10K_DBG_SNOC,
715 "snoc tx item %d paddr %pad len %d n_items %d\n",
716 i, &items[i].paddr, items[i].len, n_items);
717
718 err = ath10k_ce_send_nolock(ce_pipe,
719 items[i].transfer_context,
720 items[i].paddr,
721 items[i].len,
722 items[i].transfer_id,
723 0);
724 if (err)
725 goto err;
726
727 spin_unlock_bh(&ce->ce_lock);
728
729 return 0;
730
731err:
732 for (; i > 0; i--)
733 __ath10k_ce_send_revert(ce_pipe);
734
735 spin_unlock_bh(&ce->ce_lock);
736 return err;
737}
738
739static int ath10k_snoc_hif_get_target_info(struct ath10k *ar,
740 struct bmi_target_info *target_info)
741{
742 target_info->version = ATH10K_HW_WCN3990;
743 target_info->type = ATH10K_HW_WCN3990;
744
745 return 0;
746}
747
748static u16 ath10k_snoc_hif_get_free_queue_number(struct ath10k *ar, u8 pipe)
749{
750 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
751
752 ath10k_dbg(ar, ATH10K_DBG_SNOC, "hif get free queue number\n");
753
754 return ath10k_ce_num_free_src_entries(ar_snoc->pipe_info[pipe].ce_hdl);
755}
756
757static void ath10k_snoc_hif_send_complete_check(struct ath10k *ar, u8 pipe,
758 int force)
759{
760 int resources;
761
762 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif send complete check\n");
763
764 if (!force) {
765 resources = ath10k_snoc_hif_get_free_queue_number(ar, pipe);
766
767 if (resources > (host_ce_config_wlan[pipe].src_nentries >> 1))
768 return;
769 }
770 ath10k_ce_per_engine_service(ar, pipe);
771}
772
773static int ath10k_snoc_hif_map_service_to_pipe(struct ath10k *ar,
774 u16 service_id,
775 u8 *ul_pipe, u8 *dl_pipe)
776{
777 const struct ce_service_to_pipe *entry;
778 bool ul_set = false, dl_set = false;
779 int i;
780
781 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif map service\n");
782
783 for (i = 0; i < ARRAY_SIZE(target_service_to_ce_map_wlan); i++) {
784 entry = &target_service_to_ce_map_wlan[i];
785
786 if (__le32_to_cpu(entry->service_id) != service_id)
787 continue;
788
789 switch (__le32_to_cpu(entry->pipedir)) {
790 case PIPEDIR_NONE:
791 break;
792 case PIPEDIR_IN:
793 WARN_ON(dl_set);
794 *dl_pipe = __le32_to_cpu(entry->pipenum);
795 dl_set = true;
796 break;
797 case PIPEDIR_OUT:
798 WARN_ON(ul_set);
799 *ul_pipe = __le32_to_cpu(entry->pipenum);
800 ul_set = true;
801 break;
802 case PIPEDIR_INOUT:
803 WARN_ON(dl_set);
804 WARN_ON(ul_set);
805 *dl_pipe = __le32_to_cpu(entry->pipenum);
806 *ul_pipe = __le32_to_cpu(entry->pipenum);
807 dl_set = true;
808 ul_set = true;
809 break;
810 }
811 }
812
813 if (!ul_set || !dl_set)
814 return -ENOENT;
815
816 return 0;
817}
818
819static void ath10k_snoc_hif_get_default_pipe(struct ath10k *ar,
820 u8 *ul_pipe, u8 *dl_pipe)
821{
822 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc hif get default pipe\n");
823
824 (void)ath10k_snoc_hif_map_service_to_pipe(ar,
825 ATH10K_HTC_SVC_ID_RSVD_CTRL,
826 ul_pipe, dl_pipe);
827}
828
829static inline void ath10k_snoc_irq_disable(struct ath10k *ar)
830{
831 ath10k_ce_disable_interrupts(ar);
832}
833
834static inline void ath10k_snoc_irq_enable(struct ath10k *ar)
835{
836 ath10k_ce_enable_interrupts(ar);
837}
838
839static void ath10k_snoc_rx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
840{
841 struct ath10k_ce_pipe *ce_pipe;
842 struct ath10k_ce_ring *ce_ring;
843 struct sk_buff *skb;
844 struct ath10k *ar;
845 int i;
846
847 ar = snoc_pipe->hif_ce_state;
848 ce_pipe = snoc_pipe->ce_hdl;
849 ce_ring = ce_pipe->dest_ring;
850
851 if (!ce_ring)
852 return;
853
854 if (!snoc_pipe->buf_sz)
855 return;
856
857 for (i = 0; i < ce_ring->nentries; i++) {
858 skb = ce_ring->per_transfer_context[i];
859 if (!skb)
860 continue;
861
862 ce_ring->per_transfer_context[i] = NULL;
863
864 dma_unmap_single(ar->dev, ATH10K_SKB_RXCB(skb)->paddr,
865 skb->len + skb_tailroom(skb),
866 DMA_FROM_DEVICE);
867 dev_kfree_skb_any(skb);
868 }
869}
870
871static void ath10k_snoc_tx_pipe_cleanup(struct ath10k_snoc_pipe *snoc_pipe)
872{
873 struct ath10k_ce_pipe *ce_pipe;
874 struct ath10k_ce_ring *ce_ring;
875 struct sk_buff *skb;
876 struct ath10k *ar;
877 int i;
878
879 ar = snoc_pipe->hif_ce_state;
880 ce_pipe = snoc_pipe->ce_hdl;
881 ce_ring = ce_pipe->src_ring;
882
883 if (!ce_ring)
884 return;
885
886 if (!snoc_pipe->buf_sz)
887 return;
888
889 for (i = 0; i < ce_ring->nentries; i++) {
890 skb = ce_ring->per_transfer_context[i];
891 if (!skb)
892 continue;
893
894 ce_ring->per_transfer_context[i] = NULL;
895
896 ath10k_htc_tx_completion_handler(ar, skb);
897 }
898}
899
900static void ath10k_snoc_buffer_cleanup(struct ath10k *ar)
901{
902 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
903 struct ath10k_snoc_pipe *pipe_info;
904 int pipe_num;
905
906 del_timer_sync(&ar_snoc->rx_post_retry);
907 for (pipe_num = 0; pipe_num < CE_COUNT; pipe_num++) {
908 pipe_info = &ar_snoc->pipe_info[pipe_num];
909 ath10k_snoc_rx_pipe_cleanup(pipe_info);
910 ath10k_snoc_tx_pipe_cleanup(pipe_info);
911 }
912}
913
914static void ath10k_snoc_hif_stop(struct ath10k *ar)
915{
916 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags))
917 ath10k_snoc_irq_disable(ar);
918
919 ath10k_core_napi_sync_disable(ar);
920 ath10k_snoc_buffer_cleanup(ar);
921 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif stop\n");
922}
923
924static int ath10k_snoc_hif_start(struct ath10k *ar)
925{
926 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
927
928 bitmap_clear(ar_snoc->pending_ce_irqs, 0, CE_COUNT_MAX);
929
930 ath10k_core_napi_enable(ar);
931 ath10k_snoc_irq_enable(ar);
932 ath10k_snoc_rx_post(ar);
933
934 clear_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
935
936 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif start\n");
937
938 return 0;
939}
940
941static int ath10k_snoc_init_pipes(struct ath10k *ar)
942{
943 int i, ret;
944
945 for (i = 0; i < CE_COUNT; i++) {
946 ret = ath10k_ce_init_pipe(ar, i, &host_ce_config_wlan[i]);
947 if (ret) {
948 ath10k_err(ar, "failed to initialize copy engine pipe %d: %d\n",
949 i, ret);
950 return ret;
951 }
952 }
953
954 return 0;
955}
956
957static int ath10k_snoc_wlan_enable(struct ath10k *ar,
958 enum ath10k_firmware_mode fw_mode)
959{
960 struct ath10k_tgt_pipe_cfg tgt_cfg[CE_COUNT_MAX];
961 struct ath10k_qmi_wlan_enable_cfg cfg;
962 enum wlfw_driver_mode_enum_v01 mode;
963 int pipe_num;
964
965 for (pipe_num = 0; pipe_num < CE_COUNT_MAX; pipe_num++) {
966 tgt_cfg[pipe_num].pipe_num =
967 target_ce_config_wlan[pipe_num].pipenum;
968 tgt_cfg[pipe_num].pipe_dir =
969 target_ce_config_wlan[pipe_num].pipedir;
970 tgt_cfg[pipe_num].nentries =
971 target_ce_config_wlan[pipe_num].nentries;
972 tgt_cfg[pipe_num].nbytes_max =
973 target_ce_config_wlan[pipe_num].nbytes_max;
974 tgt_cfg[pipe_num].flags =
975 target_ce_config_wlan[pipe_num].flags;
976 tgt_cfg[pipe_num].reserved = 0;
977 }
978
979 cfg.num_ce_tgt_cfg = sizeof(target_ce_config_wlan) /
980 sizeof(struct ath10k_tgt_pipe_cfg);
981 cfg.ce_tgt_cfg = (struct ath10k_tgt_pipe_cfg *)
982 &tgt_cfg;
983 cfg.num_ce_svc_pipe_cfg = sizeof(target_service_to_ce_map_wlan) /
984 sizeof(struct ath10k_svc_pipe_cfg);
985 cfg.ce_svc_cfg = (struct ath10k_svc_pipe_cfg *)
986 &target_service_to_ce_map_wlan;
987 cfg.num_shadow_reg_cfg = ARRAY_SIZE(target_shadow_reg_cfg_map);
988 cfg.shadow_reg_cfg = (struct ath10k_shadow_reg_cfg *)
989 &target_shadow_reg_cfg_map;
990
991 switch (fw_mode) {
992 case ATH10K_FIRMWARE_MODE_NORMAL:
993 mode = QMI_WLFW_MISSION_V01;
994 break;
995 case ATH10K_FIRMWARE_MODE_UTF:
996 mode = QMI_WLFW_FTM_V01;
997 break;
998 default:
999 ath10k_err(ar, "invalid firmware mode %d\n", fw_mode);
1000 return -EINVAL;
1001 }
1002
1003 return ath10k_qmi_wlan_enable(ar, &cfg, mode,
1004 NULL);
1005}
1006
1007static int ath10k_hw_power_on(struct ath10k *ar)
1008{
1009 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1010 int ret;
1011
1012 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power on\n");
1013
1014 ret = regulator_bulk_enable(ar_snoc->num_vregs, ar_snoc->vregs);
1015 if (ret)
1016 return ret;
1017
1018 ret = clk_bulk_prepare_enable(ar_snoc->num_clks, ar_snoc->clks);
1019 if (ret)
1020 goto vreg_off;
1021
1022 return ret;
1023
1024vreg_off:
1025 regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1026 return ret;
1027}
1028
1029static int ath10k_hw_power_off(struct ath10k *ar)
1030{
1031 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1032
1033 ath10k_dbg(ar, ATH10K_DBG_SNOC, "soc power off\n");
1034
1035 clk_bulk_disable_unprepare(ar_snoc->num_clks, ar_snoc->clks);
1036
1037 return regulator_bulk_disable(ar_snoc->num_vregs, ar_snoc->vregs);
1038}
1039
1040static void ath10k_snoc_wlan_disable(struct ath10k *ar)
1041{
1042 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1043
1044 /* If both ATH10K_FLAG_CRASH_FLUSH and ATH10K_SNOC_FLAG_RECOVERY
1045 * flags are not set, it means that the driver has restarted
1046 * due to a crash inject via debugfs. In this case, the driver
1047 * needs to restart the firmware and hence send qmi wlan disable,
1048 * during the driver restart sequence.
1049 */
1050 if (!test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags) ||
1051 !test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1052 ath10k_qmi_wlan_disable(ar);
1053}
1054
1055static void ath10k_snoc_hif_power_down(struct ath10k *ar)
1056{
1057 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot hif power down\n");
1058
1059 ath10k_snoc_wlan_disable(ar);
1060 ath10k_ce_free_rri(ar);
1061 ath10k_hw_power_off(ar);
1062}
1063
1064static int ath10k_snoc_hif_power_up(struct ath10k *ar,
1065 enum ath10k_firmware_mode fw_mode)
1066{
1067 int ret;
1068
1069 ath10k_dbg(ar, ATH10K_DBG_SNOC, "%s:WCN3990 driver state = %d\n",
1070 __func__, ar->state);
1071
1072 ret = ath10k_hw_power_on(ar);
1073 if (ret) {
1074 ath10k_err(ar, "failed to power on device: %d\n", ret);
1075 return ret;
1076 }
1077
1078 ret = ath10k_snoc_wlan_enable(ar, fw_mode);
1079 if (ret) {
1080 ath10k_err(ar, "failed to enable wcn3990: %d\n", ret);
1081 goto err_hw_power_off;
1082 }
1083
1084 ath10k_ce_alloc_rri(ar);
1085
1086 ret = ath10k_snoc_init_pipes(ar);
1087 if (ret) {
1088 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
1089 goto err_free_rri;
1090 }
1091
1092 return 0;
1093
1094err_free_rri:
1095 ath10k_ce_free_rri(ar);
1096 ath10k_snoc_wlan_disable(ar);
1097
1098err_hw_power_off:
1099 ath10k_hw_power_off(ar);
1100
1101 return ret;
1102}
1103
1104static int ath10k_snoc_hif_set_target_log_mode(struct ath10k *ar,
1105 u8 fw_log_mode)
1106{
1107 u8 fw_dbg_mode;
1108
1109 if (fw_log_mode)
1110 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_CE;
1111 else
1112 fw_dbg_mode = ATH10K_ENABLE_FW_LOG_DIAG;
1113
1114 return ath10k_qmi_set_fw_log_mode(ar, fw_dbg_mode);
1115}
1116
1117#ifdef CONFIG_PM
1118static int ath10k_snoc_hif_suspend(struct ath10k *ar)
1119{
1120 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1121 int ret;
1122
1123 if (!device_may_wakeup(ar->dev))
1124 return -EPERM;
1125
1126 ret = enable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1127 if (ret) {
1128 ath10k_err(ar, "failed to enable wakeup irq :%d\n", ret);
1129 return ret;
1130 }
1131
1132 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device suspended\n");
1133
1134 return ret;
1135}
1136
1137static int ath10k_snoc_hif_resume(struct ath10k *ar)
1138{
1139 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1140 int ret;
1141
1142 if (!device_may_wakeup(ar->dev))
1143 return -EPERM;
1144
1145 ret = disable_irq_wake(ar_snoc->ce_irqs[ATH10K_SNOC_WAKE_IRQ].irq_line);
1146 if (ret) {
1147 ath10k_err(ar, "failed to disable wakeup irq: %d\n", ret);
1148 return ret;
1149 }
1150
1151 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc device resumed\n");
1152
1153 return ret;
1154}
1155#endif
1156
1157static const struct ath10k_hif_ops ath10k_snoc_hif_ops = {
1158 .read32 = ath10k_snoc_read32,
1159 .write32 = ath10k_snoc_write32,
1160 .start = ath10k_snoc_hif_start,
1161 .stop = ath10k_snoc_hif_stop,
1162 .map_service_to_pipe = ath10k_snoc_hif_map_service_to_pipe,
1163 .get_default_pipe = ath10k_snoc_hif_get_default_pipe,
1164 .power_up = ath10k_snoc_hif_power_up,
1165 .power_down = ath10k_snoc_hif_power_down,
1166 .tx_sg = ath10k_snoc_hif_tx_sg,
1167 .send_complete_check = ath10k_snoc_hif_send_complete_check,
1168 .get_free_queue_number = ath10k_snoc_hif_get_free_queue_number,
1169 .get_target_info = ath10k_snoc_hif_get_target_info,
1170 .set_target_log_mode = ath10k_snoc_hif_set_target_log_mode,
1171
1172#ifdef CONFIG_PM
1173 .suspend = ath10k_snoc_hif_suspend,
1174 .resume = ath10k_snoc_hif_resume,
1175#endif
1176};
1177
1178static const struct ath10k_bus_ops ath10k_snoc_bus_ops = {
1179 .read32 = ath10k_snoc_read32,
1180 .write32 = ath10k_snoc_write32,
1181};
1182
1183static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
1184{
1185 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1186 int i;
1187
1188 for (i = 0; i < CE_COUNT_MAX; i++) {
1189 if (ar_snoc->ce_irqs[i].irq_line == irq)
1190 return i;
1191 }
1192 ath10k_err(ar, "No matching CE id for irq %d\n", irq);
1193
1194 return -EINVAL;
1195}
1196
1197static irqreturn_t ath10k_snoc_per_engine_handler(int irq, void *arg)
1198{
1199 struct ath10k *ar = arg;
1200 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1201 int ce_id = ath10k_snoc_get_ce_id_from_irq(ar, irq);
1202
1203 if (ce_id < 0 || ce_id >= ARRAY_SIZE(ar_snoc->pipe_info)) {
1204 ath10k_warn(ar, "unexpected/invalid irq %d ce_id %d\n", irq,
1205 ce_id);
1206 return IRQ_HANDLED;
1207 }
1208
1209 ath10k_ce_disable_interrupt(ar, ce_id);
1210 set_bit(ce_id, ar_snoc->pending_ce_irqs);
1211
1212 napi_schedule(&ar->napi);
1213
1214 return IRQ_HANDLED;
1215}
1216
1217static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget)
1218{
1219 struct ath10k *ar = container_of(ctx, struct ath10k, napi);
1220 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1221 int done = 0;
1222 int ce_id;
1223
1224 if (test_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags)) {
1225 napi_complete(ctx);
1226 return done;
1227 }
1228
1229 for (ce_id = 0; ce_id < CE_COUNT; ce_id++)
1230 if (test_and_clear_bit(ce_id, ar_snoc->pending_ce_irqs)) {
1231 ath10k_ce_per_engine_service(ar, ce_id);
1232 ath10k_ce_enable_interrupt(ar, ce_id);
1233 }
1234
1235 done = ath10k_htt_txrx_compl_task(ar, budget);
1236
1237 if (done < budget)
1238 napi_complete(ctx);
1239
1240 return done;
1241}
1242
1243static void ath10k_snoc_init_napi(struct ath10k *ar)
1244{
1245 netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll);
1246}
1247
1248static int ath10k_snoc_request_irq(struct ath10k *ar)
1249{
1250 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1251 int ret, id;
1252
1253 for (id = 0; id < CE_COUNT_MAX; id++) {
1254 ret = request_irq(ar_snoc->ce_irqs[id].irq_line,
1255 ath10k_snoc_per_engine_handler, 0,
1256 ce_name[id], ar);
1257 if (ret) {
1258 ath10k_err(ar,
1259 "failed to register IRQ handler for CE %d: %d\n",
1260 id, ret);
1261 goto err_irq;
1262 }
1263 }
1264
1265 return 0;
1266
1267err_irq:
1268 for (id -= 1; id >= 0; id--)
1269 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1270
1271 return ret;
1272}
1273
1274static void ath10k_snoc_free_irq(struct ath10k *ar)
1275{
1276 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1277 int id;
1278
1279 for (id = 0; id < CE_COUNT_MAX; id++)
1280 free_irq(ar_snoc->ce_irqs[id].irq_line, ar);
1281}
1282
1283static int ath10k_snoc_resource_init(struct ath10k *ar)
1284{
1285 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1286 struct platform_device *pdev;
1287 struct resource *res;
1288 int i, ret = 0;
1289
1290 pdev = ar_snoc->dev;
1291 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "membase");
1292 if (!res) {
1293 ath10k_err(ar, "Memory base not found in DT\n");
1294 return -EINVAL;
1295 }
1296
1297 ar_snoc->mem_pa = res->start;
1298 ar_snoc->mem = devm_ioremap(&pdev->dev, ar_snoc->mem_pa,
1299 resource_size(res));
1300 if (!ar_snoc->mem) {
1301 ath10k_err(ar, "Memory base ioremap failed with physical address %pa\n",
1302 &ar_snoc->mem_pa);
1303 return -EINVAL;
1304 }
1305
1306 for (i = 0; i < CE_COUNT; i++) {
1307 ret = platform_get_irq(ar_snoc->dev, i);
1308 if (ret < 0)
1309 return ret;
1310 ar_snoc->ce_irqs[i].irq_line = ret;
1311 }
1312
1313 ret = device_property_read_u32(&pdev->dev, "qcom,xo-cal-data",
1314 &ar_snoc->xo_cal_data);
1315 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc xo-cal-data return %d\n", ret);
1316 if (ret == 0) {
1317 ar_snoc->xo_cal_supported = true;
1318 ath10k_dbg(ar, ATH10K_DBG_SNOC, "xo cal data %x\n",
1319 ar_snoc->xo_cal_data);
1320 }
1321
1322 return 0;
1323}
1324
1325static void ath10k_snoc_quirks_init(struct ath10k *ar)
1326{
1327 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1328 struct device *dev = &ar_snoc->dev->dev;
1329
1330 if (of_property_read_bool(dev->of_node, "qcom,snoc-host-cap-8bit-quirk"))
1331 set_bit(ATH10K_SNOC_FLAG_8BIT_HOST_CAP_QUIRK, &ar_snoc->flags);
1332}
1333
1334int ath10k_snoc_fw_indication(struct ath10k *ar, u64 type)
1335{
1336 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1337 struct ath10k_bus_params bus_params = {};
1338 int ret;
1339
1340 if (test_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags))
1341 return 0;
1342
1343 switch (type) {
1344 case ATH10K_QMI_EVENT_FW_READY_IND:
1345 if (test_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags)) {
1346 ath10k_core_start_recovery(ar);
1347 break;
1348 }
1349
1350 bus_params.dev_type = ATH10K_DEV_TYPE_LL;
1351 bus_params.chip_id = ar_snoc->target_info.soc_version;
1352 ret = ath10k_core_register(ar, &bus_params);
1353 if (ret) {
1354 ath10k_err(ar, "Failed to register driver core: %d\n",
1355 ret);
1356 return ret;
1357 }
1358 set_bit(ATH10K_SNOC_FLAG_REGISTERED, &ar_snoc->flags);
1359 break;
1360 case ATH10K_QMI_EVENT_FW_DOWN_IND:
1361 set_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags);
1362 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1363 break;
1364 default:
1365 ath10k_err(ar, "invalid fw indication: %llx\n", type);
1366 return -EINVAL;
1367 }
1368
1369 return 0;
1370}
1371
1372static int ath10k_snoc_setup_resource(struct ath10k *ar)
1373{
1374 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1375 struct ath10k_ce *ce = ath10k_ce_priv(ar);
1376 struct ath10k_snoc_pipe *pipe;
1377 int i, ret;
1378
1379 timer_setup(&ar_snoc->rx_post_retry, ath10k_snoc_rx_replenish_retry, 0);
1380 spin_lock_init(&ce->ce_lock);
1381 for (i = 0; i < CE_COUNT; i++) {
1382 pipe = &ar_snoc->pipe_info[i];
1383 pipe->ce_hdl = &ce->ce_states[i];
1384 pipe->pipe_num = i;
1385 pipe->hif_ce_state = ar;
1386
1387 ret = ath10k_ce_alloc_pipe(ar, i, &host_ce_config_wlan[i]);
1388 if (ret) {
1389 ath10k_err(ar, "failed to allocate copy engine pipe %d: %d\n",
1390 i, ret);
1391 return ret;
1392 }
1393
1394 pipe->buf_sz = host_ce_config_wlan[i].src_sz_max;
1395 }
1396 ath10k_snoc_init_napi(ar);
1397
1398 return 0;
1399}
1400
1401static void ath10k_snoc_release_resource(struct ath10k *ar)
1402{
1403 int i;
1404
1405 netif_napi_del(&ar->napi);
1406 for (i = 0; i < CE_COUNT; i++)
1407 ath10k_ce_free_pipe(ar, i);
1408}
1409
1410static void ath10k_msa_dump_memory(struct ath10k *ar,
1411 struct ath10k_fw_crash_data *crash_data)
1412{
1413 const struct ath10k_hw_mem_layout *mem_layout;
1414 const struct ath10k_mem_region *current_region;
1415 struct ath10k_dump_ram_data_hdr *hdr;
1416 size_t buf_len;
1417 u8 *buf;
1418
1419 if (!crash_data || !crash_data->ramdump_buf)
1420 return;
1421
1422 mem_layout = ath10k_coredump_get_mem_layout(ar);
1423 if (!mem_layout)
1424 return;
1425
1426 current_region = &mem_layout->region_table.regions[0];
1427
1428 buf = crash_data->ramdump_buf;
1429 buf_len = crash_data->ramdump_buf_len;
1430 memset(buf, 0, buf_len);
1431
1432 /* Reserve space for the header. */
1433 hdr = (void *)buf;
1434 buf += sizeof(*hdr);
1435 buf_len -= sizeof(*hdr);
1436
1437 hdr->region_type = cpu_to_le32(current_region->type);
1438 hdr->start = cpu_to_le32((unsigned long)ar->msa.vaddr);
1439 hdr->length = cpu_to_le32(ar->msa.mem_size);
1440
1441 if (current_region->len < ar->msa.mem_size) {
1442 memcpy(buf, ar->msa.vaddr, current_region->len);
1443 ath10k_warn(ar, "msa dump length is less than msa size %x, %x\n",
1444 current_region->len, ar->msa.mem_size);
1445 } else {
1446 memcpy(buf, ar->msa.vaddr, ar->msa.mem_size);
1447 }
1448}
1449
1450void ath10k_snoc_fw_crashed_dump(struct ath10k *ar)
1451{
1452 struct ath10k_fw_crash_data *crash_data;
1453 char guid[UUID_STRING_LEN + 1];
1454
1455 mutex_lock(&ar->dump_mutex);
1456
1457 spin_lock_bh(&ar->data_lock);
1458 ar->stats.fw_crash_counter++;
1459 spin_unlock_bh(&ar->data_lock);
1460
1461 crash_data = ath10k_coredump_new(ar);
1462
1463 if (crash_data)
1464 scnprintf(guid, sizeof(guid), "%pUl", &crash_data->guid);
1465 else
1466 scnprintf(guid, sizeof(guid), "n/a");
1467
1468 ath10k_err(ar, "firmware crashed! (guid %s)\n", guid);
1469 ath10k_print_driver_info(ar);
1470 ath10k_msa_dump_memory(ar, crash_data);
1471 mutex_unlock(&ar->dump_mutex);
1472}
1473
1474static int ath10k_snoc_modem_notify(struct notifier_block *nb, unsigned long action,
1475 void *data)
1476{
1477 struct ath10k_snoc *ar_snoc = container_of(nb, struct ath10k_snoc, nb);
1478 struct ath10k *ar = ar_snoc->ar;
1479 struct qcom_ssr_notify_data *notify_data = data;
1480
1481 switch (action) {
1482 case QCOM_SSR_BEFORE_POWERUP:
1483 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem starting event\n");
1484 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1485 break;
1486
1487 case QCOM_SSR_AFTER_POWERUP:
1488 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem running event\n");
1489 break;
1490
1491 case QCOM_SSR_BEFORE_SHUTDOWN:
1492 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem %s event\n",
1493 notify_data->crashed ? "crashed" : "stopping");
1494 if (!notify_data->crashed)
1495 set_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1496 else
1497 clear_bit(ATH10K_SNOC_FLAG_MODEM_STOPPED, &ar_snoc->flags);
1498 break;
1499
1500 case QCOM_SSR_AFTER_SHUTDOWN:
1501 ath10k_dbg(ar, ATH10K_DBG_SNOC, "received modem offline event\n");
1502 break;
1503
1504 default:
1505 ath10k_err(ar, "received unrecognized event %lu\n", action);
1506 break;
1507 }
1508
1509 return NOTIFY_OK;
1510}
1511
1512static int ath10k_modem_init(struct ath10k *ar)
1513{
1514 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1515 void *notifier;
1516 int ret;
1517
1518 ar_snoc->nb.notifier_call = ath10k_snoc_modem_notify;
1519
1520 notifier = qcom_register_ssr_notifier("mpss", &ar_snoc->nb);
1521 if (IS_ERR(notifier)) {
1522 ret = PTR_ERR(notifier);
1523 ath10k_err(ar, "failed to initialize modem notifier: %d\n", ret);
1524 return ret;
1525 }
1526
1527 ar_snoc->notifier = notifier;
1528
1529 return 0;
1530}
1531
1532static void ath10k_modem_deinit(struct ath10k *ar)
1533{
1534 int ret;
1535 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1536
1537 ret = qcom_unregister_ssr_notifier(ar_snoc->notifier, &ar_snoc->nb);
1538 if (ret)
1539 ath10k_err(ar, "error %d unregistering notifier\n", ret);
1540}
1541
1542static int ath10k_setup_msa_resources(struct ath10k *ar, u32 msa_size)
1543{
1544 struct device *dev = ar->dev;
1545 struct device_node *node;
1546 struct resource r;
1547 int ret;
1548
1549 node = of_parse_phandle(dev->of_node, "memory-region", 0);
1550 if (node) {
1551 ret = of_address_to_resource(node, 0, &r);
1552 of_node_put(node);
1553 if (ret) {
1554 dev_err(dev, "failed to resolve msa fixed region\n");
1555 return ret;
1556 }
1557
1558 ar->msa.paddr = r.start;
1559 ar->msa.mem_size = resource_size(&r);
1560 ar->msa.vaddr = devm_memremap(dev, ar->msa.paddr,
1561 ar->msa.mem_size,
1562 MEMREMAP_WT);
1563 if (IS_ERR(ar->msa.vaddr)) {
1564 dev_err(dev, "failed to map memory region: %pa\n",
1565 &r.start);
1566 return PTR_ERR(ar->msa.vaddr);
1567 }
1568 } else {
1569 ar->msa.vaddr = dmam_alloc_coherent(dev, msa_size,
1570 &ar->msa.paddr,
1571 GFP_KERNEL);
1572 if (!ar->msa.vaddr) {
1573 ath10k_err(ar, "failed to allocate dma memory for msa region\n");
1574 return -ENOMEM;
1575 }
1576 ar->msa.mem_size = msa_size;
1577 }
1578
1579 ath10k_dbg(ar, ATH10K_DBG_QMI, "qmi msa.paddr: %pad , msa.vaddr: 0x%p\n",
1580 &ar->msa.paddr,
1581 ar->msa.vaddr);
1582
1583 return 0;
1584}
1585
1586static int ath10k_fw_init(struct ath10k *ar)
1587{
1588 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1589 struct device *host_dev = &ar_snoc->dev->dev;
1590 struct platform_device_info info;
1591 struct iommu_domain *iommu_dom;
1592 struct platform_device *pdev;
1593 struct device_node *node;
1594 int ret;
1595
1596 node = of_get_child_by_name(host_dev->of_node, "wifi-firmware");
1597 if (!node) {
1598 ar_snoc->use_tz = true;
1599 return 0;
1600 }
1601
1602 memset(&info, 0, sizeof(info));
1603 info.fwnode = &node->fwnode;
1604 info.parent = host_dev;
1605 info.name = node->name;
1606 info.dma_mask = DMA_BIT_MASK(32);
1607
1608 pdev = platform_device_register_full(&info);
1609 if (IS_ERR(pdev)) {
1610 of_node_put(node);
1611 return PTR_ERR(pdev);
1612 }
1613
1614 pdev->dev.of_node = node;
1615
1616 ret = of_dma_configure(&pdev->dev, node, true);
1617 if (ret) {
1618 ath10k_err(ar, "dma configure fail: %d\n", ret);
1619 goto err_unregister;
1620 }
1621
1622 ar_snoc->fw.dev = &pdev->dev;
1623
1624 iommu_dom = iommu_domain_alloc(&platform_bus_type);
1625 if (!iommu_dom) {
1626 ath10k_err(ar, "failed to allocate iommu domain\n");
1627 ret = -ENOMEM;
1628 goto err_unregister;
1629 }
1630
1631 ret = iommu_attach_device(iommu_dom, ar_snoc->fw.dev);
1632 if (ret) {
1633 ath10k_err(ar, "could not attach device: %d\n", ret);
1634 goto err_iommu_free;
1635 }
1636
1637 ar_snoc->fw.iommu_domain = iommu_dom;
1638 ar_snoc->fw.fw_start_addr = ar->msa.paddr;
1639
1640 ret = iommu_map(iommu_dom, ar_snoc->fw.fw_start_addr,
1641 ar->msa.paddr, ar->msa.mem_size,
1642 IOMMU_READ | IOMMU_WRITE);
1643 if (ret) {
1644 ath10k_err(ar, "failed to map firmware region: %d\n", ret);
1645 goto err_iommu_detach;
1646 }
1647
1648 of_node_put(node);
1649
1650 return 0;
1651
1652err_iommu_detach:
1653 iommu_detach_device(iommu_dom, ar_snoc->fw.dev);
1654
1655err_iommu_free:
1656 iommu_domain_free(iommu_dom);
1657
1658err_unregister:
1659 platform_device_unregister(pdev);
1660 of_node_put(node);
1661
1662 return ret;
1663}
1664
1665static int ath10k_fw_deinit(struct ath10k *ar)
1666{
1667 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1668 const size_t mapped_size = ar_snoc->fw.mapped_mem_size;
1669 struct iommu_domain *iommu;
1670 size_t unmapped_size;
1671
1672 if (ar_snoc->use_tz)
1673 return 0;
1674
1675 iommu = ar_snoc->fw.iommu_domain;
1676
1677 unmapped_size = iommu_unmap(iommu, ar_snoc->fw.fw_start_addr,
1678 mapped_size);
1679 if (unmapped_size != mapped_size)
1680 ath10k_err(ar, "failed to unmap firmware: %zu\n",
1681 unmapped_size);
1682
1683 iommu_detach_device(iommu, ar_snoc->fw.dev);
1684 iommu_domain_free(iommu);
1685
1686 platform_device_unregister(to_platform_device(ar_snoc->fw.dev));
1687
1688 return 0;
1689}
1690
1691static const struct of_device_id ath10k_snoc_dt_match[] = {
1692 { .compatible = "qcom,wcn3990-wifi",
1693 .data = &drv_priv,
1694 },
1695 { }
1696};
1697MODULE_DEVICE_TABLE(of, ath10k_snoc_dt_match);
1698
1699static int ath10k_snoc_probe(struct platform_device *pdev)
1700{
1701 const struct ath10k_snoc_drv_priv *drv_data;
1702 struct ath10k_snoc *ar_snoc;
1703 struct device *dev;
1704 struct ath10k *ar;
1705 u32 msa_size;
1706 int ret;
1707 u32 i;
1708
1709 dev = &pdev->dev;
1710 drv_data = device_get_match_data(dev);
1711 if (!drv_data) {
1712 dev_err(dev, "failed to find matching device tree id\n");
1713 return -EINVAL;
1714 }
1715
1716 ret = dma_set_mask_and_coherent(dev, drv_data->dma_mask);
1717 if (ret) {
1718 dev_err(dev, "failed to set dma mask: %d\n", ret);
1719 return ret;
1720 }
1721
1722 ar = ath10k_core_create(sizeof(*ar_snoc), dev, ATH10K_BUS_SNOC,
1723 drv_data->hw_rev, &ath10k_snoc_hif_ops);
1724 if (!ar) {
1725 dev_err(dev, "failed to allocate core\n");
1726 return -ENOMEM;
1727 }
1728
1729 ar_snoc = ath10k_snoc_priv(ar);
1730 ar_snoc->dev = pdev;
1731 platform_set_drvdata(pdev, ar);
1732 ar_snoc->ar = ar;
1733 ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
1734 ar->ce_priv = &ar_snoc->ce;
1735 msa_size = drv_data->msa_size;
1736
1737 ath10k_snoc_quirks_init(ar);
1738
1739 ret = ath10k_snoc_resource_init(ar);
1740 if (ret) {
1741 ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
1742 goto err_core_destroy;
1743 }
1744
1745 ret = ath10k_snoc_setup_resource(ar);
1746 if (ret) {
1747 ath10k_warn(ar, "failed to setup resource: %d\n", ret);
1748 goto err_core_destroy;
1749 }
1750 ret = ath10k_snoc_request_irq(ar);
1751 if (ret) {
1752 ath10k_warn(ar, "failed to request irqs: %d\n", ret);
1753 goto err_release_resource;
1754 }
1755
1756 ar_snoc->num_vregs = ARRAY_SIZE(ath10k_regulators);
1757 ar_snoc->vregs = devm_kcalloc(&pdev->dev, ar_snoc->num_vregs,
1758 sizeof(*ar_snoc->vregs), GFP_KERNEL);
1759 if (!ar_snoc->vregs) {
1760 ret = -ENOMEM;
1761 goto err_free_irq;
1762 }
1763 for (i = 0; i < ar_snoc->num_vregs; i++)
1764 ar_snoc->vregs[i].supply = ath10k_regulators[i];
1765
1766 ret = devm_regulator_bulk_get(&pdev->dev, ar_snoc->num_vregs,
1767 ar_snoc->vregs);
1768 if (ret < 0)
1769 goto err_free_irq;
1770
1771 ar_snoc->num_clks = ARRAY_SIZE(ath10k_clocks);
1772 ar_snoc->clks = devm_kcalloc(&pdev->dev, ar_snoc->num_clks,
1773 sizeof(*ar_snoc->clks), GFP_KERNEL);
1774 if (!ar_snoc->clks) {
1775 ret = -ENOMEM;
1776 goto err_free_irq;
1777 }
1778
1779 for (i = 0; i < ar_snoc->num_clks; i++)
1780 ar_snoc->clks[i].id = ath10k_clocks[i];
1781
1782 ret = devm_clk_bulk_get_optional(&pdev->dev, ar_snoc->num_clks,
1783 ar_snoc->clks);
1784 if (ret)
1785 goto err_free_irq;
1786
1787 ret = ath10k_setup_msa_resources(ar, msa_size);
1788 if (ret) {
1789 ath10k_warn(ar, "failed to setup msa resources: %d\n", ret);
1790 goto err_free_irq;
1791 }
1792
1793 ret = ath10k_fw_init(ar);
1794 if (ret) {
1795 ath10k_err(ar, "failed to initialize firmware: %d\n", ret);
1796 goto err_free_irq;
1797 }
1798
1799 ret = ath10k_qmi_init(ar, msa_size);
1800 if (ret) {
1801 ath10k_warn(ar, "failed to register wlfw qmi client: %d\n", ret);
1802 goto err_fw_deinit;
1803 }
1804
1805 ret = ath10k_modem_init(ar);
1806 if (ret)
1807 goto err_qmi_deinit;
1808
1809 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc probe\n");
1810
1811 return 0;
1812
1813err_qmi_deinit:
1814 ath10k_qmi_deinit(ar);
1815
1816err_fw_deinit:
1817 ath10k_fw_deinit(ar);
1818
1819err_free_irq:
1820 ath10k_snoc_free_irq(ar);
1821
1822err_release_resource:
1823 ath10k_snoc_release_resource(ar);
1824
1825err_core_destroy:
1826 ath10k_core_destroy(ar);
1827
1828 return ret;
1829}
1830
1831static int ath10k_snoc_free_resources(struct ath10k *ar)
1832{
1833 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1834
1835 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc free resources\n");
1836
1837 set_bit(ATH10K_SNOC_FLAG_UNREGISTERING, &ar_snoc->flags);
1838
1839 ath10k_core_unregister(ar);
1840 ath10k_fw_deinit(ar);
1841 ath10k_snoc_free_irq(ar);
1842 ath10k_snoc_release_resource(ar);
1843 ath10k_modem_deinit(ar);
1844 ath10k_qmi_deinit(ar);
1845 ath10k_core_destroy(ar);
1846
1847 return 0;
1848}
1849
1850static int ath10k_snoc_remove(struct platform_device *pdev)
1851{
1852 struct ath10k *ar = platform_get_drvdata(pdev);
1853 struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
1854
1855 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc remove\n");
1856
1857 reinit_completion(&ar->driver_recovery);
1858
1859 if (test_bit(ATH10K_SNOC_FLAG_RECOVERY, &ar_snoc->flags))
1860 wait_for_completion_timeout(&ar->driver_recovery, 3 * HZ);
1861
1862 ath10k_snoc_free_resources(ar);
1863
1864 return 0;
1865}
1866
1867static void ath10k_snoc_shutdown(struct platform_device *pdev)
1868{
1869 struct ath10k *ar = platform_get_drvdata(pdev);
1870
1871 ath10k_dbg(ar, ATH10K_DBG_SNOC, "snoc shutdown\n");
1872 ath10k_snoc_free_resources(ar);
1873}
1874
1875static struct platform_driver ath10k_snoc_driver = {
1876 .probe = ath10k_snoc_probe,
1877 .remove = ath10k_snoc_remove,
1878 .shutdown = ath10k_snoc_shutdown,
1879 .driver = {
1880 .name = "ath10k_snoc",
1881 .of_match_table = ath10k_snoc_dt_match,
1882 },
1883};
1884module_platform_driver(ath10k_snoc_driver);
1885
1886MODULE_AUTHOR("Qualcomm");
1887MODULE_LICENSE("Dual BSD/GPL");
1888MODULE_DESCRIPTION("Driver support for Atheros WCN3990 SNOC devices");