Loading...
Note: File does not exist in v3.1.
1// SPDX-License-Identifier: GPL-2.0
2/* NXP TJA1100 BroadRReach PHY driver
3 *
4 * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5 */
6#include <linux/delay.h>
7#include <linux/ethtool.h>
8#include <linux/ethtool_netlink.h>
9#include <linux/kernel.h>
10#include <linux/mdio.h>
11#include <linux/mii.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/phy.h>
15#include <linux/hwmon.h>
16#include <linux/bitfield.h>
17#include <linux/of_mdio.h>
18#include <linux/of_irq.h>
19
20#define PHY_ID_MASK 0xfffffff0
21#define PHY_ID_TJA1100 0x0180dc40
22#define PHY_ID_TJA1101 0x0180dd00
23#define PHY_ID_TJA1102 0x0180dc80
24
25#define MII_ECTRL 17
26#define MII_ECTRL_LINK_CONTROL BIT(15)
27#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
28#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
29#define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
30#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
31#define MII_ECTRL_CABLE_TEST BIT(5)
32#define MII_ECTRL_CONFIG_EN BIT(2)
33#define MII_ECTRL_WAKE_REQUEST BIT(0)
34
35#define MII_CFG1 18
36#define MII_CFG1_MASTER_SLAVE BIT(15)
37#define MII_CFG1_AUTO_OP BIT(14)
38#define MII_CFG1_INTERFACE_MODE_MASK GENMASK(9, 8)
39#define MII_CFG1_MII_MODE (0x0 << 8)
40#define MII_CFG1_RMII_MODE_REFCLK_IN BIT(8)
41#define MII_CFG1_RMII_MODE_REFCLK_OUT BIT(9)
42#define MII_CFG1_REVMII_MODE GENMASK(9, 8)
43#define MII_CFG1_SLEEP_CONFIRM BIT(6)
44#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
45#define MII_CFG1_LED_MODE_LINKUP 0
46#define MII_CFG1_LED_ENABLE BIT(3)
47
48#define MII_CFG2 19
49#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
50#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
51
52#define MII_INTSRC 21
53#define MII_INTSRC_LINK_FAIL BIT(10)
54#define MII_INTSRC_LINK_UP BIT(9)
55#define MII_INTSRC_MASK (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
56#define MII_INTSRC_UV_ERR BIT(3)
57#define MII_INTSRC_TEMP_ERR BIT(1)
58
59#define MII_INTEN 22
60#define MII_INTEN_LINK_FAIL BIT(10)
61#define MII_INTEN_LINK_UP BIT(9)
62#define MII_INTEN_UV_ERR BIT(3)
63#define MII_INTEN_TEMP_ERR BIT(1)
64
65#define MII_COMMSTAT 23
66#define MII_COMMSTAT_LINK_UP BIT(15)
67#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
68#define MII_COMMSTAT_SQI_MAX 7
69
70#define MII_GENSTAT 24
71#define MII_GENSTAT_PLL_LOCKED BIT(14)
72
73#define MII_EXTSTAT 25
74#define MII_EXTSTAT_SHORT_DETECT BIT(8)
75#define MII_EXTSTAT_OPEN_DETECT BIT(7)
76#define MII_EXTSTAT_POLARITY_DETECT BIT(6)
77
78#define MII_COMMCFG 27
79#define MII_COMMCFG_AUTO_OP BIT(15)
80
81/* Configure REF_CLK as input in RMII mode */
82#define TJA110X_RMII_MODE_REFCLK_IN BIT(0)
83
84struct tja11xx_priv {
85 char *hwmon_name;
86 struct device *hwmon_dev;
87 struct phy_device *phydev;
88 struct work_struct phy_register_work;
89 u32 flags;
90};
91
92struct tja11xx_phy_stats {
93 const char *string;
94 u8 reg;
95 u8 off;
96 u16 mask;
97};
98
99static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
100 { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
101 { "phy_polarity_detect", 25, 6, BIT(6) },
102 { "phy_open_detect", 25, 7, BIT(7) },
103 { "phy_short_detect", 25, 8, BIT(8) },
104 { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
105 { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
106};
107
108static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
109{
110 int val;
111
112 return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
113 150, 30000, false);
114}
115
116static int phy_modify_check(struct phy_device *phydev, u8 reg,
117 u16 mask, u16 set)
118{
119 int ret;
120
121 ret = phy_modify(phydev, reg, mask, set);
122 if (ret)
123 return ret;
124
125 return tja11xx_check(phydev, reg, mask, set);
126}
127
128static int tja11xx_enable_reg_write(struct phy_device *phydev)
129{
130 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
131}
132
133static int tja11xx_enable_link_control(struct phy_device *phydev)
134{
135 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
136}
137
138static int tja11xx_disable_link_control(struct phy_device *phydev)
139{
140 return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
141}
142
143static int tja11xx_wakeup(struct phy_device *phydev)
144{
145 int ret;
146
147 ret = phy_read(phydev, MII_ECTRL);
148 if (ret < 0)
149 return ret;
150
151 switch (ret & MII_ECTRL_POWER_MODE_MASK) {
152 case MII_ECTRL_POWER_MODE_NO_CHANGE:
153 break;
154 case MII_ECTRL_POWER_MODE_NORMAL:
155 ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
156 if (ret)
157 return ret;
158
159 ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
160 if (ret)
161 return ret;
162 break;
163 case MII_ECTRL_POWER_MODE_STANDBY:
164 ret = phy_modify_check(phydev, MII_ECTRL,
165 MII_ECTRL_POWER_MODE_MASK,
166 MII_ECTRL_POWER_MODE_STANDBY);
167 if (ret)
168 return ret;
169
170 ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
171 MII_ECTRL_POWER_MODE_NORMAL);
172 if (ret)
173 return ret;
174
175 ret = phy_modify_check(phydev, MII_GENSTAT,
176 MII_GENSTAT_PLL_LOCKED,
177 MII_GENSTAT_PLL_LOCKED);
178 if (ret)
179 return ret;
180
181 return tja11xx_enable_link_control(phydev);
182 default:
183 break;
184 }
185
186 return 0;
187}
188
189static int tja11xx_soft_reset(struct phy_device *phydev)
190{
191 int ret;
192
193 ret = tja11xx_enable_reg_write(phydev);
194 if (ret)
195 return ret;
196
197 return genphy_soft_reset(phydev);
198}
199
200static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
201{
202 bool finished = false;
203 int ret;
204
205 if (phydev->link)
206 return 0;
207
208 if (!phydev->drv->cable_test_start ||
209 !phydev->drv->cable_test_get_status)
210 return 0;
211
212 ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
213 if (ret)
214 return ret;
215
216 ret = phydev->drv->cable_test_start(phydev);
217 if (ret)
218 return ret;
219
220 /* According to the documentation this test takes 100 usec */
221 usleep_range(100, 200);
222
223 ret = phydev->drv->cable_test_get_status(phydev, &finished);
224 if (ret)
225 return ret;
226
227 if (finished)
228 ethnl_cable_test_finished(phydev);
229
230 return 0;
231}
232
233static int tja11xx_config_aneg(struct phy_device *phydev)
234{
235 int ret, changed = 0;
236 u16 ctl = 0;
237
238 switch (phydev->master_slave_set) {
239 case MASTER_SLAVE_CFG_MASTER_FORCE:
240 ctl |= MII_CFG1_MASTER_SLAVE;
241 break;
242 case MASTER_SLAVE_CFG_SLAVE_FORCE:
243 break;
244 case MASTER_SLAVE_CFG_UNKNOWN:
245 case MASTER_SLAVE_CFG_UNSUPPORTED:
246 goto do_test;
247 default:
248 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
249 return -ENOTSUPP;
250 }
251
252 changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
253 if (changed < 0)
254 return changed;
255
256do_test:
257 ret = tja11xx_config_aneg_cable_test(phydev);
258 if (ret)
259 return ret;
260
261 return __genphy_config_aneg(phydev, changed);
262}
263
264static int tja11xx_get_interface_mode(struct phy_device *phydev)
265{
266 struct tja11xx_priv *priv = phydev->priv;
267 int mii_mode;
268
269 switch (phydev->interface) {
270 case PHY_INTERFACE_MODE_MII:
271 mii_mode = MII_CFG1_MII_MODE;
272 break;
273 case PHY_INTERFACE_MODE_REVMII:
274 mii_mode = MII_CFG1_REVMII_MODE;
275 break;
276 case PHY_INTERFACE_MODE_RMII:
277 if (priv->flags & TJA110X_RMII_MODE_REFCLK_IN)
278 mii_mode = MII_CFG1_RMII_MODE_REFCLK_IN;
279 else
280 mii_mode = MII_CFG1_RMII_MODE_REFCLK_OUT;
281 break;
282 default:
283 return -EINVAL;
284 }
285
286 return mii_mode;
287}
288
289static int tja11xx_config_init(struct phy_device *phydev)
290{
291 u16 reg_mask, reg_val;
292 int ret;
293
294 ret = tja11xx_enable_reg_write(phydev);
295 if (ret)
296 return ret;
297
298 phydev->autoneg = AUTONEG_DISABLE;
299 phydev->speed = SPEED_100;
300 phydev->duplex = DUPLEX_FULL;
301
302 switch (phydev->phy_id & PHY_ID_MASK) {
303 case PHY_ID_TJA1100:
304 reg_mask = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
305 MII_CFG1_LED_ENABLE;
306 reg_val = MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
307 MII_CFG1_LED_ENABLE;
308
309 reg_mask |= MII_CFG1_INTERFACE_MODE_MASK;
310 ret = tja11xx_get_interface_mode(phydev);
311 if (ret < 0)
312 return ret;
313
314 reg_val |= (ret & 0xffff);
315 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
316 if (ret)
317 return ret;
318 break;
319 case PHY_ID_TJA1101:
320 reg_mask = MII_CFG1_INTERFACE_MODE_MASK;
321 ret = tja11xx_get_interface_mode(phydev);
322 if (ret < 0)
323 return ret;
324
325 reg_val = ret & 0xffff;
326 ret = phy_modify(phydev, MII_CFG1, reg_mask, reg_val);
327 if (ret)
328 return ret;
329 fallthrough;
330 case PHY_ID_TJA1102:
331 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
332 if (ret)
333 return ret;
334 break;
335 default:
336 return -EINVAL;
337 }
338
339 ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
340 if (ret)
341 return ret;
342
343 ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
344 MII_CFG2_SLEEP_REQUEST_TO_16MS);
345 if (ret)
346 return ret;
347
348 ret = tja11xx_wakeup(phydev);
349 if (ret < 0)
350 return ret;
351
352 /* ACK interrupts by reading the status register */
353 ret = phy_read(phydev, MII_INTSRC);
354 if (ret < 0)
355 return ret;
356
357 return 0;
358}
359
360static int tja11xx_read_status(struct phy_device *phydev)
361{
362 int ret;
363
364 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
365 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
366
367 ret = genphy_update_link(phydev);
368 if (ret)
369 return ret;
370
371 ret = phy_read(phydev, MII_CFG1);
372 if (ret < 0)
373 return ret;
374
375 if (ret & MII_CFG1_MASTER_SLAVE)
376 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
377 else
378 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
379
380 if (phydev->link) {
381 ret = phy_read(phydev, MII_COMMSTAT);
382 if (ret < 0)
383 return ret;
384
385 if (!(ret & MII_COMMSTAT_LINK_UP))
386 phydev->link = 0;
387 }
388
389 return 0;
390}
391
392static int tja11xx_get_sqi(struct phy_device *phydev)
393{
394 int ret;
395
396 ret = phy_read(phydev, MII_COMMSTAT);
397 if (ret < 0)
398 return ret;
399
400 return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
401}
402
403static int tja11xx_get_sqi_max(struct phy_device *phydev)
404{
405 return MII_COMMSTAT_SQI_MAX;
406}
407
408static int tja11xx_get_sset_count(struct phy_device *phydev)
409{
410 return ARRAY_SIZE(tja11xx_hw_stats);
411}
412
413static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
414{
415 int i;
416
417 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
418 strncpy(data + i * ETH_GSTRING_LEN,
419 tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
420 }
421}
422
423static void tja11xx_get_stats(struct phy_device *phydev,
424 struct ethtool_stats *stats, u64 *data)
425{
426 int i, ret;
427
428 for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
429 ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
430 if (ret < 0)
431 data[i] = U64_MAX;
432 else {
433 data[i] = ret & tja11xx_hw_stats[i].mask;
434 data[i] >>= tja11xx_hw_stats[i].off;
435 }
436 }
437}
438
439static int tja11xx_hwmon_read(struct device *dev,
440 enum hwmon_sensor_types type,
441 u32 attr, int channel, long *value)
442{
443 struct phy_device *phydev = dev_get_drvdata(dev);
444 int ret;
445
446 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
447 ret = phy_read(phydev, MII_INTSRC);
448 if (ret < 0)
449 return ret;
450
451 *value = !!(ret & MII_INTSRC_TEMP_ERR);
452 return 0;
453 }
454
455 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
456 ret = phy_read(phydev, MII_INTSRC);
457 if (ret < 0)
458 return ret;
459
460 *value = !!(ret & MII_INTSRC_UV_ERR);
461 return 0;
462 }
463
464 return -EOPNOTSUPP;
465}
466
467static umode_t tja11xx_hwmon_is_visible(const void *data,
468 enum hwmon_sensor_types type,
469 u32 attr, int channel)
470{
471 if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
472 return 0444;
473
474 if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
475 return 0444;
476
477 return 0;
478}
479
480static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
481 HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
482 HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
483 NULL
484};
485
486static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
487 .is_visible = tja11xx_hwmon_is_visible,
488 .read = tja11xx_hwmon_read,
489};
490
491static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
492 .ops = &tja11xx_hwmon_hwmon_ops,
493 .info = tja11xx_hwmon_info,
494};
495
496static int tja11xx_hwmon_register(struct phy_device *phydev,
497 struct tja11xx_priv *priv)
498{
499 struct device *dev = &phydev->mdio.dev;
500
501 priv->hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
502 if (IS_ERR(priv->hwmon_name))
503 return PTR_ERR(priv->hwmon_name);
504
505 priv->hwmon_dev =
506 devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
507 phydev,
508 &tja11xx_hwmon_chip_info,
509 NULL);
510
511 return PTR_ERR_OR_ZERO(priv->hwmon_dev);
512}
513
514static int tja11xx_parse_dt(struct phy_device *phydev)
515{
516 struct device_node *node = phydev->mdio.dev.of_node;
517 struct tja11xx_priv *priv = phydev->priv;
518
519 if (!IS_ENABLED(CONFIG_OF_MDIO))
520 return 0;
521
522 if (of_property_read_bool(node, "nxp,rmii-refclk-in"))
523 priv->flags |= TJA110X_RMII_MODE_REFCLK_IN;
524
525 return 0;
526}
527
528static int tja11xx_probe(struct phy_device *phydev)
529{
530 struct device *dev = &phydev->mdio.dev;
531 struct tja11xx_priv *priv;
532 int ret;
533
534 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
535 if (!priv)
536 return -ENOMEM;
537
538 priv->phydev = phydev;
539 phydev->priv = priv;
540
541 ret = tja11xx_parse_dt(phydev);
542 if (ret)
543 return ret;
544
545 return tja11xx_hwmon_register(phydev, priv);
546}
547
548static void tja1102_p1_register(struct work_struct *work)
549{
550 struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
551 phy_register_work);
552 struct phy_device *phydev_phy0 = priv->phydev;
553 struct mii_bus *bus = phydev_phy0->mdio.bus;
554 struct device *dev = &phydev_phy0->mdio.dev;
555 struct device_node *np = dev->of_node;
556 struct device_node *child;
557 int ret;
558
559 for_each_available_child_of_node(np, child) {
560 struct phy_device *phy;
561 int addr;
562
563 addr = of_mdio_parse_addr(dev, child);
564 if (addr < 0) {
565 dev_err(dev, "Can't parse addr\n");
566 continue;
567 } else if (addr != phydev_phy0->mdio.addr + 1) {
568 /* Currently we care only about double PHY chip TJA1102.
569 * If some day NXP will decide to bring chips with more
570 * PHYs, this logic should be reworked.
571 */
572 dev_err(dev, "Unexpected address. Should be: %i\n",
573 phydev_phy0->mdio.addr + 1);
574 continue;
575 }
576
577 if (mdiobus_is_registered_device(bus, addr)) {
578 dev_err(dev, "device is already registered\n");
579 continue;
580 }
581
582 /* Real PHY ID of Port 1 is 0 */
583 phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
584 if (IS_ERR(phy)) {
585 dev_err(dev, "Can't create PHY device for Port 1: %i\n",
586 addr);
587 continue;
588 }
589
590 /* Overwrite parent device. phy_device_create() set parent to
591 * the mii_bus->dev, which is not correct in case.
592 */
593 phy->mdio.dev.parent = dev;
594
595 ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
596 if (ret) {
597 /* All resources needed for Port 1 should be already
598 * available for Port 0. Both ports use the same
599 * interrupt line, so -EPROBE_DEFER would make no sense
600 * here.
601 */
602 dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
603 ret);
604 phy_device_free(phy);
605 }
606 }
607}
608
609static int tja1102_p0_probe(struct phy_device *phydev)
610{
611 struct device *dev = &phydev->mdio.dev;
612 struct tja11xx_priv *priv;
613 int ret;
614
615 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
616 if (!priv)
617 return -ENOMEM;
618
619 priv->phydev = phydev;
620 INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
621
622 ret = tja11xx_hwmon_register(phydev, priv);
623 if (ret)
624 return ret;
625
626 schedule_work(&priv->phy_register_work);
627
628 return 0;
629}
630
631static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
632{
633 int ret;
634
635 if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
636 return 0;
637
638 ret = phy_read(phydev, MII_PHYSID2);
639 if (ret < 0)
640 return ret;
641
642 /* TJA1102 Port 1 has phyid 0 and doesn't support temperature
643 * and undervoltage alarms.
644 */
645 if (port0)
646 return ret ? 1 : 0;
647
648 return !ret;
649}
650
651static int tja1102_p0_match_phy_device(struct phy_device *phydev)
652{
653 return tja1102_match_phy_device(phydev, true);
654}
655
656static int tja1102_p1_match_phy_device(struct phy_device *phydev)
657{
658 return tja1102_match_phy_device(phydev, false);
659}
660
661static int tja11xx_ack_interrupt(struct phy_device *phydev)
662{
663 int ret;
664
665 ret = phy_read(phydev, MII_INTSRC);
666
667 return (ret < 0) ? ret : 0;
668}
669
670static int tja11xx_config_intr(struct phy_device *phydev)
671{
672 int value = 0;
673 int err;
674
675 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
676 err = tja11xx_ack_interrupt(phydev);
677 if (err)
678 return err;
679
680 value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP |
681 MII_INTEN_UV_ERR | MII_INTEN_TEMP_ERR;
682 err = phy_write(phydev, MII_INTEN, value);
683 } else {
684 err = phy_write(phydev, MII_INTEN, value);
685 if (err)
686 return err;
687
688 err = tja11xx_ack_interrupt(phydev);
689 }
690
691 return err;
692}
693
694static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
695{
696 struct device *dev = &phydev->mdio.dev;
697 int irq_status;
698
699 irq_status = phy_read(phydev, MII_INTSRC);
700 if (irq_status < 0) {
701 phy_error(phydev);
702 return IRQ_NONE;
703 }
704
705 if (irq_status & MII_INTSRC_TEMP_ERR)
706 dev_warn(dev, "Overtemperature error detected (temp > 155C°).\n");
707 if (irq_status & MII_INTSRC_UV_ERR)
708 dev_warn(dev, "Undervoltage error detected.\n");
709
710 if (!(irq_status & MII_INTSRC_MASK))
711 return IRQ_NONE;
712
713 phy_trigger_machine(phydev);
714
715 return IRQ_HANDLED;
716}
717
718static int tja11xx_cable_test_start(struct phy_device *phydev)
719{
720 int ret;
721
722 ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
723 if (ret)
724 return ret;
725
726 ret = tja11xx_wakeup(phydev);
727 if (ret < 0)
728 return ret;
729
730 ret = tja11xx_disable_link_control(phydev);
731 if (ret < 0)
732 return ret;
733
734 return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
735}
736
737/*
738 * | BI_DA+ | BI_DA- | Result
739 * | open | open | open
740 * | + short to - | - short to + | short
741 * | short to Vdd | open | open
742 * | open | shot to Vdd | open
743 * | short to Vdd | short to Vdd | short
744 * | shot to GND | open | open
745 * | open | shot to GND | open
746 * | short to GND | shot to GND | short
747 * | connected to active link partner (master) | shot and open
748 */
749static int tja11xx_cable_test_report_trans(u32 result)
750{
751 u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
752
753 if ((result & mask) == mask) {
754 /* connected to active link partner (master) */
755 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
756 } else if ((result & mask) == 0) {
757 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
758 } else if (result & MII_EXTSTAT_SHORT_DETECT) {
759 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
760 } else if (result & MII_EXTSTAT_OPEN_DETECT) {
761 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
762 } else {
763 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
764 }
765}
766
767static int tja11xx_cable_test_report(struct phy_device *phydev)
768{
769 int ret;
770
771 ret = phy_read(phydev, MII_EXTSTAT);
772 if (ret < 0)
773 return ret;
774
775 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
776 tja11xx_cable_test_report_trans(ret));
777
778 return 0;
779}
780
781static int tja11xx_cable_test_get_status(struct phy_device *phydev,
782 bool *finished)
783{
784 int ret;
785
786 *finished = false;
787
788 ret = phy_read(phydev, MII_ECTRL);
789 if (ret < 0)
790 return ret;
791
792 if (!(ret & MII_ECTRL_CABLE_TEST)) {
793 *finished = true;
794
795 ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
796 if (ret)
797 return ret;
798
799 return tja11xx_cable_test_report(phydev);
800 }
801
802 return 0;
803}
804
805static struct phy_driver tja11xx_driver[] = {
806 {
807 PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
808 .name = "NXP TJA1100",
809 .features = PHY_BASIC_T1_FEATURES,
810 .probe = tja11xx_probe,
811 .soft_reset = tja11xx_soft_reset,
812 .config_aneg = tja11xx_config_aneg,
813 .config_init = tja11xx_config_init,
814 .read_status = tja11xx_read_status,
815 .get_sqi = tja11xx_get_sqi,
816 .get_sqi_max = tja11xx_get_sqi_max,
817 .suspend = genphy_suspend,
818 .resume = genphy_resume,
819 .set_loopback = genphy_loopback,
820 /* Statistics */
821 .get_sset_count = tja11xx_get_sset_count,
822 .get_strings = tja11xx_get_strings,
823 .get_stats = tja11xx_get_stats,
824 }, {
825 PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
826 .name = "NXP TJA1101",
827 .features = PHY_BASIC_T1_FEATURES,
828 .probe = tja11xx_probe,
829 .soft_reset = tja11xx_soft_reset,
830 .config_aneg = tja11xx_config_aneg,
831 .config_init = tja11xx_config_init,
832 .read_status = tja11xx_read_status,
833 .get_sqi = tja11xx_get_sqi,
834 .get_sqi_max = tja11xx_get_sqi_max,
835 .suspend = genphy_suspend,
836 .resume = genphy_resume,
837 .set_loopback = genphy_loopback,
838 /* Statistics */
839 .get_sset_count = tja11xx_get_sset_count,
840 .get_strings = tja11xx_get_strings,
841 .get_stats = tja11xx_get_stats,
842 }, {
843 .name = "NXP TJA1102 Port 0",
844 .features = PHY_BASIC_T1_FEATURES,
845 .flags = PHY_POLL_CABLE_TEST,
846 .probe = tja1102_p0_probe,
847 .soft_reset = tja11xx_soft_reset,
848 .config_aneg = tja11xx_config_aneg,
849 .config_init = tja11xx_config_init,
850 .read_status = tja11xx_read_status,
851 .get_sqi = tja11xx_get_sqi,
852 .get_sqi_max = tja11xx_get_sqi_max,
853 .match_phy_device = tja1102_p0_match_phy_device,
854 .suspend = genphy_suspend,
855 .resume = genphy_resume,
856 .set_loopback = genphy_loopback,
857 /* Statistics */
858 .get_sset_count = tja11xx_get_sset_count,
859 .get_strings = tja11xx_get_strings,
860 .get_stats = tja11xx_get_stats,
861 .config_intr = tja11xx_config_intr,
862 .handle_interrupt = tja11xx_handle_interrupt,
863 .cable_test_start = tja11xx_cable_test_start,
864 .cable_test_get_status = tja11xx_cable_test_get_status,
865 }, {
866 .name = "NXP TJA1102 Port 1",
867 .features = PHY_BASIC_T1_FEATURES,
868 .flags = PHY_POLL_CABLE_TEST,
869 /* currently no probe for Port 1 is need */
870 .soft_reset = tja11xx_soft_reset,
871 .config_aneg = tja11xx_config_aneg,
872 .config_init = tja11xx_config_init,
873 .read_status = tja11xx_read_status,
874 .get_sqi = tja11xx_get_sqi,
875 .get_sqi_max = tja11xx_get_sqi_max,
876 .match_phy_device = tja1102_p1_match_phy_device,
877 .suspend = genphy_suspend,
878 .resume = genphy_resume,
879 .set_loopback = genphy_loopback,
880 /* Statistics */
881 .get_sset_count = tja11xx_get_sset_count,
882 .get_strings = tja11xx_get_strings,
883 .get_stats = tja11xx_get_stats,
884 .config_intr = tja11xx_config_intr,
885 .handle_interrupt = tja11xx_handle_interrupt,
886 .cable_test_start = tja11xx_cable_test_start,
887 .cable_test_get_status = tja11xx_cable_test_get_status,
888 }
889};
890
891module_phy_driver(tja11xx_driver);
892
893static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
894 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
895 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
896 { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
897 { }
898};
899
900MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
901
902MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
903MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
904MODULE_LICENSE("GPL");