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1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
2/*
3 * Driver for Microsemi VSC85xx PHYs
4 *
5 * Copyright (c) 2016 Microsemi Corporation
6 */
7
8#ifndef _MSCC_PHY_H_
9#define _MSCC_PHY_H_
10
11#if IS_ENABLED(CONFIG_MACSEC)
12#include "mscc_macsec.h"
13#endif
14
15enum rgmii_clock_delay {
16 RGMII_CLK_DELAY_0_2_NS = 0,
17 RGMII_CLK_DELAY_0_8_NS = 1,
18 RGMII_CLK_DELAY_1_1_NS = 2,
19 RGMII_CLK_DELAY_1_7_NS = 3,
20 RGMII_CLK_DELAY_2_0_NS = 4,
21 RGMII_CLK_DELAY_2_3_NS = 5,
22 RGMII_CLK_DELAY_2_6_NS = 6,
23 RGMII_CLK_DELAY_3_4_NS = 7
24};
25
26/* Microsemi VSC85xx PHY registers */
27/* IEEE 802. Std Registers */
28#define MSCC_PHY_BYPASS_CONTROL 18
29#define DISABLE_HP_AUTO_MDIX_MASK 0x0080
30#define DISABLE_PAIR_SWAP_CORR_MASK 0x0020
31#define DISABLE_POLARITY_CORR_MASK 0x0010
32#define PARALLEL_DET_IGNORE_ADVERTISED 0x0008
33
34#define MSCC_PHY_EXT_CNTL_STATUS 22
35#define SMI_BROADCAST_WR_EN 0x0001
36
37#define MSCC_PHY_ERR_RX_CNT 19
38#define MSCC_PHY_ERR_FALSE_CARRIER_CNT 20
39#define MSCC_PHY_ERR_LINK_DISCONNECT_CNT 21
40#define ERR_CNT_MASK GENMASK(7, 0)
41
42#define MSCC_PHY_EXT_PHY_CNTL_1 23
43#define MAC_IF_SELECTION_MASK 0x1800
44#define MAC_IF_SELECTION_GMII 0
45#define MAC_IF_SELECTION_RMII 1
46#define MAC_IF_SELECTION_RGMII 2
47#define MAC_IF_SELECTION_POS 11
48#define VSC8584_MAC_IF_SELECTION_MASK 0x1000
49#define VSC8584_MAC_IF_SELECTION_SGMII 0
50#define VSC8584_MAC_IF_SELECTION_1000BASEX 1
51#define VSC8584_MAC_IF_SELECTION_POS 12
52#define FAR_END_LOOPBACK_MODE_MASK 0x0008
53#define MEDIA_OP_MODE_MASK 0x0700
54#define MEDIA_OP_MODE_COPPER 0
55#define MEDIA_OP_MODE_SERDES 1
56#define MEDIA_OP_MODE_1000BASEX 2
57#define MEDIA_OP_MODE_100BASEFX 3
58#define MEDIA_OP_MODE_AMS_COPPER_SERDES 5
59#define MEDIA_OP_MODE_AMS_COPPER_1000BASEX 6
60#define MEDIA_OP_MODE_AMS_COPPER_100BASEFX 7
61#define MEDIA_OP_MODE_POS 8
62
63#define MSCC_PHY_EXT_PHY_CNTL_2 24
64
65#define MII_VSC85XX_INT_MASK 25
66#define MII_VSC85XX_INT_MASK_MDINT BIT(15)
67#define MII_VSC85XX_INT_MASK_LINK_CHG BIT(13)
68#define MII_VSC85XX_INT_MASK_WOL BIT(6)
69#define MII_VSC85XX_INT_MASK_EXT BIT(5)
70#define MII_VSC85XX_INT_STATUS 26
71
72#define MII_VSC85XX_INT_MASK_MASK (MII_VSC85XX_INT_MASK_MDINT | \
73 MII_VSC85XX_INT_MASK_LINK_CHG | \
74 MII_VSC85XX_INT_MASK_EXT)
75
76#define MSCC_PHY_WOL_MAC_CONTROL 27
77#define EDGE_RATE_CNTL_POS 5
78#define EDGE_RATE_CNTL_MASK 0x00E0
79
80#define MSCC_PHY_DEV_AUX_CNTL 28
81#define HP_AUTO_MDIX_X_OVER_IND_MASK 0x2000
82
83#define MSCC_PHY_LED_MODE_SEL 29
84#define LED_MODE_SEL_POS(x) ((x) * 4)
85#define LED_MODE_SEL_MASK(x) (GENMASK(3, 0) << LED_MODE_SEL_POS(x))
86#define LED_MODE_SEL(x, mode) (((mode) << LED_MODE_SEL_POS(x)) & LED_MODE_SEL_MASK(x))
87
88#define MSCC_EXT_PAGE_CSR_CNTL_17 17
89#define MSCC_EXT_PAGE_CSR_CNTL_18 18
90
91#define MSCC_EXT_PAGE_CSR_CNTL_19 19
92#define MSCC_PHY_CSR_CNTL_19_REG_ADDR(x) (x)
93#define MSCC_PHY_CSR_CNTL_19_TARGET(x) ((x) << 12)
94#define MSCC_PHY_CSR_CNTL_19_READ BIT(14)
95#define MSCC_PHY_CSR_CNTL_19_CMD BIT(15)
96
97#define MSCC_EXT_PAGE_CSR_CNTL_20 20
98#define MSCC_PHY_CSR_CNTL_20_TARGET(x) (x)
99
100#define PHY_MCB_TARGET 0x07
101#define PHY_MCB_S6G_WRITE BIT(31)
102#define PHY_MCB_S6G_READ BIT(30)
103
104#define PHY_S6G_PLL5G_CFG0 0x06
105#define PHY_S6G_PLL5G_CFG2 0x08
106#define PHY_S6G_LCPLL_CFG 0x11
107#define PHY_S6G_PLL_CFG 0x2b
108#define PHY_S6G_COMMON_CFG 0x2c
109#define PHY_S6G_GPC_CFG 0x2e
110#define PHY_S6G_MISC_CFG 0x3b
111#define PHY_MCB_S6G_CFG 0x3f
112#define PHY_S6G_DFT_CFG2 0x3e
113#define PHY_S6G_PLL_STATUS 0x31
114#define PHY_S6G_IB_STATUS0 0x2f
115
116#define PHY_S6G_SYS_RST_POS 31
117#define PHY_S6G_ENA_LANE_POS 18
118#define PHY_S6G_ENA_LOOP_POS 8
119#define PHY_S6G_QRATE_POS 6
120#define PHY_S6G_IF_MODE_POS 4
121#define PHY_S6G_PLL_ENA_OFFS_POS 21
122#define PHY_S6G_PLL_FSM_CTRL_DATA_POS 8
123#define PHY_S6G_PLL_FSM_ENA_POS 7
124
125#define PHY_S6G_CFG2_FSM_DIS 1
126#define PHY_S6G_CFG2_FSM_CLK_BP 23
127
128#define MSCC_EXT_PAGE_ACCESS 31
129#define MSCC_PHY_PAGE_STANDARD 0x0000 /* Standard registers */
130#define MSCC_PHY_PAGE_EXTENDED 0x0001 /* Extended registers */
131#define MSCC_PHY_PAGE_EXTENDED_2 0x0002 /* Extended reg - page 2 */
132#define MSCC_PHY_PAGE_EXTENDED_3 0x0003 /* Extended reg - page 3 */
133#define MSCC_PHY_PAGE_EXTENDED_4 0x0004 /* Extended reg - page 4 */
134#define MSCC_PHY_PAGE_CSR_CNTL MSCC_PHY_PAGE_EXTENDED_4
135#define MSCC_PHY_PAGE_MACSEC MSCC_PHY_PAGE_EXTENDED_4
136/* Extended reg - GPIO; this is a bank of registers that are shared for all PHYs
137 * in the same package.
138 */
139#define MSCC_PHY_PAGE_EXTENDED_GPIO 0x0010 /* Extended reg - GPIO */
140#define MSCC_PHY_PAGE_1588 0x1588 /* PTP (1588) */
141#define MSCC_PHY_PAGE_TEST 0x2a30 /* Test reg */
142#define MSCC_PHY_PAGE_TR 0x52b5 /* Token ring registers */
143#define MSCC_PHY_GPIO_CONTROL_2 14
144
145#define MSCC_PHY_COMA_MODE 0x2000 /* input(1) / output(0) */
146#define MSCC_PHY_COMA_OUTPUT 0x1000 /* value to output */
147
148/* Extended Page 1 Registers */
149#define MSCC_PHY_CU_MEDIA_CRC_VALID_CNT 18
150#define VALID_CRC_CNT_CRC_MASK GENMASK(13, 0)
151
152#define MSCC_PHY_EXT_MODE_CNTL 19
153#define FORCE_MDI_CROSSOVER_MASK 0x000C
154#define FORCE_MDI_CROSSOVER_MDIX 0x000C
155#define FORCE_MDI_CROSSOVER_MDI 0x0008
156
157#define MSCC_PHY_ACTIPHY_CNTL 20
158#define PHY_ADDR_REVERSED 0x0200
159#define DOWNSHIFT_CNTL_MASK 0x001C
160#define DOWNSHIFT_EN 0x0010
161#define DOWNSHIFT_CNTL_POS 2
162
163#define MSCC_PHY_EXT_PHY_CNTL_4 23
164#define PHY_CNTL_4_ADDR_POS 11
165
166#define MSCC_PHY_VERIPHY_CNTL_2 25
167
168#define MSCC_PHY_VERIPHY_CNTL_3 26
169
170/* Extended Page 2 Registers */
171#define MSCC_PHY_CU_PMD_TX_CNTL 16
172
173/* RGMII setting controls at address 18E2, for VSC8572 and similar */
174#define VSC8572_RGMII_CNTL 18
175#define VSC8572_RGMII_RX_DELAY_MASK 0x000E
176#define VSC8572_RGMII_TX_DELAY_MASK 0x0070
177
178/* RGMII controls at address 20E2, for VSC8502 and similar */
179#define VSC8502_RGMII_CNTL 20
180#define VSC8502_RGMII_RX_DELAY_MASK 0x0070
181#define VSC8502_RGMII_TX_DELAY_MASK 0x0007
182
183#define MSCC_PHY_WOL_LOWER_MAC_ADDR 21
184#define MSCC_PHY_WOL_MID_MAC_ADDR 22
185#define MSCC_PHY_WOL_UPPER_MAC_ADDR 23
186#define MSCC_PHY_WOL_LOWER_PASSWD 24
187#define MSCC_PHY_WOL_MID_PASSWD 25
188#define MSCC_PHY_WOL_UPPER_PASSWD 26
189
190#define MSCC_PHY_WOL_MAC_CONTROL 27
191#define SECURE_ON_ENABLE 0x8000
192#define SECURE_ON_PASSWD_LEN_4 0x4000
193
194#define MSCC_PHY_EXTENDED_INT 28
195#define MSCC_PHY_EXTENDED_INT_MS_EGR BIT(9)
196
197/* Extended Page 3 Registers */
198#define MSCC_PHY_SERDES_TX_VALID_CNT 21
199#define MSCC_PHY_SERDES_TX_CRC_ERR_CNT 22
200#define MSCC_PHY_SERDES_RX_VALID_CNT 28
201#define MSCC_PHY_SERDES_RX_CRC_ERR_CNT 29
202
203/* Extended page GPIO Registers */
204#define MSCC_DW8051_CNTL_STATUS 0
205#define MICRO_NSOFT_RESET 0x8000
206#define RUN_FROM_INT_ROM 0x4000
207#define AUTOINC_ADDR 0x2000
208#define PATCH_RAM_CLK 0x1000
209#define MICRO_PATCH_EN 0x0080
210#define DW8051_CLK_EN 0x0010
211#define MICRO_CLK_EN 0x0008
212#define MICRO_CLK_DIVIDE(x) ((x) >> 1)
213#define MSCC_DW8051_VLD_MASK 0xf1ff
214
215/* x Address in range 1-4 */
216#define MSCC_TRAP_ROM_ADDR(x) ((x) * 2 + 1)
217#define MSCC_PATCH_RAM_ADDR(x) (((x) + 1) * 2)
218#define MSCC_INT_MEM_ADDR 11
219
220#define MSCC_INT_MEM_CNTL 12
221#define READ_SFR 0x6000
222#define READ_PRAM 0x4000
223#define READ_ROM 0x2000
224#define READ_RAM 0x0000
225#define INT_MEM_WRITE_EN 0x1000
226#define EN_PATCH_RAM_TRAP_ADDR(x) (0x0100 << ((x) - 1))
227#define INT_MEM_DATA_M 0x00ff
228#define INT_MEM_DATA(x) (INT_MEM_DATA_M & (x))
229
230#define MSCC_PHY_PROC_CMD 18
231#define PROC_CMD_NCOMPLETED 0x8000
232#define PROC_CMD_FAILED 0x4000
233#define PROC_CMD_SGMII_PORT(x) ((x) << 8)
234#define PROC_CMD_FIBER_PORT(x) (0x0100 << (x) % 4)
235#define PROC_CMD_QSGMII_PORT 0x0c00
236#define PROC_CMD_RST_CONF_PORT 0x0080
237#define PROC_CMD_RECONF_PORT 0x0000
238#define PROC_CMD_READ_MOD_WRITE_PORT 0x0040
239#define PROC_CMD_WRITE 0x0040
240#define PROC_CMD_READ 0x0000
241#define PROC_CMD_FIBER_DISABLE 0x0020
242#define PROC_CMD_FIBER_100BASE_FX 0x0010
243#define PROC_CMD_FIBER_1000BASE_X 0x0000
244#define PROC_CMD_SGMII_MAC 0x0030
245#define PROC_CMD_QSGMII_MAC 0x0020
246#define PROC_CMD_NO_MAC_CONF 0x0000
247#define PROC_CMD_1588_DEFAULT_INIT 0x0010
248#define PROC_CMD_NOP 0x000f
249#define PROC_CMD_PHY_INIT 0x000a
250#define PROC_CMD_CRC16 0x0008
251#define PROC_CMD_FIBER_MEDIA_CONF 0x0001
252#define PROC_CMD_MCB_ACCESS_MAC_CONF 0x0000
253#define PROC_CMD_NCOMPLETED_TIMEOUT_MS 500
254
255#define MSCC_PHY_MAC_CFG_FASTLINK 19
256#define MAC_CFG_MASK 0xc000
257#define MAC_CFG_SGMII 0x0000
258#define MAC_CFG_QSGMII 0x4000
259#define MAC_CFG_RGMII 0x8000
260
261/* Test page Registers */
262#define MSCC_PHY_TEST_PAGE_5 5
263#define MSCC_PHY_TEST_PAGE_8 8
264#define TR_CLK_DISABLE 0x8000
265#define MSCC_PHY_TEST_PAGE_9 9
266#define MSCC_PHY_TEST_PAGE_20 20
267#define MSCC_PHY_TEST_PAGE_24 24
268
269/* Token ring page Registers */
270#define MSCC_PHY_TR_CNTL 16
271#define TR_WRITE 0x8000
272#define TR_ADDR(x) (0x7fff & (x))
273#define MSCC_PHY_TR_LSB 17
274#define MSCC_PHY_TR_MSB 18
275
276/* Microsemi PHY ID's
277 * Code assumes lowest nibble is 0
278 */
279#define PHY_ID_VSC8502 0x00070630
280#define PHY_ID_VSC8504 0x000704c0
281#define PHY_ID_VSC8514 0x00070670
282#define PHY_ID_VSC8530 0x00070560
283#define PHY_ID_VSC8531 0x00070570
284#define PHY_ID_VSC8540 0x00070760
285#define PHY_ID_VSC8541 0x00070770
286#define PHY_ID_VSC8552 0x000704e0
287#define PHY_ID_VSC856X 0x000707e0
288#define PHY_ID_VSC8572 0x000704d0
289#define PHY_ID_VSC8574 0x000704a0
290#define PHY_ID_VSC8575 0x000707d0
291#define PHY_ID_VSC8582 0x000707b0
292#define PHY_ID_VSC8584 0x000707c0
293
294#define MSCC_VDDMAC_1500 1500
295#define MSCC_VDDMAC_1800 1800
296#define MSCC_VDDMAC_2500 2500
297#define MSCC_VDDMAC_3300 3300
298
299#define DOWNSHIFT_COUNT_MAX 5
300
301#define MAX_LEDS 4
302
303#define VSC8584_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
304 BIT(VSC8531_LINK_1000_ACTIVITY) | \
305 BIT(VSC8531_LINK_100_ACTIVITY) | \
306 BIT(VSC8531_LINK_10_ACTIVITY) | \
307 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
308 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
309 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
310 BIT(VSC8584_LINK_100FX_1000X_ACTIVITY) | \
311 BIT(VSC8531_DUPLEX_COLLISION) | \
312 BIT(VSC8531_COLLISION) | \
313 BIT(VSC8531_ACTIVITY) | \
314 BIT(VSC8584_100FX_1000X_ACTIVITY) | \
315 BIT(VSC8531_AUTONEG_FAULT) | \
316 BIT(VSC8531_SERIAL_MODE) | \
317 BIT(VSC8531_FORCE_LED_OFF) | \
318 BIT(VSC8531_FORCE_LED_ON))
319
320#define VSC85XX_SUPP_LED_MODES (BIT(VSC8531_LINK_ACTIVITY) | \
321 BIT(VSC8531_LINK_1000_ACTIVITY) | \
322 BIT(VSC8531_LINK_100_ACTIVITY) | \
323 BIT(VSC8531_LINK_10_ACTIVITY) | \
324 BIT(VSC8531_LINK_100_1000_ACTIVITY) | \
325 BIT(VSC8531_LINK_10_1000_ACTIVITY) | \
326 BIT(VSC8531_LINK_10_100_ACTIVITY) | \
327 BIT(VSC8531_DUPLEX_COLLISION) | \
328 BIT(VSC8531_COLLISION) | \
329 BIT(VSC8531_ACTIVITY) | \
330 BIT(VSC8531_AUTONEG_FAULT) | \
331 BIT(VSC8531_SERIAL_MODE) | \
332 BIT(VSC8531_FORCE_LED_OFF) | \
333 BIT(VSC8531_FORCE_LED_ON))
334
335#define MSCC_VSC8584_REVB_INT8051_FW "microchip/mscc_vsc8584_revb_int8051_fb48.bin"
336#define MSCC_VSC8584_REVB_INT8051_FW_START_ADDR 0xe800
337#define MSCC_VSC8584_REVB_INT8051_FW_CRC 0xfb48
338
339#define MSCC_VSC8574_REVB_INT8051_FW "microchip/mscc_vsc8574_revb_int8051_29e8.bin"
340#define MSCC_VSC8574_REVB_INT8051_FW_START_ADDR 0x4000
341#define MSCC_VSC8574_REVB_INT8051_FW_CRC 0x29e8
342
343#define VSC8584_REVB 0x0001
344#define MSCC_DEV_REV_MASK GENMASK(3, 0)
345
346#define MSCC_ROM_TRAP_SERDES_6G_CFG 0x1E48
347#define MSCC_RAM_TRAP_SERDES_6G_CFG 0x1E4F
348#define PATCH_VEC_ZERO_EN 0x0100
349
350struct reg_val {
351 u16 reg;
352 u32 val;
353};
354
355struct vsc85xx_hw_stat {
356 const char *string;
357 u8 reg;
358 u16 page;
359 u16 mask;
360};
361
362struct vsc8531_private {
363 int rate_magic;
364 u16 supp_led_modes;
365 u32 leds_mode[MAX_LEDS];
366 u8 nleds;
367 const struct vsc85xx_hw_stat *hw_stats;
368 u64 *stats;
369 int nstats;
370 /* PHY address within the package. */
371 u8 addr;
372 /* For multiple port PHYs; the MDIO address of the base PHY in the
373 * package.
374 */
375 unsigned int base_addr;
376
377#if IS_ENABLED(CONFIG_MACSEC)
378 /* MACsec fields:
379 * - One SecY per device (enforced at the s/w implementation level)
380 * - macsec_flows: list of h/w flows
381 * - ingr_flows: bitmap of ingress flows
382 * - egr_flows: bitmap of egress flows
383 */
384 struct macsec_secy *secy;
385 struct list_head macsec_flows;
386 unsigned long ingr_flows;
387 unsigned long egr_flows;
388#endif
389
390 struct mii_timestamper mii_ts;
391
392 bool input_clk_init;
393 struct vsc85xx_ptp *ptp;
394 /* LOAD/SAVE GPIO pin, used for retrieving or setting time to the PHC. */
395 struct gpio_desc *load_save;
396
397 /* For multiple port PHYs; the MDIO address of the base PHY in the
398 * pair of two PHYs that share a 1588 engine. PHY0 and PHY2 are coupled.
399 * PHY1 and PHY3 as well. PHY0 and PHY1 are base PHYs for their
400 * respective pair.
401 */
402 unsigned int ts_base_addr;
403 u8 ts_base_phy;
404
405 /* ts_lock: used for per-PHY timestamping operations.
406 * phc_lock: used for per-PHY PHC opertations.
407 */
408 struct mutex ts_lock;
409 struct mutex phc_lock;
410};
411
412/* Shared structure between the PHYs of the same package.
413 * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO
414 * is shared.
415 */
416struct vsc85xx_shared_private {
417 struct mutex gpio_lock;
418};
419
420#if IS_ENABLED(CONFIG_OF_MDIO)
421struct vsc8531_edge_rate_table {
422 u32 vddmac;
423 u32 slowdown[8];
424};
425#endif /* CONFIG_OF_MDIO */
426
427enum csr_target {
428 MACRO_CTRL = 0x07,
429};
430
431u32 vsc85xx_csr_read(struct phy_device *phydev,
432 enum csr_target target, u32 reg);
433
434int vsc85xx_csr_write(struct phy_device *phydev,
435 enum csr_target target, u32 reg, u32 val);
436
437int phy_base_write(struct phy_device *phydev, u32 regnum, u16 val);
438int phy_base_read(struct phy_device *phydev, u32 regnum);
439int phy_update_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb);
440int phy_commit_mcb_s6g(struct phy_device *phydev, u32 reg, u8 mcb);
441int vsc8584_cmd(struct phy_device *phydev, u16 val);
442
443#if IS_ENABLED(CONFIG_MACSEC)
444int vsc8584_macsec_init(struct phy_device *phydev);
445void vsc8584_handle_macsec_interrupt(struct phy_device *phydev);
446void vsc8584_config_macsec_intr(struct phy_device *phydev);
447#else
448static inline int vsc8584_macsec_init(struct phy_device *phydev)
449{
450 return 0;
451}
452static inline void vsc8584_handle_macsec_interrupt(struct phy_device *phydev)
453{
454}
455static inline void vsc8584_config_macsec_intr(struct phy_device *phydev)
456{
457}
458#endif
459
460#if IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING)
461void vsc85xx_link_change_notify(struct phy_device *phydev);
462void vsc8584_config_ts_intr(struct phy_device *phydev);
463int vsc8584_ptp_init(struct phy_device *phydev);
464int vsc8584_ptp_probe_once(struct phy_device *phydev);
465int vsc8584_ptp_probe(struct phy_device *phydev);
466irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev);
467#else
468static inline void vsc85xx_link_change_notify(struct phy_device *phydev)
469{
470}
471static inline void vsc8584_config_ts_intr(struct phy_device *phydev)
472{
473}
474static inline int vsc8584_ptp_init(struct phy_device *phydev)
475{
476 return 0;
477}
478static inline int vsc8584_ptp_probe_once(struct phy_device *phydev)
479{
480 return 0;
481}
482static inline int vsc8584_ptp_probe(struct phy_device *phydev)
483{
484 return 0;
485}
486static inline irqreturn_t vsc8584_handle_ts_interrupt(struct phy_device *phydev)
487{
488 return IRQ_NONE;
489}
490#endif
491
492#endif /* _MSCC_PHY_H_ */