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1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010 Micrel, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 * Support : ksz9021 1000/100/10 phy from Micrel
16 * ks8001, ks8737, ks8721, ks8041, ks8051 100/10 phy
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/phy.h>
22#include <linux/micrel_phy.h>
23
24/* general Interrupt control/status reg in vendor specific block. */
25#define MII_KSZPHY_INTCS 0x1B
26#define KSZPHY_INTCS_JABBER (1 << 15)
27#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
28#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
29#define KSZPHY_INTCS_PARELLEL (1 << 12)
30#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
31#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
32#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
33#define KSZPHY_INTCS_LINK_UP (1 << 8)
34#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
35 KSZPHY_INTCS_LINK_DOWN)
36
37/* general PHY control reg in vendor specific block. */
38#define MII_KSZPHY_CTRL 0x1F
39/* bitmap of PHY register to set interrupt mode */
40#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
41#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
42#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
43#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
44
45static int kszphy_ack_interrupt(struct phy_device *phydev)
46{
47 /* bit[7..0] int status, which is a read and clear register. */
48 int rc;
49
50 rc = phy_read(phydev, MII_KSZPHY_INTCS);
51
52 return (rc < 0) ? rc : 0;
53}
54
55static int kszphy_set_interrupt(struct phy_device *phydev)
56{
57 int temp;
58 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
59 KSZPHY_INTCS_ALL : 0;
60 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
61}
62
63static int kszphy_config_intr(struct phy_device *phydev)
64{
65 int temp, rc;
66
67 /* set the interrupt pin active low */
68 temp = phy_read(phydev, MII_KSZPHY_CTRL);
69 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
70 phy_write(phydev, MII_KSZPHY_CTRL, temp);
71 rc = kszphy_set_interrupt(phydev);
72 return rc < 0 ? rc : 0;
73}
74
75static int ksz9021_config_intr(struct phy_device *phydev)
76{
77 int temp, rc;
78
79 /* set the interrupt pin active low */
80 temp = phy_read(phydev, MII_KSZPHY_CTRL);
81 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
82 phy_write(phydev, MII_KSZPHY_CTRL, temp);
83 rc = kszphy_set_interrupt(phydev);
84 return rc < 0 ? rc : 0;
85}
86
87static int ks8737_config_intr(struct phy_device *phydev)
88{
89 int temp, rc;
90
91 /* set the interrupt pin active low */
92 temp = phy_read(phydev, MII_KSZPHY_CTRL);
93 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
94 phy_write(phydev, MII_KSZPHY_CTRL, temp);
95 rc = kszphy_set_interrupt(phydev);
96 return rc < 0 ? rc : 0;
97}
98
99static int kszphy_config_init(struct phy_device *phydev)
100{
101 return 0;
102}
103
104static int ks8051_config_init(struct phy_device *phydev)
105{
106 int regval;
107
108 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
109 regval = phy_read(phydev, MII_KSZPHY_CTRL);
110 regval |= KSZ8051_RMII_50MHZ_CLK;
111 phy_write(phydev, MII_KSZPHY_CTRL, regval);
112 }
113
114 return 0;
115}
116
117static struct phy_driver ks8737_driver = {
118 .phy_id = PHY_ID_KS8737,
119 .phy_id_mask = 0x00fffff0,
120 .name = "Micrel KS8737",
121 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
122 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
123 .config_init = kszphy_config_init,
124 .config_aneg = genphy_config_aneg,
125 .read_status = genphy_read_status,
126 .ack_interrupt = kszphy_ack_interrupt,
127 .config_intr = ks8737_config_intr,
128 .driver = { .owner = THIS_MODULE,},
129};
130
131static struct phy_driver ks8041_driver = {
132 .phy_id = PHY_ID_KS8041,
133 .phy_id_mask = 0x00fffff0,
134 .name = "Micrel KS8041",
135 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
136 | SUPPORTED_Asym_Pause),
137 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
138 .config_init = kszphy_config_init,
139 .config_aneg = genphy_config_aneg,
140 .read_status = genphy_read_status,
141 .ack_interrupt = kszphy_ack_interrupt,
142 .config_intr = kszphy_config_intr,
143 .driver = { .owner = THIS_MODULE,},
144};
145
146static struct phy_driver ks8051_driver = {
147 .phy_id = PHY_ID_KS8051,
148 .phy_id_mask = 0x00fffff0,
149 .name = "Micrel KS8051",
150 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
151 | SUPPORTED_Asym_Pause),
152 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
153 .config_init = ks8051_config_init,
154 .config_aneg = genphy_config_aneg,
155 .read_status = genphy_read_status,
156 .ack_interrupt = kszphy_ack_interrupt,
157 .config_intr = kszphy_config_intr,
158 .driver = { .owner = THIS_MODULE,},
159};
160
161static struct phy_driver ks8001_driver = {
162 .phy_id = PHY_ID_KS8001,
163 .name = "Micrel KS8001 or KS8721",
164 .phy_id_mask = 0x00fffff0,
165 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
166 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
167 .config_init = kszphy_config_init,
168 .config_aneg = genphy_config_aneg,
169 .read_status = genphy_read_status,
170 .ack_interrupt = kszphy_ack_interrupt,
171 .config_intr = kszphy_config_intr,
172 .driver = { .owner = THIS_MODULE,},
173};
174
175static struct phy_driver ksz9021_driver = {
176 .phy_id = PHY_ID_KSZ9021,
177 .phy_id_mask = 0x000fff10,
178 .name = "Micrel KSZ9021 Gigabit PHY",
179 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
180 | SUPPORTED_Asym_Pause),
181 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
182 .config_init = kszphy_config_init,
183 .config_aneg = genphy_config_aneg,
184 .read_status = genphy_read_status,
185 .ack_interrupt = kszphy_ack_interrupt,
186 .config_intr = ksz9021_config_intr,
187 .driver = { .owner = THIS_MODULE, },
188};
189
190static int __init ksphy_init(void)
191{
192 int ret;
193
194 ret = phy_driver_register(&ks8001_driver);
195 if (ret)
196 goto err1;
197
198 ret = phy_driver_register(&ksz9021_driver);
199 if (ret)
200 goto err2;
201
202 ret = phy_driver_register(&ks8737_driver);
203 if (ret)
204 goto err3;
205 ret = phy_driver_register(&ks8041_driver);
206 if (ret)
207 goto err4;
208 ret = phy_driver_register(&ks8051_driver);
209 if (ret)
210 goto err5;
211
212 return 0;
213
214err5:
215 phy_driver_unregister(&ks8041_driver);
216err4:
217 phy_driver_unregister(&ks8737_driver);
218err3:
219 phy_driver_unregister(&ksz9021_driver);
220err2:
221 phy_driver_unregister(&ks8001_driver);
222err1:
223 return ret;
224}
225
226static void __exit ksphy_exit(void)
227{
228 phy_driver_unregister(&ks8001_driver);
229 phy_driver_unregister(&ks8737_driver);
230 phy_driver_unregister(&ksz9021_driver);
231 phy_driver_unregister(&ks8041_driver);
232 phy_driver_unregister(&ks8051_driver);
233}
234
235module_init(ksphy_init);
236module_exit(ksphy_exit);
237
238MODULE_DESCRIPTION("Micrel PHY driver");
239MODULE_AUTHOR("David J. Choi");
240MODULE_LICENSE("GPL");
241
242static struct mdio_device_id __maybe_unused micrel_tbl[] = {
243 { PHY_ID_KSZ9021, 0x000fff10 },
244 { PHY_ID_KS8001, 0x00fffff0 },
245 { PHY_ID_KS8737, 0x00fffff0 },
246 { PHY_ID_KS8041, 0x00fffff0 },
247 { PHY_ID_KS8051, 0x00fffff0 },
248 { }
249};
250
251MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477
20 */
21
22#include <linux/bitfield.h>
23#include <linux/ethtool_netlink.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29#include <linux/clk.h>
30#include <linux/delay.h>
31#include <linux/ptp_clock_kernel.h>
32#include <linux/ptp_clock.h>
33#include <linux/ptp_classify.h>
34#include <linux/net_tstamp.h>
35#include <linux/gpio/consumer.h>
36
37/* Operation Mode Strap Override */
38#define MII_KSZPHY_OMSO 0x16
39#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
40#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
41#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
42#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
43#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
44
45/* general Interrupt control/status reg in vendor specific block. */
46#define MII_KSZPHY_INTCS 0x1B
47#define KSZPHY_INTCS_JABBER BIT(15)
48#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
49#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
50#define KSZPHY_INTCS_PARELLEL BIT(12)
51#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
52#define KSZPHY_INTCS_LINK_DOWN BIT(10)
53#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
54#define KSZPHY_INTCS_LINK_UP BIT(8)
55#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
56 KSZPHY_INTCS_LINK_DOWN)
57#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
58#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
59#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
60 KSZPHY_INTCS_LINK_UP_STATUS)
61
62/* LinkMD Control/Status */
63#define KSZ8081_LMD 0x1d
64#define KSZ8081_LMD_ENABLE_TEST BIT(15)
65#define KSZ8081_LMD_STAT_NORMAL 0
66#define KSZ8081_LMD_STAT_OPEN 1
67#define KSZ8081_LMD_STAT_SHORT 2
68#define KSZ8081_LMD_STAT_FAIL 3
69#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
70/* Short cable (<10 meter) has been detected by LinkMD */
71#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
72#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
73
74#define KSZ9x31_LMD 0x12
75#define KSZ9x31_LMD_VCT_EN BIT(15)
76#define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
77#define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
78#define KSZ9x31_LMD_VCT_SEL_RESULT 0
79#define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
80#define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
81#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
82#define KSZ9x31_LMD_VCT_ST_NORMAL 0
83#define KSZ9x31_LMD_VCT_ST_OPEN 1
84#define KSZ9x31_LMD_VCT_ST_SHORT 2
85#define KSZ9x31_LMD_VCT_ST_FAIL 3
86#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
87#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
88#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
89#define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
90#define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
91#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
92#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
93#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
94
95#define KSZPHY_WIRE_PAIR_MASK 0x3
96
97#define LAN8814_CABLE_DIAG 0x12
98#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
99#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
100#define LAN8814_PAIR_BIT_SHIFT 12
101
102#define LAN8814_WIRE_PAIR_MASK 0xF
103
104/* Lan8814 general Interrupt control/status reg in GPHY specific block. */
105#define LAN8814_INTC 0x18
106#define LAN8814_INTS 0x1B
107
108#define LAN8814_INT_LINK_DOWN BIT(2)
109#define LAN8814_INT_LINK_UP BIT(0)
110#define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
111 LAN8814_INT_LINK_DOWN)
112
113#define LAN8814_INTR_CTRL_REG 0x34
114#define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
115#define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
116
117/* Represents 1ppm adjustment in 2^32 format with
118 * each nsec contains 4 clock cycles.
119 * The value is calculated as following: (1/1000000)/((2^-32)/4)
120 */
121#define LAN8814_1PPM_FORMAT 17179
122
123#define PTP_RX_MOD 0x024F
124#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
125#define PTP_RX_TIMESTAMP_EN 0x024D
126#define PTP_TX_TIMESTAMP_EN 0x028D
127
128#define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
129#define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
130#define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
131#define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
132
133#define PTP_TX_PARSE_L2_ADDR_EN 0x0284
134#define PTP_RX_PARSE_L2_ADDR_EN 0x0244
135
136#define PTP_TX_PARSE_IP_ADDR_EN 0x0285
137#define PTP_RX_PARSE_IP_ADDR_EN 0x0245
138#define LTC_HARD_RESET 0x023F
139#define LTC_HARD_RESET_ BIT(0)
140
141#define TSU_HARD_RESET 0x02C1
142#define TSU_HARD_RESET_ BIT(0)
143
144#define PTP_CMD_CTL 0x0200
145#define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
146#define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
147#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
148#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
149#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
150#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
151
152#define PTP_CLOCK_SET_SEC_MID 0x0206
153#define PTP_CLOCK_SET_SEC_LO 0x0207
154#define PTP_CLOCK_SET_NS_HI 0x0208
155#define PTP_CLOCK_SET_NS_LO 0x0209
156
157#define PTP_CLOCK_READ_SEC_MID 0x022A
158#define PTP_CLOCK_READ_SEC_LO 0x022B
159#define PTP_CLOCK_READ_NS_HI 0x022C
160#define PTP_CLOCK_READ_NS_LO 0x022D
161
162#define PTP_OPERATING_MODE 0x0241
163#define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
164
165#define PTP_TX_MOD 0x028F
166#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
167#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
168
169#define PTP_RX_PARSE_CONFIG 0x0242
170#define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
171#define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
172#define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
173
174#define PTP_TX_PARSE_CONFIG 0x0282
175#define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
176#define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
177#define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
178
179#define PTP_CLOCK_RATE_ADJ_HI 0x020C
180#define PTP_CLOCK_RATE_ADJ_LO 0x020D
181#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
182
183#define PTP_LTC_STEP_ADJ_HI 0x0212
184#define PTP_LTC_STEP_ADJ_LO 0x0213
185#define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
186
187#define LAN8814_INTR_STS_REG 0x0033
188#define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
189#define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
190#define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
191#define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
192
193#define PTP_CAP_INFO 0x022A
194#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
195#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
196
197#define PTP_TX_EGRESS_SEC_HI 0x0296
198#define PTP_TX_EGRESS_SEC_LO 0x0297
199#define PTP_TX_EGRESS_NS_HI 0x0294
200#define PTP_TX_EGRESS_NS_LO 0x0295
201#define PTP_TX_MSG_HEADER2 0x0299
202
203#define PTP_RX_INGRESS_SEC_HI 0x0256
204#define PTP_RX_INGRESS_SEC_LO 0x0257
205#define PTP_RX_INGRESS_NS_HI 0x0254
206#define PTP_RX_INGRESS_NS_LO 0x0255
207#define PTP_RX_MSG_HEADER2 0x0259
208
209#define PTP_TSU_INT_EN 0x0200
210#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
211#define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
212#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
213#define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
214
215#define PTP_TSU_INT_STS 0x0201
216#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
217#define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
218#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
219#define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
220
221#define LAN8814_LED_CTRL_1 0x0
222#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
223
224/* PHY Control 1 */
225#define MII_KSZPHY_CTRL_1 0x1e
226#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
227
228/* PHY Control 2 / PHY Control (if no PHY Control 1) */
229#define MII_KSZPHY_CTRL_2 0x1f
230#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
231/* bitmap of PHY register to set interrupt mode */
232#define KSZ8081_CTRL2_HP_MDIX BIT(15)
233#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
234#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
235#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
236#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
237#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
238#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
239
240/* Write/read to/from extended registers */
241#define MII_KSZPHY_EXTREG 0x0b
242#define KSZPHY_EXTREG_WRITE 0x8000
243
244#define MII_KSZPHY_EXTREG_WRITE 0x0c
245#define MII_KSZPHY_EXTREG_READ 0x0d
246
247/* Extended registers */
248#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
249#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
250#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
251
252#define PS_TO_REG 200
253#define FIFO_SIZE 8
254
255struct kszphy_hw_stat {
256 const char *string;
257 u8 reg;
258 u8 bits;
259};
260
261static struct kszphy_hw_stat kszphy_hw_stats[] = {
262 { "phy_receive_errors", 21, 16},
263 { "phy_idle_errors", 10, 8 },
264};
265
266struct kszphy_type {
267 u32 led_mode_reg;
268 u16 interrupt_level_mask;
269 u16 cable_diag_reg;
270 unsigned long pair_mask;
271 bool has_broadcast_disable;
272 bool has_nand_tree_disable;
273 bool has_rmii_ref_clk_sel;
274};
275
276/* Shared structure between the PHYs of the same package. */
277struct lan8814_shared_priv {
278 struct phy_device *phydev;
279 struct ptp_clock *ptp_clock;
280 struct ptp_clock_info ptp_clock_info;
281
282 /* Reference counter to how many ports in the package are enabling the
283 * timestamping
284 */
285 u8 ref;
286
287 /* Lock for ptp_clock and ref */
288 struct mutex shared_lock;
289};
290
291struct lan8814_ptp_rx_ts {
292 struct list_head list;
293 u32 seconds;
294 u32 nsec;
295 u16 seq_id;
296};
297
298struct kszphy_ptp_priv {
299 struct mii_timestamper mii_ts;
300 struct phy_device *phydev;
301
302 struct sk_buff_head tx_queue;
303 struct sk_buff_head rx_queue;
304
305 struct list_head rx_ts_list;
306 /* Lock for Rx ts fifo */
307 spinlock_t rx_ts_lock;
308
309 int hwts_tx_type;
310 enum hwtstamp_rx_filters rx_filter;
311 int layer;
312 int version;
313};
314
315struct kszphy_priv {
316 struct kszphy_ptp_priv ptp_priv;
317 const struct kszphy_type *type;
318 int led_mode;
319 u16 vct_ctrl1000;
320 bool rmii_ref_clk_sel;
321 bool rmii_ref_clk_sel_val;
322 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
323};
324
325static const struct kszphy_type lan8814_type = {
326 .led_mode_reg = ~LAN8814_LED_CTRL_1,
327 .cable_diag_reg = LAN8814_CABLE_DIAG,
328 .pair_mask = LAN8814_WIRE_PAIR_MASK,
329};
330
331static const struct kszphy_type ksz886x_type = {
332 .cable_diag_reg = KSZ8081_LMD,
333 .pair_mask = KSZPHY_WIRE_PAIR_MASK,
334};
335
336static const struct kszphy_type ksz8021_type = {
337 .led_mode_reg = MII_KSZPHY_CTRL_2,
338 .has_broadcast_disable = true,
339 .has_nand_tree_disable = true,
340 .has_rmii_ref_clk_sel = true,
341};
342
343static const struct kszphy_type ksz8041_type = {
344 .led_mode_reg = MII_KSZPHY_CTRL_1,
345};
346
347static const struct kszphy_type ksz8051_type = {
348 .led_mode_reg = MII_KSZPHY_CTRL_2,
349 .has_nand_tree_disable = true,
350};
351
352static const struct kszphy_type ksz8081_type = {
353 .led_mode_reg = MII_KSZPHY_CTRL_2,
354 .has_broadcast_disable = true,
355 .has_nand_tree_disable = true,
356 .has_rmii_ref_clk_sel = true,
357};
358
359static const struct kszphy_type ks8737_type = {
360 .interrupt_level_mask = BIT(14),
361};
362
363static const struct kszphy_type ksz9021_type = {
364 .interrupt_level_mask = BIT(14),
365};
366
367static int kszphy_extended_write(struct phy_device *phydev,
368 u32 regnum, u16 val)
369{
370 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
371 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
372}
373
374static int kszphy_extended_read(struct phy_device *phydev,
375 u32 regnum)
376{
377 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
378 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
379}
380
381static int kszphy_ack_interrupt(struct phy_device *phydev)
382{
383 /* bit[7..0] int status, which is a read and clear register. */
384 int rc;
385
386 rc = phy_read(phydev, MII_KSZPHY_INTCS);
387
388 return (rc < 0) ? rc : 0;
389}
390
391static int kszphy_config_intr(struct phy_device *phydev)
392{
393 const struct kszphy_type *type = phydev->drv->driver_data;
394 int temp, err;
395 u16 mask;
396
397 if (type && type->interrupt_level_mask)
398 mask = type->interrupt_level_mask;
399 else
400 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
401
402 /* set the interrupt pin active low */
403 temp = phy_read(phydev, MII_KSZPHY_CTRL);
404 if (temp < 0)
405 return temp;
406 temp &= ~mask;
407 phy_write(phydev, MII_KSZPHY_CTRL, temp);
408
409 /* enable / disable interrupts */
410 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
411 err = kszphy_ack_interrupt(phydev);
412 if (err)
413 return err;
414
415 temp = KSZPHY_INTCS_ALL;
416 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
417 } else {
418 temp = 0;
419 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
420 if (err)
421 return err;
422
423 err = kszphy_ack_interrupt(phydev);
424 }
425
426 return err;
427}
428
429static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
430{
431 int irq_status;
432
433 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
434 if (irq_status < 0) {
435 phy_error(phydev);
436 return IRQ_NONE;
437 }
438
439 if (!(irq_status & KSZPHY_INTCS_STATUS))
440 return IRQ_NONE;
441
442 phy_trigger_machine(phydev);
443
444 return IRQ_HANDLED;
445}
446
447static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
448{
449 int ctrl;
450
451 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
452 if (ctrl < 0)
453 return ctrl;
454
455 if (val)
456 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
457 else
458 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
459
460 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
461}
462
463static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
464{
465 int rc, temp, shift;
466
467 switch (reg) {
468 case MII_KSZPHY_CTRL_1:
469 shift = 14;
470 break;
471 case MII_KSZPHY_CTRL_2:
472 shift = 4;
473 break;
474 default:
475 return -EINVAL;
476 }
477
478 temp = phy_read(phydev, reg);
479 if (temp < 0) {
480 rc = temp;
481 goto out;
482 }
483
484 temp &= ~(3 << shift);
485 temp |= val << shift;
486 rc = phy_write(phydev, reg, temp);
487out:
488 if (rc < 0)
489 phydev_err(phydev, "failed to set led mode\n");
490
491 return rc;
492}
493
494/* Disable PHY address 0 as the broadcast address, so that it can be used as a
495 * unique (non-broadcast) address on a shared bus.
496 */
497static int kszphy_broadcast_disable(struct phy_device *phydev)
498{
499 int ret;
500
501 ret = phy_read(phydev, MII_KSZPHY_OMSO);
502 if (ret < 0)
503 goto out;
504
505 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
506out:
507 if (ret)
508 phydev_err(phydev, "failed to disable broadcast address\n");
509
510 return ret;
511}
512
513static int kszphy_nand_tree_disable(struct phy_device *phydev)
514{
515 int ret;
516
517 ret = phy_read(phydev, MII_KSZPHY_OMSO);
518 if (ret < 0)
519 goto out;
520
521 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
522 return 0;
523
524 ret = phy_write(phydev, MII_KSZPHY_OMSO,
525 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
526out:
527 if (ret)
528 phydev_err(phydev, "failed to disable NAND tree mode\n");
529
530 return ret;
531}
532
533/* Some config bits need to be set again on resume, handle them here. */
534static int kszphy_config_reset(struct phy_device *phydev)
535{
536 struct kszphy_priv *priv = phydev->priv;
537 int ret;
538
539 if (priv->rmii_ref_clk_sel) {
540 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
541 if (ret) {
542 phydev_err(phydev,
543 "failed to set rmii reference clock\n");
544 return ret;
545 }
546 }
547
548 if (priv->type && priv->led_mode >= 0)
549 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
550
551 return 0;
552}
553
554static int kszphy_config_init(struct phy_device *phydev)
555{
556 struct kszphy_priv *priv = phydev->priv;
557 const struct kszphy_type *type;
558
559 if (!priv)
560 return 0;
561
562 type = priv->type;
563
564 if (type && type->has_broadcast_disable)
565 kszphy_broadcast_disable(phydev);
566
567 if (type && type->has_nand_tree_disable)
568 kszphy_nand_tree_disable(phydev);
569
570 return kszphy_config_reset(phydev);
571}
572
573static int ksz8041_fiber_mode(struct phy_device *phydev)
574{
575 struct device_node *of_node = phydev->mdio.dev.of_node;
576
577 return of_property_read_bool(of_node, "micrel,fiber-mode");
578}
579
580static int ksz8041_config_init(struct phy_device *phydev)
581{
582 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
583
584 /* Limit supported and advertised modes in fiber mode */
585 if (ksz8041_fiber_mode(phydev)) {
586 phydev->dev_flags |= MICREL_PHY_FXEN;
587 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
588 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
589
590 linkmode_and(phydev->supported, phydev->supported, mask);
591 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
592 phydev->supported);
593 linkmode_and(phydev->advertising, phydev->advertising, mask);
594 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
595 phydev->advertising);
596 phydev->autoneg = AUTONEG_DISABLE;
597 }
598
599 return kszphy_config_init(phydev);
600}
601
602static int ksz8041_config_aneg(struct phy_device *phydev)
603{
604 /* Skip auto-negotiation in fiber mode */
605 if (phydev->dev_flags & MICREL_PHY_FXEN) {
606 phydev->speed = SPEED_100;
607 return 0;
608 }
609
610 return genphy_config_aneg(phydev);
611}
612
613static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
614 const bool ksz_8051)
615{
616 int ret;
617
618 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
619 return 0;
620
621 ret = phy_read(phydev, MII_BMSR);
622 if (ret < 0)
623 return ret;
624
625 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
626 * exact PHY ID. However, they can be told apart by the extended
627 * capability registers presence. The KSZ8051 PHY has them while
628 * the switch does not.
629 */
630 ret &= BMSR_ERCAP;
631 if (ksz_8051)
632 return ret;
633 else
634 return !ret;
635}
636
637static int ksz8051_match_phy_device(struct phy_device *phydev)
638{
639 return ksz8051_ksz8795_match_phy_device(phydev, true);
640}
641
642static int ksz8081_config_init(struct phy_device *phydev)
643{
644 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
645 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
646 * pull-down is missing, the factory test mode should be cleared by
647 * manually writing a 0.
648 */
649 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
650
651 return kszphy_config_init(phydev);
652}
653
654static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
655{
656 u16 val;
657
658 switch (ctrl) {
659 case ETH_TP_MDI:
660 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
661 break;
662 case ETH_TP_MDI_X:
663 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
664 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
665 break;
666 case ETH_TP_MDI_AUTO:
667 val = 0;
668 break;
669 default:
670 return 0;
671 }
672
673 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
674 KSZ8081_CTRL2_HP_MDIX |
675 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
676 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
677 KSZ8081_CTRL2_HP_MDIX | val);
678}
679
680static int ksz8081_config_aneg(struct phy_device *phydev)
681{
682 int ret;
683
684 ret = genphy_config_aneg(phydev);
685 if (ret)
686 return ret;
687
688 /* The MDI-X configuration is automatically changed by the PHY after
689 * switching from autoneg off to on. So, take MDI-X configuration under
690 * own control and set it after autoneg configuration was done.
691 */
692 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
693}
694
695static int ksz8081_mdix_update(struct phy_device *phydev)
696{
697 int ret;
698
699 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
700 if (ret < 0)
701 return ret;
702
703 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
704 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
705 phydev->mdix_ctrl = ETH_TP_MDI_X;
706 else
707 phydev->mdix_ctrl = ETH_TP_MDI;
708 } else {
709 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
710 }
711
712 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
713 if (ret < 0)
714 return ret;
715
716 if (ret & KSZ8081_CTRL1_MDIX_STAT)
717 phydev->mdix = ETH_TP_MDI;
718 else
719 phydev->mdix = ETH_TP_MDI_X;
720
721 return 0;
722}
723
724static int ksz8081_read_status(struct phy_device *phydev)
725{
726 int ret;
727
728 ret = ksz8081_mdix_update(phydev);
729 if (ret < 0)
730 return ret;
731
732 return genphy_read_status(phydev);
733}
734
735static int ksz8061_config_init(struct phy_device *phydev)
736{
737 int ret;
738
739 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
740 if (ret)
741 return ret;
742
743 return kszphy_config_init(phydev);
744}
745
746static int ksz8795_match_phy_device(struct phy_device *phydev)
747{
748 return ksz8051_ksz8795_match_phy_device(phydev, false);
749}
750
751static int ksz9021_load_values_from_of(struct phy_device *phydev,
752 const struct device_node *of_node,
753 u16 reg,
754 const char *field1, const char *field2,
755 const char *field3, const char *field4)
756{
757 int val1 = -1;
758 int val2 = -2;
759 int val3 = -3;
760 int val4 = -4;
761 int newval;
762 int matches = 0;
763
764 if (!of_property_read_u32(of_node, field1, &val1))
765 matches++;
766
767 if (!of_property_read_u32(of_node, field2, &val2))
768 matches++;
769
770 if (!of_property_read_u32(of_node, field3, &val3))
771 matches++;
772
773 if (!of_property_read_u32(of_node, field4, &val4))
774 matches++;
775
776 if (!matches)
777 return 0;
778
779 if (matches < 4)
780 newval = kszphy_extended_read(phydev, reg);
781 else
782 newval = 0;
783
784 if (val1 != -1)
785 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
786
787 if (val2 != -2)
788 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
789
790 if (val3 != -3)
791 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
792
793 if (val4 != -4)
794 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
795
796 return kszphy_extended_write(phydev, reg, newval);
797}
798
799static int ksz9021_config_init(struct phy_device *phydev)
800{
801 const struct device_node *of_node;
802 const struct device *dev_walker;
803
804 /* The Micrel driver has a deprecated option to place phy OF
805 * properties in the MAC node. Walk up the tree of devices to
806 * find a device with an OF node.
807 */
808 dev_walker = &phydev->mdio.dev;
809 do {
810 of_node = dev_walker->of_node;
811 dev_walker = dev_walker->parent;
812
813 } while (!of_node && dev_walker);
814
815 if (of_node) {
816 ksz9021_load_values_from_of(phydev, of_node,
817 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
818 "txen-skew-ps", "txc-skew-ps",
819 "rxdv-skew-ps", "rxc-skew-ps");
820 ksz9021_load_values_from_of(phydev, of_node,
821 MII_KSZPHY_RX_DATA_PAD_SKEW,
822 "rxd0-skew-ps", "rxd1-skew-ps",
823 "rxd2-skew-ps", "rxd3-skew-ps");
824 ksz9021_load_values_from_of(phydev, of_node,
825 MII_KSZPHY_TX_DATA_PAD_SKEW,
826 "txd0-skew-ps", "txd1-skew-ps",
827 "txd2-skew-ps", "txd3-skew-ps");
828 }
829 return 0;
830}
831
832#define KSZ9031_PS_TO_REG 60
833
834/* Extended registers */
835/* MMD Address 0x0 */
836#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
837#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
838
839/* MMD Address 0x2 */
840#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
841#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
842#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
843
844#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
845#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
846#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
847#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
848#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
849
850#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
851#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
852#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
853#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
854#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
855
856#define MII_KSZ9031RN_CLK_PAD_SKEW 8
857#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
858#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
859
860/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
861 * provide different RGMII options we need to configure delay offset
862 * for each pad relative to build in delay.
863 */
864/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
865 * 1.80ns
866 */
867#define RX_ID 0x7
868#define RX_CLK_ID 0x19
869
870/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
871 * internal 1.2ns delay.
872 */
873#define RX_ND 0xc
874#define RX_CLK_ND 0x0
875
876/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
877#define TX_ID 0x0
878#define TX_CLK_ID 0x1f
879
880/* set tx and tx_clk to "No delay adjustment" to keep 0ns
881 * dealy
882 */
883#define TX_ND 0x7
884#define TX_CLK_ND 0xf
885
886/* MMD Address 0x1C */
887#define MII_KSZ9031RN_EDPD 0x23
888#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
889
890static int ksz9031_of_load_skew_values(struct phy_device *phydev,
891 const struct device_node *of_node,
892 u16 reg, size_t field_sz,
893 const char *field[], u8 numfields,
894 bool *update)
895{
896 int val[4] = {-1, -2, -3, -4};
897 int matches = 0;
898 u16 mask;
899 u16 maxval;
900 u16 newval;
901 int i;
902
903 for (i = 0; i < numfields; i++)
904 if (!of_property_read_u32(of_node, field[i], val + i))
905 matches++;
906
907 if (!matches)
908 return 0;
909
910 *update |= true;
911
912 if (matches < numfields)
913 newval = phy_read_mmd(phydev, 2, reg);
914 else
915 newval = 0;
916
917 maxval = (field_sz == 4) ? 0xf : 0x1f;
918 for (i = 0; i < numfields; i++)
919 if (val[i] != -(i + 1)) {
920 mask = 0xffff;
921 mask ^= maxval << (field_sz * i);
922 newval = (newval & mask) |
923 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
924 << (field_sz * i));
925 }
926
927 return phy_write_mmd(phydev, 2, reg, newval);
928}
929
930/* Center KSZ9031RNX FLP timing at 16ms. */
931static int ksz9031_center_flp_timing(struct phy_device *phydev)
932{
933 int result;
934
935 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
936 0x0006);
937 if (result)
938 return result;
939
940 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
941 0x1A80);
942 if (result)
943 return result;
944
945 return genphy_restart_aneg(phydev);
946}
947
948/* Enable energy-detect power-down mode */
949static int ksz9031_enable_edpd(struct phy_device *phydev)
950{
951 int reg;
952
953 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
954 if (reg < 0)
955 return reg;
956 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
957 reg | MII_KSZ9031RN_EDPD_ENABLE);
958}
959
960static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
961{
962 u16 rx, tx, rx_clk, tx_clk;
963 int ret;
964
965 switch (phydev->interface) {
966 case PHY_INTERFACE_MODE_RGMII:
967 tx = TX_ND;
968 tx_clk = TX_CLK_ND;
969 rx = RX_ND;
970 rx_clk = RX_CLK_ND;
971 break;
972 case PHY_INTERFACE_MODE_RGMII_ID:
973 tx = TX_ID;
974 tx_clk = TX_CLK_ID;
975 rx = RX_ID;
976 rx_clk = RX_CLK_ID;
977 break;
978 case PHY_INTERFACE_MODE_RGMII_RXID:
979 tx = TX_ND;
980 tx_clk = TX_CLK_ND;
981 rx = RX_ID;
982 rx_clk = RX_CLK_ID;
983 break;
984 case PHY_INTERFACE_MODE_RGMII_TXID:
985 tx = TX_ID;
986 tx_clk = TX_CLK_ID;
987 rx = RX_ND;
988 rx_clk = RX_CLK_ND;
989 break;
990 default:
991 return 0;
992 }
993
994 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
995 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
996 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
997 if (ret < 0)
998 return ret;
999
1000 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1001 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1002 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1003 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1004 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1005 if (ret < 0)
1006 return ret;
1007
1008 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1009 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1010 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1011 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1012 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1013 if (ret < 0)
1014 return ret;
1015
1016 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1017 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1018 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1019}
1020
1021static int ksz9031_config_init(struct phy_device *phydev)
1022{
1023 const struct device_node *of_node;
1024 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1025 static const char *rx_data_skews[4] = {
1026 "rxd0-skew-ps", "rxd1-skew-ps",
1027 "rxd2-skew-ps", "rxd3-skew-ps"
1028 };
1029 static const char *tx_data_skews[4] = {
1030 "txd0-skew-ps", "txd1-skew-ps",
1031 "txd2-skew-ps", "txd3-skew-ps"
1032 };
1033 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1034 const struct device *dev_walker;
1035 int result;
1036
1037 result = ksz9031_enable_edpd(phydev);
1038 if (result < 0)
1039 return result;
1040
1041 /* The Micrel driver has a deprecated option to place phy OF
1042 * properties in the MAC node. Walk up the tree of devices to
1043 * find a device with an OF node.
1044 */
1045 dev_walker = &phydev->mdio.dev;
1046 do {
1047 of_node = dev_walker->of_node;
1048 dev_walker = dev_walker->parent;
1049 } while (!of_node && dev_walker);
1050
1051 if (of_node) {
1052 bool update = false;
1053
1054 if (phy_interface_is_rgmii(phydev)) {
1055 result = ksz9031_config_rgmii_delay(phydev);
1056 if (result < 0)
1057 return result;
1058 }
1059
1060 ksz9031_of_load_skew_values(phydev, of_node,
1061 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1062 clk_skews, 2, &update);
1063
1064 ksz9031_of_load_skew_values(phydev, of_node,
1065 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1066 control_skews, 2, &update);
1067
1068 ksz9031_of_load_skew_values(phydev, of_node,
1069 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1070 rx_data_skews, 4, &update);
1071
1072 ksz9031_of_load_skew_values(phydev, of_node,
1073 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1074 tx_data_skews, 4, &update);
1075
1076 if (update && !phy_interface_is_rgmii(phydev))
1077 phydev_warn(phydev,
1078 "*-skew-ps values should be used only with RGMII PHY modes\n");
1079
1080 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1081 * When the device links in the 1000BASE-T slave mode only,
1082 * the optional 125MHz reference output clock (CLK125_NDO)
1083 * has wide duty cycle variation.
1084 *
1085 * The optional CLK125_NDO clock does not meet the RGMII
1086 * 45/55 percent (min/max) duty cycle requirement and therefore
1087 * cannot be used directly by the MAC side for clocking
1088 * applications that have setup/hold time requirements on
1089 * rising and falling clock edges.
1090 *
1091 * Workaround:
1092 * Force the phy to be the master to receive a stable clock
1093 * which meets the duty cycle requirement.
1094 */
1095 if (of_property_read_bool(of_node, "micrel,force-master")) {
1096 result = phy_read(phydev, MII_CTRL1000);
1097 if (result < 0)
1098 goto err_force_master;
1099
1100 /* enable master mode, config & prefer master */
1101 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1102 result = phy_write(phydev, MII_CTRL1000, result);
1103 if (result < 0)
1104 goto err_force_master;
1105 }
1106 }
1107
1108 return ksz9031_center_flp_timing(phydev);
1109
1110err_force_master:
1111 phydev_err(phydev, "failed to force the phy to master mode\n");
1112 return result;
1113}
1114
1115#define KSZ9131_SKEW_5BIT_MAX 2400
1116#define KSZ9131_SKEW_4BIT_MAX 800
1117#define KSZ9131_OFFSET 700
1118#define KSZ9131_STEP 100
1119
1120static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1121 struct device_node *of_node,
1122 u16 reg, size_t field_sz,
1123 char *field[], u8 numfields)
1124{
1125 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1126 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1127 int skewval, skewmax = 0;
1128 int matches = 0;
1129 u16 maxval;
1130 u16 newval;
1131 u16 mask;
1132 int i;
1133
1134 /* psec properties in dts should mean x pico seconds */
1135 if (field_sz == 5)
1136 skewmax = KSZ9131_SKEW_5BIT_MAX;
1137 else
1138 skewmax = KSZ9131_SKEW_4BIT_MAX;
1139
1140 for (i = 0; i < numfields; i++)
1141 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1142 if (skewval < -KSZ9131_OFFSET)
1143 skewval = -KSZ9131_OFFSET;
1144 else if (skewval > skewmax)
1145 skewval = skewmax;
1146
1147 val[i] = skewval + KSZ9131_OFFSET;
1148 matches++;
1149 }
1150
1151 if (!matches)
1152 return 0;
1153
1154 if (matches < numfields)
1155 newval = phy_read_mmd(phydev, 2, reg);
1156 else
1157 newval = 0;
1158
1159 maxval = (field_sz == 4) ? 0xf : 0x1f;
1160 for (i = 0; i < numfields; i++)
1161 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1162 mask = 0xffff;
1163 mask ^= maxval << (field_sz * i);
1164 newval = (newval & mask) |
1165 (((val[i] / KSZ9131_STEP) & maxval)
1166 << (field_sz * i));
1167 }
1168
1169 return phy_write_mmd(phydev, 2, reg, newval);
1170}
1171
1172#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1173#define KSZ9131RN_RXC_DLL_CTRL 76
1174#define KSZ9131RN_TXC_DLL_CTRL 77
1175#define KSZ9131RN_DLL_CTRL_BYPASS BIT_MASK(12)
1176#define KSZ9131RN_DLL_ENABLE_DELAY 0
1177#define KSZ9131RN_DLL_DISABLE_DELAY BIT(12)
1178
1179static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1180{
1181 u16 rxcdll_val, txcdll_val;
1182 int ret;
1183
1184 switch (phydev->interface) {
1185 case PHY_INTERFACE_MODE_RGMII:
1186 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1187 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1188 break;
1189 case PHY_INTERFACE_MODE_RGMII_ID:
1190 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1191 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1192 break;
1193 case PHY_INTERFACE_MODE_RGMII_RXID:
1194 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1195 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1196 break;
1197 case PHY_INTERFACE_MODE_RGMII_TXID:
1198 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1199 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1200 break;
1201 default:
1202 return 0;
1203 }
1204
1205 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1206 KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1207 rxcdll_val);
1208 if (ret < 0)
1209 return ret;
1210
1211 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1212 KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1213 txcdll_val);
1214}
1215
1216/* Silicon Errata DS80000693B
1217 *
1218 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1219 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1220 * according to the datasheet (off if there is no link).
1221 */
1222static int ksz9131_led_errata(struct phy_device *phydev)
1223{
1224 int reg;
1225
1226 reg = phy_read_mmd(phydev, 2, 0);
1227 if (reg < 0)
1228 return reg;
1229
1230 if (!(reg & BIT(4)))
1231 return 0;
1232
1233 return phy_set_bits(phydev, 0x1e, BIT(9));
1234}
1235
1236static int ksz9131_config_init(struct phy_device *phydev)
1237{
1238 struct device_node *of_node;
1239 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1240 char *rx_data_skews[4] = {
1241 "rxd0-skew-psec", "rxd1-skew-psec",
1242 "rxd2-skew-psec", "rxd3-skew-psec"
1243 };
1244 char *tx_data_skews[4] = {
1245 "txd0-skew-psec", "txd1-skew-psec",
1246 "txd2-skew-psec", "txd3-skew-psec"
1247 };
1248 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1249 const struct device *dev_walker;
1250 int ret;
1251
1252 dev_walker = &phydev->mdio.dev;
1253 do {
1254 of_node = dev_walker->of_node;
1255 dev_walker = dev_walker->parent;
1256 } while (!of_node && dev_walker);
1257
1258 if (!of_node)
1259 return 0;
1260
1261 if (phy_interface_is_rgmii(phydev)) {
1262 ret = ksz9131_config_rgmii_delay(phydev);
1263 if (ret < 0)
1264 return ret;
1265 }
1266
1267 ret = ksz9131_of_load_skew_values(phydev, of_node,
1268 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1269 clk_skews, 2);
1270 if (ret < 0)
1271 return ret;
1272
1273 ret = ksz9131_of_load_skew_values(phydev, of_node,
1274 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1275 control_skews, 2);
1276 if (ret < 0)
1277 return ret;
1278
1279 ret = ksz9131_of_load_skew_values(phydev, of_node,
1280 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1281 rx_data_skews, 4);
1282 if (ret < 0)
1283 return ret;
1284
1285 ret = ksz9131_of_load_skew_values(phydev, of_node,
1286 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1287 tx_data_skews, 4);
1288 if (ret < 0)
1289 return ret;
1290
1291 ret = ksz9131_led_errata(phydev);
1292 if (ret < 0)
1293 return ret;
1294
1295 return 0;
1296}
1297
1298#define MII_KSZ9131_AUTO_MDIX 0x1C
1299#define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1300#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1301
1302static int ksz9131_mdix_update(struct phy_device *phydev)
1303{
1304 int ret;
1305
1306 ret = phy_read(phydev, MII_KSZ9131_AUTO_MDIX);
1307 if (ret < 0)
1308 return ret;
1309
1310 if (ret & MII_KSZ9131_AUTO_MDIX_SWAP_OFF) {
1311 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1312 phydev->mdix_ctrl = ETH_TP_MDI;
1313 else
1314 phydev->mdix_ctrl = ETH_TP_MDI_X;
1315 } else {
1316 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1317 }
1318
1319 if (ret & MII_KSZ9131_AUTO_MDI_SET)
1320 phydev->mdix = ETH_TP_MDI;
1321 else
1322 phydev->mdix = ETH_TP_MDI_X;
1323
1324 return 0;
1325}
1326
1327static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1328{
1329 u16 val;
1330
1331 switch (ctrl) {
1332 case ETH_TP_MDI:
1333 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1334 MII_KSZ9131_AUTO_MDI_SET;
1335 break;
1336 case ETH_TP_MDI_X:
1337 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1338 break;
1339 case ETH_TP_MDI_AUTO:
1340 val = 0;
1341 break;
1342 default:
1343 return 0;
1344 }
1345
1346 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1347 MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1348 MII_KSZ9131_AUTO_MDI_SET, val);
1349}
1350
1351static int ksz9131_read_status(struct phy_device *phydev)
1352{
1353 int ret;
1354
1355 ret = ksz9131_mdix_update(phydev);
1356 if (ret < 0)
1357 return ret;
1358
1359 return genphy_read_status(phydev);
1360}
1361
1362static int ksz9131_config_aneg(struct phy_device *phydev)
1363{
1364 int ret;
1365
1366 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1367 if (ret)
1368 return ret;
1369
1370 return genphy_config_aneg(phydev);
1371}
1372
1373#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1374#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1375#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1376static int ksz8873mll_read_status(struct phy_device *phydev)
1377{
1378 int regval;
1379
1380 /* dummy read */
1381 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1382
1383 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1384
1385 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1386 phydev->duplex = DUPLEX_HALF;
1387 else
1388 phydev->duplex = DUPLEX_FULL;
1389
1390 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1391 phydev->speed = SPEED_10;
1392 else
1393 phydev->speed = SPEED_100;
1394
1395 phydev->link = 1;
1396 phydev->pause = phydev->asym_pause = 0;
1397
1398 return 0;
1399}
1400
1401static int ksz9031_get_features(struct phy_device *phydev)
1402{
1403 int ret;
1404
1405 ret = genphy_read_abilities(phydev);
1406 if (ret < 0)
1407 return ret;
1408
1409 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1410 * Whenever the device's Asymmetric Pause capability is set to 1,
1411 * link-up may fail after a link-up to link-down transition.
1412 *
1413 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1414 *
1415 * Workaround:
1416 * Do not enable the Asymmetric Pause capability bit.
1417 */
1418 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1419
1420 /* We force setting the Pause capability as the core will force the
1421 * Asymmetric Pause capability to 1 otherwise.
1422 */
1423 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1424
1425 return 0;
1426}
1427
1428static int ksz9031_read_status(struct phy_device *phydev)
1429{
1430 int err;
1431 int regval;
1432
1433 err = genphy_read_status(phydev);
1434 if (err)
1435 return err;
1436
1437 /* Make sure the PHY is not broken. Read idle error count,
1438 * and reset the PHY if it is maxed out.
1439 */
1440 regval = phy_read(phydev, MII_STAT1000);
1441 if ((regval & 0xFF) == 0xFF) {
1442 phy_init_hw(phydev);
1443 phydev->link = 0;
1444 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1445 phydev->drv->config_intr(phydev);
1446 return genphy_config_aneg(phydev);
1447 }
1448
1449 return 0;
1450}
1451
1452static int ksz9x31_cable_test_start(struct phy_device *phydev)
1453{
1454 struct kszphy_priv *priv = phydev->priv;
1455 int ret;
1456
1457 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1458 * Prior to running the cable diagnostics, Auto-negotiation should
1459 * be disabled, full duplex set and the link speed set to 1000Mbps
1460 * via the Basic Control Register.
1461 */
1462 ret = phy_modify(phydev, MII_BMCR,
1463 BMCR_SPEED1000 | BMCR_FULLDPLX |
1464 BMCR_ANENABLE | BMCR_SPEED100,
1465 BMCR_SPEED1000 | BMCR_FULLDPLX);
1466 if (ret)
1467 return ret;
1468
1469 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1470 * The Master-Slave configuration should be set to Slave by writing
1471 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1472 * Register.
1473 */
1474 ret = phy_read(phydev, MII_CTRL1000);
1475 if (ret < 0)
1476 return ret;
1477
1478 /* Cache these bits, they need to be restored once LinkMD finishes. */
1479 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1480 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1481 ret |= CTL1000_ENABLE_MASTER;
1482
1483 return phy_write(phydev, MII_CTRL1000, ret);
1484}
1485
1486static int ksz9x31_cable_test_result_trans(u16 status)
1487{
1488 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1489 case KSZ9x31_LMD_VCT_ST_NORMAL:
1490 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1491 case KSZ9x31_LMD_VCT_ST_OPEN:
1492 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1493 case KSZ9x31_LMD_VCT_ST_SHORT:
1494 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1495 case KSZ9x31_LMD_VCT_ST_FAIL:
1496 fallthrough;
1497 default:
1498 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1499 }
1500}
1501
1502static bool ksz9x31_cable_test_failed(u16 status)
1503{
1504 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1505
1506 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1507}
1508
1509static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1510{
1511 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1512 case KSZ9x31_LMD_VCT_ST_OPEN:
1513 fallthrough;
1514 case KSZ9x31_LMD_VCT_ST_SHORT:
1515 return true;
1516 }
1517 return false;
1518}
1519
1520static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1521{
1522 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1523
1524 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1525 *
1526 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1527 */
1528 if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131)
1529 dt = clamp(dt - 22, 0, 255);
1530
1531 return (dt * 400) / 10;
1532}
1533
1534static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1535{
1536 int val, ret;
1537
1538 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1539 !(val & KSZ9x31_LMD_VCT_EN),
1540 30000, 100000, true);
1541
1542 return ret < 0 ? ret : 0;
1543}
1544
1545static int ksz9x31_cable_test_get_pair(int pair)
1546{
1547 static const int ethtool_pair[] = {
1548 ETHTOOL_A_CABLE_PAIR_A,
1549 ETHTOOL_A_CABLE_PAIR_B,
1550 ETHTOOL_A_CABLE_PAIR_C,
1551 ETHTOOL_A_CABLE_PAIR_D,
1552 };
1553
1554 return ethtool_pair[pair];
1555}
1556
1557static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1558{
1559 int ret, val;
1560
1561 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1562 * To test each individual cable pair, set the cable pair in the Cable
1563 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1564 * Diagnostic Register, along with setting the Cable Diagnostics Test
1565 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1566 * will self clear when the test is concluded.
1567 */
1568 ret = phy_write(phydev, KSZ9x31_LMD,
1569 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1570 if (ret)
1571 return ret;
1572
1573 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1574 if (ret)
1575 return ret;
1576
1577 val = phy_read(phydev, KSZ9x31_LMD);
1578 if (val < 0)
1579 return val;
1580
1581 if (ksz9x31_cable_test_failed(val))
1582 return -EAGAIN;
1583
1584 ret = ethnl_cable_test_result(phydev,
1585 ksz9x31_cable_test_get_pair(pair),
1586 ksz9x31_cable_test_result_trans(val));
1587 if (ret)
1588 return ret;
1589
1590 if (!ksz9x31_cable_test_fault_length_valid(val))
1591 return 0;
1592
1593 return ethnl_cable_test_fault_length(phydev,
1594 ksz9x31_cable_test_get_pair(pair),
1595 ksz9x31_cable_test_fault_length(phydev, val));
1596}
1597
1598static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1599 bool *finished)
1600{
1601 struct kszphy_priv *priv = phydev->priv;
1602 unsigned long pair_mask = 0xf;
1603 int retries = 20;
1604 int pair, ret, rv;
1605
1606 *finished = false;
1607
1608 /* Try harder if link partner is active */
1609 while (pair_mask && retries--) {
1610 for_each_set_bit(pair, &pair_mask, 4) {
1611 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1612 if (ret == -EAGAIN)
1613 continue;
1614 if (ret < 0)
1615 return ret;
1616 clear_bit(pair, &pair_mask);
1617 }
1618 /* If link partner is in autonegotiation mode it will send 2ms
1619 * of FLPs with at least 6ms of silence.
1620 * Add 2ms sleep to have better chances to hit this silence.
1621 */
1622 if (pair_mask)
1623 usleep_range(2000, 3000);
1624 }
1625
1626 /* Report remaining unfinished pair result as unknown. */
1627 for_each_set_bit(pair, &pair_mask, 4) {
1628 ret = ethnl_cable_test_result(phydev,
1629 ksz9x31_cable_test_get_pair(pair),
1630 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1631 }
1632
1633 *finished = true;
1634
1635 /* Restore cached bits from before LinkMD got started. */
1636 rv = phy_modify(phydev, MII_CTRL1000,
1637 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1638 priv->vct_ctrl1000);
1639 if (rv)
1640 return rv;
1641
1642 return ret;
1643}
1644
1645static int ksz8873mll_config_aneg(struct phy_device *phydev)
1646{
1647 return 0;
1648}
1649
1650static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1651{
1652 u16 val;
1653
1654 switch (ctrl) {
1655 case ETH_TP_MDI:
1656 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1657 break;
1658 case ETH_TP_MDI_X:
1659 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1660 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1661 * sheet seems to be missing:
1662 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1663 * 0 = Normal operation (transmit on TX+/TX- pins)
1664 */
1665 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1666 break;
1667 case ETH_TP_MDI_AUTO:
1668 val = 0;
1669 break;
1670 default:
1671 return 0;
1672 }
1673
1674 return phy_modify(phydev, MII_BMCR,
1675 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1676 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1677 KSZ886X_BMCR_HP_MDIX | val);
1678}
1679
1680static int ksz886x_config_aneg(struct phy_device *phydev)
1681{
1682 int ret;
1683
1684 ret = genphy_config_aneg(phydev);
1685 if (ret)
1686 return ret;
1687
1688 /* The MDI-X configuration is automatically changed by the PHY after
1689 * switching from autoneg off to on. So, take MDI-X configuration under
1690 * own control and set it after autoneg configuration was done.
1691 */
1692 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1693}
1694
1695static int ksz886x_mdix_update(struct phy_device *phydev)
1696{
1697 int ret;
1698
1699 ret = phy_read(phydev, MII_BMCR);
1700 if (ret < 0)
1701 return ret;
1702
1703 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1704 if (ret & KSZ886X_BMCR_FORCE_MDI)
1705 phydev->mdix_ctrl = ETH_TP_MDI_X;
1706 else
1707 phydev->mdix_ctrl = ETH_TP_MDI;
1708 } else {
1709 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1710 }
1711
1712 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1713 if (ret < 0)
1714 return ret;
1715
1716 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1717 if (ret & KSZ886X_CTRL_MDIX_STAT)
1718 phydev->mdix = ETH_TP_MDI_X;
1719 else
1720 phydev->mdix = ETH_TP_MDI;
1721
1722 return 0;
1723}
1724
1725static int ksz886x_read_status(struct phy_device *phydev)
1726{
1727 int ret;
1728
1729 ret = ksz886x_mdix_update(phydev);
1730 if (ret < 0)
1731 return ret;
1732
1733 return genphy_read_status(phydev);
1734}
1735
1736static int kszphy_get_sset_count(struct phy_device *phydev)
1737{
1738 return ARRAY_SIZE(kszphy_hw_stats);
1739}
1740
1741static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1742{
1743 int i;
1744
1745 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1746 strscpy(data + i * ETH_GSTRING_LEN,
1747 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1748 }
1749}
1750
1751static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1752{
1753 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1754 struct kszphy_priv *priv = phydev->priv;
1755 int val;
1756 u64 ret;
1757
1758 val = phy_read(phydev, stat.reg);
1759 if (val < 0) {
1760 ret = U64_MAX;
1761 } else {
1762 val = val & ((1 << stat.bits) - 1);
1763 priv->stats[i] += val;
1764 ret = priv->stats[i];
1765 }
1766
1767 return ret;
1768}
1769
1770static void kszphy_get_stats(struct phy_device *phydev,
1771 struct ethtool_stats *stats, u64 *data)
1772{
1773 int i;
1774
1775 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1776 data[i] = kszphy_get_stat(phydev, i);
1777}
1778
1779static int kszphy_suspend(struct phy_device *phydev)
1780{
1781 /* Disable PHY Interrupts */
1782 if (phy_interrupt_is_valid(phydev)) {
1783 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1784 if (phydev->drv->config_intr)
1785 phydev->drv->config_intr(phydev);
1786 }
1787
1788 return genphy_suspend(phydev);
1789}
1790
1791static void kszphy_parse_led_mode(struct phy_device *phydev)
1792{
1793 const struct kszphy_type *type = phydev->drv->driver_data;
1794 const struct device_node *np = phydev->mdio.dev.of_node;
1795 struct kszphy_priv *priv = phydev->priv;
1796 int ret;
1797
1798 if (type && type->led_mode_reg) {
1799 ret = of_property_read_u32(np, "micrel,led-mode",
1800 &priv->led_mode);
1801
1802 if (ret)
1803 priv->led_mode = -1;
1804
1805 if (priv->led_mode > 3) {
1806 phydev_err(phydev, "invalid led mode: 0x%02x\n",
1807 priv->led_mode);
1808 priv->led_mode = -1;
1809 }
1810 } else {
1811 priv->led_mode = -1;
1812 }
1813}
1814
1815static int kszphy_resume(struct phy_device *phydev)
1816{
1817 int ret;
1818
1819 genphy_resume(phydev);
1820
1821 /* After switching from power-down to normal mode, an internal global
1822 * reset is automatically generated. Wait a minimum of 1 ms before
1823 * read/write access to the PHY registers.
1824 */
1825 usleep_range(1000, 2000);
1826
1827 ret = kszphy_config_reset(phydev);
1828 if (ret)
1829 return ret;
1830
1831 /* Enable PHY Interrupts */
1832 if (phy_interrupt_is_valid(phydev)) {
1833 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1834 if (phydev->drv->config_intr)
1835 phydev->drv->config_intr(phydev);
1836 }
1837
1838 return 0;
1839}
1840
1841static int kszphy_probe(struct phy_device *phydev)
1842{
1843 const struct kszphy_type *type = phydev->drv->driver_data;
1844 const struct device_node *np = phydev->mdio.dev.of_node;
1845 struct kszphy_priv *priv;
1846 struct clk *clk;
1847
1848 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1849 if (!priv)
1850 return -ENOMEM;
1851
1852 phydev->priv = priv;
1853
1854 priv->type = type;
1855
1856 kszphy_parse_led_mode(phydev);
1857
1858 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1859 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1860 if (!IS_ERR_OR_NULL(clk)) {
1861 unsigned long rate = clk_get_rate(clk);
1862 bool rmii_ref_clk_sel_25_mhz;
1863
1864 if (type)
1865 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1866 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1867 "micrel,rmii-reference-clock-select-25-mhz");
1868
1869 if (rate > 24500000 && rate < 25500000) {
1870 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1871 } else if (rate > 49500000 && rate < 50500000) {
1872 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1873 } else {
1874 phydev_err(phydev, "Clock rate out of range: %ld\n",
1875 rate);
1876 return -EINVAL;
1877 }
1878 }
1879
1880 if (ksz8041_fiber_mode(phydev))
1881 phydev->port = PORT_FIBRE;
1882
1883 /* Support legacy board-file configuration */
1884 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1885 priv->rmii_ref_clk_sel = true;
1886 priv->rmii_ref_clk_sel_val = true;
1887 }
1888
1889 return 0;
1890}
1891
1892static int lan8814_cable_test_start(struct phy_device *phydev)
1893{
1894 /* If autoneg is enabled, we won't be able to test cross pair
1895 * short. In this case, the PHY will "detect" a link and
1896 * confuse the internal state machine - disable auto neg here.
1897 * Set the speed to 1000mbit and full duplex.
1898 */
1899 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
1900 BMCR_SPEED1000 | BMCR_FULLDPLX);
1901}
1902
1903static int ksz886x_cable_test_start(struct phy_device *phydev)
1904{
1905 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1906 return -EOPNOTSUPP;
1907
1908 /* If autoneg is enabled, we won't be able to test cross pair
1909 * short. In this case, the PHY will "detect" a link and
1910 * confuse the internal state machine - disable auto neg here.
1911 * If autoneg is disabled, we should set the speed to 10mbit.
1912 */
1913 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1914}
1915
1916static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
1917{
1918 switch (FIELD_GET(mask, status)) {
1919 case KSZ8081_LMD_STAT_NORMAL:
1920 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1921 case KSZ8081_LMD_STAT_SHORT:
1922 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1923 case KSZ8081_LMD_STAT_OPEN:
1924 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1925 case KSZ8081_LMD_STAT_FAIL:
1926 fallthrough;
1927 default:
1928 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1929 }
1930}
1931
1932static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
1933{
1934 return FIELD_GET(mask, status) ==
1935 KSZ8081_LMD_STAT_FAIL;
1936}
1937
1938static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
1939{
1940 switch (FIELD_GET(mask, status)) {
1941 case KSZ8081_LMD_STAT_OPEN:
1942 fallthrough;
1943 case KSZ8081_LMD_STAT_SHORT:
1944 return true;
1945 }
1946 return false;
1947}
1948
1949static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
1950 u16 status, u16 data_mask)
1951{
1952 int dt;
1953
1954 /* According to the data sheet the distance to the fault is
1955 * DELTA_TIME * 0.4 meters for ksz phys.
1956 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
1957 */
1958 dt = FIELD_GET(data_mask, status);
1959
1960 if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_LAN8814)
1961 return ((dt - 22) * 800) / 10;
1962 else
1963 return (dt * 400) / 10;
1964}
1965
1966static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1967{
1968 const struct kszphy_type *type = phydev->drv->driver_data;
1969 int val, ret;
1970
1971 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
1972 !(val & KSZ8081_LMD_ENABLE_TEST),
1973 30000, 100000, true);
1974
1975 return ret < 0 ? ret : 0;
1976}
1977
1978static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
1979{
1980 static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
1981 ETHTOOL_A_CABLE_PAIR_B,
1982 ETHTOOL_A_CABLE_PAIR_C,
1983 ETHTOOL_A_CABLE_PAIR_D,
1984 };
1985 u32 fault_length;
1986 int ret;
1987 int val;
1988
1989 val = KSZ8081_LMD_ENABLE_TEST;
1990 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
1991
1992 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
1993 if (ret < 0)
1994 return ret;
1995
1996 ret = ksz886x_cable_test_wait_for_completion(phydev);
1997 if (ret)
1998 return ret;
1999
2000 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2001 if (val < 0)
2002 return val;
2003
2004 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2005 return -EAGAIN;
2006
2007 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2008 ksz886x_cable_test_result_trans(val,
2009 LAN8814_CABLE_DIAG_STAT_MASK
2010 ));
2011 if (ret)
2012 return ret;
2013
2014 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2015 return 0;
2016
2017 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2018 LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2019
2020 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2021}
2022
2023static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2024{
2025 static const int ethtool_pair[] = {
2026 ETHTOOL_A_CABLE_PAIR_A,
2027 ETHTOOL_A_CABLE_PAIR_B,
2028 };
2029 int ret, val, mdix;
2030 u32 fault_length;
2031
2032 /* There is no way to choice the pair, like we do one ksz9031.
2033 * We can workaround this limitation by using the MDI-X functionality.
2034 */
2035 if (pair == 0)
2036 mdix = ETH_TP_MDI;
2037 else
2038 mdix = ETH_TP_MDI_X;
2039
2040 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2041 case PHY_ID_KSZ8081:
2042 ret = ksz8081_config_mdix(phydev, mdix);
2043 break;
2044 case PHY_ID_KSZ886X:
2045 ret = ksz886x_config_mdix(phydev, mdix);
2046 break;
2047 default:
2048 ret = -ENODEV;
2049 }
2050
2051 if (ret)
2052 return ret;
2053
2054 /* Now we are ready to fire. This command will send a 100ns pulse
2055 * to the pair.
2056 */
2057 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2058 if (ret)
2059 return ret;
2060
2061 ret = ksz886x_cable_test_wait_for_completion(phydev);
2062 if (ret)
2063 return ret;
2064
2065 val = phy_read(phydev, KSZ8081_LMD);
2066 if (val < 0)
2067 return val;
2068
2069 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2070 return -EAGAIN;
2071
2072 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2073 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2074 if (ret)
2075 return ret;
2076
2077 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2078 return 0;
2079
2080 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2081
2082 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2083}
2084
2085static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2086 bool *finished)
2087{
2088 const struct kszphy_type *type = phydev->drv->driver_data;
2089 unsigned long pair_mask = type->pair_mask;
2090 int retries = 20;
2091 int pair, ret;
2092
2093 *finished = false;
2094
2095 /* Try harder if link partner is active */
2096 while (pair_mask && retries--) {
2097 for_each_set_bit(pair, &pair_mask, 4) {
2098 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2099 ret = lan8814_cable_test_one_pair(phydev, pair);
2100 else
2101 ret = ksz886x_cable_test_one_pair(phydev, pair);
2102 if (ret == -EAGAIN)
2103 continue;
2104 if (ret < 0)
2105 return ret;
2106 clear_bit(pair, &pair_mask);
2107 }
2108 /* If link partner is in autonegotiation mode it will send 2ms
2109 * of FLPs with at least 6ms of silence.
2110 * Add 2ms sleep to have better chances to hit this silence.
2111 */
2112 if (pair_mask)
2113 msleep(2);
2114 }
2115
2116 *finished = true;
2117
2118 return ret;
2119}
2120
2121#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2122#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2123#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2124
2125#define LAN8814_QSGMII_SOFT_RESET 0x43
2126#define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2127#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2128#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2129#define LAN8814_ALIGN_SWAP 0x4a
2130#define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2131#define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2132
2133#define LAN8804_ALIGN_SWAP 0x4a
2134#define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2135#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2136#define LAN8814_CLOCK_MANAGEMENT 0xd
2137#define LAN8814_LINK_QUALITY 0x8e
2138
2139static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2140{
2141 int data;
2142
2143 phy_lock_mdio_bus(phydev);
2144 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2145 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2146 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2147 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2148 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2149 phy_unlock_mdio_bus(phydev);
2150
2151 return data;
2152}
2153
2154static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2155 u16 val)
2156{
2157 phy_lock_mdio_bus(phydev);
2158 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2159 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2160 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2161 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2162
2163 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2164 if (val != 0)
2165 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2166 val);
2167 phy_unlock_mdio_bus(phydev);
2168 return val;
2169}
2170
2171static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2172{
2173 u16 val = 0;
2174
2175 if (enable)
2176 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2177 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2178 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2179 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2180
2181 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2182}
2183
2184static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2185 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2186{
2187 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2188 *seconds = (*seconds << 16) |
2189 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2190
2191 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2192 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2193 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2194
2195 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2196}
2197
2198static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2199 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2200{
2201 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2202 *seconds = *seconds << 16 |
2203 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2204
2205 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2206 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2207 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2208
2209 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2210}
2211
2212static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2213{
2214 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2215 struct phy_device *phydev = ptp_priv->phydev;
2216 struct lan8814_shared_priv *shared = phydev->shared->priv;
2217
2218 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2219 SOF_TIMESTAMPING_RX_HARDWARE |
2220 SOF_TIMESTAMPING_RAW_HARDWARE;
2221
2222 info->phc_index = ptp_clock_index(shared->ptp_clock);
2223
2224 info->tx_types =
2225 (1 << HWTSTAMP_TX_OFF) |
2226 (1 << HWTSTAMP_TX_ON) |
2227 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2228
2229 info->rx_filters =
2230 (1 << HWTSTAMP_FILTER_NONE) |
2231 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2232 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2233 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2234 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2235
2236 return 0;
2237}
2238
2239static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2240{
2241 int i;
2242
2243 for (i = 0; i < FIFO_SIZE; ++i)
2244 lanphy_read_page_reg(phydev, 5,
2245 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2246
2247 /* Read to clear overflow status bit */
2248 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2249}
2250
2251static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
2252{
2253 struct kszphy_ptp_priv *ptp_priv =
2254 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2255 struct phy_device *phydev = ptp_priv->phydev;
2256 struct lan8814_shared_priv *shared = phydev->shared->priv;
2257 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2258 struct hwtstamp_config config;
2259 int txcfg = 0, rxcfg = 0;
2260 int pkt_ts_enable;
2261
2262 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2263 return -EFAULT;
2264
2265 ptp_priv->hwts_tx_type = config.tx_type;
2266 ptp_priv->rx_filter = config.rx_filter;
2267
2268 switch (config.rx_filter) {
2269 case HWTSTAMP_FILTER_NONE:
2270 ptp_priv->layer = 0;
2271 ptp_priv->version = 0;
2272 break;
2273 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2274 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2275 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2276 ptp_priv->layer = PTP_CLASS_L4;
2277 ptp_priv->version = PTP_CLASS_V2;
2278 break;
2279 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2280 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2281 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2282 ptp_priv->layer = PTP_CLASS_L2;
2283 ptp_priv->version = PTP_CLASS_V2;
2284 break;
2285 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2286 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2287 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2288 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2289 ptp_priv->version = PTP_CLASS_V2;
2290 break;
2291 default:
2292 return -ERANGE;
2293 }
2294
2295 if (ptp_priv->layer & PTP_CLASS_L2) {
2296 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2297 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2298 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2299 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2300 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2301 }
2302 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2303 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2304
2305 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2306 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2307 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2308 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2309
2310 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
2311 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2312 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2313
2314 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2315 lan8814_config_ts_intr(ptp_priv->phydev, true);
2316 else
2317 lan8814_config_ts_intr(ptp_priv->phydev, false);
2318
2319 mutex_lock(&shared->shared_lock);
2320 if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2321 shared->ref++;
2322 else
2323 shared->ref--;
2324
2325 if (shared->ref)
2326 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2327 PTP_CMD_CTL_PTP_ENABLE_);
2328 else
2329 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2330 PTP_CMD_CTL_PTP_DISABLE_);
2331 mutex_unlock(&shared->shared_lock);
2332
2333 /* In case of multiple starts and stops, these needs to be cleared */
2334 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2335 list_del(&rx_ts->list);
2336 kfree(rx_ts);
2337 }
2338 skb_queue_purge(&ptp_priv->rx_queue);
2339 skb_queue_purge(&ptp_priv->tx_queue);
2340
2341 lan8814_flush_fifo(ptp_priv->phydev, false);
2342 lan8814_flush_fifo(ptp_priv->phydev, true);
2343
2344 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
2345}
2346
2347static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2348 struct sk_buff *skb, int type)
2349{
2350 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2351
2352 switch (ptp_priv->hwts_tx_type) {
2353 case HWTSTAMP_TX_ONESTEP_SYNC:
2354 if (ptp_msg_is_sync(skb, type)) {
2355 kfree_skb(skb);
2356 return;
2357 }
2358 fallthrough;
2359 case HWTSTAMP_TX_ON:
2360 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2361 skb_queue_tail(&ptp_priv->tx_queue, skb);
2362 break;
2363 case HWTSTAMP_TX_OFF:
2364 default:
2365 kfree_skb(skb);
2366 break;
2367 }
2368}
2369
2370static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2371{
2372 struct ptp_header *ptp_header;
2373 u32 type;
2374
2375 skb_push(skb, ETH_HLEN);
2376 type = ptp_classify_raw(skb);
2377 ptp_header = ptp_parse_header(skb, type);
2378 skb_pull_inline(skb, ETH_HLEN);
2379
2380 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2381}
2382
2383static bool lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2384 struct sk_buff *skb)
2385{
2386 struct skb_shared_hwtstamps *shhwtstamps;
2387 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2388 unsigned long flags;
2389 bool ret = false;
2390 u16 skb_sig;
2391
2392 lan8814_get_sig_rx(skb, &skb_sig);
2393
2394 /* Iterate over all RX timestamps and match it with the received skbs */
2395 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2396 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2397 /* Check if we found the signature we were looking for. */
2398 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2399 continue;
2400
2401 shhwtstamps = skb_hwtstamps(skb);
2402 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2403 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2404 rx_ts->nsec);
2405 list_del(&rx_ts->list);
2406 kfree(rx_ts);
2407
2408 ret = true;
2409 break;
2410 }
2411 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2412
2413 if (ret)
2414 netif_rx(skb);
2415 return ret;
2416}
2417
2418static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2419{
2420 struct kszphy_ptp_priv *ptp_priv =
2421 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2422
2423 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2424 type == PTP_CLASS_NONE)
2425 return false;
2426
2427 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2428 return false;
2429
2430 /* If we failed to match then add it to the queue for when the timestamp
2431 * will come
2432 */
2433 if (!lan8814_match_rx_ts(ptp_priv, skb))
2434 skb_queue_tail(&ptp_priv->rx_queue, skb);
2435
2436 return true;
2437}
2438
2439static void lan8814_ptp_clock_set(struct phy_device *phydev,
2440 u32 seconds, u32 nano_seconds)
2441{
2442 u32 sec_low, sec_high, nsec_low, nsec_high;
2443
2444 sec_low = seconds & 0xffff;
2445 sec_high = (seconds >> 16) & 0xffff;
2446 nsec_low = nano_seconds & 0xffff;
2447 nsec_high = (nano_seconds >> 16) & 0x3fff;
2448
2449 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2450 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2451 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2452 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2453
2454 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2455}
2456
2457static void lan8814_ptp_clock_get(struct phy_device *phydev,
2458 u32 *seconds, u32 *nano_seconds)
2459{
2460 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2461
2462 *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2463 *seconds = (*seconds << 16) |
2464 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2465
2466 *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2467 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2468 lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2469}
2470
2471static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2472 struct timespec64 *ts)
2473{
2474 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2475 ptp_clock_info);
2476 struct phy_device *phydev = shared->phydev;
2477 u32 nano_seconds;
2478 u32 seconds;
2479
2480 mutex_lock(&shared->shared_lock);
2481 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2482 mutex_unlock(&shared->shared_lock);
2483 ts->tv_sec = seconds;
2484 ts->tv_nsec = nano_seconds;
2485
2486 return 0;
2487}
2488
2489static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2490 const struct timespec64 *ts)
2491{
2492 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2493 ptp_clock_info);
2494 struct phy_device *phydev = shared->phydev;
2495
2496 mutex_lock(&shared->shared_lock);
2497 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2498 mutex_unlock(&shared->shared_lock);
2499
2500 return 0;
2501}
2502
2503static void lan8814_ptp_clock_step(struct phy_device *phydev,
2504 s64 time_step_ns)
2505{
2506 u32 nano_seconds_step;
2507 u64 abs_time_step_ns;
2508 u32 unsigned_seconds;
2509 u32 nano_seconds;
2510 u32 remainder;
2511 s32 seconds;
2512
2513 if (time_step_ns > 15000000000LL) {
2514 /* convert to clock set */
2515 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2516 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2517 &remainder);
2518 nano_seconds += remainder;
2519 if (nano_seconds >= 1000000000) {
2520 unsigned_seconds++;
2521 nano_seconds -= 1000000000;
2522 }
2523 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2524 return;
2525 } else if (time_step_ns < -15000000000LL) {
2526 /* convert to clock set */
2527 time_step_ns = -time_step_ns;
2528
2529 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2530 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2531 &remainder);
2532 nano_seconds_step = remainder;
2533 if (nano_seconds < nano_seconds_step) {
2534 unsigned_seconds--;
2535 nano_seconds += 1000000000;
2536 }
2537 nano_seconds -= nano_seconds_step;
2538 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2539 nano_seconds);
2540 return;
2541 }
2542
2543 /* do clock step */
2544 if (time_step_ns >= 0) {
2545 abs_time_step_ns = (u64)time_step_ns;
2546 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2547 &remainder);
2548 nano_seconds = remainder;
2549 } else {
2550 abs_time_step_ns = (u64)(-time_step_ns);
2551 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2552 &remainder));
2553 nano_seconds = remainder;
2554 if (nano_seconds > 0) {
2555 /* subtracting nano seconds is not allowed
2556 * convert to subtracting from seconds,
2557 * and adding to nanoseconds
2558 */
2559 seconds--;
2560 nano_seconds = (1000000000 - nano_seconds);
2561 }
2562 }
2563
2564 if (nano_seconds > 0) {
2565 /* add 8 ns to cover the likely normal increment */
2566 nano_seconds += 8;
2567 }
2568
2569 if (nano_seconds >= 1000000000) {
2570 /* carry into seconds */
2571 seconds++;
2572 nano_seconds -= 1000000000;
2573 }
2574
2575 while (seconds) {
2576 if (seconds > 0) {
2577 u32 adjustment_value = (u32)seconds;
2578 u16 adjustment_value_lo, adjustment_value_hi;
2579
2580 if (adjustment_value > 0xF)
2581 adjustment_value = 0xF;
2582
2583 adjustment_value_lo = adjustment_value & 0xffff;
2584 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2585
2586 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2587 adjustment_value_lo);
2588 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2589 PTP_LTC_STEP_ADJ_DIR_ |
2590 adjustment_value_hi);
2591 seconds -= ((s32)adjustment_value);
2592 } else {
2593 u32 adjustment_value = (u32)(-seconds);
2594 u16 adjustment_value_lo, adjustment_value_hi;
2595
2596 if (adjustment_value > 0xF)
2597 adjustment_value = 0xF;
2598
2599 adjustment_value_lo = adjustment_value & 0xffff;
2600 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2601
2602 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2603 adjustment_value_lo);
2604 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2605 adjustment_value_hi);
2606 seconds += ((s32)adjustment_value);
2607 }
2608 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2609 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2610 }
2611 if (nano_seconds) {
2612 u16 nano_seconds_lo;
2613 u16 nano_seconds_hi;
2614
2615 nano_seconds_lo = nano_seconds & 0xffff;
2616 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2617
2618 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2619 nano_seconds_lo);
2620 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2621 PTP_LTC_STEP_ADJ_DIR_ |
2622 nano_seconds_hi);
2623 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2624 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2625 }
2626}
2627
2628static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2629{
2630 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2631 ptp_clock_info);
2632 struct phy_device *phydev = shared->phydev;
2633
2634 mutex_lock(&shared->shared_lock);
2635 lan8814_ptp_clock_step(phydev, delta);
2636 mutex_unlock(&shared->shared_lock);
2637
2638 return 0;
2639}
2640
2641static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2642{
2643 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2644 ptp_clock_info);
2645 struct phy_device *phydev = shared->phydev;
2646 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2647 bool positive = true;
2648 u32 kszphy_rate_adj;
2649
2650 if (scaled_ppm < 0) {
2651 scaled_ppm = -scaled_ppm;
2652 positive = false;
2653 }
2654
2655 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2656 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2657
2658 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2659 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2660
2661 if (positive)
2662 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2663
2664 mutex_lock(&shared->shared_lock);
2665 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2666 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2667 mutex_unlock(&shared->shared_lock);
2668
2669 return 0;
2670}
2671
2672static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2673{
2674 struct ptp_header *ptp_header;
2675 u32 type;
2676
2677 type = ptp_classify_raw(skb);
2678 ptp_header = ptp_parse_header(skb, type);
2679
2680 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2681}
2682
2683static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2684{
2685 struct phy_device *phydev = ptp_priv->phydev;
2686 struct skb_shared_hwtstamps shhwtstamps;
2687 struct sk_buff *skb, *skb_tmp;
2688 unsigned long flags;
2689 u32 seconds, nsec;
2690 bool ret = false;
2691 u16 skb_sig;
2692 u16 seq_id;
2693
2694 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2695
2696 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2697 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2698 lan8814_get_sig_tx(skb, &skb_sig);
2699
2700 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2701 continue;
2702
2703 __skb_unlink(skb, &ptp_priv->tx_queue);
2704 ret = true;
2705 break;
2706 }
2707 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2708
2709 if (ret) {
2710 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2711 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2712 skb_complete_tx_timestamp(skb, &shhwtstamps);
2713 }
2714}
2715
2716static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2717{
2718 struct phy_device *phydev = ptp_priv->phydev;
2719 u32 reg;
2720
2721 do {
2722 lan8814_dequeue_tx_skb(ptp_priv);
2723
2724 /* If other timestamps are available in the FIFO,
2725 * process them.
2726 */
2727 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2728 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2729}
2730
2731static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2732 struct lan8814_ptp_rx_ts *rx_ts)
2733{
2734 struct skb_shared_hwtstamps *shhwtstamps;
2735 struct sk_buff *skb, *skb_tmp;
2736 unsigned long flags;
2737 bool ret = false;
2738 u16 skb_sig;
2739
2740 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2741 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2742 lan8814_get_sig_rx(skb, &skb_sig);
2743
2744 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2745 continue;
2746
2747 __skb_unlink(skb, &ptp_priv->rx_queue);
2748
2749 ret = true;
2750 break;
2751 }
2752 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2753
2754 if (ret) {
2755 shhwtstamps = skb_hwtstamps(skb);
2756 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2757 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2758 netif_rx(skb);
2759 }
2760
2761 return ret;
2762}
2763
2764static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2765{
2766 struct phy_device *phydev = ptp_priv->phydev;
2767 struct lan8814_ptp_rx_ts *rx_ts;
2768 unsigned long flags;
2769 u32 reg;
2770
2771 do {
2772 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2773 if (!rx_ts)
2774 return;
2775
2776 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2777 &rx_ts->seq_id);
2778
2779 /* If we failed to match the skb add it to the queue for when
2780 * the frame will come
2781 */
2782 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2783 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2784 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2785 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2786 } else {
2787 kfree(rx_ts);
2788 }
2789
2790 /* If other timestamps are available in the FIFO,
2791 * process them.
2792 */
2793 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2794 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2795}
2796
2797static void lan8814_handle_ptp_interrupt(struct phy_device *phydev)
2798{
2799 struct kszphy_priv *priv = phydev->priv;
2800 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2801 u16 status;
2802
2803 status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2804 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2805 lan8814_get_tx_ts(ptp_priv);
2806
2807 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2808 lan8814_get_rx_ts(ptp_priv);
2809
2810 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2811 lan8814_flush_fifo(phydev, true);
2812 skb_queue_purge(&ptp_priv->tx_queue);
2813 }
2814
2815 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2816 lan8814_flush_fifo(phydev, false);
2817 skb_queue_purge(&ptp_priv->rx_queue);
2818 }
2819}
2820
2821static int lan8804_config_init(struct phy_device *phydev)
2822{
2823 int val;
2824
2825 /* MDI-X setting for swap A,B transmit */
2826 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2827 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2828 val |= LAN8804_ALIGN_TX_A_B_SWAP;
2829 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2830
2831 /* Make sure that the PHY will not stop generating the clock when the
2832 * link partner goes down
2833 */
2834 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2835 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2836
2837 return 0;
2838}
2839
2840static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
2841{
2842 int status;
2843
2844 status = phy_read(phydev, LAN8814_INTS);
2845 if (status < 0) {
2846 phy_error(phydev);
2847 return IRQ_NONE;
2848 }
2849
2850 if (status > 0)
2851 phy_trigger_machine(phydev);
2852
2853 return IRQ_HANDLED;
2854}
2855
2856#define LAN8804_OUTPUT_CONTROL 25
2857#define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
2858#define LAN8804_CONTROL 31
2859#define LAN8804_CONTROL_INTR_POLARITY BIT(14)
2860
2861static int lan8804_config_intr(struct phy_device *phydev)
2862{
2863 int err;
2864
2865 /* This is an internal PHY of lan966x and is not possible to change the
2866 * polarity on the GIC found in lan966x, therefore change the polarity
2867 * of the interrupt in the PHY from being active low instead of active
2868 * high.
2869 */
2870 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
2871
2872 /* By default interrupt buffer is open-drain in which case the interrupt
2873 * can be active only low. Therefore change the interrupt buffer to be
2874 * push-pull to be able to change interrupt polarity
2875 */
2876 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
2877 LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
2878
2879 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2880 err = phy_read(phydev, LAN8814_INTS);
2881 if (err < 0)
2882 return err;
2883
2884 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
2885 if (err)
2886 return err;
2887 } else {
2888 err = phy_write(phydev, LAN8814_INTC, 0);
2889 if (err)
2890 return err;
2891
2892 err = phy_read(phydev, LAN8814_INTS);
2893 if (err < 0)
2894 return err;
2895 }
2896
2897 return 0;
2898}
2899
2900static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2901{
2902 int irq_status, tsu_irq_status;
2903 int ret = IRQ_NONE;
2904
2905 irq_status = phy_read(phydev, LAN8814_INTS);
2906 if (irq_status < 0) {
2907 phy_error(phydev);
2908 return IRQ_NONE;
2909 }
2910
2911 if (irq_status & LAN8814_INT_LINK) {
2912 phy_trigger_machine(phydev);
2913 ret = IRQ_HANDLED;
2914 }
2915
2916 while (1) {
2917 tsu_irq_status = lanphy_read_page_reg(phydev, 4,
2918 LAN8814_INTR_STS_REG);
2919
2920 if (tsu_irq_status > 0 &&
2921 (tsu_irq_status & (LAN8814_INTR_STS_REG_1588_TSU0_ |
2922 LAN8814_INTR_STS_REG_1588_TSU1_ |
2923 LAN8814_INTR_STS_REG_1588_TSU2_ |
2924 LAN8814_INTR_STS_REG_1588_TSU3_))) {
2925 lan8814_handle_ptp_interrupt(phydev);
2926 ret = IRQ_HANDLED;
2927 } else {
2928 break;
2929 }
2930 }
2931
2932 return ret;
2933}
2934
2935static int lan8814_ack_interrupt(struct phy_device *phydev)
2936{
2937 /* bit[12..0] int status, which is a read and clear register. */
2938 int rc;
2939
2940 rc = phy_read(phydev, LAN8814_INTS);
2941
2942 return (rc < 0) ? rc : 0;
2943}
2944
2945static int lan8814_config_intr(struct phy_device *phydev)
2946{
2947 int err;
2948
2949 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
2950 LAN8814_INTR_CTRL_REG_POLARITY |
2951 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
2952
2953 /* enable / disable interrupts */
2954 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2955 err = lan8814_ack_interrupt(phydev);
2956 if (err)
2957 return err;
2958
2959 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
2960 } else {
2961 err = phy_write(phydev, LAN8814_INTC, 0);
2962 if (err)
2963 return err;
2964
2965 err = lan8814_ack_interrupt(phydev);
2966 }
2967
2968 return err;
2969}
2970
2971static void lan8814_ptp_init(struct phy_device *phydev)
2972{
2973 struct kszphy_priv *priv = phydev->priv;
2974 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2975 u32 temp;
2976
2977 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2978 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2979 return;
2980
2981 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
2982
2983 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
2984 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2985 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
2986
2987 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
2988 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2989 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
2990
2991 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
2992 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
2993
2994 /* Removing default registers configs related to L2 and IP */
2995 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
2996 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
2997 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
2998 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
2999
3000 skb_queue_head_init(&ptp_priv->tx_queue);
3001 skb_queue_head_init(&ptp_priv->rx_queue);
3002 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3003 spin_lock_init(&ptp_priv->rx_ts_lock);
3004
3005 ptp_priv->phydev = phydev;
3006
3007 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3008 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3009 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3010 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3011
3012 phydev->mii_ts = &ptp_priv->mii_ts;
3013}
3014
3015static int lan8814_ptp_probe_once(struct phy_device *phydev)
3016{
3017 struct lan8814_shared_priv *shared = phydev->shared->priv;
3018
3019 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3020 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3021 return 0;
3022
3023 /* Initialise shared lock for clock*/
3024 mutex_init(&shared->shared_lock);
3025
3026 shared->ptp_clock_info.owner = THIS_MODULE;
3027 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3028 shared->ptp_clock_info.max_adj = 31249999;
3029 shared->ptp_clock_info.n_alarm = 0;
3030 shared->ptp_clock_info.n_ext_ts = 0;
3031 shared->ptp_clock_info.n_pins = 0;
3032 shared->ptp_clock_info.pps = 0;
3033 shared->ptp_clock_info.pin_config = NULL;
3034 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3035 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3036 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3037 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3038 shared->ptp_clock_info.getcrosststamp = NULL;
3039
3040 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3041 &phydev->mdio.dev);
3042 if (IS_ERR_OR_NULL(shared->ptp_clock)) {
3043 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3044 PTR_ERR(shared->ptp_clock));
3045 return -EINVAL;
3046 }
3047
3048 phydev_dbg(phydev, "successfully registered ptp clock\n");
3049
3050 shared->phydev = phydev;
3051
3052 /* The EP.4 is shared between all the PHYs in the package and also it
3053 * can be accessed by any of the PHYs
3054 */
3055 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3056 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3057 PTP_OPERATING_MODE_STANDALONE_);
3058
3059 return 0;
3060}
3061
3062static void lan8814_setup_led(struct phy_device *phydev, int val)
3063{
3064 int temp;
3065
3066 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3067
3068 if (val)
3069 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3070 else
3071 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3072
3073 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3074}
3075
3076static int lan8814_config_init(struct phy_device *phydev)
3077{
3078 struct kszphy_priv *lan8814 = phydev->priv;
3079 int val;
3080
3081 /* Reset the PHY */
3082 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3083 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3084 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3085
3086 /* Disable ANEG with QSGMII PCS Host side */
3087 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3088 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3089 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3090
3091 /* MDI-X setting for swap A,B transmit */
3092 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3093 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3094 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3095 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3096
3097 if (lan8814->led_mode >= 0)
3098 lan8814_setup_led(phydev, lan8814->led_mode);
3099
3100 return 0;
3101}
3102
3103/* It is expected that there will not be any 'lan8814_take_coma_mode'
3104 * function called in suspend. Because the GPIO line can be shared, so if one of
3105 * the phys goes back in coma mode, then all the other PHYs will go, which is
3106 * wrong.
3107 */
3108static int lan8814_release_coma_mode(struct phy_device *phydev)
3109{
3110 struct gpio_desc *gpiod;
3111
3112 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3113 GPIOD_OUT_HIGH_OPEN_DRAIN |
3114 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3115 if (IS_ERR(gpiod))
3116 return PTR_ERR(gpiod);
3117
3118 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3119 gpiod_set_value_cansleep(gpiod, 0);
3120
3121 return 0;
3122}
3123
3124static int lan8814_probe(struct phy_device *phydev)
3125{
3126 const struct kszphy_type *type = phydev->drv->driver_data;
3127 struct kszphy_priv *priv;
3128 u16 addr;
3129 int err;
3130
3131 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
3132 if (!priv)
3133 return -ENOMEM;
3134
3135 phydev->priv = priv;
3136
3137 priv->type = type;
3138
3139 kszphy_parse_led_mode(phydev);
3140
3141 /* Strap-in value for PHY address, below register read gives starting
3142 * phy address value
3143 */
3144 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
3145 devm_phy_package_join(&phydev->mdio.dev, phydev,
3146 addr, sizeof(struct lan8814_shared_priv));
3147
3148 if (phy_package_init_once(phydev)) {
3149 err = lan8814_release_coma_mode(phydev);
3150 if (err)
3151 return err;
3152
3153 err = lan8814_ptp_probe_once(phydev);
3154 if (err)
3155 return err;
3156 }
3157
3158 lan8814_ptp_init(phydev);
3159
3160 return 0;
3161}
3162
3163static struct phy_driver ksphy_driver[] = {
3164{
3165 .phy_id = PHY_ID_KS8737,
3166 .phy_id_mask = MICREL_PHY_ID_MASK,
3167 .name = "Micrel KS8737",
3168 /* PHY_BASIC_FEATURES */
3169 .driver_data = &ks8737_type,
3170 .probe = kszphy_probe,
3171 .config_init = kszphy_config_init,
3172 .config_intr = kszphy_config_intr,
3173 .handle_interrupt = kszphy_handle_interrupt,
3174 .suspend = kszphy_suspend,
3175 .resume = kszphy_resume,
3176}, {
3177 .phy_id = PHY_ID_KSZ8021,
3178 .phy_id_mask = 0x00ffffff,
3179 .name = "Micrel KSZ8021 or KSZ8031",
3180 /* PHY_BASIC_FEATURES */
3181 .driver_data = &ksz8021_type,
3182 .probe = kszphy_probe,
3183 .config_init = kszphy_config_init,
3184 .config_intr = kszphy_config_intr,
3185 .handle_interrupt = kszphy_handle_interrupt,
3186 .get_sset_count = kszphy_get_sset_count,
3187 .get_strings = kszphy_get_strings,
3188 .get_stats = kszphy_get_stats,
3189 .suspend = kszphy_suspend,
3190 .resume = kszphy_resume,
3191}, {
3192 .phy_id = PHY_ID_KSZ8031,
3193 .phy_id_mask = 0x00ffffff,
3194 .name = "Micrel KSZ8031",
3195 /* PHY_BASIC_FEATURES */
3196 .driver_data = &ksz8021_type,
3197 .probe = kszphy_probe,
3198 .config_init = kszphy_config_init,
3199 .config_intr = kszphy_config_intr,
3200 .handle_interrupt = kszphy_handle_interrupt,
3201 .get_sset_count = kszphy_get_sset_count,
3202 .get_strings = kszphy_get_strings,
3203 .get_stats = kszphy_get_stats,
3204 .suspend = kszphy_suspend,
3205 .resume = kszphy_resume,
3206}, {
3207 .phy_id = PHY_ID_KSZ8041,
3208 .phy_id_mask = MICREL_PHY_ID_MASK,
3209 .name = "Micrel KSZ8041",
3210 /* PHY_BASIC_FEATURES */
3211 .driver_data = &ksz8041_type,
3212 .probe = kszphy_probe,
3213 .config_init = ksz8041_config_init,
3214 .config_aneg = ksz8041_config_aneg,
3215 .config_intr = kszphy_config_intr,
3216 .handle_interrupt = kszphy_handle_interrupt,
3217 .get_sset_count = kszphy_get_sset_count,
3218 .get_strings = kszphy_get_strings,
3219 .get_stats = kszphy_get_stats,
3220 /* No suspend/resume callbacks because of errata DS80000700A,
3221 * receiver error following software power down.
3222 */
3223}, {
3224 .phy_id = PHY_ID_KSZ8041RNLI,
3225 .phy_id_mask = MICREL_PHY_ID_MASK,
3226 .name = "Micrel KSZ8041RNLI",
3227 /* PHY_BASIC_FEATURES */
3228 .driver_data = &ksz8041_type,
3229 .probe = kszphy_probe,
3230 .config_init = kszphy_config_init,
3231 .config_intr = kszphy_config_intr,
3232 .handle_interrupt = kszphy_handle_interrupt,
3233 .get_sset_count = kszphy_get_sset_count,
3234 .get_strings = kszphy_get_strings,
3235 .get_stats = kszphy_get_stats,
3236 .suspend = kszphy_suspend,
3237 .resume = kszphy_resume,
3238}, {
3239 .name = "Micrel KSZ8051",
3240 /* PHY_BASIC_FEATURES */
3241 .driver_data = &ksz8051_type,
3242 .probe = kszphy_probe,
3243 .config_init = kszphy_config_init,
3244 .config_intr = kszphy_config_intr,
3245 .handle_interrupt = kszphy_handle_interrupt,
3246 .get_sset_count = kszphy_get_sset_count,
3247 .get_strings = kszphy_get_strings,
3248 .get_stats = kszphy_get_stats,
3249 .match_phy_device = ksz8051_match_phy_device,
3250 .suspend = kszphy_suspend,
3251 .resume = kszphy_resume,
3252}, {
3253 .phy_id = PHY_ID_KSZ8001,
3254 .name = "Micrel KSZ8001 or KS8721",
3255 .phy_id_mask = 0x00fffffc,
3256 /* PHY_BASIC_FEATURES */
3257 .driver_data = &ksz8041_type,
3258 .probe = kszphy_probe,
3259 .config_init = kszphy_config_init,
3260 .config_intr = kszphy_config_intr,
3261 .handle_interrupt = kszphy_handle_interrupt,
3262 .get_sset_count = kszphy_get_sset_count,
3263 .get_strings = kszphy_get_strings,
3264 .get_stats = kszphy_get_stats,
3265 .suspend = kszphy_suspend,
3266 .resume = kszphy_resume,
3267}, {
3268 .phy_id = PHY_ID_KSZ8081,
3269 .name = "Micrel KSZ8081 or KSZ8091",
3270 .phy_id_mask = MICREL_PHY_ID_MASK,
3271 .flags = PHY_POLL_CABLE_TEST,
3272 /* PHY_BASIC_FEATURES */
3273 .driver_data = &ksz8081_type,
3274 .probe = kszphy_probe,
3275 .config_init = ksz8081_config_init,
3276 .soft_reset = genphy_soft_reset,
3277 .config_aneg = ksz8081_config_aneg,
3278 .read_status = ksz8081_read_status,
3279 .config_intr = kszphy_config_intr,
3280 .handle_interrupt = kszphy_handle_interrupt,
3281 .get_sset_count = kszphy_get_sset_count,
3282 .get_strings = kszphy_get_strings,
3283 .get_stats = kszphy_get_stats,
3284 .suspend = kszphy_suspend,
3285 .resume = kszphy_resume,
3286 .cable_test_start = ksz886x_cable_test_start,
3287 .cable_test_get_status = ksz886x_cable_test_get_status,
3288}, {
3289 .phy_id = PHY_ID_KSZ8061,
3290 .name = "Micrel KSZ8061",
3291 .phy_id_mask = MICREL_PHY_ID_MASK,
3292 /* PHY_BASIC_FEATURES */
3293 .probe = kszphy_probe,
3294 .config_init = ksz8061_config_init,
3295 .config_intr = kszphy_config_intr,
3296 .handle_interrupt = kszphy_handle_interrupt,
3297 .suspend = kszphy_suspend,
3298 .resume = kszphy_resume,
3299}, {
3300 .phy_id = PHY_ID_KSZ9021,
3301 .phy_id_mask = 0x000ffffe,
3302 .name = "Micrel KSZ9021 Gigabit PHY",
3303 /* PHY_GBIT_FEATURES */
3304 .driver_data = &ksz9021_type,
3305 .probe = kszphy_probe,
3306 .get_features = ksz9031_get_features,
3307 .config_init = ksz9021_config_init,
3308 .config_intr = kszphy_config_intr,
3309 .handle_interrupt = kszphy_handle_interrupt,
3310 .get_sset_count = kszphy_get_sset_count,
3311 .get_strings = kszphy_get_strings,
3312 .get_stats = kszphy_get_stats,
3313 .suspend = kszphy_suspend,
3314 .resume = kszphy_resume,
3315 .read_mmd = genphy_read_mmd_unsupported,
3316 .write_mmd = genphy_write_mmd_unsupported,
3317}, {
3318 .phy_id = PHY_ID_KSZ9031,
3319 .phy_id_mask = MICREL_PHY_ID_MASK,
3320 .name = "Micrel KSZ9031 Gigabit PHY",
3321 .flags = PHY_POLL_CABLE_TEST,
3322 .driver_data = &ksz9021_type,
3323 .probe = kszphy_probe,
3324 .get_features = ksz9031_get_features,
3325 .config_init = ksz9031_config_init,
3326 .soft_reset = genphy_soft_reset,
3327 .read_status = ksz9031_read_status,
3328 .config_intr = kszphy_config_intr,
3329 .handle_interrupt = kszphy_handle_interrupt,
3330 .get_sset_count = kszphy_get_sset_count,
3331 .get_strings = kszphy_get_strings,
3332 .get_stats = kszphy_get_stats,
3333 .suspend = kszphy_suspend,
3334 .resume = kszphy_resume,
3335 .cable_test_start = ksz9x31_cable_test_start,
3336 .cable_test_get_status = ksz9x31_cable_test_get_status,
3337}, {
3338 .phy_id = PHY_ID_LAN8814,
3339 .phy_id_mask = MICREL_PHY_ID_MASK,
3340 .name = "Microchip INDY Gigabit Quad PHY",
3341 .flags = PHY_POLL_CABLE_TEST,
3342 .config_init = lan8814_config_init,
3343 .driver_data = &lan8814_type,
3344 .probe = lan8814_probe,
3345 .soft_reset = genphy_soft_reset,
3346 .read_status = ksz9031_read_status,
3347 .get_sset_count = kszphy_get_sset_count,
3348 .get_strings = kszphy_get_strings,
3349 .get_stats = kszphy_get_stats,
3350 .suspend = genphy_suspend,
3351 .resume = kszphy_resume,
3352 .config_intr = lan8814_config_intr,
3353 .handle_interrupt = lan8814_handle_interrupt,
3354 .cable_test_start = lan8814_cable_test_start,
3355 .cable_test_get_status = ksz886x_cable_test_get_status,
3356}, {
3357 .phy_id = PHY_ID_LAN8804,
3358 .phy_id_mask = MICREL_PHY_ID_MASK,
3359 .name = "Microchip LAN966X Gigabit PHY",
3360 .config_init = lan8804_config_init,
3361 .driver_data = &ksz9021_type,
3362 .probe = kszphy_probe,
3363 .soft_reset = genphy_soft_reset,
3364 .read_status = ksz9031_read_status,
3365 .get_sset_count = kszphy_get_sset_count,
3366 .get_strings = kszphy_get_strings,
3367 .get_stats = kszphy_get_stats,
3368 .suspend = genphy_suspend,
3369 .resume = kszphy_resume,
3370 .config_intr = lan8804_config_intr,
3371 .handle_interrupt = lan8804_handle_interrupt,
3372}, {
3373 .phy_id = PHY_ID_KSZ9131,
3374 .phy_id_mask = MICREL_PHY_ID_MASK,
3375 .name = "Microchip KSZ9131 Gigabit PHY",
3376 /* PHY_GBIT_FEATURES */
3377 .flags = PHY_POLL_CABLE_TEST,
3378 .driver_data = &ksz9021_type,
3379 .probe = kszphy_probe,
3380 .config_init = ksz9131_config_init,
3381 .config_intr = kszphy_config_intr,
3382 .config_aneg = ksz9131_config_aneg,
3383 .read_status = ksz9131_read_status,
3384 .handle_interrupt = kszphy_handle_interrupt,
3385 .get_sset_count = kszphy_get_sset_count,
3386 .get_strings = kszphy_get_strings,
3387 .get_stats = kszphy_get_stats,
3388 .suspend = kszphy_suspend,
3389 .resume = kszphy_resume,
3390 .cable_test_start = ksz9x31_cable_test_start,
3391 .cable_test_get_status = ksz9x31_cable_test_get_status,
3392}, {
3393 .phy_id = PHY_ID_KSZ8873MLL,
3394 .phy_id_mask = MICREL_PHY_ID_MASK,
3395 .name = "Micrel KSZ8873MLL Switch",
3396 /* PHY_BASIC_FEATURES */
3397 .config_init = kszphy_config_init,
3398 .config_aneg = ksz8873mll_config_aneg,
3399 .read_status = ksz8873mll_read_status,
3400 .suspend = genphy_suspend,
3401 .resume = genphy_resume,
3402}, {
3403 .phy_id = PHY_ID_KSZ886X,
3404 .phy_id_mask = MICREL_PHY_ID_MASK,
3405 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
3406 .driver_data = &ksz886x_type,
3407 /* PHY_BASIC_FEATURES */
3408 .flags = PHY_POLL_CABLE_TEST,
3409 .config_init = kszphy_config_init,
3410 .config_aneg = ksz886x_config_aneg,
3411 .read_status = ksz886x_read_status,
3412 .suspend = genphy_suspend,
3413 .resume = genphy_resume,
3414 .cable_test_start = ksz886x_cable_test_start,
3415 .cable_test_get_status = ksz886x_cable_test_get_status,
3416}, {
3417 .name = "Micrel KSZ87XX Switch",
3418 /* PHY_BASIC_FEATURES */
3419 .config_init = kszphy_config_init,
3420 .match_phy_device = ksz8795_match_phy_device,
3421 .suspend = genphy_suspend,
3422 .resume = genphy_resume,
3423}, {
3424 .phy_id = PHY_ID_KSZ9477,
3425 .phy_id_mask = MICREL_PHY_ID_MASK,
3426 .name = "Microchip KSZ9477",
3427 /* PHY_GBIT_FEATURES */
3428 .config_init = kszphy_config_init,
3429 .config_intr = kszphy_config_intr,
3430 .handle_interrupt = kszphy_handle_interrupt,
3431 .suspend = genphy_suspend,
3432 .resume = genphy_resume,
3433} };
3434
3435module_phy_driver(ksphy_driver);
3436
3437MODULE_DESCRIPTION("Micrel PHY driver");
3438MODULE_AUTHOR("David J. Choi");
3439MODULE_LICENSE("GPL");
3440
3441static struct mdio_device_id __maybe_unused micrel_tbl[] = {
3442 { PHY_ID_KSZ9021, 0x000ffffe },
3443 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
3444 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
3445 { PHY_ID_KSZ8001, 0x00fffffc },
3446 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
3447 { PHY_ID_KSZ8021, 0x00ffffff },
3448 { PHY_ID_KSZ8031, 0x00ffffff },
3449 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
3450 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
3451 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
3452 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
3453 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
3454 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
3455 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
3456 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
3457 { }
3458};
3459
3460MODULE_DEVICE_TABLE(mdio, micrel_tbl);