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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/if_ether.h>
29#include <linux/delay.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33
34#include "e1000_mac.h"
35
36#include "igb.h"
37
38static s32 igb_set_default_fc(struct e1000_hw *hw);
39static s32 igb_set_fc_watermarks(struct e1000_hw *hw);
40
41/**
42 * igb_get_bus_info_pcie - Get PCIe bus information
43 * @hw: pointer to the HW structure
44 *
45 * Determines and stores the system bus information for a particular
46 * network interface. The following bus information is determined and stored:
47 * bus speed, bus width, type (PCIe), and PCIe function.
48 **/
49s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
50{
51 struct e1000_bus_info *bus = &hw->bus;
52 s32 ret_val;
53 u32 reg;
54 u16 pcie_link_status;
55
56 bus->type = e1000_bus_type_pci_express;
57
58 ret_val = igb_read_pcie_cap_reg(hw,
59 PCI_EXP_LNKSTA,
60 &pcie_link_status);
61 if (ret_val) {
62 bus->width = e1000_bus_width_unknown;
63 bus->speed = e1000_bus_speed_unknown;
64 } else {
65 switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
66 case PCI_EXP_LNKSTA_CLS_2_5GB:
67 bus->speed = e1000_bus_speed_2500;
68 break;
69 case PCI_EXP_LNKSTA_CLS_5_0GB:
70 bus->speed = e1000_bus_speed_5000;
71 break;
72 default:
73 bus->speed = e1000_bus_speed_unknown;
74 break;
75 }
76
77 bus->width = (enum e1000_bus_width)((pcie_link_status &
78 PCI_EXP_LNKSTA_NLW) >>
79 PCI_EXP_LNKSTA_NLW_SHIFT);
80 }
81
82 reg = rd32(E1000_STATUS);
83 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
84
85 return 0;
86}
87
88/**
89 * igb_clear_vfta - Clear VLAN filter table
90 * @hw: pointer to the HW structure
91 *
92 * Clears the register array which contains the VLAN filter table by
93 * setting all the values to 0.
94 **/
95void igb_clear_vfta(struct e1000_hw *hw)
96{
97 u32 offset;
98
99 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
100 array_wr32(E1000_VFTA, offset, 0);
101 wrfl();
102 }
103}
104
105/**
106 * igb_write_vfta - Write value to VLAN filter table
107 * @hw: pointer to the HW structure
108 * @offset: register offset in VLAN filter table
109 * @value: register value written to VLAN filter table
110 *
111 * Writes value at the given offset in the register array which stores
112 * the VLAN filter table.
113 **/
114static void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
115{
116 array_wr32(E1000_VFTA, offset, value);
117 wrfl();
118}
119
120/**
121 * igb_init_rx_addrs - Initialize receive address's
122 * @hw: pointer to the HW structure
123 * @rar_count: receive address registers
124 *
125 * Setups the receive address registers by setting the base receive address
126 * register to the devices MAC address and clearing all the other receive
127 * address registers to 0.
128 **/
129void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
130{
131 u32 i;
132 u8 mac_addr[ETH_ALEN] = {0};
133
134 /* Setup the receive address */
135 hw_dbg("Programming MAC Address into RAR[0]\n");
136
137 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
138
139 /* Zero out the other (rar_entry_count - 1) receive addresses */
140 hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
141 for (i = 1; i < rar_count; i++)
142 hw->mac.ops.rar_set(hw, mac_addr, i);
143}
144
145/**
146 * igb_vfta_set - enable or disable vlan in VLAN filter table
147 * @hw: pointer to the HW structure
148 * @vid: VLAN id to add or remove
149 * @add: if true add filter, if false remove
150 *
151 * Sets or clears a bit in the VLAN filter table array based on VLAN id
152 * and if we are adding or removing the filter
153 **/
154s32 igb_vfta_set(struct e1000_hw *hw, u32 vid, bool add)
155{
156 u32 index = (vid >> E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
157 u32 mask = 1 << (vid & E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
158 u32 vfta = array_rd32(E1000_VFTA, index);
159 s32 ret_val = 0;
160
161 /* bit was set/cleared before we started */
162 if ((!!(vfta & mask)) == add) {
163 ret_val = -E1000_ERR_CONFIG;
164 } else {
165 if (add)
166 vfta |= mask;
167 else
168 vfta &= ~mask;
169 }
170
171 igb_write_vfta(hw, index, vfta);
172
173 return ret_val;
174}
175
176/**
177 * igb_check_alt_mac_addr - Check for alternate MAC addr
178 * @hw: pointer to the HW structure
179 *
180 * Checks the nvm for an alternate MAC address. An alternate MAC address
181 * can be setup by pre-boot software and must be treated like a permanent
182 * address and must override the actual permanent MAC address. If an
183 * alternate MAC address is fopund it is saved in the hw struct and
184 * prgrammed into RAR0 and the cuntion returns success, otherwise the
185 * function returns an error.
186 **/
187s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
188{
189 u32 i;
190 s32 ret_val = 0;
191 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
192 u8 alt_mac_addr[ETH_ALEN];
193
194 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
195 &nvm_alt_mac_addr_offset);
196 if (ret_val) {
197 hw_dbg("NVM Read Error\n");
198 goto out;
199 }
200
201 if (nvm_alt_mac_addr_offset == 0xFFFF) {
202 /* There is no Alternate MAC Address */
203 goto out;
204 }
205
206 if (hw->bus.func == E1000_FUNC_1)
207 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
208 for (i = 0; i < ETH_ALEN; i += 2) {
209 offset = nvm_alt_mac_addr_offset + (i >> 1);
210 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
211 if (ret_val) {
212 hw_dbg("NVM Read Error\n");
213 goto out;
214 }
215
216 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
217 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
218 }
219
220 /* if multicast bit is set, the alternate address will not be used */
221 if (is_multicast_ether_addr(alt_mac_addr)) {
222 hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
223 goto out;
224 }
225
226 /*
227 * We have a valid alternate MAC address, and we want to treat it the
228 * same as the normal permanent MAC address stored by the HW into the
229 * RAR. Do this by mapping this address into RAR0.
230 */
231 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
232
233out:
234 return ret_val;
235}
236
237/**
238 * igb_rar_set - Set receive address register
239 * @hw: pointer to the HW structure
240 * @addr: pointer to the receive address
241 * @index: receive address array register
242 *
243 * Sets the receive address array register at index to the address passed
244 * in by addr.
245 **/
246void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
247{
248 u32 rar_low, rar_high;
249
250 /*
251 * HW expects these in little endian so we reverse the byte order
252 * from network order (big endian) to little endian
253 */
254 rar_low = ((u32) addr[0] |
255 ((u32) addr[1] << 8) |
256 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
257
258 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
259
260 /* If MAC address zero, no need to set the AV bit */
261 if (rar_low || rar_high)
262 rar_high |= E1000_RAH_AV;
263
264 /*
265 * Some bridges will combine consecutive 32-bit writes into
266 * a single burst write, which will malfunction on some parts.
267 * The flushes avoid this.
268 */
269 wr32(E1000_RAL(index), rar_low);
270 wrfl();
271 wr32(E1000_RAH(index), rar_high);
272 wrfl();
273}
274
275/**
276 * igb_mta_set - Set multicast filter table address
277 * @hw: pointer to the HW structure
278 * @hash_value: determines the MTA register and bit to set
279 *
280 * The multicast table address is a register array of 32-bit registers.
281 * The hash_value is used to determine what register the bit is in, the
282 * current value is read, the new bit is OR'd in and the new value is
283 * written back into the register.
284 **/
285void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
286{
287 u32 hash_bit, hash_reg, mta;
288
289 /*
290 * The MTA is a register array of 32-bit registers. It is
291 * treated like an array of (32*mta_reg_count) bits. We want to
292 * set bit BitArray[hash_value]. So we figure out what register
293 * the bit is in, read it, OR in the new bit, then write
294 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a
295 * mask to bits 31:5 of the hash value which gives us the
296 * register we're modifying. The hash bit within that register
297 * is determined by the lower 5 bits of the hash value.
298 */
299 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
300 hash_bit = hash_value & 0x1F;
301
302 mta = array_rd32(E1000_MTA, hash_reg);
303
304 mta |= (1 << hash_bit);
305
306 array_wr32(E1000_MTA, hash_reg, mta);
307 wrfl();
308}
309
310/**
311 * igb_hash_mc_addr - Generate a multicast hash value
312 * @hw: pointer to the HW structure
313 * @mc_addr: pointer to a multicast address
314 *
315 * Generates a multicast address hash value which is used to determine
316 * the multicast filter table array address and new table value. See
317 * igb_mta_set()
318 **/
319static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
320{
321 u32 hash_value, hash_mask;
322 u8 bit_shift = 0;
323
324 /* Register count multiplied by bits per register */
325 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
326
327 /*
328 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
329 * where 0xFF would still fall within the hash mask.
330 */
331 while (hash_mask >> bit_shift != 0xFF)
332 bit_shift++;
333
334 /*
335 * The portion of the address that is used for the hash table
336 * is determined by the mc_filter_type setting.
337 * The algorithm is such that there is a total of 8 bits of shifting.
338 * The bit_shift for a mc_filter_type of 0 represents the number of
339 * left-shifts where the MSB of mc_addr[5] would still fall within
340 * the hash_mask. Case 0 does this exactly. Since there are a total
341 * of 8 bits of shifting, then mc_addr[4] will shift right the
342 * remaining number of bits. Thus 8 - bit_shift. The rest of the
343 * cases are a variation of this algorithm...essentially raising the
344 * number of bits to shift mc_addr[5] left, while still keeping the
345 * 8-bit shifting total.
346 *
347 * For example, given the following Destination MAC Address and an
348 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
349 * we can see that the bit_shift for case 0 is 4. These are the hash
350 * values resulting from each mc_filter_type...
351 * [0] [1] [2] [3] [4] [5]
352 * 01 AA 00 12 34 56
353 * LSB MSB
354 *
355 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
356 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
357 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
358 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
359 */
360 switch (hw->mac.mc_filter_type) {
361 default:
362 case 0:
363 break;
364 case 1:
365 bit_shift += 1;
366 break;
367 case 2:
368 bit_shift += 2;
369 break;
370 case 3:
371 bit_shift += 4;
372 break;
373 }
374
375 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
376 (((u16) mc_addr[5]) << bit_shift)));
377
378 return hash_value;
379}
380
381/**
382 * igb_update_mc_addr_list - Update Multicast addresses
383 * @hw: pointer to the HW structure
384 * @mc_addr_list: array of multicast addresses to program
385 * @mc_addr_count: number of multicast addresses to program
386 *
387 * Updates entire Multicast Table Array.
388 * The caller must have a packed mc_addr_list of multicast addresses.
389 **/
390void igb_update_mc_addr_list(struct e1000_hw *hw,
391 u8 *mc_addr_list, u32 mc_addr_count)
392{
393 u32 hash_value, hash_bit, hash_reg;
394 int i;
395
396 /* clear mta_shadow */
397 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
398
399 /* update mta_shadow from mc_addr_list */
400 for (i = 0; (u32) i < mc_addr_count; i++) {
401 hash_value = igb_hash_mc_addr(hw, mc_addr_list);
402
403 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
404 hash_bit = hash_value & 0x1F;
405
406 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
407 mc_addr_list += (ETH_ALEN);
408 }
409
410 /* replace the entire MTA table */
411 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
412 array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
413 wrfl();
414}
415
416/**
417 * igb_clear_hw_cntrs_base - Clear base hardware counters
418 * @hw: pointer to the HW structure
419 *
420 * Clears the base hardware counters by reading the counter registers.
421 **/
422void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
423{
424 rd32(E1000_CRCERRS);
425 rd32(E1000_SYMERRS);
426 rd32(E1000_MPC);
427 rd32(E1000_SCC);
428 rd32(E1000_ECOL);
429 rd32(E1000_MCC);
430 rd32(E1000_LATECOL);
431 rd32(E1000_COLC);
432 rd32(E1000_DC);
433 rd32(E1000_SEC);
434 rd32(E1000_RLEC);
435 rd32(E1000_XONRXC);
436 rd32(E1000_XONTXC);
437 rd32(E1000_XOFFRXC);
438 rd32(E1000_XOFFTXC);
439 rd32(E1000_FCRUC);
440 rd32(E1000_GPRC);
441 rd32(E1000_BPRC);
442 rd32(E1000_MPRC);
443 rd32(E1000_GPTC);
444 rd32(E1000_GORCL);
445 rd32(E1000_GORCH);
446 rd32(E1000_GOTCL);
447 rd32(E1000_GOTCH);
448 rd32(E1000_RNBC);
449 rd32(E1000_RUC);
450 rd32(E1000_RFC);
451 rd32(E1000_ROC);
452 rd32(E1000_RJC);
453 rd32(E1000_TORL);
454 rd32(E1000_TORH);
455 rd32(E1000_TOTL);
456 rd32(E1000_TOTH);
457 rd32(E1000_TPR);
458 rd32(E1000_TPT);
459 rd32(E1000_MPTC);
460 rd32(E1000_BPTC);
461}
462
463/**
464 * igb_check_for_copper_link - Check for link (Copper)
465 * @hw: pointer to the HW structure
466 *
467 * Checks to see of the link status of the hardware has changed. If a
468 * change in link status has been detected, then we read the PHY registers
469 * to get the current speed/duplex if link exists.
470 **/
471s32 igb_check_for_copper_link(struct e1000_hw *hw)
472{
473 struct e1000_mac_info *mac = &hw->mac;
474 s32 ret_val;
475 bool link;
476
477 /*
478 * We only want to go out to the PHY registers to see if Auto-Neg
479 * has completed and/or if our link status has changed. The
480 * get_link_status flag is set upon receiving a Link Status
481 * Change or Rx Sequence Error interrupt.
482 */
483 if (!mac->get_link_status) {
484 ret_val = 0;
485 goto out;
486 }
487
488 /*
489 * First we want to see if the MII Status Register reports
490 * link. If so, then we want to get the current speed/duplex
491 * of the PHY.
492 */
493 ret_val = igb_phy_has_link(hw, 1, 0, &link);
494 if (ret_val)
495 goto out;
496
497 if (!link)
498 goto out; /* No link detected */
499
500 mac->get_link_status = false;
501
502 /*
503 * Check if there was DownShift, must be checked
504 * immediately after link-up
505 */
506 igb_check_downshift(hw);
507
508 /*
509 * If we are forcing speed/duplex, then we simply return since
510 * we have already determined whether we have link or not.
511 */
512 if (!mac->autoneg) {
513 ret_val = -E1000_ERR_CONFIG;
514 goto out;
515 }
516
517 /*
518 * Auto-Neg is enabled. Auto Speed Detection takes care
519 * of MAC speed/duplex configuration. So we only need to
520 * configure Collision Distance in the MAC.
521 */
522 igb_config_collision_dist(hw);
523
524 /*
525 * Configure Flow Control now that Auto-Neg has completed.
526 * First, we need to restore the desired flow control
527 * settings because we may have had to re-autoneg with a
528 * different link partner.
529 */
530 ret_val = igb_config_fc_after_link_up(hw);
531 if (ret_val)
532 hw_dbg("Error configuring flow control\n");
533
534out:
535 return ret_val;
536}
537
538/**
539 * igb_setup_link - Setup flow control and link settings
540 * @hw: pointer to the HW structure
541 *
542 * Determines which flow control settings to use, then configures flow
543 * control. Calls the appropriate media-specific link configuration
544 * function. Assuming the adapter has a valid link partner, a valid link
545 * should be established. Assumes the hardware has previously been reset
546 * and the transmitter and receiver are not enabled.
547 **/
548s32 igb_setup_link(struct e1000_hw *hw)
549{
550 s32 ret_val = 0;
551
552 /*
553 * In the case of the phy reset being blocked, we already have a link.
554 * We do not need to set it up again.
555 */
556 if (igb_check_reset_block(hw))
557 goto out;
558
559 /*
560 * If requested flow control is set to default, set flow control
561 * based on the EEPROM flow control settings.
562 */
563 if (hw->fc.requested_mode == e1000_fc_default) {
564 ret_val = igb_set_default_fc(hw);
565 if (ret_val)
566 goto out;
567 }
568
569 /*
570 * We want to save off the original Flow Control configuration just
571 * in case we get disconnected and then reconnected into a different
572 * hub or switch with different Flow Control capabilities.
573 */
574 hw->fc.current_mode = hw->fc.requested_mode;
575
576 hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
577
578 /* Call the necessary media_type subroutine to configure the link. */
579 ret_val = hw->mac.ops.setup_physical_interface(hw);
580 if (ret_val)
581 goto out;
582
583 /*
584 * Initialize the flow control address, type, and PAUSE timer
585 * registers to their default values. This is done even if flow
586 * control is disabled, because it does not hurt anything to
587 * initialize these registers.
588 */
589 hw_dbg("Initializing the Flow Control address, type and timer regs\n");
590 wr32(E1000_FCT, FLOW_CONTROL_TYPE);
591 wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
592 wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
593
594 wr32(E1000_FCTTV, hw->fc.pause_time);
595
596 ret_val = igb_set_fc_watermarks(hw);
597
598out:
599 return ret_val;
600}
601
602/**
603 * igb_config_collision_dist - Configure collision distance
604 * @hw: pointer to the HW structure
605 *
606 * Configures the collision distance to the default value and is used
607 * during link setup. Currently no func pointer exists and all
608 * implementations are handled in the generic version of this function.
609 **/
610void igb_config_collision_dist(struct e1000_hw *hw)
611{
612 u32 tctl;
613
614 tctl = rd32(E1000_TCTL);
615
616 tctl &= ~E1000_TCTL_COLD;
617 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
618
619 wr32(E1000_TCTL, tctl);
620 wrfl();
621}
622
623/**
624 * igb_set_fc_watermarks - Set flow control high/low watermarks
625 * @hw: pointer to the HW structure
626 *
627 * Sets the flow control high/low threshold (watermark) registers. If
628 * flow control XON frame transmission is enabled, then set XON frame
629 * tansmission as well.
630 **/
631static s32 igb_set_fc_watermarks(struct e1000_hw *hw)
632{
633 s32 ret_val = 0;
634 u32 fcrtl = 0, fcrth = 0;
635
636 /*
637 * Set the flow control receive threshold registers. Normally,
638 * these registers will be set to a default threshold that may be
639 * adjusted later by the driver's runtime code. However, if the
640 * ability to transmit pause frames is not enabled, then these
641 * registers will be set to 0.
642 */
643 if (hw->fc.current_mode & e1000_fc_tx_pause) {
644 /*
645 * We need to set up the Receive Threshold high and low water
646 * marks as well as (optionally) enabling the transmission of
647 * XON frames.
648 */
649 fcrtl = hw->fc.low_water;
650 if (hw->fc.send_xon)
651 fcrtl |= E1000_FCRTL_XONE;
652
653 fcrth = hw->fc.high_water;
654 }
655 wr32(E1000_FCRTL, fcrtl);
656 wr32(E1000_FCRTH, fcrth);
657
658 return ret_val;
659}
660
661/**
662 * igb_set_default_fc - Set flow control default values
663 * @hw: pointer to the HW structure
664 *
665 * Read the EEPROM for the default values for flow control and store the
666 * values.
667 **/
668static s32 igb_set_default_fc(struct e1000_hw *hw)
669{
670 s32 ret_val = 0;
671 u16 nvm_data;
672
673 /*
674 * Read and store word 0x0F of the EEPROM. This word contains bits
675 * that determine the hardware's default PAUSE (flow control) mode,
676 * a bit that determines whether the HW defaults to enabling or
677 * disabling auto-negotiation, and the direction of the
678 * SW defined pins. If there is no SW over-ride of the flow
679 * control setting, then the variable hw->fc will
680 * be initialized based on a value in the EEPROM.
681 */
682 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
683
684 if (ret_val) {
685 hw_dbg("NVM Read Error\n");
686 goto out;
687 }
688
689 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
690 hw->fc.requested_mode = e1000_fc_none;
691 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
692 NVM_WORD0F_ASM_DIR)
693 hw->fc.requested_mode = e1000_fc_tx_pause;
694 else
695 hw->fc.requested_mode = e1000_fc_full;
696
697out:
698 return ret_val;
699}
700
701/**
702 * igb_force_mac_fc - Force the MAC's flow control settings
703 * @hw: pointer to the HW structure
704 *
705 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
706 * device control register to reflect the adapter settings. TFCE and RFCE
707 * need to be explicitly set by software when a copper PHY is used because
708 * autonegotiation is managed by the PHY rather than the MAC. Software must
709 * also configure these bits when link is forced on a fiber connection.
710 **/
711s32 igb_force_mac_fc(struct e1000_hw *hw)
712{
713 u32 ctrl;
714 s32 ret_val = 0;
715
716 ctrl = rd32(E1000_CTRL);
717
718 /*
719 * Because we didn't get link via the internal auto-negotiation
720 * mechanism (we either forced link or we got link via PHY
721 * auto-neg), we have to manually enable/disable transmit an
722 * receive flow control.
723 *
724 * The "Case" statement below enables/disable flow control
725 * according to the "hw->fc.current_mode" parameter.
726 *
727 * The possible values of the "fc" parameter are:
728 * 0: Flow control is completely disabled
729 * 1: Rx flow control is enabled (we can receive pause
730 * frames but not send pause frames).
731 * 2: Tx flow control is enabled (we can send pause frames
732 * frames but we do not receive pause frames).
733 * 3: Both Rx and TX flow control (symmetric) is enabled.
734 * other: No other values should be possible at this point.
735 */
736 hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
737
738 switch (hw->fc.current_mode) {
739 case e1000_fc_none:
740 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
741 break;
742 case e1000_fc_rx_pause:
743 ctrl &= (~E1000_CTRL_TFCE);
744 ctrl |= E1000_CTRL_RFCE;
745 break;
746 case e1000_fc_tx_pause:
747 ctrl &= (~E1000_CTRL_RFCE);
748 ctrl |= E1000_CTRL_TFCE;
749 break;
750 case e1000_fc_full:
751 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
752 break;
753 default:
754 hw_dbg("Flow control param set incorrectly\n");
755 ret_val = -E1000_ERR_CONFIG;
756 goto out;
757 }
758
759 wr32(E1000_CTRL, ctrl);
760
761out:
762 return ret_val;
763}
764
765/**
766 * igb_config_fc_after_link_up - Configures flow control after link
767 * @hw: pointer to the HW structure
768 *
769 * Checks the status of auto-negotiation after link up to ensure that the
770 * speed and duplex were not forced. If the link needed to be forced, then
771 * flow control needs to be forced also. If auto-negotiation is enabled
772 * and did not fail, then we configure flow control based on our link
773 * partner.
774 **/
775s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
776{
777 struct e1000_mac_info *mac = &hw->mac;
778 s32 ret_val = 0;
779 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
780 u16 speed, duplex;
781
782 /*
783 * Check for the case where we have fiber media and auto-neg failed
784 * so we had to force link. In this case, we need to force the
785 * configuration of the MAC to match the "fc" parameter.
786 */
787 if (mac->autoneg_failed) {
788 if (hw->phy.media_type == e1000_media_type_internal_serdes)
789 ret_val = igb_force_mac_fc(hw);
790 } else {
791 if (hw->phy.media_type == e1000_media_type_copper)
792 ret_val = igb_force_mac_fc(hw);
793 }
794
795 if (ret_val) {
796 hw_dbg("Error forcing flow control settings\n");
797 goto out;
798 }
799
800 /*
801 * Check for the case where we have copper media and auto-neg is
802 * enabled. In this case, we need to check and see if Auto-Neg
803 * has completed, and if so, how the PHY and link partner has
804 * flow control configured.
805 */
806 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
807 /*
808 * Read the MII Status Register and check to see if AutoNeg
809 * has completed. We read this twice because this reg has
810 * some "sticky" (latched) bits.
811 */
812 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
813 &mii_status_reg);
814 if (ret_val)
815 goto out;
816 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
817 &mii_status_reg);
818 if (ret_val)
819 goto out;
820
821 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
822 hw_dbg("Copper PHY and Auto Neg "
823 "has not completed.\n");
824 goto out;
825 }
826
827 /*
828 * The AutoNeg process has completed, so we now need to
829 * read both the Auto Negotiation Advertisement
830 * Register (Address 4) and the Auto_Negotiation Base
831 * Page Ability Register (Address 5) to determine how
832 * flow control was negotiated.
833 */
834 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
835 &mii_nway_adv_reg);
836 if (ret_val)
837 goto out;
838 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
839 &mii_nway_lp_ability_reg);
840 if (ret_val)
841 goto out;
842
843 /*
844 * Two bits in the Auto Negotiation Advertisement Register
845 * (Address 4) and two bits in the Auto Negotiation Base
846 * Page Ability Register (Address 5) determine flow control
847 * for both the PHY and the link partner. The following
848 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
849 * 1999, describes these PAUSE resolution bits and how flow
850 * control is determined based upon these settings.
851 * NOTE: DC = Don't Care
852 *
853 * LOCAL DEVICE | LINK PARTNER
854 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
855 *-------|---------|-------|---------|--------------------
856 * 0 | 0 | DC | DC | e1000_fc_none
857 * 0 | 1 | 0 | DC | e1000_fc_none
858 * 0 | 1 | 1 | 0 | e1000_fc_none
859 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
860 * 1 | 0 | 0 | DC | e1000_fc_none
861 * 1 | DC | 1 | DC | e1000_fc_full
862 * 1 | 1 | 0 | 0 | e1000_fc_none
863 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
864 *
865 * Are both PAUSE bits set to 1? If so, this implies
866 * Symmetric Flow Control is enabled at both ends. The
867 * ASM_DIR bits are irrelevant per the spec.
868 *
869 * For Symmetric Flow Control:
870 *
871 * LOCAL DEVICE | LINK PARTNER
872 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
873 *-------|---------|-------|---------|--------------------
874 * 1 | DC | 1 | DC | E1000_fc_full
875 *
876 */
877 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
878 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
879 /*
880 * Now we need to check if the user selected RX ONLY
881 * of pause frames. In this case, we had to advertise
882 * FULL flow control because we could not advertise RX
883 * ONLY. Hence, we must now check to see if we need to
884 * turn OFF the TRANSMISSION of PAUSE frames.
885 */
886 if (hw->fc.requested_mode == e1000_fc_full) {
887 hw->fc.current_mode = e1000_fc_full;
888 hw_dbg("Flow Control = FULL.\r\n");
889 } else {
890 hw->fc.current_mode = e1000_fc_rx_pause;
891 hw_dbg("Flow Control = "
892 "RX PAUSE frames only.\r\n");
893 }
894 }
895 /*
896 * For receiving PAUSE frames ONLY.
897 *
898 * LOCAL DEVICE | LINK PARTNER
899 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
900 *-------|---------|-------|---------|--------------------
901 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
902 */
903 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
904 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
905 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
906 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
907 hw->fc.current_mode = e1000_fc_tx_pause;
908 hw_dbg("Flow Control = TX PAUSE frames only.\r\n");
909 }
910 /*
911 * For transmitting PAUSE frames ONLY.
912 *
913 * LOCAL DEVICE | LINK PARTNER
914 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
915 *-------|---------|-------|---------|--------------------
916 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
917 */
918 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
919 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
920 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
921 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
922 hw->fc.current_mode = e1000_fc_rx_pause;
923 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
924 }
925 /*
926 * Per the IEEE spec, at this point flow control should be
927 * disabled. However, we want to consider that we could
928 * be connected to a legacy switch that doesn't advertise
929 * desired flow control, but can be forced on the link
930 * partner. So if we advertised no flow control, that is
931 * what we will resolve to. If we advertised some kind of
932 * receive capability (Rx Pause Only or Full Flow Control)
933 * and the link partner advertised none, we will configure
934 * ourselves to enable Rx Flow Control only. We can do
935 * this safely for two reasons: If the link partner really
936 * didn't want flow control enabled, and we enable Rx, no
937 * harm done since we won't be receiving any PAUSE frames
938 * anyway. If the intent on the link partner was to have
939 * flow control enabled, then by us enabling RX only, we
940 * can at least receive pause frames and process them.
941 * This is a good idea because in most cases, since we are
942 * predominantly a server NIC, more times than not we will
943 * be asked to delay transmission of packets than asking
944 * our link partner to pause transmission of frames.
945 */
946 else if ((hw->fc.requested_mode == e1000_fc_none ||
947 hw->fc.requested_mode == e1000_fc_tx_pause) ||
948 hw->fc.strict_ieee) {
949 hw->fc.current_mode = e1000_fc_none;
950 hw_dbg("Flow Control = NONE.\r\n");
951 } else {
952 hw->fc.current_mode = e1000_fc_rx_pause;
953 hw_dbg("Flow Control = RX PAUSE frames only.\r\n");
954 }
955
956 /*
957 * Now we need to do one last check... If we auto-
958 * negotiated to HALF DUPLEX, flow control should not be
959 * enabled per IEEE 802.3 spec.
960 */
961 ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
962 if (ret_val) {
963 hw_dbg("Error getting link speed and duplex\n");
964 goto out;
965 }
966
967 if (duplex == HALF_DUPLEX)
968 hw->fc.current_mode = e1000_fc_none;
969
970 /*
971 * Now we call a subroutine to actually force the MAC
972 * controller to use the correct flow control settings.
973 */
974 ret_val = igb_force_mac_fc(hw);
975 if (ret_val) {
976 hw_dbg("Error forcing flow control settings\n");
977 goto out;
978 }
979 }
980
981out:
982 return ret_val;
983}
984
985/**
986 * igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
987 * @hw: pointer to the HW structure
988 * @speed: stores the current speed
989 * @duplex: stores the current duplex
990 *
991 * Read the status register for the current speed/duplex and store the current
992 * speed and duplex for copper connections.
993 **/
994s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
995 u16 *duplex)
996{
997 u32 status;
998
999 status = rd32(E1000_STATUS);
1000 if (status & E1000_STATUS_SPEED_1000) {
1001 *speed = SPEED_1000;
1002 hw_dbg("1000 Mbs, ");
1003 } else if (status & E1000_STATUS_SPEED_100) {
1004 *speed = SPEED_100;
1005 hw_dbg("100 Mbs, ");
1006 } else {
1007 *speed = SPEED_10;
1008 hw_dbg("10 Mbs, ");
1009 }
1010
1011 if (status & E1000_STATUS_FD) {
1012 *duplex = FULL_DUPLEX;
1013 hw_dbg("Full Duplex\n");
1014 } else {
1015 *duplex = HALF_DUPLEX;
1016 hw_dbg("Half Duplex\n");
1017 }
1018
1019 return 0;
1020}
1021
1022/**
1023 * igb_get_hw_semaphore - Acquire hardware semaphore
1024 * @hw: pointer to the HW structure
1025 *
1026 * Acquire the HW semaphore to access the PHY or NVM
1027 **/
1028s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1029{
1030 u32 swsm;
1031 s32 ret_val = 0;
1032 s32 timeout = hw->nvm.word_size + 1;
1033 s32 i = 0;
1034
1035 /* Get the SW semaphore */
1036 while (i < timeout) {
1037 swsm = rd32(E1000_SWSM);
1038 if (!(swsm & E1000_SWSM_SMBI))
1039 break;
1040
1041 udelay(50);
1042 i++;
1043 }
1044
1045 if (i == timeout) {
1046 hw_dbg("Driver can't access device - SMBI bit is set.\n");
1047 ret_val = -E1000_ERR_NVM;
1048 goto out;
1049 }
1050
1051 /* Get the FW semaphore. */
1052 for (i = 0; i < timeout; i++) {
1053 swsm = rd32(E1000_SWSM);
1054 wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1055
1056 /* Semaphore acquired if bit latched */
1057 if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
1058 break;
1059
1060 udelay(50);
1061 }
1062
1063 if (i == timeout) {
1064 /* Release semaphores */
1065 igb_put_hw_semaphore(hw);
1066 hw_dbg("Driver can't access the NVM\n");
1067 ret_val = -E1000_ERR_NVM;
1068 goto out;
1069 }
1070
1071out:
1072 return ret_val;
1073}
1074
1075/**
1076 * igb_put_hw_semaphore - Release hardware semaphore
1077 * @hw: pointer to the HW structure
1078 *
1079 * Release hardware semaphore used to access the PHY or NVM
1080 **/
1081void igb_put_hw_semaphore(struct e1000_hw *hw)
1082{
1083 u32 swsm;
1084
1085 swsm = rd32(E1000_SWSM);
1086
1087 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1088
1089 wr32(E1000_SWSM, swsm);
1090}
1091
1092/**
1093 * igb_get_auto_rd_done - Check for auto read completion
1094 * @hw: pointer to the HW structure
1095 *
1096 * Check EEPROM for Auto Read done bit.
1097 **/
1098s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1099{
1100 s32 i = 0;
1101 s32 ret_val = 0;
1102
1103
1104 while (i < AUTO_READ_DONE_TIMEOUT) {
1105 if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
1106 break;
1107 msleep(1);
1108 i++;
1109 }
1110
1111 if (i == AUTO_READ_DONE_TIMEOUT) {
1112 hw_dbg("Auto read by HW from NVM has not completed.\n");
1113 ret_val = -E1000_ERR_RESET;
1114 goto out;
1115 }
1116
1117out:
1118 return ret_val;
1119}
1120
1121/**
1122 * igb_valid_led_default - Verify a valid default LED config
1123 * @hw: pointer to the HW structure
1124 * @data: pointer to the NVM (EEPROM)
1125 *
1126 * Read the EEPROM for the current default LED configuration. If the
1127 * LED configuration is not valid, set to a valid LED configuration.
1128 **/
1129static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1130{
1131 s32 ret_val;
1132
1133 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1134 if (ret_val) {
1135 hw_dbg("NVM Read Error\n");
1136 goto out;
1137 }
1138
1139 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1140 switch(hw->phy.media_type) {
1141 case e1000_media_type_internal_serdes:
1142 *data = ID_LED_DEFAULT_82575_SERDES;
1143 break;
1144 case e1000_media_type_copper:
1145 default:
1146 *data = ID_LED_DEFAULT;
1147 break;
1148 }
1149 }
1150out:
1151 return ret_val;
1152}
1153
1154/**
1155 * igb_id_led_init -
1156 * @hw: pointer to the HW structure
1157 *
1158 **/
1159s32 igb_id_led_init(struct e1000_hw *hw)
1160{
1161 struct e1000_mac_info *mac = &hw->mac;
1162 s32 ret_val;
1163 const u32 ledctl_mask = 0x000000FF;
1164 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1165 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1166 u16 data, i, temp;
1167 const u16 led_mask = 0x0F;
1168
1169 ret_val = igb_valid_led_default(hw, &data);
1170 if (ret_val)
1171 goto out;
1172
1173 mac->ledctl_default = rd32(E1000_LEDCTL);
1174 mac->ledctl_mode1 = mac->ledctl_default;
1175 mac->ledctl_mode2 = mac->ledctl_default;
1176
1177 for (i = 0; i < 4; i++) {
1178 temp = (data >> (i << 2)) & led_mask;
1179 switch (temp) {
1180 case ID_LED_ON1_DEF2:
1181 case ID_LED_ON1_ON2:
1182 case ID_LED_ON1_OFF2:
1183 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1184 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1185 break;
1186 case ID_LED_OFF1_DEF2:
1187 case ID_LED_OFF1_ON2:
1188 case ID_LED_OFF1_OFF2:
1189 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1190 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1191 break;
1192 default:
1193 /* Do nothing */
1194 break;
1195 }
1196 switch (temp) {
1197 case ID_LED_DEF1_ON2:
1198 case ID_LED_ON1_ON2:
1199 case ID_LED_OFF1_ON2:
1200 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1201 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1202 break;
1203 case ID_LED_DEF1_OFF2:
1204 case ID_LED_ON1_OFF2:
1205 case ID_LED_OFF1_OFF2:
1206 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1207 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1208 break;
1209 default:
1210 /* Do nothing */
1211 break;
1212 }
1213 }
1214
1215out:
1216 return ret_val;
1217}
1218
1219/**
1220 * igb_cleanup_led - Set LED config to default operation
1221 * @hw: pointer to the HW structure
1222 *
1223 * Remove the current LED configuration and set the LED configuration
1224 * to the default value, saved from the EEPROM.
1225 **/
1226s32 igb_cleanup_led(struct e1000_hw *hw)
1227{
1228 wr32(E1000_LEDCTL, hw->mac.ledctl_default);
1229 return 0;
1230}
1231
1232/**
1233 * igb_blink_led - Blink LED
1234 * @hw: pointer to the HW structure
1235 *
1236 * Blink the led's which are set to be on.
1237 **/
1238s32 igb_blink_led(struct e1000_hw *hw)
1239{
1240 u32 ledctl_blink = 0;
1241 u32 i;
1242
1243 /*
1244 * set the blink bit for each LED that's "on" (0x0E)
1245 * in ledctl_mode2
1246 */
1247 ledctl_blink = hw->mac.ledctl_mode2;
1248 for (i = 0; i < 4; i++)
1249 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1250 E1000_LEDCTL_MODE_LED_ON)
1251 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1252 (i * 8));
1253
1254 wr32(E1000_LEDCTL, ledctl_blink);
1255
1256 return 0;
1257}
1258
1259/**
1260 * igb_led_off - Turn LED off
1261 * @hw: pointer to the HW structure
1262 *
1263 * Turn LED off.
1264 **/
1265s32 igb_led_off(struct e1000_hw *hw)
1266{
1267 switch (hw->phy.media_type) {
1268 case e1000_media_type_copper:
1269 wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
1270 break;
1271 default:
1272 break;
1273 }
1274
1275 return 0;
1276}
1277
1278/**
1279 * igb_disable_pcie_master - Disables PCI-express master access
1280 * @hw: pointer to the HW structure
1281 *
1282 * Returns 0 (0) if successful, else returns -10
1283 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not casued
1284 * the master requests to be disabled.
1285 *
1286 * Disables PCI-Express master access and verifies there are no pending
1287 * requests.
1288 **/
1289s32 igb_disable_pcie_master(struct e1000_hw *hw)
1290{
1291 u32 ctrl;
1292 s32 timeout = MASTER_DISABLE_TIMEOUT;
1293 s32 ret_val = 0;
1294
1295 if (hw->bus.type != e1000_bus_type_pci_express)
1296 goto out;
1297
1298 ctrl = rd32(E1000_CTRL);
1299 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1300 wr32(E1000_CTRL, ctrl);
1301
1302 while (timeout) {
1303 if (!(rd32(E1000_STATUS) &
1304 E1000_STATUS_GIO_MASTER_ENABLE))
1305 break;
1306 udelay(100);
1307 timeout--;
1308 }
1309
1310 if (!timeout) {
1311 hw_dbg("Master requests are pending.\n");
1312 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1313 goto out;
1314 }
1315
1316out:
1317 return ret_val;
1318}
1319
1320/**
1321 * igb_validate_mdi_setting - Verify MDI/MDIx settings
1322 * @hw: pointer to the HW structure
1323 *
1324 * Verify that when not using auto-negotitation that MDI/MDIx is correctly
1325 * set, which is forced to MDI mode only.
1326 **/
1327s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1328{
1329 s32 ret_val = 0;
1330
1331 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1332 hw_dbg("Invalid MDI setting detected\n");
1333 hw->phy.mdix = 1;
1334 ret_val = -E1000_ERR_CONFIG;
1335 goto out;
1336 }
1337
1338out:
1339 return ret_val;
1340}
1341
1342/**
1343 * igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1344 * @hw: pointer to the HW structure
1345 * @reg: 32bit register offset such as E1000_SCTL
1346 * @offset: register offset to write to
1347 * @data: data to write at register offset
1348 *
1349 * Writes an address/data control type register. There are several of these
1350 * and they all have the format address << 8 | data and bit 31 is polled for
1351 * completion.
1352 **/
1353s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1354 u32 offset, u8 data)
1355{
1356 u32 i, regvalue = 0;
1357 s32 ret_val = 0;
1358
1359 /* Set up the address and data */
1360 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1361 wr32(reg, regvalue);
1362
1363 /* Poll the ready bit to see if the MDI read completed */
1364 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1365 udelay(5);
1366 regvalue = rd32(reg);
1367 if (regvalue & E1000_GEN_CTL_READY)
1368 break;
1369 }
1370 if (!(regvalue & E1000_GEN_CTL_READY)) {
1371 hw_dbg("Reg %08x did not indicate ready\n", reg);
1372 ret_val = -E1000_ERR_PHY;
1373 goto out;
1374 }
1375
1376out:
1377 return ret_val;
1378}
1379
1380/**
1381 * igb_enable_mng_pass_thru - Enable processing of ARP's
1382 * @hw: pointer to the HW structure
1383 *
1384 * Verifies the hardware needs to leave interface enabled so that frames can
1385 * be directed to and from the management interface.
1386 **/
1387bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
1388{
1389 u32 manc;
1390 u32 fwsm, factps;
1391 bool ret_val = false;
1392
1393 if (!hw->mac.asf_firmware_present)
1394 goto out;
1395
1396 manc = rd32(E1000_MANC);
1397
1398 if (!(manc & E1000_MANC_RCV_TCO_EN))
1399 goto out;
1400
1401 if (hw->mac.arc_subsystem_valid) {
1402 fwsm = rd32(E1000_FWSM);
1403 factps = rd32(E1000_FACTPS);
1404
1405 if (!(factps & E1000_FACTPS_MNGCG) &&
1406 ((fwsm & E1000_FWSM_MODE_MASK) ==
1407 (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
1408 ret_val = true;
1409 goto out;
1410 }
1411 } else {
1412 if ((manc & E1000_MANC_SMBUS_EN) &&
1413 !(manc & E1000_MANC_ASF_EN)) {
1414 ret_val = true;
1415 goto out;
1416 }
1417 }
1418
1419out:
1420 return ret_val;
1421}