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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Copyright (c) 2018, Intel Corporation. */
3
4#ifndef _ICE_ADMINQ_CMD_H_
5#define _ICE_ADMINQ_CMD_H_
6
7/* This header file defines the Admin Queue commands, error codes and
8 * descriptor format. It is shared between Firmware and Software.
9 */
10
11#define ICE_MAX_VSI 768
12#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
13#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
14
15struct ice_aqc_generic {
16 __le32 param0;
17 __le32 param1;
18 __le32 addr_high;
19 __le32 addr_low;
20};
21
22/* Get version (direct 0x0001) */
23struct ice_aqc_get_ver {
24 __le32 rom_ver;
25 __le32 fw_build;
26 u8 fw_branch;
27 u8 fw_major;
28 u8 fw_minor;
29 u8 fw_patch;
30 u8 api_branch;
31 u8 api_major;
32 u8 api_minor;
33 u8 api_patch;
34};
35
36/* Send driver version (indirect 0x0002) */
37struct ice_aqc_driver_ver {
38 u8 major_ver;
39 u8 minor_ver;
40 u8 build_ver;
41 u8 subbuild_ver;
42 u8 reserved[4];
43 __le32 addr_high;
44 __le32 addr_low;
45};
46
47/* Queue Shutdown (direct 0x0003) */
48struct ice_aqc_q_shutdown {
49 u8 driver_unloading;
50#define ICE_AQC_DRIVER_UNLOADING BIT(0)
51 u8 reserved[15];
52};
53
54/* Request resource ownership (direct 0x0008)
55 * Release resource ownership (direct 0x0009)
56 */
57struct ice_aqc_req_res {
58 __le16 res_id;
59#define ICE_AQC_RES_ID_NVM 1
60#define ICE_AQC_RES_ID_SDP 2
61#define ICE_AQC_RES_ID_CHNG_LOCK 3
62#define ICE_AQC_RES_ID_GLBL_LOCK 4
63 __le16 access_type;
64#define ICE_AQC_RES_ACCESS_READ 1
65#define ICE_AQC_RES_ACCESS_WRITE 2
66
67 /* Upon successful completion, FW writes this value and driver is
68 * expected to release resource before timeout. This value is provided
69 * in milliseconds.
70 */
71 __le32 timeout;
72#define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000
73#define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000
74#define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000
75#define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000
76 /* For SDP: pin ID of the SDP */
77 __le32 res_number;
78 /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */
79 __le16 status;
80#define ICE_AQ_RES_GLBL_SUCCESS 0
81#define ICE_AQ_RES_GLBL_IN_PROG 1
82#define ICE_AQ_RES_GLBL_DONE 2
83 u8 reserved[2];
84};
85
86/* Get function capabilities (indirect 0x000A)
87 * Get device capabilities (indirect 0x000B)
88 */
89struct ice_aqc_list_caps {
90 u8 cmd_flags;
91 u8 pf_index;
92 u8 reserved[2];
93 __le32 count;
94 __le32 addr_high;
95 __le32 addr_low;
96};
97
98/* Device/Function buffer entry, repeated per reported capability */
99struct ice_aqc_list_caps_elem {
100 __le16 cap;
101#define ICE_AQC_CAPS_VALID_FUNCTIONS 0x0005
102#define ICE_AQC_CAPS_SRIOV 0x0012
103#define ICE_AQC_CAPS_VF 0x0013
104#define ICE_AQC_CAPS_VSI 0x0017
105#define ICE_AQC_CAPS_DCB 0x0018
106#define ICE_AQC_CAPS_RSS 0x0040
107#define ICE_AQC_CAPS_RXQS 0x0041
108#define ICE_AQC_CAPS_TXQS 0x0042
109#define ICE_AQC_CAPS_MSIX 0x0043
110#define ICE_AQC_CAPS_FD 0x0045
111#define ICE_AQC_CAPS_1588 0x0046
112#define ICE_AQC_CAPS_MAX_MTU 0x0047
113#define ICE_AQC_CAPS_NVM_VER 0x0048
114#define ICE_AQC_CAPS_PENDING_NVM_VER 0x0049
115#define ICE_AQC_CAPS_OROM_VER 0x004A
116#define ICE_AQC_CAPS_PENDING_OROM_VER 0x004B
117#define ICE_AQC_CAPS_NET_VER 0x004C
118#define ICE_AQC_CAPS_PENDING_NET_VER 0x004D
119#define ICE_AQC_CAPS_RDMA 0x0051
120#define ICE_AQC_CAPS_PCIE_RESET_AVOIDANCE 0x0076
121#define ICE_AQC_CAPS_POST_UPDATE_RESET_RESTRICT 0x0077
122#define ICE_AQC_CAPS_NVM_MGMT 0x0080
123
124 u8 major_ver;
125 u8 minor_ver;
126 /* Number of resources described by this capability */
127 __le32 number;
128 /* Only meaningful for some types of resources */
129 __le32 logical_id;
130 /* Only meaningful for some types of resources */
131 __le32 phys_id;
132 __le64 rsvd1;
133 __le64 rsvd2;
134};
135
136/* Manage MAC address, read command - indirect (0x0107)
137 * This struct is also used for the response
138 */
139struct ice_aqc_manage_mac_read {
140 __le16 flags; /* Zeroed by device driver */
141#define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4)
142#define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5)
143#define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6)
144#define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7)
145#define ICE_AQC_MAN_MAC_READ_S 4
146#define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S)
147 u8 rsvd[2];
148 u8 num_addr; /* Used in response */
149 u8 rsvd1[3];
150 __le32 addr_high;
151 __le32 addr_low;
152};
153
154/* Response buffer format for manage MAC read command */
155struct ice_aqc_manage_mac_read_resp {
156 u8 lport_num;
157 u8 addr_type;
158#define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0
159#define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1
160 u8 mac_addr[ETH_ALEN];
161};
162
163/* Manage MAC address, write command - direct (0x0108) */
164struct ice_aqc_manage_mac_write {
165 u8 rsvd;
166 u8 flags;
167#define ICE_AQC_MAN_MAC_WR_MC_MAG_EN BIT(0)
168#define ICE_AQC_MAN_MAC_WR_WOL_LAA_PFR_KEEP BIT(1)
169#define ICE_AQC_MAN_MAC_WR_S 6
170#define ICE_AQC_MAN_MAC_WR_M ICE_M(3, ICE_AQC_MAN_MAC_WR_S)
171#define ICE_AQC_MAN_MAC_UPDATE_LAA 0
172#define ICE_AQC_MAN_MAC_UPDATE_LAA_WOL BIT(ICE_AQC_MAN_MAC_WR_S)
173 /* byte stream in network order */
174 u8 mac_addr[ETH_ALEN];
175 __le32 addr_high;
176 __le32 addr_low;
177};
178
179/* Clear PXE Command and response (direct 0x0110) */
180struct ice_aqc_clear_pxe {
181 u8 rx_cnt;
182#define ICE_AQC_CLEAR_PXE_RX_CNT 0x2
183 u8 reserved[15];
184};
185
186/* Get switch configuration (0x0200) */
187struct ice_aqc_get_sw_cfg {
188 /* Reserved for command and copy of request flags for response */
189 __le16 flags;
190 /* First desc in case of command and next_elem in case of response
191 * In case of response, if it is not zero, means all the configuration
192 * was not returned and new command shall be sent with this value in
193 * the 'first desc' field
194 */
195 __le16 element;
196 /* Reserved for command, only used for response */
197 __le16 num_elems;
198 __le16 rsvd;
199 __le32 addr_high;
200 __le32 addr_low;
201};
202
203/* Each entry in the response buffer is of the following type: */
204struct ice_aqc_get_sw_cfg_resp_elem {
205 /* VSI/Port Number */
206 __le16 vsi_port_num;
207#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0
208#define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \
209 (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S)
210#define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14
211#define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S)
212#define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0
213#define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1
214#define ICE_AQC_GET_SW_CONF_RESP_VSI 2
215
216 /* SWID VSI/Port belongs to */
217 __le16 swid;
218
219 /* Bit 14..0 : PF/VF number VSI belongs to
220 * Bit 15 : VF indication bit
221 */
222 __le16 pf_vf_num;
223#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0
224#define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \
225 (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S)
226#define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15)
227};
228
229/* Set Port parameters, (direct, 0x0203) */
230struct ice_aqc_set_port_params {
231 __le16 cmd_flags;
232#define ICE_AQC_SET_P_PARAMS_DOUBLE_VLAN_ENA BIT(2)
233 __le16 bad_frame_vsi;
234 __le16 swid;
235 u8 reserved[10];
236};
237
238/* These resource type defines are used for all switch resource
239 * commands where a resource type is required, such as:
240 * Get Resource Allocation command (indirect 0x0204)
241 * Allocate Resources command (indirect 0x0208)
242 * Free Resources command (indirect 0x0209)
243 * Get Allocated Resource Descriptors Command (indirect 0x020A)
244 */
245#define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03
246#define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04
247#define ICE_AQC_RES_TYPE_RECIPE 0x05
248#define ICE_AQC_RES_TYPE_FDIR_COUNTER_BLOCK 0x21
249#define ICE_AQC_RES_TYPE_FDIR_GUARANTEED_ENTRIES 0x22
250#define ICE_AQC_RES_TYPE_FDIR_SHARED_ENTRIES 0x23
251#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID 0x58
252#define ICE_AQC_RES_TYPE_FD_PROF_BLDR_TCAM 0x59
253#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID 0x60
254#define ICE_AQC_RES_TYPE_HASH_PROF_BLDR_TCAM 0x61
255
256#define ICE_AQC_RES_TYPE_FLAG_SHARED BIT(7)
257#define ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM BIT(12)
258#define ICE_AQC_RES_TYPE_FLAG_IGNORE_INDEX BIT(13)
259
260#define ICE_AQC_RES_TYPE_FLAG_DEDICATED 0x00
261
262#define ICE_AQC_RES_TYPE_S 0
263#define ICE_AQC_RES_TYPE_M (0x07F << ICE_AQC_RES_TYPE_S)
264
265/* Allocate Resources command (indirect 0x0208)
266 * Free Resources command (indirect 0x0209)
267 */
268struct ice_aqc_alloc_free_res_cmd {
269 __le16 num_entries; /* Number of Resource entries */
270 u8 reserved[6];
271 __le32 addr_high;
272 __le32 addr_low;
273};
274
275/* Resource descriptor */
276struct ice_aqc_res_elem {
277 union {
278 __le16 sw_resp;
279 __le16 flu_resp;
280 } e;
281};
282
283/* Buffer for Allocate/Free Resources commands */
284struct ice_aqc_alloc_free_res_elem {
285 __le16 res_type; /* Types defined above cmd 0x0204 */
286#define ICE_AQC_RES_TYPE_SHARED_S 7
287#define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S)
288#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8
289#define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \
290 (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S)
291 __le16 num_elems;
292 struct ice_aqc_res_elem elem[];
293};
294
295/* Request buffer for Set VLAN Mode AQ command (indirect 0x020C) */
296struct ice_aqc_set_vlan_mode {
297 u8 reserved;
298 u8 l2tag_prio_tagging;
299#define ICE_AQ_VLAN_PRIO_TAG_S 0
300#define ICE_AQ_VLAN_PRIO_TAG_M (0x7 << ICE_AQ_VLAN_PRIO_TAG_S)
301#define ICE_AQ_VLAN_PRIO_TAG_NOT_SUPPORTED 0x0
302#define ICE_AQ_VLAN_PRIO_TAG_STAG 0x1
303#define ICE_AQ_VLAN_PRIO_TAG_OUTER_CTAG 0x2
304#define ICE_AQ_VLAN_PRIO_TAG_OUTER_VLAN 0x3
305#define ICE_AQ_VLAN_PRIO_TAG_INNER_CTAG 0x4
306#define ICE_AQ_VLAN_PRIO_TAG_MAX 0x4
307#define ICE_AQ_VLAN_PRIO_TAG_ERROR 0x7
308 u8 l2tag_reserved[64];
309 u8 rdma_packet;
310#define ICE_AQ_VLAN_RDMA_TAG_S 0
311#define ICE_AQ_VLAN_RDMA_TAG_M (0x3F << ICE_AQ_VLAN_RDMA_TAG_S)
312#define ICE_AQ_SVM_VLAN_RDMA_PKT_FLAG_SETTING 0x10
313#define ICE_AQ_DVM_VLAN_RDMA_PKT_FLAG_SETTING 0x1A
314 u8 rdma_reserved[2];
315 u8 mng_vlan_prot_id;
316#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_OUTER 0x10
317#define ICE_AQ_VLAN_MNG_PROTOCOL_ID_INNER 0x11
318 u8 prot_id_reserved[30];
319};
320
321/* Response buffer for Get VLAN Mode AQ command (indirect 0x020D) */
322struct ice_aqc_get_vlan_mode {
323 u8 vlan_mode;
324#define ICE_AQ_VLAN_MODE_DVM_ENA BIT(0)
325 u8 l2tag_prio_tagging;
326 u8 reserved[98];
327};
328
329/* Add VSI (indirect 0x0210)
330 * Update VSI (indirect 0x0211)
331 * Get VSI (indirect 0x0212)
332 * Free VSI (indirect 0x0213)
333 */
334struct ice_aqc_add_get_update_free_vsi {
335 __le16 vsi_num;
336#define ICE_AQ_VSI_NUM_S 0
337#define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S)
338#define ICE_AQ_VSI_IS_VALID BIT(15)
339 __le16 cmd_flags;
340#define ICE_AQ_VSI_KEEP_ALLOC 0x1
341 u8 vf_id;
342 u8 reserved;
343 __le16 vsi_flags;
344#define ICE_AQ_VSI_TYPE_S 0
345#define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S)
346#define ICE_AQ_VSI_TYPE_VF 0x0
347#define ICE_AQ_VSI_TYPE_VMDQ2 0x1
348#define ICE_AQ_VSI_TYPE_PF 0x2
349#define ICE_AQ_VSI_TYPE_EMP_MNG 0x3
350 __le32 addr_high;
351 __le32 addr_low;
352};
353
354/* Response descriptor for:
355 * Add VSI (indirect 0x0210)
356 * Update VSI (indirect 0x0211)
357 * Free VSI (indirect 0x0213)
358 */
359struct ice_aqc_add_update_free_vsi_resp {
360 __le16 vsi_num;
361 __le16 ext_status;
362 __le16 vsi_used;
363 __le16 vsi_free;
364 __le32 addr_high;
365 __le32 addr_low;
366};
367
368struct ice_aqc_vsi_props {
369 __le16 valid_sections;
370#define ICE_AQ_VSI_PROP_SW_VALID BIT(0)
371#define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1)
372#define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2)
373#define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3)
374#define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4)
375#define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5)
376#define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6)
377#define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7)
378#define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8)
379#define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11)
380#define ICE_AQ_VSI_PROP_PASID_VALID BIT(12)
381 /* switch section */
382 u8 sw_id;
383 u8 sw_flags;
384#define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5)
385#define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6)
386#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
387 u8 sw_flags2;
388#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
389#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
390#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
391#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
392 u8 veb_stat_id;
393#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
394#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
395#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
396 /* security section */
397 u8 sec_flags;
398#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
399#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
400#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
401#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
402#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
403 u8 sec_reserved;
404 /* VLAN section */
405 __le16 port_based_inner_vlan; /* VLANS include priority bits */
406 u8 inner_vlan_reserved[2];
407 u8 inner_vlan_flags;
408#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
409#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
410#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
411#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
412#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
413#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
414#define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
415#define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
416#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
417#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
418#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
419#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
420 u8 inner_vlan_reserved2[3];
421 /* ingress egress up sections */
422 __le32 ingress_table; /* bitmap, 3 bits per up */
423#define ICE_AQ_VSI_UP_TABLE_UP0_S 0
424#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
425#define ICE_AQ_VSI_UP_TABLE_UP1_S 3
426#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
427#define ICE_AQ_VSI_UP_TABLE_UP2_S 6
428#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
429#define ICE_AQ_VSI_UP_TABLE_UP3_S 9
430#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
431#define ICE_AQ_VSI_UP_TABLE_UP4_S 12
432#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
433#define ICE_AQ_VSI_UP_TABLE_UP5_S 15
434#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
435#define ICE_AQ_VSI_UP_TABLE_UP6_S 18
436#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
437#define ICE_AQ_VSI_UP_TABLE_UP7_S 21
438#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
439 __le32 egress_table; /* same defines as for ingress table */
440 /* outer tags section */
441 __le16 port_based_outer_vlan;
442 u8 outer_vlan_flags;
443#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
444#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
445#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
446#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
447#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
448#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
449#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
450#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
451#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
452#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
453#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
454#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
455#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
456#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
457#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
458#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
459#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
460#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
461#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
462 u8 outer_vlan_reserved;
463 /* queue mapping section */
464 __le16 mapping_flags;
465#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
466#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
467 __le16 q_mapping[16];
468#define ICE_AQ_VSI_Q_S 0
469#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
470 __le16 tc_mapping[8];
471#define ICE_AQ_VSI_TC_Q_OFFSET_S 0
472#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
473#define ICE_AQ_VSI_TC_Q_NUM_S 11
474#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
475 /* queueing option section */
476 u8 q_opt_rss;
477#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
478#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
479#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
480#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
481#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
482#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
483#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
484#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
485#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
486#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
487#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
488#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
489#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
490 u8 q_opt_tc;
491#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
492#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
493#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
494 u8 q_opt_flags;
495#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
496 u8 q_opt_reserved[3];
497 /* outer up section */
498 __le32 outer_up_table; /* same structure and defines as ingress tbl */
499 /* section 10 */
500 __le16 sect_10_reserved;
501 /* flow director section */
502 __le16 fd_options;
503#define ICE_AQ_VSI_FD_ENABLE BIT(0)
504#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
505#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
506 __le16 max_fd_fltr_dedicated;
507 __le16 max_fd_fltr_shared;
508 __le16 fd_def_q;
509#define ICE_AQ_VSI_FD_DEF_Q_S 0
510#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
511#define ICE_AQ_VSI_FD_DEF_GRP_S 12
512#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
513 __le16 fd_report_opt;
514#define ICE_AQ_VSI_FD_REPORT_Q_S 0
515#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
516#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
517#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
518#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
519 /* PASID section */
520 __le32 pasid_id;
521#define ICE_AQ_VSI_PASID_ID_S 0
522#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
523#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
524 u8 reserved[24];
525};
526
527#define ICE_MAX_NUM_RECIPES 64
528
529/* Add/Get Recipe (indirect 0x0290/0x0292) */
530struct ice_aqc_add_get_recipe {
531 __le16 num_sub_recipes; /* Input in Add cmd, Output in Get cmd */
532 __le16 return_index; /* Input, used for Get cmd only */
533 u8 reserved[4];
534 __le32 addr_high;
535 __le32 addr_low;
536};
537
538struct ice_aqc_recipe_content {
539 u8 rid;
540#define ICE_AQ_RECIPE_ID_S 0
541#define ICE_AQ_RECIPE_ID_M (0x3F << ICE_AQ_RECIPE_ID_S)
542#define ICE_AQ_RECIPE_ID_IS_ROOT BIT(7)
543#define ICE_AQ_SW_ID_LKUP_IDX 0
544 u8 lkup_indx[5];
545#define ICE_AQ_RECIPE_LKUP_DATA_S 0
546#define ICE_AQ_RECIPE_LKUP_DATA_M (0x3F << ICE_AQ_RECIPE_LKUP_DATA_S)
547#define ICE_AQ_RECIPE_LKUP_IGNORE BIT(7)
548#define ICE_AQ_SW_ID_LKUP_MASK 0x00FF
549 __le16 mask[5];
550 u8 result_indx;
551#define ICE_AQ_RECIPE_RESULT_DATA_S 0
552#define ICE_AQ_RECIPE_RESULT_DATA_M (0x3F << ICE_AQ_RECIPE_RESULT_DATA_S)
553#define ICE_AQ_RECIPE_RESULT_EN BIT(7)
554 u8 rsvd0[3];
555 u8 act_ctrl_join_priority;
556 u8 act_ctrl_fwd_priority;
557#define ICE_AQ_RECIPE_FWD_PRIORITY_S 0
558#define ICE_AQ_RECIPE_FWD_PRIORITY_M (0xF << ICE_AQ_RECIPE_FWD_PRIORITY_S)
559 u8 act_ctrl;
560#define ICE_AQ_RECIPE_ACT_NEED_PASS_L2 BIT(0)
561#define ICE_AQ_RECIPE_ACT_ALLOW_PASS_L2 BIT(1)
562#define ICE_AQ_RECIPE_ACT_INV_ACT BIT(2)
563#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_S 4
564#define ICE_AQ_RECIPE_ACT_PRUNE_INDX_M (0x3 << ICE_AQ_RECIPE_ACT_PRUNE_INDX_S)
565 u8 rsvd1;
566 __le32 dflt_act;
567#define ICE_AQ_RECIPE_DFLT_ACT_S 0
568#define ICE_AQ_RECIPE_DFLT_ACT_M (0x7FFFF << ICE_AQ_RECIPE_DFLT_ACT_S)
569#define ICE_AQ_RECIPE_DFLT_ACT_VALID BIT(31)
570};
571
572struct ice_aqc_recipe_data_elem {
573 u8 recipe_indx;
574 u8 resp_bits;
575#define ICE_AQ_RECIPE_WAS_UPDATED BIT(0)
576 u8 rsvd0[2];
577 u8 recipe_bitmap[8];
578 u8 rsvd1[4];
579 struct ice_aqc_recipe_content content;
580 u8 rsvd2[20];
581};
582
583/* Set/Get Recipes to Profile Association (direct 0x0291/0x0293) */
584struct ice_aqc_recipe_to_profile {
585 __le16 profile_id;
586 u8 rsvd[6];
587 DECLARE_BITMAP(recipe_assoc, ICE_MAX_NUM_RECIPES);
588};
589
590/* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3)
591 */
592struct ice_aqc_sw_rules {
593 /* ops: add switch rules, referring the number of rules.
594 * ops: update switch rules, referring the number of filters
595 * ops: remove switch rules, referring the entry index.
596 * ops: get switch rules, referring to the number of filters.
597 */
598 __le16 num_rules_fltr_entry_index;
599 u8 reserved[6];
600 __le32 addr_high;
601 __le32 addr_low;
602};
603
604/* Add switch rule response:
605 * Content of return buffer is same as the input buffer. The status field and
606 * LUT index are updated as part of the response
607 */
608struct ice_aqc_sw_rules_elem_hdr {
609 __le16 type; /* Switch rule type, one of T_... */
610#define ICE_AQC_SW_RULES_T_LKUP_RX 0x0
611#define ICE_AQC_SW_RULES_T_LKUP_TX 0x1
612#define ICE_AQC_SW_RULES_T_LG_ACT 0x2
613#define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3
614#define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4
615#define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5
616#define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6
617 __le16 status;
618} __packed __aligned(sizeof(__le16));
619
620/* Add/Update/Get/Remove lookup Rx/Tx command/response entry
621 * This structures describes the lookup rules and associated actions. "index"
622 * is returned as part of a response to a successful Add command, and can be
623 * used to identify the rule for Update/Get/Remove commands.
624 */
625struct ice_sw_rule_lkup_rx_tx {
626 struct ice_aqc_sw_rules_elem_hdr hdr;
627
628 __le16 recipe_id;
629#define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10
630 /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */
631 __le16 src;
632 __le32 act;
633
634 /* Bit 0:1 - Action type */
635#define ICE_SINGLE_ACT_TYPE_S 0x00
636#define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S)
637
638 /* Bit 2 - Loop back enable
639 * Bit 3 - LAN enable
640 */
641#define ICE_SINGLE_ACT_LB_ENABLE BIT(2)
642#define ICE_SINGLE_ACT_LAN_ENABLE BIT(3)
643
644 /* Action type = 0 - Forward to VSI or VSI list */
645#define ICE_SINGLE_ACT_VSI_FORWARDING 0x0
646
647#define ICE_SINGLE_ACT_VSI_ID_S 4
648#define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S)
649#define ICE_SINGLE_ACT_VSI_LIST_ID_S 4
650#define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S)
651 /* This bit needs to be set if action is forward to VSI list */
652#define ICE_SINGLE_ACT_VSI_LIST BIT(14)
653#define ICE_SINGLE_ACT_VALID_BIT BIT(17)
654#define ICE_SINGLE_ACT_DROP BIT(18)
655
656 /* Action type = 1 - Forward to Queue of Queue group */
657#define ICE_SINGLE_ACT_TO_Q 0x1
658#define ICE_SINGLE_ACT_Q_INDEX_S 4
659#define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S)
660#define ICE_SINGLE_ACT_Q_REGION_S 15
661#define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S)
662#define ICE_SINGLE_ACT_Q_PRIORITY BIT(18)
663
664 /* Action type = 2 - Prune */
665#define ICE_SINGLE_ACT_PRUNE 0x2
666#define ICE_SINGLE_ACT_EGRESS BIT(15)
667#define ICE_SINGLE_ACT_INGRESS BIT(16)
668#define ICE_SINGLE_ACT_PRUNET BIT(17)
669 /* Bit 18 should be set to 0 for this action */
670
671 /* Action type = 2 - Pointer */
672#define ICE_SINGLE_ACT_PTR 0x2
673#define ICE_SINGLE_ACT_PTR_VAL_S 4
674#define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
675 /* Bit 18 should be set to 1 */
676#define ICE_SINGLE_ACT_PTR_BIT BIT(18)
677
678 /* Action type = 3 - Other actions. Last two bits
679 * are other action identifier
680 */
681#define ICE_SINGLE_ACT_OTHER_ACTS 0x3
682#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17
683#define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \
684 (0x3 << ICE_SINGLE_OTHER_ACT_IDENTIFIER_S)
685
686 /* Bit 17:18 - Defines other actions */
687 /* Other action = 0 - Mirror VSI */
688#define ICE_SINGLE_OTHER_ACT_MIRROR 0
689#define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4
690#define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \
691 (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S)
692
693 /* Other action = 3 - Set Stat count */
694#define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3
695#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4
696#define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \
697 (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S)
698
699 __le16 index; /* The index of the rule in the lookup table */
700 /* Length and values of the header to be matched per recipe or
701 * lookup-type
702 */
703 __le16 hdr_len;
704 u8 hdr_data[];
705} __packed __aligned(sizeof(__le16));
706
707/* Add/Update/Remove large action command/response entry
708 * "index" is returned as part of a response to a successful Add command, and
709 * can be used to identify the action for Update/Get/Remove commands.
710 */
711struct ice_sw_rule_lg_act {
712 struct ice_aqc_sw_rules_elem_hdr hdr;
713
714 __le16 index; /* Index in large action table */
715 __le16 size;
716 /* Max number of large actions */
717#define ICE_MAX_LG_ACT 4
718 /* Bit 0:1 - Action type */
719#define ICE_LG_ACT_TYPE_S 0
720#define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S)
721
722 /* Action type = 0 - Forward to VSI or VSI list */
723#define ICE_LG_ACT_VSI_FORWARDING 0
724#define ICE_LG_ACT_VSI_ID_S 3
725#define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S)
726#define ICE_LG_ACT_VSI_LIST_ID_S 3
727#define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S)
728 /* This bit needs to be set if action is forward to VSI list */
729#define ICE_LG_ACT_VSI_LIST BIT(13)
730
731#define ICE_LG_ACT_VALID_BIT BIT(16)
732
733 /* Action type = 1 - Forward to Queue of Queue group */
734#define ICE_LG_ACT_TO_Q 0x1
735#define ICE_LG_ACT_Q_INDEX_S 3
736#define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S)
737#define ICE_LG_ACT_Q_REGION_S 14
738#define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S)
739#define ICE_LG_ACT_Q_PRIORITY_SET BIT(17)
740
741 /* Action type = 2 - Prune */
742#define ICE_LG_ACT_PRUNE 0x2
743#define ICE_LG_ACT_EGRESS BIT(14)
744#define ICE_LG_ACT_INGRESS BIT(15)
745#define ICE_LG_ACT_PRUNET BIT(16)
746
747 /* Action type = 3 - Mirror VSI */
748#define ICE_LG_OTHER_ACT_MIRROR 0x3
749#define ICE_LG_ACT_MIRROR_VSI_ID_S 3
750#define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S)
751
752 /* Action type = 5 - Generic Value */
753#define ICE_LG_ACT_GENERIC 0x5
754#define ICE_LG_ACT_GENERIC_VALUE_S 3
755#define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S)
756#define ICE_LG_ACT_GENERIC_OFFSET_S 19
757#define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S)
758#define ICE_LG_ACT_GENERIC_PRIORITY_S 22
759#define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S)
760#define ICE_LG_ACT_GENERIC_OFF_RX_DESC_PROF_IDX 7
761
762 /* Action = 7 - Set Stat count */
763#define ICE_LG_ACT_STAT_COUNT 0x7
764#define ICE_LG_ACT_STAT_COUNT_S 3
765#define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S)
766 __le32 act[]; /* array of size for actions */
767} __packed __aligned(sizeof(__le16));
768
769/* Add/Update/Remove VSI list command/response entry
770 * "index" is returned as part of a response to a successful Add command, and
771 * can be used to identify the VSI list for Update/Get/Remove commands.
772 */
773struct ice_sw_rule_vsi_list {
774 struct ice_aqc_sw_rules_elem_hdr hdr;
775
776 __le16 index; /* Index of VSI/Prune list */
777 __le16 number_vsi;
778 __le16 vsi[]; /* Array of number_vsi VSI numbers */
779} __packed __aligned(sizeof(__le16));
780
781/* Query PFC Mode (direct 0x0302)
782 * Set PFC Mode (direct 0x0303)
783 */
784struct ice_aqc_set_query_pfc_mode {
785 u8 pfc_mode;
786/* For Query Command response, reserved in all other cases */
787#define ICE_AQC_PFC_VLAN_BASED_PFC 1
788#define ICE_AQC_PFC_DSCP_BASED_PFC 2
789 u8 rsvd[15];
790};
791/* Get Default Topology (indirect 0x0400) */
792struct ice_aqc_get_topo {
793 u8 port_num;
794 u8 num_branches;
795 __le16 reserved1;
796 __le32 reserved2;
797 __le32 addr_high;
798 __le32 addr_low;
799};
800
801/* Update TSE (indirect 0x0403)
802 * Get TSE (indirect 0x0404)
803 * Add TSE (indirect 0x0401)
804 * Delete TSE (indirect 0x040F)
805 * Move TSE (indirect 0x0408)
806 * Suspend Nodes (indirect 0x0409)
807 * Resume Nodes (indirect 0x040A)
808 */
809struct ice_aqc_sched_elem_cmd {
810 __le16 num_elem_req; /* Used by commands */
811 __le16 num_elem_resp; /* Used by responses */
812 __le32 reserved;
813 __le32 addr_high;
814 __le32 addr_low;
815};
816
817struct ice_aqc_txsched_move_grp_info_hdr {
818 __le32 src_parent_teid;
819 __le32 dest_parent_teid;
820 __le16 num_elems;
821 __le16 reserved;
822};
823
824struct ice_aqc_move_elem {
825 struct ice_aqc_txsched_move_grp_info_hdr hdr;
826 __le32 teid[];
827};
828
829struct ice_aqc_elem_info_bw {
830 __le16 bw_profile_idx;
831 __le16 bw_alloc;
832};
833
834struct ice_aqc_txsched_elem {
835 u8 elem_type; /* Special field, reserved for some aq calls */
836#define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0
837#define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1
838#define ICE_AQC_ELEM_TYPE_TC 0x2
839#define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3
840#define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4
841#define ICE_AQC_ELEM_TYPE_LEAF 0x5
842#define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6
843 u8 valid_sections;
844#define ICE_AQC_ELEM_VALID_GENERIC BIT(0)
845#define ICE_AQC_ELEM_VALID_CIR BIT(1)
846#define ICE_AQC_ELEM_VALID_EIR BIT(2)
847#define ICE_AQC_ELEM_VALID_SHARED BIT(3)
848 u8 generic;
849#define ICE_AQC_ELEM_GENERIC_MODE_M 0x1
850#define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1
851#define ICE_AQC_ELEM_GENERIC_PRIO_M GENMASK(3, 1)
852#define ICE_AQC_ELEM_GENERIC_SP_S 0x4
853#define ICE_AQC_ELEM_GENERIC_SP_M GENMASK(4, 4)
854#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5
855#define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \
856 (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S)
857 u8 flags; /* Special field, reserved for some aq calls */
858#define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1
859 struct ice_aqc_elem_info_bw cir_bw;
860 struct ice_aqc_elem_info_bw eir_bw;
861 __le16 srl_id;
862 __le16 reserved2;
863};
864
865struct ice_aqc_txsched_elem_data {
866 __le32 parent_teid;
867 __le32 node_teid;
868 struct ice_aqc_txsched_elem data;
869};
870
871struct ice_aqc_txsched_topo_grp_info_hdr {
872 __le32 parent_teid;
873 __le16 num_elems;
874 __le16 reserved2;
875};
876
877struct ice_aqc_add_elem {
878 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
879 struct ice_aqc_txsched_elem_data generic[];
880};
881
882struct ice_aqc_get_topo_elem {
883 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
884 struct ice_aqc_txsched_elem_data
885 generic[ICE_AQC_TOPO_MAX_LEVEL_NUM];
886};
887
888struct ice_aqc_delete_elem {
889 struct ice_aqc_txsched_topo_grp_info_hdr hdr;
890 __le32 teid[];
891};
892
893/* Query Port ETS (indirect 0x040E)
894 *
895 * This indirect command is used to query port TC node configuration.
896 */
897struct ice_aqc_query_port_ets {
898 __le32 port_teid;
899 __le32 reserved;
900 __le32 addr_high;
901 __le32 addr_low;
902};
903
904struct ice_aqc_port_ets_elem {
905 u8 tc_valid_bits;
906 u8 reserved[3];
907 /* 3 bits for UP per TC 0-7, 4th byte reserved */
908 __le32 up2tc;
909 u8 tc_bw_share[8];
910 __le32 port_eir_prof_id;
911 __le32 port_cir_prof_id;
912 /* 3 bits per Node priority to TC 0-7, 4th byte reserved */
913 __le32 tc_node_prio;
914#define ICE_TC_NODE_PRIO_S 0x4
915 u8 reserved1[4];
916 __le32 tc_node_teid[8]; /* Used for response, reserved in command */
917};
918
919/* Rate limiting profile for
920 * Add RL profile (indirect 0x0410)
921 * Query RL profile (indirect 0x0411)
922 * Remove RL profile (indirect 0x0415)
923 * These indirect commands acts on single or multiple
924 * RL profiles with specified data.
925 */
926struct ice_aqc_rl_profile {
927 __le16 num_profiles;
928 __le16 num_processed; /* Only for response. Reserved in Command. */
929 u8 reserved[4];
930 __le32 addr_high;
931 __le32 addr_low;
932};
933
934struct ice_aqc_rl_profile_elem {
935 u8 level;
936 u8 flags;
937#define ICE_AQC_RL_PROFILE_TYPE_S 0x0
938#define ICE_AQC_RL_PROFILE_TYPE_M (0x3 << ICE_AQC_RL_PROFILE_TYPE_S)
939#define ICE_AQC_RL_PROFILE_TYPE_CIR 0
940#define ICE_AQC_RL_PROFILE_TYPE_EIR 1
941#define ICE_AQC_RL_PROFILE_TYPE_SRL 2
942/* The following flag is used for Query RL Profile Data */
943#define ICE_AQC_RL_PROFILE_INVAL_S 0x7
944#define ICE_AQC_RL_PROFILE_INVAL_M (0x1 << ICE_AQC_RL_PROFILE_INVAL_S)
945
946 __le16 profile_id;
947 __le16 max_burst_size;
948 __le16 rl_multiply;
949 __le16 wake_up_calc;
950 __le16 rl_encode;
951};
952
953/* Query Scheduler Resource Allocation (indirect 0x0412)
954 * This indirect command retrieves the scheduler resources allocated by
955 * EMP Firmware to the given PF.
956 */
957struct ice_aqc_query_txsched_res {
958 u8 reserved[8];
959 __le32 addr_high;
960 __le32 addr_low;
961};
962
963struct ice_aqc_generic_sched_props {
964 __le16 phys_levels;
965 __le16 logical_levels;
966 u8 flattening_bitmap;
967 u8 max_device_cgds;
968 u8 max_pf_cgds;
969 u8 rsvd0;
970 __le16 rdma_qsets;
971 u8 rsvd1[22];
972};
973
974struct ice_aqc_layer_props {
975 u8 logical_layer;
976 u8 chunk_size;
977 __le16 max_device_nodes;
978 __le16 max_pf_nodes;
979 u8 rsvd0[4];
980 __le16 max_sibl_grp_sz;
981 __le16 max_cir_rl_profiles;
982 __le16 max_eir_rl_profiles;
983 __le16 max_srl_profiles;
984 u8 rsvd1[14];
985};
986
987struct ice_aqc_query_txsched_res_resp {
988 struct ice_aqc_generic_sched_props sched_props;
989 struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM];
990};
991
992/* Get PHY capabilities (indirect 0x0600) */
993struct ice_aqc_get_phy_caps {
994 u8 lport_num;
995 u8 reserved;
996 __le16 param0;
997 /* 18.0 - Report qualified modules */
998#define ICE_AQC_GET_PHY_RQM BIT(0)
999 /* 18.1 - 18.3 : Report mode
1000 * 000b - Report NVM capabilities
1001 * 001b - Report topology capabilities
1002 * 010b - Report SW configured
1003 * 100b - Report default capabilities
1004 */
1005#define ICE_AQC_REPORT_MODE_S 1
1006#define ICE_AQC_REPORT_MODE_M (7 << ICE_AQC_REPORT_MODE_S)
1007#define ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA 0
1008#define ICE_AQC_REPORT_TOPO_CAP_MEDIA BIT(1)
1009#define ICE_AQC_REPORT_ACTIVE_CFG BIT(2)
1010#define ICE_AQC_REPORT_DFLT_CFG BIT(3)
1011 __le32 reserved1;
1012 __le32 addr_high;
1013 __le32 addr_low;
1014};
1015
1016/* This is #define of PHY type (Extended):
1017 * The first set of defines is for phy_type_low.
1018 */
1019#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
1020#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
1021#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
1022#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
1023#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
1024#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
1025#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
1026#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
1027#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
1028#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
1029#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
1030#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
1031#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
1032#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
1033#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
1034#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
1035#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
1036#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
1037#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
1038#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
1039#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
1040#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
1041#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
1042#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
1043#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
1044#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
1045#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
1046#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
1047#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
1048#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
1049#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
1050#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
1051#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
1052#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
1053#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
1054#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
1055#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
1056#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
1057#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
1058#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
1059#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
1060#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
1061#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
1062#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
1063#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
1064#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
1065#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
1066#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
1067#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
1068#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
1069#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
1070#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
1071#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
1072#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
1073#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
1074#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
1075#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
1076#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
1077#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
1078#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
1079#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
1080#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
1081#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
1082#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
1083#define ICE_PHY_TYPE_LOW_MAX_INDEX 63
1084/* The second set of defines is for phy_type_high. */
1085#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
1086#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
1087#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
1088#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
1089#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
1090#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
1091
1092struct ice_aqc_get_phy_caps_data {
1093 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1094 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1095 u8 caps;
1096#define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0)
1097#define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1)
1098#define ICE_AQC_PHY_LOW_POWER_MODE BIT(2)
1099#define ICE_AQC_PHY_EN_LINK BIT(3)
1100#define ICE_AQC_PHY_AN_MODE BIT(4)
1101#define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5)
1102#define ICE_AQC_PHY_EN_AUTO_FEC BIT(7)
1103#define ICE_AQC_PHY_CAPS_MASK ICE_M(0xff, 0)
1104 u8 low_power_ctrl_an;
1105#define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0)
1106#define ICE_AQC_PHY_AN_EN_CLAUSE28 BIT(1)
1107#define ICE_AQC_PHY_AN_EN_CLAUSE73 BIT(2)
1108#define ICE_AQC_PHY_AN_EN_CLAUSE37 BIT(3)
1109 __le16 eee_cap;
1110#define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0)
1111#define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1)
1112#define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2)
1113#define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3)
1114#define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4)
1115#define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5)
1116#define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6)
1117 __le16 eeer_value;
1118 u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
1119 u8 phy_fw_ver[8];
1120 u8 link_fec_options;
1121#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0)
1122#define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1)
1123#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
1124#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
1125#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
1126#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
1127#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
1128#define ICE_AQC_PHY_FEC_MASK ICE_M(0xdf, 0)
1129 u8 module_compliance_enforcement;
1130#define ICE_AQC_MOD_ENFORCE_STRICT_MODE BIT(0)
1131 u8 extended_compliance_code;
1132#define ICE_MODULE_TYPE_TOTAL_BYTE 3
1133 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
1134#define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0
1135#define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80
1136#define ICE_AQC_MOD_TYPE_IDENT 1
1137#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0)
1138#define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1)
1139#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4)
1140#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5)
1141#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6)
1142#define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7)
1143#define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0
1144#define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86
1145 u8 qualified_module_count;
1146 u8 rsvd2[7]; /* Bytes 47:41 reserved */
1147#define ICE_AQC_QUAL_MOD_COUNT_MAX 16
1148 struct {
1149 u8 v_oui[3];
1150 u8 rsvd3;
1151 u8 v_part[16];
1152 __le32 v_rev;
1153 __le64 rsvd4;
1154 } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX];
1155};
1156
1157/* Set PHY capabilities (direct 0x0601)
1158 * NOTE: This command must be followed by setup link and restart auto-neg
1159 */
1160struct ice_aqc_set_phy_cfg {
1161 u8 lport_num;
1162 u8 reserved[7];
1163 __le32 addr_high;
1164 __le32 addr_low;
1165};
1166
1167/* Set PHY config command data structure */
1168struct ice_aqc_set_phy_cfg_data {
1169 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1170 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1171 u8 caps;
1172#define ICE_AQ_PHY_ENA_VALID_MASK ICE_M(0xef, 0)
1173#define ICE_AQ_PHY_ENA_TX_PAUSE_ABILITY BIT(0)
1174#define ICE_AQ_PHY_ENA_RX_PAUSE_ABILITY BIT(1)
1175#define ICE_AQ_PHY_ENA_LOW_POWER BIT(2)
1176#define ICE_AQ_PHY_ENA_LINK BIT(3)
1177#define ICE_AQ_PHY_ENA_AUTO_LINK_UPDT BIT(5)
1178#define ICE_AQ_PHY_ENA_LESM BIT(6)
1179#define ICE_AQ_PHY_ENA_AUTO_FEC BIT(7)
1180 u8 low_power_ctrl_an;
1181 __le16 eee_cap; /* Value from ice_aqc_get_phy_caps */
1182 __le16 eeer_value;
1183 u8 link_fec_opt; /* Use defines from ice_aqc_get_phy_caps */
1184 u8 module_compliance_enforcement;
1185};
1186
1187/* Set MAC Config command data structure (direct 0x0603) */
1188struct ice_aqc_set_mac_cfg {
1189 __le16 max_frame_size;
1190 u8 params;
1191#define ICE_AQ_SET_MAC_PACE_S 3
1192#define ICE_AQ_SET_MAC_PACE_M (0xF << ICE_AQ_SET_MAC_PACE_S)
1193#define ICE_AQ_SET_MAC_PACE_TYPE_M BIT(7)
1194#define ICE_AQ_SET_MAC_PACE_TYPE_RATE 0
1195#define ICE_AQ_SET_MAC_PACE_TYPE_FIXED ICE_AQ_SET_MAC_PACE_TYPE_M
1196 u8 tx_tmr_priority;
1197 __le16 tx_tmr_value;
1198 __le16 fc_refresh_threshold;
1199 u8 drop_opts;
1200#define ICE_AQ_SET_MAC_AUTO_DROP_MASK BIT(0)
1201#define ICE_AQ_SET_MAC_AUTO_DROP_NONE 0
1202#define ICE_AQ_SET_MAC_AUTO_DROP_BLOCKING_PKTS BIT(0)
1203 u8 reserved[7];
1204};
1205
1206/* Restart AN command data structure (direct 0x0605)
1207 * Also used for response, with only the lport_num field present.
1208 */
1209struct ice_aqc_restart_an {
1210 u8 lport_num;
1211 u8 reserved;
1212 u8 cmd_flags;
1213#define ICE_AQC_RESTART_AN_LINK_RESTART BIT(1)
1214#define ICE_AQC_RESTART_AN_LINK_ENABLE BIT(2)
1215 u8 reserved2[13];
1216};
1217
1218/* Get link status (indirect 0x0607), also used for Link Status Event */
1219struct ice_aqc_get_link_status {
1220 u8 lport_num;
1221 u8 reserved;
1222 __le16 cmd_flags;
1223#define ICE_AQ_LSE_M 0x3
1224#define ICE_AQ_LSE_NOP 0x0
1225#define ICE_AQ_LSE_DIS 0x2
1226#define ICE_AQ_LSE_ENA 0x3
1227 /* only response uses this flag */
1228#define ICE_AQ_LSE_IS_ENABLED 0x1
1229 __le32 reserved2;
1230 __le32 addr_high;
1231 __le32 addr_low;
1232};
1233
1234/* Get link status response data structure, also used for Link Status Event */
1235struct ice_aqc_get_link_status_data {
1236 u8 topo_media_conflict;
1237#define ICE_AQ_LINK_TOPO_CONFLICT BIT(0)
1238#define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1)
1239#define ICE_AQ_LINK_TOPO_CORRUPT BIT(2)
1240#define ICE_AQ_LINK_TOPO_UNREACH_PRT BIT(4)
1241#define ICE_AQ_LINK_TOPO_UNDRUTIL_PRT BIT(5)
1242#define ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA BIT(6)
1243#define ICE_AQ_LINK_TOPO_UNSUPP_MEDIA BIT(7)
1244 u8 link_cfg_err;
1245#define ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED BIT(5)
1246#define ICE_AQ_LINK_EXTERNAL_PHY_LOAD_FAILURE BIT(6)
1247#define ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT BIT(7)
1248 u8 link_info;
1249#define ICE_AQ_LINK_UP BIT(0) /* Link Status */
1250#define ICE_AQ_LINK_FAULT BIT(1)
1251#define ICE_AQ_LINK_FAULT_TX BIT(2)
1252#define ICE_AQ_LINK_FAULT_RX BIT(3)
1253#define ICE_AQ_LINK_FAULT_REMOTE BIT(4)
1254#define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */
1255#define ICE_AQ_MEDIA_AVAILABLE BIT(6)
1256#define ICE_AQ_SIGNAL_DETECT BIT(7)
1257 u8 an_info;
1258#define ICE_AQ_AN_COMPLETED BIT(0)
1259#define ICE_AQ_LP_AN_ABILITY BIT(1)
1260#define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */
1261#define ICE_AQ_FEC_EN BIT(3)
1262#define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */
1263#define ICE_AQ_LINK_PAUSE_TX BIT(5)
1264#define ICE_AQ_LINK_PAUSE_RX BIT(6)
1265#define ICE_AQ_QUALIFIED_MODULE BIT(7)
1266 u8 ext_info;
1267#define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0)
1268#define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */
1269 /* Port Tx Suspended */
1270#define ICE_AQ_LINK_TX_S 2
1271#define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S)
1272#define ICE_AQ_LINK_TX_ACTIVE 0
1273#define ICE_AQ_LINK_TX_DRAINED 1
1274#define ICE_AQ_LINK_TX_FLUSHED 3
1275 u8 reserved2;
1276 __le16 max_frame_size;
1277 u8 cfg;
1278#define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0)
1279#define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1)
1280#define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2)
1281#define ICE_AQ_FEC_MASK ICE_M(0x7, 0)
1282 /* Pacing Config */
1283#define ICE_AQ_CFG_PACING_S 3
1284#define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S)
1285#define ICE_AQ_CFG_PACING_TYPE_M BIT(7)
1286#define ICE_AQ_CFG_PACING_TYPE_AVG 0
1287#define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M
1288 /* External Device Power Ability */
1289 u8 power_desc;
1290#define ICE_AQ_PWR_CLASS_M 0x3F
1291#define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0
1292#define ICE_AQ_LINK_PWR_BASET_HIGH 1
1293#define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0
1294#define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1
1295#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
1296#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
1297 __le16 link_speed;
1298#define ICE_AQ_LINK_SPEED_M 0x7FF
1299#define ICE_AQ_LINK_SPEED_10MB BIT(0)
1300#define ICE_AQ_LINK_SPEED_100MB BIT(1)
1301#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
1302#define ICE_AQ_LINK_SPEED_2500MB BIT(3)
1303#define ICE_AQ_LINK_SPEED_5GB BIT(4)
1304#define ICE_AQ_LINK_SPEED_10GB BIT(5)
1305#define ICE_AQ_LINK_SPEED_20GB BIT(6)
1306#define ICE_AQ_LINK_SPEED_25GB BIT(7)
1307#define ICE_AQ_LINK_SPEED_40GB BIT(8)
1308#define ICE_AQ_LINK_SPEED_50GB BIT(9)
1309#define ICE_AQ_LINK_SPEED_100GB BIT(10)
1310#define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15)
1311 __le32 reserved3; /* Aligns next field to 8-byte boundary */
1312 __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
1313 __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
1314};
1315
1316/* Set event mask command (direct 0x0613) */
1317struct ice_aqc_set_event_mask {
1318 u8 lport_num;
1319 u8 reserved[7];
1320 __le16 event_mask;
1321#define ICE_AQ_LINK_EVENT_UPDOWN BIT(1)
1322#define ICE_AQ_LINK_EVENT_MEDIA_NA BIT(2)
1323#define ICE_AQ_LINK_EVENT_LINK_FAULT BIT(3)
1324#define ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM BIT(4)
1325#define ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS BIT(5)
1326#define ICE_AQ_LINK_EVENT_SIGNAL_DETECT BIT(6)
1327#define ICE_AQ_LINK_EVENT_AN_COMPLETED BIT(7)
1328#define ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL BIT(8)
1329#define ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED BIT(9)
1330#define ICE_AQ_LINK_EVENT_PHY_FW_LOAD_FAIL BIT(12)
1331 u8 reserved1[6];
1332};
1333
1334/* Set MAC Loopback command (direct 0x0620) */
1335struct ice_aqc_set_mac_lb {
1336 u8 lb_mode;
1337#define ICE_AQ_MAC_LB_EN BIT(0)
1338#define ICE_AQ_MAC_LB_OSC_CLK BIT(1)
1339 u8 reserved[15];
1340};
1341
1342struct ice_aqc_link_topo_params {
1343 u8 lport_num;
1344 u8 lport_num_valid;
1345#define ICE_AQC_LINK_TOPO_PORT_NUM_VALID BIT(0)
1346 u8 node_type_ctx;
1347#define ICE_AQC_LINK_TOPO_NODE_TYPE_S 0
1348#define ICE_AQC_LINK_TOPO_NODE_TYPE_M (0xF << ICE_AQC_LINK_TOPO_NODE_TYPE_S)
1349#define ICE_AQC_LINK_TOPO_NODE_TYPE_PHY 0
1350#define ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL 1
1351#define ICE_AQC_LINK_TOPO_NODE_TYPE_MUX_CTRL 2
1352#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED_CTRL 3
1353#define ICE_AQC_LINK_TOPO_NODE_TYPE_LED 4
1354#define ICE_AQC_LINK_TOPO_NODE_TYPE_THERMAL 5
1355#define ICE_AQC_LINK_TOPO_NODE_TYPE_CAGE 6
1356#define ICE_AQC_LINK_TOPO_NODE_TYPE_MEZZ 7
1357#define ICE_AQC_LINK_TOPO_NODE_TYPE_ID_EEPROM 8
1358#define ICE_AQC_LINK_TOPO_NODE_CTX_S 4
1359#define ICE_AQC_LINK_TOPO_NODE_CTX_M \
1360 (0xF << ICE_AQC_LINK_TOPO_NODE_CTX_S)
1361#define ICE_AQC_LINK_TOPO_NODE_CTX_GLOBAL 0
1362#define ICE_AQC_LINK_TOPO_NODE_CTX_BOARD 1
1363#define ICE_AQC_LINK_TOPO_NODE_CTX_PORT 2
1364#define ICE_AQC_LINK_TOPO_NODE_CTX_NODE 3
1365#define ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED 4
1366#define ICE_AQC_LINK_TOPO_NODE_CTX_OVERRIDE 5
1367 u8 index;
1368};
1369
1370struct ice_aqc_link_topo_addr {
1371 struct ice_aqc_link_topo_params topo_params;
1372 __le16 handle;
1373#define ICE_AQC_LINK_TOPO_HANDLE_S 0
1374#define ICE_AQC_LINK_TOPO_HANDLE_M (0x3FF << ICE_AQC_LINK_TOPO_HANDLE_S)
1375/* Used to decode the handle field */
1376#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_M BIT(9)
1377#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_LOM BIT(9)
1378#define ICE_AQC_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ 0
1379#define ICE_AQC_LINK_TOPO_HANDLE_NODE_S 0
1380/* In case of a Mezzanine type */
1381#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_NODE_M \
1382 (0x3F << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1383#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S 6
1384#define ICE_AQC_LINK_TOPO_HANDLE_MEZZ_M (0x7 << ICE_AQC_LINK_TOPO_HANDLE_MEZZ_S)
1385/* In case of a LOM type */
1386#define ICE_AQC_LINK_TOPO_HANDLE_LOM_NODE_M \
1387 (0x1FF << ICE_AQC_LINK_TOPO_HANDLE_NODE_S)
1388};
1389
1390/* Get Link Topology Handle (direct, 0x06E0) */
1391struct ice_aqc_get_link_topo {
1392 struct ice_aqc_link_topo_addr addr;
1393 u8 node_part_num;
1394#define ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575 0x21
1395 u8 rsvd[9];
1396};
1397
1398/* Read/Write I2C (direct, 0x06E2/0x06E3) */
1399struct ice_aqc_i2c {
1400 struct ice_aqc_link_topo_addr topo_addr;
1401 __le16 i2c_addr;
1402 u8 i2c_params;
1403#define ICE_AQC_I2C_DATA_SIZE_M GENMASK(3, 0)
1404#define ICE_AQC_I2C_USE_REPEATED_START BIT(7)
1405
1406 u8 rsvd;
1407 __le16 i2c_bus_addr;
1408 u8 i2c_data[4]; /* Used only by write command, reserved in read. */
1409};
1410
1411/* Read I2C Response (direct, 0x06E2) */
1412struct ice_aqc_read_i2c_resp {
1413 u8 i2c_data[16];
1414};
1415
1416/* Set Port Identification LED (direct, 0x06E9) */
1417struct ice_aqc_set_port_id_led {
1418 u8 lport_num;
1419 u8 lport_num_valid;
1420 u8 ident_mode;
1421#define ICE_AQC_PORT_IDENT_LED_BLINK BIT(0)
1422#define ICE_AQC_PORT_IDENT_LED_ORIG 0
1423 u8 rsvd[13];
1424};
1425
1426/* Get Port Options (indirect, 0x06EA) */
1427struct ice_aqc_get_port_options {
1428 u8 lport_num;
1429 u8 lport_num_valid;
1430 u8 port_options_count;
1431#define ICE_AQC_PORT_OPT_COUNT_M GENMASK(3, 0)
1432#define ICE_AQC_PORT_OPT_MAX 16
1433
1434 u8 innermost_phy_index;
1435 u8 port_options;
1436#define ICE_AQC_PORT_OPT_ACTIVE_M GENMASK(3, 0)
1437#define ICE_AQC_PORT_OPT_VALID BIT(7)
1438
1439 u8 pending_port_option_status;
1440#define ICE_AQC_PENDING_PORT_OPT_IDX_M GENMASK(3, 0)
1441#define ICE_AQC_PENDING_PORT_OPT_VALID BIT(7)
1442
1443 u8 rsvd[2];
1444 __le32 addr_high;
1445 __le32 addr_low;
1446};
1447
1448struct ice_aqc_get_port_options_elem {
1449 u8 pmd;
1450#define ICE_AQC_PORT_OPT_PMD_COUNT_M GENMASK(3, 0)
1451
1452 u8 max_lane_speed;
1453#define ICE_AQC_PORT_OPT_MAX_LANE_M GENMASK(3, 0)
1454#define ICE_AQC_PORT_OPT_MAX_LANE_100M 0
1455#define ICE_AQC_PORT_OPT_MAX_LANE_1G 1
1456#define ICE_AQC_PORT_OPT_MAX_LANE_2500M 2
1457#define ICE_AQC_PORT_OPT_MAX_LANE_5G 3
1458#define ICE_AQC_PORT_OPT_MAX_LANE_10G 4
1459#define ICE_AQC_PORT_OPT_MAX_LANE_25G 5
1460#define ICE_AQC_PORT_OPT_MAX_LANE_50G 6
1461#define ICE_AQC_PORT_OPT_MAX_LANE_100G 7
1462
1463 u8 global_scid[2];
1464 u8 phy_scid[2];
1465 u8 pf2port_cid[2];
1466};
1467
1468/* Set Port Option (direct, 0x06EB) */
1469struct ice_aqc_set_port_option {
1470 u8 lport_num;
1471 u8 lport_num_valid;
1472 u8 selected_port_option;
1473 u8 rsvd[13];
1474};
1475
1476/* Set/Get GPIO (direct, 0x06EC/0x06ED) */
1477struct ice_aqc_gpio {
1478 __le16 gpio_ctrl_handle;
1479#define ICE_AQC_GPIO_HANDLE_S 0
1480#define ICE_AQC_GPIO_HANDLE_M (0x3FF << ICE_AQC_GPIO_HANDLE_S)
1481 u8 gpio_num;
1482 u8 gpio_val;
1483 u8 rsvd[12];
1484};
1485
1486/* Read/Write SFF EEPROM command (indirect 0x06EE) */
1487struct ice_aqc_sff_eeprom {
1488 u8 lport_num;
1489 u8 lport_num_valid;
1490#define ICE_AQC_SFF_PORT_NUM_VALID BIT(0)
1491 __le16 i2c_bus_addr;
1492#define ICE_AQC_SFF_I2CBUS_7BIT_M 0x7F
1493#define ICE_AQC_SFF_I2CBUS_10BIT_M 0x3FF
1494#define ICE_AQC_SFF_I2CBUS_TYPE_M BIT(10)
1495#define ICE_AQC_SFF_I2CBUS_TYPE_7BIT 0
1496#define ICE_AQC_SFF_I2CBUS_TYPE_10BIT ICE_AQC_SFF_I2CBUS_TYPE_M
1497#define ICE_AQC_SFF_SET_EEPROM_PAGE_S 11
1498#define ICE_AQC_SFF_SET_EEPROM_PAGE_M (0x3 << ICE_AQC_SFF_SET_EEPROM_PAGE_S)
1499#define ICE_AQC_SFF_NO_PAGE_CHANGE 0
1500#define ICE_AQC_SFF_SET_23_ON_MISMATCH 1
1501#define ICE_AQC_SFF_SET_22_ON_MISMATCH 2
1502#define ICE_AQC_SFF_IS_WRITE BIT(15)
1503 __le16 i2c_mem_addr;
1504 __le16 eeprom_page;
1505#define ICE_AQC_SFF_EEPROM_BANK_S 0
1506#define ICE_AQC_SFF_EEPROM_BANK_M (0xFF << ICE_AQC_SFF_EEPROM_BANK_S)
1507#define ICE_AQC_SFF_EEPROM_PAGE_S 8
1508#define ICE_AQC_SFF_EEPROM_PAGE_M (0xFF << ICE_AQC_SFF_EEPROM_PAGE_S)
1509 __le32 addr_high;
1510 __le32 addr_low;
1511};
1512
1513/* NVM Read command (indirect 0x0701)
1514 * NVM Erase commands (direct 0x0702)
1515 * NVM Update commands (indirect 0x0703)
1516 */
1517struct ice_aqc_nvm {
1518#define ICE_AQC_NVM_MAX_OFFSET 0xFFFFFF
1519 __le16 offset_low;
1520 u8 offset_high;
1521 u8 cmd_flags;
1522#define ICE_AQC_NVM_LAST_CMD BIT(0)
1523#define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */
1524#define ICE_AQC_NVM_PRESERVATION_S 1
1525#define ICE_AQC_NVM_PRESERVATION_M (3 << ICE_AQC_NVM_PRESERVATION_S)
1526#define ICE_AQC_NVM_NO_PRESERVATION (0 << ICE_AQC_NVM_PRESERVATION_S)
1527#define ICE_AQC_NVM_PRESERVE_ALL BIT(1)
1528#define ICE_AQC_NVM_FACTORY_DEFAULT (2 << ICE_AQC_NVM_PRESERVATION_S)
1529#define ICE_AQC_NVM_PRESERVE_SELECTED (3 << ICE_AQC_NVM_PRESERVATION_S)
1530#define ICE_AQC_NVM_ACTIV_SEL_NVM BIT(3) /* Write Activate/SR Dump only */
1531#define ICE_AQC_NVM_ACTIV_SEL_OROM BIT(4)
1532#define ICE_AQC_NVM_ACTIV_SEL_NETLIST BIT(5)
1533#define ICE_AQC_NVM_SPECIAL_UPDATE BIT(6)
1534#define ICE_AQC_NVM_REVERT_LAST_ACTIV BIT(6) /* Write Activate only */
1535#define ICE_AQC_NVM_ACTIV_SEL_MASK ICE_M(0x7, 3)
1536#define ICE_AQC_NVM_FLASH_ONLY BIT(7)
1537#define ICE_AQC_NVM_RESET_LVL_M ICE_M(0x3, 0) /* Write reply only */
1538#define ICE_AQC_NVM_POR_FLAG 0
1539#define ICE_AQC_NVM_PERST_FLAG 1
1540#define ICE_AQC_NVM_EMPR_FLAG 2
1541#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
1542 /* For Write Activate, several flags are sent as part of a separate
1543 * flags2 field using a separate byte. For simplicity of the software
1544 * interface, we pass the flags as a 16 bit value so these flags are
1545 * all offset by 8 bits
1546 */
1547#define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */
1548 __le16 module_typeid;
1549 __le16 length;
1550#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
1551 __le32 addr_high;
1552 __le32 addr_low;
1553};
1554
1555#define ICE_AQC_NVM_START_POINT 0
1556
1557/* NVM Checksum Command (direct, 0x0706) */
1558struct ice_aqc_nvm_checksum {
1559 u8 flags;
1560#define ICE_AQC_NVM_CHECKSUM_VERIFY BIT(0)
1561#define ICE_AQC_NVM_CHECKSUM_RECALC BIT(1)
1562 u8 rsvd;
1563 __le16 checksum; /* Used only by response */
1564#define ICE_AQC_NVM_CHECKSUM_CORRECT 0xBABA
1565 u8 rsvd2[12];
1566};
1567
1568/* Used for NVM Set Package Data command - 0x070A */
1569struct ice_aqc_nvm_pkg_data {
1570 u8 reserved[3];
1571 u8 cmd_flags;
1572#define ICE_AQC_NVM_PKG_DELETE BIT(0) /* used for command call */
1573#define ICE_AQC_NVM_PKG_SKIPPED BIT(0) /* used for command response */
1574
1575 u32 reserved1;
1576 __le32 addr_high;
1577 __le32 addr_low;
1578};
1579
1580/* Used for Pass Component Table command - 0x070B */
1581struct ice_aqc_nvm_pass_comp_tbl {
1582 u8 component_response; /* Response only */
1583#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED 0x0
1584#define ICE_AQ_NVM_PASS_COMP_CAN_MAY_BE_UPDATEABLE 0x1
1585#define ICE_AQ_NVM_PASS_COMP_CAN_NOT_BE_UPDATED 0x2
1586 u8 component_response_code; /* Response only */
1587#define ICE_AQ_NVM_PASS_COMP_CAN_BE_UPDATED_CODE 0x0
1588#define ICE_AQ_NVM_PASS_COMP_STAMP_IDENTICAL_CODE 0x1
1589#define ICE_AQ_NVM_PASS_COMP_STAMP_LOWER 0x2
1590#define ICE_AQ_NVM_PASS_COMP_INVALID_STAMP_CODE 0x3
1591#define ICE_AQ_NVM_PASS_COMP_CONFLICT_CODE 0x4
1592#define ICE_AQ_NVM_PASS_COMP_PRE_REQ_NOT_MET_CODE 0x5
1593#define ICE_AQ_NVM_PASS_COMP_NOT_SUPPORTED_CODE 0x6
1594#define ICE_AQ_NVM_PASS_COMP_CANNOT_DOWNGRADE_CODE 0x7
1595#define ICE_AQ_NVM_PASS_COMP_INCOMPLETE_IMAGE_CODE 0x8
1596#define ICE_AQ_NVM_PASS_COMP_VER_STR_IDENTICAL_CODE 0xA
1597#define ICE_AQ_NVM_PASS_COMP_VER_STR_LOWER_CODE 0xB
1598 u8 reserved;
1599 u8 transfer_flag;
1600#define ICE_AQ_NVM_PASS_COMP_TBL_START 0x1
1601#define ICE_AQ_NVM_PASS_COMP_TBL_MIDDLE 0x2
1602#define ICE_AQ_NVM_PASS_COMP_TBL_END 0x4
1603#define ICE_AQ_NVM_PASS_COMP_TBL_START_AND_END 0x5
1604 __le32 reserved1;
1605 __le32 addr_high;
1606 __le32 addr_low;
1607};
1608
1609struct ice_aqc_nvm_comp_tbl {
1610 __le16 comp_class;
1611#define NVM_COMP_CLASS_ALL_FW 0x000A
1612
1613 __le16 comp_id;
1614#define NVM_COMP_ID_OROM 0x5
1615#define NVM_COMP_ID_NVM 0x6
1616#define NVM_COMP_ID_NETLIST 0x8
1617
1618 u8 comp_class_idx;
1619#define FWU_COMP_CLASS_IDX_NOT_USE 0x0
1620
1621 __le32 comp_cmp_stamp;
1622 u8 cvs_type;
1623#define NVM_CVS_TYPE_ASCII 0x1
1624
1625 u8 cvs_len;
1626 u8 cvs[]; /* Component Version String */
1627} __packed;
1628
1629/* Send to PF command (indirect 0x0801) ID is only used by PF
1630 *
1631 * Send to VF command (indirect 0x0802) ID is only used by PF
1632 *
1633 */
1634struct ice_aqc_pf_vf_msg {
1635 __le32 id;
1636 u32 reserved;
1637 __le32 addr_high;
1638 __le32 addr_low;
1639};
1640
1641/* Get LLDP MIB (indirect 0x0A00)
1642 * Note: This is also used by the LLDP MIB Change Event (0x0A01)
1643 * as the format is the same.
1644 */
1645struct ice_aqc_lldp_get_mib {
1646 u8 type;
1647#define ICE_AQ_LLDP_MIB_TYPE_S 0
1648#define ICE_AQ_LLDP_MIB_TYPE_M (0x3 << ICE_AQ_LLDP_MIB_TYPE_S)
1649#define ICE_AQ_LLDP_MIB_LOCAL 0
1650#define ICE_AQ_LLDP_MIB_REMOTE 1
1651#define ICE_AQ_LLDP_MIB_LOCAL_AND_REMOTE 2
1652#define ICE_AQ_LLDP_BRID_TYPE_S 2
1653#define ICE_AQ_LLDP_BRID_TYPE_M (0x3 << ICE_AQ_LLDP_BRID_TYPE_S)
1654#define ICE_AQ_LLDP_BRID_TYPE_NEAREST_BRID 0
1655#define ICE_AQ_LLDP_BRID_TYPE_NON_TPMR 1
1656/* Tx pause flags in the 0xA01 event use ICE_AQ_LLDP_TX_* */
1657#define ICE_AQ_LLDP_TX_S 0x4
1658#define ICE_AQ_LLDP_TX_M (0x03 << ICE_AQ_LLDP_TX_S)
1659#define ICE_AQ_LLDP_TX_ACTIVE 0
1660#define ICE_AQ_LLDP_TX_SUSPENDED 1
1661#define ICE_AQ_LLDP_TX_FLUSHED 3
1662/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
1663 * and in the LLDP MIB Change Event (0x0A01). They are valid for the
1664 * Get LLDP MIB (0x0A00) response only.
1665 */
1666 u8 reserved1;
1667 __le16 local_len;
1668 __le16 remote_len;
1669 u8 reserved2[2];
1670 __le32 addr_high;
1671 __le32 addr_low;
1672};
1673
1674/* Configure LLDP MIB Change Event (direct 0x0A01) */
1675/* For MIB Change Event use ice_aqc_lldp_get_mib structure above */
1676struct ice_aqc_lldp_set_mib_change {
1677 u8 command;
1678#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1679#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
1680 u8 reserved[15];
1681};
1682
1683/* Stop LLDP (direct 0x0A05) */
1684struct ice_aqc_lldp_stop {
1685 u8 command;
1686#define ICE_AQ_LLDP_AGENT_STATE_MASK BIT(0)
1687#define ICE_AQ_LLDP_AGENT_STOP 0x0
1688#define ICE_AQ_LLDP_AGENT_SHUTDOWN ICE_AQ_LLDP_AGENT_STATE_MASK
1689#define ICE_AQ_LLDP_AGENT_PERSIST_DIS BIT(1)
1690 u8 reserved[15];
1691};
1692
1693/* Start LLDP (direct 0x0A06) */
1694struct ice_aqc_lldp_start {
1695 u8 command;
1696#define ICE_AQ_LLDP_AGENT_START BIT(0)
1697#define ICE_AQ_LLDP_AGENT_PERSIST_ENA BIT(1)
1698 u8 reserved[15];
1699};
1700
1701/* Get CEE DCBX Oper Config (0x0A07)
1702 * The command uses the generic descriptor struct and
1703 * returns the struct below as an indirect response.
1704 */
1705struct ice_aqc_get_cee_dcb_cfg_resp {
1706 u8 oper_num_tc;
1707 u8 oper_prio_tc[4];
1708 u8 oper_tc_bw[8];
1709 u8 oper_pfc_en;
1710 __le16 oper_app_prio;
1711#define ICE_AQC_CEE_APP_FCOE_S 0
1712#define ICE_AQC_CEE_APP_FCOE_M (0x7 << ICE_AQC_CEE_APP_FCOE_S)
1713#define ICE_AQC_CEE_APP_ISCSI_S 3
1714#define ICE_AQC_CEE_APP_ISCSI_M (0x7 << ICE_AQC_CEE_APP_ISCSI_S)
1715#define ICE_AQC_CEE_APP_FIP_S 8
1716#define ICE_AQC_CEE_APP_FIP_M (0x7 << ICE_AQC_CEE_APP_FIP_S)
1717 __le32 tlv_status;
1718#define ICE_AQC_CEE_PG_STATUS_S 0
1719#define ICE_AQC_CEE_PG_STATUS_M (0x7 << ICE_AQC_CEE_PG_STATUS_S)
1720#define ICE_AQC_CEE_PFC_STATUS_S 3
1721#define ICE_AQC_CEE_PFC_STATUS_M (0x7 << ICE_AQC_CEE_PFC_STATUS_S)
1722#define ICE_AQC_CEE_FCOE_STATUS_S 8
1723#define ICE_AQC_CEE_FCOE_STATUS_M (0x7 << ICE_AQC_CEE_FCOE_STATUS_S)
1724#define ICE_AQC_CEE_ISCSI_STATUS_S 11
1725#define ICE_AQC_CEE_ISCSI_STATUS_M (0x7 << ICE_AQC_CEE_ISCSI_STATUS_S)
1726#define ICE_AQC_CEE_FIP_STATUS_S 16
1727#define ICE_AQC_CEE_FIP_STATUS_M (0x7 << ICE_AQC_CEE_FIP_STATUS_S)
1728 u8 reserved[12];
1729};
1730
1731/* Set Local LLDP MIB (indirect 0x0A08)
1732 * Used to replace the local MIB of a given LLDP agent. e.g. DCBX
1733 */
1734struct ice_aqc_lldp_set_local_mib {
1735 u8 type;
1736#define SET_LOCAL_MIB_TYPE_DCBX_M BIT(0)
1737#define SET_LOCAL_MIB_TYPE_LOCAL_MIB 0
1738#define SET_LOCAL_MIB_TYPE_CEE_M BIT(1)
1739#define SET_LOCAL_MIB_TYPE_CEE_WILLING 0
1740#define SET_LOCAL_MIB_TYPE_CEE_NON_WILLING SET_LOCAL_MIB_TYPE_CEE_M
1741 u8 reserved0;
1742 __le16 length;
1743 u8 reserved1[4];
1744 __le32 addr_high;
1745 __le32 addr_low;
1746};
1747
1748/* Stop/Start LLDP Agent (direct 0x0A09)
1749 * Used for stopping/starting specific LLDP agent. e.g. DCBX.
1750 * The same structure is used for the response, with the command field
1751 * being used as the status field.
1752 */
1753struct ice_aqc_lldp_stop_start_specific_agent {
1754 u8 command;
1755#define ICE_AQC_START_STOP_AGENT_M BIT(0)
1756#define ICE_AQC_START_STOP_AGENT_STOP_DCBX 0
1757#define ICE_AQC_START_STOP_AGENT_START_DCBX ICE_AQC_START_STOP_AGENT_M
1758 u8 reserved[15];
1759};
1760
1761/* LLDP Filter Control (direct 0x0A0A) */
1762struct ice_aqc_lldp_filter_ctrl {
1763 u8 cmd_flags;
1764#define ICE_AQC_LLDP_FILTER_ACTION_ADD 0x0
1765#define ICE_AQC_LLDP_FILTER_ACTION_DELETE 0x1
1766 u8 reserved1;
1767 __le16 vsi_num;
1768 u8 reserved2[12];
1769};
1770
1771/* Get/Set RSS key (indirect 0x0B04/0x0B02) */
1772struct ice_aqc_get_set_rss_key {
1773#define ICE_AQC_GSET_RSS_KEY_VSI_VALID BIT(15)
1774#define ICE_AQC_GSET_RSS_KEY_VSI_ID_S 0
1775#define ICE_AQC_GSET_RSS_KEY_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_KEY_VSI_ID_S)
1776 __le16 vsi_id;
1777 u8 reserved[6];
1778 __le32 addr_high;
1779 __le32 addr_low;
1780};
1781
1782#define ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE 0x28
1783#define ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE 0xC
1784#define ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE \
1785 (ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE + \
1786 ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE)
1787
1788struct ice_aqc_get_set_rss_keys {
1789 u8 standard_rss_key[ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE];
1790 u8 extended_hash_key[ICE_AQC_GET_SET_RSS_KEY_DATA_HASH_KEY_SIZE];
1791};
1792
1793/* Get/Set RSS LUT (indirect 0x0B05/0x0B03) */
1794struct ice_aqc_get_set_rss_lut {
1795#define ICE_AQC_GSET_RSS_LUT_VSI_VALID BIT(15)
1796#define ICE_AQC_GSET_RSS_LUT_VSI_ID_S 0
1797#define ICE_AQC_GSET_RSS_LUT_VSI_ID_M (0x3FF << ICE_AQC_GSET_RSS_LUT_VSI_ID_S)
1798 __le16 vsi_id;
1799#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S 0
1800#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M \
1801 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S)
1802
1803#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI 0
1804#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF 1
1805#define ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL 2
1806
1807#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S 2
1808#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M \
1809 (0x3 << ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S)
1810
1811#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 128
1812#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128_FLAG 0
1813#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 512
1814#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG 1
1815#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K 2048
1816#define ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG 2
1817
1818#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S 4
1819#define ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M \
1820 (0xF << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S)
1821
1822 __le16 flags;
1823 __le32 reserved;
1824 __le32 addr_high;
1825 __le32 addr_low;
1826};
1827
1828/* Sideband Control Interface Commands */
1829/* Neighbor Device Request (indirect 0x0C00); also used for the response. */
1830struct ice_aqc_neigh_dev_req {
1831 __le16 sb_data_len;
1832 u8 reserved[6];
1833 __le32 addr_high;
1834 __le32 addr_low;
1835};
1836
1837/* Add Tx LAN Queues (indirect 0x0C30) */
1838struct ice_aqc_add_txqs {
1839 u8 num_qgrps;
1840 u8 reserved[3];
1841 __le32 reserved1;
1842 __le32 addr_high;
1843 __le32 addr_low;
1844};
1845
1846/* This is the descriptor of each queue entry for the Add Tx LAN Queues
1847 * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp.
1848 */
1849struct ice_aqc_add_txqs_perq {
1850 __le16 txq_id;
1851 u8 rsvd[2];
1852 __le32 q_teid;
1853 u8 txq_ctx[22];
1854 u8 rsvd2[2];
1855 struct ice_aqc_txsched_elem info;
1856};
1857
1858/* The format of the command buffer for Add Tx LAN Queues (0x0C30)
1859 * is an array of the following structs. Please note that the length of
1860 * each struct ice_aqc_add_tx_qgrp is variable due
1861 * to the variable number of queues in each group!
1862 */
1863struct ice_aqc_add_tx_qgrp {
1864 __le32 parent_teid;
1865 u8 num_txqs;
1866 u8 rsvd[3];
1867 struct ice_aqc_add_txqs_perq txqs[];
1868};
1869
1870/* Disable Tx LAN Queues (indirect 0x0C31) */
1871struct ice_aqc_dis_txqs {
1872 u8 cmd_type;
1873#define ICE_AQC_Q_DIS_CMD_S 0
1874#define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S)
1875#define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S)
1876#define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S)
1877#define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S)
1878#define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S)
1879#define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2)
1880#define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3)
1881 u8 num_entries;
1882 __le16 vmvf_and_timeout;
1883#define ICE_AQC_Q_DIS_VMVF_NUM_S 0
1884#define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S)
1885#define ICE_AQC_Q_DIS_TIMEOUT_S 10
1886#define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S)
1887 __le32 blocked_cgds;
1888 __le32 addr_high;
1889 __le32 addr_low;
1890};
1891
1892/* The buffer for Disable Tx LAN Queues (indirect 0x0C31)
1893 * contains the following structures, arrayed one after the
1894 * other.
1895 * Note: Since the q_id is 16 bits wide, if the
1896 * number of queues is even, then 2 bytes of alignment MUST be
1897 * added before the start of the next group, to allow correct
1898 * alignment of the parent_teid field.
1899 */
1900struct ice_aqc_dis_txq_item {
1901 __le32 parent_teid;
1902 u8 num_qs;
1903 u8 rsvd;
1904 /* The length of the q_id array varies according to num_qs */
1905#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15
1906#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \
1907 (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1908#define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \
1909 (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S)
1910 __le16 q_id[];
1911} __packed;
1912
1913/* Add Tx RDMA Queue Set (indirect 0x0C33) */
1914struct ice_aqc_add_rdma_qset {
1915 u8 num_qset_grps;
1916 u8 reserved[7];
1917 __le32 addr_high;
1918 __le32 addr_low;
1919};
1920
1921/* This is the descriptor of each Qset entry for the Add Tx RDMA Queue Set
1922 * command (0x0C33). Only used within struct ice_aqc_add_rdma_qset.
1923 */
1924struct ice_aqc_add_tx_rdma_qset_entry {
1925 __le16 tx_qset_id;
1926 u8 rsvd[2];
1927 __le32 qset_teid;
1928 struct ice_aqc_txsched_elem info;
1929};
1930
1931/* The format of the command buffer for Add Tx RDMA Queue Set(0x0C33)
1932 * is an array of the following structs. Please note that the length of
1933 * each struct ice_aqc_add_rdma_qset is variable due to the variable
1934 * number of queues in each group!
1935 */
1936struct ice_aqc_add_rdma_qset_data {
1937 __le32 parent_teid;
1938 __le16 num_qsets;
1939 u8 rsvd[2];
1940 struct ice_aqc_add_tx_rdma_qset_entry rdma_qsets[];
1941};
1942
1943/* Configure Firmware Logging Command (indirect 0xFF09)
1944 * Logging Information Read Response (indirect 0xFF10)
1945 * Note: The 0xFF10 command has no input parameters.
1946 */
1947struct ice_aqc_fw_logging {
1948 u8 log_ctrl;
1949#define ICE_AQC_FW_LOG_AQ_EN BIT(0)
1950#define ICE_AQC_FW_LOG_UART_EN BIT(1)
1951 u8 rsvd0;
1952 u8 log_ctrl_valid; /* Not used by 0xFF10 Response */
1953#define ICE_AQC_FW_LOG_AQ_VALID BIT(0)
1954#define ICE_AQC_FW_LOG_UART_VALID BIT(1)
1955 u8 rsvd1[5];
1956 __le32 addr_high;
1957 __le32 addr_low;
1958};
1959
1960enum ice_aqc_fw_logging_mod {
1961 ICE_AQC_FW_LOG_ID_GENERAL = 0,
1962 ICE_AQC_FW_LOG_ID_CTRL,
1963 ICE_AQC_FW_LOG_ID_LINK,
1964 ICE_AQC_FW_LOG_ID_LINK_TOPO,
1965 ICE_AQC_FW_LOG_ID_DNL,
1966 ICE_AQC_FW_LOG_ID_I2C,
1967 ICE_AQC_FW_LOG_ID_SDP,
1968 ICE_AQC_FW_LOG_ID_MDIO,
1969 ICE_AQC_FW_LOG_ID_ADMINQ,
1970 ICE_AQC_FW_LOG_ID_HDMA,
1971 ICE_AQC_FW_LOG_ID_LLDP,
1972 ICE_AQC_FW_LOG_ID_DCBX,
1973 ICE_AQC_FW_LOG_ID_DCB,
1974 ICE_AQC_FW_LOG_ID_NETPROXY,
1975 ICE_AQC_FW_LOG_ID_NVM,
1976 ICE_AQC_FW_LOG_ID_AUTH,
1977 ICE_AQC_FW_LOG_ID_VPD,
1978 ICE_AQC_FW_LOG_ID_IOSF,
1979 ICE_AQC_FW_LOG_ID_PARSER,
1980 ICE_AQC_FW_LOG_ID_SW,
1981 ICE_AQC_FW_LOG_ID_SCHEDULER,
1982 ICE_AQC_FW_LOG_ID_TXQ,
1983 ICE_AQC_FW_LOG_ID_RSVD,
1984 ICE_AQC_FW_LOG_ID_POST,
1985 ICE_AQC_FW_LOG_ID_WATCHDOG,
1986 ICE_AQC_FW_LOG_ID_TASK_DISPATCH,
1987 ICE_AQC_FW_LOG_ID_MNG,
1988 ICE_AQC_FW_LOG_ID_MAX,
1989};
1990
1991/* Defines for both above FW logging command/response buffers */
1992#define ICE_AQC_FW_LOG_ID_S 0
1993#define ICE_AQC_FW_LOG_ID_M (0xFFF << ICE_AQC_FW_LOG_ID_S)
1994
1995#define ICE_AQC_FW_LOG_CONF_SUCCESS 0 /* Used by response */
1996#define ICE_AQC_FW_LOG_CONF_BAD_INDX BIT(12) /* Used by response */
1997
1998#define ICE_AQC_FW_LOG_EN_S 12
1999#define ICE_AQC_FW_LOG_EN_M (0xF << ICE_AQC_FW_LOG_EN_S)
2000#define ICE_AQC_FW_LOG_INFO_EN BIT(12) /* Used by command */
2001#define ICE_AQC_FW_LOG_INIT_EN BIT(13) /* Used by command */
2002#define ICE_AQC_FW_LOG_FLOW_EN BIT(14) /* Used by command */
2003#define ICE_AQC_FW_LOG_ERR_EN BIT(15) /* Used by command */
2004
2005/* Get/Clear FW Log (indirect 0xFF11) */
2006struct ice_aqc_get_clear_fw_log {
2007 u8 flags;
2008#define ICE_AQC_FW_LOG_CLEAR BIT(0)
2009#define ICE_AQC_FW_LOG_MORE_DATA_AVAIL BIT(1)
2010 u8 rsvd1[7];
2011 __le32 addr_high;
2012 __le32 addr_low;
2013};
2014
2015/* Download Package (indirect 0x0C40) */
2016/* Also used for Update Package (indirect 0x0C41 and 0x0C42) */
2017struct ice_aqc_download_pkg {
2018 u8 flags;
2019#define ICE_AQC_DOWNLOAD_PKG_LAST_BUF 0x01
2020 u8 reserved[3];
2021 __le32 reserved1;
2022 __le32 addr_high;
2023 __le32 addr_low;
2024};
2025
2026struct ice_aqc_download_pkg_resp {
2027 __le32 error_offset;
2028 __le32 error_info;
2029 __le32 addr_high;
2030 __le32 addr_low;
2031};
2032
2033/* Get Package Info List (indirect 0x0C43) */
2034struct ice_aqc_get_pkg_info_list {
2035 __le32 reserved1;
2036 __le32 reserved2;
2037 __le32 addr_high;
2038 __le32 addr_low;
2039};
2040
2041/* Version format for packages */
2042struct ice_pkg_ver {
2043 u8 major;
2044 u8 minor;
2045 u8 update;
2046 u8 draft;
2047};
2048
2049#define ICE_PKG_NAME_SIZE 32
2050#define ICE_SEG_ID_SIZE 28
2051#define ICE_SEG_NAME_SIZE 28
2052
2053struct ice_aqc_get_pkg_info {
2054 struct ice_pkg_ver ver;
2055 char name[ICE_SEG_NAME_SIZE];
2056 __le32 track_id;
2057 u8 is_in_nvm;
2058 u8 is_active;
2059 u8 is_active_at_boot;
2060 u8 is_modified;
2061};
2062
2063/* Get Package Info List response buffer format (0x0C43) */
2064struct ice_aqc_get_pkg_info_resp {
2065 __le32 count;
2066 struct ice_aqc_get_pkg_info pkg_info[];
2067};
2068
2069/* Driver Shared Parameters (direct, 0x0C90) */
2070struct ice_aqc_driver_shared_params {
2071 u8 set_or_get_op;
2072#define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
2073#define ICE_AQC_DRIVER_PARAM_SET 0
2074#define ICE_AQC_DRIVER_PARAM_GET 1
2075 u8 param_indx;
2076#define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
2077 u8 rsvd[2];
2078 __le32 param_val;
2079 __le32 addr_high;
2080 __le32 addr_low;
2081};
2082
2083enum ice_aqc_driver_params {
2084 /* OS clock index for PTP timer Domain 0 */
2085 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0,
2086 /* OS clock index for PTP timer Domain 1 */
2087 ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1,
2088
2089 /* Add new parameters above */
2090 ICE_AQC_DRIVER_PARAM_MAX = 16,
2091};
2092
2093/* Lan Queue Overflow Event (direct, 0x1001) */
2094struct ice_aqc_event_lan_overflow {
2095 __le32 prtdcb_ruptq;
2096 __le32 qtx_ctl;
2097 u8 reserved[8];
2098};
2099
2100/**
2101 * struct ice_aq_desc - Admin Queue (AQ) descriptor
2102 * @flags: ICE_AQ_FLAG_* flags
2103 * @opcode: AQ command opcode
2104 * @datalen: length in bytes of indirect/external data buffer
2105 * @retval: return value from firmware
2106 * @cookie_high: opaque data high-half
2107 * @cookie_low: opaque data low-half
2108 * @params: command-specific parameters
2109 *
2110 * Descriptor format for commands the driver posts on the Admin Transmit Queue
2111 * (ATQ). The firmware writes back onto the command descriptor and returns
2112 * the result of the command. Asynchronous events that are not an immediate
2113 * result of the command are written to the Admin Receive Queue (ARQ) using
2114 * the same descriptor format. Descriptors are in little-endian notation with
2115 * 32-bit words.
2116 */
2117struct ice_aq_desc {
2118 __le16 flags;
2119 __le16 opcode;
2120 __le16 datalen;
2121 __le16 retval;
2122 __le32 cookie_high;
2123 __le32 cookie_low;
2124 union {
2125 u8 raw[16];
2126 struct ice_aqc_generic generic;
2127 struct ice_aqc_get_ver get_ver;
2128 struct ice_aqc_driver_ver driver_ver;
2129 struct ice_aqc_q_shutdown q_shutdown;
2130 struct ice_aqc_req_res res_owner;
2131 struct ice_aqc_manage_mac_read mac_read;
2132 struct ice_aqc_manage_mac_write mac_write;
2133 struct ice_aqc_clear_pxe clear_pxe;
2134 struct ice_aqc_list_caps get_cap;
2135 struct ice_aqc_get_phy_caps get_phy;
2136 struct ice_aqc_set_phy_cfg set_phy;
2137 struct ice_aqc_restart_an restart_an;
2138 struct ice_aqc_gpio read_write_gpio;
2139 struct ice_aqc_sff_eeprom read_write_sff_param;
2140 struct ice_aqc_set_port_id_led set_port_id_led;
2141 struct ice_aqc_get_port_options get_port_options;
2142 struct ice_aqc_set_port_option set_port_option;
2143 struct ice_aqc_get_sw_cfg get_sw_conf;
2144 struct ice_aqc_set_port_params set_port_params;
2145 struct ice_aqc_sw_rules sw_rules;
2146 struct ice_aqc_add_get_recipe add_get_recipe;
2147 struct ice_aqc_recipe_to_profile recipe_to_profile;
2148 struct ice_aqc_get_topo get_topo;
2149 struct ice_aqc_sched_elem_cmd sched_elem_cmd;
2150 struct ice_aqc_query_txsched_res query_sched_res;
2151 struct ice_aqc_query_port_ets port_ets;
2152 struct ice_aqc_rl_profile rl_profile;
2153 struct ice_aqc_nvm nvm;
2154 struct ice_aqc_nvm_checksum nvm_checksum;
2155 struct ice_aqc_nvm_pkg_data pkg_data;
2156 struct ice_aqc_nvm_pass_comp_tbl pass_comp_tbl;
2157 struct ice_aqc_pf_vf_msg virt;
2158 struct ice_aqc_set_query_pfc_mode set_query_pfc_mode;
2159 struct ice_aqc_lldp_get_mib lldp_get_mib;
2160 struct ice_aqc_lldp_set_mib_change lldp_set_event;
2161 struct ice_aqc_lldp_stop lldp_stop;
2162 struct ice_aqc_lldp_start lldp_start;
2163 struct ice_aqc_lldp_set_local_mib lldp_set_mib;
2164 struct ice_aqc_lldp_stop_start_specific_agent lldp_agent_ctrl;
2165 struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl;
2166 struct ice_aqc_get_set_rss_lut get_set_rss_lut;
2167 struct ice_aqc_get_set_rss_key get_set_rss_key;
2168 struct ice_aqc_neigh_dev_req neigh_dev;
2169 struct ice_aqc_add_txqs add_txqs;
2170 struct ice_aqc_dis_txqs dis_txqs;
2171 struct ice_aqc_add_rdma_qset add_rdma_qset;
2172 struct ice_aqc_add_get_update_free_vsi vsi_cmd;
2173 struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
2174 struct ice_aqc_fw_logging fw_logging;
2175 struct ice_aqc_get_clear_fw_log get_clear_fw_log;
2176 struct ice_aqc_download_pkg download_pkg;
2177 struct ice_aqc_driver_shared_params drv_shared_params;
2178 struct ice_aqc_set_mac_lb set_mac_lb;
2179 struct ice_aqc_alloc_free_res_cmd sw_res_ctrl;
2180 struct ice_aqc_set_mac_cfg set_mac_cfg;
2181 struct ice_aqc_set_event_mask set_event_mask;
2182 struct ice_aqc_get_link_status get_link_status;
2183 struct ice_aqc_event_lan_overflow lan_overflow;
2184 struct ice_aqc_get_link_topo get_link_topo;
2185 struct ice_aqc_i2c read_write_i2c;
2186 struct ice_aqc_read_i2c_resp read_i2c_resp;
2187 } params;
2188};
2189
2190/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */
2191#define ICE_AQ_LG_BUF 512
2192
2193#define ICE_AQ_FLAG_ERR_S 2
2194#define ICE_AQ_FLAG_LB_S 9
2195#define ICE_AQ_FLAG_RD_S 10
2196#define ICE_AQ_FLAG_BUF_S 12
2197#define ICE_AQ_FLAG_SI_S 13
2198
2199#define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */
2200#define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */
2201#define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */
2202#define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */
2203#define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */
2204
2205/* error codes */
2206enum ice_aq_err {
2207 ICE_AQ_RC_OK = 0, /* Success */
2208 ICE_AQ_RC_EPERM = 1, /* Operation not permitted */
2209 ICE_AQ_RC_ENOENT = 2, /* No such element */
2210 ICE_AQ_RC_ENOMEM = 9, /* Out of memory */
2211 ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */
2212 ICE_AQ_RC_EEXIST = 13, /* Object already exists */
2213 ICE_AQ_RC_EINVAL = 14, /* Invalid argument */
2214 ICE_AQ_RC_ENOSPC = 16, /* No space left or allocation failure */
2215 ICE_AQ_RC_ENOSYS = 17, /* Function not implemented */
2216 ICE_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
2217 ICE_AQ_RC_ENOSEC = 24, /* Missing security manifest */
2218 ICE_AQ_RC_EBADSIG = 25, /* Bad RSA signature */
2219 ICE_AQ_RC_ESVN = 26, /* SVN number prohibits this package */
2220 ICE_AQ_RC_EBADMAN = 27, /* Manifest hash mismatch */
2221 ICE_AQ_RC_EBADBUF = 28, /* Buffer hash mismatches manifest */
2222};
2223
2224/* Admin Queue command opcodes */
2225enum ice_adminq_opc {
2226 /* AQ commands */
2227 ice_aqc_opc_get_ver = 0x0001,
2228 ice_aqc_opc_driver_ver = 0x0002,
2229 ice_aqc_opc_q_shutdown = 0x0003,
2230
2231 /* resource ownership */
2232 ice_aqc_opc_req_res = 0x0008,
2233 ice_aqc_opc_release_res = 0x0009,
2234
2235 /* device/function capabilities */
2236 ice_aqc_opc_list_func_caps = 0x000A,
2237 ice_aqc_opc_list_dev_caps = 0x000B,
2238
2239 /* manage MAC address */
2240 ice_aqc_opc_manage_mac_read = 0x0107,
2241 ice_aqc_opc_manage_mac_write = 0x0108,
2242
2243 /* PXE */
2244 ice_aqc_opc_clear_pxe_mode = 0x0110,
2245
2246 /* internal switch commands */
2247 ice_aqc_opc_get_sw_cfg = 0x0200,
2248 ice_aqc_opc_set_port_params = 0x0203,
2249
2250 /* Alloc/Free/Get Resources */
2251 ice_aqc_opc_alloc_res = 0x0208,
2252 ice_aqc_opc_free_res = 0x0209,
2253 ice_aqc_opc_set_vlan_mode_parameters = 0x020C,
2254 ice_aqc_opc_get_vlan_mode_parameters = 0x020D,
2255
2256 /* VSI commands */
2257 ice_aqc_opc_add_vsi = 0x0210,
2258 ice_aqc_opc_update_vsi = 0x0211,
2259 ice_aqc_opc_free_vsi = 0x0213,
2260
2261 /* recipe commands */
2262 ice_aqc_opc_add_recipe = 0x0290,
2263 ice_aqc_opc_recipe_to_profile = 0x0291,
2264 ice_aqc_opc_get_recipe = 0x0292,
2265 ice_aqc_opc_get_recipe_to_profile = 0x0293,
2266
2267 /* switch rules population commands */
2268 ice_aqc_opc_add_sw_rules = 0x02A0,
2269 ice_aqc_opc_update_sw_rules = 0x02A1,
2270 ice_aqc_opc_remove_sw_rules = 0x02A2,
2271
2272 ice_aqc_opc_clear_pf_cfg = 0x02A4,
2273
2274 /* DCB commands */
2275 ice_aqc_opc_query_pfc_mode = 0x0302,
2276 ice_aqc_opc_set_pfc_mode = 0x0303,
2277
2278 /* transmit scheduler commands */
2279 ice_aqc_opc_get_dflt_topo = 0x0400,
2280 ice_aqc_opc_add_sched_elems = 0x0401,
2281 ice_aqc_opc_cfg_sched_elems = 0x0403,
2282 ice_aqc_opc_get_sched_elems = 0x0404,
2283 ice_aqc_opc_move_sched_elems = 0x0408,
2284 ice_aqc_opc_suspend_sched_elems = 0x0409,
2285 ice_aqc_opc_resume_sched_elems = 0x040A,
2286 ice_aqc_opc_query_port_ets = 0x040E,
2287 ice_aqc_opc_delete_sched_elems = 0x040F,
2288 ice_aqc_opc_add_rl_profiles = 0x0410,
2289 ice_aqc_opc_query_sched_res = 0x0412,
2290 ice_aqc_opc_remove_rl_profiles = 0x0415,
2291
2292 /* PHY commands */
2293 ice_aqc_opc_get_phy_caps = 0x0600,
2294 ice_aqc_opc_set_phy_cfg = 0x0601,
2295 ice_aqc_opc_set_mac_cfg = 0x0603,
2296 ice_aqc_opc_restart_an = 0x0605,
2297 ice_aqc_opc_get_link_status = 0x0607,
2298 ice_aqc_opc_set_event_mask = 0x0613,
2299 ice_aqc_opc_set_mac_lb = 0x0620,
2300 ice_aqc_opc_get_link_topo = 0x06E0,
2301 ice_aqc_opc_read_i2c = 0x06E2,
2302 ice_aqc_opc_write_i2c = 0x06E3,
2303 ice_aqc_opc_set_port_id_led = 0x06E9,
2304 ice_aqc_opc_get_port_options = 0x06EA,
2305 ice_aqc_opc_set_port_option = 0x06EB,
2306 ice_aqc_opc_set_gpio = 0x06EC,
2307 ice_aqc_opc_get_gpio = 0x06ED,
2308 ice_aqc_opc_sff_eeprom = 0x06EE,
2309
2310 /* NVM commands */
2311 ice_aqc_opc_nvm_read = 0x0701,
2312 ice_aqc_opc_nvm_erase = 0x0702,
2313 ice_aqc_opc_nvm_write = 0x0703,
2314 ice_aqc_opc_nvm_checksum = 0x0706,
2315 ice_aqc_opc_nvm_write_activate = 0x0707,
2316 ice_aqc_opc_nvm_update_empr = 0x0709,
2317 ice_aqc_opc_nvm_pkg_data = 0x070A,
2318 ice_aqc_opc_nvm_pass_component_tbl = 0x070B,
2319
2320 /* PF/VF mailbox commands */
2321 ice_mbx_opc_send_msg_to_pf = 0x0801,
2322 ice_mbx_opc_send_msg_to_vf = 0x0802,
2323 /* LLDP commands */
2324 ice_aqc_opc_lldp_get_mib = 0x0A00,
2325 ice_aqc_opc_lldp_set_mib_change = 0x0A01,
2326 ice_aqc_opc_lldp_stop = 0x0A05,
2327 ice_aqc_opc_lldp_start = 0x0A06,
2328 ice_aqc_opc_get_cee_dcb_cfg = 0x0A07,
2329 ice_aqc_opc_lldp_set_local_mib = 0x0A08,
2330 ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
2331 ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
2332
2333 /* RSS commands */
2334 ice_aqc_opc_set_rss_key = 0x0B02,
2335 ice_aqc_opc_set_rss_lut = 0x0B03,
2336 ice_aqc_opc_get_rss_key = 0x0B04,
2337 ice_aqc_opc_get_rss_lut = 0x0B05,
2338
2339 /* Sideband Control Interface commands */
2340 ice_aqc_opc_neighbour_device_request = 0x0C00,
2341
2342 /* Tx queue handling commands/events */
2343 ice_aqc_opc_add_txqs = 0x0C30,
2344 ice_aqc_opc_dis_txqs = 0x0C31,
2345 ice_aqc_opc_add_rdma_qset = 0x0C33,
2346
2347 /* package commands */
2348 ice_aqc_opc_download_pkg = 0x0C40,
2349 ice_aqc_opc_upload_section = 0x0C41,
2350 ice_aqc_opc_update_pkg = 0x0C42,
2351 ice_aqc_opc_get_pkg_info_list = 0x0C43,
2352
2353 ice_aqc_opc_driver_shared_params = 0x0C90,
2354
2355 /* Standalone Commands/Events */
2356 ice_aqc_opc_event_lan_overflow = 0x1001,
2357
2358 /* debug commands */
2359 ice_aqc_opc_fw_logging = 0xFF09,
2360 ice_aqc_opc_fw_logging_info = 0xFF10,
2361};
2362
2363#endif /* _ICE_ADMINQ_CMD_H_ */