1/*
  2 * QorIQ 10G MDIO Controller
  3 *
  4 * Copyright 2012 Freescale Semiconductor, Inc.
  5 * Copyright 2021 NXP
  6 *
  7 * Authors: Andy Fleming <afleming@freescale.com>
  8 *          Timur Tabi <timur@freescale.com>
  9 *
 10 * This file is licensed under the terms of the GNU General Public License
 11 * version 2.  This program is licensed "as is" without any warranty of any
 12 * kind, whether express or implied.
 13 */
 14
 15#include <linux/acpi.h>
 16#include <linux/acpi_mdio.h>
 17#include <linux/clk.h>
 18#include <linux/interrupt.h>
 19#include <linux/kernel.h>
 20#include <linux/mdio.h>
 21#include <linux/module.h>
 22#include <linux/of_address.h>
 23#include <linux/of_mdio.h>
 24#include <linux/of_platform.h>
 25#include <linux/phy.h>
 26#include <linux/slab.h>
 27
 28/* Number of microseconds to wait for a register to respond */
 29#define TIMEOUT	1000
 30
 31struct tgec_mdio_controller {
 32	__be32	reserved[12];
 33	__be32	mdio_stat;	/* MDIO configuration and status */
 34	__be32	mdio_ctl;	/* MDIO control */
 35	__be32	mdio_data;	/* MDIO data */
 36	__be32	mdio_addr;	/* MDIO address */
 37} __packed;
 38
 39#define MDIO_STAT_ENC		BIT(6)
 40#define MDIO_STAT_CLKDIV(x)	(((x) & 0x1ff) << 7)
 41#define MDIO_STAT_BSY		BIT(0)
 42#define MDIO_STAT_RD_ER		BIT(1)
 43#define MDIO_STAT_PRE_DIS	BIT(5)
 44#define MDIO_CTL_DEV_ADDR(x) 	(x & 0x1f)
 45#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)
 46#define MDIO_CTL_PRE_DIS	BIT(10)
 47#define MDIO_CTL_SCAN_EN	BIT(11)
 48#define MDIO_CTL_POST_INC	BIT(14)
 49#define MDIO_CTL_READ		BIT(15)
 50
 51#define MDIO_DATA(x)		(x & 0xffff)
 52
 53struct mdio_fsl_priv {
 54	struct	tgec_mdio_controller __iomem *mdio_base;
 55	struct	clk *enet_clk;
 56	u32	mdc_freq;
 57	bool	is_little_endian;
 58	bool	has_a009885;
 59	bool	has_a011043;
 60};
 61
 62static u32 xgmac_read32(void __iomem *regs,
 63			bool is_little_endian)
 64{
 65	if (is_little_endian)
 66		return ioread32(regs);
 67	else
 68		return ioread32be(regs);
 69}
 70
 71static void xgmac_write32(u32 value,
 72			  void __iomem *regs,
 73			  bool is_little_endian)
 74{
 75	if (is_little_endian)
 76		iowrite32(value, regs);
 77	else
 78		iowrite32be(value, regs);
 79}
 80
 81/*
 82 * Wait until the MDIO bus is free
 83 */
 84static int xgmac_wait_until_free(struct device *dev,
 85				 struct tgec_mdio_controller __iomem *regs,
 86				 bool is_little_endian)
 87{
 88	unsigned int timeout;
 89
 90	/* Wait till the bus is free */
 91	timeout = TIMEOUT;
 92	while ((xgmac_read32(&regs->mdio_stat, is_little_endian) &
 93		MDIO_STAT_BSY) && timeout) {
 94		cpu_relax();
 95		timeout--;
 96	}
 97
 98	if (!timeout) {
 99		dev_err(dev, "timeout waiting for bus to be free\n");
100		return -ETIMEDOUT;
101	}
102
103	return 0;
104}
105
106/*
107 * Wait till the MDIO read or write operation is complete
108 */
109static int xgmac_wait_until_done(struct device *dev,
110				 struct tgec_mdio_controller __iomem *regs,
111				 bool is_little_endian)
112{
113	unsigned int timeout;
114
115	/* Wait till the MDIO write is complete */
116	timeout = TIMEOUT;
117	while ((xgmac_read32(&regs->mdio_stat, is_little_endian) &
118		MDIO_STAT_BSY) && timeout) {
119		cpu_relax();
120		timeout--;
121	}
122
123	if (!timeout) {
124		dev_err(dev, "timeout waiting for operation to complete\n");
125		return -ETIMEDOUT;
126	}
127
128	return 0;
129}
130
131/*
132 * Write value to the PHY for this device to the register at regnum,waiting
133 * until the write is done before it returns.  All PHY configuration has to be
134 * done through the TSEC1 MIIM regs.
135 */
136static int xgmac_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
137{
138	struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
139	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
140	uint16_t dev_addr;
141	u32 mdio_ctl, mdio_stat;
142	int ret;
143	bool endian = priv->is_little_endian;
144
145	mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
146	if (regnum & MII_ADDR_C45) {
147		/* Clause 45 (ie 10G) */
148		dev_addr = (regnum >> 16) & 0x1f;
149		mdio_stat |= MDIO_STAT_ENC;
150	} else {
151		/* Clause 22 (ie 1G) */
152		dev_addr = regnum & 0x1f;
153		mdio_stat &= ~MDIO_STAT_ENC;
154	}
155
156	xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
157
158	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
159	if (ret)
160		return ret;
161
162	/* Set the port and dev addr */
163	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
164	xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
165
166	/* Set the register address */
167	if (regnum & MII_ADDR_C45) {
168		xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian);
169
170		ret = xgmac_wait_until_free(&bus->dev, regs, endian);
171		if (ret)
172			return ret;
173	}
174
175	/* Write the value to the register */
176	xgmac_write32(MDIO_DATA(value), &regs->mdio_data, endian);
177
178	ret = xgmac_wait_until_done(&bus->dev, regs, endian);
179	if (ret)
180		return ret;
181
182	return 0;
183}
184
185/*
186 * Reads from register regnum in the PHY for device dev, returning the value.
187 * Clears miimcom first.  All PHY configuration has to be done through the
188 * TSEC1 MIIM regs.
189 */
190static int xgmac_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
191{
192	struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
193	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
194	unsigned long flags;
195	uint16_t dev_addr;
196	uint32_t mdio_stat;
197	uint32_t mdio_ctl;
198	int ret;
199	bool endian = priv->is_little_endian;
200
201	mdio_stat = xgmac_read32(&regs->mdio_stat, endian);
202	if (regnum & MII_ADDR_C45) {
203		dev_addr = (regnum >> 16) & 0x1f;
204		mdio_stat |= MDIO_STAT_ENC;
205	} else {
206		dev_addr = regnum & 0x1f;
207		mdio_stat &= ~MDIO_STAT_ENC;
208	}
209
210	xgmac_write32(mdio_stat, &regs->mdio_stat, endian);
211
212	ret = xgmac_wait_until_free(&bus->dev, regs, endian);
213	if (ret)
214		return ret;
215
216	/* Set the Port and Device Addrs */
217	mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
218	xgmac_write32(mdio_ctl, &regs->mdio_ctl, endian);
219
220	/* Set the register address */
221	if (regnum & MII_ADDR_C45) {
222		xgmac_write32(regnum & 0xffff, &regs->mdio_addr, endian);
223
224		ret = xgmac_wait_until_free(&bus->dev, regs, endian);
225		if (ret)
226			return ret;
227	}
228
229	if (priv->has_a009885)
230		/* Once the operation completes, i.e. MDIO_STAT_BSY clears, we
231		 * must read back the data register within 16 MDC cycles.
232		 */
233		local_irq_save(flags);
234
235	/* Initiate the read */
236	xgmac_write32(mdio_ctl | MDIO_CTL_READ, &regs->mdio_ctl, endian);
237
238	ret = xgmac_wait_until_done(&bus->dev, regs, endian);
239	if (ret)
240		goto irq_restore;
241
242	/* Return all Fs if nothing was there */
243	if ((xgmac_read32(&regs->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
244	    !priv->has_a011043) {
245		dev_dbg(&bus->dev,
246			"Error while reading PHY%d reg at %d.%d\n",
247			phy_id, dev_addr, regnum);
248		ret = 0xffff;
249	} else {
250		ret = xgmac_read32(&regs->mdio_data, endian) & 0xffff;
251		dev_dbg(&bus->dev, "read %04x\n", ret);
252	}
253
254irq_restore:
255	if (priv->has_a009885)
256		local_irq_restore(flags);
257
258	return ret;
259}
260
261static int xgmac_mdio_set_mdc_freq(struct mii_bus *bus)
262{
263	struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
264	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
265	struct device *dev = bus->parent;
266	u32 mdio_stat, div;
267
268	if (device_property_read_u32(dev, "clock-frequency", &priv->mdc_freq))
269		return 0;
270
271	priv->enet_clk = devm_clk_get(dev, NULL);
272	if (IS_ERR(priv->enet_clk)) {
273		dev_err(dev, "Input clock unknown, not changing MDC frequency");
274		return PTR_ERR(priv->enet_clk);
275	}
276
277	div = ((clk_get_rate(priv->enet_clk) / priv->mdc_freq) - 1) / 2;
278	if (div < 5 || div > 0x1ff) {
279		dev_err(dev, "Requested MDC frequency is out of range, ignoring");
280		return -EINVAL;
281	}
282
283	mdio_stat = xgmac_read32(&regs->mdio_stat, priv->is_little_endian);
284	mdio_stat &= ~MDIO_STAT_CLKDIV(0x1ff);
285	mdio_stat |= MDIO_STAT_CLKDIV(div);
286	xgmac_write32(mdio_stat, &regs->mdio_stat, priv->is_little_endian);
287	return 0;
288}
289
290static void xgmac_mdio_set_suppress_preamble(struct mii_bus *bus)
291{
292	struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
293	struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
294	struct device *dev = bus->parent;
295	u32 mdio_stat;
296
297	if (!device_property_read_bool(dev, "suppress-preamble"))
298		return;
299
300	mdio_stat = xgmac_read32(&regs->mdio_stat, priv->is_little_endian);
301	mdio_stat |= MDIO_STAT_PRE_DIS;
302	xgmac_write32(mdio_stat, &regs->mdio_stat, priv->is_little_endian);
303}
304
305static int xgmac_mdio_probe(struct platform_device *pdev)
306{
307	struct fwnode_handle *fwnode;
308	struct mdio_fsl_priv *priv;
309	struct resource *res;
310	struct mii_bus *bus;
311	int ret;
312
313	/* In DPAA-1, MDIO is one of the many FMan sub-devices. The FMan
314	 * defines a register space that spans a large area, covering all the
315	 * subdevice areas. Therefore, MDIO cannot claim exclusive access to
316	 * this register area.
317	 */
318	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
319	if (!res) {
320		dev_err(&pdev->dev, "could not obtain address\n");
321		return -EINVAL;
322	}
323
324	bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(struct mdio_fsl_priv));
325	if (!bus)
326		return -ENOMEM;
327
328	bus->name = "Freescale XGMAC MDIO Bus";
329	bus->read = xgmac_mdio_read;
330	bus->write = xgmac_mdio_write;
331	bus->parent = &pdev->dev;
332	bus->probe_capabilities = MDIOBUS_C22_C45;
333	snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);
334
335	priv = bus->priv;
336	priv->mdio_base = devm_ioremap(&pdev->dev, res->start,
337				       resource_size(res));
338	if (!priv->mdio_base)
339		return -ENOMEM;
340
341	/* For both ACPI and DT cases, endianness of MDIO controller
342	 * needs to be specified using "little-endian" property.
343	 */
344	priv->is_little_endian = device_property_read_bool(&pdev->dev,
345							   "little-endian");
346
347	priv->has_a009885 = device_property_read_bool(&pdev->dev,
348						      "fsl,erratum-a009885");
349	priv->has_a011043 = device_property_read_bool(&pdev->dev,
350						      "fsl,erratum-a011043");
351
352	xgmac_mdio_set_suppress_preamble(bus);
353
354	ret = xgmac_mdio_set_mdc_freq(bus);
355	if (ret)
356		return ret;
357
358	fwnode = dev_fwnode(&pdev->dev);
359	if (is_of_node(fwnode))
360		ret = of_mdiobus_register(bus, to_of_node(fwnode));
361	else if (is_acpi_node(fwnode))
362		ret = acpi_mdiobus_register(bus, fwnode);
363	else
364		ret = -EINVAL;
365	if (ret) {
366		dev_err(&pdev->dev, "cannot register MDIO bus\n");
367		return ret;
368	}
369
370	platform_set_drvdata(pdev, bus);
371
372	return 0;
373}
374
375static const struct of_device_id xgmac_mdio_match[] = {
376	{
377		.compatible = "fsl,fman-xmdio",
378	},
379	{
380		.compatible = "fsl,fman-memac-mdio",
381	},
382	{},
383};
384MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
385
386static const struct acpi_device_id xgmac_acpi_match[] = {
387	{ "NXP0006" },
388	{ }
389};
390MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match);
391
392static struct platform_driver xgmac_mdio_driver = {
393	.driver = {
394		.name = "fsl-fman_xmdio",
395		.of_match_table = xgmac_mdio_match,
396		.acpi_match_table = xgmac_acpi_match,
397	},
398	.probe = xgmac_mdio_probe,
399};
400
401module_platform_driver(xgmac_mdio_driver);
402
403MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
404MODULE_LICENSE("GPL v2");