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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef FS_ENET_H
3#define FS_ENET_H
4
5#include <linux/mii.h>
6#include <linux/netdevice.h>
7#include <linux/types.h>
8#include <linux/list.h>
9#include <linux/phy.h>
10#include <linux/dma-mapping.h>
11
12#include <linux/fs_enet_pd.h>
13#include <asm/fs_pd.h>
14
15#ifdef CONFIG_CPM1
16#include <asm/cpm1.h>
17#endif
18
19#if defined(CONFIG_FS_ENET_HAS_FEC)
20#include <asm/cpm.h>
21
22#if defined(CONFIG_FS_ENET_MPC5121_FEC)
23/* MPC5121 FEC has different register layout */
24struct fec {
25 u32 fec_reserved0;
26 u32 fec_ievent; /* Interrupt event reg */
27 u32 fec_imask; /* Interrupt mask reg */
28 u32 fec_reserved1;
29 u32 fec_r_des_active; /* Receive descriptor reg */
30 u32 fec_x_des_active; /* Transmit descriptor reg */
31 u32 fec_reserved2[3];
32 u32 fec_ecntrl; /* Ethernet control reg */
33 u32 fec_reserved3[6];
34 u32 fec_mii_data; /* MII manage frame reg */
35 u32 fec_mii_speed; /* MII speed control reg */
36 u32 fec_reserved4[7];
37 u32 fec_mib_ctrlstat; /* MIB control/status reg */
38 u32 fec_reserved5[7];
39 u32 fec_r_cntrl; /* Receive control reg */
40 u32 fec_reserved6[15];
41 u32 fec_x_cntrl; /* Transmit Control reg */
42 u32 fec_reserved7[7];
43 u32 fec_addr_low; /* Low 32bits MAC address */
44 u32 fec_addr_high; /* High 16bits MAC address */
45 u32 fec_opd; /* Opcode + Pause duration */
46 u32 fec_reserved8[10];
47 u32 fec_hash_table_high; /* High 32bits hash table */
48 u32 fec_hash_table_low; /* Low 32bits hash table */
49 u32 fec_grp_hash_table_high; /* High 32bits hash table */
50 u32 fec_grp_hash_table_low; /* Low 32bits hash table */
51 u32 fec_reserved9[7];
52 u32 fec_x_wmrk; /* FIFO transmit water mark */
53 u32 fec_reserved10;
54 u32 fec_r_bound; /* FIFO receive bound reg */
55 u32 fec_r_fstart; /* FIFO receive start reg */
56 u32 fec_reserved11[11];
57 u32 fec_r_des_start; /* Receive descriptor ring */
58 u32 fec_x_des_start; /* Transmit descriptor ring */
59 u32 fec_r_buff_size; /* Maximum receive buff size */
60 u32 fec_reserved12[26];
61 u32 fec_dma_control; /* DMA Endian and other ctrl */
62};
63#endif
64
65struct fec_info {
66 struct fec __iomem *fecp;
67 u32 mii_speed;
68};
69#endif
70
71#ifdef CONFIG_CPM2
72#include <asm/cpm2.h>
73#endif
74
75/* hw driver ops */
76struct fs_ops {
77 int (*setup_data)(struct net_device *dev);
78 int (*allocate_bd)(struct net_device *dev);
79 void (*free_bd)(struct net_device *dev);
80 void (*cleanup_data)(struct net_device *dev);
81 void (*set_multicast_list)(struct net_device *dev);
82 void (*adjust_link)(struct net_device *dev);
83 void (*restart)(struct net_device *dev);
84 void (*stop)(struct net_device *dev);
85 void (*napi_clear_event)(struct net_device *dev);
86 void (*napi_enable)(struct net_device *dev);
87 void (*napi_disable)(struct net_device *dev);
88 void (*rx_bd_done)(struct net_device *dev);
89 void (*tx_kickstart)(struct net_device *dev);
90 u32 (*get_int_events)(struct net_device *dev);
91 void (*clear_int_events)(struct net_device *dev, u32 int_events);
92 void (*ev_error)(struct net_device *dev, u32 int_events);
93 int (*get_regs)(struct net_device *dev, void *p, int *sizep);
94 int (*get_regs_len)(struct net_device *dev);
95 void (*tx_restart)(struct net_device *dev);
96};
97
98struct phy_info {
99 unsigned int id;
100 const char *name;
101 void (*startup) (struct net_device * dev);
102 void (*shutdown) (struct net_device * dev);
103 void (*ack_int) (struct net_device * dev);
104};
105
106/* The FEC stores dest/src/type, data, and checksum for receive packets.
107 */
108#define MAX_MTU 1508 /* Allow fullsized pppoe packets over VLAN */
109#define MIN_MTU 46 /* this is data size */
110#define CRC_LEN 4
111
112#define PKT_MAXBUF_SIZE (MAX_MTU+ETH_HLEN+CRC_LEN)
113#define PKT_MINBUF_SIZE (MIN_MTU+ETH_HLEN+CRC_LEN)
114
115/* Must be a multiple of 32 (to cover both FEC & FCC) */
116#define PKT_MAXBLR_SIZE ((PKT_MAXBUF_SIZE + 31) & ~31)
117/* This is needed so that invalidate_xxx wont invalidate too much */
118#define ENET_RX_ALIGN 16
119#define ENET_RX_FRSIZE L1_CACHE_ALIGN(PKT_MAXBUF_SIZE + ENET_RX_ALIGN - 1)
120
121struct fs_enet_private {
122 struct napi_struct napi;
123 struct device *dev; /* pointer back to the device (must be initialized first) */
124 struct net_device *ndev;
125 spinlock_t lock; /* during all ops except TX pckt processing */
126 spinlock_t tx_lock; /* during fs_start_xmit and fs_tx */
127 struct fs_platform_info *fpi;
128 struct work_struct timeout_work;
129 const struct fs_ops *ops;
130 int rx_ring, tx_ring;
131 dma_addr_t ring_mem_addr;
132 void __iomem *ring_base;
133 struct sk_buff **rx_skbuff;
134 struct sk_buff **tx_skbuff;
135 char *mapped_as_page;
136 cbd_t __iomem *rx_bd_base; /* Address of Rx and Tx buffers. */
137 cbd_t __iomem *tx_bd_base;
138 cbd_t __iomem *dirty_tx; /* ring entries to be free()ed. */
139 cbd_t __iomem *cur_rx;
140 cbd_t __iomem *cur_tx;
141 int tx_free;
142 const struct phy_info *phy;
143 u32 msg_enable;
144 struct mii_if_info mii_if;
145 unsigned int last_mii_status;
146 int interrupt;
147
148 int oldduplex, oldspeed, oldlink; /* current settings */
149
150 /* event masks */
151 u32 ev_napi; /* mask of NAPI events */
152 u32 ev; /* event mask */
153 u32 ev_err; /* error event mask */
154
155 u16 bd_rx_empty; /* mask of BD rx empty */
156 u16 bd_rx_err; /* mask of BD rx errors */
157
158 union {
159 struct {
160 int idx; /* FEC1 = 0, FEC2 = 1 */
161 void __iomem *fecp; /* hw registers */
162 u32 hthi, htlo; /* state for multicast */
163 } fec;
164
165 struct {
166 int idx; /* FCC1-3 = 0-2 */
167 void __iomem *fccp; /* hw registers */
168 void __iomem *ep; /* parameter ram */
169 void __iomem *fcccp; /* hw registers cont. */
170 void __iomem *mem; /* FCC DPRAM */
171 u32 gaddrh, gaddrl; /* group address */
172 } fcc;
173
174 struct {
175 int idx; /* FEC1 = 0, FEC2 = 1 */
176 void __iomem *sccp; /* hw registers */
177 void __iomem *ep; /* parameter ram */
178 u32 hthi, htlo; /* state for multicast */
179 } scc;
180
181 };
182};
183
184/***************************************************************************/
185
186void fs_init_bds(struct net_device *dev);
187void fs_cleanup_bds(struct net_device *dev);
188
189/***************************************************************************/
190
191#define DRV_MODULE_NAME "fs_enet"
192#define PFX DRV_MODULE_NAME ": "
193
194/***************************************************************************/
195
196int fs_enet_platform_init(void);
197void fs_enet_platform_cleanup(void);
198
199/***************************************************************************/
200/* buffer descriptor access macros */
201
202/* access macros */
203#if defined(CONFIG_CPM1)
204/* for a CPM1 __raw_xxx's are sufficient */
205#define __cbd_out32(addr, x) __raw_writel(x, addr)
206#define __cbd_out16(addr, x) __raw_writew(x, addr)
207#define __cbd_in32(addr) __raw_readl(addr)
208#define __cbd_in16(addr) __raw_readw(addr)
209#else
210/* for others play it safe */
211#define __cbd_out32(addr, x) out_be32(addr, x)
212#define __cbd_out16(addr, x) out_be16(addr, x)
213#define __cbd_in32(addr) in_be32(addr)
214#define __cbd_in16(addr) in_be16(addr)
215#endif
216
217/* write */
218#define CBDW_SC(_cbd, _sc) __cbd_out16(&(_cbd)->cbd_sc, (_sc))
219#define CBDW_DATLEN(_cbd, _datlen) __cbd_out16(&(_cbd)->cbd_datlen, (_datlen))
220#define CBDW_BUFADDR(_cbd, _bufaddr) __cbd_out32(&(_cbd)->cbd_bufaddr, (_bufaddr))
221
222/* read */
223#define CBDR_SC(_cbd) __cbd_in16(&(_cbd)->cbd_sc)
224#define CBDR_DATLEN(_cbd) __cbd_in16(&(_cbd)->cbd_datlen)
225#define CBDR_BUFADDR(_cbd) __cbd_in32(&(_cbd)->cbd_bufaddr)
226
227/* set bits */
228#define CBDS_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) | (_sc))
229
230/* clear bits */
231#define CBDC_SC(_cbd, _sc) CBDW_SC(_cbd, CBDR_SC(_cbd) & ~(_sc))
232
233/*******************************************************************/
234
235extern const struct fs_ops fs_fec_ops;
236extern const struct fs_ops fs_fcc_ops;
237extern const struct fs_ops fs_scc_ops;
238
239/*******************************************************************/
240
241#endif