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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Marvell 88e6xxx Ethernet switch single-chip support
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 *
7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
8 *
9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
11 */
12
13#include <linux/bitfield.h>
14#include <linux/delay.h>
15#include <linux/dsa/mv88e6xxx.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/if_bridge.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/irqdomain.h>
22#include <linux/jiffies.h>
23#include <linux/list.h>
24#include <linux/mdio.h>
25#include <linux/module.h>
26#include <linux/of_device.h>
27#include <linux/of_irq.h>
28#include <linux/of_mdio.h>
29#include <linux/platform_data/mv88e6xxx.h>
30#include <linux/netdevice.h>
31#include <linux/gpio/consumer.h>
32#include <linux/phylink.h>
33#include <net/dsa.h>
34
35#include "chip.h"
36#include "devlink.h"
37#include "global1.h"
38#include "global2.h"
39#include "hwtstamp.h"
40#include "phy.h"
41#include "port.h"
42#include "ptp.h"
43#include "serdes.h"
44#include "smi.h"
45
46static void assert_reg_lock(struct mv88e6xxx_chip *chip)
47{
48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
49 dev_err(chip->dev, "Switch registers lock not held!\n");
50 dump_stack();
51 }
52}
53
54int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
55{
56 int err;
57
58 assert_reg_lock(chip);
59
60 err = mv88e6xxx_smi_read(chip, addr, reg, val);
61 if (err)
62 return err;
63
64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
65 addr, reg, *val);
66
67 return 0;
68}
69
70int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
71{
72 int err;
73
74 assert_reg_lock(chip);
75
76 err = mv88e6xxx_smi_write(chip, addr, reg, val);
77 if (err)
78 return err;
79
80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
81 addr, reg, val);
82
83 return 0;
84}
85
86int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
87 u16 mask, u16 val)
88{
89 const unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 u16 data;
91 int err;
92 int i;
93
94 /* There's no bus specific operation to wait for a mask. Even
95 * if the initial poll takes longer than 50ms, always do at
96 * least one more attempt.
97 */
98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) {
99 err = mv88e6xxx_read(chip, addr, reg, &data);
100 if (err)
101 return err;
102
103 if ((data & mask) == val)
104 return 0;
105
106 if (i < 2)
107 cpu_relax();
108 else
109 usleep_range(1000, 2000);
110 }
111
112 dev_err(chip->dev, "Timeout while waiting for switch\n");
113 return -ETIMEDOUT;
114}
115
116int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
117 int bit, int val)
118{
119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit),
120 val ? BIT(bit) : 0x0000);
121}
122
123struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
124{
125 struct mv88e6xxx_mdio_bus *mdio_bus;
126
127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
128 list);
129 if (!mdio_bus)
130 return NULL;
131
132 return mdio_bus->bus;
133}
134
135static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
136{
137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
138 unsigned int n = d->hwirq;
139
140 chip->g1_irq.masked |= (1 << n);
141}
142
143static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
144{
145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
146 unsigned int n = d->hwirq;
147
148 chip->g1_irq.masked &= ~(1 << n);
149}
150
151static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
152{
153 unsigned int nhandled = 0;
154 unsigned int sub_irq;
155 unsigned int n;
156 u16 reg;
157 u16 ctl1;
158 int err;
159
160 mv88e6xxx_reg_lock(chip);
161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
162 mv88e6xxx_reg_unlock(chip);
163
164 if (err)
165 goto out;
166
167 do {
168 for (n = 0; n < chip->g1_irq.nirqs; ++n) {
169 if (reg & (1 << n)) {
170 sub_irq = irq_find_mapping(chip->g1_irq.domain,
171 n);
172 handle_nested_irq(sub_irq);
173 ++nhandled;
174 }
175 }
176
177 mv88e6xxx_reg_lock(chip);
178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1);
179 if (err)
180 goto unlock;
181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
182unlock:
183 mv88e6xxx_reg_unlock(chip);
184 if (err)
185 goto out;
186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0);
187 } while (reg & ctl1);
188
189out:
190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
191}
192
193static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
194{
195 struct mv88e6xxx_chip *chip = dev_id;
196
197 return mv88e6xxx_g1_irq_thread_work(chip);
198}
199
200static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
201{
202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
203
204 mv88e6xxx_reg_lock(chip);
205}
206
207static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
208{
209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
211 u16 reg;
212 int err;
213
214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®);
215 if (err)
216 goto out;
217
218 reg &= ~mask;
219 reg |= (~chip->g1_irq.masked & mask);
220
221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
222 if (err)
223 goto out;
224
225out:
226 mv88e6xxx_reg_unlock(chip);
227}
228
229static const struct irq_chip mv88e6xxx_g1_irq_chip = {
230 .name = "mv88e6xxx-g1",
231 .irq_mask = mv88e6xxx_g1_irq_mask,
232 .irq_unmask = mv88e6xxx_g1_irq_unmask,
233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock,
234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock,
235};
236
237static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
238 unsigned int irq,
239 irq_hw_number_t hwirq)
240{
241 struct mv88e6xxx_chip *chip = d->host_data;
242
243 irq_set_chip_data(irq, d->host_data);
244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
245 irq_set_noprobe(irq);
246
247 return 0;
248}
249
250static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
251 .map = mv88e6xxx_g1_irq_domain_map,
252 .xlate = irq_domain_xlate_twocell,
253};
254
255/* To be called with reg_lock held */
256static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
257{
258 int irq, virq;
259 u16 mask;
260
261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
264
265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
266 virq = irq_find_mapping(chip->g1_irq.domain, irq);
267 irq_dispose_mapping(virq);
268 }
269
270 irq_domain_remove(chip->g1_irq.domain);
271}
272
273static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
274{
275 /*
276 * free_irq must be called without reg_lock taken because the irq
277 * handler takes this lock, too.
278 */
279 free_irq(chip->irq, chip);
280
281 mv88e6xxx_reg_lock(chip);
282 mv88e6xxx_g1_irq_free_common(chip);
283 mv88e6xxx_reg_unlock(chip);
284}
285
286static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
287{
288 int err, irq, virq;
289 u16 reg, mask;
290
291 chip->g1_irq.nirqs = chip->info->g1_irqs;
292 chip->g1_irq.domain = irq_domain_add_simple(
293 NULL, chip->g1_irq.nirqs, 0,
294 &mv88e6xxx_g1_irq_domain_ops, chip);
295 if (!chip->g1_irq.domain)
296 return -ENOMEM;
297
298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
299 irq_create_mapping(chip->g1_irq.domain, irq);
300
301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
302 chip->g1_irq.masked = ~0;
303
304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
305 if (err)
306 goto out_mapping;
307
308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
309
310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
311 if (err)
312 goto out_disable;
313
314 /* Reading the interrupt status clears (most of) them */
315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®);
316 if (err)
317 goto out_disable;
318
319 return 0;
320
321out_disable:
322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
324
325out_mapping:
326 for (irq = 0; irq < 16; irq++) {
327 virq = irq_find_mapping(chip->g1_irq.domain, irq);
328 irq_dispose_mapping(virq);
329 }
330
331 irq_domain_remove(chip->g1_irq.domain);
332
333 return err;
334}
335
336static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
337{
338 static struct lock_class_key lock_key;
339 static struct lock_class_key request_key;
340 int err;
341
342 err = mv88e6xxx_g1_irq_setup_common(chip);
343 if (err)
344 return err;
345
346 /* These lock classes tells lockdep that global 1 irqs are in
347 * a different category than their parent GPIO, so it won't
348 * report false recursion.
349 */
350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key);
351
352 snprintf(chip->irq_name, sizeof(chip->irq_name),
353 "mv88e6xxx-%s", dev_name(chip->dev));
354
355 mv88e6xxx_reg_unlock(chip);
356 err = request_threaded_irq(chip->irq, NULL,
357 mv88e6xxx_g1_irq_thread_fn,
358 IRQF_ONESHOT | IRQF_SHARED,
359 chip->irq_name, chip);
360 mv88e6xxx_reg_lock(chip);
361 if (err)
362 mv88e6xxx_g1_irq_free_common(chip);
363
364 return err;
365}
366
367static void mv88e6xxx_irq_poll(struct kthread_work *work)
368{
369 struct mv88e6xxx_chip *chip = container_of(work,
370 struct mv88e6xxx_chip,
371 irq_poll_work.work);
372 mv88e6xxx_g1_irq_thread_work(chip);
373
374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
375 msecs_to_jiffies(100));
376}
377
378static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
379{
380 int err;
381
382 err = mv88e6xxx_g1_irq_setup_common(chip);
383 if (err)
384 return err;
385
386 kthread_init_delayed_work(&chip->irq_poll_work,
387 mv88e6xxx_irq_poll);
388
389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev));
390 if (IS_ERR(chip->kworker))
391 return PTR_ERR(chip->kworker);
392
393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
394 msecs_to_jiffies(100));
395
396 return 0;
397}
398
399static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
400{
401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
402 kthread_destroy_worker(chip->kworker);
403
404 mv88e6xxx_reg_lock(chip);
405 mv88e6xxx_g1_irq_free_common(chip);
406 mv88e6xxx_reg_unlock(chip);
407}
408
409static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip,
410 int port, phy_interface_t interface)
411{
412 int err;
413
414 if (chip->info->ops->port_set_rgmii_delay) {
415 err = chip->info->ops->port_set_rgmii_delay(chip, port,
416 interface);
417 if (err && err != -EOPNOTSUPP)
418 return err;
419 }
420
421 if (chip->info->ops->port_set_cmode) {
422 err = chip->info->ops->port_set_cmode(chip, port,
423 interface);
424 if (err && err != -EOPNOTSUPP)
425 return err;
426 }
427
428 return 0;
429}
430
431static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
432 int link, int speed, int duplex, int pause,
433 phy_interface_t mode)
434{
435 int err;
436
437 if (!chip->info->ops->port_set_link)
438 return 0;
439
440 /* Port's MAC control must not be changed unless the link is down */
441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);
442 if (err)
443 return err;
444
445 if (chip->info->ops->port_set_speed_duplex) {
446 err = chip->info->ops->port_set_speed_duplex(chip, port,
447 speed, duplex);
448 if (err && err != -EOPNOTSUPP)
449 goto restore_link;
450 }
451
452 if (chip->info->ops->port_set_pause) {
453 err = chip->info->ops->port_set_pause(chip, port, pause);
454 if (err)
455 goto restore_link;
456 }
457
458 err = mv88e6xxx_port_config_interface(chip, port, mode);
459restore_link:
460 if (chip->info->ops->port_set_link(chip, port, link))
461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
462
463 return err;
464}
465
466static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
467{
468 struct mv88e6xxx_chip *chip = ds->priv;
469
470 return port < chip->info->num_internal_phys;
471}
472
473static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port)
474{
475 u16 reg;
476 int err;
477
478 /* The 88e6250 family does not have the PHY detect bit. Instead,
479 * report whether the port is internal.
480 */
481 if (chip->info->family == MV88E6XXX_FAMILY_6250)
482 return port < chip->info->num_internal_phys;
483
484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
485 if (err) {
486 dev_err(chip->dev,
487 "p%d: %s: failed to read port status\n",
488 port, __func__);
489 return err;
490 }
491
492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT);
493}
494
495static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port,
496 struct phylink_link_state *state)
497{
498 struct mv88e6xxx_chip *chip = ds->priv;
499 int lane;
500 int err;
501
502 mv88e6xxx_reg_lock(chip);
503 lane = mv88e6xxx_serdes_get_lane(chip, port);
504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)
505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,
506 state);
507 else
508 err = -EOPNOTSUPP;
509 mv88e6xxx_reg_unlock(chip);
510
511 return err;
512}
513
514static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
515 unsigned int mode,
516 phy_interface_t interface,
517 const unsigned long *advertise)
518{
519 const struct mv88e6xxx_ops *ops = chip->info->ops;
520 int lane;
521
522 if (ops->serdes_pcs_config) {
523 lane = mv88e6xxx_serdes_get_lane(chip, port);
524 if (lane >= 0)
525 return ops->serdes_pcs_config(chip, port, lane, mode,
526 interface, advertise);
527 }
528
529 return 0;
530}
531
532static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port)
533{
534 struct mv88e6xxx_chip *chip = ds->priv;
535 const struct mv88e6xxx_ops *ops;
536 int err = 0;
537 int lane;
538
539 ops = chip->info->ops;
540
541 if (ops->serdes_pcs_an_restart) {
542 mv88e6xxx_reg_lock(chip);
543 lane = mv88e6xxx_serdes_get_lane(chip, port);
544 if (lane >= 0)
545 err = ops->serdes_pcs_an_restart(chip, port, lane);
546 mv88e6xxx_reg_unlock(chip);
547
548 if (err)
549 dev_err(ds->dev, "p%d: failed to restart AN\n", port);
550 }
551}
552
553static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
554 unsigned int mode,
555 int speed, int duplex)
556{
557 const struct mv88e6xxx_ops *ops = chip->info->ops;
558 int lane;
559
560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {
561 lane = mv88e6xxx_serdes_get_lane(chip, port);
562 if (lane >= 0)
563 return ops->serdes_pcs_link_up(chip, port, lane,
564 speed, duplex);
565 }
566
567 return 0;
568}
569
570static const u8 mv88e6185_phy_interface_modes[] = {
571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII,
572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII,
573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII,
574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII,
575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX,
576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX,
577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII,
578};
579
580static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
581 struct phylink_config *config)
582{
583 u8 cmode = chip->ports[port].cmode;
584
585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
586
587 if (mv88e6xxx_phy_is_internal(chip->ds, port)) {
588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
589 } else {
590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
591 mv88e6185_phy_interface_modes[cmode])
592 __set_bit(mv88e6185_phy_interface_modes[cmode],
593 config->supported_interfaces);
594
595 config->mac_capabilities |= MAC_1000FD;
596 }
597}
598
599static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
600 struct phylink_config *config)
601{
602 u8 cmode = chip->ports[port].cmode;
603
604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) &&
605 mv88e6185_phy_interface_modes[cmode])
606 __set_bit(mv88e6185_phy_interface_modes[cmode],
607 config->supported_interfaces);
608
609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
610 MAC_1000FD;
611}
612
613static const u8 mv88e6xxx_phy_interface_modes[] = {
614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_MII,
615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII,
616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII,
617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_RMII,
618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII,
619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX,
620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX,
621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII,
622 /* higher interface modes are not needed here, since ports supporting
623 * them are writable, and so the supported interfaces are filled in the
624 * corresponding .phylink_set_interfaces() implementation below
625 */
626};
627
628static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported)
629{
630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) &&
631 mv88e6xxx_phy_interface_modes[cmode])
632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported);
633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII)
634 phy_interface_set_rgmii(supported);
635}
636
637static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
638 struct phylink_config *config)
639{
640 unsigned long *supported = config->supported_interfaces;
641
642 /* Translate the default cmode */
643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
644
645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100;
646}
647
648static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip)
649{
650 u16 reg, val;
651 int err;
652
653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®);
654 if (err)
655 return err;
656
657 /* If PHY_DETECT is zero, then we are not in auto-media mode */
658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT))
659 return 0xf;
660
661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT;
662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val);
663 if (err)
664 return err;
665
666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val);
667 if (err)
668 return err;
669
670 /* Restore PHY_DETECT value */
671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg);
672 if (err)
673 return err;
674
675 return val & MV88E6XXX_PORT_STS_CMODE_MASK;
676}
677
678static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
679 struct phylink_config *config)
680{
681 unsigned long *supported = config->supported_interfaces;
682 int err, cmode;
683
684 /* Translate the default cmode */
685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
686
687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
688 MAC_1000FD;
689
690 /* Port 4 supports automedia if the serdes is associated with it. */
691 if (port == 4) {
692 err = mv88e6352_g2_scratch_port_has_serdes(chip, port);
693 if (err < 0)
694 dev_err(chip->dev, "p%d: failed to read scratch\n",
695 port);
696 if (err <= 0)
697 return;
698
699 cmode = mv88e6352_get_port4_serdes_cmode(chip);
700 if (cmode < 0)
701 dev_err(chip->dev, "p%d: failed to read serdes cmode\n",
702 port);
703 else
704 mv88e6xxx_translate_cmode(cmode, supported);
705 }
706}
707
708static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
709 struct phylink_config *config)
710{
711 unsigned long *supported = config->supported_interfaces;
712
713 /* Translate the default cmode */
714 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
715
716 /* No ethtool bits for 200Mbps */
717 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
718 MAC_1000FD;
719
720 /* The C_Mode field is programmable on port 5 */
721 if (port == 5) {
722 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
724 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
725
726 config->mac_capabilities |= MAC_2500FD;
727 }
728}
729
730static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
731 struct phylink_config *config)
732{
733 unsigned long *supported = config->supported_interfaces;
734
735 /* Translate the default cmode */
736 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
737
738 /* No ethtool bits for 200Mbps */
739 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
740 MAC_1000FD;
741
742 /* The C_Mode field is programmable on ports 9 and 10 */
743 if (port == 9 || port == 10) {
744 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
745 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
746 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
747
748 config->mac_capabilities |= MAC_2500FD;
749 }
750}
751
752static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
753 struct phylink_config *config)
754{
755 unsigned long *supported = config->supported_interfaces;
756
757 mv88e6390_phylink_get_caps(chip, port, config);
758
759 /* For the 6x90X, ports 2-7 can be in automedia mode.
760 * (Note that 6x90 doesn't support RXAUI nor XAUI).
761 *
762 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is
763 * configured for 1000BASE-X, SGMII or 2500BASE-X.
764 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is
765 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
766 *
767 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is
768 * configured for 1000BASE-X, SGMII or 2500BASE-X.
769 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is
770 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X.
771 *
772 * For now, be permissive (as the old code was) and allow 1000BASE-X
773 * on ports 2..7.
774 */
775 if (port >= 2 && port <= 7)
776 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
777
778 /* The C_Mode field can also be programmed for 10G speeds */
779 if (port == 9 || port == 10) {
780 __set_bit(PHY_INTERFACE_MODE_XAUI, supported);
781 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported);
782
783 config->mac_capabilities |= MAC_10000FD;
784 }
785}
786
787static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port,
788 struct phylink_config *config)
789{
790 unsigned long *supported = config->supported_interfaces;
791 bool is_6191x =
792 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X;
793
794 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported);
795
796 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 |
797 MAC_1000FD;
798
799 /* The C_Mode field can be programmed for ports 0, 9 and 10 */
800 if (port == 0 || port == 9 || port == 10) {
801 __set_bit(PHY_INTERFACE_MODE_SGMII, supported);
802 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
803
804 /* 6191X supports >1G modes only on port 10 */
805 if (!is_6191x || port == 10) {
806 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
807 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported);
808 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
809 /* FIXME: USXGMII is not supported yet */
810 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */
811
812 config->mac_capabilities |= MAC_2500FD | MAC_5000FD |
813 MAC_10000FD;
814 }
815 }
816
817 if (port == 0) {
818 __set_bit(PHY_INTERFACE_MODE_RMII, supported);
819 __set_bit(PHY_INTERFACE_MODE_RGMII, supported);
820 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported);
821 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported);
822 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported);
823 }
824}
825
826static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port,
827 struct phylink_config *config)
828{
829 struct mv88e6xxx_chip *chip = ds->priv;
830
831 mv88e6xxx_reg_lock(chip);
832 chip->info->ops->phylink_get_caps(chip, port, config);
833 mv88e6xxx_reg_unlock(chip);
834
835 if (mv88e6xxx_phy_is_internal(ds, port)) {
836 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
837 config->supported_interfaces);
838 /* Internal ports with no phy-mode need GMII for PHYLIB */
839 __set_bit(PHY_INTERFACE_MODE_GMII,
840 config->supported_interfaces);
841 }
842}
843
844static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
845 unsigned int mode,
846 const struct phylink_link_state *state)
847{
848 struct mv88e6xxx_chip *chip = ds->priv;
849 struct mv88e6xxx_port *p;
850 int err = 0;
851
852 p = &chip->ports[port];
853
854 mv88e6xxx_reg_lock(chip);
855
856 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) {
857 /* In inband mode, the link may come up at any time while the
858 * link is not forced down. Force the link down while we
859 * reconfigure the interface mode.
860 */
861 if (mode == MLO_AN_INBAND &&
862 p->interface != state->interface &&
863 chip->info->ops->port_set_link)
864 chip->info->ops->port_set_link(chip, port,
865 LINK_FORCED_DOWN);
866
867 err = mv88e6xxx_port_config_interface(chip, port,
868 state->interface);
869 if (err && err != -EOPNOTSUPP)
870 goto err_unlock;
871
872 err = mv88e6xxx_serdes_pcs_config(chip, port, mode,
873 state->interface,
874 state->advertising);
875 /* FIXME: we should restart negotiation if something changed -
876 * which is something we get if we convert to using phylinks
877 * PCS operations.
878 */
879 if (err > 0)
880 err = 0;
881 }
882
883 /* Undo the forced down state above after completing configuration
884 * irrespective of its state on entry, which allows the link to come
885 * up in the in-band case where there is no separate SERDES. Also
886 * ensure that the link can come up if the PPU is in use and we are
887 * in PHY mode (we treat the PPU as an effective in-band mechanism.)
888 */
889 if (chip->info->ops->port_set_link &&
890 ((mode == MLO_AN_INBAND && p->interface != state->interface) ||
891 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port))))
892 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED);
893
894 p->interface = state->interface;
895
896err_unlock:
897 mv88e6xxx_reg_unlock(chip);
898
899 if (err && err != -EOPNOTSUPP)
900 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port);
901}
902
903static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
904 unsigned int mode,
905 phy_interface_t interface)
906{
907 struct mv88e6xxx_chip *chip = ds->priv;
908 const struct mv88e6xxx_ops *ops;
909 int err = 0;
910
911 ops = chip->info->ops;
912
913 mv88e6xxx_reg_lock(chip);
914 /* Force the link down if we know the port may not be automatically
915 * updated by the switch or if we are using fixed-link mode.
916 */
917 if ((!mv88e6xxx_port_ppu_updates(chip, port) ||
918 mode == MLO_AN_FIXED) && ops->port_sync_link)
919 err = ops->port_sync_link(chip, port, mode, false);
920
921 if (!err && ops->port_set_speed_duplex)
922 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED,
923 DUPLEX_UNFORCED);
924 mv88e6xxx_reg_unlock(chip);
925
926 if (err)
927 dev_err(chip->dev,
928 "p%d: failed to force MAC link down\n", port);
929}
930
931static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
932 unsigned int mode, phy_interface_t interface,
933 struct phy_device *phydev,
934 int speed, int duplex,
935 bool tx_pause, bool rx_pause)
936{
937 struct mv88e6xxx_chip *chip = ds->priv;
938 const struct mv88e6xxx_ops *ops;
939 int err = 0;
940
941 ops = chip->info->ops;
942
943 mv88e6xxx_reg_lock(chip);
944 /* Configure and force the link up if we know that the port may not
945 * automatically updated by the switch or if we are using fixed-link
946 * mode.
947 */
948 if (!mv88e6xxx_port_ppu_updates(chip, port) ||
949 mode == MLO_AN_FIXED) {
950 /* FIXME: for an automedia port, should we force the link
951 * down here - what if the link comes up due to "other" media
952 * while we're bringing the port up, how is the exclusivity
953 * handled in the Marvell hardware? E.g. port 2 on 88E6390
954 * shared between internal PHY and Serdes.
955 */
956 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed,
957 duplex);
958 if (err)
959 goto error;
960
961 if (ops->port_set_speed_duplex) {
962 err = ops->port_set_speed_duplex(chip, port,
963 speed, duplex);
964 if (err && err != -EOPNOTSUPP)
965 goto error;
966 }
967
968 if (ops->port_sync_link)
969 err = ops->port_sync_link(chip, port, mode, true);
970 }
971error:
972 mv88e6xxx_reg_unlock(chip);
973
974 if (err && err != -EOPNOTSUPP)
975 dev_err(ds->dev,
976 "p%d: failed to configure MAC link up\n", port);
977}
978
979static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
980{
981 if (!chip->info->ops->stats_snapshot)
982 return -EOPNOTSUPP;
983
984 return chip->info->ops->stats_snapshot(chip, port);
985}
986
987static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
988 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, },
989 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, },
990 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, },
991 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, },
992 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, },
993 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, },
994 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, },
995 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, },
996 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, },
997 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, },
998 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, },
999 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, },
1000 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, },
1001 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, },
1002 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, },
1003 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, },
1004 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, },
1005 { "excessive", 4, 0x11, STATS_TYPE_BANK0, },
1006 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, },
1007 { "deferred", 4, 0x05, STATS_TYPE_BANK0, },
1008 { "single", 4, 0x14, STATS_TYPE_BANK0, },
1009 { "multiple", 4, 0x17, STATS_TYPE_BANK0, },
1010 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, },
1011 { "late", 4, 0x1f, STATS_TYPE_BANK0, },
1012 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, },
1013 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, },
1014 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, },
1015 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, },
1016 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, },
1017 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, },
1018 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, },
1019 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, },
1020 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, },
1021 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, },
1022 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, },
1023 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, },
1024 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, },
1025 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, },
1026 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, },
1027 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, },
1028 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, },
1029 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, },
1030 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, },
1031 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, },
1032 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, },
1033 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, },
1034 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, },
1035 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, },
1036 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, },
1037 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, },
1038 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, },
1039 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, },
1040 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, },
1041 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, },
1042 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, },
1043 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, },
1044 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, },
1045 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, },
1046 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, },
1047};
1048
1049static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
1050 struct mv88e6xxx_hw_stat *s,
1051 int port, u16 bank1_select,
1052 u16 histogram)
1053{
1054 u32 low;
1055 u32 high = 0;
1056 u16 reg = 0;
1057 int err;
1058 u64 value;
1059
1060 switch (s->type) {
1061 case STATS_TYPE_PORT:
1062 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
1063 if (err)
1064 return U64_MAX;
1065
1066 low = reg;
1067 if (s->size == 4) {
1068 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
1069 if (err)
1070 return U64_MAX;
1071 low |= ((u32)reg) << 16;
1072 }
1073 break;
1074 case STATS_TYPE_BANK1:
1075 reg = bank1_select;
1076 fallthrough;
1077 case STATS_TYPE_BANK0:
1078 reg |= s->reg | histogram;
1079 mv88e6xxx_g1_stats_read(chip, reg, &low);
1080 if (s->size == 8)
1081 mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
1082 break;
1083 default:
1084 return U64_MAX;
1085 }
1086 value = (((u64)high) << 32) | low;
1087 return value;
1088}
1089
1090static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
1091 uint8_t *data, int types)
1092{
1093 struct mv88e6xxx_hw_stat *stat;
1094 int i, j;
1095
1096 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1097 stat = &mv88e6xxx_hw_stats[i];
1098 if (stat->type & types) {
1099 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
1100 ETH_GSTRING_LEN);
1101 j++;
1102 }
1103 }
1104
1105 return j;
1106}
1107
1108static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
1109 uint8_t *data)
1110{
1111 return mv88e6xxx_stats_get_strings(chip, data,
1112 STATS_TYPE_BANK0 | STATS_TYPE_PORT);
1113}
1114
1115static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip,
1116 uint8_t *data)
1117{
1118 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0);
1119}
1120
1121static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
1122 uint8_t *data)
1123{
1124 return mv88e6xxx_stats_get_strings(chip, data,
1125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
1126}
1127
1128static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
1129 "atu_member_violation",
1130 "atu_miss_violation",
1131 "atu_full_violation",
1132 "vtu_member_violation",
1133 "vtu_miss_violation",
1134};
1135
1136static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
1137{
1138 unsigned int i;
1139
1140 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
1141 strscpy(data + i * ETH_GSTRING_LEN,
1142 mv88e6xxx_atu_vtu_stats_strings[i],
1143 ETH_GSTRING_LEN);
1144}
1145
1146static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
1147 u32 stringset, uint8_t *data)
1148{
1149 struct mv88e6xxx_chip *chip = ds->priv;
1150 int count = 0;
1151
1152 if (stringset != ETH_SS_STATS)
1153 return;
1154
1155 mv88e6xxx_reg_lock(chip);
1156
1157 if (chip->info->ops->stats_get_strings)
1158 count = chip->info->ops->stats_get_strings(chip, data);
1159
1160 if (chip->info->ops->serdes_get_strings) {
1161 data += count * ETH_GSTRING_LEN;
1162 count = chip->info->ops->serdes_get_strings(chip, port, data);
1163 }
1164
1165 data += count * ETH_GSTRING_LEN;
1166 mv88e6xxx_atu_vtu_get_strings(data);
1167
1168 mv88e6xxx_reg_unlock(chip);
1169}
1170
1171static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
1172 int types)
1173{
1174 struct mv88e6xxx_hw_stat *stat;
1175 int i, j;
1176
1177 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1178 stat = &mv88e6xxx_hw_stats[i];
1179 if (stat->type & types)
1180 j++;
1181 }
1182 return j;
1183}
1184
1185static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1186{
1187 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1188 STATS_TYPE_PORT);
1189}
1190
1191static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1192{
1193 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0);
1194}
1195
1196static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
1197{
1198 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
1199 STATS_TYPE_BANK1);
1200}
1201
1202static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1203{
1204 struct mv88e6xxx_chip *chip = ds->priv;
1205 int serdes_count = 0;
1206 int count = 0;
1207
1208 if (sset != ETH_SS_STATS)
1209 return 0;
1210
1211 mv88e6xxx_reg_lock(chip);
1212 if (chip->info->ops->stats_get_sset_count)
1213 count = chip->info->ops->stats_get_sset_count(chip);
1214 if (count < 0)
1215 goto out;
1216
1217 if (chip->info->ops->serdes_get_sset_count)
1218 serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1219 port);
1220 if (serdes_count < 0) {
1221 count = serdes_count;
1222 goto out;
1223 }
1224 count += serdes_count;
1225 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1226
1227out:
1228 mv88e6xxx_reg_unlock(chip);
1229
1230 return count;
1231}
1232
1233static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1234 uint64_t *data, int types,
1235 u16 bank1_select, u16 histogram)
1236{
1237 struct mv88e6xxx_hw_stat *stat;
1238 int i, j;
1239
1240 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1241 stat = &mv88e6xxx_hw_stats[i];
1242 if (stat->type & types) {
1243 mv88e6xxx_reg_lock(chip);
1244 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1245 bank1_select,
1246 histogram);
1247 mv88e6xxx_reg_unlock(chip);
1248
1249 j++;
1250 }
1251 }
1252 return j;
1253}
1254
1255static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1256 uint64_t *data)
1257{
1258 return mv88e6xxx_stats_get_stats(chip, port, data,
1259 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1260 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1261}
1262
1263static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1264 uint64_t *data)
1265{
1266 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0,
1267 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1268}
1269
1270static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1271 uint64_t *data)
1272{
1273 return mv88e6xxx_stats_get_stats(chip, port, data,
1274 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1275 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1276 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1277}
1278
1279static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1280 uint64_t *data)
1281{
1282 return mv88e6xxx_stats_get_stats(chip, port, data,
1283 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1284 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1285 0);
1286}
1287
1288static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1289 uint64_t *data)
1290{
1291 *data++ = chip->ports[port].atu_member_violation;
1292 *data++ = chip->ports[port].atu_miss_violation;
1293 *data++ = chip->ports[port].atu_full_violation;
1294 *data++ = chip->ports[port].vtu_member_violation;
1295 *data++ = chip->ports[port].vtu_miss_violation;
1296}
1297
1298static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1299 uint64_t *data)
1300{
1301 int count = 0;
1302
1303 if (chip->info->ops->stats_get_stats)
1304 count = chip->info->ops->stats_get_stats(chip, port, data);
1305
1306 mv88e6xxx_reg_lock(chip);
1307 if (chip->info->ops->serdes_get_stats) {
1308 data += count;
1309 count = chip->info->ops->serdes_get_stats(chip, port, data);
1310 }
1311 data += count;
1312 mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1313 mv88e6xxx_reg_unlock(chip);
1314}
1315
1316static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1317 uint64_t *data)
1318{
1319 struct mv88e6xxx_chip *chip = ds->priv;
1320 int ret;
1321
1322 mv88e6xxx_reg_lock(chip);
1323
1324 ret = mv88e6xxx_stats_snapshot(chip, port);
1325 mv88e6xxx_reg_unlock(chip);
1326
1327 if (ret < 0)
1328 return;
1329
1330 mv88e6xxx_get_stats(chip, port, data);
1331
1332}
1333
1334static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1335{
1336 struct mv88e6xxx_chip *chip = ds->priv;
1337 int len;
1338
1339 len = 32 * sizeof(u16);
1340 if (chip->info->ops->serdes_get_regs_len)
1341 len += chip->info->ops->serdes_get_regs_len(chip, port);
1342
1343 return len;
1344}
1345
1346static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1347 struct ethtool_regs *regs, void *_p)
1348{
1349 struct mv88e6xxx_chip *chip = ds->priv;
1350 int err;
1351 u16 reg;
1352 u16 *p = _p;
1353 int i;
1354
1355 regs->version = chip->info->prod_num;
1356
1357 memset(p, 0xff, 32 * sizeof(u16));
1358
1359 mv88e6xxx_reg_lock(chip);
1360
1361 for (i = 0; i < 32; i++) {
1362
1363 err = mv88e6xxx_port_read(chip, port, i, ®);
1364 if (!err)
1365 p[i] = reg;
1366 }
1367
1368 if (chip->info->ops->serdes_get_regs)
1369 chip->info->ops->serdes_get_regs(chip, port, &p[i]);
1370
1371 mv88e6xxx_reg_unlock(chip);
1372}
1373
1374static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1375 struct ethtool_eee *e)
1376{
1377 /* Nothing to do on the port's MAC */
1378 return 0;
1379}
1380
1381static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1382 struct ethtool_eee *e)
1383{
1384 /* Nothing to do on the port's MAC */
1385 return 0;
1386}
1387
1388/* Mask of the local ports allowed to receive frames from a given fabric port */
1389static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1390{
1391 struct dsa_switch *ds = chip->ds;
1392 struct dsa_switch_tree *dst = ds->dst;
1393 struct dsa_port *dp, *other_dp;
1394 bool found = false;
1395 u16 pvlan;
1396
1397 /* dev is a physical switch */
1398 if (dev <= dst->last_switch) {
1399 list_for_each_entry(dp, &dst->ports, list) {
1400 if (dp->ds->index == dev && dp->index == port) {
1401 /* dp might be a DSA link or a user port, so it
1402 * might or might not have a bridge.
1403 * Use the "found" variable for both cases.
1404 */
1405 found = true;
1406 break;
1407 }
1408 }
1409 /* dev is a virtual bridge */
1410 } else {
1411 list_for_each_entry(dp, &dst->ports, list) {
1412 unsigned int bridge_num = dsa_port_bridge_num_get(dp);
1413
1414 if (!bridge_num)
1415 continue;
1416
1417 if (bridge_num + dst->last_switch != dev)
1418 continue;
1419
1420 found = true;
1421 break;
1422 }
1423 }
1424
1425 /* Prevent frames from unknown switch or virtual bridge */
1426 if (!found)
1427 return 0;
1428
1429 /* Frames from DSA links and CPU ports can egress any local port */
1430 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA)
1431 return mv88e6xxx_port_mask(chip);
1432
1433 pvlan = 0;
1434
1435 /* Frames from standalone user ports can only egress on the
1436 * upstream port.
1437 */
1438 if (!dsa_port_bridge_dev_get(dp))
1439 return BIT(dsa_switch_upstream_port(ds));
1440
1441 /* Frames from bridged user ports can egress any local DSA
1442 * links and CPU ports, as well as any local member of their
1443 * bridge group.
1444 */
1445 dsa_switch_for_each_port(other_dp, ds)
1446 if (other_dp->type == DSA_PORT_TYPE_CPU ||
1447 other_dp->type == DSA_PORT_TYPE_DSA ||
1448 dsa_port_bridge_same(dp, other_dp))
1449 pvlan |= BIT(other_dp->index);
1450
1451 return pvlan;
1452}
1453
1454static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1455{
1456 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1457
1458 /* prevent frames from going back out of the port they came in on */
1459 output_ports &= ~BIT(port);
1460
1461 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1462}
1463
1464static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1465 u8 state)
1466{
1467 struct mv88e6xxx_chip *chip = ds->priv;
1468 int err;
1469
1470 mv88e6xxx_reg_lock(chip);
1471 err = mv88e6xxx_port_set_state(chip, port, state);
1472 mv88e6xxx_reg_unlock(chip);
1473
1474 if (err)
1475 dev_err(ds->dev, "p%d: failed to update state\n", port);
1476}
1477
1478static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1479{
1480 int err;
1481
1482 if (chip->info->ops->ieee_pri_map) {
1483 err = chip->info->ops->ieee_pri_map(chip);
1484 if (err)
1485 return err;
1486 }
1487
1488 if (chip->info->ops->ip_pri_map) {
1489 err = chip->info->ops->ip_pri_map(chip);
1490 if (err)
1491 return err;
1492 }
1493
1494 return 0;
1495}
1496
1497static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1498{
1499 struct dsa_switch *ds = chip->ds;
1500 int target, port;
1501 int err;
1502
1503 if (!chip->info->global2_addr)
1504 return 0;
1505
1506 /* Initialize the routing port to the 32 possible target devices */
1507 for (target = 0; target < 32; target++) {
1508 port = dsa_routing_port(ds, target);
1509 if (port == ds->num_ports)
1510 port = 0x1f;
1511
1512 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1513 if (err)
1514 return err;
1515 }
1516
1517 if (chip->info->ops->set_cascade_port) {
1518 port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1519 err = chip->info->ops->set_cascade_port(chip, port);
1520 if (err)
1521 return err;
1522 }
1523
1524 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1525 if (err)
1526 return err;
1527
1528 return 0;
1529}
1530
1531static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1532{
1533 /* Clear all trunk masks and mapping */
1534 if (chip->info->global2_addr)
1535 return mv88e6xxx_g2_trunk_clear(chip);
1536
1537 return 0;
1538}
1539
1540static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1541{
1542 if (chip->info->ops->rmu_disable)
1543 return chip->info->ops->rmu_disable(chip);
1544
1545 return 0;
1546}
1547
1548static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1549{
1550 if (chip->info->ops->pot_clear)
1551 return chip->info->ops->pot_clear(chip);
1552
1553 return 0;
1554}
1555
1556static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1557{
1558 if (chip->info->ops->mgmt_rsvd2cpu)
1559 return chip->info->ops->mgmt_rsvd2cpu(chip);
1560
1561 return 0;
1562}
1563
1564static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1565{
1566 int err;
1567
1568 err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1569 if (err)
1570 return err;
1571
1572 /* The chips that have a "learn2all" bit in Global1, ATU
1573 * Control are precisely those whose port registers have a
1574 * Message Port bit in Port Control 1 and hence implement
1575 * ->port_setup_message_port.
1576 */
1577 if (chip->info->ops->port_setup_message_port) {
1578 err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1579 if (err)
1580 return err;
1581 }
1582
1583 return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1584}
1585
1586static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1587{
1588 int port;
1589 int err;
1590
1591 if (!chip->info->ops->irl_init_all)
1592 return 0;
1593
1594 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1595 /* Disable ingress rate limiting by resetting all per port
1596 * ingress rate limit resources to their initial state.
1597 */
1598 err = chip->info->ops->irl_init_all(chip, port);
1599 if (err)
1600 return err;
1601 }
1602
1603 return 0;
1604}
1605
1606static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1607{
1608 if (chip->info->ops->set_switch_mac) {
1609 u8 addr[ETH_ALEN];
1610
1611 eth_random_addr(addr);
1612
1613 return chip->info->ops->set_switch_mac(chip, addr);
1614 }
1615
1616 return 0;
1617}
1618
1619static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1620{
1621 struct dsa_switch_tree *dst = chip->ds->dst;
1622 struct dsa_switch *ds;
1623 struct dsa_port *dp;
1624 u16 pvlan = 0;
1625
1626 if (!mv88e6xxx_has_pvt(chip))
1627 return 0;
1628
1629 /* Skip the local source device, which uses in-chip port VLAN */
1630 if (dev != chip->ds->index) {
1631 pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1632
1633 ds = dsa_switch_find(dst->index, dev);
1634 dp = ds ? dsa_to_port(ds, port) : NULL;
1635 if (dp && dp->lag) {
1636 /* As the PVT is used to limit flooding of
1637 * FORWARD frames, which use the LAG ID as the
1638 * source port, we must translate dev/port to
1639 * the special "LAG device" in the PVT, using
1640 * the LAG ID (one-based) as the port number
1641 * (zero-based).
1642 */
1643 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK;
1644 port = dsa_port_lag_id_get(dp) - 1;
1645 }
1646 }
1647
1648 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1649}
1650
1651static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1652{
1653 int dev, port;
1654 int err;
1655
1656 if (!mv88e6xxx_has_pvt(chip))
1657 return 0;
1658
1659 /* Clear 5 Bit Port for usage with Marvell Link Street devices:
1660 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1661 */
1662 err = mv88e6xxx_g2_misc_4_bit_port(chip);
1663 if (err)
1664 return err;
1665
1666 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1667 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1668 err = mv88e6xxx_pvt_map(chip, dev, port);
1669 if (err)
1670 return err;
1671 }
1672 }
1673
1674 return 0;
1675}
1676
1677static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port,
1678 u16 fid)
1679{
1680 if (dsa_to_port(chip->ds, port)->lag)
1681 /* Hardware is incapable of fast-aging a LAG through a
1682 * regular ATU move operation. Until we have something
1683 * more fancy in place this is a no-op.
1684 */
1685 return -EOPNOTSUPP;
1686
1687 return mv88e6xxx_g1_atu_remove(chip, fid, port, false);
1688}
1689
1690static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1691{
1692 struct mv88e6xxx_chip *chip = ds->priv;
1693 int err;
1694
1695 mv88e6xxx_reg_lock(chip);
1696 err = mv88e6xxx_port_fast_age_fid(chip, port, 0);
1697 mv88e6xxx_reg_unlock(chip);
1698
1699 if (err)
1700 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n",
1701 port, err);
1702}
1703
1704static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1705{
1706 if (!mv88e6xxx_max_vid(chip))
1707 return 0;
1708
1709 return mv88e6xxx_g1_vtu_flush(chip);
1710}
1711
1712static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1713 struct mv88e6xxx_vtu_entry *entry)
1714{
1715 int err;
1716
1717 if (!chip->info->ops->vtu_getnext)
1718 return -EOPNOTSUPP;
1719
1720 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip);
1721 entry->valid = false;
1722
1723 err = chip->info->ops->vtu_getnext(chip, entry);
1724
1725 if (entry->vid != vid)
1726 entry->valid = false;
1727
1728 return err;
1729}
1730
1731static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
1732 int (*cb)(struct mv88e6xxx_chip *chip,
1733 const struct mv88e6xxx_vtu_entry *entry,
1734 void *priv),
1735 void *priv)
1736{
1737 struct mv88e6xxx_vtu_entry entry = {
1738 .vid = mv88e6xxx_max_vid(chip),
1739 .valid = false,
1740 };
1741 int err;
1742
1743 if (!chip->info->ops->vtu_getnext)
1744 return -EOPNOTSUPP;
1745
1746 do {
1747 err = chip->info->ops->vtu_getnext(chip, &entry);
1748 if (err)
1749 return err;
1750
1751 if (!entry.valid)
1752 break;
1753
1754 err = cb(chip, &entry, priv);
1755 if (err)
1756 return err;
1757 } while (entry.vid < mv88e6xxx_max_vid(chip));
1758
1759 return 0;
1760}
1761
1762static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1763 struct mv88e6xxx_vtu_entry *entry)
1764{
1765 if (!chip->info->ops->vtu_loadpurge)
1766 return -EOPNOTSUPP;
1767
1768 return chip->info->ops->vtu_loadpurge(chip, entry);
1769}
1770
1771static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip,
1772 const struct mv88e6xxx_vtu_entry *entry,
1773 void *_fid_bitmap)
1774{
1775 unsigned long *fid_bitmap = _fid_bitmap;
1776
1777 set_bit(entry->fid, fid_bitmap);
1778 return 0;
1779}
1780
1781int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap)
1782{
1783 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1784
1785 /* Every FID has an associated VID, so walking the VTU
1786 * will discover the full set of FIDs in use.
1787 */
1788 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap);
1789}
1790
1791static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1792{
1793 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1794 int err;
1795
1796 err = mv88e6xxx_fid_map(chip, fid_bitmap);
1797 if (err)
1798 return err;
1799
1800 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID);
1801 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1802 return -ENOSPC;
1803
1804 /* Clear the database */
1805 return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1806}
1807
1808static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1809 struct mv88e6xxx_stu_entry *entry)
1810{
1811 if (!chip->info->ops->stu_loadpurge)
1812 return -EOPNOTSUPP;
1813
1814 return chip->info->ops->stu_loadpurge(chip, entry);
1815}
1816
1817static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip)
1818{
1819 struct mv88e6xxx_stu_entry stu = {
1820 .valid = true,
1821 .sid = 0
1822 };
1823
1824 if (!mv88e6xxx_has_stu(chip))
1825 return 0;
1826
1827 /* Make sure that SID 0 is always valid. This is used by VTU
1828 * entries that do not make use of the STU, e.g. when creating
1829 * a VLAN upper on a port that is also part of a VLAN
1830 * filtering bridge.
1831 */
1832 return mv88e6xxx_stu_loadpurge(chip, &stu);
1833}
1834
1835static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid)
1836{
1837 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 };
1838 struct mv88e6xxx_mst *mst;
1839
1840 __set_bit(0, busy);
1841
1842 list_for_each_entry(mst, &chip->msts, node)
1843 __set_bit(mst->stu.sid, busy);
1844
1845 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID);
1846
1847 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0;
1848}
1849
1850static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid)
1851{
1852 struct mv88e6xxx_mst *mst, *tmp;
1853 int err;
1854
1855 if (!sid)
1856 return 0;
1857
1858 list_for_each_entry_safe(mst, tmp, &chip->msts, node) {
1859 if (mst->stu.sid != sid)
1860 continue;
1861
1862 if (!refcount_dec_and_test(&mst->refcnt))
1863 return 0;
1864
1865 mst->stu.valid = false;
1866 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1867 if (err) {
1868 refcount_set(&mst->refcnt, 1);
1869 return err;
1870 }
1871
1872 list_del(&mst->node);
1873 kfree(mst);
1874 return 0;
1875 }
1876
1877 return -ENOENT;
1878}
1879
1880static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br,
1881 u16 msti, u8 *sid)
1882{
1883 struct mv88e6xxx_mst *mst;
1884 int err, i;
1885
1886 if (!mv88e6xxx_has_stu(chip)) {
1887 err = -EOPNOTSUPP;
1888 goto err;
1889 }
1890
1891 if (!msti) {
1892 *sid = 0;
1893 return 0;
1894 }
1895
1896 list_for_each_entry(mst, &chip->msts, node) {
1897 if (mst->br == br && mst->msti == msti) {
1898 refcount_inc(&mst->refcnt);
1899 *sid = mst->stu.sid;
1900 return 0;
1901 }
1902 }
1903
1904 err = mv88e6xxx_sid_get(chip, sid);
1905 if (err)
1906 goto err;
1907
1908 mst = kzalloc(sizeof(*mst), GFP_KERNEL);
1909 if (!mst) {
1910 err = -ENOMEM;
1911 goto err;
1912 }
1913
1914 INIT_LIST_HEAD(&mst->node);
1915 refcount_set(&mst->refcnt, 1);
1916 mst->br = br;
1917 mst->msti = msti;
1918 mst->stu.valid = true;
1919 mst->stu.sid = *sid;
1920
1921 /* The bridge starts out all ports in the disabled state. But
1922 * a STU state of disabled means to go by the port-global
1923 * state. So we set all user port's initial state to blocking,
1924 * to match the bridge's behavior.
1925 */
1926 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
1927 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ?
1928 MV88E6XXX_PORT_CTL0_STATE_BLOCKING :
1929 MV88E6XXX_PORT_CTL0_STATE_DISABLED;
1930
1931 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1932 if (err)
1933 goto err_free;
1934
1935 list_add_tail(&mst->node, &chip->msts);
1936 return 0;
1937
1938err_free:
1939 kfree(mst);
1940err:
1941 return err;
1942}
1943
1944static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port,
1945 const struct switchdev_mst_state *st)
1946{
1947 struct dsa_port *dp = dsa_to_port(ds, port);
1948 struct mv88e6xxx_chip *chip = ds->priv;
1949 struct mv88e6xxx_mst *mst;
1950 u8 state;
1951 int err;
1952
1953 if (!mv88e6xxx_has_stu(chip))
1954 return -EOPNOTSUPP;
1955
1956 switch (st->state) {
1957 case BR_STATE_DISABLED:
1958 case BR_STATE_BLOCKING:
1959 case BR_STATE_LISTENING:
1960 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING;
1961 break;
1962 case BR_STATE_LEARNING:
1963 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING;
1964 break;
1965 case BR_STATE_FORWARDING:
1966 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
1967 break;
1968 default:
1969 return -EINVAL;
1970 }
1971
1972 list_for_each_entry(mst, &chip->msts, node) {
1973 if (mst->br == dsa_port_bridge_dev_get(dp) &&
1974 mst->msti == st->msti) {
1975 if (mst->stu.state[port] == state)
1976 return 0;
1977
1978 mst->stu.state[port] = state;
1979 mv88e6xxx_reg_lock(chip);
1980 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu);
1981 mv88e6xxx_reg_unlock(chip);
1982 return err;
1983 }
1984 }
1985
1986 return -ENOENT;
1987}
1988
1989static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1990 u16 vid)
1991{
1992 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp;
1993 struct mv88e6xxx_chip *chip = ds->priv;
1994 struct mv88e6xxx_vtu_entry vlan;
1995 int err;
1996
1997 /* DSA and CPU ports have to be members of multiple vlans */
1998 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp))
1999 return 0;
2000
2001 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2002 if (err)
2003 return err;
2004
2005 if (!vlan.valid)
2006 return 0;
2007
2008 dsa_switch_for_each_user_port(other_dp, ds) {
2009 struct net_device *other_br;
2010
2011 if (vlan.member[other_dp->index] ==
2012 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2013 continue;
2014
2015 if (dsa_port_bridge_same(dp, other_dp))
2016 break; /* same bridge, check next VLAN */
2017
2018 other_br = dsa_port_bridge_dev_get(other_dp);
2019 if (!other_br)
2020 continue;
2021
2022 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
2023 port, vlan.vid, other_dp->index, netdev_name(other_br));
2024 return -EOPNOTSUPP;
2025 }
2026
2027 return 0;
2028}
2029
2030static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port)
2031{
2032 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2033 struct net_device *br = dsa_port_bridge_dev_get(dp);
2034 struct mv88e6xxx_port *p = &chip->ports[port];
2035 u16 pvid = MV88E6XXX_VID_STANDALONE;
2036 bool drop_untagged = false;
2037 int err;
2038
2039 if (br) {
2040 if (br_vlan_enabled(br)) {
2041 pvid = p->bridge_pvid.vid;
2042 drop_untagged = !p->bridge_pvid.valid;
2043 } else {
2044 pvid = MV88E6XXX_VID_BRIDGED;
2045 }
2046 }
2047
2048 err = mv88e6xxx_port_set_pvid(chip, port, pvid);
2049 if (err)
2050 return err;
2051
2052 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged);
2053}
2054
2055static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2056 bool vlan_filtering,
2057 struct netlink_ext_ack *extack)
2058{
2059 struct mv88e6xxx_chip *chip = ds->priv;
2060 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
2061 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
2062 int err;
2063
2064 if (!mv88e6xxx_max_vid(chip))
2065 return -EOPNOTSUPP;
2066
2067 mv88e6xxx_reg_lock(chip);
2068
2069 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
2070 if (err)
2071 goto unlock;
2072
2073 err = mv88e6xxx_port_commit_pvid(chip, port);
2074 if (err)
2075 goto unlock;
2076
2077unlock:
2078 mv88e6xxx_reg_unlock(chip);
2079
2080 return err;
2081}
2082
2083static int
2084mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2085 const struct switchdev_obj_port_vlan *vlan)
2086{
2087 struct mv88e6xxx_chip *chip = ds->priv;
2088 int err;
2089
2090 if (!mv88e6xxx_max_vid(chip))
2091 return -EOPNOTSUPP;
2092
2093 /* If the requested port doesn't belong to the same bridge as the VLAN
2094 * members, do not support it (yet) and fallback to software VLAN.
2095 */
2096 mv88e6xxx_reg_lock(chip);
2097 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid);
2098 mv88e6xxx_reg_unlock(chip);
2099
2100 return err;
2101}
2102
2103static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2104 const unsigned char *addr, u16 vid,
2105 u8 state)
2106{
2107 struct mv88e6xxx_atu_entry entry;
2108 struct mv88e6xxx_vtu_entry vlan;
2109 u16 fid;
2110 int err;
2111
2112 /* Ports have two private address databases: one for when the port is
2113 * standalone and one for when the port is under a bridge and the
2114 * 802.1Q mode is disabled. When the port is standalone, DSA wants its
2115 * address database to remain 100% empty, so we never load an ATU entry
2116 * into a standalone port's database. Therefore, translate the null
2117 * VLAN ID into the port's database used for VLAN-unaware bridging.
2118 */
2119 if (vid == 0) {
2120 fid = MV88E6XXX_FID_BRIDGED;
2121 } else {
2122 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2123 if (err)
2124 return err;
2125
2126 /* switchdev expects -EOPNOTSUPP to honor software VLANs */
2127 if (!vlan.valid)
2128 return -EOPNOTSUPP;
2129
2130 fid = vlan.fid;
2131 }
2132
2133 entry.state = 0;
2134 ether_addr_copy(entry.mac, addr);
2135 eth_addr_dec(entry.mac);
2136
2137 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry);
2138 if (err)
2139 return err;
2140
2141 /* Initialize a fresh ATU entry if it isn't found */
2142 if (!entry.state || !ether_addr_equal(entry.mac, addr)) {
2143 memset(&entry, 0, sizeof(entry));
2144 ether_addr_copy(entry.mac, addr);
2145 }
2146
2147 /* Purge the ATU entry only if no port is using it anymore */
2148 if (!state) {
2149 entry.portvec &= ~BIT(port);
2150 if (!entry.portvec)
2151 entry.state = 0;
2152 } else {
2153 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)
2154 entry.portvec = BIT(port);
2155 else
2156 entry.portvec |= BIT(port);
2157
2158 entry.state = state;
2159 }
2160
2161 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry);
2162}
2163
2164static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port,
2165 const struct mv88e6xxx_policy *policy)
2166{
2167 enum mv88e6xxx_policy_mapping mapping = policy->mapping;
2168 enum mv88e6xxx_policy_action action = policy->action;
2169 const u8 *addr = policy->addr;
2170 u16 vid = policy->vid;
2171 u8 state;
2172 int err;
2173 int id;
2174
2175 if (!chip->info->ops->port_set_policy)
2176 return -EOPNOTSUPP;
2177
2178 switch (mapping) {
2179 case MV88E6XXX_POLICY_MAPPING_DA:
2180 case MV88E6XXX_POLICY_MAPPING_SA:
2181 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2182 state = 0; /* Dissociate the port and address */
2183 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2184 is_multicast_ether_addr(addr))
2185 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY;
2186 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD &&
2187 is_unicast_ether_addr(addr))
2188 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY;
2189 else
2190 return -EOPNOTSUPP;
2191
2192 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2193 state);
2194 if (err)
2195 return err;
2196 break;
2197 default:
2198 return -EOPNOTSUPP;
2199 }
2200
2201 /* Skip the port's policy clearing if the mapping is still in use */
2202 if (action == MV88E6XXX_POLICY_ACTION_NORMAL)
2203 idr_for_each_entry(&chip->policies, policy, id)
2204 if (policy->port == port &&
2205 policy->mapping == mapping &&
2206 policy->action != action)
2207 return 0;
2208
2209 return chip->info->ops->port_set_policy(chip, port, mapping, action);
2210}
2211
2212static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port,
2213 struct ethtool_rx_flow_spec *fs)
2214{
2215 struct ethhdr *mac_entry = &fs->h_u.ether_spec;
2216 struct ethhdr *mac_mask = &fs->m_u.ether_spec;
2217 enum mv88e6xxx_policy_mapping mapping;
2218 enum mv88e6xxx_policy_action action;
2219 struct mv88e6xxx_policy *policy;
2220 u16 vid = 0;
2221 u8 *addr;
2222 int err;
2223 int id;
2224
2225 if (fs->location != RX_CLS_LOC_ANY)
2226 return -EINVAL;
2227
2228 if (fs->ring_cookie == RX_CLS_FLOW_DISC)
2229 action = MV88E6XXX_POLICY_ACTION_DISCARD;
2230 else
2231 return -EOPNOTSUPP;
2232
2233 switch (fs->flow_type & ~FLOW_EXT) {
2234 case ETHER_FLOW:
2235 if (!is_zero_ether_addr(mac_mask->h_dest) &&
2236 is_zero_ether_addr(mac_mask->h_source)) {
2237 mapping = MV88E6XXX_POLICY_MAPPING_DA;
2238 addr = mac_entry->h_dest;
2239 } else if (is_zero_ether_addr(mac_mask->h_dest) &&
2240 !is_zero_ether_addr(mac_mask->h_source)) {
2241 mapping = MV88E6XXX_POLICY_MAPPING_SA;
2242 addr = mac_entry->h_source;
2243 } else {
2244 /* Cannot support DA and SA mapping in the same rule */
2245 return -EOPNOTSUPP;
2246 }
2247 break;
2248 default:
2249 return -EOPNOTSUPP;
2250 }
2251
2252 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) {
2253 if (fs->m_ext.vlan_tci != htons(0xffff))
2254 return -EOPNOTSUPP;
2255 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK;
2256 }
2257
2258 idr_for_each_entry(&chip->policies, policy, id) {
2259 if (policy->port == port && policy->mapping == mapping &&
2260 policy->action == action && policy->vid == vid &&
2261 ether_addr_equal(policy->addr, addr))
2262 return -EEXIST;
2263 }
2264
2265 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL);
2266 if (!policy)
2267 return -ENOMEM;
2268
2269 fs->location = 0;
2270 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff,
2271 GFP_KERNEL);
2272 if (err) {
2273 devm_kfree(chip->dev, policy);
2274 return err;
2275 }
2276
2277 memcpy(&policy->fs, fs, sizeof(*fs));
2278 ether_addr_copy(policy->addr, addr);
2279 policy->mapping = mapping;
2280 policy->action = action;
2281 policy->port = port;
2282 policy->vid = vid;
2283
2284 err = mv88e6xxx_policy_apply(chip, port, policy);
2285 if (err) {
2286 idr_remove(&chip->policies, fs->location);
2287 devm_kfree(chip->dev, policy);
2288 return err;
2289 }
2290
2291 return 0;
2292}
2293
2294static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port,
2295 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
2296{
2297 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2298 struct mv88e6xxx_chip *chip = ds->priv;
2299 struct mv88e6xxx_policy *policy;
2300 int err;
2301 int id;
2302
2303 mv88e6xxx_reg_lock(chip);
2304
2305 switch (rxnfc->cmd) {
2306 case ETHTOOL_GRXCLSRLCNT:
2307 rxnfc->data = 0;
2308 rxnfc->data |= RX_CLS_LOC_SPECIAL;
2309 rxnfc->rule_cnt = 0;
2310 idr_for_each_entry(&chip->policies, policy, id)
2311 if (policy->port == port)
2312 rxnfc->rule_cnt++;
2313 err = 0;
2314 break;
2315 case ETHTOOL_GRXCLSRULE:
2316 err = -ENOENT;
2317 policy = idr_find(&chip->policies, fs->location);
2318 if (policy) {
2319 memcpy(fs, &policy->fs, sizeof(*fs));
2320 err = 0;
2321 }
2322 break;
2323 case ETHTOOL_GRXCLSRLALL:
2324 rxnfc->data = 0;
2325 rxnfc->rule_cnt = 0;
2326 idr_for_each_entry(&chip->policies, policy, id)
2327 if (policy->port == port)
2328 rule_locs[rxnfc->rule_cnt++] = id;
2329 err = 0;
2330 break;
2331 default:
2332 err = -EOPNOTSUPP;
2333 break;
2334 }
2335
2336 mv88e6xxx_reg_unlock(chip);
2337
2338 return err;
2339}
2340
2341static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port,
2342 struct ethtool_rxnfc *rxnfc)
2343{
2344 struct ethtool_rx_flow_spec *fs = &rxnfc->fs;
2345 struct mv88e6xxx_chip *chip = ds->priv;
2346 struct mv88e6xxx_policy *policy;
2347 int err;
2348
2349 mv88e6xxx_reg_lock(chip);
2350
2351 switch (rxnfc->cmd) {
2352 case ETHTOOL_SRXCLSRLINS:
2353 err = mv88e6xxx_policy_insert(chip, port, fs);
2354 break;
2355 case ETHTOOL_SRXCLSRLDEL:
2356 err = -ENOENT;
2357 policy = idr_remove(&chip->policies, fs->location);
2358 if (policy) {
2359 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL;
2360 err = mv88e6xxx_policy_apply(chip, port, policy);
2361 devm_kfree(chip->dev, policy);
2362 }
2363 break;
2364 default:
2365 err = -EOPNOTSUPP;
2366 break;
2367 }
2368
2369 mv88e6xxx_reg_unlock(chip);
2370
2371 return err;
2372}
2373
2374static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
2375 u16 vid)
2376{
2377 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2378 u8 broadcast[ETH_ALEN];
2379
2380 eth_broadcast_addr(broadcast);
2381
2382 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
2383}
2384
2385static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
2386{
2387 int port;
2388 int err;
2389
2390 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2391 struct dsa_port *dp = dsa_to_port(chip->ds, port);
2392 struct net_device *brport;
2393
2394 if (dsa_is_unused_port(chip->ds, port))
2395 continue;
2396
2397 brport = dsa_port_to_bridge_port(dp);
2398 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD))
2399 /* Skip bridged user ports where broadcast
2400 * flooding is disabled.
2401 */
2402 continue;
2403
2404 err = mv88e6xxx_port_add_broadcast(chip, port, vid);
2405 if (err)
2406 return err;
2407 }
2408
2409 return 0;
2410}
2411
2412struct mv88e6xxx_port_broadcast_sync_ctx {
2413 int port;
2414 bool flood;
2415};
2416
2417static int
2418mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip,
2419 const struct mv88e6xxx_vtu_entry *vlan,
2420 void *_ctx)
2421{
2422 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx;
2423 u8 broadcast[ETH_ALEN];
2424 u8 state;
2425
2426 if (ctx->flood)
2427 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
2428 else
2429 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED;
2430
2431 eth_broadcast_addr(broadcast);
2432
2433 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast,
2434 vlan->vid, state);
2435}
2436
2437static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port,
2438 bool flood)
2439{
2440 struct mv88e6xxx_port_broadcast_sync_ctx ctx = {
2441 .port = port,
2442 .flood = flood,
2443 };
2444 struct mv88e6xxx_vtu_entry vid0 = {
2445 .vid = 0,
2446 };
2447 int err;
2448
2449 /* Update the port's private database... */
2450 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx);
2451 if (err)
2452 return err;
2453
2454 /* ...and the database for all VLANs. */
2455 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan,
2456 &ctx);
2457}
2458
2459static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port,
2460 u16 vid, u8 member, bool warn)
2461{
2462 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2463 struct mv88e6xxx_vtu_entry vlan;
2464 int i, err;
2465
2466 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2467 if (err)
2468 return err;
2469
2470 if (!vlan.valid) {
2471 memset(&vlan, 0, sizeof(vlan));
2472
2473 if (vid == MV88E6XXX_VID_STANDALONE)
2474 vlan.policy = true;
2475
2476 err = mv88e6xxx_atu_new(chip, &vlan.fid);
2477 if (err)
2478 return err;
2479
2480 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
2481 if (i == port)
2482 vlan.member[i] = member;
2483 else
2484 vlan.member[i] = non_member;
2485
2486 vlan.vid = vid;
2487 vlan.valid = true;
2488
2489 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2490 if (err)
2491 return err;
2492
2493 err = mv88e6xxx_broadcast_setup(chip, vlan.vid);
2494 if (err)
2495 return err;
2496 } else if (vlan.member[port] != member) {
2497 vlan.member[port] = member;
2498
2499 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2500 if (err)
2501 return err;
2502 } else if (warn) {
2503 dev_info(chip->dev, "p%d: already a member of VLAN %d\n",
2504 port, vid);
2505 }
2506
2507 return 0;
2508}
2509
2510static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2511 const struct switchdev_obj_port_vlan *vlan,
2512 struct netlink_ext_ack *extack)
2513{
2514 struct mv88e6xxx_chip *chip = ds->priv;
2515 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2516 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2517 struct mv88e6xxx_port *p = &chip->ports[port];
2518 bool warn;
2519 u8 member;
2520 int err;
2521
2522 if (!vlan->vid)
2523 return 0;
2524
2525 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan);
2526 if (err)
2527 return err;
2528
2529 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
2530 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
2531 else if (untagged)
2532 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
2533 else
2534 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
2535
2536 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port
2537 * and then the CPU port. Do not warn for duplicates for the CPU port.
2538 */
2539 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port);
2540
2541 mv88e6xxx_reg_lock(chip);
2542
2543 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn);
2544 if (err) {
2545 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
2546 vlan->vid, untagged ? 'u' : 't');
2547 goto out;
2548 }
2549
2550 if (pvid) {
2551 p->bridge_pvid.vid = vlan->vid;
2552 p->bridge_pvid.valid = true;
2553
2554 err = mv88e6xxx_port_commit_pvid(chip, port);
2555 if (err)
2556 goto out;
2557 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) {
2558 /* The old pvid was reinstalled as a non-pvid VLAN */
2559 p->bridge_pvid.valid = false;
2560
2561 err = mv88e6xxx_port_commit_pvid(chip, port);
2562 if (err)
2563 goto out;
2564 }
2565
2566out:
2567 mv88e6xxx_reg_unlock(chip);
2568
2569 return err;
2570}
2571
2572static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip,
2573 int port, u16 vid)
2574{
2575 struct mv88e6xxx_vtu_entry vlan;
2576 int i, err;
2577
2578 if (!vid)
2579 return 0;
2580
2581 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2582 if (err)
2583 return err;
2584
2585 /* If the VLAN doesn't exist in hardware or the port isn't a member,
2586 * tell switchdev that this VLAN is likely handled in software.
2587 */
2588 if (!vlan.valid ||
2589 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2590 return -EOPNOTSUPP;
2591
2592 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2593
2594 /* keep the VLAN unless all ports are excluded */
2595 vlan.valid = false;
2596 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
2597 if (vlan.member[i] !=
2598 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2599 vlan.valid = true;
2600 break;
2601 }
2602 }
2603
2604 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2605 if (err)
2606 return err;
2607
2608 if (!vlan.valid) {
2609 err = mv88e6xxx_mst_put(chip, vlan.sid);
2610 if (err)
2611 return err;
2612 }
2613
2614 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
2615}
2616
2617static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2618 const struct switchdev_obj_port_vlan *vlan)
2619{
2620 struct mv88e6xxx_chip *chip = ds->priv;
2621 struct mv88e6xxx_port *p = &chip->ports[port];
2622 int err = 0;
2623 u16 pvid;
2624
2625 if (!mv88e6xxx_max_vid(chip))
2626 return -EOPNOTSUPP;
2627
2628 /* The ATU removal procedure needs the FID to be mapped in the VTU,
2629 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA
2630 * switchdev workqueue to ensure that all FDB entries are deleted
2631 * before we remove the VLAN.
2632 */
2633 dsa_flush_workqueue();
2634
2635 mv88e6xxx_reg_lock(chip);
2636
2637 err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
2638 if (err)
2639 goto unlock;
2640
2641 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid);
2642 if (err)
2643 goto unlock;
2644
2645 if (vlan->vid == pvid) {
2646 p->bridge_pvid.valid = false;
2647
2648 err = mv88e6xxx_port_commit_pvid(chip, port);
2649 if (err)
2650 goto unlock;
2651 }
2652
2653unlock:
2654 mv88e6xxx_reg_unlock(chip);
2655
2656 return err;
2657}
2658
2659static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid)
2660{
2661 struct mv88e6xxx_chip *chip = ds->priv;
2662 struct mv88e6xxx_vtu_entry vlan;
2663 int err;
2664
2665 mv88e6xxx_reg_lock(chip);
2666
2667 err = mv88e6xxx_vtu_get(chip, vid, &vlan);
2668 if (err)
2669 goto unlock;
2670
2671 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid);
2672
2673unlock:
2674 mv88e6xxx_reg_unlock(chip);
2675
2676 return err;
2677}
2678
2679static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds,
2680 struct dsa_bridge bridge,
2681 const struct switchdev_vlan_msti *msti)
2682{
2683 struct mv88e6xxx_chip *chip = ds->priv;
2684 struct mv88e6xxx_vtu_entry vlan;
2685 u8 old_sid, new_sid;
2686 int err;
2687
2688 if (!mv88e6xxx_has_stu(chip))
2689 return -EOPNOTSUPP;
2690
2691 mv88e6xxx_reg_lock(chip);
2692
2693 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan);
2694 if (err)
2695 goto unlock;
2696
2697 if (!vlan.valid) {
2698 err = -EINVAL;
2699 goto unlock;
2700 }
2701
2702 old_sid = vlan.sid;
2703
2704 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid);
2705 if (err)
2706 goto unlock;
2707
2708 if (new_sid != old_sid) {
2709 vlan.sid = new_sid;
2710
2711 err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
2712 if (err) {
2713 mv88e6xxx_mst_put(chip, new_sid);
2714 goto unlock;
2715 }
2716 }
2717
2718 err = mv88e6xxx_mst_put(chip, old_sid);
2719
2720unlock:
2721 mv88e6xxx_reg_unlock(chip);
2722 return err;
2723}
2724
2725static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2726 const unsigned char *addr, u16 vid,
2727 struct dsa_db db)
2728{
2729 struct mv88e6xxx_chip *chip = ds->priv;
2730 int err;
2731
2732 mv88e6xxx_reg_lock(chip);
2733 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
2734 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2735 mv88e6xxx_reg_unlock(chip);
2736
2737 return err;
2738}
2739
2740static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2741 const unsigned char *addr, u16 vid,
2742 struct dsa_db db)
2743{
2744 struct mv88e6xxx_chip *chip = ds->priv;
2745 int err;
2746
2747 mv88e6xxx_reg_lock(chip);
2748 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0);
2749 mv88e6xxx_reg_unlock(chip);
2750
2751 return err;
2752}
2753
2754static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2755 u16 fid, u16 vid, int port,
2756 dsa_fdb_dump_cb_t *cb, void *data)
2757{
2758 struct mv88e6xxx_atu_entry addr;
2759 bool is_static;
2760 int err;
2761
2762 addr.state = 0;
2763 eth_broadcast_addr(addr.mac);
2764
2765 do {
2766 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
2767 if (err)
2768 return err;
2769
2770 if (!addr.state)
2771 break;
2772
2773 if (addr.trunk || (addr.portvec & BIT(port)) == 0)
2774 continue;
2775
2776 if (!is_unicast_ether_addr(addr.mac))
2777 continue;
2778
2779 is_static = (addr.state ==
2780 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
2781 err = cb(addr.mac, vid, is_static, data);
2782 if (err)
2783 return err;
2784 } while (!is_broadcast_ether_addr(addr.mac));
2785
2786 return err;
2787}
2788
2789struct mv88e6xxx_port_db_dump_vlan_ctx {
2790 int port;
2791 dsa_fdb_dump_cb_t *cb;
2792 void *data;
2793};
2794
2795static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip,
2796 const struct mv88e6xxx_vtu_entry *entry,
2797 void *_data)
2798{
2799 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data;
2800
2801 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid,
2802 ctx->port, ctx->cb, ctx->data);
2803}
2804
2805static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2806 dsa_fdb_dump_cb_t *cb, void *data)
2807{
2808 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = {
2809 .port = port,
2810 .cb = cb,
2811 .data = data,
2812 };
2813 u16 fid;
2814 int err;
2815
2816 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2817 err = mv88e6xxx_port_get_fid(chip, port, &fid);
2818 if (err)
2819 return err;
2820
2821 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
2822 if (err)
2823 return err;
2824
2825 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx);
2826}
2827
2828static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2829 dsa_fdb_dump_cb_t *cb, void *data)
2830{
2831 struct mv88e6xxx_chip *chip = ds->priv;
2832 int err;
2833
2834 mv88e6xxx_reg_lock(chip);
2835 err = mv88e6xxx_port_db_dump(chip, port, cb, data);
2836 mv88e6xxx_reg_unlock(chip);
2837
2838 return err;
2839}
2840
2841static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
2842 struct dsa_bridge bridge)
2843{
2844 struct dsa_switch *ds = chip->ds;
2845 struct dsa_switch_tree *dst = ds->dst;
2846 struct dsa_port *dp;
2847 int err;
2848
2849 list_for_each_entry(dp, &dst->ports, list) {
2850 if (dsa_port_offloads_bridge(dp, &bridge)) {
2851 if (dp->ds == ds) {
2852 /* This is a local bridge group member,
2853 * remap its Port VLAN Map.
2854 */
2855 err = mv88e6xxx_port_vlan_map(chip, dp->index);
2856 if (err)
2857 return err;
2858 } else {
2859 /* This is an external bridge group member,
2860 * remap its cross-chip Port VLAN Table entry.
2861 */
2862 err = mv88e6xxx_pvt_map(chip, dp->ds->index,
2863 dp->index);
2864 if (err)
2865 return err;
2866 }
2867 }
2868 }
2869
2870 return 0;
2871}
2872
2873/* Treat the software bridge as a virtual single-port switch behind the
2874 * CPU and map in the PVT. First dst->last_switch elements are taken by
2875 * physical switches, so start from beyond that range.
2876 */
2877static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds,
2878 unsigned int bridge_num)
2879{
2880 u8 dev = bridge_num + ds->dst->last_switch;
2881 struct mv88e6xxx_chip *chip = ds->priv;
2882
2883 return mv88e6xxx_pvt_map(chip, dev, 0);
2884}
2885
2886static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2887 struct dsa_bridge bridge,
2888 bool *tx_fwd_offload,
2889 struct netlink_ext_ack *extack)
2890{
2891 struct mv88e6xxx_chip *chip = ds->priv;
2892 int err;
2893
2894 mv88e6xxx_reg_lock(chip);
2895
2896 err = mv88e6xxx_bridge_map(chip, bridge);
2897 if (err)
2898 goto unlock;
2899
2900 err = mv88e6xxx_port_set_map_da(chip, port, true);
2901 if (err)
2902 goto unlock;
2903
2904 err = mv88e6xxx_port_commit_pvid(chip, port);
2905 if (err)
2906 goto unlock;
2907
2908 if (mv88e6xxx_has_pvt(chip)) {
2909 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2910 if (err)
2911 goto unlock;
2912
2913 *tx_fwd_offload = true;
2914 }
2915
2916unlock:
2917 mv88e6xxx_reg_unlock(chip);
2918
2919 return err;
2920}
2921
2922static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
2923 struct dsa_bridge bridge)
2924{
2925 struct mv88e6xxx_chip *chip = ds->priv;
2926 int err;
2927
2928 mv88e6xxx_reg_lock(chip);
2929
2930 if (bridge.tx_fwd_offload &&
2931 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2932 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2933
2934 if (mv88e6xxx_bridge_map(chip, bridge) ||
2935 mv88e6xxx_port_vlan_map(chip, port))
2936 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
2937
2938 err = mv88e6xxx_port_set_map_da(chip, port, false);
2939 if (err)
2940 dev_err(ds->dev,
2941 "port %d failed to restore map-DA: %pe\n",
2942 port, ERR_PTR(err));
2943
2944 err = mv88e6xxx_port_commit_pvid(chip, port);
2945 if (err)
2946 dev_err(ds->dev,
2947 "port %d failed to restore standalone pvid: %pe\n",
2948 port, ERR_PTR(err));
2949
2950 mv88e6xxx_reg_unlock(chip);
2951}
2952
2953static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds,
2954 int tree_index, int sw_index,
2955 int port, struct dsa_bridge bridge,
2956 struct netlink_ext_ack *extack)
2957{
2958 struct mv88e6xxx_chip *chip = ds->priv;
2959 int err;
2960
2961 if (tree_index != ds->dst->index)
2962 return 0;
2963
2964 mv88e6xxx_reg_lock(chip);
2965 err = mv88e6xxx_pvt_map(chip, sw_index, port);
2966 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num);
2967 mv88e6xxx_reg_unlock(chip);
2968
2969 return err;
2970}
2971
2972static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds,
2973 int tree_index, int sw_index,
2974 int port, struct dsa_bridge bridge)
2975{
2976 struct mv88e6xxx_chip *chip = ds->priv;
2977
2978 if (tree_index != ds->dst->index)
2979 return;
2980
2981 mv88e6xxx_reg_lock(chip);
2982 if (mv88e6xxx_pvt_map(chip, sw_index, port) ||
2983 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num))
2984 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2985 mv88e6xxx_reg_unlock(chip);
2986}
2987
2988static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2989{
2990 if (chip->info->ops->reset)
2991 return chip->info->ops->reset(chip);
2992
2993 return 0;
2994}
2995
2996static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2997{
2998 struct gpio_desc *gpiod = chip->reset;
2999
3000 /* If there is a GPIO connected to the reset pin, toggle it */
3001 if (gpiod) {
3002 gpiod_set_value_cansleep(gpiod, 1);
3003 usleep_range(10000, 20000);
3004 gpiod_set_value_cansleep(gpiod, 0);
3005 usleep_range(10000, 20000);
3006
3007 mv88e6xxx_g1_wait_eeprom_done(chip);
3008 }
3009}
3010
3011static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
3012{
3013 int i, err;
3014
3015 /* Set all ports to the Disabled state */
3016 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3017 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
3018 if (err)
3019 return err;
3020 }
3021
3022 /* Wait for transmit queues to drain,
3023 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
3024 */
3025 usleep_range(2000, 4000);
3026
3027 return 0;
3028}
3029
3030static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
3031{
3032 int err;
3033
3034 err = mv88e6xxx_disable_ports(chip);
3035 if (err)
3036 return err;
3037
3038 mv88e6xxx_hardware_reset(chip);
3039
3040 return mv88e6xxx_software_reset(chip);
3041}
3042
3043static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
3044 enum mv88e6xxx_frame_mode frame,
3045 enum mv88e6xxx_egress_mode egress, u16 etype)
3046{
3047 int err;
3048
3049 if (!chip->info->ops->port_set_frame_mode)
3050 return -EOPNOTSUPP;
3051
3052 err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
3053 if (err)
3054 return err;
3055
3056 err = chip->info->ops->port_set_frame_mode(chip, port, frame);
3057 if (err)
3058 return err;
3059
3060 if (chip->info->ops->port_set_ether_type)
3061 return chip->info->ops->port_set_ether_type(chip, port, etype);
3062
3063 return 0;
3064}
3065
3066static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
3067{
3068 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
3069 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3070 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3071}
3072
3073static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
3074{
3075 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
3076 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
3077 MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
3078}
3079
3080static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
3081{
3082 return mv88e6xxx_set_port_mode(chip, port,
3083 MV88E6XXX_FRAME_MODE_ETHERTYPE,
3084 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
3085 ETH_P_EDSA);
3086}
3087
3088static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
3089{
3090 if (dsa_is_dsa_port(chip->ds, port))
3091 return mv88e6xxx_set_port_mode_dsa(chip, port);
3092
3093 if (dsa_is_user_port(chip->ds, port))
3094 return mv88e6xxx_set_port_mode_normal(chip, port);
3095
3096 /* Setup CPU port mode depending on its supported tag format */
3097 if (chip->tag_protocol == DSA_TAG_PROTO_DSA)
3098 return mv88e6xxx_set_port_mode_dsa(chip, port);
3099
3100 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA)
3101 return mv88e6xxx_set_port_mode_edsa(chip, port);
3102
3103 return -EINVAL;
3104}
3105
3106static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
3107{
3108 bool message = dsa_is_dsa_port(chip->ds, port);
3109
3110 return mv88e6xxx_port_set_message_port(chip, port, message);
3111}
3112
3113static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
3114{
3115 int err;
3116
3117 if (chip->info->ops->port_set_ucast_flood) {
3118 err = chip->info->ops->port_set_ucast_flood(chip, port, true);
3119 if (err)
3120 return err;
3121 }
3122 if (chip->info->ops->port_set_mcast_flood) {
3123 err = chip->info->ops->port_set_mcast_flood(chip, port, true);
3124 if (err)
3125 return err;
3126 }
3127
3128 return 0;
3129}
3130
3131static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id)
3132{
3133 struct mv88e6xxx_port *mvp = dev_id;
3134 struct mv88e6xxx_chip *chip = mvp->chip;
3135 irqreturn_t ret = IRQ_NONE;
3136 int port = mvp->port;
3137 int lane;
3138
3139 mv88e6xxx_reg_lock(chip);
3140 lane = mv88e6xxx_serdes_get_lane(chip, port);
3141 if (lane >= 0)
3142 ret = mv88e6xxx_serdes_irq_status(chip, port, lane);
3143 mv88e6xxx_reg_unlock(chip);
3144
3145 return ret;
3146}
3147
3148static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,
3149 int lane)
3150{
3151 struct mv88e6xxx_port *dev_id = &chip->ports[port];
3152 unsigned int irq;
3153 int err;
3154
3155 /* Nothing to request if this SERDES port has no IRQ */
3156 irq = mv88e6xxx_serdes_irq_mapping(chip, port);
3157 if (!irq)
3158 return 0;
3159
3160 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name),
3161 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port);
3162
3163 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */
3164 mv88e6xxx_reg_unlock(chip);
3165 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn,
3166 IRQF_ONESHOT, dev_id->serdes_irq_name,
3167 dev_id);
3168 mv88e6xxx_reg_lock(chip);
3169 if (err)
3170 return err;
3171
3172 dev_id->serdes_irq = irq;
3173
3174 return mv88e6xxx_serdes_irq_enable(chip, port, lane);
3175}
3176
3177static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,
3178 int lane)
3179{
3180 struct mv88e6xxx_port *dev_id = &chip->ports[port];
3181 unsigned int irq = dev_id->serdes_irq;
3182 int err;
3183
3184 /* Nothing to free if no IRQ has been requested */
3185 if (!irq)
3186 return 0;
3187
3188 err = mv88e6xxx_serdes_irq_disable(chip, port, lane);
3189
3190 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */
3191 mv88e6xxx_reg_unlock(chip);
3192 free_irq(irq, dev_id);
3193 mv88e6xxx_reg_lock(chip);
3194
3195 dev_id->serdes_irq = 0;
3196
3197 return err;
3198}
3199
3200static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
3201 bool on)
3202{
3203 int lane;
3204 int err;
3205
3206 lane = mv88e6xxx_serdes_get_lane(chip, port);
3207 if (lane < 0)
3208 return 0;
3209
3210 if (on) {
3211 err = mv88e6xxx_serdes_power_up(chip, port, lane);
3212 if (err)
3213 return err;
3214
3215 err = mv88e6xxx_serdes_irq_request(chip, port, lane);
3216 } else {
3217 err = mv88e6xxx_serdes_irq_free(chip, port, lane);
3218 if (err)
3219 return err;
3220
3221 err = mv88e6xxx_serdes_power_down(chip, port, lane);
3222 }
3223
3224 return err;
3225}
3226
3227static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,
3228 enum mv88e6xxx_egress_direction direction,
3229 int port)
3230{
3231 int err;
3232
3233 if (!chip->info->ops->set_egress_port)
3234 return -EOPNOTSUPP;
3235
3236 err = chip->info->ops->set_egress_port(chip, direction, port);
3237 if (err)
3238 return err;
3239
3240 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)
3241 chip->ingress_dest_port = port;
3242 else
3243 chip->egress_dest_port = port;
3244
3245 return 0;
3246}
3247
3248static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
3249{
3250 struct dsa_switch *ds = chip->ds;
3251 int upstream_port;
3252 int err;
3253
3254 upstream_port = dsa_upstream_port(ds, port);
3255 if (chip->info->ops->port_set_upstream_port) {
3256 err = chip->info->ops->port_set_upstream_port(chip, port,
3257 upstream_port);
3258 if (err)
3259 return err;
3260 }
3261
3262 if (port == upstream_port) {
3263 if (chip->info->ops->set_cpu_port) {
3264 err = chip->info->ops->set_cpu_port(chip,
3265 upstream_port);
3266 if (err)
3267 return err;
3268 }
3269
3270 err = mv88e6xxx_set_egress_port(chip,
3271 MV88E6XXX_EGRESS_DIR_INGRESS,
3272 upstream_port);
3273 if (err && err != -EOPNOTSUPP)
3274 return err;
3275
3276 err = mv88e6xxx_set_egress_port(chip,
3277 MV88E6XXX_EGRESS_DIR_EGRESS,
3278 upstream_port);
3279 if (err && err != -EOPNOTSUPP)
3280 return err;
3281 }
3282
3283 return 0;
3284}
3285
3286static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
3287{
3288 struct device_node *phy_handle = NULL;
3289 struct dsa_switch *ds = chip->ds;
3290 phy_interface_t mode;
3291 struct dsa_port *dp;
3292 int tx_amp, speed;
3293 int err;
3294 u16 reg;
3295
3296 chip->ports[port].chip = chip;
3297 chip->ports[port].port = port;
3298
3299 dp = dsa_to_port(ds, port);
3300
3301 /* MAC Forcing register: don't force link, speed, duplex or flow control
3302 * state to any particular values on physical ports, but force the CPU
3303 * port and all DSA ports to their maximum bandwidth and full duplex.
3304 */
3305 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
3306 struct phylink_config pl_config = {};
3307 unsigned long caps;
3308
3309 chip->info->ops->phylink_get_caps(chip, port, &pl_config);
3310
3311 caps = pl_config.mac_capabilities;
3312
3313 if (chip->info->ops->port_max_speed_mode)
3314 mode = chip->info->ops->port_max_speed_mode(port);
3315 else
3316 mode = PHY_INTERFACE_MODE_NA;
3317
3318 if (caps & MAC_10000FD)
3319 speed = SPEED_10000;
3320 else if (caps & MAC_5000FD)
3321 speed = SPEED_5000;
3322 else if (caps & MAC_2500FD)
3323 speed = SPEED_2500;
3324 else if (caps & MAC_1000)
3325 speed = SPEED_1000;
3326 else if (caps & MAC_100)
3327 speed = SPEED_100;
3328 else
3329 speed = SPEED_10;
3330
3331 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
3332 speed, DUPLEX_FULL,
3333 PAUSE_OFF, mode);
3334 } else {
3335 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
3336 SPEED_UNFORCED, DUPLEX_UNFORCED,
3337 PAUSE_ON,
3338 PHY_INTERFACE_MODE_NA);
3339 }
3340 if (err)
3341 return err;
3342
3343 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
3344 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
3345 * tunneling, determine priority by looking at 802.1p and IP
3346 * priority fields (IP prio has precedence), and set STP state
3347 * to Forwarding.
3348 *
3349 * If this is the CPU link, use DSA or EDSA tagging depending
3350 * on which tagging mode was configured.
3351 *
3352 * If this is a link to another switch, use DSA tagging mode.
3353 *
3354 * If this is the upstream port for this switch, enable
3355 * forwarding of unknown unicasts and multicasts.
3356 */
3357 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
3358 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
3359 MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
3360 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
3361 if (err)
3362 return err;
3363
3364 err = mv88e6xxx_setup_port_mode(chip, port);
3365 if (err)
3366 return err;
3367
3368 err = mv88e6xxx_setup_egress_floods(chip, port);
3369 if (err)
3370 return err;
3371
3372 /* Port Control 2: don't force a good FCS, set the MTU size to
3373 * 10222 bytes, disable 802.1q tags checking, don't discard
3374 * tagged or untagged frames on this port, skip destination
3375 * address lookup on user ports, disable ARP mirroring and don't
3376 * send a copy of all transmitted/received frames on this port
3377 * to the CPU.
3378 */
3379 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port));
3380 if (err)
3381 return err;
3382
3383 err = mv88e6xxx_setup_upstream_port(chip, port);
3384 if (err)
3385 return err;
3386
3387 /* On chips that support it, set all downstream DSA ports'
3388 * VLAN policy to TRAP. In combination with loading
3389 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this
3390 * provides a better isolation barrier between standalone
3391 * ports, as the ATU is bypassed on any intermediate switches
3392 * between the incoming port and the CPU.
3393 */
3394 if (dsa_is_downstream_port(ds, port) &&
3395 chip->info->ops->port_set_policy) {
3396 err = chip->info->ops->port_set_policy(chip, port,
3397 MV88E6XXX_POLICY_MAPPING_VTU,
3398 MV88E6XXX_POLICY_ACTION_TRAP);
3399 if (err)
3400 return err;
3401 }
3402
3403 /* User ports start out in standalone mode and 802.1Q is
3404 * therefore disabled. On DSA ports, all valid VIDs are always
3405 * loaded in the VTU - therefore, enable 802.1Q in order to take
3406 * advantage of VLAN policy on chips that supports it.
3407 */
3408 err = mv88e6xxx_port_set_8021q_mode(chip, port,
3409 dsa_is_user_port(ds, port) ?
3410 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED :
3411 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE);
3412 if (err)
3413 return err;
3414
3415 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by
3416 * virtue of the fact that mv88e6xxx_atu_new() will pick it as
3417 * the first free FID. This will be used as the private PVID for
3418 * unbridged ports. Shared (DSA and CPU) ports must also be
3419 * members of this VID, in order to trap all frames assigned to
3420 * it to the CPU.
3421 */
3422 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE,
3423 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3424 false);
3425 if (err)
3426 return err;
3427
3428 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the
3429 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as
3430 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used
3431 * as the private PVID on ports under a VLAN-unaware bridge.
3432 * Shared (DSA and CPU) ports must also be members of it, to translate
3433 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of
3434 * relying on their port default FID.
3435 */
3436 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED,
3437 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED,
3438 false);
3439 if (err)
3440 return err;
3441
3442 if (chip->info->ops->port_set_jumbo_size) {
3443 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218);
3444 if (err)
3445 return err;
3446 }
3447
3448 /* Port Association Vector: disable automatic address learning
3449 * on all user ports since they start out in standalone
3450 * mode. When joining a bridge, learning will be configured to
3451 * match the bridge port settings. Enable learning on all
3452 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the
3453 * learning process.
3454 *
3455 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData,
3456 * and RefreshLocked. I.e. setup standard automatic learning.
3457 */
3458 if (dsa_is_user_port(ds, port))
3459 reg = 0;
3460 else
3461 reg = 1 << port;
3462
3463 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
3464 reg);
3465 if (err)
3466 return err;
3467
3468 /* Egress rate control 2: disable egress rate control. */
3469 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
3470 0x0000);
3471 if (err)
3472 return err;
3473
3474 if (chip->info->ops->port_pause_limit) {
3475 err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
3476 if (err)
3477 return err;
3478 }
3479
3480 if (chip->info->ops->port_disable_learn_limit) {
3481 err = chip->info->ops->port_disable_learn_limit(chip, port);
3482 if (err)
3483 return err;
3484 }
3485
3486 if (chip->info->ops->port_disable_pri_override) {
3487 err = chip->info->ops->port_disable_pri_override(chip, port);
3488 if (err)
3489 return err;
3490 }
3491
3492 if (chip->info->ops->port_tag_remap) {
3493 err = chip->info->ops->port_tag_remap(chip, port);
3494 if (err)
3495 return err;
3496 }
3497
3498 if (chip->info->ops->port_egress_rate_limiting) {
3499 err = chip->info->ops->port_egress_rate_limiting(chip, port);
3500 if (err)
3501 return err;
3502 }
3503
3504 if (chip->info->ops->port_setup_message_port) {
3505 err = chip->info->ops->port_setup_message_port(chip, port);
3506 if (err)
3507 return err;
3508 }
3509
3510 if (chip->info->ops->serdes_set_tx_amplitude) {
3511 if (dp)
3512 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0);
3513
3514 if (phy_handle && !of_property_read_u32(phy_handle,
3515 "tx-p2p-microvolt",
3516 &tx_amp))
3517 err = chip->info->ops->serdes_set_tx_amplitude(chip,
3518 port, tx_amp);
3519 if (phy_handle) {
3520 of_node_put(phy_handle);
3521 if (err)
3522 return err;
3523 }
3524 }
3525
3526 /* Port based VLAN map: give each port the same default address
3527 * database, and allow bidirectional communication between the
3528 * CPU and DSA port(s), and the other ports.
3529 */
3530 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE);
3531 if (err)
3532 return err;
3533
3534 err = mv88e6xxx_port_vlan_map(chip, port);
3535 if (err)
3536 return err;
3537
3538 /* Default VLAN ID and priority: don't set a default VLAN
3539 * ID, and set the default packet priority to zero.
3540 */
3541 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
3542}
3543
3544static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port)
3545{
3546 struct mv88e6xxx_chip *chip = ds->priv;
3547
3548 if (chip->info->ops->port_set_jumbo_size)
3549 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3550 else if (chip->info->ops->set_max_frame_size)
3551 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3552 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN;
3553}
3554
3555static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
3556{
3557 struct mv88e6xxx_chip *chip = ds->priv;
3558 int ret = 0;
3559
3560 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
3561 new_mtu += EDSA_HLEN;
3562
3563 mv88e6xxx_reg_lock(chip);
3564 if (chip->info->ops->port_set_jumbo_size)
3565 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu);
3566 else if (chip->info->ops->set_max_frame_size)
3567 ret = chip->info->ops->set_max_frame_size(chip, new_mtu);
3568 else
3569 if (new_mtu > 1522)
3570 ret = -EINVAL;
3571 mv88e6xxx_reg_unlock(chip);
3572
3573 return ret;
3574}
3575
3576static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
3577 struct phy_device *phydev)
3578{
3579 struct mv88e6xxx_chip *chip = ds->priv;
3580 int err;
3581
3582 mv88e6xxx_reg_lock(chip);
3583 err = mv88e6xxx_serdes_power(chip, port, true);
3584 mv88e6xxx_reg_unlock(chip);
3585
3586 return err;
3587}
3588
3589static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port)
3590{
3591 struct mv88e6xxx_chip *chip = ds->priv;
3592
3593 mv88e6xxx_reg_lock(chip);
3594 if (mv88e6xxx_serdes_power(chip, port, false))
3595 dev_err(chip->dev, "failed to power off SERDES\n");
3596 mv88e6xxx_reg_unlock(chip);
3597}
3598
3599static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3600 unsigned int ageing_time)
3601{
3602 struct mv88e6xxx_chip *chip = ds->priv;
3603 int err;
3604
3605 mv88e6xxx_reg_lock(chip);
3606 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
3607 mv88e6xxx_reg_unlock(chip);
3608
3609 return err;
3610}
3611
3612static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
3613{
3614 int err;
3615
3616 /* Initialize the statistics unit */
3617 if (chip->info->ops->stats_set_histogram) {
3618 err = chip->info->ops->stats_set_histogram(chip);
3619 if (err)
3620 return err;
3621 }
3622
3623 return mv88e6xxx_g1_stats_clear(chip);
3624}
3625
3626/* Check if the errata has already been applied. */
3627static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
3628{
3629 int port;
3630 int err;
3631 u16 val;
3632
3633 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3634 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val);
3635 if (err) {
3636 dev_err(chip->dev,
3637 "Error reading hidden register: %d\n", err);
3638 return false;
3639 }
3640 if (val != 0x01c0)
3641 return false;
3642 }
3643
3644 return true;
3645}
3646
3647/* The 6390 copper ports have an errata which require poking magic
3648 * values into undocumented hidden registers and then performing a
3649 * software reset.
3650 */
3651static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
3652{
3653 int port;
3654 int err;
3655
3656 if (mv88e6390_setup_errata_applied(chip))
3657 return 0;
3658
3659 /* Set the ports into blocking mode */
3660 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3661 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
3662 if (err)
3663 return err;
3664 }
3665
3666 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
3667 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0);
3668 if (err)
3669 return err;
3670 }
3671
3672 return mv88e6xxx_software_reset(chip);
3673}
3674
3675static void mv88e6xxx_teardown(struct dsa_switch *ds)
3676{
3677 mv88e6xxx_teardown_devlink_params(ds);
3678 dsa_devlink_resources_unregister(ds);
3679 mv88e6xxx_teardown_devlink_regions_global(ds);
3680}
3681
3682static int mv88e6xxx_setup(struct dsa_switch *ds)
3683{
3684 struct mv88e6xxx_chip *chip = ds->priv;
3685 u8 cmode;
3686 int err;
3687 int i;
3688
3689 chip->ds = ds;
3690 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
3691
3692 /* Since virtual bridges are mapped in the PVT, the number we support
3693 * depends on the physical switch topology. We need to let DSA figure
3694 * that out and therefore we cannot set this at dsa_register_switch()
3695 * time.
3696 */
3697 if (mv88e6xxx_has_pvt(chip))
3698 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES -
3699 ds->dst->last_switch - 1;
3700
3701 mv88e6xxx_reg_lock(chip);
3702
3703 if (chip->info->ops->setup_errata) {
3704 err = chip->info->ops->setup_errata(chip);
3705 if (err)
3706 goto unlock;
3707 }
3708
3709 /* Cache the cmode of each port. */
3710 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3711 if (chip->info->ops->port_get_cmode) {
3712 err = chip->info->ops->port_get_cmode(chip, i, &cmode);
3713 if (err)
3714 goto unlock;
3715
3716 chip->ports[i].cmode = cmode;
3717 }
3718 }
3719
3720 err = mv88e6xxx_vtu_setup(chip);
3721 if (err)
3722 goto unlock;
3723
3724 /* Must be called after mv88e6xxx_vtu_setup (which flushes the
3725 * VTU, thereby also flushing the STU).
3726 */
3727 err = mv88e6xxx_stu_setup(chip);
3728 if (err)
3729 goto unlock;
3730
3731 /* Setup Switch Port Registers */
3732 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
3733 if (dsa_is_unused_port(ds, i))
3734 continue;
3735
3736 /* Prevent the use of an invalid port. */
3737 if (mv88e6xxx_is_invalid_port(chip, i)) {
3738 dev_err(chip->dev, "port %d is invalid\n", i);
3739 err = -EINVAL;
3740 goto unlock;
3741 }
3742
3743 err = mv88e6xxx_setup_port(chip, i);
3744 if (err)
3745 goto unlock;
3746 }
3747
3748 err = mv88e6xxx_irl_setup(chip);
3749 if (err)
3750 goto unlock;
3751
3752 err = mv88e6xxx_mac_setup(chip);
3753 if (err)
3754 goto unlock;
3755
3756 err = mv88e6xxx_phy_setup(chip);
3757 if (err)
3758 goto unlock;
3759
3760 err = mv88e6xxx_pvt_setup(chip);
3761 if (err)
3762 goto unlock;
3763
3764 err = mv88e6xxx_atu_setup(chip);
3765 if (err)
3766 goto unlock;
3767
3768 err = mv88e6xxx_broadcast_setup(chip, 0);
3769 if (err)
3770 goto unlock;
3771
3772 err = mv88e6xxx_pot_setup(chip);
3773 if (err)
3774 goto unlock;
3775
3776 err = mv88e6xxx_rmu_setup(chip);
3777 if (err)
3778 goto unlock;
3779
3780 err = mv88e6xxx_rsvd2cpu_setup(chip);
3781 if (err)
3782 goto unlock;
3783
3784 err = mv88e6xxx_trunk_setup(chip);
3785 if (err)
3786 goto unlock;
3787
3788 err = mv88e6xxx_devmap_setup(chip);
3789 if (err)
3790 goto unlock;
3791
3792 err = mv88e6xxx_pri_setup(chip);
3793 if (err)
3794 goto unlock;
3795
3796 /* Setup PTP Hardware Clock and timestamping */
3797 if (chip->info->ptp_support) {
3798 err = mv88e6xxx_ptp_setup(chip);
3799 if (err)
3800 goto unlock;
3801
3802 err = mv88e6xxx_hwtstamp_setup(chip);
3803 if (err)
3804 goto unlock;
3805 }
3806
3807 err = mv88e6xxx_stats_setup(chip);
3808 if (err)
3809 goto unlock;
3810
3811unlock:
3812 mv88e6xxx_reg_unlock(chip);
3813
3814 if (err)
3815 return err;
3816
3817 /* Have to be called without holding the register lock, since
3818 * they take the devlink lock, and we later take the locks in
3819 * the reverse order when getting/setting parameters or
3820 * resource occupancy.
3821 */
3822 err = mv88e6xxx_setup_devlink_resources(ds);
3823 if (err)
3824 return err;
3825
3826 err = mv88e6xxx_setup_devlink_params(ds);
3827 if (err)
3828 goto out_resources;
3829
3830 err = mv88e6xxx_setup_devlink_regions_global(ds);
3831 if (err)
3832 goto out_params;
3833
3834 return 0;
3835
3836out_params:
3837 mv88e6xxx_teardown_devlink_params(ds);
3838out_resources:
3839 dsa_devlink_resources_unregister(ds);
3840
3841 return err;
3842}
3843
3844static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port)
3845{
3846 return mv88e6xxx_setup_devlink_regions_port(ds, port);
3847}
3848
3849static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port)
3850{
3851 mv88e6xxx_teardown_devlink_regions_port(ds, port);
3852}
3853
3854/* prod_id for switch families which do not have a PHY model number */
3855static const u16 family_prod_id_table[] = {
3856 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
3857 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
3858 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
3859};
3860
3861static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3862{
3863 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3864 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3865 u16 prod_id;
3866 u16 val;
3867 int err;
3868
3869 if (!chip->info->ops->phy_read)
3870 return -EOPNOTSUPP;
3871
3872 mv88e6xxx_reg_lock(chip);
3873 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
3874 mv88e6xxx_reg_unlock(chip);
3875
3876 /* Some internal PHYs don't have a model number. */
3877 if (reg == MII_PHYSID2 && !(val & 0x3f0) &&
3878 chip->info->family < ARRAY_SIZE(family_prod_id_table)) {
3879 prod_id = family_prod_id_table[chip->info->family];
3880 if (prod_id)
3881 val |= prod_id >> 4;
3882 }
3883
3884 return err ? err : val;
3885}
3886
3887static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3888{
3889 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
3890 struct mv88e6xxx_chip *chip = mdio_bus->chip;
3891 int err;
3892
3893 if (!chip->info->ops->phy_write)
3894 return -EOPNOTSUPP;
3895
3896 mv88e6xxx_reg_lock(chip);
3897 err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
3898 mv88e6xxx_reg_unlock(chip);
3899
3900 return err;
3901}
3902
3903static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3904 struct device_node *np,
3905 bool external)
3906{
3907 static int index;
3908 struct mv88e6xxx_mdio_bus *mdio_bus;
3909 struct mii_bus *bus;
3910 int err;
3911
3912 if (external) {
3913 mv88e6xxx_reg_lock(chip);
3914 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
3915 mv88e6xxx_reg_unlock(chip);
3916
3917 if (err)
3918 return err;
3919 }
3920
3921 bus = mdiobus_alloc_size(sizeof(*mdio_bus));
3922 if (!bus)
3923 return -ENOMEM;
3924
3925 mdio_bus = bus->priv;
3926 mdio_bus->bus = bus;
3927 mdio_bus->chip = chip;
3928 INIT_LIST_HEAD(&mdio_bus->list);
3929 mdio_bus->external = external;
3930
3931 if (np) {
3932 bus->name = np->full_name;
3933 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
3934 } else {
3935 bus->name = "mv88e6xxx SMI";
3936 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3937 }
3938
3939 bus->read = mv88e6xxx_mdio_read;
3940 bus->write = mv88e6xxx_mdio_write;
3941 bus->parent = chip->dev;
3942
3943 if (!external) {
3944 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
3945 if (err)
3946 goto out;
3947 }
3948
3949 err = of_mdiobus_register(bus, np);
3950 if (err) {
3951 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3952 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3953 goto out;
3954 }
3955
3956 if (external)
3957 list_add_tail(&mdio_bus->list, &chip->mdios);
3958 else
3959 list_add(&mdio_bus->list, &chip->mdios);
3960
3961 return 0;
3962
3963out:
3964 mdiobus_free(bus);
3965 return err;
3966}
3967
3968static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
3969
3970{
3971 struct mv88e6xxx_mdio_bus *mdio_bus, *p;
3972 struct mii_bus *bus;
3973
3974 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) {
3975 bus = mdio_bus->bus;
3976
3977 if (!mdio_bus->external)
3978 mv88e6xxx_g2_irq_mdio_free(chip, bus);
3979
3980 mdiobus_unregister(bus);
3981 mdiobus_free(bus);
3982 }
3983}
3984
3985static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
3986 struct device_node *np)
3987{
3988 struct device_node *child;
3989 int err;
3990
3991 /* Always register one mdio bus for the internal/default mdio
3992 * bus. This maybe represented in the device tree, but is
3993 * optional.
3994 */
3995 child = of_get_child_by_name(np, "mdio");
3996 err = mv88e6xxx_mdio_register(chip, child, false);
3997 of_node_put(child);
3998 if (err)
3999 return err;
4000
4001 /* Walk the device tree, and see if there are any other nodes
4002 * which say they are compatible with the external mdio
4003 * bus.
4004 */
4005 for_each_available_child_of_node(np, child) {
4006 if (of_device_is_compatible(
4007 child, "marvell,mv88e6xxx-mdio-external")) {
4008 err = mv88e6xxx_mdio_register(chip, child, true);
4009 if (err) {
4010 mv88e6xxx_mdios_unregister(chip);
4011 of_node_put(child);
4012 return err;
4013 }
4014 }
4015 }
4016
4017 return 0;
4018}
4019
4020static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
4021{
4022 struct mv88e6xxx_chip *chip = ds->priv;
4023
4024 return chip->eeprom_len;
4025}
4026
4027static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
4028 struct ethtool_eeprom *eeprom, u8 *data)
4029{
4030 struct mv88e6xxx_chip *chip = ds->priv;
4031 int err;
4032
4033 if (!chip->info->ops->get_eeprom)
4034 return -EOPNOTSUPP;
4035
4036 mv88e6xxx_reg_lock(chip);
4037 err = chip->info->ops->get_eeprom(chip, eeprom, data);
4038 mv88e6xxx_reg_unlock(chip);
4039
4040 if (err)
4041 return err;
4042
4043 eeprom->magic = 0xc3ec4951;
4044
4045 return 0;
4046}
4047
4048static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
4049 struct ethtool_eeprom *eeprom, u8 *data)
4050{
4051 struct mv88e6xxx_chip *chip = ds->priv;
4052 int err;
4053
4054 if (!chip->info->ops->set_eeprom)
4055 return -EOPNOTSUPP;
4056
4057 if (eeprom->magic != 0xc3ec4951)
4058 return -EINVAL;
4059
4060 mv88e6xxx_reg_lock(chip);
4061 err = chip->info->ops->set_eeprom(chip, eeprom, data);
4062 mv88e6xxx_reg_unlock(chip);
4063
4064 return err;
4065}
4066
4067static const struct mv88e6xxx_ops mv88e6085_ops = {
4068 /* MV88E6XXX_FAMILY_6097 */
4069 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4070 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4071 .irl_init_all = mv88e6352_g2_irl_init_all,
4072 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4073 .phy_read = mv88e6185_phy_ppu_read,
4074 .phy_write = mv88e6185_phy_ppu_write,
4075 .port_set_link = mv88e6xxx_port_set_link,
4076 .port_sync_link = mv88e6xxx_port_sync_link,
4077 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4078 .port_tag_remap = mv88e6095_port_tag_remap,
4079 .port_set_policy = mv88e6352_port_set_policy,
4080 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4081 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4082 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4083 .port_set_ether_type = mv88e6351_port_set_ether_type,
4084 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4085 .port_pause_limit = mv88e6097_port_pause_limit,
4086 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4087 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4088 .port_get_cmode = mv88e6185_port_get_cmode,
4089 .port_setup_message_port = mv88e6xxx_setup_message_port,
4090 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4091 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4092 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4093 .stats_get_strings = mv88e6095_stats_get_strings,
4094 .stats_get_stats = mv88e6095_stats_get_stats,
4095 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4096 .set_egress_port = mv88e6095_g1_set_egress_port,
4097 .watchdog_ops = &mv88e6097_watchdog_ops,
4098 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4099 .pot_clear = mv88e6xxx_g2_pot_clear,
4100 .ppu_enable = mv88e6185_g1_ppu_enable,
4101 .ppu_disable = mv88e6185_g1_ppu_disable,
4102 .reset = mv88e6185_g1_reset,
4103 .rmu_disable = mv88e6085_g1_rmu_disable,
4104 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4105 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4106 .stu_getnext = mv88e6352_g1_stu_getnext,
4107 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4108 .phylink_get_caps = mv88e6185_phylink_get_caps,
4109 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4110};
4111
4112static const struct mv88e6xxx_ops mv88e6095_ops = {
4113 /* MV88E6XXX_FAMILY_6095 */
4114 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4115 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4116 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4117 .phy_read = mv88e6185_phy_ppu_read,
4118 .phy_write = mv88e6185_phy_ppu_write,
4119 .port_set_link = mv88e6xxx_port_set_link,
4120 .port_sync_link = mv88e6185_port_sync_link,
4121 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4122 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4123 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4124 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4125 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4126 .port_get_cmode = mv88e6185_port_get_cmode,
4127 .port_setup_message_port = mv88e6xxx_setup_message_port,
4128 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4129 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4130 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4131 .stats_get_strings = mv88e6095_stats_get_strings,
4132 .stats_get_stats = mv88e6095_stats_get_stats,
4133 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4134 .serdes_power = mv88e6185_serdes_power,
4135 .serdes_get_lane = mv88e6185_serdes_get_lane,
4136 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4137 .ppu_enable = mv88e6185_g1_ppu_enable,
4138 .ppu_disable = mv88e6185_g1_ppu_disable,
4139 .reset = mv88e6185_g1_reset,
4140 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4141 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4142 .phylink_get_caps = mv88e6095_phylink_get_caps,
4143 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4144};
4145
4146static const struct mv88e6xxx_ops mv88e6097_ops = {
4147 /* MV88E6XXX_FAMILY_6097 */
4148 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4149 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4150 .irl_init_all = mv88e6352_g2_irl_init_all,
4151 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4152 .phy_read = mv88e6xxx_g2_smi_phy_read,
4153 .phy_write = mv88e6xxx_g2_smi_phy_write,
4154 .port_set_link = mv88e6xxx_port_set_link,
4155 .port_sync_link = mv88e6185_port_sync_link,
4156 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4157 .port_tag_remap = mv88e6095_port_tag_remap,
4158 .port_set_policy = mv88e6352_port_set_policy,
4159 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4160 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4161 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4162 .port_set_ether_type = mv88e6351_port_set_ether_type,
4163 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4164 .port_pause_limit = mv88e6097_port_pause_limit,
4165 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4166 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4167 .port_get_cmode = mv88e6185_port_get_cmode,
4168 .port_setup_message_port = mv88e6xxx_setup_message_port,
4169 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4170 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4171 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4172 .stats_get_strings = mv88e6095_stats_get_strings,
4173 .stats_get_stats = mv88e6095_stats_get_stats,
4174 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4175 .set_egress_port = mv88e6095_g1_set_egress_port,
4176 .watchdog_ops = &mv88e6097_watchdog_ops,
4177 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4178 .serdes_power = mv88e6185_serdes_power,
4179 .serdes_get_lane = mv88e6185_serdes_get_lane,
4180 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4181 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4182 .serdes_irq_enable = mv88e6097_serdes_irq_enable,
4183 .serdes_irq_status = mv88e6097_serdes_irq_status,
4184 .pot_clear = mv88e6xxx_g2_pot_clear,
4185 .reset = mv88e6352_g1_reset,
4186 .rmu_disable = mv88e6085_g1_rmu_disable,
4187 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4188 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4189 .phylink_get_caps = mv88e6095_phylink_get_caps,
4190 .stu_getnext = mv88e6352_g1_stu_getnext,
4191 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4192 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4193};
4194
4195static const struct mv88e6xxx_ops mv88e6123_ops = {
4196 /* MV88E6XXX_FAMILY_6165 */
4197 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4198 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4199 .irl_init_all = mv88e6352_g2_irl_init_all,
4200 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4201 .phy_read = mv88e6xxx_g2_smi_phy_read,
4202 .phy_write = mv88e6xxx_g2_smi_phy_write,
4203 .port_set_link = mv88e6xxx_port_set_link,
4204 .port_sync_link = mv88e6xxx_port_sync_link,
4205 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4206 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4207 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4208 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4209 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4210 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4211 .port_get_cmode = mv88e6185_port_get_cmode,
4212 .port_setup_message_port = mv88e6xxx_setup_message_port,
4213 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4214 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4215 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4216 .stats_get_strings = mv88e6095_stats_get_strings,
4217 .stats_get_stats = mv88e6095_stats_get_stats,
4218 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4219 .set_egress_port = mv88e6095_g1_set_egress_port,
4220 .watchdog_ops = &mv88e6097_watchdog_ops,
4221 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4222 .pot_clear = mv88e6xxx_g2_pot_clear,
4223 .reset = mv88e6352_g1_reset,
4224 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4225 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4226 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4227 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4228 .stu_getnext = mv88e6352_g1_stu_getnext,
4229 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4230 .phylink_get_caps = mv88e6185_phylink_get_caps,
4231 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4232};
4233
4234static const struct mv88e6xxx_ops mv88e6131_ops = {
4235 /* MV88E6XXX_FAMILY_6185 */
4236 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4237 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4238 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4239 .phy_read = mv88e6185_phy_ppu_read,
4240 .phy_write = mv88e6185_phy_ppu_write,
4241 .port_set_link = mv88e6xxx_port_set_link,
4242 .port_sync_link = mv88e6xxx_port_sync_link,
4243 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4244 .port_tag_remap = mv88e6095_port_tag_remap,
4245 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4246 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4247 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4248 .port_set_ether_type = mv88e6351_port_set_ether_type,
4249 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4250 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4251 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4252 .port_pause_limit = mv88e6097_port_pause_limit,
4253 .port_set_pause = mv88e6185_port_set_pause,
4254 .port_get_cmode = mv88e6185_port_get_cmode,
4255 .port_setup_message_port = mv88e6xxx_setup_message_port,
4256 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4257 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4258 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4259 .stats_get_strings = mv88e6095_stats_get_strings,
4260 .stats_get_stats = mv88e6095_stats_get_stats,
4261 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4262 .set_egress_port = mv88e6095_g1_set_egress_port,
4263 .watchdog_ops = &mv88e6097_watchdog_ops,
4264 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4265 .ppu_enable = mv88e6185_g1_ppu_enable,
4266 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4267 .ppu_disable = mv88e6185_g1_ppu_disable,
4268 .reset = mv88e6185_g1_reset,
4269 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4270 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4271 .phylink_get_caps = mv88e6185_phylink_get_caps,
4272};
4273
4274static const struct mv88e6xxx_ops mv88e6141_ops = {
4275 /* MV88E6XXX_FAMILY_6341 */
4276 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4277 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4278 .irl_init_all = mv88e6352_g2_irl_init_all,
4279 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4280 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4281 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4282 .phy_read = mv88e6xxx_g2_smi_phy_read,
4283 .phy_write = mv88e6xxx_g2_smi_phy_write,
4284 .port_set_link = mv88e6xxx_port_set_link,
4285 .port_sync_link = mv88e6xxx_port_sync_link,
4286 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4287 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
4288 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
4289 .port_tag_remap = mv88e6095_port_tag_remap,
4290 .port_set_policy = mv88e6352_port_set_policy,
4291 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4292 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4293 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4294 .port_set_ether_type = mv88e6351_port_set_ether_type,
4295 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4296 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4297 .port_pause_limit = mv88e6097_port_pause_limit,
4298 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4299 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4300 .port_get_cmode = mv88e6352_port_get_cmode,
4301 .port_set_cmode = mv88e6341_port_set_cmode,
4302 .port_setup_message_port = mv88e6xxx_setup_message_port,
4303 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4304 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4305 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4306 .stats_get_strings = mv88e6320_stats_get_strings,
4307 .stats_get_stats = mv88e6390_stats_get_stats,
4308 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4309 .set_egress_port = mv88e6390_g1_set_egress_port,
4310 .watchdog_ops = &mv88e6390_watchdog_ops,
4311 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4312 .pot_clear = mv88e6xxx_g2_pot_clear,
4313 .reset = mv88e6352_g1_reset,
4314 .rmu_disable = mv88e6390_g1_rmu_disable,
4315 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4316 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4317 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4318 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4319 .stu_getnext = mv88e6352_g1_stu_getnext,
4320 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4321 .serdes_power = mv88e6390_serdes_power,
4322 .serdes_get_lane = mv88e6341_serdes_get_lane,
4323 /* Check status register pause & lpa register */
4324 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4325 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4326 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4327 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4328 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4329 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4330 .serdes_irq_status = mv88e6390_serdes_irq_status,
4331 .gpio_ops = &mv88e6352_gpio_ops,
4332 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
4333 .serdes_get_strings = mv88e6390_serdes_get_strings,
4334 .serdes_get_stats = mv88e6390_serdes_get_stats,
4335 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4336 .serdes_get_regs = mv88e6390_serdes_get_regs,
4337 .phylink_get_caps = mv88e6341_phylink_get_caps,
4338};
4339
4340static const struct mv88e6xxx_ops mv88e6161_ops = {
4341 /* MV88E6XXX_FAMILY_6165 */
4342 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4343 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4344 .irl_init_all = mv88e6352_g2_irl_init_all,
4345 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4346 .phy_read = mv88e6xxx_g2_smi_phy_read,
4347 .phy_write = mv88e6xxx_g2_smi_phy_write,
4348 .port_set_link = mv88e6xxx_port_set_link,
4349 .port_sync_link = mv88e6xxx_port_sync_link,
4350 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4351 .port_tag_remap = mv88e6095_port_tag_remap,
4352 .port_set_policy = mv88e6352_port_set_policy,
4353 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4354 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4355 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4356 .port_set_ether_type = mv88e6351_port_set_ether_type,
4357 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4358 .port_pause_limit = mv88e6097_port_pause_limit,
4359 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4360 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4361 .port_get_cmode = mv88e6185_port_get_cmode,
4362 .port_setup_message_port = mv88e6xxx_setup_message_port,
4363 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4364 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4365 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4366 .stats_get_strings = mv88e6095_stats_get_strings,
4367 .stats_get_stats = mv88e6095_stats_get_stats,
4368 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4369 .set_egress_port = mv88e6095_g1_set_egress_port,
4370 .watchdog_ops = &mv88e6097_watchdog_ops,
4371 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4372 .pot_clear = mv88e6xxx_g2_pot_clear,
4373 .reset = mv88e6352_g1_reset,
4374 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4375 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4376 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4377 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4378 .stu_getnext = mv88e6352_g1_stu_getnext,
4379 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4380 .avb_ops = &mv88e6165_avb_ops,
4381 .ptp_ops = &mv88e6165_ptp_ops,
4382 .phylink_get_caps = mv88e6185_phylink_get_caps,
4383 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4384};
4385
4386static const struct mv88e6xxx_ops mv88e6165_ops = {
4387 /* MV88E6XXX_FAMILY_6165 */
4388 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4389 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4390 .irl_init_all = mv88e6352_g2_irl_init_all,
4391 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4392 .phy_read = mv88e6165_phy_read,
4393 .phy_write = mv88e6165_phy_write,
4394 .port_set_link = mv88e6xxx_port_set_link,
4395 .port_sync_link = mv88e6xxx_port_sync_link,
4396 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4397 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4398 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4399 .port_get_cmode = mv88e6185_port_get_cmode,
4400 .port_setup_message_port = mv88e6xxx_setup_message_port,
4401 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4402 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4403 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4404 .stats_get_strings = mv88e6095_stats_get_strings,
4405 .stats_get_stats = mv88e6095_stats_get_stats,
4406 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4407 .set_egress_port = mv88e6095_g1_set_egress_port,
4408 .watchdog_ops = &mv88e6097_watchdog_ops,
4409 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4410 .pot_clear = mv88e6xxx_g2_pot_clear,
4411 .reset = mv88e6352_g1_reset,
4412 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4413 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4414 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4415 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4416 .stu_getnext = mv88e6352_g1_stu_getnext,
4417 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4418 .avb_ops = &mv88e6165_avb_ops,
4419 .ptp_ops = &mv88e6165_ptp_ops,
4420 .phylink_get_caps = mv88e6185_phylink_get_caps,
4421};
4422
4423static const struct mv88e6xxx_ops mv88e6171_ops = {
4424 /* MV88E6XXX_FAMILY_6351 */
4425 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4426 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4427 .irl_init_all = mv88e6352_g2_irl_init_all,
4428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4429 .phy_read = mv88e6xxx_g2_smi_phy_read,
4430 .phy_write = mv88e6xxx_g2_smi_phy_write,
4431 .port_set_link = mv88e6xxx_port_set_link,
4432 .port_sync_link = mv88e6xxx_port_sync_link,
4433 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4434 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4435 .port_tag_remap = mv88e6095_port_tag_remap,
4436 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4437 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4438 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4439 .port_set_ether_type = mv88e6351_port_set_ether_type,
4440 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4441 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4442 .port_pause_limit = mv88e6097_port_pause_limit,
4443 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4444 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4445 .port_get_cmode = mv88e6352_port_get_cmode,
4446 .port_setup_message_port = mv88e6xxx_setup_message_port,
4447 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4448 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4449 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4450 .stats_get_strings = mv88e6095_stats_get_strings,
4451 .stats_get_stats = mv88e6095_stats_get_stats,
4452 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4453 .set_egress_port = mv88e6095_g1_set_egress_port,
4454 .watchdog_ops = &mv88e6097_watchdog_ops,
4455 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4456 .pot_clear = mv88e6xxx_g2_pot_clear,
4457 .reset = mv88e6352_g1_reset,
4458 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4459 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4460 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4461 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4462 .stu_getnext = mv88e6352_g1_stu_getnext,
4463 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4464 .phylink_get_caps = mv88e6185_phylink_get_caps,
4465};
4466
4467static const struct mv88e6xxx_ops mv88e6172_ops = {
4468 /* MV88E6XXX_FAMILY_6352 */
4469 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4470 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4471 .irl_init_all = mv88e6352_g2_irl_init_all,
4472 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4473 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4475 .phy_read = mv88e6xxx_g2_smi_phy_read,
4476 .phy_write = mv88e6xxx_g2_smi_phy_write,
4477 .port_set_link = mv88e6xxx_port_set_link,
4478 .port_sync_link = mv88e6xxx_port_sync_link,
4479 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4480 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4481 .port_tag_remap = mv88e6095_port_tag_remap,
4482 .port_set_policy = mv88e6352_port_set_policy,
4483 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4484 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4485 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4486 .port_set_ether_type = mv88e6351_port_set_ether_type,
4487 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4488 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4489 .port_pause_limit = mv88e6097_port_pause_limit,
4490 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4491 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4492 .port_get_cmode = mv88e6352_port_get_cmode,
4493 .port_setup_message_port = mv88e6xxx_setup_message_port,
4494 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4495 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4496 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4497 .stats_get_strings = mv88e6095_stats_get_strings,
4498 .stats_get_stats = mv88e6095_stats_get_stats,
4499 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4500 .set_egress_port = mv88e6095_g1_set_egress_port,
4501 .watchdog_ops = &mv88e6097_watchdog_ops,
4502 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4503 .pot_clear = mv88e6xxx_g2_pot_clear,
4504 .reset = mv88e6352_g1_reset,
4505 .rmu_disable = mv88e6352_g1_rmu_disable,
4506 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4507 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4508 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4509 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4510 .stu_getnext = mv88e6352_g1_stu_getnext,
4511 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4512 .serdes_get_lane = mv88e6352_serdes_get_lane,
4513 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4514 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4515 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4516 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4517 .serdes_power = mv88e6352_serdes_power,
4518 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4519 .serdes_get_regs = mv88e6352_serdes_get_regs,
4520 .gpio_ops = &mv88e6352_gpio_ops,
4521 .phylink_get_caps = mv88e6352_phylink_get_caps,
4522};
4523
4524static const struct mv88e6xxx_ops mv88e6175_ops = {
4525 /* MV88E6XXX_FAMILY_6351 */
4526 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4527 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4528 .irl_init_all = mv88e6352_g2_irl_init_all,
4529 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4530 .phy_read = mv88e6xxx_g2_smi_phy_read,
4531 .phy_write = mv88e6xxx_g2_smi_phy_write,
4532 .port_set_link = mv88e6xxx_port_set_link,
4533 .port_sync_link = mv88e6xxx_port_sync_link,
4534 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4535 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4536 .port_tag_remap = mv88e6095_port_tag_remap,
4537 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4538 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4539 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4540 .port_set_ether_type = mv88e6351_port_set_ether_type,
4541 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4542 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4543 .port_pause_limit = mv88e6097_port_pause_limit,
4544 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4545 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4546 .port_get_cmode = mv88e6352_port_get_cmode,
4547 .port_setup_message_port = mv88e6xxx_setup_message_port,
4548 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4549 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4550 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4551 .stats_get_strings = mv88e6095_stats_get_strings,
4552 .stats_get_stats = mv88e6095_stats_get_stats,
4553 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4554 .set_egress_port = mv88e6095_g1_set_egress_port,
4555 .watchdog_ops = &mv88e6097_watchdog_ops,
4556 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4557 .pot_clear = mv88e6xxx_g2_pot_clear,
4558 .reset = mv88e6352_g1_reset,
4559 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4560 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4561 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4562 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4563 .stu_getnext = mv88e6352_g1_stu_getnext,
4564 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4565 .phylink_get_caps = mv88e6185_phylink_get_caps,
4566};
4567
4568static const struct mv88e6xxx_ops mv88e6176_ops = {
4569 /* MV88E6XXX_FAMILY_6352 */
4570 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4571 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4572 .irl_init_all = mv88e6352_g2_irl_init_all,
4573 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4574 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4576 .phy_read = mv88e6xxx_g2_smi_phy_read,
4577 .phy_write = mv88e6xxx_g2_smi_phy_write,
4578 .port_set_link = mv88e6xxx_port_set_link,
4579 .port_sync_link = mv88e6xxx_port_sync_link,
4580 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4581 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4582 .port_tag_remap = mv88e6095_port_tag_remap,
4583 .port_set_policy = mv88e6352_port_set_policy,
4584 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4585 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4586 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4587 .port_set_ether_type = mv88e6351_port_set_ether_type,
4588 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4589 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4590 .port_pause_limit = mv88e6097_port_pause_limit,
4591 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4592 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4593 .port_get_cmode = mv88e6352_port_get_cmode,
4594 .port_setup_message_port = mv88e6xxx_setup_message_port,
4595 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4597 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4598 .stats_get_strings = mv88e6095_stats_get_strings,
4599 .stats_get_stats = mv88e6095_stats_get_stats,
4600 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4601 .set_egress_port = mv88e6095_g1_set_egress_port,
4602 .watchdog_ops = &mv88e6097_watchdog_ops,
4603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4604 .pot_clear = mv88e6xxx_g2_pot_clear,
4605 .reset = mv88e6352_g1_reset,
4606 .rmu_disable = mv88e6352_g1_rmu_disable,
4607 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4608 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4609 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4610 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4611 .stu_getnext = mv88e6352_g1_stu_getnext,
4612 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4613 .serdes_get_lane = mv88e6352_serdes_get_lane,
4614 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4615 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4616 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4617 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4618 .serdes_power = mv88e6352_serdes_power,
4619 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4620 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4621 .serdes_irq_status = mv88e6352_serdes_irq_status,
4622 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4623 .serdes_get_regs = mv88e6352_serdes_get_regs,
4624 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4625 .gpio_ops = &mv88e6352_gpio_ops,
4626 .phylink_get_caps = mv88e6352_phylink_get_caps,
4627};
4628
4629static const struct mv88e6xxx_ops mv88e6185_ops = {
4630 /* MV88E6XXX_FAMILY_6185 */
4631 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4632 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4633 .set_switch_mac = mv88e6xxx_g1_set_switch_mac,
4634 .phy_read = mv88e6185_phy_ppu_read,
4635 .phy_write = mv88e6185_phy_ppu_write,
4636 .port_set_link = mv88e6xxx_port_set_link,
4637 .port_sync_link = mv88e6185_port_sync_link,
4638 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
4639 .port_set_frame_mode = mv88e6085_port_set_frame_mode,
4640 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown,
4641 .port_set_mcast_flood = mv88e6185_port_set_default_forward,
4642 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
4643 .port_set_upstream_port = mv88e6095_port_set_upstream_port,
4644 .port_set_pause = mv88e6185_port_set_pause,
4645 .port_get_cmode = mv88e6185_port_get_cmode,
4646 .port_setup_message_port = mv88e6xxx_setup_message_port,
4647 .stats_snapshot = mv88e6xxx_g1_stats_snapshot,
4648 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4649 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4650 .stats_get_strings = mv88e6095_stats_get_strings,
4651 .stats_get_stats = mv88e6095_stats_get_stats,
4652 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4653 .set_egress_port = mv88e6095_g1_set_egress_port,
4654 .watchdog_ops = &mv88e6097_watchdog_ops,
4655 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
4656 .serdes_power = mv88e6185_serdes_power,
4657 .serdes_get_lane = mv88e6185_serdes_get_lane,
4658 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state,
4659 .set_cascade_port = mv88e6185_g1_set_cascade_port,
4660 .ppu_enable = mv88e6185_g1_ppu_enable,
4661 .ppu_disable = mv88e6185_g1_ppu_disable,
4662 .reset = mv88e6185_g1_reset,
4663 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4664 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4665 .phylink_get_caps = mv88e6185_phylink_get_caps,
4666 .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
4667};
4668
4669static const struct mv88e6xxx_ops mv88e6190_ops = {
4670 /* MV88E6XXX_FAMILY_6390 */
4671 .setup_errata = mv88e6390_setup_errata,
4672 .irl_init_all = mv88e6390_g2_irl_init_all,
4673 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4674 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4675 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4676 .phy_read = mv88e6xxx_g2_smi_phy_read,
4677 .phy_write = mv88e6xxx_g2_smi_phy_write,
4678 .port_set_link = mv88e6xxx_port_set_link,
4679 .port_sync_link = mv88e6xxx_port_sync_link,
4680 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4681 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4682 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4683 .port_tag_remap = mv88e6390_port_tag_remap,
4684 .port_set_policy = mv88e6352_port_set_policy,
4685 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4686 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4687 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4688 .port_set_ether_type = mv88e6351_port_set_ether_type,
4689 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4690 .port_pause_limit = mv88e6390_port_pause_limit,
4691 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4692 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4693 .port_get_cmode = mv88e6352_port_get_cmode,
4694 .port_set_cmode = mv88e6390_port_set_cmode,
4695 .port_setup_message_port = mv88e6xxx_setup_message_port,
4696 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4697 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4698 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4699 .stats_get_strings = mv88e6320_stats_get_strings,
4700 .stats_get_stats = mv88e6390_stats_get_stats,
4701 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4702 .set_egress_port = mv88e6390_g1_set_egress_port,
4703 .watchdog_ops = &mv88e6390_watchdog_ops,
4704 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4705 .pot_clear = mv88e6xxx_g2_pot_clear,
4706 .reset = mv88e6352_g1_reset,
4707 .rmu_disable = mv88e6390_g1_rmu_disable,
4708 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4709 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4710 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4711 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4712 .stu_getnext = mv88e6390_g1_stu_getnext,
4713 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4714 .serdes_power = mv88e6390_serdes_power,
4715 .serdes_get_lane = mv88e6390_serdes_get_lane,
4716 /* Check status register pause & lpa register */
4717 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4718 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4719 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4720 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4721 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4722 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4723 .serdes_irq_status = mv88e6390_serdes_irq_status,
4724 .serdes_get_strings = mv88e6390_serdes_get_strings,
4725 .serdes_get_stats = mv88e6390_serdes_get_stats,
4726 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4727 .serdes_get_regs = mv88e6390_serdes_get_regs,
4728 .gpio_ops = &mv88e6352_gpio_ops,
4729 .phylink_get_caps = mv88e6390_phylink_get_caps,
4730};
4731
4732static const struct mv88e6xxx_ops mv88e6190x_ops = {
4733 /* MV88E6XXX_FAMILY_6390 */
4734 .setup_errata = mv88e6390_setup_errata,
4735 .irl_init_all = mv88e6390_g2_irl_init_all,
4736 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4737 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4738 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4739 .phy_read = mv88e6xxx_g2_smi_phy_read,
4740 .phy_write = mv88e6xxx_g2_smi_phy_write,
4741 .port_set_link = mv88e6xxx_port_set_link,
4742 .port_sync_link = mv88e6xxx_port_sync_link,
4743 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4744 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
4745 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
4746 .port_tag_remap = mv88e6390_port_tag_remap,
4747 .port_set_policy = mv88e6352_port_set_policy,
4748 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4749 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4750 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4751 .port_set_ether_type = mv88e6351_port_set_ether_type,
4752 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4753 .port_pause_limit = mv88e6390_port_pause_limit,
4754 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4755 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4756 .port_get_cmode = mv88e6352_port_get_cmode,
4757 .port_set_cmode = mv88e6390x_port_set_cmode,
4758 .port_setup_message_port = mv88e6xxx_setup_message_port,
4759 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4760 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4761 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4762 .stats_get_strings = mv88e6320_stats_get_strings,
4763 .stats_get_stats = mv88e6390_stats_get_stats,
4764 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4765 .set_egress_port = mv88e6390_g1_set_egress_port,
4766 .watchdog_ops = &mv88e6390_watchdog_ops,
4767 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4768 .pot_clear = mv88e6xxx_g2_pot_clear,
4769 .reset = mv88e6352_g1_reset,
4770 .rmu_disable = mv88e6390_g1_rmu_disable,
4771 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4772 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4773 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4774 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4775 .stu_getnext = mv88e6390_g1_stu_getnext,
4776 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4777 .serdes_power = mv88e6390_serdes_power,
4778 .serdes_get_lane = mv88e6390x_serdes_get_lane,
4779 /* Check status register pause & lpa register */
4780 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4781 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4782 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4783 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4784 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4785 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4786 .serdes_irq_status = mv88e6390_serdes_irq_status,
4787 .serdes_get_strings = mv88e6390_serdes_get_strings,
4788 .serdes_get_stats = mv88e6390_serdes_get_stats,
4789 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4790 .serdes_get_regs = mv88e6390_serdes_get_regs,
4791 .gpio_ops = &mv88e6352_gpio_ops,
4792 .phylink_get_caps = mv88e6390x_phylink_get_caps,
4793};
4794
4795static const struct mv88e6xxx_ops mv88e6191_ops = {
4796 /* MV88E6XXX_FAMILY_6390 */
4797 .setup_errata = mv88e6390_setup_errata,
4798 .irl_init_all = mv88e6390_g2_irl_init_all,
4799 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4800 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4801 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4802 .phy_read = mv88e6xxx_g2_smi_phy_read,
4803 .phy_write = mv88e6xxx_g2_smi_phy_write,
4804 .port_set_link = mv88e6xxx_port_set_link,
4805 .port_sync_link = mv88e6xxx_port_sync_link,
4806 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4807 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4808 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4809 .port_tag_remap = mv88e6390_port_tag_remap,
4810 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4811 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4812 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4813 .port_set_ether_type = mv88e6351_port_set_ether_type,
4814 .port_pause_limit = mv88e6390_port_pause_limit,
4815 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4816 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4817 .port_get_cmode = mv88e6352_port_get_cmode,
4818 .port_set_cmode = mv88e6390_port_set_cmode,
4819 .port_setup_message_port = mv88e6xxx_setup_message_port,
4820 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4821 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4822 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4823 .stats_get_strings = mv88e6320_stats_get_strings,
4824 .stats_get_stats = mv88e6390_stats_get_stats,
4825 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4826 .set_egress_port = mv88e6390_g1_set_egress_port,
4827 .watchdog_ops = &mv88e6390_watchdog_ops,
4828 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4829 .pot_clear = mv88e6xxx_g2_pot_clear,
4830 .reset = mv88e6352_g1_reset,
4831 .rmu_disable = mv88e6390_g1_rmu_disable,
4832 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4833 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4834 .vtu_getnext = mv88e6390_g1_vtu_getnext,
4835 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
4836 .stu_getnext = mv88e6390_g1_stu_getnext,
4837 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
4838 .serdes_power = mv88e6390_serdes_power,
4839 .serdes_get_lane = mv88e6390_serdes_get_lane,
4840 /* Check status register pause & lpa register */
4841 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
4842 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
4843 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
4844 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
4845 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
4846 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
4847 .serdes_irq_status = mv88e6390_serdes_irq_status,
4848 .serdes_get_strings = mv88e6390_serdes_get_strings,
4849 .serdes_get_stats = mv88e6390_serdes_get_stats,
4850 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
4851 .serdes_get_regs = mv88e6390_serdes_get_regs,
4852 .avb_ops = &mv88e6390_avb_ops,
4853 .ptp_ops = &mv88e6352_ptp_ops,
4854 .phylink_get_caps = mv88e6390_phylink_get_caps,
4855};
4856
4857static const struct mv88e6xxx_ops mv88e6240_ops = {
4858 /* MV88E6XXX_FAMILY_6352 */
4859 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
4860 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4861 .irl_init_all = mv88e6352_g2_irl_init_all,
4862 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4863 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4864 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4865 .phy_read = mv88e6xxx_g2_smi_phy_read,
4866 .phy_write = mv88e6xxx_g2_smi_phy_write,
4867 .port_set_link = mv88e6xxx_port_set_link,
4868 .port_sync_link = mv88e6xxx_port_sync_link,
4869 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4870 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
4871 .port_tag_remap = mv88e6095_port_tag_remap,
4872 .port_set_policy = mv88e6352_port_set_policy,
4873 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4874 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4875 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4876 .port_set_ether_type = mv88e6351_port_set_ether_type,
4877 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
4878 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4879 .port_pause_limit = mv88e6097_port_pause_limit,
4880 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4881 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4882 .port_get_cmode = mv88e6352_port_get_cmode,
4883 .port_setup_message_port = mv88e6xxx_setup_message_port,
4884 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4885 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4886 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
4887 .stats_get_strings = mv88e6095_stats_get_strings,
4888 .stats_get_stats = mv88e6095_stats_get_stats,
4889 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4890 .set_egress_port = mv88e6095_g1_set_egress_port,
4891 .watchdog_ops = &mv88e6097_watchdog_ops,
4892 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4893 .pot_clear = mv88e6xxx_g2_pot_clear,
4894 .reset = mv88e6352_g1_reset,
4895 .rmu_disable = mv88e6352_g1_rmu_disable,
4896 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4897 .atu_set_hash = mv88e6165_g1_atu_set_hash,
4898 .vtu_getnext = mv88e6352_g1_vtu_getnext,
4899 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
4900 .stu_getnext = mv88e6352_g1_stu_getnext,
4901 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
4902 .serdes_get_lane = mv88e6352_serdes_get_lane,
4903 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
4904 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
4905 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
4906 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
4907 .serdes_power = mv88e6352_serdes_power,
4908 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
4909 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
4910 .serdes_irq_status = mv88e6352_serdes_irq_status,
4911 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
4912 .serdes_get_regs = mv88e6352_serdes_get_regs,
4913 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
4914 .gpio_ops = &mv88e6352_gpio_ops,
4915 .avb_ops = &mv88e6352_avb_ops,
4916 .ptp_ops = &mv88e6352_ptp_ops,
4917 .phylink_get_caps = mv88e6352_phylink_get_caps,
4918};
4919
4920static const struct mv88e6xxx_ops mv88e6250_ops = {
4921 /* MV88E6XXX_FAMILY_6250 */
4922 .ieee_pri_map = mv88e6250_g1_ieee_pri_map,
4923 .ip_pri_map = mv88e6085_g1_ip_pri_map,
4924 .irl_init_all = mv88e6352_g2_irl_init_all,
4925 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
4926 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
4927 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4928 .phy_read = mv88e6xxx_g2_smi_phy_read,
4929 .phy_write = mv88e6xxx_g2_smi_phy_write,
4930 .port_set_link = mv88e6xxx_port_set_link,
4931 .port_sync_link = mv88e6xxx_port_sync_link,
4932 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
4933 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex,
4934 .port_tag_remap = mv88e6095_port_tag_remap,
4935 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4936 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4937 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4938 .port_set_ether_type = mv88e6351_port_set_ether_type,
4939 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
4940 .port_pause_limit = mv88e6097_port_pause_limit,
4941 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4942 .stats_snapshot = mv88e6320_g1_stats_snapshot,
4943 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
4944 .stats_get_sset_count = mv88e6250_stats_get_sset_count,
4945 .stats_get_strings = mv88e6250_stats_get_strings,
4946 .stats_get_stats = mv88e6250_stats_get_stats,
4947 .set_cpu_port = mv88e6095_g1_set_cpu_port,
4948 .set_egress_port = mv88e6095_g1_set_egress_port,
4949 .watchdog_ops = &mv88e6250_watchdog_ops,
4950 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
4951 .pot_clear = mv88e6xxx_g2_pot_clear,
4952 .reset = mv88e6250_g1_reset,
4953 .vtu_getnext = mv88e6185_g1_vtu_getnext,
4954 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
4955 .avb_ops = &mv88e6352_avb_ops,
4956 .ptp_ops = &mv88e6250_ptp_ops,
4957 .phylink_get_caps = mv88e6250_phylink_get_caps,
4958};
4959
4960static const struct mv88e6xxx_ops mv88e6290_ops = {
4961 /* MV88E6XXX_FAMILY_6390 */
4962 .setup_errata = mv88e6390_setup_errata,
4963 .irl_init_all = mv88e6390_g2_irl_init_all,
4964 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
4965 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
4966 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
4967 .phy_read = mv88e6xxx_g2_smi_phy_read,
4968 .phy_write = mv88e6xxx_g2_smi_phy_write,
4969 .port_set_link = mv88e6xxx_port_set_link,
4970 .port_sync_link = mv88e6xxx_port_sync_link,
4971 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
4972 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
4973 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
4974 .port_tag_remap = mv88e6390_port_tag_remap,
4975 .port_set_policy = mv88e6352_port_set_policy,
4976 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
4977 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
4978 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
4979 .port_set_ether_type = mv88e6351_port_set_ether_type,
4980 .port_pause_limit = mv88e6390_port_pause_limit,
4981 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
4982 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
4983 .port_get_cmode = mv88e6352_port_get_cmode,
4984 .port_set_cmode = mv88e6390_port_set_cmode,
4985 .port_setup_message_port = mv88e6xxx_setup_message_port,
4986 .stats_snapshot = mv88e6390_g1_stats_snapshot,
4987 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
4988 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
4989 .stats_get_strings = mv88e6320_stats_get_strings,
4990 .stats_get_stats = mv88e6390_stats_get_stats,
4991 .set_cpu_port = mv88e6390_g1_set_cpu_port,
4992 .set_egress_port = mv88e6390_g1_set_egress_port,
4993 .watchdog_ops = &mv88e6390_watchdog_ops,
4994 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
4995 .pot_clear = mv88e6xxx_g2_pot_clear,
4996 .reset = mv88e6352_g1_reset,
4997 .rmu_disable = mv88e6390_g1_rmu_disable,
4998 .atu_get_hash = mv88e6165_g1_atu_get_hash,
4999 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5000 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5001 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5002 .stu_getnext = mv88e6390_g1_stu_getnext,
5003 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5004 .serdes_power = mv88e6390_serdes_power,
5005 .serdes_get_lane = mv88e6390_serdes_get_lane,
5006 /* Check status register pause & lpa register */
5007 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5008 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5009 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5010 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5011 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5012 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5013 .serdes_irq_status = mv88e6390_serdes_irq_status,
5014 .serdes_get_strings = mv88e6390_serdes_get_strings,
5015 .serdes_get_stats = mv88e6390_serdes_get_stats,
5016 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5017 .serdes_get_regs = mv88e6390_serdes_get_regs,
5018 .gpio_ops = &mv88e6352_gpio_ops,
5019 .avb_ops = &mv88e6390_avb_ops,
5020 .ptp_ops = &mv88e6352_ptp_ops,
5021 .phylink_get_caps = mv88e6390_phylink_get_caps,
5022};
5023
5024static const struct mv88e6xxx_ops mv88e6320_ops = {
5025 /* MV88E6XXX_FAMILY_6320 */
5026 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5027 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5028 .irl_init_all = mv88e6352_g2_irl_init_all,
5029 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5030 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5031 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5032 .phy_read = mv88e6xxx_g2_smi_phy_read,
5033 .phy_write = mv88e6xxx_g2_smi_phy_write,
5034 .port_set_link = mv88e6xxx_port_set_link,
5035 .port_sync_link = mv88e6xxx_port_sync_link,
5036 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5037 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5038 .port_tag_remap = mv88e6095_port_tag_remap,
5039 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5040 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5041 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5042 .port_set_ether_type = mv88e6351_port_set_ether_type,
5043 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5044 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5045 .port_pause_limit = mv88e6097_port_pause_limit,
5046 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5047 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5048 .port_get_cmode = mv88e6352_port_get_cmode,
5049 .port_setup_message_port = mv88e6xxx_setup_message_port,
5050 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5051 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5052 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5053 .stats_get_strings = mv88e6320_stats_get_strings,
5054 .stats_get_stats = mv88e6320_stats_get_stats,
5055 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5056 .set_egress_port = mv88e6095_g1_set_egress_port,
5057 .watchdog_ops = &mv88e6390_watchdog_ops,
5058 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5059 .pot_clear = mv88e6xxx_g2_pot_clear,
5060 .reset = mv88e6352_g1_reset,
5061 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5062 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5063 .gpio_ops = &mv88e6352_gpio_ops,
5064 .avb_ops = &mv88e6352_avb_ops,
5065 .ptp_ops = &mv88e6352_ptp_ops,
5066 .phylink_get_caps = mv88e6185_phylink_get_caps,
5067};
5068
5069static const struct mv88e6xxx_ops mv88e6321_ops = {
5070 /* MV88E6XXX_FAMILY_6320 */
5071 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5072 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5073 .irl_init_all = mv88e6352_g2_irl_init_all,
5074 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5075 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5076 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5077 .phy_read = mv88e6xxx_g2_smi_phy_read,
5078 .phy_write = mv88e6xxx_g2_smi_phy_write,
5079 .port_set_link = mv88e6xxx_port_set_link,
5080 .port_sync_link = mv88e6xxx_port_sync_link,
5081 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay,
5082 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5083 .port_tag_remap = mv88e6095_port_tag_remap,
5084 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5085 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5086 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5087 .port_set_ether_type = mv88e6351_port_set_ether_type,
5088 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5089 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5090 .port_pause_limit = mv88e6097_port_pause_limit,
5091 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5092 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5093 .port_get_cmode = mv88e6352_port_get_cmode,
5094 .port_setup_message_port = mv88e6xxx_setup_message_port,
5095 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5096 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5097 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5098 .stats_get_strings = mv88e6320_stats_get_strings,
5099 .stats_get_stats = mv88e6320_stats_get_stats,
5100 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5101 .set_egress_port = mv88e6095_g1_set_egress_port,
5102 .watchdog_ops = &mv88e6390_watchdog_ops,
5103 .reset = mv88e6352_g1_reset,
5104 .vtu_getnext = mv88e6185_g1_vtu_getnext,
5105 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
5106 .gpio_ops = &mv88e6352_gpio_ops,
5107 .avb_ops = &mv88e6352_avb_ops,
5108 .ptp_ops = &mv88e6352_ptp_ops,
5109 .phylink_get_caps = mv88e6185_phylink_get_caps,
5110};
5111
5112static const struct mv88e6xxx_ops mv88e6341_ops = {
5113 /* MV88E6XXX_FAMILY_6341 */
5114 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5115 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5116 .irl_init_all = mv88e6352_g2_irl_init_all,
5117 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5118 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5119 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5120 .phy_read = mv88e6xxx_g2_smi_phy_read,
5121 .phy_write = mv88e6xxx_g2_smi_phy_write,
5122 .port_set_link = mv88e6xxx_port_set_link,
5123 .port_sync_link = mv88e6xxx_port_sync_link,
5124 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5125 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex,
5126 .port_max_speed_mode = mv88e6341_port_max_speed_mode,
5127 .port_tag_remap = mv88e6095_port_tag_remap,
5128 .port_set_policy = mv88e6352_port_set_policy,
5129 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5130 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5131 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5132 .port_set_ether_type = mv88e6351_port_set_ether_type,
5133 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5134 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5135 .port_pause_limit = mv88e6097_port_pause_limit,
5136 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5137 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5138 .port_get_cmode = mv88e6352_port_get_cmode,
5139 .port_set_cmode = mv88e6341_port_set_cmode,
5140 .port_setup_message_port = mv88e6xxx_setup_message_port,
5141 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5142 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5143 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5144 .stats_get_strings = mv88e6320_stats_get_strings,
5145 .stats_get_stats = mv88e6390_stats_get_stats,
5146 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5147 .set_egress_port = mv88e6390_g1_set_egress_port,
5148 .watchdog_ops = &mv88e6390_watchdog_ops,
5149 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5150 .pot_clear = mv88e6xxx_g2_pot_clear,
5151 .reset = mv88e6352_g1_reset,
5152 .rmu_disable = mv88e6390_g1_rmu_disable,
5153 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5154 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5155 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5156 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5157 .stu_getnext = mv88e6352_g1_stu_getnext,
5158 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5159 .serdes_power = mv88e6390_serdes_power,
5160 .serdes_get_lane = mv88e6341_serdes_get_lane,
5161 /* Check status register pause & lpa register */
5162 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5163 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5164 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5165 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5166 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5167 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5168 .serdes_irq_status = mv88e6390_serdes_irq_status,
5169 .gpio_ops = &mv88e6352_gpio_ops,
5170 .avb_ops = &mv88e6390_avb_ops,
5171 .ptp_ops = &mv88e6352_ptp_ops,
5172 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5173 .serdes_get_strings = mv88e6390_serdes_get_strings,
5174 .serdes_get_stats = mv88e6390_serdes_get_stats,
5175 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5176 .serdes_get_regs = mv88e6390_serdes_get_regs,
5177 .phylink_get_caps = mv88e6341_phylink_get_caps,
5178};
5179
5180static const struct mv88e6xxx_ops mv88e6350_ops = {
5181 /* MV88E6XXX_FAMILY_6351 */
5182 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5183 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5184 .irl_init_all = mv88e6352_g2_irl_init_all,
5185 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5186 .phy_read = mv88e6xxx_g2_smi_phy_read,
5187 .phy_write = mv88e6xxx_g2_smi_phy_write,
5188 .port_set_link = mv88e6xxx_port_set_link,
5189 .port_sync_link = mv88e6xxx_port_sync_link,
5190 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5191 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5192 .port_tag_remap = mv88e6095_port_tag_remap,
5193 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5194 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5195 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5196 .port_set_ether_type = mv88e6351_port_set_ether_type,
5197 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5198 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5199 .port_pause_limit = mv88e6097_port_pause_limit,
5200 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5201 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5202 .port_get_cmode = mv88e6352_port_get_cmode,
5203 .port_setup_message_port = mv88e6xxx_setup_message_port,
5204 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5205 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5206 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5207 .stats_get_strings = mv88e6095_stats_get_strings,
5208 .stats_get_stats = mv88e6095_stats_get_stats,
5209 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5210 .set_egress_port = mv88e6095_g1_set_egress_port,
5211 .watchdog_ops = &mv88e6097_watchdog_ops,
5212 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5213 .pot_clear = mv88e6xxx_g2_pot_clear,
5214 .reset = mv88e6352_g1_reset,
5215 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5216 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5217 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5218 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5219 .stu_getnext = mv88e6352_g1_stu_getnext,
5220 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5221 .phylink_get_caps = mv88e6185_phylink_get_caps,
5222};
5223
5224static const struct mv88e6xxx_ops mv88e6351_ops = {
5225 /* MV88E6XXX_FAMILY_6351 */
5226 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5227 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5228 .irl_init_all = mv88e6352_g2_irl_init_all,
5229 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5230 .phy_read = mv88e6xxx_g2_smi_phy_read,
5231 .phy_write = mv88e6xxx_g2_smi_phy_write,
5232 .port_set_link = mv88e6xxx_port_set_link,
5233 .port_sync_link = mv88e6xxx_port_sync_link,
5234 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5235 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex,
5236 .port_tag_remap = mv88e6095_port_tag_remap,
5237 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5238 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5239 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5240 .port_set_ether_type = mv88e6351_port_set_ether_type,
5241 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5242 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5243 .port_pause_limit = mv88e6097_port_pause_limit,
5244 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5245 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5246 .port_get_cmode = mv88e6352_port_get_cmode,
5247 .port_setup_message_port = mv88e6xxx_setup_message_port,
5248 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5249 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5250 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5251 .stats_get_strings = mv88e6095_stats_get_strings,
5252 .stats_get_stats = mv88e6095_stats_get_stats,
5253 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5254 .set_egress_port = mv88e6095_g1_set_egress_port,
5255 .watchdog_ops = &mv88e6097_watchdog_ops,
5256 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5257 .pot_clear = mv88e6xxx_g2_pot_clear,
5258 .reset = mv88e6352_g1_reset,
5259 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5260 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5261 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5262 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5263 .stu_getnext = mv88e6352_g1_stu_getnext,
5264 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5265 .avb_ops = &mv88e6352_avb_ops,
5266 .ptp_ops = &mv88e6352_ptp_ops,
5267 .phylink_get_caps = mv88e6185_phylink_get_caps,
5268};
5269
5270static const struct mv88e6xxx_ops mv88e6352_ops = {
5271 /* MV88E6XXX_FAMILY_6352 */
5272 .ieee_pri_map = mv88e6085_g1_ieee_pri_map,
5273 .ip_pri_map = mv88e6085_g1_ip_pri_map,
5274 .irl_init_all = mv88e6352_g2_irl_init_all,
5275 .get_eeprom = mv88e6xxx_g2_get_eeprom16,
5276 .set_eeprom = mv88e6xxx_g2_set_eeprom16,
5277 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5278 .phy_read = mv88e6xxx_g2_smi_phy_read,
5279 .phy_write = mv88e6xxx_g2_smi_phy_write,
5280 .port_set_link = mv88e6xxx_port_set_link,
5281 .port_sync_link = mv88e6xxx_port_sync_link,
5282 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
5283 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex,
5284 .port_tag_remap = mv88e6095_port_tag_remap,
5285 .port_set_policy = mv88e6352_port_set_policy,
5286 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5287 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5288 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5289 .port_set_ether_type = mv88e6351_port_set_ether_type,
5290 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5291 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5292 .port_pause_limit = mv88e6097_port_pause_limit,
5293 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5294 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5295 .port_get_cmode = mv88e6352_port_get_cmode,
5296 .port_setup_message_port = mv88e6xxx_setup_message_port,
5297 .stats_snapshot = mv88e6320_g1_stats_snapshot,
5298 .stats_set_histogram = mv88e6095_g1_stats_set_histogram,
5299 .stats_get_sset_count = mv88e6095_stats_get_sset_count,
5300 .stats_get_strings = mv88e6095_stats_get_strings,
5301 .stats_get_stats = mv88e6095_stats_get_stats,
5302 .set_cpu_port = mv88e6095_g1_set_cpu_port,
5303 .set_egress_port = mv88e6095_g1_set_egress_port,
5304 .watchdog_ops = &mv88e6097_watchdog_ops,
5305 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
5306 .pot_clear = mv88e6xxx_g2_pot_clear,
5307 .reset = mv88e6352_g1_reset,
5308 .rmu_disable = mv88e6352_g1_rmu_disable,
5309 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5310 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5311 .vtu_getnext = mv88e6352_g1_vtu_getnext,
5312 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
5313 .stu_getnext = mv88e6352_g1_stu_getnext,
5314 .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
5315 .serdes_get_lane = mv88e6352_serdes_get_lane,
5316 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
5317 .serdes_pcs_config = mv88e6352_serdes_pcs_config,
5318 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart,
5319 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up,
5320 .serdes_power = mv88e6352_serdes_power,
5321 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping,
5322 .serdes_irq_enable = mv88e6352_serdes_irq_enable,
5323 .serdes_irq_status = mv88e6352_serdes_irq_status,
5324 .gpio_ops = &mv88e6352_gpio_ops,
5325 .avb_ops = &mv88e6352_avb_ops,
5326 .ptp_ops = &mv88e6352_ptp_ops,
5327 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
5328 .serdes_get_strings = mv88e6352_serdes_get_strings,
5329 .serdes_get_stats = mv88e6352_serdes_get_stats,
5330 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len,
5331 .serdes_get_regs = mv88e6352_serdes_get_regs,
5332 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude,
5333 .phylink_get_caps = mv88e6352_phylink_get_caps,
5334};
5335
5336static const struct mv88e6xxx_ops mv88e6390_ops = {
5337 /* MV88E6XXX_FAMILY_6390 */
5338 .setup_errata = mv88e6390_setup_errata,
5339 .irl_init_all = mv88e6390_g2_irl_init_all,
5340 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5341 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5342 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5343 .phy_read = mv88e6xxx_g2_smi_phy_read,
5344 .phy_write = mv88e6xxx_g2_smi_phy_write,
5345 .port_set_link = mv88e6xxx_port_set_link,
5346 .port_sync_link = mv88e6xxx_port_sync_link,
5347 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5348 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex,
5349 .port_max_speed_mode = mv88e6390_port_max_speed_mode,
5350 .port_tag_remap = mv88e6390_port_tag_remap,
5351 .port_set_policy = mv88e6352_port_set_policy,
5352 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5353 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5354 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5355 .port_set_ether_type = mv88e6351_port_set_ether_type,
5356 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5357 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5358 .port_pause_limit = mv88e6390_port_pause_limit,
5359 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5360 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5361 .port_get_cmode = mv88e6352_port_get_cmode,
5362 .port_set_cmode = mv88e6390_port_set_cmode,
5363 .port_setup_message_port = mv88e6xxx_setup_message_port,
5364 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5365 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5366 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5367 .stats_get_strings = mv88e6320_stats_get_strings,
5368 .stats_get_stats = mv88e6390_stats_get_stats,
5369 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5370 .set_egress_port = mv88e6390_g1_set_egress_port,
5371 .watchdog_ops = &mv88e6390_watchdog_ops,
5372 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5373 .pot_clear = mv88e6xxx_g2_pot_clear,
5374 .reset = mv88e6352_g1_reset,
5375 .rmu_disable = mv88e6390_g1_rmu_disable,
5376 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5377 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5378 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5379 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5380 .stu_getnext = mv88e6390_g1_stu_getnext,
5381 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5382 .serdes_power = mv88e6390_serdes_power,
5383 .serdes_get_lane = mv88e6390_serdes_get_lane,
5384 /* Check status register pause & lpa register */
5385 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5386 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5387 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5388 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5389 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5390 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5391 .serdes_irq_status = mv88e6390_serdes_irq_status,
5392 .gpio_ops = &mv88e6352_gpio_ops,
5393 .avb_ops = &mv88e6390_avb_ops,
5394 .ptp_ops = &mv88e6352_ptp_ops,
5395 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5396 .serdes_get_strings = mv88e6390_serdes_get_strings,
5397 .serdes_get_stats = mv88e6390_serdes_get_stats,
5398 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5399 .serdes_get_regs = mv88e6390_serdes_get_regs,
5400 .phylink_get_caps = mv88e6390_phylink_get_caps,
5401};
5402
5403static const struct mv88e6xxx_ops mv88e6390x_ops = {
5404 /* MV88E6XXX_FAMILY_6390 */
5405 .setup_errata = mv88e6390_setup_errata,
5406 .irl_init_all = mv88e6390_g2_irl_init_all,
5407 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5408 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5409 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5410 .phy_read = mv88e6xxx_g2_smi_phy_read,
5411 .phy_write = mv88e6xxx_g2_smi_phy_write,
5412 .port_set_link = mv88e6xxx_port_set_link,
5413 .port_sync_link = mv88e6xxx_port_sync_link,
5414 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5415 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex,
5416 .port_max_speed_mode = mv88e6390x_port_max_speed_mode,
5417 .port_tag_remap = mv88e6390_port_tag_remap,
5418 .port_set_policy = mv88e6352_port_set_policy,
5419 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5420 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5421 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5422 .port_set_ether_type = mv88e6351_port_set_ether_type,
5423 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5424 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5425 .port_pause_limit = mv88e6390_port_pause_limit,
5426 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5427 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5428 .port_get_cmode = mv88e6352_port_get_cmode,
5429 .port_set_cmode = mv88e6390x_port_set_cmode,
5430 .port_setup_message_port = mv88e6xxx_setup_message_port,
5431 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5432 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5433 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5434 .stats_get_strings = mv88e6320_stats_get_strings,
5435 .stats_get_stats = mv88e6390_stats_get_stats,
5436 .set_cpu_port = mv88e6390_g1_set_cpu_port,
5437 .set_egress_port = mv88e6390_g1_set_egress_port,
5438 .watchdog_ops = &mv88e6390_watchdog_ops,
5439 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
5440 .pot_clear = mv88e6xxx_g2_pot_clear,
5441 .reset = mv88e6352_g1_reset,
5442 .rmu_disable = mv88e6390_g1_rmu_disable,
5443 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5444 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5445 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5446 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5447 .stu_getnext = mv88e6390_g1_stu_getnext,
5448 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5449 .serdes_power = mv88e6390_serdes_power,
5450 .serdes_get_lane = mv88e6390x_serdes_get_lane,
5451 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state,
5452 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5453 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5454 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5455 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5456 .serdes_irq_enable = mv88e6390_serdes_irq_enable,
5457 .serdes_irq_status = mv88e6390_serdes_irq_status,
5458 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count,
5459 .serdes_get_strings = mv88e6390_serdes_get_strings,
5460 .serdes_get_stats = mv88e6390_serdes_get_stats,
5461 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len,
5462 .serdes_get_regs = mv88e6390_serdes_get_regs,
5463 .gpio_ops = &mv88e6352_gpio_ops,
5464 .avb_ops = &mv88e6390_avb_ops,
5465 .ptp_ops = &mv88e6352_ptp_ops,
5466 .phylink_get_caps = mv88e6390x_phylink_get_caps,
5467};
5468
5469static const struct mv88e6xxx_ops mv88e6393x_ops = {
5470 /* MV88E6XXX_FAMILY_6393 */
5471 .setup_errata = mv88e6393x_serdes_setup_errata,
5472 .irl_init_all = mv88e6390_g2_irl_init_all,
5473 .get_eeprom = mv88e6xxx_g2_get_eeprom8,
5474 .set_eeprom = mv88e6xxx_g2_set_eeprom8,
5475 .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
5476 .phy_read = mv88e6xxx_g2_smi_phy_read,
5477 .phy_write = mv88e6xxx_g2_smi_phy_write,
5478 .port_set_link = mv88e6xxx_port_set_link,
5479 .port_sync_link = mv88e6xxx_port_sync_link,
5480 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
5481 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,
5482 .port_max_speed_mode = mv88e6393x_port_max_speed_mode,
5483 .port_tag_remap = mv88e6390_port_tag_remap,
5484 .port_set_policy = mv88e6393x_port_set_policy,
5485 .port_set_frame_mode = mv88e6351_port_set_frame_mode,
5486 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood,
5487 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood,
5488 .port_set_ether_type = mv88e6393x_port_set_ether_type,
5489 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
5490 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
5491 .port_pause_limit = mv88e6390_port_pause_limit,
5492 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
5493 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
5494 .port_get_cmode = mv88e6352_port_get_cmode,
5495 .port_set_cmode = mv88e6393x_port_set_cmode,
5496 .port_setup_message_port = mv88e6xxx_setup_message_port,
5497 .port_set_upstream_port = mv88e6393x_port_set_upstream_port,
5498 .stats_snapshot = mv88e6390_g1_stats_snapshot,
5499 .stats_set_histogram = mv88e6390_g1_stats_set_histogram,
5500 .stats_get_sset_count = mv88e6320_stats_get_sset_count,
5501 .stats_get_strings = mv88e6320_stats_get_strings,
5502 .stats_get_stats = mv88e6390_stats_get_stats,
5503 /* .set_cpu_port is missing because this family does not support a global
5504 * CPU port, only per port CPU port which is set via
5505 * .port_set_upstream_port method.
5506 */
5507 .set_egress_port = mv88e6393x_set_egress_port,
5508 .watchdog_ops = &mv88e6390_watchdog_ops,
5509 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,
5510 .pot_clear = mv88e6xxx_g2_pot_clear,
5511 .reset = mv88e6352_g1_reset,
5512 .rmu_disable = mv88e6390_g1_rmu_disable,
5513 .atu_get_hash = mv88e6165_g1_atu_get_hash,
5514 .atu_set_hash = mv88e6165_g1_atu_set_hash,
5515 .vtu_getnext = mv88e6390_g1_vtu_getnext,
5516 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
5517 .stu_getnext = mv88e6390_g1_stu_getnext,
5518 .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
5519 .serdes_power = mv88e6393x_serdes_power,
5520 .serdes_get_lane = mv88e6393x_serdes_get_lane,
5521 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,
5522 .serdes_pcs_config = mv88e6390_serdes_pcs_config,
5523 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,
5524 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,
5525 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping,
5526 .serdes_irq_enable = mv88e6393x_serdes_irq_enable,
5527 .serdes_irq_status = mv88e6393x_serdes_irq_status,
5528 /* TODO: serdes stats */
5529 .gpio_ops = &mv88e6352_gpio_ops,
5530 .avb_ops = &mv88e6390_avb_ops,
5531 .ptp_ops = &mv88e6352_ptp_ops,
5532 .phylink_get_caps = mv88e6393x_phylink_get_caps,
5533};
5534
5535static const struct mv88e6xxx_info mv88e6xxx_table[] = {
5536 [MV88E6085] = {
5537 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
5538 .family = MV88E6XXX_FAMILY_6097,
5539 .name = "Marvell 88E6085",
5540 .num_databases = 4096,
5541 .num_macs = 8192,
5542 .num_ports = 10,
5543 .num_internal_phys = 5,
5544 .max_vid = 4095,
5545 .max_sid = 63,
5546 .port_base_addr = 0x10,
5547 .phy_base_addr = 0x0,
5548 .global1_addr = 0x1b,
5549 .global2_addr = 0x1c,
5550 .age_time_coeff = 15000,
5551 .g1_irqs = 8,
5552 .g2_irqs = 10,
5553 .atu_move_port_mask = 0xf,
5554 .pvt = true,
5555 .multi_chip = true,
5556 .ops = &mv88e6085_ops,
5557 },
5558
5559 [MV88E6095] = {
5560 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
5561 .family = MV88E6XXX_FAMILY_6095,
5562 .name = "Marvell 88E6095/88E6095F",
5563 .num_databases = 256,
5564 .num_macs = 8192,
5565 .num_ports = 11,
5566 .num_internal_phys = 0,
5567 .max_vid = 4095,
5568 .port_base_addr = 0x10,
5569 .phy_base_addr = 0x0,
5570 .global1_addr = 0x1b,
5571 .global2_addr = 0x1c,
5572 .age_time_coeff = 15000,
5573 .g1_irqs = 8,
5574 .atu_move_port_mask = 0xf,
5575 .multi_chip = true,
5576 .ops = &mv88e6095_ops,
5577 },
5578
5579 [MV88E6097] = {
5580 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
5581 .family = MV88E6XXX_FAMILY_6097,
5582 .name = "Marvell 88E6097/88E6097F",
5583 .num_databases = 4096,
5584 .num_macs = 8192,
5585 .num_ports = 11,
5586 .num_internal_phys = 8,
5587 .max_vid = 4095,
5588 .max_sid = 63,
5589 .port_base_addr = 0x10,
5590 .phy_base_addr = 0x0,
5591 .global1_addr = 0x1b,
5592 .global2_addr = 0x1c,
5593 .age_time_coeff = 15000,
5594 .g1_irqs = 8,
5595 .g2_irqs = 10,
5596 .atu_move_port_mask = 0xf,
5597 .pvt = true,
5598 .multi_chip = true,
5599 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5600 .ops = &mv88e6097_ops,
5601 },
5602
5603 [MV88E6123] = {
5604 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
5605 .family = MV88E6XXX_FAMILY_6165,
5606 .name = "Marvell 88E6123",
5607 .num_databases = 4096,
5608 .num_macs = 1024,
5609 .num_ports = 3,
5610 .num_internal_phys = 5,
5611 .max_vid = 4095,
5612 .max_sid = 63,
5613 .port_base_addr = 0x10,
5614 .phy_base_addr = 0x0,
5615 .global1_addr = 0x1b,
5616 .global2_addr = 0x1c,
5617 .age_time_coeff = 15000,
5618 .g1_irqs = 9,
5619 .g2_irqs = 10,
5620 .atu_move_port_mask = 0xf,
5621 .pvt = true,
5622 .multi_chip = true,
5623 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5624 .ops = &mv88e6123_ops,
5625 },
5626
5627 [MV88E6131] = {
5628 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
5629 .family = MV88E6XXX_FAMILY_6185,
5630 .name = "Marvell 88E6131",
5631 .num_databases = 256,
5632 .num_macs = 8192,
5633 .num_ports = 8,
5634 .num_internal_phys = 0,
5635 .max_vid = 4095,
5636 .port_base_addr = 0x10,
5637 .phy_base_addr = 0x0,
5638 .global1_addr = 0x1b,
5639 .global2_addr = 0x1c,
5640 .age_time_coeff = 15000,
5641 .g1_irqs = 9,
5642 .atu_move_port_mask = 0xf,
5643 .multi_chip = true,
5644 .ops = &mv88e6131_ops,
5645 },
5646
5647 [MV88E6141] = {
5648 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
5649 .family = MV88E6XXX_FAMILY_6341,
5650 .name = "Marvell 88E6141",
5651 .num_databases = 4096,
5652 .num_macs = 2048,
5653 .num_ports = 6,
5654 .num_internal_phys = 5,
5655 .num_gpio = 11,
5656 .max_vid = 4095,
5657 .max_sid = 63,
5658 .port_base_addr = 0x10,
5659 .phy_base_addr = 0x10,
5660 .global1_addr = 0x1b,
5661 .global2_addr = 0x1c,
5662 .age_time_coeff = 3750,
5663 .atu_move_port_mask = 0x1f,
5664 .g1_irqs = 9,
5665 .g2_irqs = 10,
5666 .pvt = true,
5667 .multi_chip = true,
5668 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5669 .ops = &mv88e6141_ops,
5670 },
5671
5672 [MV88E6161] = {
5673 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
5674 .family = MV88E6XXX_FAMILY_6165,
5675 .name = "Marvell 88E6161",
5676 .num_databases = 4096,
5677 .num_macs = 1024,
5678 .num_ports = 6,
5679 .num_internal_phys = 5,
5680 .max_vid = 4095,
5681 .max_sid = 63,
5682 .port_base_addr = 0x10,
5683 .phy_base_addr = 0x0,
5684 .global1_addr = 0x1b,
5685 .global2_addr = 0x1c,
5686 .age_time_coeff = 15000,
5687 .g1_irqs = 9,
5688 .g2_irqs = 10,
5689 .atu_move_port_mask = 0xf,
5690 .pvt = true,
5691 .multi_chip = true,
5692 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5693 .ptp_support = true,
5694 .ops = &mv88e6161_ops,
5695 },
5696
5697 [MV88E6165] = {
5698 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
5699 .family = MV88E6XXX_FAMILY_6165,
5700 .name = "Marvell 88E6165",
5701 .num_databases = 4096,
5702 .num_macs = 8192,
5703 .num_ports = 6,
5704 .num_internal_phys = 0,
5705 .max_vid = 4095,
5706 .max_sid = 63,
5707 .port_base_addr = 0x10,
5708 .phy_base_addr = 0x0,
5709 .global1_addr = 0x1b,
5710 .global2_addr = 0x1c,
5711 .age_time_coeff = 15000,
5712 .g1_irqs = 9,
5713 .g2_irqs = 10,
5714 .atu_move_port_mask = 0xf,
5715 .pvt = true,
5716 .multi_chip = true,
5717 .ptp_support = true,
5718 .ops = &mv88e6165_ops,
5719 },
5720
5721 [MV88E6171] = {
5722 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
5723 .family = MV88E6XXX_FAMILY_6351,
5724 .name = "Marvell 88E6171",
5725 .num_databases = 4096,
5726 .num_macs = 8192,
5727 .num_ports = 7,
5728 .num_internal_phys = 5,
5729 .max_vid = 4095,
5730 .max_sid = 63,
5731 .port_base_addr = 0x10,
5732 .phy_base_addr = 0x0,
5733 .global1_addr = 0x1b,
5734 .global2_addr = 0x1c,
5735 .age_time_coeff = 15000,
5736 .g1_irqs = 9,
5737 .g2_irqs = 10,
5738 .atu_move_port_mask = 0xf,
5739 .pvt = true,
5740 .multi_chip = true,
5741 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5742 .ops = &mv88e6171_ops,
5743 },
5744
5745 [MV88E6172] = {
5746 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
5747 .family = MV88E6XXX_FAMILY_6352,
5748 .name = "Marvell 88E6172",
5749 .num_databases = 4096,
5750 .num_macs = 8192,
5751 .num_ports = 7,
5752 .num_internal_phys = 5,
5753 .num_gpio = 15,
5754 .max_vid = 4095,
5755 .max_sid = 63,
5756 .port_base_addr = 0x10,
5757 .phy_base_addr = 0x0,
5758 .global1_addr = 0x1b,
5759 .global2_addr = 0x1c,
5760 .age_time_coeff = 15000,
5761 .g1_irqs = 9,
5762 .g2_irqs = 10,
5763 .atu_move_port_mask = 0xf,
5764 .pvt = true,
5765 .multi_chip = true,
5766 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5767 .ops = &mv88e6172_ops,
5768 },
5769
5770 [MV88E6175] = {
5771 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
5772 .family = MV88E6XXX_FAMILY_6351,
5773 .name = "Marvell 88E6175",
5774 .num_databases = 4096,
5775 .num_macs = 8192,
5776 .num_ports = 7,
5777 .num_internal_phys = 5,
5778 .max_vid = 4095,
5779 .max_sid = 63,
5780 .port_base_addr = 0x10,
5781 .phy_base_addr = 0x0,
5782 .global1_addr = 0x1b,
5783 .global2_addr = 0x1c,
5784 .age_time_coeff = 15000,
5785 .g1_irqs = 9,
5786 .g2_irqs = 10,
5787 .atu_move_port_mask = 0xf,
5788 .pvt = true,
5789 .multi_chip = true,
5790 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5791 .ops = &mv88e6175_ops,
5792 },
5793
5794 [MV88E6176] = {
5795 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
5796 .family = MV88E6XXX_FAMILY_6352,
5797 .name = "Marvell 88E6176",
5798 .num_databases = 4096,
5799 .num_macs = 8192,
5800 .num_ports = 7,
5801 .num_internal_phys = 5,
5802 .num_gpio = 15,
5803 .max_vid = 4095,
5804 .max_sid = 63,
5805 .port_base_addr = 0x10,
5806 .phy_base_addr = 0x0,
5807 .global1_addr = 0x1b,
5808 .global2_addr = 0x1c,
5809 .age_time_coeff = 15000,
5810 .g1_irqs = 9,
5811 .g2_irqs = 10,
5812 .atu_move_port_mask = 0xf,
5813 .pvt = true,
5814 .multi_chip = true,
5815 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5816 .ops = &mv88e6176_ops,
5817 },
5818
5819 [MV88E6185] = {
5820 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
5821 .family = MV88E6XXX_FAMILY_6185,
5822 .name = "Marvell 88E6185",
5823 .num_databases = 256,
5824 .num_macs = 8192,
5825 .num_ports = 10,
5826 .num_internal_phys = 0,
5827 .max_vid = 4095,
5828 .port_base_addr = 0x10,
5829 .phy_base_addr = 0x0,
5830 .global1_addr = 0x1b,
5831 .global2_addr = 0x1c,
5832 .age_time_coeff = 15000,
5833 .g1_irqs = 8,
5834 .atu_move_port_mask = 0xf,
5835 .multi_chip = true,
5836 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
5837 .ops = &mv88e6185_ops,
5838 },
5839
5840 [MV88E6190] = {
5841 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
5842 .family = MV88E6XXX_FAMILY_6390,
5843 .name = "Marvell 88E6190",
5844 .num_databases = 4096,
5845 .num_macs = 16384,
5846 .num_ports = 11, /* 10 + Z80 */
5847 .num_internal_phys = 9,
5848 .num_gpio = 16,
5849 .max_vid = 8191,
5850 .max_sid = 63,
5851 .port_base_addr = 0x0,
5852 .phy_base_addr = 0x0,
5853 .global1_addr = 0x1b,
5854 .global2_addr = 0x1c,
5855 .age_time_coeff = 3750,
5856 .g1_irqs = 9,
5857 .g2_irqs = 14,
5858 .pvt = true,
5859 .multi_chip = true,
5860 .atu_move_port_mask = 0x1f,
5861 .ops = &mv88e6190_ops,
5862 },
5863
5864 [MV88E6190X] = {
5865 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
5866 .family = MV88E6XXX_FAMILY_6390,
5867 .name = "Marvell 88E6190X",
5868 .num_databases = 4096,
5869 .num_macs = 16384,
5870 .num_ports = 11, /* 10 + Z80 */
5871 .num_internal_phys = 9,
5872 .num_gpio = 16,
5873 .max_vid = 8191,
5874 .max_sid = 63,
5875 .port_base_addr = 0x0,
5876 .phy_base_addr = 0x0,
5877 .global1_addr = 0x1b,
5878 .global2_addr = 0x1c,
5879 .age_time_coeff = 3750,
5880 .g1_irqs = 9,
5881 .g2_irqs = 14,
5882 .atu_move_port_mask = 0x1f,
5883 .pvt = true,
5884 .multi_chip = true,
5885 .ops = &mv88e6190x_ops,
5886 },
5887
5888 [MV88E6191] = {
5889 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
5890 .family = MV88E6XXX_FAMILY_6390,
5891 .name = "Marvell 88E6191",
5892 .num_databases = 4096,
5893 .num_macs = 16384,
5894 .num_ports = 11, /* 10 + Z80 */
5895 .num_internal_phys = 9,
5896 .max_vid = 8191,
5897 .max_sid = 63,
5898 .port_base_addr = 0x0,
5899 .phy_base_addr = 0x0,
5900 .global1_addr = 0x1b,
5901 .global2_addr = 0x1c,
5902 .age_time_coeff = 3750,
5903 .g1_irqs = 9,
5904 .g2_irqs = 14,
5905 .atu_move_port_mask = 0x1f,
5906 .pvt = true,
5907 .multi_chip = true,
5908 .ptp_support = true,
5909 .ops = &mv88e6191_ops,
5910 },
5911
5912 [MV88E6191X] = {
5913 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,
5914 .family = MV88E6XXX_FAMILY_6393,
5915 .name = "Marvell 88E6191X",
5916 .num_databases = 4096,
5917 .num_ports = 11, /* 10 + Z80 */
5918 .num_internal_phys = 9,
5919 .max_vid = 8191,
5920 .max_sid = 63,
5921 .port_base_addr = 0x0,
5922 .phy_base_addr = 0x0,
5923 .global1_addr = 0x1b,
5924 .global2_addr = 0x1c,
5925 .age_time_coeff = 3750,
5926 .g1_irqs = 10,
5927 .g2_irqs = 14,
5928 .atu_move_port_mask = 0x1f,
5929 .pvt = true,
5930 .multi_chip = true,
5931 .ptp_support = true,
5932 .ops = &mv88e6393x_ops,
5933 },
5934
5935 [MV88E6193X] = {
5936 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,
5937 .family = MV88E6XXX_FAMILY_6393,
5938 .name = "Marvell 88E6193X",
5939 .num_databases = 4096,
5940 .num_ports = 11, /* 10 + Z80 */
5941 .num_internal_phys = 9,
5942 .max_vid = 8191,
5943 .max_sid = 63,
5944 .port_base_addr = 0x0,
5945 .phy_base_addr = 0x0,
5946 .global1_addr = 0x1b,
5947 .global2_addr = 0x1c,
5948 .age_time_coeff = 3750,
5949 .g1_irqs = 10,
5950 .g2_irqs = 14,
5951 .atu_move_port_mask = 0x1f,
5952 .pvt = true,
5953 .multi_chip = true,
5954 .ptp_support = true,
5955 .ops = &mv88e6393x_ops,
5956 },
5957
5958 [MV88E6220] = {
5959 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,
5960 .family = MV88E6XXX_FAMILY_6250,
5961 .name = "Marvell 88E6220",
5962 .num_databases = 64,
5963
5964 /* Ports 2-4 are not routed to pins
5965 * => usable ports 0, 1, 5, 6
5966 */
5967 .num_ports = 7,
5968 .num_internal_phys = 2,
5969 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4),
5970 .max_vid = 4095,
5971 .port_base_addr = 0x08,
5972 .phy_base_addr = 0x00,
5973 .global1_addr = 0x0f,
5974 .global2_addr = 0x07,
5975 .age_time_coeff = 15000,
5976 .g1_irqs = 9,
5977 .g2_irqs = 10,
5978 .atu_move_port_mask = 0xf,
5979 .dual_chip = true,
5980 .ptp_support = true,
5981 .ops = &mv88e6250_ops,
5982 },
5983
5984 [MV88E6240] = {
5985 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
5986 .family = MV88E6XXX_FAMILY_6352,
5987 .name = "Marvell 88E6240",
5988 .num_databases = 4096,
5989 .num_macs = 8192,
5990 .num_ports = 7,
5991 .num_internal_phys = 5,
5992 .num_gpio = 15,
5993 .max_vid = 4095,
5994 .max_sid = 63,
5995 .port_base_addr = 0x10,
5996 .phy_base_addr = 0x0,
5997 .global1_addr = 0x1b,
5998 .global2_addr = 0x1c,
5999 .age_time_coeff = 15000,
6000 .g1_irqs = 9,
6001 .g2_irqs = 10,
6002 .atu_move_port_mask = 0xf,
6003 .pvt = true,
6004 .multi_chip = true,
6005 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6006 .ptp_support = true,
6007 .ops = &mv88e6240_ops,
6008 },
6009
6010 [MV88E6250] = {
6011 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250,
6012 .family = MV88E6XXX_FAMILY_6250,
6013 .name = "Marvell 88E6250",
6014 .num_databases = 64,
6015 .num_ports = 7,
6016 .num_internal_phys = 5,
6017 .max_vid = 4095,
6018 .port_base_addr = 0x08,
6019 .phy_base_addr = 0x00,
6020 .global1_addr = 0x0f,
6021 .global2_addr = 0x07,
6022 .age_time_coeff = 15000,
6023 .g1_irqs = 9,
6024 .g2_irqs = 10,
6025 .atu_move_port_mask = 0xf,
6026 .dual_chip = true,
6027 .ptp_support = true,
6028 .ops = &mv88e6250_ops,
6029 },
6030
6031 [MV88E6290] = {
6032 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
6033 .family = MV88E6XXX_FAMILY_6390,
6034 .name = "Marvell 88E6290",
6035 .num_databases = 4096,
6036 .num_ports = 11, /* 10 + Z80 */
6037 .num_internal_phys = 9,
6038 .num_gpio = 16,
6039 .max_vid = 8191,
6040 .max_sid = 63,
6041 .port_base_addr = 0x0,
6042 .phy_base_addr = 0x0,
6043 .global1_addr = 0x1b,
6044 .global2_addr = 0x1c,
6045 .age_time_coeff = 3750,
6046 .g1_irqs = 9,
6047 .g2_irqs = 14,
6048 .atu_move_port_mask = 0x1f,
6049 .pvt = true,
6050 .multi_chip = true,
6051 .ptp_support = true,
6052 .ops = &mv88e6290_ops,
6053 },
6054
6055 [MV88E6320] = {
6056 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
6057 .family = MV88E6XXX_FAMILY_6320,
6058 .name = "Marvell 88E6320",
6059 .num_databases = 4096,
6060 .num_macs = 8192,
6061 .num_ports = 7,
6062 .num_internal_phys = 5,
6063 .num_gpio = 15,
6064 .max_vid = 4095,
6065 .port_base_addr = 0x10,
6066 .phy_base_addr = 0x0,
6067 .global1_addr = 0x1b,
6068 .global2_addr = 0x1c,
6069 .age_time_coeff = 15000,
6070 .g1_irqs = 8,
6071 .g2_irqs = 10,
6072 .atu_move_port_mask = 0xf,
6073 .pvt = true,
6074 .multi_chip = true,
6075 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6076 .ptp_support = true,
6077 .ops = &mv88e6320_ops,
6078 },
6079
6080 [MV88E6321] = {
6081 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
6082 .family = MV88E6XXX_FAMILY_6320,
6083 .name = "Marvell 88E6321",
6084 .num_databases = 4096,
6085 .num_macs = 8192,
6086 .num_ports = 7,
6087 .num_internal_phys = 5,
6088 .num_gpio = 15,
6089 .max_vid = 4095,
6090 .port_base_addr = 0x10,
6091 .phy_base_addr = 0x0,
6092 .global1_addr = 0x1b,
6093 .global2_addr = 0x1c,
6094 .age_time_coeff = 15000,
6095 .g1_irqs = 8,
6096 .g2_irqs = 10,
6097 .atu_move_port_mask = 0xf,
6098 .multi_chip = true,
6099 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6100 .ptp_support = true,
6101 .ops = &mv88e6321_ops,
6102 },
6103
6104 [MV88E6341] = {
6105 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
6106 .family = MV88E6XXX_FAMILY_6341,
6107 .name = "Marvell 88E6341",
6108 .num_databases = 4096,
6109 .num_macs = 2048,
6110 .num_internal_phys = 5,
6111 .num_ports = 6,
6112 .num_gpio = 11,
6113 .max_vid = 4095,
6114 .max_sid = 63,
6115 .port_base_addr = 0x10,
6116 .phy_base_addr = 0x10,
6117 .global1_addr = 0x1b,
6118 .global2_addr = 0x1c,
6119 .age_time_coeff = 3750,
6120 .atu_move_port_mask = 0x1f,
6121 .g1_irqs = 9,
6122 .g2_irqs = 10,
6123 .pvt = true,
6124 .multi_chip = true,
6125 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6126 .ptp_support = true,
6127 .ops = &mv88e6341_ops,
6128 },
6129
6130 [MV88E6350] = {
6131 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
6132 .family = MV88E6XXX_FAMILY_6351,
6133 .name = "Marvell 88E6350",
6134 .num_databases = 4096,
6135 .num_macs = 8192,
6136 .num_ports = 7,
6137 .num_internal_phys = 5,
6138 .max_vid = 4095,
6139 .max_sid = 63,
6140 .port_base_addr = 0x10,
6141 .phy_base_addr = 0x0,
6142 .global1_addr = 0x1b,
6143 .global2_addr = 0x1c,
6144 .age_time_coeff = 15000,
6145 .g1_irqs = 9,
6146 .g2_irqs = 10,
6147 .atu_move_port_mask = 0xf,
6148 .pvt = true,
6149 .multi_chip = true,
6150 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6151 .ops = &mv88e6350_ops,
6152 },
6153
6154 [MV88E6351] = {
6155 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
6156 .family = MV88E6XXX_FAMILY_6351,
6157 .name = "Marvell 88E6351",
6158 .num_databases = 4096,
6159 .num_macs = 8192,
6160 .num_ports = 7,
6161 .num_internal_phys = 5,
6162 .max_vid = 4095,
6163 .max_sid = 63,
6164 .port_base_addr = 0x10,
6165 .phy_base_addr = 0x0,
6166 .global1_addr = 0x1b,
6167 .global2_addr = 0x1c,
6168 .age_time_coeff = 15000,
6169 .g1_irqs = 9,
6170 .g2_irqs = 10,
6171 .atu_move_port_mask = 0xf,
6172 .pvt = true,
6173 .multi_chip = true,
6174 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6175 .ops = &mv88e6351_ops,
6176 },
6177
6178 [MV88E6352] = {
6179 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
6180 .family = MV88E6XXX_FAMILY_6352,
6181 .name = "Marvell 88E6352",
6182 .num_databases = 4096,
6183 .num_macs = 8192,
6184 .num_ports = 7,
6185 .num_internal_phys = 5,
6186 .num_gpio = 15,
6187 .max_vid = 4095,
6188 .max_sid = 63,
6189 .port_base_addr = 0x10,
6190 .phy_base_addr = 0x0,
6191 .global1_addr = 0x1b,
6192 .global2_addr = 0x1c,
6193 .age_time_coeff = 15000,
6194 .g1_irqs = 9,
6195 .g2_irqs = 10,
6196 .atu_move_port_mask = 0xf,
6197 .pvt = true,
6198 .multi_chip = true,
6199 .edsa_support = MV88E6XXX_EDSA_SUPPORTED,
6200 .ptp_support = true,
6201 .ops = &mv88e6352_ops,
6202 },
6203 [MV88E6390] = {
6204 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
6205 .family = MV88E6XXX_FAMILY_6390,
6206 .name = "Marvell 88E6390",
6207 .num_databases = 4096,
6208 .num_macs = 16384,
6209 .num_ports = 11, /* 10 + Z80 */
6210 .num_internal_phys = 9,
6211 .num_gpio = 16,
6212 .max_vid = 8191,
6213 .max_sid = 63,
6214 .port_base_addr = 0x0,
6215 .phy_base_addr = 0x0,
6216 .global1_addr = 0x1b,
6217 .global2_addr = 0x1c,
6218 .age_time_coeff = 3750,
6219 .g1_irqs = 9,
6220 .g2_irqs = 14,
6221 .atu_move_port_mask = 0x1f,
6222 .pvt = true,
6223 .multi_chip = true,
6224 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6225 .ptp_support = true,
6226 .ops = &mv88e6390_ops,
6227 },
6228 [MV88E6390X] = {
6229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
6230 .family = MV88E6XXX_FAMILY_6390,
6231 .name = "Marvell 88E6390X",
6232 .num_databases = 4096,
6233 .num_macs = 16384,
6234 .num_ports = 11, /* 10 + Z80 */
6235 .num_internal_phys = 9,
6236 .num_gpio = 16,
6237 .max_vid = 8191,
6238 .max_sid = 63,
6239 .port_base_addr = 0x0,
6240 .phy_base_addr = 0x0,
6241 .global1_addr = 0x1b,
6242 .global2_addr = 0x1c,
6243 .age_time_coeff = 3750,
6244 .g1_irqs = 9,
6245 .g2_irqs = 14,
6246 .atu_move_port_mask = 0x1f,
6247 .pvt = true,
6248 .multi_chip = true,
6249 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED,
6250 .ptp_support = true,
6251 .ops = &mv88e6390x_ops,
6252 },
6253
6254 [MV88E6393X] = {
6255 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,
6256 .family = MV88E6XXX_FAMILY_6393,
6257 .name = "Marvell 88E6393X",
6258 .num_databases = 4096,
6259 .num_ports = 11, /* 10 + Z80 */
6260 .num_internal_phys = 9,
6261 .max_vid = 8191,
6262 .max_sid = 63,
6263 .port_base_addr = 0x0,
6264 .phy_base_addr = 0x0,
6265 .global1_addr = 0x1b,
6266 .global2_addr = 0x1c,
6267 .age_time_coeff = 3750,
6268 .g1_irqs = 10,
6269 .g2_irqs = 14,
6270 .atu_move_port_mask = 0x1f,
6271 .pvt = true,
6272 .multi_chip = true,
6273 .ptp_support = true,
6274 .ops = &mv88e6393x_ops,
6275 },
6276};
6277
6278static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
6279{
6280 int i;
6281
6282 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
6283 if (mv88e6xxx_table[i].prod_num == prod_num)
6284 return &mv88e6xxx_table[i];
6285
6286 return NULL;
6287}
6288
6289static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
6290{
6291 const struct mv88e6xxx_info *info;
6292 unsigned int prod_num, rev;
6293 u16 id;
6294 int err;
6295
6296 mv88e6xxx_reg_lock(chip);
6297 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
6298 mv88e6xxx_reg_unlock(chip);
6299 if (err)
6300 return err;
6301
6302 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
6303 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
6304
6305 info = mv88e6xxx_lookup_info(prod_num);
6306 if (!info)
6307 return -ENODEV;
6308
6309 /* Update the compatible info with the probed one */
6310 chip->info = info;
6311
6312 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
6313 chip->info->prod_num, chip->info->name, rev);
6314
6315 return 0;
6316}
6317
6318static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip,
6319 struct mdio_device *mdiodev)
6320{
6321 int err;
6322
6323 /* dual_chip takes precedence over single/multi-chip modes */
6324 if (chip->info->dual_chip)
6325 return -EINVAL;
6326
6327 /* If the mdio addr is 16 indicating the first port address of a switch
6328 * (e.g. mv88e6*41) in single chip addressing mode the device may be
6329 * configured in single chip addressing mode. Setup the smi access as
6330 * single chip addressing mode and attempt to detect the model of the
6331 * switch, if this fails the device is not configured in single chip
6332 * addressing mode.
6333 */
6334 if (mdiodev->addr != 16)
6335 return -EINVAL;
6336
6337 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0);
6338 if (err)
6339 return err;
6340
6341 return mv88e6xxx_detect(chip);
6342}
6343
6344static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
6345{
6346 struct mv88e6xxx_chip *chip;
6347
6348 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
6349 if (!chip)
6350 return NULL;
6351
6352 chip->dev = dev;
6353
6354 mutex_init(&chip->reg_lock);
6355 INIT_LIST_HEAD(&chip->mdios);
6356 idr_init(&chip->policies);
6357 INIT_LIST_HEAD(&chip->msts);
6358
6359 return chip;
6360}
6361
6362static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
6363 int port,
6364 enum dsa_tag_protocol m)
6365{
6366 struct mv88e6xxx_chip *chip = ds->priv;
6367
6368 return chip->tag_protocol;
6369}
6370
6371static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds,
6372 enum dsa_tag_protocol proto)
6373{
6374 struct mv88e6xxx_chip *chip = ds->priv;
6375 enum dsa_tag_protocol old_protocol;
6376 struct dsa_port *cpu_dp;
6377 int err;
6378
6379 switch (proto) {
6380 case DSA_TAG_PROTO_EDSA:
6381 switch (chip->info->edsa_support) {
6382 case MV88E6XXX_EDSA_UNSUPPORTED:
6383 return -EPROTONOSUPPORT;
6384 case MV88E6XXX_EDSA_UNDOCUMENTED:
6385 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n");
6386 fallthrough;
6387 case MV88E6XXX_EDSA_SUPPORTED:
6388 break;
6389 }
6390 break;
6391 case DSA_TAG_PROTO_DSA:
6392 break;
6393 default:
6394 return -EPROTONOSUPPORT;
6395 }
6396
6397 old_protocol = chip->tag_protocol;
6398 chip->tag_protocol = proto;
6399
6400 mv88e6xxx_reg_lock(chip);
6401 dsa_switch_for_each_cpu_port(cpu_dp, ds) {
6402 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6403 if (err) {
6404 mv88e6xxx_reg_unlock(chip);
6405 goto unwind;
6406 }
6407 }
6408 mv88e6xxx_reg_unlock(chip);
6409
6410 return 0;
6411
6412unwind:
6413 chip->tag_protocol = old_protocol;
6414
6415 mv88e6xxx_reg_lock(chip);
6416 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds)
6417 mv88e6xxx_setup_port_mode(chip, cpu_dp->index);
6418 mv88e6xxx_reg_unlock(chip);
6419
6420 return err;
6421}
6422
6423static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
6424 const struct switchdev_obj_port_mdb *mdb,
6425 struct dsa_db db)
6426{
6427 struct mv88e6xxx_chip *chip = ds->priv;
6428 int err;
6429
6430 mv88e6xxx_reg_lock(chip);
6431 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
6432 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC);
6433 mv88e6xxx_reg_unlock(chip);
6434
6435 return err;
6436}
6437
6438static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
6439 const struct switchdev_obj_port_mdb *mdb,
6440 struct dsa_db db)
6441{
6442 struct mv88e6xxx_chip *chip = ds->priv;
6443 int err;
6444
6445 mv88e6xxx_reg_lock(chip);
6446 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0);
6447 mv88e6xxx_reg_unlock(chip);
6448
6449 return err;
6450}
6451
6452static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port,
6453 struct dsa_mall_mirror_tc_entry *mirror,
6454 bool ingress,
6455 struct netlink_ext_ack *extack)
6456{
6457 enum mv88e6xxx_egress_direction direction = ingress ?
6458 MV88E6XXX_EGRESS_DIR_INGRESS :
6459 MV88E6XXX_EGRESS_DIR_EGRESS;
6460 struct mv88e6xxx_chip *chip = ds->priv;
6461 bool other_mirrors = false;
6462 int i;
6463 int err;
6464
6465 mutex_lock(&chip->reg_lock);
6466 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=
6467 mirror->to_local_port) {
6468 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6469 other_mirrors |= ingress ?
6470 chip->ports[i].mirror_ingress :
6471 chip->ports[i].mirror_egress;
6472
6473 /* Can't change egress port when other mirror is active */
6474 if (other_mirrors) {
6475 err = -EBUSY;
6476 goto out;
6477 }
6478
6479 err = mv88e6xxx_set_egress_port(chip, direction,
6480 mirror->to_local_port);
6481 if (err)
6482 goto out;
6483 }
6484
6485 err = mv88e6xxx_port_set_mirror(chip, port, direction, true);
6486out:
6487 mutex_unlock(&chip->reg_lock);
6488
6489 return err;
6490}
6491
6492static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port,
6493 struct dsa_mall_mirror_tc_entry *mirror)
6494{
6495 enum mv88e6xxx_egress_direction direction = mirror->ingress ?
6496 MV88E6XXX_EGRESS_DIR_INGRESS :
6497 MV88E6XXX_EGRESS_DIR_EGRESS;
6498 struct mv88e6xxx_chip *chip = ds->priv;
6499 bool other_mirrors = false;
6500 int i;
6501
6502 mutex_lock(&chip->reg_lock);
6503 if (mv88e6xxx_port_set_mirror(chip, port, direction, false))
6504 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port);
6505
6506 for (i = 0; i < mv88e6xxx_num_ports(chip); i++)
6507 other_mirrors |= mirror->ingress ?
6508 chip->ports[i].mirror_ingress :
6509 chip->ports[i].mirror_egress;
6510
6511 /* Reset egress port when no other mirror is active */
6512 if (!other_mirrors) {
6513 if (mv88e6xxx_set_egress_port(chip, direction,
6514 dsa_upstream_port(ds, port)))
6515 dev_err(ds->dev, "failed to set egress port\n");
6516 }
6517
6518 mutex_unlock(&chip->reg_lock);
6519}
6520
6521static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port,
6522 struct switchdev_brport_flags flags,
6523 struct netlink_ext_ack *extack)
6524{
6525 struct mv88e6xxx_chip *chip = ds->priv;
6526 const struct mv88e6xxx_ops *ops;
6527
6528 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
6529 BR_BCAST_FLOOD | BR_PORT_LOCKED))
6530 return -EINVAL;
6531
6532 ops = chip->info->ops;
6533
6534 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood)
6535 return -EINVAL;
6536
6537 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood)
6538 return -EINVAL;
6539
6540 return 0;
6541}
6542
6543static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port,
6544 struct switchdev_brport_flags flags,
6545 struct netlink_ext_ack *extack)
6546{
6547 struct mv88e6xxx_chip *chip = ds->priv;
6548 int err = -EOPNOTSUPP;
6549
6550 mv88e6xxx_reg_lock(chip);
6551
6552 if (flags.mask & BR_LEARNING) {
6553 bool learning = !!(flags.val & BR_LEARNING);
6554 u16 pav = learning ? (1 << port) : 0;
6555
6556 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav);
6557 if (err)
6558 goto out;
6559 }
6560
6561 if (flags.mask & BR_FLOOD) {
6562 bool unicast = !!(flags.val & BR_FLOOD);
6563
6564 err = chip->info->ops->port_set_ucast_flood(chip, port,
6565 unicast);
6566 if (err)
6567 goto out;
6568 }
6569
6570 if (flags.mask & BR_MCAST_FLOOD) {
6571 bool multicast = !!(flags.val & BR_MCAST_FLOOD);
6572
6573 err = chip->info->ops->port_set_mcast_flood(chip, port,
6574 multicast);
6575 if (err)
6576 goto out;
6577 }
6578
6579 if (flags.mask & BR_BCAST_FLOOD) {
6580 bool broadcast = !!(flags.val & BR_BCAST_FLOOD);
6581
6582 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast);
6583 if (err)
6584 goto out;
6585 }
6586
6587 if (flags.mask & BR_PORT_LOCKED) {
6588 bool locked = !!(flags.val & BR_PORT_LOCKED);
6589
6590 err = mv88e6xxx_port_set_lock(chip, port, locked);
6591 if (err)
6592 goto out;
6593 }
6594out:
6595 mv88e6xxx_reg_unlock(chip);
6596
6597 return err;
6598}
6599
6600static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds,
6601 struct dsa_lag lag,
6602 struct netdev_lag_upper_info *info,
6603 struct netlink_ext_ack *extack)
6604{
6605 struct mv88e6xxx_chip *chip = ds->priv;
6606 struct dsa_port *dp;
6607 int members = 0;
6608
6609 if (!mv88e6xxx_has_lag(chip)) {
6610 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload");
6611 return false;
6612 }
6613
6614 if (!lag.id)
6615 return false;
6616
6617 dsa_lag_foreach_port(dp, ds->dst, &lag)
6618 /* Includes the port joining the LAG */
6619 members++;
6620
6621 if (members > 8) {
6622 NL_SET_ERR_MSG_MOD(extack,
6623 "Cannot offload more than 8 LAG ports");
6624 return false;
6625 }
6626
6627 /* We could potentially relax this to include active
6628 * backup in the future.
6629 */
6630 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
6631 NL_SET_ERR_MSG_MOD(extack,
6632 "Can only offload LAG using hash TX type");
6633 return false;
6634 }
6635
6636 /* Ideally we would also validate that the hash type matches
6637 * the hardware. Alas, this is always set to unknown on team
6638 * interfaces.
6639 */
6640 return true;
6641}
6642
6643static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag)
6644{
6645 struct mv88e6xxx_chip *chip = ds->priv;
6646 struct dsa_port *dp;
6647 u16 map = 0;
6648 int id;
6649
6650 /* DSA LAG IDs are one-based, hardware is zero-based */
6651 id = lag.id - 1;
6652
6653 /* Build the map of all ports to distribute flows destined for
6654 * this LAG. This can be either a local user port, or a DSA
6655 * port if the LAG port is on a remote chip.
6656 */
6657 dsa_lag_foreach_port(dp, ds->dst, &lag)
6658 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index));
6659
6660 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map);
6661}
6662
6663static const u8 mv88e6xxx_lag_mask_table[8][8] = {
6664 /* Row number corresponds to the number of active members in a
6665 * LAG. Each column states which of the eight hash buckets are
6666 * mapped to the column:th port in the LAG.
6667 *
6668 * Example: In a LAG with three active ports, the second port
6669 * ([2][1]) would be selected for traffic mapped to buckets
6670 * 3,4,5 (0x38).
6671 */
6672 { 0xff, 0, 0, 0, 0, 0, 0, 0 },
6673 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 },
6674 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 },
6675 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 },
6676 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 },
6677 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 },
6678 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 },
6679 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 },
6680};
6681
6682static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port,
6683 int num_tx, int nth)
6684{
6685 u8 active = 0;
6686 int i;
6687
6688 num_tx = num_tx <= 8 ? num_tx : 8;
6689 if (nth < num_tx)
6690 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth];
6691
6692 for (i = 0; i < 8; i++) {
6693 if (BIT(i) & active)
6694 mask[i] |= BIT(port);
6695 }
6696}
6697
6698static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds)
6699{
6700 struct mv88e6xxx_chip *chip = ds->priv;
6701 unsigned int id, num_tx;
6702 struct dsa_port *dp;
6703 struct dsa_lag *lag;
6704 int i, err, nth;
6705 u16 mask[8];
6706 u16 ivec;
6707
6708 /* Assume no port is a member of any LAG. */
6709 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1;
6710
6711 /* Disable all masks for ports that _are_ members of a LAG. */
6712 dsa_switch_for_each_port(dp, ds) {
6713 if (!dp->lag)
6714 continue;
6715
6716 ivec &= ~BIT(dp->index);
6717 }
6718
6719 for (i = 0; i < 8; i++)
6720 mask[i] = ivec;
6721
6722 /* Enable the correct subset of masks for all LAG ports that
6723 * are in the Tx set.
6724 */
6725 dsa_lags_foreach_id(id, ds->dst) {
6726 lag = dsa_lag_by_id(ds->dst, id);
6727 if (!lag)
6728 continue;
6729
6730 num_tx = 0;
6731 dsa_lag_foreach_port(dp, ds->dst, lag) {
6732 if (dp->lag_tx_enabled)
6733 num_tx++;
6734 }
6735
6736 if (!num_tx)
6737 continue;
6738
6739 nth = 0;
6740 dsa_lag_foreach_port(dp, ds->dst, lag) {
6741 if (!dp->lag_tx_enabled)
6742 continue;
6743
6744 if (dp->ds == ds)
6745 mv88e6xxx_lag_set_port_mask(mask, dp->index,
6746 num_tx, nth);
6747
6748 nth++;
6749 }
6750 }
6751
6752 for (i = 0; i < 8; i++) {
6753 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]);
6754 if (err)
6755 return err;
6756 }
6757
6758 return 0;
6759}
6760
6761static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds,
6762 struct dsa_lag lag)
6763{
6764 int err;
6765
6766 err = mv88e6xxx_lag_sync_masks(ds);
6767
6768 if (!err)
6769 err = mv88e6xxx_lag_sync_map(ds, lag);
6770
6771 return err;
6772}
6773
6774static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port)
6775{
6776 struct mv88e6xxx_chip *chip = ds->priv;
6777 int err;
6778
6779 mv88e6xxx_reg_lock(chip);
6780 err = mv88e6xxx_lag_sync_masks(ds);
6781 mv88e6xxx_reg_unlock(chip);
6782 return err;
6783}
6784
6785static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port,
6786 struct dsa_lag lag,
6787 struct netdev_lag_upper_info *info,
6788 struct netlink_ext_ack *extack)
6789{
6790 struct mv88e6xxx_chip *chip = ds->priv;
6791 int err, id;
6792
6793 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6794 return -EOPNOTSUPP;
6795
6796 /* DSA LAG IDs are one-based */
6797 id = lag.id - 1;
6798
6799 mv88e6xxx_reg_lock(chip);
6800
6801 err = mv88e6xxx_port_set_trunk(chip, port, true, id);
6802 if (err)
6803 goto err_unlock;
6804
6805 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6806 if (err)
6807 goto err_clear_trunk;
6808
6809 mv88e6xxx_reg_unlock(chip);
6810 return 0;
6811
6812err_clear_trunk:
6813 mv88e6xxx_port_set_trunk(chip, port, false, 0);
6814err_unlock:
6815 mv88e6xxx_reg_unlock(chip);
6816 return err;
6817}
6818
6819static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port,
6820 struct dsa_lag lag)
6821{
6822 struct mv88e6xxx_chip *chip = ds->priv;
6823 int err_sync, err_trunk;
6824
6825 mv88e6xxx_reg_lock(chip);
6826 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6827 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0);
6828 mv88e6xxx_reg_unlock(chip);
6829 return err_sync ? : err_trunk;
6830}
6831
6832static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index,
6833 int port)
6834{
6835 struct mv88e6xxx_chip *chip = ds->priv;
6836 int err;
6837
6838 mv88e6xxx_reg_lock(chip);
6839 err = mv88e6xxx_lag_sync_masks(ds);
6840 mv88e6xxx_reg_unlock(chip);
6841 return err;
6842}
6843
6844static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index,
6845 int port, struct dsa_lag lag,
6846 struct netdev_lag_upper_info *info,
6847 struct netlink_ext_ack *extack)
6848{
6849 struct mv88e6xxx_chip *chip = ds->priv;
6850 int err;
6851
6852 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack))
6853 return -EOPNOTSUPP;
6854
6855 mv88e6xxx_reg_lock(chip);
6856
6857 err = mv88e6xxx_lag_sync_masks_map(ds, lag);
6858 if (err)
6859 goto unlock;
6860
6861 err = mv88e6xxx_pvt_map(chip, sw_index, port);
6862
6863unlock:
6864 mv88e6xxx_reg_unlock(chip);
6865 return err;
6866}
6867
6868static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index,
6869 int port, struct dsa_lag lag)
6870{
6871 struct mv88e6xxx_chip *chip = ds->priv;
6872 int err_sync, err_pvt;
6873
6874 mv88e6xxx_reg_lock(chip);
6875 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag);
6876 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port);
6877 mv88e6xxx_reg_unlock(chip);
6878 return err_sync ? : err_pvt;
6879}
6880
6881static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
6882 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
6883 .change_tag_protocol = mv88e6xxx_change_tag_protocol,
6884 .setup = mv88e6xxx_setup,
6885 .teardown = mv88e6xxx_teardown,
6886 .port_setup = mv88e6xxx_port_setup,
6887 .port_teardown = mv88e6xxx_port_teardown,
6888 .phylink_get_caps = mv88e6xxx_get_caps,
6889 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state,
6890 .phylink_mac_config = mv88e6xxx_mac_config,
6891 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart,
6892 .phylink_mac_link_down = mv88e6xxx_mac_link_down,
6893 .phylink_mac_link_up = mv88e6xxx_mac_link_up,
6894 .get_strings = mv88e6xxx_get_strings,
6895 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
6896 .get_sset_count = mv88e6xxx_get_sset_count,
6897 .port_enable = mv88e6xxx_port_enable,
6898 .port_disable = mv88e6xxx_port_disable,
6899 .port_max_mtu = mv88e6xxx_get_max_mtu,
6900 .port_change_mtu = mv88e6xxx_change_mtu,
6901 .get_mac_eee = mv88e6xxx_get_mac_eee,
6902 .set_mac_eee = mv88e6xxx_set_mac_eee,
6903 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
6904 .get_eeprom = mv88e6xxx_get_eeprom,
6905 .set_eeprom = mv88e6xxx_set_eeprom,
6906 .get_regs_len = mv88e6xxx_get_regs_len,
6907 .get_regs = mv88e6xxx_get_regs,
6908 .get_rxnfc = mv88e6xxx_get_rxnfc,
6909 .set_rxnfc = mv88e6xxx_set_rxnfc,
6910 .set_ageing_time = mv88e6xxx_set_ageing_time,
6911 .port_bridge_join = mv88e6xxx_port_bridge_join,
6912 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
6913 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags,
6914 .port_bridge_flags = mv88e6xxx_port_bridge_flags,
6915 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
6916 .port_mst_state_set = mv88e6xxx_port_mst_state_set,
6917 .port_fast_age = mv88e6xxx_port_fast_age,
6918 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age,
6919 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
6920 .port_vlan_add = mv88e6xxx_port_vlan_add,
6921 .port_vlan_del = mv88e6xxx_port_vlan_del,
6922 .vlan_msti_set = mv88e6xxx_vlan_msti_set,
6923 .port_fdb_add = mv88e6xxx_port_fdb_add,
6924 .port_fdb_del = mv88e6xxx_port_fdb_del,
6925 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
6926 .port_mdb_add = mv88e6xxx_port_mdb_add,
6927 .port_mdb_del = mv88e6xxx_port_mdb_del,
6928 .port_mirror_add = mv88e6xxx_port_mirror_add,
6929 .port_mirror_del = mv88e6xxx_port_mirror_del,
6930 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join,
6931 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave,
6932 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set,
6933 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get,
6934 .port_txtstamp = mv88e6xxx_port_txtstamp,
6935 .port_rxtstamp = mv88e6xxx_port_rxtstamp,
6936 .get_ts_info = mv88e6xxx_get_ts_info,
6937 .devlink_param_get = mv88e6xxx_devlink_param_get,
6938 .devlink_param_set = mv88e6xxx_devlink_param_set,
6939 .devlink_info_get = mv88e6xxx_devlink_info_get,
6940 .port_lag_change = mv88e6xxx_port_lag_change,
6941 .port_lag_join = mv88e6xxx_port_lag_join,
6942 .port_lag_leave = mv88e6xxx_port_lag_leave,
6943 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change,
6944 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join,
6945 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave,
6946};
6947
6948static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
6949{
6950 struct device *dev = chip->dev;
6951 struct dsa_switch *ds;
6952
6953 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
6954 if (!ds)
6955 return -ENOMEM;
6956
6957 ds->dev = dev;
6958 ds->num_ports = mv88e6xxx_num_ports(chip);
6959 ds->priv = chip;
6960 ds->dev = dev;
6961 ds->ops = &mv88e6xxx_switch_ops;
6962 ds->ageing_time_min = chip->info->age_time_coeff;
6963 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
6964
6965 /* Some chips support up to 32, but that requires enabling the
6966 * 5-bit port mode, which we do not support. 640k^W16 ought to
6967 * be enough for anyone.
6968 */
6969 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0;
6970
6971 dev_set_drvdata(dev, ds);
6972
6973 return dsa_register_switch(ds);
6974}
6975
6976static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
6977{
6978 dsa_unregister_switch(chip->ds);
6979}
6980
6981static const void *pdata_device_get_match_data(struct device *dev)
6982{
6983 const struct of_device_id *matches = dev->driver->of_match_table;
6984 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
6985
6986 for (; matches->name[0] || matches->type[0] || matches->compatible[0];
6987 matches++) {
6988 if (!strcmp(pdata->compatible, matches->compatible))
6989 return matches->data;
6990 }
6991 return NULL;
6992}
6993
6994/* There is no suspend to RAM support at DSA level yet, the switch configuration
6995 * would be lost after a power cycle so prevent it to be suspended.
6996 */
6997static int __maybe_unused mv88e6xxx_suspend(struct device *dev)
6998{
6999 return -EOPNOTSUPP;
7000}
7001
7002static int __maybe_unused mv88e6xxx_resume(struct device *dev)
7003{
7004 return 0;
7005}
7006
7007static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume);
7008
7009static int mv88e6xxx_probe(struct mdio_device *mdiodev)
7010{
7011 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
7012 const struct mv88e6xxx_info *compat_info = NULL;
7013 struct device *dev = &mdiodev->dev;
7014 struct device_node *np = dev->of_node;
7015 struct mv88e6xxx_chip *chip;
7016 int port;
7017 int err;
7018
7019 if (!np && !pdata)
7020 return -EINVAL;
7021
7022 if (np)
7023 compat_info = of_device_get_match_data(dev);
7024
7025 if (pdata) {
7026 compat_info = pdata_device_get_match_data(dev);
7027
7028 if (!pdata->netdev)
7029 return -EINVAL;
7030
7031 for (port = 0; port < DSA_MAX_PORTS; port++) {
7032 if (!(pdata->enabled_ports & (1 << port)))
7033 continue;
7034 if (strcmp(pdata->cd.port_names[port], "cpu"))
7035 continue;
7036 pdata->cd.netdev[port] = &pdata->netdev->dev;
7037 break;
7038 }
7039 }
7040
7041 if (!compat_info)
7042 return -EINVAL;
7043
7044 chip = mv88e6xxx_alloc_chip(dev);
7045 if (!chip) {
7046 err = -ENOMEM;
7047 goto out;
7048 }
7049
7050 chip->info = compat_info;
7051
7052 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
7053 if (IS_ERR(chip->reset)) {
7054 err = PTR_ERR(chip->reset);
7055 goto out;
7056 }
7057 if (chip->reset)
7058 usleep_range(1000, 2000);
7059
7060 /* Detect if the device is configured in single chip addressing mode,
7061 * otherwise continue with address specific smi init/detection.
7062 */
7063 err = mv88e6xxx_single_chip_detect(chip, mdiodev);
7064 if (err) {
7065 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
7066 if (err)
7067 goto out;
7068
7069 err = mv88e6xxx_detect(chip);
7070 if (err)
7071 goto out;
7072 }
7073
7074 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED)
7075 chip->tag_protocol = DSA_TAG_PROTO_EDSA;
7076 else
7077 chip->tag_protocol = DSA_TAG_PROTO_DSA;
7078
7079 mv88e6xxx_phy_init(chip);
7080
7081 if (chip->info->ops->get_eeprom) {
7082 if (np)
7083 of_property_read_u32(np, "eeprom-length",
7084 &chip->eeprom_len);
7085 else
7086 chip->eeprom_len = pdata->eeprom_len;
7087 }
7088
7089 mv88e6xxx_reg_lock(chip);
7090 err = mv88e6xxx_switch_reset(chip);
7091 mv88e6xxx_reg_unlock(chip);
7092 if (err)
7093 goto out;
7094
7095 if (np) {
7096 chip->irq = of_irq_get(np, 0);
7097 if (chip->irq == -EPROBE_DEFER) {
7098 err = chip->irq;
7099 goto out;
7100 }
7101 }
7102
7103 if (pdata)
7104 chip->irq = pdata->irq;
7105
7106 /* Has to be performed before the MDIO bus is created, because
7107 * the PHYs will link their interrupts to these interrupt
7108 * controllers
7109 */
7110 mv88e6xxx_reg_lock(chip);
7111 if (chip->irq > 0)
7112 err = mv88e6xxx_g1_irq_setup(chip);
7113 else
7114 err = mv88e6xxx_irq_poll_setup(chip);
7115 mv88e6xxx_reg_unlock(chip);
7116
7117 if (err)
7118 goto out;
7119
7120 if (chip->info->g2_irqs > 0) {
7121 err = mv88e6xxx_g2_irq_setup(chip);
7122 if (err)
7123 goto out_g1_irq;
7124 }
7125
7126 err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
7127 if (err)
7128 goto out_g2_irq;
7129
7130 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
7131 if (err)
7132 goto out_g1_atu_prob_irq;
7133
7134 err = mv88e6xxx_mdios_register(chip, np);
7135 if (err)
7136 goto out_g1_vtu_prob_irq;
7137
7138 err = mv88e6xxx_register_switch(chip);
7139 if (err)
7140 goto out_mdio;
7141
7142 return 0;
7143
7144out_mdio:
7145 mv88e6xxx_mdios_unregister(chip);
7146out_g1_vtu_prob_irq:
7147 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7148out_g1_atu_prob_irq:
7149 mv88e6xxx_g1_atu_prob_irq_free(chip);
7150out_g2_irq:
7151 if (chip->info->g2_irqs > 0)
7152 mv88e6xxx_g2_irq_free(chip);
7153out_g1_irq:
7154 if (chip->irq > 0)
7155 mv88e6xxx_g1_irq_free(chip);
7156 else
7157 mv88e6xxx_irq_poll_free(chip);
7158out:
7159 if (pdata)
7160 dev_put(pdata->netdev);
7161
7162 return err;
7163}
7164
7165static void mv88e6xxx_remove(struct mdio_device *mdiodev)
7166{
7167 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7168 struct mv88e6xxx_chip *chip;
7169
7170 if (!ds)
7171 return;
7172
7173 chip = ds->priv;
7174
7175 if (chip->info->ptp_support) {
7176 mv88e6xxx_hwtstamp_free(chip);
7177 mv88e6xxx_ptp_free(chip);
7178 }
7179
7180 mv88e6xxx_phy_destroy(chip);
7181 mv88e6xxx_unregister_switch(chip);
7182 mv88e6xxx_mdios_unregister(chip);
7183
7184 mv88e6xxx_g1_vtu_prob_irq_free(chip);
7185 mv88e6xxx_g1_atu_prob_irq_free(chip);
7186
7187 if (chip->info->g2_irqs > 0)
7188 mv88e6xxx_g2_irq_free(chip);
7189
7190 if (chip->irq > 0)
7191 mv88e6xxx_g1_irq_free(chip);
7192 else
7193 mv88e6xxx_irq_poll_free(chip);
7194}
7195
7196static void mv88e6xxx_shutdown(struct mdio_device *mdiodev)
7197{
7198 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
7199
7200 if (!ds)
7201 return;
7202
7203 dsa_switch_shutdown(ds);
7204
7205 dev_set_drvdata(&mdiodev->dev, NULL);
7206}
7207
7208static const struct of_device_id mv88e6xxx_of_match[] = {
7209 {
7210 .compatible = "marvell,mv88e6085",
7211 .data = &mv88e6xxx_table[MV88E6085],
7212 },
7213 {
7214 .compatible = "marvell,mv88e6190",
7215 .data = &mv88e6xxx_table[MV88E6190],
7216 },
7217 {
7218 .compatible = "marvell,mv88e6250",
7219 .data = &mv88e6xxx_table[MV88E6250],
7220 },
7221 { /* sentinel */ },
7222};
7223
7224MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
7225
7226static struct mdio_driver mv88e6xxx_driver = {
7227 .probe = mv88e6xxx_probe,
7228 .remove = mv88e6xxx_remove,
7229 .shutdown = mv88e6xxx_shutdown,
7230 .mdiodrv.driver = {
7231 .name = "mv88e6085",
7232 .of_match_table = mv88e6xxx_of_match,
7233 .pm = &mv88e6xxx_pm_ops,
7234 },
7235};
7236
7237mdio_module_driver(mv88e6xxx_driver);
7238
7239MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
7240MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
7241MODULE_LICENSE("GPL");