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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6
7#include <linux/pci.h>
8
9#include <linux/kthread.h>
10#include <linux/interrupt.h>
11#include <linux/pm_runtime.h>
12#include <linux/sizes.h>
13#include <linux/delay.h>
14
15#include "mei_dev.h"
16#include "hbm.h"
17
18#include "hw-me.h"
19#include "hw-me-regs.h"
20
21#include "mei-trace.h"
22
23/**
24 * mei_me_reg_read - Reads 32bit data from the mei device
25 *
26 * @hw: the me hardware structure
27 * @offset: offset from which to read the data
28 *
29 * Return: register value (u32)
30 */
31static inline u32 mei_me_reg_read(const struct mei_me_hw *hw,
32 unsigned long offset)
33{
34 return ioread32(hw->mem_addr + offset);
35}
36
37
38/**
39 * mei_me_reg_write - Writes 32bit data to the mei device
40 *
41 * @hw: the me hardware structure
42 * @offset: offset from which to write the data
43 * @value: register value to write (u32)
44 */
45static inline void mei_me_reg_write(const struct mei_me_hw *hw,
46 unsigned long offset, u32 value)
47{
48 iowrite32(value, hw->mem_addr + offset);
49}
50
51/**
52 * mei_me_mecbrw_read - Reads 32bit data from ME circular buffer
53 * read window register
54 *
55 * @dev: the device structure
56 *
57 * Return: ME_CB_RW register value (u32)
58 */
59static inline u32 mei_me_mecbrw_read(const struct mei_device *dev)
60{
61 return mei_me_reg_read(to_me_hw(dev), ME_CB_RW);
62}
63
64/**
65 * mei_me_hcbww_write - write 32bit data to the host circular buffer
66 *
67 * @dev: the device structure
68 * @data: 32bit data to be written to the host circular buffer
69 */
70static inline void mei_me_hcbww_write(struct mei_device *dev, u32 data)
71{
72 mei_me_reg_write(to_me_hw(dev), H_CB_WW, data);
73}
74
75/**
76 * mei_me_mecsr_read - Reads 32bit data from the ME CSR
77 *
78 * @dev: the device structure
79 *
80 * Return: ME_CSR_HA register value (u32)
81 */
82static inline u32 mei_me_mecsr_read(const struct mei_device *dev)
83{
84 u32 reg;
85
86 reg = mei_me_reg_read(to_me_hw(dev), ME_CSR_HA);
87 trace_mei_reg_read(dev->dev, "ME_CSR_HA", ME_CSR_HA, reg);
88
89 return reg;
90}
91
92/**
93 * mei_hcsr_read - Reads 32bit data from the host CSR
94 *
95 * @dev: the device structure
96 *
97 * Return: H_CSR register value (u32)
98 */
99static inline u32 mei_hcsr_read(const struct mei_device *dev)
100{
101 u32 reg;
102
103 reg = mei_me_reg_read(to_me_hw(dev), H_CSR);
104 trace_mei_reg_read(dev->dev, "H_CSR", H_CSR, reg);
105
106 return reg;
107}
108
109/**
110 * mei_hcsr_write - writes H_CSR register to the mei device
111 *
112 * @dev: the device structure
113 * @reg: new register value
114 */
115static inline void mei_hcsr_write(struct mei_device *dev, u32 reg)
116{
117 trace_mei_reg_write(dev->dev, "H_CSR", H_CSR, reg);
118 mei_me_reg_write(to_me_hw(dev), H_CSR, reg);
119}
120
121/**
122 * mei_hcsr_set - writes H_CSR register to the mei device,
123 * and ignores the H_IS bit for it is write-one-to-zero.
124 *
125 * @dev: the device structure
126 * @reg: new register value
127 */
128static inline void mei_hcsr_set(struct mei_device *dev, u32 reg)
129{
130 reg &= ~H_CSR_IS_MASK;
131 mei_hcsr_write(dev, reg);
132}
133
134/**
135 * mei_hcsr_set_hig - set host interrupt (set H_IG)
136 *
137 * @dev: the device structure
138 */
139static inline void mei_hcsr_set_hig(struct mei_device *dev)
140{
141 u32 hcsr;
142
143 hcsr = mei_hcsr_read(dev) | H_IG;
144 mei_hcsr_set(dev, hcsr);
145}
146
147/**
148 * mei_me_d0i3c_read - Reads 32bit data from the D0I3C register
149 *
150 * @dev: the device structure
151 *
152 * Return: H_D0I3C register value (u32)
153 */
154static inline u32 mei_me_d0i3c_read(const struct mei_device *dev)
155{
156 u32 reg;
157
158 reg = mei_me_reg_read(to_me_hw(dev), H_D0I3C);
159 trace_mei_reg_read(dev->dev, "H_D0I3C", H_D0I3C, reg);
160
161 return reg;
162}
163
164/**
165 * mei_me_d0i3c_write - writes H_D0I3C register to device
166 *
167 * @dev: the device structure
168 * @reg: new register value
169 */
170static inline void mei_me_d0i3c_write(struct mei_device *dev, u32 reg)
171{
172 trace_mei_reg_write(dev->dev, "H_D0I3C", H_D0I3C, reg);
173 mei_me_reg_write(to_me_hw(dev), H_D0I3C, reg);
174}
175
176/**
177 * mei_me_trc_status - read trc status register
178 *
179 * @dev: mei device
180 * @trc: trc status register value
181 *
182 * Return: 0 on success, error otherwise
183 */
184static int mei_me_trc_status(struct mei_device *dev, u32 *trc)
185{
186 struct mei_me_hw *hw = to_me_hw(dev);
187
188 if (!hw->cfg->hw_trc_supported)
189 return -EOPNOTSUPP;
190
191 *trc = mei_me_reg_read(hw, ME_TRC);
192 trace_mei_reg_read(dev->dev, "ME_TRC", ME_TRC, *trc);
193
194 return 0;
195}
196
197/**
198 * mei_me_fw_status - read fw status register from pci config space
199 *
200 * @dev: mei device
201 * @fw_status: fw status register values
202 *
203 * Return: 0 on success, error otherwise
204 */
205static int mei_me_fw_status(struct mei_device *dev,
206 struct mei_fw_status *fw_status)
207{
208 struct mei_me_hw *hw = to_me_hw(dev);
209 const struct mei_fw_status *fw_src = &hw->cfg->fw_status;
210 int ret;
211 int i;
212
213 if (!fw_status || !hw->read_fws)
214 return -EINVAL;
215
216 fw_status->count = fw_src->count;
217 for (i = 0; i < fw_src->count && i < MEI_FW_STATUS_MAX; i++) {
218 ret = hw->read_fws(dev, fw_src->status[i],
219 &fw_status->status[i]);
220 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_X",
221 fw_src->status[i],
222 fw_status->status[i]);
223 if (ret)
224 return ret;
225 }
226
227 return 0;
228}
229
230/**
231 * mei_me_hw_config - configure hw dependent settings
232 *
233 * @dev: mei device
234 *
235 * Return:
236 * * -EINVAL when read_fws is not set
237 * * 0 on success
238 *
239 */
240static int mei_me_hw_config(struct mei_device *dev)
241{
242 struct mei_me_hw *hw = to_me_hw(dev);
243 u32 hcsr, reg;
244
245 if (WARN_ON(!hw->read_fws))
246 return -EINVAL;
247
248 /* Doesn't change in runtime */
249 hcsr = mei_hcsr_read(dev);
250 hw->hbuf_depth = (hcsr & H_CBD) >> 24;
251
252 reg = 0;
253 hw->read_fws(dev, PCI_CFG_HFS_1, ®);
254 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
255 hw->d0i3_supported =
256 ((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
257
258 hw->pg_state = MEI_PG_OFF;
259 if (hw->d0i3_supported) {
260 reg = mei_me_d0i3c_read(dev);
261 if (reg & H_D0I3C_I3)
262 hw->pg_state = MEI_PG_ON;
263 }
264
265 return 0;
266}
267
268/**
269 * mei_me_pg_state - translate internal pg state
270 * to the mei power gating state
271 *
272 * @dev: mei device
273 *
274 * Return: MEI_PG_OFF if aliveness is on and MEI_PG_ON otherwise
275 */
276static inline enum mei_pg_state mei_me_pg_state(struct mei_device *dev)
277{
278 struct mei_me_hw *hw = to_me_hw(dev);
279
280 return hw->pg_state;
281}
282
283static inline u32 me_intr_src(u32 hcsr)
284{
285 return hcsr & H_CSR_IS_MASK;
286}
287
288/**
289 * me_intr_disable - disables mei device interrupts
290 * using supplied hcsr register value.
291 *
292 * @dev: the device structure
293 * @hcsr: supplied hcsr register value
294 */
295static inline void me_intr_disable(struct mei_device *dev, u32 hcsr)
296{
297 hcsr &= ~H_CSR_IE_MASK;
298 mei_hcsr_set(dev, hcsr);
299}
300
301/**
302 * me_intr_clear - clear and stop interrupts
303 *
304 * @dev: the device structure
305 * @hcsr: supplied hcsr register value
306 */
307static inline void me_intr_clear(struct mei_device *dev, u32 hcsr)
308{
309 if (me_intr_src(hcsr))
310 mei_hcsr_write(dev, hcsr);
311}
312
313/**
314 * mei_me_intr_clear - clear and stop interrupts
315 *
316 * @dev: the device structure
317 */
318static void mei_me_intr_clear(struct mei_device *dev)
319{
320 u32 hcsr = mei_hcsr_read(dev);
321
322 me_intr_clear(dev, hcsr);
323}
324/**
325 * mei_me_intr_enable - enables mei device interrupts
326 *
327 * @dev: the device structure
328 */
329static void mei_me_intr_enable(struct mei_device *dev)
330{
331 u32 hcsr;
332
333 if (mei_me_hw_use_polling(to_me_hw(dev)))
334 return;
335
336 hcsr = mei_hcsr_read(dev) | H_CSR_IE_MASK;
337 mei_hcsr_set(dev, hcsr);
338}
339
340/**
341 * mei_me_intr_disable - disables mei device interrupts
342 *
343 * @dev: the device structure
344 */
345static void mei_me_intr_disable(struct mei_device *dev)
346{
347 u32 hcsr = mei_hcsr_read(dev);
348
349 me_intr_disable(dev, hcsr);
350}
351
352/**
353 * mei_me_synchronize_irq - wait for pending IRQ handlers
354 *
355 * @dev: the device structure
356 */
357static void mei_me_synchronize_irq(struct mei_device *dev)
358{
359 struct mei_me_hw *hw = to_me_hw(dev);
360
361 if (mei_me_hw_use_polling(hw))
362 return;
363
364 synchronize_irq(hw->irq);
365}
366
367/**
368 * mei_me_hw_reset_release - release device from the reset
369 *
370 * @dev: the device structure
371 */
372static void mei_me_hw_reset_release(struct mei_device *dev)
373{
374 u32 hcsr = mei_hcsr_read(dev);
375
376 hcsr |= H_IG;
377 hcsr &= ~H_RST;
378 mei_hcsr_set(dev, hcsr);
379}
380
381/**
382 * mei_me_host_set_ready - enable device
383 *
384 * @dev: mei device
385 */
386static void mei_me_host_set_ready(struct mei_device *dev)
387{
388 u32 hcsr = mei_hcsr_read(dev);
389
390 if (!mei_me_hw_use_polling(to_me_hw(dev)))
391 hcsr |= H_CSR_IE_MASK;
392
393 hcsr |= H_IG | H_RDY;
394 mei_hcsr_set(dev, hcsr);
395}
396
397/**
398 * mei_me_host_is_ready - check whether the host has turned ready
399 *
400 * @dev: mei device
401 * Return: bool
402 */
403static bool mei_me_host_is_ready(struct mei_device *dev)
404{
405 u32 hcsr = mei_hcsr_read(dev);
406
407 return (hcsr & H_RDY) == H_RDY;
408}
409
410/**
411 * mei_me_hw_is_ready - check whether the me(hw) has turned ready
412 *
413 * @dev: mei device
414 * Return: bool
415 */
416static bool mei_me_hw_is_ready(struct mei_device *dev)
417{
418 u32 mecsr = mei_me_mecsr_read(dev);
419
420 return (mecsr & ME_RDY_HRA) == ME_RDY_HRA;
421}
422
423/**
424 * mei_me_hw_is_resetting - check whether the me(hw) is in reset
425 *
426 * @dev: mei device
427 * Return: bool
428 */
429static bool mei_me_hw_is_resetting(struct mei_device *dev)
430{
431 u32 mecsr = mei_me_mecsr_read(dev);
432
433 return (mecsr & ME_RST_HRA) == ME_RST_HRA;
434}
435
436/**
437 * mei_gsc_pxp_check - check for gsc firmware entering pxp mode
438 *
439 * @dev: the device structure
440 */
441static void mei_gsc_pxp_check(struct mei_device *dev)
442{
443 struct mei_me_hw *hw = to_me_hw(dev);
444 u32 fwsts5 = 0;
445
446 if (dev->pxp_mode == MEI_DEV_PXP_DEFAULT)
447 return;
448
449 hw->read_fws(dev, PCI_CFG_HFS_5, &fwsts5);
450 trace_mei_pci_cfg_read(dev->dev, "PCI_CFG_HFS_5", PCI_CFG_HFS_5, fwsts5);
451 if ((fwsts5 & GSC_CFG_HFS_5_BOOT_TYPE_MSK) == GSC_CFG_HFS_5_BOOT_TYPE_PXP) {
452 dev_dbg(dev->dev, "pxp mode is ready 0x%08x\n", fwsts5);
453 dev->pxp_mode = MEI_DEV_PXP_READY;
454 } else {
455 dev_dbg(dev->dev, "pxp mode is not ready 0x%08x\n", fwsts5);
456 }
457}
458
459/**
460 * mei_me_hw_ready_wait - wait until the me(hw) has turned ready
461 * or timeout is reached
462 *
463 * @dev: mei device
464 * Return: 0 on success, error otherwise
465 */
466static int mei_me_hw_ready_wait(struct mei_device *dev)
467{
468 mutex_unlock(&dev->device_lock);
469 wait_event_timeout(dev->wait_hw_ready,
470 dev->recvd_hw_ready,
471 dev->timeouts.hw_ready);
472 mutex_lock(&dev->device_lock);
473 if (!dev->recvd_hw_ready) {
474 dev_err(dev->dev, "wait hw ready failed\n");
475 return -ETIME;
476 }
477
478 mei_gsc_pxp_check(dev);
479
480 mei_me_hw_reset_release(dev);
481 dev->recvd_hw_ready = false;
482 return 0;
483}
484
485/**
486 * mei_me_hw_start - hw start routine
487 *
488 * @dev: mei device
489 * Return: 0 on success, error otherwise
490 */
491static int mei_me_hw_start(struct mei_device *dev)
492{
493 int ret = mei_me_hw_ready_wait(dev);
494
495 if (ret)
496 return ret;
497 dev_dbg(dev->dev, "hw is ready\n");
498
499 mei_me_host_set_ready(dev);
500 return ret;
501}
502
503
504/**
505 * mei_hbuf_filled_slots - gets number of device filled buffer slots
506 *
507 * @dev: the device structure
508 *
509 * Return: number of filled slots
510 */
511static unsigned char mei_hbuf_filled_slots(struct mei_device *dev)
512{
513 u32 hcsr;
514 char read_ptr, write_ptr;
515
516 hcsr = mei_hcsr_read(dev);
517
518 read_ptr = (char) ((hcsr & H_CBRP) >> 8);
519 write_ptr = (char) ((hcsr & H_CBWP) >> 16);
520
521 return (unsigned char) (write_ptr - read_ptr);
522}
523
524/**
525 * mei_me_hbuf_is_empty - checks if host buffer is empty.
526 *
527 * @dev: the device structure
528 *
529 * Return: true if empty, false - otherwise.
530 */
531static bool mei_me_hbuf_is_empty(struct mei_device *dev)
532{
533 return mei_hbuf_filled_slots(dev) == 0;
534}
535
536/**
537 * mei_me_hbuf_empty_slots - counts write empty slots.
538 *
539 * @dev: the device structure
540 *
541 * Return: -EOVERFLOW if overflow, otherwise empty slots count
542 */
543static int mei_me_hbuf_empty_slots(struct mei_device *dev)
544{
545 struct mei_me_hw *hw = to_me_hw(dev);
546 unsigned char filled_slots, empty_slots;
547
548 filled_slots = mei_hbuf_filled_slots(dev);
549 empty_slots = hw->hbuf_depth - filled_slots;
550
551 /* check for overflow */
552 if (filled_slots > hw->hbuf_depth)
553 return -EOVERFLOW;
554
555 return empty_slots;
556}
557
558/**
559 * mei_me_hbuf_depth - returns depth of the hw buffer.
560 *
561 * @dev: the device structure
562 *
563 * Return: size of hw buffer in slots
564 */
565static u32 mei_me_hbuf_depth(const struct mei_device *dev)
566{
567 struct mei_me_hw *hw = to_me_hw(dev);
568
569 return hw->hbuf_depth;
570}
571
572/**
573 * mei_me_hbuf_write - writes a message to host hw buffer.
574 *
575 * @dev: the device structure
576 * @hdr: header of message
577 * @hdr_len: header length in bytes: must be multiplication of a slot (4bytes)
578 * @data: payload
579 * @data_len: payload length in bytes
580 *
581 * Return: 0 if success, < 0 - otherwise.
582 */
583static int mei_me_hbuf_write(struct mei_device *dev,
584 const void *hdr, size_t hdr_len,
585 const void *data, size_t data_len)
586{
587 unsigned long rem;
588 unsigned long i;
589 const u32 *reg_buf;
590 u32 dw_cnt;
591 int empty_slots;
592
593 if (WARN_ON(!hdr || hdr_len & 0x3))
594 return -EINVAL;
595
596 if (!data && data_len) {
597 dev_err(dev->dev, "wrong parameters null data with data_len = %zu\n", data_len);
598 return -EINVAL;
599 }
600
601 dev_dbg(dev->dev, MEI_HDR_FMT, MEI_HDR_PRM((struct mei_msg_hdr *)hdr));
602
603 empty_slots = mei_hbuf_empty_slots(dev);
604 dev_dbg(dev->dev, "empty slots = %d.\n", empty_slots);
605
606 if (empty_slots < 0)
607 return -EOVERFLOW;
608
609 dw_cnt = mei_data2slots(hdr_len + data_len);
610 if (dw_cnt > (u32)empty_slots)
611 return -EMSGSIZE;
612
613 reg_buf = hdr;
614 for (i = 0; i < hdr_len / MEI_SLOT_SIZE; i++)
615 mei_me_hcbww_write(dev, reg_buf[i]);
616
617 reg_buf = data;
618 for (i = 0; i < data_len / MEI_SLOT_SIZE; i++)
619 mei_me_hcbww_write(dev, reg_buf[i]);
620
621 rem = data_len & 0x3;
622 if (rem > 0) {
623 u32 reg = 0;
624
625 memcpy(®, (const u8 *)data + data_len - rem, rem);
626 mei_me_hcbww_write(dev, reg);
627 }
628
629 mei_hcsr_set_hig(dev);
630 if (!mei_me_hw_is_ready(dev))
631 return -EIO;
632
633 return 0;
634}
635
636/**
637 * mei_me_count_full_read_slots - counts read full slots.
638 *
639 * @dev: the device structure
640 *
641 * Return: -EOVERFLOW if overflow, otherwise filled slots count
642 */
643static int mei_me_count_full_read_slots(struct mei_device *dev)
644{
645 u32 me_csr;
646 char read_ptr, write_ptr;
647 unsigned char buffer_depth, filled_slots;
648
649 me_csr = mei_me_mecsr_read(dev);
650 buffer_depth = (unsigned char)((me_csr & ME_CBD_HRA) >> 24);
651 read_ptr = (char) ((me_csr & ME_CBRP_HRA) >> 8);
652 write_ptr = (char) ((me_csr & ME_CBWP_HRA) >> 16);
653 filled_slots = (unsigned char) (write_ptr - read_ptr);
654
655 /* check for overflow */
656 if (filled_slots > buffer_depth)
657 return -EOVERFLOW;
658
659 dev_dbg(dev->dev, "filled_slots =%08x\n", filled_slots);
660 return (int)filled_slots;
661}
662
663/**
664 * mei_me_read_slots - reads a message from mei device.
665 *
666 * @dev: the device structure
667 * @buffer: message buffer will be written
668 * @buffer_length: message size will be read
669 *
670 * Return: always 0
671 */
672static int mei_me_read_slots(struct mei_device *dev, unsigned char *buffer,
673 unsigned long buffer_length)
674{
675 u32 *reg_buf = (u32 *)buffer;
676
677 for (; buffer_length >= MEI_SLOT_SIZE; buffer_length -= MEI_SLOT_SIZE)
678 *reg_buf++ = mei_me_mecbrw_read(dev);
679
680 if (buffer_length > 0) {
681 u32 reg = mei_me_mecbrw_read(dev);
682
683 memcpy(reg_buf, ®, buffer_length);
684 }
685
686 mei_hcsr_set_hig(dev);
687 return 0;
688}
689
690/**
691 * mei_me_pg_set - write pg enter register
692 *
693 * @dev: the device structure
694 */
695static void mei_me_pg_set(struct mei_device *dev)
696{
697 struct mei_me_hw *hw = to_me_hw(dev);
698 u32 reg;
699
700 reg = mei_me_reg_read(hw, H_HPG_CSR);
701 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
702
703 reg |= H_HPG_CSR_PGI;
704
705 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
706 mei_me_reg_write(hw, H_HPG_CSR, reg);
707}
708
709/**
710 * mei_me_pg_unset - write pg exit register
711 *
712 * @dev: the device structure
713 */
714static void mei_me_pg_unset(struct mei_device *dev)
715{
716 struct mei_me_hw *hw = to_me_hw(dev);
717 u32 reg;
718
719 reg = mei_me_reg_read(hw, H_HPG_CSR);
720 trace_mei_reg_read(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
721
722 WARN(!(reg & H_HPG_CSR_PGI), "PGI is not set\n");
723
724 reg |= H_HPG_CSR_PGIHEXR;
725
726 trace_mei_reg_write(dev->dev, "H_HPG_CSR", H_HPG_CSR, reg);
727 mei_me_reg_write(hw, H_HPG_CSR, reg);
728}
729
730/**
731 * mei_me_pg_legacy_enter_sync - perform legacy pg entry procedure
732 *
733 * @dev: the device structure
734 *
735 * Return: 0 on success an error code otherwise
736 */
737static int mei_me_pg_legacy_enter_sync(struct mei_device *dev)
738{
739 struct mei_me_hw *hw = to_me_hw(dev);
740 int ret;
741
742 dev->pg_event = MEI_PG_EVENT_WAIT;
743
744 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
745 if (ret)
746 return ret;
747
748 mutex_unlock(&dev->device_lock);
749 wait_event_timeout(dev->wait_pg,
750 dev->pg_event == MEI_PG_EVENT_RECEIVED,
751 dev->timeouts.pgi);
752 mutex_lock(&dev->device_lock);
753
754 if (dev->pg_event == MEI_PG_EVENT_RECEIVED) {
755 mei_me_pg_set(dev);
756 ret = 0;
757 } else {
758 ret = -ETIME;
759 }
760
761 dev->pg_event = MEI_PG_EVENT_IDLE;
762 hw->pg_state = MEI_PG_ON;
763
764 return ret;
765}
766
767/**
768 * mei_me_pg_legacy_exit_sync - perform legacy pg exit procedure
769 *
770 * @dev: the device structure
771 *
772 * Return: 0 on success an error code otherwise
773 */
774static int mei_me_pg_legacy_exit_sync(struct mei_device *dev)
775{
776 struct mei_me_hw *hw = to_me_hw(dev);
777 int ret;
778
779 if (dev->pg_event == MEI_PG_EVENT_RECEIVED)
780 goto reply;
781
782 dev->pg_event = MEI_PG_EVENT_WAIT;
783
784 mei_me_pg_unset(dev);
785
786 mutex_unlock(&dev->device_lock);
787 wait_event_timeout(dev->wait_pg,
788 dev->pg_event == MEI_PG_EVENT_RECEIVED,
789 dev->timeouts.pgi);
790 mutex_lock(&dev->device_lock);
791
792reply:
793 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
794 ret = -ETIME;
795 goto out;
796 }
797
798 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
799 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_EXIT_RES_CMD);
800 if (ret)
801 return ret;
802
803 mutex_unlock(&dev->device_lock);
804 wait_event_timeout(dev->wait_pg,
805 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
806 dev->timeouts.pgi);
807 mutex_lock(&dev->device_lock);
808
809 if (dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED)
810 ret = 0;
811 else
812 ret = -ETIME;
813
814out:
815 dev->pg_event = MEI_PG_EVENT_IDLE;
816 hw->pg_state = MEI_PG_OFF;
817
818 return ret;
819}
820
821/**
822 * mei_me_pg_in_transition - is device now in pg transition
823 *
824 * @dev: the device structure
825 *
826 * Return: true if in pg transition, false otherwise
827 */
828static bool mei_me_pg_in_transition(struct mei_device *dev)
829{
830 return dev->pg_event >= MEI_PG_EVENT_WAIT &&
831 dev->pg_event <= MEI_PG_EVENT_INTR_WAIT;
832}
833
834/**
835 * mei_me_pg_is_enabled - detect if PG is supported by HW
836 *
837 * @dev: the device structure
838 *
839 * Return: true is pg supported, false otherwise
840 */
841static bool mei_me_pg_is_enabled(struct mei_device *dev)
842{
843 struct mei_me_hw *hw = to_me_hw(dev);
844 u32 reg = mei_me_mecsr_read(dev);
845
846 if (hw->d0i3_supported)
847 return true;
848
849 if ((reg & ME_PGIC_HRA) == 0)
850 goto notsupported;
851
852 if (!dev->hbm_f_pg_supported)
853 goto notsupported;
854
855 return true;
856
857notsupported:
858 dev_dbg(dev->dev, "pg: not supported: d0i3 = %d HGP = %d hbm version %d.%d ?= %d.%d\n",
859 hw->d0i3_supported,
860 !!(reg & ME_PGIC_HRA),
861 dev->version.major_version,
862 dev->version.minor_version,
863 HBM_MAJOR_VERSION_PGI,
864 HBM_MINOR_VERSION_PGI);
865
866 return false;
867}
868
869/**
870 * mei_me_d0i3_set - write d0i3 register bit on mei device.
871 *
872 * @dev: the device structure
873 * @intr: ask for interrupt
874 *
875 * Return: D0I3C register value
876 */
877static u32 mei_me_d0i3_set(struct mei_device *dev, bool intr)
878{
879 u32 reg = mei_me_d0i3c_read(dev);
880
881 reg |= H_D0I3C_I3;
882 if (intr)
883 reg |= H_D0I3C_IR;
884 else
885 reg &= ~H_D0I3C_IR;
886 mei_me_d0i3c_write(dev, reg);
887 /* read it to ensure HW consistency */
888 reg = mei_me_d0i3c_read(dev);
889 return reg;
890}
891
892/**
893 * mei_me_d0i3_unset - clean d0i3 register bit on mei device.
894 *
895 * @dev: the device structure
896 *
897 * Return: D0I3C register value
898 */
899static u32 mei_me_d0i3_unset(struct mei_device *dev)
900{
901 u32 reg = mei_me_d0i3c_read(dev);
902
903 reg &= ~H_D0I3C_I3;
904 reg |= H_D0I3C_IR;
905 mei_me_d0i3c_write(dev, reg);
906 /* read it to ensure HW consistency */
907 reg = mei_me_d0i3c_read(dev);
908 return reg;
909}
910
911/**
912 * mei_me_d0i3_enter_sync - perform d0i3 entry procedure
913 *
914 * @dev: the device structure
915 *
916 * Return: 0 on success an error code otherwise
917 */
918static int mei_me_d0i3_enter_sync(struct mei_device *dev)
919{
920 struct mei_me_hw *hw = to_me_hw(dev);
921 int ret;
922 u32 reg;
923
924 reg = mei_me_d0i3c_read(dev);
925 if (reg & H_D0I3C_I3) {
926 /* we are in d0i3, nothing to do */
927 dev_dbg(dev->dev, "d0i3 set not needed\n");
928 ret = 0;
929 goto on;
930 }
931
932 /* PGI entry procedure */
933 dev->pg_event = MEI_PG_EVENT_WAIT;
934
935 ret = mei_hbm_pg(dev, MEI_PG_ISOLATION_ENTRY_REQ_CMD);
936 if (ret)
937 /* FIXME: should we reset here? */
938 goto out;
939
940 mutex_unlock(&dev->device_lock);
941 wait_event_timeout(dev->wait_pg,
942 dev->pg_event == MEI_PG_EVENT_RECEIVED,
943 dev->timeouts.pgi);
944 mutex_lock(&dev->device_lock);
945
946 if (dev->pg_event != MEI_PG_EVENT_RECEIVED) {
947 ret = -ETIME;
948 goto out;
949 }
950 /* end PGI entry procedure */
951
952 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
953
954 reg = mei_me_d0i3_set(dev, true);
955 if (!(reg & H_D0I3C_CIP)) {
956 dev_dbg(dev->dev, "d0i3 enter wait not needed\n");
957 ret = 0;
958 goto on;
959 }
960
961 mutex_unlock(&dev->device_lock);
962 wait_event_timeout(dev->wait_pg,
963 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
964 dev->timeouts.d0i3);
965 mutex_lock(&dev->device_lock);
966
967 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
968 reg = mei_me_d0i3c_read(dev);
969 if (!(reg & H_D0I3C_I3)) {
970 ret = -ETIME;
971 goto out;
972 }
973 }
974
975 ret = 0;
976on:
977 hw->pg_state = MEI_PG_ON;
978out:
979 dev->pg_event = MEI_PG_EVENT_IDLE;
980 dev_dbg(dev->dev, "d0i3 enter ret = %d\n", ret);
981 return ret;
982}
983
984/**
985 * mei_me_d0i3_enter - perform d0i3 entry procedure
986 * no hbm PG handshake
987 * no waiting for confirmation; runs with interrupts
988 * disabled
989 *
990 * @dev: the device structure
991 *
992 * Return: 0 on success an error code otherwise
993 */
994static int mei_me_d0i3_enter(struct mei_device *dev)
995{
996 struct mei_me_hw *hw = to_me_hw(dev);
997 u32 reg;
998
999 reg = mei_me_d0i3c_read(dev);
1000 if (reg & H_D0I3C_I3) {
1001 /* we are in d0i3, nothing to do */
1002 dev_dbg(dev->dev, "already d0i3 : set not needed\n");
1003 goto on;
1004 }
1005
1006 mei_me_d0i3_set(dev, false);
1007on:
1008 hw->pg_state = MEI_PG_ON;
1009 dev->pg_event = MEI_PG_EVENT_IDLE;
1010 dev_dbg(dev->dev, "d0i3 enter\n");
1011 return 0;
1012}
1013
1014/**
1015 * mei_me_d0i3_exit_sync - perform d0i3 exit procedure
1016 *
1017 * @dev: the device structure
1018 *
1019 * Return: 0 on success an error code otherwise
1020 */
1021static int mei_me_d0i3_exit_sync(struct mei_device *dev)
1022{
1023 struct mei_me_hw *hw = to_me_hw(dev);
1024 int ret;
1025 u32 reg;
1026
1027 dev->pg_event = MEI_PG_EVENT_INTR_WAIT;
1028
1029 reg = mei_me_d0i3c_read(dev);
1030 if (!(reg & H_D0I3C_I3)) {
1031 /* we are not in d0i3, nothing to do */
1032 dev_dbg(dev->dev, "d0i3 exit not needed\n");
1033 ret = 0;
1034 goto off;
1035 }
1036
1037 reg = mei_me_d0i3_unset(dev);
1038 if (!(reg & H_D0I3C_CIP)) {
1039 dev_dbg(dev->dev, "d0i3 exit wait not needed\n");
1040 ret = 0;
1041 goto off;
1042 }
1043
1044 mutex_unlock(&dev->device_lock);
1045 wait_event_timeout(dev->wait_pg,
1046 dev->pg_event == MEI_PG_EVENT_INTR_RECEIVED,
1047 dev->timeouts.d0i3);
1048 mutex_lock(&dev->device_lock);
1049
1050 if (dev->pg_event != MEI_PG_EVENT_INTR_RECEIVED) {
1051 reg = mei_me_d0i3c_read(dev);
1052 if (reg & H_D0I3C_I3) {
1053 ret = -ETIME;
1054 goto out;
1055 }
1056 }
1057
1058 ret = 0;
1059off:
1060 hw->pg_state = MEI_PG_OFF;
1061out:
1062 dev->pg_event = MEI_PG_EVENT_IDLE;
1063
1064 dev_dbg(dev->dev, "d0i3 exit ret = %d\n", ret);
1065 return ret;
1066}
1067
1068/**
1069 * mei_me_pg_legacy_intr - perform legacy pg processing
1070 * in interrupt thread handler
1071 *
1072 * @dev: the device structure
1073 */
1074static void mei_me_pg_legacy_intr(struct mei_device *dev)
1075{
1076 struct mei_me_hw *hw = to_me_hw(dev);
1077
1078 if (dev->pg_event != MEI_PG_EVENT_INTR_WAIT)
1079 return;
1080
1081 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1082 hw->pg_state = MEI_PG_OFF;
1083 if (waitqueue_active(&dev->wait_pg))
1084 wake_up(&dev->wait_pg);
1085}
1086
1087/**
1088 * mei_me_d0i3_intr - perform d0i3 processing in interrupt thread handler
1089 *
1090 * @dev: the device structure
1091 * @intr_source: interrupt source
1092 */
1093static void mei_me_d0i3_intr(struct mei_device *dev, u32 intr_source)
1094{
1095 struct mei_me_hw *hw = to_me_hw(dev);
1096
1097 if (dev->pg_event == MEI_PG_EVENT_INTR_WAIT &&
1098 (intr_source & H_D0I3C_IS)) {
1099 dev->pg_event = MEI_PG_EVENT_INTR_RECEIVED;
1100 if (hw->pg_state == MEI_PG_ON) {
1101 hw->pg_state = MEI_PG_OFF;
1102 if (dev->hbm_state != MEI_HBM_IDLE) {
1103 /*
1104 * force H_RDY because it could be
1105 * wiped off during PG
1106 */
1107 dev_dbg(dev->dev, "d0i3 set host ready\n");
1108 mei_me_host_set_ready(dev);
1109 }
1110 } else {
1111 hw->pg_state = MEI_PG_ON;
1112 }
1113
1114 wake_up(&dev->wait_pg);
1115 }
1116
1117 if (hw->pg_state == MEI_PG_ON && (intr_source & H_IS)) {
1118 /*
1119 * HW sent some data and we are in D0i3, so
1120 * we got here because of HW initiated exit from D0i3.
1121 * Start runtime pm resume sequence to exit low power state.
1122 */
1123 dev_dbg(dev->dev, "d0i3 want resume\n");
1124 mei_hbm_pg_resume(dev);
1125 }
1126}
1127
1128/**
1129 * mei_me_pg_intr - perform pg processing in interrupt thread handler
1130 *
1131 * @dev: the device structure
1132 * @intr_source: interrupt source
1133 */
1134static void mei_me_pg_intr(struct mei_device *dev, u32 intr_source)
1135{
1136 struct mei_me_hw *hw = to_me_hw(dev);
1137
1138 if (hw->d0i3_supported)
1139 mei_me_d0i3_intr(dev, intr_source);
1140 else
1141 mei_me_pg_legacy_intr(dev);
1142}
1143
1144/**
1145 * mei_me_pg_enter_sync - perform runtime pm entry procedure
1146 *
1147 * @dev: the device structure
1148 *
1149 * Return: 0 on success an error code otherwise
1150 */
1151int mei_me_pg_enter_sync(struct mei_device *dev)
1152{
1153 struct mei_me_hw *hw = to_me_hw(dev);
1154
1155 if (hw->d0i3_supported)
1156 return mei_me_d0i3_enter_sync(dev);
1157 else
1158 return mei_me_pg_legacy_enter_sync(dev);
1159}
1160
1161/**
1162 * mei_me_pg_exit_sync - perform runtime pm exit procedure
1163 *
1164 * @dev: the device structure
1165 *
1166 * Return: 0 on success an error code otherwise
1167 */
1168int mei_me_pg_exit_sync(struct mei_device *dev)
1169{
1170 struct mei_me_hw *hw = to_me_hw(dev);
1171
1172 if (hw->d0i3_supported)
1173 return mei_me_d0i3_exit_sync(dev);
1174 else
1175 return mei_me_pg_legacy_exit_sync(dev);
1176}
1177
1178/**
1179 * mei_me_hw_reset - resets fw via mei csr register.
1180 *
1181 * @dev: the device structure
1182 * @intr_enable: if interrupt should be enabled after reset.
1183 *
1184 * Return: 0 on success an error code otherwise
1185 */
1186static int mei_me_hw_reset(struct mei_device *dev, bool intr_enable)
1187{
1188 struct mei_me_hw *hw = to_me_hw(dev);
1189 int ret;
1190 u32 hcsr;
1191
1192 if (intr_enable) {
1193 mei_me_intr_enable(dev);
1194 if (hw->d0i3_supported) {
1195 ret = mei_me_d0i3_exit_sync(dev);
1196 if (ret)
1197 return ret;
1198 } else {
1199 hw->pg_state = MEI_PG_OFF;
1200 }
1201 }
1202
1203 pm_runtime_set_active(dev->dev);
1204
1205 hcsr = mei_hcsr_read(dev);
1206 /* H_RST may be found lit before reset is started,
1207 * for example if preceding reset flow hasn't completed.
1208 * In that case asserting H_RST will be ignored, therefore
1209 * we need to clean H_RST bit to start a successful reset sequence.
1210 */
1211 if ((hcsr & H_RST) == H_RST) {
1212 dev_warn(dev->dev, "H_RST is set = 0x%08X", hcsr);
1213 hcsr &= ~H_RST;
1214 mei_hcsr_set(dev, hcsr);
1215 hcsr = mei_hcsr_read(dev);
1216 }
1217
1218 hcsr |= H_RST | H_IG | H_CSR_IS_MASK;
1219
1220 if (!intr_enable || mei_me_hw_use_polling(to_me_hw(dev)))
1221 hcsr &= ~H_CSR_IE_MASK;
1222
1223 dev->recvd_hw_ready = false;
1224 mei_hcsr_write(dev, hcsr);
1225
1226 /*
1227 * Host reads the H_CSR once to ensure that the
1228 * posted write to H_CSR completes.
1229 */
1230 hcsr = mei_hcsr_read(dev);
1231
1232 if ((hcsr & H_RST) == 0)
1233 dev_warn(dev->dev, "H_RST is not set = 0x%08X", hcsr);
1234
1235 if ((hcsr & H_RDY) == H_RDY)
1236 dev_warn(dev->dev, "H_RDY is not cleared 0x%08X", hcsr);
1237
1238 if (!intr_enable) {
1239 mei_me_hw_reset_release(dev);
1240 if (hw->d0i3_supported) {
1241 ret = mei_me_d0i3_enter(dev);
1242 if (ret)
1243 return ret;
1244 }
1245 }
1246 return 0;
1247}
1248
1249/**
1250 * mei_me_irq_quick_handler - The ISR of the MEI device
1251 *
1252 * @irq: The irq number
1253 * @dev_id: pointer to the device structure
1254 *
1255 * Return: irqreturn_t
1256 */
1257irqreturn_t mei_me_irq_quick_handler(int irq, void *dev_id)
1258{
1259 struct mei_device *dev = (struct mei_device *)dev_id;
1260 u32 hcsr;
1261
1262 hcsr = mei_hcsr_read(dev);
1263 if (!me_intr_src(hcsr))
1264 return IRQ_NONE;
1265
1266 dev_dbg(dev->dev, "interrupt source 0x%08X\n", me_intr_src(hcsr));
1267
1268 /* disable interrupts on device */
1269 me_intr_disable(dev, hcsr);
1270 return IRQ_WAKE_THREAD;
1271}
1272EXPORT_SYMBOL_GPL(mei_me_irq_quick_handler);
1273
1274/**
1275 * mei_me_irq_thread_handler - function called after ISR to handle the interrupt
1276 * processing.
1277 *
1278 * @irq: The irq number
1279 * @dev_id: pointer to the device structure
1280 *
1281 * Return: irqreturn_t
1282 *
1283 */
1284irqreturn_t mei_me_irq_thread_handler(int irq, void *dev_id)
1285{
1286 struct mei_device *dev = (struct mei_device *) dev_id;
1287 struct list_head cmpl_list;
1288 s32 slots;
1289 u32 hcsr;
1290 int rets = 0;
1291
1292 dev_dbg(dev->dev, "function called after ISR to handle the interrupt processing.\n");
1293 /* initialize our complete list */
1294 mutex_lock(&dev->device_lock);
1295
1296 hcsr = mei_hcsr_read(dev);
1297 me_intr_clear(dev, hcsr);
1298
1299 INIT_LIST_HEAD(&cmpl_list);
1300
1301 /* check if ME wants a reset */
1302 if (!mei_hw_is_ready(dev) && dev->dev_state != MEI_DEV_RESETTING) {
1303 dev_warn(dev->dev, "FW not ready: resetting: dev_state = %d pxp = %d\n",
1304 dev->dev_state, dev->pxp_mode);
1305 if (dev->dev_state == MEI_DEV_POWERING_DOWN ||
1306 dev->dev_state == MEI_DEV_POWER_DOWN)
1307 mei_cl_all_disconnect(dev);
1308 else if (dev->dev_state != MEI_DEV_DISABLED)
1309 schedule_work(&dev->reset_work);
1310 goto end;
1311 }
1312
1313 if (mei_me_hw_is_resetting(dev))
1314 mei_hcsr_set_hig(dev);
1315
1316 mei_me_pg_intr(dev, me_intr_src(hcsr));
1317
1318 /* check if we need to start the dev */
1319 if (!mei_host_is_ready(dev)) {
1320 if (mei_hw_is_ready(dev)) {
1321 dev_dbg(dev->dev, "we need to start the dev.\n");
1322 dev->recvd_hw_ready = true;
1323 wake_up(&dev->wait_hw_ready);
1324 } else {
1325 dev_dbg(dev->dev, "Spurious Interrupt\n");
1326 }
1327 goto end;
1328 }
1329 /* check slots available for reading */
1330 slots = mei_count_full_read_slots(dev);
1331 while (slots > 0) {
1332 dev_dbg(dev->dev, "slots to read = %08x\n", slots);
1333 rets = mei_irq_read_handler(dev, &cmpl_list, &slots);
1334 /* There is a race between ME write and interrupt delivery:
1335 * Not all data is always available immediately after the
1336 * interrupt, so try to read again on the next interrupt.
1337 */
1338 if (rets == -ENODATA)
1339 break;
1340
1341 if (rets) {
1342 dev_err(dev->dev, "mei_irq_read_handler ret = %d, state = %d.\n",
1343 rets, dev->dev_state);
1344 if (dev->dev_state != MEI_DEV_RESETTING &&
1345 dev->dev_state != MEI_DEV_DISABLED &&
1346 dev->dev_state != MEI_DEV_POWERING_DOWN &&
1347 dev->dev_state != MEI_DEV_POWER_DOWN)
1348 schedule_work(&dev->reset_work);
1349 goto end;
1350 }
1351 }
1352
1353 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1354
1355 /*
1356 * During PG handshake only allowed write is the replay to the
1357 * PG exit message, so block calling write function
1358 * if the pg event is in PG handshake
1359 */
1360 if (dev->pg_event != MEI_PG_EVENT_WAIT &&
1361 dev->pg_event != MEI_PG_EVENT_RECEIVED) {
1362 rets = mei_irq_write_handler(dev, &cmpl_list);
1363 dev->hbuf_is_ready = mei_hbuf_is_ready(dev);
1364 }
1365
1366 mei_irq_compl_handler(dev, &cmpl_list);
1367
1368end:
1369 dev_dbg(dev->dev, "interrupt thread end ret = %d\n", rets);
1370 mei_me_intr_enable(dev);
1371 mutex_unlock(&dev->device_lock);
1372 return IRQ_HANDLED;
1373}
1374EXPORT_SYMBOL_GPL(mei_me_irq_thread_handler);
1375
1376#define MEI_POLLING_TIMEOUT_ACTIVE 100
1377#define MEI_POLLING_TIMEOUT_IDLE 500
1378
1379/**
1380 * mei_me_polling_thread - interrupt register polling thread
1381 *
1382 * The thread monitors the interrupt source register and calls
1383 * mei_me_irq_thread_handler() to handle the firmware
1384 * input.
1385 *
1386 * The function polls in MEI_POLLING_TIMEOUT_ACTIVE timeout
1387 * in case there was an event, in idle case the polling
1388 * time increases yet again by MEI_POLLING_TIMEOUT_ACTIVE
1389 * up to MEI_POLLING_TIMEOUT_IDLE.
1390 *
1391 * @_dev: mei device
1392 *
1393 * Return: always 0
1394 */
1395int mei_me_polling_thread(void *_dev)
1396{
1397 struct mei_device *dev = _dev;
1398 irqreturn_t irq_ret;
1399 long polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
1400
1401 dev_dbg(dev->dev, "kernel thread is running\n");
1402 while (!kthread_should_stop()) {
1403 struct mei_me_hw *hw = to_me_hw(dev);
1404 u32 hcsr;
1405
1406 wait_event_timeout(hw->wait_active,
1407 hw->is_active || kthread_should_stop(),
1408 msecs_to_jiffies(MEI_POLLING_TIMEOUT_IDLE));
1409
1410 if (kthread_should_stop())
1411 break;
1412
1413 hcsr = mei_hcsr_read(dev);
1414 if (me_intr_src(hcsr)) {
1415 polling_timeout = MEI_POLLING_TIMEOUT_ACTIVE;
1416 irq_ret = mei_me_irq_thread_handler(1, dev);
1417 if (irq_ret != IRQ_HANDLED)
1418 dev_err(dev->dev, "irq_ret %d\n", irq_ret);
1419 } else {
1420 /*
1421 * Increase timeout by MEI_POLLING_TIMEOUT_ACTIVE
1422 * up to MEI_POLLING_TIMEOUT_IDLE
1423 */
1424 polling_timeout = clamp_val(polling_timeout + MEI_POLLING_TIMEOUT_ACTIVE,
1425 MEI_POLLING_TIMEOUT_ACTIVE,
1426 MEI_POLLING_TIMEOUT_IDLE);
1427 }
1428
1429 schedule_timeout_interruptible(msecs_to_jiffies(polling_timeout));
1430 }
1431
1432 return 0;
1433}
1434EXPORT_SYMBOL_GPL(mei_me_polling_thread);
1435
1436static const struct mei_hw_ops mei_me_hw_ops = {
1437
1438 .trc_status = mei_me_trc_status,
1439 .fw_status = mei_me_fw_status,
1440 .pg_state = mei_me_pg_state,
1441
1442 .host_is_ready = mei_me_host_is_ready,
1443
1444 .hw_is_ready = mei_me_hw_is_ready,
1445 .hw_reset = mei_me_hw_reset,
1446 .hw_config = mei_me_hw_config,
1447 .hw_start = mei_me_hw_start,
1448
1449 .pg_in_transition = mei_me_pg_in_transition,
1450 .pg_is_enabled = mei_me_pg_is_enabled,
1451
1452 .intr_clear = mei_me_intr_clear,
1453 .intr_enable = mei_me_intr_enable,
1454 .intr_disable = mei_me_intr_disable,
1455 .synchronize_irq = mei_me_synchronize_irq,
1456
1457 .hbuf_free_slots = mei_me_hbuf_empty_slots,
1458 .hbuf_is_ready = mei_me_hbuf_is_empty,
1459 .hbuf_depth = mei_me_hbuf_depth,
1460
1461 .write = mei_me_hbuf_write,
1462
1463 .rdbuf_full_slots = mei_me_count_full_read_slots,
1464 .read_hdr = mei_me_mecbrw_read,
1465 .read = mei_me_read_slots
1466};
1467
1468/**
1469 * mei_me_fw_type_nm() - check for nm sku
1470 *
1471 * Read ME FW Status register to check for the Node Manager (NM) Firmware.
1472 * The NM FW is only signaled in PCI function 0.
1473 * __Note__: Deprecated by PCH8 and newer.
1474 *
1475 * @pdev: pci device
1476 *
1477 * Return: true in case of NM firmware
1478 */
1479static bool mei_me_fw_type_nm(const struct pci_dev *pdev)
1480{
1481 u32 reg;
1482 unsigned int devfn;
1483
1484 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1485 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_2, ®);
1486 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_2", PCI_CFG_HFS_2, reg);
1487 /* make sure that bit 9 (NM) is up and bit 10 (DM) is down */
1488 return (reg & 0x600) == 0x200;
1489}
1490
1491#define MEI_CFG_FW_NM \
1492 .quirk_probe = mei_me_fw_type_nm
1493
1494/**
1495 * mei_me_fw_type_sps_4() - check for sps 4.0 sku
1496 *
1497 * Read ME FW Status register to check for SPS Firmware.
1498 * The SPS FW is only signaled in the PCI function 0.
1499 * __Note__: Deprecated by SPS 5.0 and newer.
1500 *
1501 * @pdev: pci device
1502 *
1503 * Return: true in case of SPS firmware
1504 */
1505static bool mei_me_fw_type_sps_4(const struct pci_dev *pdev)
1506{
1507 u32 reg;
1508 unsigned int devfn;
1509
1510 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1511 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_1, ®);
1512 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_1", PCI_CFG_HFS_1, reg);
1513 return (reg & PCI_CFG_HFS_1_OPMODE_MSK) == PCI_CFG_HFS_1_OPMODE_SPS;
1514}
1515
1516#define MEI_CFG_FW_SPS_4 \
1517 .quirk_probe = mei_me_fw_type_sps_4
1518
1519/**
1520 * mei_me_fw_type_sps_ign() - check for sps or ign sku
1521 *
1522 * Read ME FW Status register to check for SPS or IGN Firmware.
1523 * The SPS/IGN FW is only signaled in pci function 0
1524 *
1525 * @pdev: pci device
1526 *
1527 * Return: true in case of SPS/IGN firmware
1528 */
1529static bool mei_me_fw_type_sps_ign(const struct pci_dev *pdev)
1530{
1531 u32 reg;
1532 u32 fw_type;
1533 unsigned int devfn;
1534
1535 devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
1536 pci_bus_read_config_dword(pdev->bus, devfn, PCI_CFG_HFS_3, ®);
1537 trace_mei_pci_cfg_read(&pdev->dev, "PCI_CFG_HFS_3", PCI_CFG_HFS_3, reg);
1538 fw_type = (reg & PCI_CFG_HFS_3_FW_SKU_MSK);
1539
1540 dev_dbg(&pdev->dev, "fw type is %d\n", fw_type);
1541
1542 return fw_type == PCI_CFG_HFS_3_FW_SKU_IGN ||
1543 fw_type == PCI_CFG_HFS_3_FW_SKU_SPS;
1544}
1545
1546#define MEI_CFG_KIND_ITOUCH \
1547 .kind = "itouch"
1548
1549#define MEI_CFG_TYPE_GSC \
1550 .kind = "gsc"
1551
1552#define MEI_CFG_TYPE_GSCFI \
1553 .kind = "gscfi"
1554
1555#define MEI_CFG_FW_SPS_IGN \
1556 .quirk_probe = mei_me_fw_type_sps_ign
1557
1558#define MEI_CFG_FW_VER_SUPP \
1559 .fw_ver_supported = 1
1560
1561#define MEI_CFG_ICH_HFS \
1562 .fw_status.count = 0
1563
1564#define MEI_CFG_ICH10_HFS \
1565 .fw_status.count = 1, \
1566 .fw_status.status[0] = PCI_CFG_HFS_1
1567
1568#define MEI_CFG_PCH_HFS \
1569 .fw_status.count = 2, \
1570 .fw_status.status[0] = PCI_CFG_HFS_1, \
1571 .fw_status.status[1] = PCI_CFG_HFS_2
1572
1573#define MEI_CFG_PCH8_HFS \
1574 .fw_status.count = 6, \
1575 .fw_status.status[0] = PCI_CFG_HFS_1, \
1576 .fw_status.status[1] = PCI_CFG_HFS_2, \
1577 .fw_status.status[2] = PCI_CFG_HFS_3, \
1578 .fw_status.status[3] = PCI_CFG_HFS_4, \
1579 .fw_status.status[4] = PCI_CFG_HFS_5, \
1580 .fw_status.status[5] = PCI_CFG_HFS_6
1581
1582#define MEI_CFG_DMA_128 \
1583 .dma_size[DMA_DSCR_HOST] = SZ_128K, \
1584 .dma_size[DMA_DSCR_DEVICE] = SZ_128K, \
1585 .dma_size[DMA_DSCR_CTRL] = PAGE_SIZE
1586
1587#define MEI_CFG_TRC \
1588 .hw_trc_supported = 1
1589
1590/* ICH Legacy devices */
1591static const struct mei_cfg mei_me_ich_cfg = {
1592 MEI_CFG_ICH_HFS,
1593};
1594
1595/* ICH devices */
1596static const struct mei_cfg mei_me_ich10_cfg = {
1597 MEI_CFG_ICH10_HFS,
1598};
1599
1600/* PCH6 devices */
1601static const struct mei_cfg mei_me_pch6_cfg = {
1602 MEI_CFG_PCH_HFS,
1603};
1604
1605/* PCH7 devices */
1606static const struct mei_cfg mei_me_pch7_cfg = {
1607 MEI_CFG_PCH_HFS,
1608 MEI_CFG_FW_VER_SUPP,
1609};
1610
1611/* PCH Cougar Point and Patsburg with quirk for Node Manager exclusion */
1612static const struct mei_cfg mei_me_pch_cpt_pbg_cfg = {
1613 MEI_CFG_PCH_HFS,
1614 MEI_CFG_FW_VER_SUPP,
1615 MEI_CFG_FW_NM,
1616};
1617
1618/* PCH8 Lynx Point and newer devices */
1619static const struct mei_cfg mei_me_pch8_cfg = {
1620 MEI_CFG_PCH8_HFS,
1621 MEI_CFG_FW_VER_SUPP,
1622};
1623
1624/* PCH8 Lynx Point and newer devices - iTouch */
1625static const struct mei_cfg mei_me_pch8_itouch_cfg = {
1626 MEI_CFG_KIND_ITOUCH,
1627 MEI_CFG_PCH8_HFS,
1628 MEI_CFG_FW_VER_SUPP,
1629};
1630
1631/* PCH8 Lynx Point with quirk for SPS Firmware exclusion */
1632static const struct mei_cfg mei_me_pch8_sps_4_cfg = {
1633 MEI_CFG_PCH8_HFS,
1634 MEI_CFG_FW_VER_SUPP,
1635 MEI_CFG_FW_SPS_4,
1636};
1637
1638/* LBG with quirk for SPS (4.0) Firmware exclusion */
1639static const struct mei_cfg mei_me_pch12_sps_4_cfg = {
1640 MEI_CFG_PCH8_HFS,
1641 MEI_CFG_FW_VER_SUPP,
1642 MEI_CFG_FW_SPS_4,
1643};
1644
1645/* Cannon Lake and newer devices */
1646static const struct mei_cfg mei_me_pch12_cfg = {
1647 MEI_CFG_PCH8_HFS,
1648 MEI_CFG_FW_VER_SUPP,
1649 MEI_CFG_DMA_128,
1650};
1651
1652/* Cannon Lake with quirk for SPS 5.0 and newer Firmware exclusion */
1653static const struct mei_cfg mei_me_pch12_sps_cfg = {
1654 MEI_CFG_PCH8_HFS,
1655 MEI_CFG_FW_VER_SUPP,
1656 MEI_CFG_DMA_128,
1657 MEI_CFG_FW_SPS_IGN,
1658};
1659
1660/* Cannon Lake itouch with quirk for SPS 5.0 and newer Firmware exclusion
1661 * w/o DMA support.
1662 */
1663static const struct mei_cfg mei_me_pch12_itouch_sps_cfg = {
1664 MEI_CFG_KIND_ITOUCH,
1665 MEI_CFG_PCH8_HFS,
1666 MEI_CFG_FW_VER_SUPP,
1667 MEI_CFG_FW_SPS_IGN,
1668};
1669
1670/* Tiger Lake and newer devices */
1671static const struct mei_cfg mei_me_pch15_cfg = {
1672 MEI_CFG_PCH8_HFS,
1673 MEI_CFG_FW_VER_SUPP,
1674 MEI_CFG_DMA_128,
1675 MEI_CFG_TRC,
1676};
1677
1678/* Tiger Lake with quirk for SPS 5.0 and newer Firmware exclusion */
1679static const struct mei_cfg mei_me_pch15_sps_cfg = {
1680 MEI_CFG_PCH8_HFS,
1681 MEI_CFG_FW_VER_SUPP,
1682 MEI_CFG_DMA_128,
1683 MEI_CFG_TRC,
1684 MEI_CFG_FW_SPS_IGN,
1685};
1686
1687/* Graphics System Controller */
1688static const struct mei_cfg mei_me_gsc_cfg = {
1689 MEI_CFG_TYPE_GSC,
1690 MEI_CFG_PCH8_HFS,
1691 MEI_CFG_FW_VER_SUPP,
1692};
1693
1694/* Graphics System Controller Firmware Interface */
1695static const struct mei_cfg mei_me_gscfi_cfg = {
1696 MEI_CFG_TYPE_GSCFI,
1697 MEI_CFG_PCH8_HFS,
1698 MEI_CFG_FW_VER_SUPP,
1699};
1700
1701/*
1702 * mei_cfg_list - A list of platform platform specific configurations.
1703 * Note: has to be synchronized with enum mei_cfg_idx.
1704 */
1705static const struct mei_cfg *const mei_cfg_list[] = {
1706 [MEI_ME_UNDEF_CFG] = NULL,
1707 [MEI_ME_ICH_CFG] = &mei_me_ich_cfg,
1708 [MEI_ME_ICH10_CFG] = &mei_me_ich10_cfg,
1709 [MEI_ME_PCH6_CFG] = &mei_me_pch6_cfg,
1710 [MEI_ME_PCH7_CFG] = &mei_me_pch7_cfg,
1711 [MEI_ME_PCH_CPT_PBG_CFG] = &mei_me_pch_cpt_pbg_cfg,
1712 [MEI_ME_PCH8_CFG] = &mei_me_pch8_cfg,
1713 [MEI_ME_PCH8_ITOUCH_CFG] = &mei_me_pch8_itouch_cfg,
1714 [MEI_ME_PCH8_SPS_4_CFG] = &mei_me_pch8_sps_4_cfg,
1715 [MEI_ME_PCH12_CFG] = &mei_me_pch12_cfg,
1716 [MEI_ME_PCH12_SPS_4_CFG] = &mei_me_pch12_sps_4_cfg,
1717 [MEI_ME_PCH12_SPS_CFG] = &mei_me_pch12_sps_cfg,
1718 [MEI_ME_PCH12_SPS_ITOUCH_CFG] = &mei_me_pch12_itouch_sps_cfg,
1719 [MEI_ME_PCH15_CFG] = &mei_me_pch15_cfg,
1720 [MEI_ME_PCH15_SPS_CFG] = &mei_me_pch15_sps_cfg,
1721 [MEI_ME_GSC_CFG] = &mei_me_gsc_cfg,
1722 [MEI_ME_GSCFI_CFG] = &mei_me_gscfi_cfg,
1723};
1724
1725const struct mei_cfg *mei_me_get_cfg(kernel_ulong_t idx)
1726{
1727 BUILD_BUG_ON(ARRAY_SIZE(mei_cfg_list) != MEI_ME_NUM_CFG);
1728
1729 if (idx >= MEI_ME_NUM_CFG)
1730 return NULL;
1731
1732 return mei_cfg_list[idx];
1733}
1734EXPORT_SYMBOL_GPL(mei_me_get_cfg);
1735
1736/**
1737 * mei_me_dev_init - allocates and initializes the mei device structure
1738 *
1739 * @parent: device associated with physical device (pci/platform)
1740 * @cfg: per device generation config
1741 * @slow_fw: configure longer timeouts as FW is slow
1742 *
1743 * Return: The mei_device pointer on success, NULL on failure.
1744 */
1745struct mei_device *mei_me_dev_init(struct device *parent,
1746 const struct mei_cfg *cfg, bool slow_fw)
1747{
1748 struct mei_device *dev;
1749 struct mei_me_hw *hw;
1750 int i;
1751
1752 dev = devm_kzalloc(parent, sizeof(*dev) + sizeof(*hw), GFP_KERNEL);
1753 if (!dev)
1754 return NULL;
1755
1756 hw = to_me_hw(dev);
1757
1758 for (i = 0; i < DMA_DSCR_NUM; i++)
1759 dev->dr_dscr[i].size = cfg->dma_size[i];
1760
1761 mei_device_init(dev, parent, slow_fw, &mei_me_hw_ops);
1762 hw->cfg = cfg;
1763
1764 dev->fw_f_fw_ver_supported = cfg->fw_ver_supported;
1765
1766 dev->kind = cfg->kind;
1767
1768 return dev;
1769}
1770EXPORT_SYMBOL_GPL(mei_me_dev_init);