1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas RIIC driver
  4 *
  5 * Copyright (C) 2013 Wolfram Sang <wsa@sang-engineering.com>
  6 * Copyright (C) 2013 Renesas Solutions Corp.
  7 */
  8
  9/*
 10 * This i2c core has a lot of interrupts, namely 8. We use their chaining as
 11 * some kind of state machine.
 12 *
 13 * 1) The main xfer routine kicks off a transmission by putting the start bit
 14 * (or repeated start) on the bus and enabling the transmit interrupt (TIE)
 15 * since we need to send the slave address + RW bit in every case.
 16 *
 17 * 2) TIE sends slave address + RW bit and selects how to continue.
 18 *
 19 * 3a) Write case: We keep utilizing TIE as long as we have data to send. If we
 20 * are done, we switch over to the transmission done interrupt (TEIE) and mark
 21 * the message as completed (includes sending STOP) there.
 22 *
 23 * 3b) Read case: We switch over to receive interrupt (RIE). One dummy read is
 24 * needed to start clocking, then we keep receiving until we are done. Note
 25 * that we use the RDRFS mode all the time, i.e. we ACK/NACK every byte by
 26 * writing to the ACKBT bit. I tried using the RDRFS mode only at the end of a
 27 * message to create the final NACK as sketched in the datasheet. This caused
 28 * some subtle races (when byte n was processed and byte n+1 was already
 29 * waiting), though, and I started with the safe approach.
 30 *
 31 * 4) If we got a NACK somewhere, we flag the error and stop the transmission
 32 * via NAKIE.
 33 *
 34 * Also check the comments in the interrupt routines for some gory details.
 35 */
 36
 37#include <linux/clk.h>
 38#include <linux/completion.h>
 39#include <linux/err.h>
 40#include <linux/i2c.h>
 41#include <linux/interrupt.h>
 42#include <linux/io.h>
 43#include <linux/module.h>
 44#include <linux/of.h>
 45#include <linux/of_device.h>
 46#include <linux/platform_device.h>
 47#include <linux/pm_runtime.h>
 48#include <linux/reset.h>
 49
 50#define RIIC_ICCR1	0x00
 51#define RIIC_ICCR2	0x04
 52#define RIIC_ICMR1	0x08
 53#define RIIC_ICMR3	0x10
 54#define RIIC_ICSER	0x18
 55#define RIIC_ICIER	0x1c
 56#define RIIC_ICSR2	0x24
 57#define RIIC_ICBRL	0x34
 58#define RIIC_ICBRH	0x38
 59#define RIIC_ICDRT	0x3c
 60#define RIIC_ICDRR	0x40
 61
 62#define ICCR1_ICE	0x80
 63#define ICCR1_IICRST	0x40
 64#define ICCR1_SOWP	0x10
 65
 66#define ICCR2_BBSY	0x80
 67#define ICCR2_SP	0x08
 68#define ICCR2_RS	0x04
 69#define ICCR2_ST	0x02
 70
 71#define ICMR1_CKS_MASK	0x70
 72#define ICMR1_BCWP	0x08
 73#define ICMR1_CKS(_x)	((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP)
 74
 75#define ICMR3_RDRFS	0x20
 76#define ICMR3_ACKWP	0x10
 77#define ICMR3_ACKBT	0x08
 78
 79#define ICIER_TIE	0x80
 80#define ICIER_TEIE	0x40
 81#define ICIER_RIE	0x20
 82#define ICIER_NAKIE	0x10
 83#define ICIER_SPIE	0x08
 84
 85#define ICSR2_NACKF	0x10
 86
 87#define ICBR_RESERVED	0xe0 /* Should be 1 on writes */
 88
 89#define RIIC_INIT_MSG	-1
 90
 91struct riic_dev {
 92	void __iomem *base;
 93	u8 *buf;
 94	struct i2c_msg *msg;
 95	int bytes_left;
 96	int err;
 97	int is_last;
 98	struct completion msg_done;
 99	struct i2c_adapter adapter;
100	struct clk *clk;
101};
102
103struct riic_irq_desc {
104	int res_num;
105	irq_handler_t isr;
106	char *name;
107};
108
109static inline void riic_clear_set_bit(struct riic_dev *riic, u8 clear, u8 set, u8 reg)
110{
111	writeb((readb(riic->base + reg) & ~clear) | set, riic->base + reg);
112}
113
114static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
115{
116	struct riic_dev *riic = i2c_get_adapdata(adap);
117	unsigned long time_left;
118	int i;
119	u8 start_bit;
120
121	pm_runtime_get_sync(adap->dev.parent);
122
123	if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) {
124		riic->err = -EBUSY;
125		goto out;
126	}
127
128	reinit_completion(&riic->msg_done);
129	riic->err = 0;
130
131	writeb(0, riic->base + RIIC_ICSR2);
132
133	for (i = 0, start_bit = ICCR2_ST; i < num; i++) {
134		riic->bytes_left = RIIC_INIT_MSG;
135		riic->buf = msgs[i].buf;
136		riic->msg = &msgs[i];
137		riic->is_last = (i == num - 1);
138
139		writeb(ICIER_NAKIE | ICIER_TIE, riic->base + RIIC_ICIER);
140
141		writeb(start_bit, riic->base + RIIC_ICCR2);
142
143		time_left = wait_for_completion_timeout(&riic->msg_done, riic->adapter.timeout);
144		if (time_left == 0)
145			riic->err = -ETIMEDOUT;
146
147		if (riic->err)
148			break;
149
150		start_bit = ICCR2_RS;
151	}
152
153 out:
154	pm_runtime_put(adap->dev.parent);
155
156	return riic->err ?: num;
157}
158
159static irqreturn_t riic_tdre_isr(int irq, void *data)
160{
161	struct riic_dev *riic = data;
162	u8 val;
163
164	if (!riic->bytes_left)
165		return IRQ_NONE;
166
167	if (riic->bytes_left == RIIC_INIT_MSG) {
168		if (riic->msg->flags & I2C_M_RD)
169			/* On read, switch over to receive interrupt */
170			riic_clear_set_bit(riic, ICIER_TIE, ICIER_RIE, RIIC_ICIER);
171		else
172			/* On write, initialize length */
173			riic->bytes_left = riic->msg->len;
174
175		val = i2c_8bit_addr_from_msg(riic->msg);
176	} else {
177		val = *riic->buf;
178		riic->buf++;
179		riic->bytes_left--;
180	}
181
182	/*
183	 * Switch to transmission ended interrupt when done. Do check here
184	 * after bytes_left was initialized to support SMBUS_QUICK (new msg has
185	 * 0 length then)
186	 */
187	if (riic->bytes_left == 0)
188		riic_clear_set_bit(riic, ICIER_TIE, ICIER_TEIE, RIIC_ICIER);
189
190	/*
191	 * This acks the TIE interrupt. We get another TIE immediately if our
192	 * value could be moved to the shadow shift register right away. So
193	 * this must be after updates to ICIER (where we want to disable TIE)!
194	 */
195	writeb(val, riic->base + RIIC_ICDRT);
196
197	return IRQ_HANDLED;
198}
199
200static irqreturn_t riic_tend_isr(int irq, void *data)
201{
202	struct riic_dev *riic = data;
203
204	if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) {
205		/* We got a NACKIE */
206		readb(riic->base + RIIC_ICDRR);	/* dummy read */
207		riic_clear_set_bit(riic, ICSR2_NACKF, 0, RIIC_ICSR2);
208		riic->err = -ENXIO;
209	} else if (riic->bytes_left) {
210		return IRQ_NONE;
211	}
212
213	if (riic->is_last || riic->err) {
214		riic_clear_set_bit(riic, ICIER_TEIE, ICIER_SPIE, RIIC_ICIER);
215		writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
216	} else {
217		/* Transfer is complete, but do not send STOP */
218		riic_clear_set_bit(riic, ICIER_TEIE, 0, RIIC_ICIER);
219		complete(&riic->msg_done);
220	}
221
222	return IRQ_HANDLED;
223}
224
225static irqreturn_t riic_rdrf_isr(int irq, void *data)
226{
227	struct riic_dev *riic = data;
228
229	if (!riic->bytes_left)
230		return IRQ_NONE;
231
232	if (riic->bytes_left == RIIC_INIT_MSG) {
233		riic->bytes_left = riic->msg->len;
234		readb(riic->base + RIIC_ICDRR);	/* dummy read */
235		return IRQ_HANDLED;
236	}
237
238	if (riic->bytes_left == 1) {
239		/* STOP must come before we set ACKBT! */
240		if (riic->is_last) {
241			riic_clear_set_bit(riic, 0, ICIER_SPIE, RIIC_ICIER);
242			writeb(ICCR2_SP, riic->base + RIIC_ICCR2);
243		}
244
245		riic_clear_set_bit(riic, 0, ICMR3_ACKBT, RIIC_ICMR3);
246
247	} else {
248		riic_clear_set_bit(riic, ICMR3_ACKBT, 0, RIIC_ICMR3);
249	}
250
251	/* Reading acks the RIE interrupt */
252	*riic->buf = readb(riic->base + RIIC_ICDRR);
253	riic->buf++;
254	riic->bytes_left--;
255
256	return IRQ_HANDLED;
257}
258
259static irqreturn_t riic_stop_isr(int irq, void *data)
260{
261	struct riic_dev *riic = data;
262
263	/* read back registers to confirm writes have fully propagated */
264	writeb(0, riic->base + RIIC_ICSR2);
265	readb(riic->base + RIIC_ICSR2);
266	writeb(0, riic->base + RIIC_ICIER);
267	readb(riic->base + RIIC_ICIER);
268
269	complete(&riic->msg_done);
270
271	return IRQ_HANDLED;
272}
273
274static u32 riic_func(struct i2c_adapter *adap)
275{
276	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
277}
278
279static const struct i2c_algorithm riic_algo = {
280	.master_xfer	= riic_xfer,
281	.functionality	= riic_func,
282};
283
284static int riic_init_hw(struct riic_dev *riic, struct i2c_timings *t)
285{
286	int ret = 0;
287	unsigned long rate;
288	int total_ticks, cks, brl, brh;
289
290	pm_runtime_get_sync(riic->adapter.dev.parent);
291
292	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) {
293		dev_err(&riic->adapter.dev,
294			"unsupported bus speed (%dHz). %d max\n",
295			t->bus_freq_hz, I2C_MAX_FAST_MODE_FREQ);
296		ret = -EINVAL;
297		goto out;
298	}
299
300	rate = clk_get_rate(riic->clk);
301
302	/*
303	 * Assume the default register settings:
304	 *  FER.SCLE = 1 (SCL sync circuit enabled, adds 2 or 3 cycles)
305	 *  FER.NFE = 1 (noise circuit enabled)
306	 *  MR3.NF = 0 (1 cycle of noise filtered out)
307	 *
308	 * Freq (CKS=000) = (I2CCLK + tr + tf)/ (BRH + 3 + 1) + (BRL + 3 + 1)
309	 * Freq (CKS!=000) = (I2CCLK + tr + tf)/ (BRH + 2 + 1) + (BRL + 2 + 1)
310	 */
311
312	/*
313	 * Determine reference clock rate. We must be able to get the desired
314	 * frequency with only 62 clock ticks max (31 high, 31 low).
315	 * Aim for a duty of 60% LOW, 40% HIGH.
316	 */
317	total_ticks = DIV_ROUND_UP(rate, t->bus_freq_hz);
318
319	for (cks = 0; cks < 7; cks++) {
320		/*
321		 * 60% low time must be less than BRL + 2 + 1
322		 * BRL max register value is 0x1F.
323		 */
324		brl = ((total_ticks * 6) / 10);
325		if (brl <= (0x1F + 3))
326			break;
327
328		total_ticks /= 2;
329		rate /= 2;
330	}
331
332	if (brl > (0x1F + 3)) {
333		dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n",
334			(unsigned long)t->bus_freq_hz);
335		ret = -EINVAL;
336		goto out;
337	}
338
339	brh = total_ticks - brl;
340
341	/* Remove automatic clock ticks for sync circuit and NF */
342	if (cks == 0) {
343		brl -= 4;
344		brh -= 4;
345	} else {
346		brl -= 3;
347		brh -= 3;
348	}
349
350	/*
351	 * Remove clock ticks for rise and fall times. Convert ns to clock
352	 * ticks.
353	 */
354	brl -= t->scl_fall_ns / (1000000000 / rate);
355	brh -= t->scl_rise_ns / (1000000000 / rate);
356
357	/* Adjust for min register values for when SCLE=1 and NFE=1 */
358	if (brl < 1)
359		brl = 1;
360	if (brh < 1)
361		brh = 1;
362
363	pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n",
364		 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6),
365		 t->scl_fall_ns / (1000000000 / rate),
366		 t->scl_rise_ns / (1000000000 / rate), cks, brl, brh);
367
368	/* Changing the order of accessing IICRST and ICE may break things! */
369	writeb(ICCR1_IICRST | ICCR1_SOWP, riic->base + RIIC_ICCR1);
370	riic_clear_set_bit(riic, 0, ICCR1_ICE, RIIC_ICCR1);
371
372	writeb(ICMR1_CKS(cks), riic->base + RIIC_ICMR1);
373	writeb(brh | ICBR_RESERVED, riic->base + RIIC_ICBRH);
374	writeb(brl | ICBR_RESERVED, riic->base + RIIC_ICBRL);
375
376	writeb(0, riic->base + RIIC_ICSER);
377	writeb(ICMR3_ACKWP | ICMR3_RDRFS, riic->base + RIIC_ICMR3);
378
379	riic_clear_set_bit(riic, ICCR1_IICRST, 0, RIIC_ICCR1);
380
381out:
382	pm_runtime_put(riic->adapter.dev.parent);
383	return ret;
384}
385
386static struct riic_irq_desc riic_irqs[] = {
387	{ .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" },
388	{ .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" },
389	{ .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" },
390	{ .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" },
391	{ .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" },
392};
393
394static void riic_reset_control_assert(void *data)
395{
396	reset_control_assert(data);
397}
398
399static int riic_i2c_probe(struct platform_device *pdev)
400{
401	struct riic_dev *riic;
402	struct i2c_adapter *adap;
403	struct i2c_timings i2c_t;
404	struct reset_control *rstc;
405	int i, ret;
406
407	riic = devm_kzalloc(&pdev->dev, sizeof(*riic), GFP_KERNEL);
408	if (!riic)
409		return -ENOMEM;
410
411	riic->base = devm_platform_ioremap_resource(pdev, 0);
412	if (IS_ERR(riic->base))
413		return PTR_ERR(riic->base);
414
415	riic->clk = devm_clk_get(&pdev->dev, NULL);
416	if (IS_ERR(riic->clk)) {
417		dev_err(&pdev->dev, "missing controller clock");
418		return PTR_ERR(riic->clk);
419	}
420
421	rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
422	if (IS_ERR(rstc))
423		return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
424				     "Error: missing reset ctrl\n");
425
426	ret = reset_control_deassert(rstc);
427	if (ret)
428		return ret;
429
430	ret = devm_add_action_or_reset(&pdev->dev, riic_reset_control_assert, rstc);
431	if (ret)
432		return ret;
433
434	for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) {
435		ret = platform_get_irq(pdev, riic_irqs[i].res_num);
436		if (ret < 0)
437			return ret;
438
439		ret = devm_request_irq(&pdev->dev, ret, riic_irqs[i].isr,
440				       0, riic_irqs[i].name, riic);
441		if (ret) {
442			dev_err(&pdev->dev, "failed to request irq %s\n", riic_irqs[i].name);
443			return ret;
444		}
445	}
446
447	adap = &riic->adapter;
448	i2c_set_adapdata(adap, riic);
449	strscpy(adap->name, "Renesas RIIC adapter", sizeof(adap->name));
450	adap->owner = THIS_MODULE;
451	adap->algo = &riic_algo;
452	adap->dev.parent = &pdev->dev;
453	adap->dev.of_node = pdev->dev.of_node;
454
455	init_completion(&riic->msg_done);
456
457	i2c_parse_fw_timings(&pdev->dev, &i2c_t, true);
458
459	pm_runtime_enable(&pdev->dev);
460
461	ret = riic_init_hw(riic, &i2c_t);
462	if (ret)
463		goto out;
464
465	ret = i2c_add_adapter(adap);
466	if (ret)
467		goto out;
468
469	platform_set_drvdata(pdev, riic);
470
471	dev_info(&pdev->dev, "registered with %dHz bus speed\n",
472		 i2c_t.bus_freq_hz);
473	return 0;
474
475out:
476	pm_runtime_disable(&pdev->dev);
477	return ret;
478}
479
480static int riic_i2c_remove(struct platform_device *pdev)
481{
482	struct riic_dev *riic = platform_get_drvdata(pdev);
483
484	pm_runtime_get_sync(&pdev->dev);
485	writeb(0, riic->base + RIIC_ICIER);
486	pm_runtime_put(&pdev->dev);
487	i2c_del_adapter(&riic->adapter);
488	pm_runtime_disable(&pdev->dev);
489
490	return 0;
491}
492
493static const struct of_device_id riic_i2c_dt_ids[] = {
494	{ .compatible = "renesas,riic-rz", },
495	{ /* Sentinel */ },
496};
497
498static struct platform_driver riic_i2c_driver = {
499	.probe		= riic_i2c_probe,
500	.remove		= riic_i2c_remove,
501	.driver		= {
502		.name	= "i2c-riic",
503		.of_match_table = riic_i2c_dt_ids,
504	},
505};
506
507module_platform_driver(riic_i2c_driver);
508
509MODULE_DESCRIPTION("Renesas RIIC adapter");
510MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
511MODULE_LICENSE("GPL v2");
512MODULE_DEVICE_TABLE(of, riic_i2c_dt_ids);