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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight Program Flow Trace driver
6 */
7
8#include <linux/kernel.h>
9#include <linux/moduleparam.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <linux/fs.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include <linux/smp.h>
19#include <linux/sysfs.h>
20#include <linux/stat.h>
21#include <linux/pm_runtime.h>
22#include <linux/cpu.h>
23#include <linux/of.h>
24#include <linux/coresight.h>
25#include <linux/coresight-pmu.h>
26#include <linux/amba/bus.h>
27#include <linux/seq_file.h>
28#include <linux/uaccess.h>
29#include <linux/clk.h>
30#include <linux/perf_event.h>
31#include <asm/sections.h>
32
33#include "coresight-etm.h"
34#include "coresight-etm-perf.h"
35
36/*
37 * Not really modular but using module_param is the easiest way to
38 * remain consistent with existing use cases for now.
39 */
40static int boot_enable;
41module_param_named(boot_enable, boot_enable, int, S_IRUGO);
42
43static struct etm_drvdata *etmdrvdata[NR_CPUS];
44
45static enum cpuhp_state hp_online;
46
47/*
48 * Memory mapped writes to clear os lock are not supported on some processors
49 * and OS lock must be unlocked before any memory mapped access on such
50 * processors, otherwise memory mapped reads/writes will be invalid.
51 */
52static void etm_os_unlock(struct etm_drvdata *drvdata)
53{
54 /* Writing any value to ETMOSLAR unlocks the trace registers */
55 etm_writel(drvdata, 0x0, ETMOSLAR);
56 drvdata->os_unlock = true;
57 isb();
58}
59
60static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
61{
62 u32 etmcr;
63
64 /* Ensure pending cp14 accesses complete before setting pwrdwn */
65 mb();
66 isb();
67 etmcr = etm_readl(drvdata, ETMCR);
68 etmcr |= ETMCR_PWD_DWN;
69 etm_writel(drvdata, etmcr, ETMCR);
70}
71
72static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
73{
74 u32 etmcr;
75
76 etmcr = etm_readl(drvdata, ETMCR);
77 etmcr &= ~ETMCR_PWD_DWN;
78 etm_writel(drvdata, etmcr, ETMCR);
79 /* Ensure pwrup completes before subsequent cp14 accesses */
80 mb();
81 isb();
82}
83
84static void etm_set_pwrup(struct etm_drvdata *drvdata)
85{
86 u32 etmpdcr;
87
88 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
89 etmpdcr |= ETMPDCR_PWD_UP;
90 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
91 /* Ensure pwrup completes before subsequent cp14 accesses */
92 mb();
93 isb();
94}
95
96static void etm_clr_pwrup(struct etm_drvdata *drvdata)
97{
98 u32 etmpdcr;
99
100 /* Ensure pending cp14 accesses complete before clearing pwrup */
101 mb();
102 isb();
103 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
104 etmpdcr &= ~ETMPDCR_PWD_UP;
105 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
106}
107
108/**
109 * coresight_timeout_etm - loop until a bit has changed to a specific state.
110 * @drvdata: etm's private data structure.
111 * @offset: address of a register, starting from @addr.
112 * @position: the position of the bit of interest.
113 * @value: the value the bit should have.
114 *
115 * Basically the same as @coresight_timeout except for the register access
116 * method where we have to account for CP14 configurations.
117
118 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
119 * TIMEOUT_US has elapsed, which ever happens first.
120 */
121
122static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
123 int position, int value)
124{
125 int i;
126 u32 val;
127
128 for (i = TIMEOUT_US; i > 0; i--) {
129 val = etm_readl(drvdata, offset);
130 /* Waiting on the bit to go from 0 to 1 */
131 if (value) {
132 if (val & BIT(position))
133 return 0;
134 /* Waiting on the bit to go from 1 to 0 */
135 } else {
136 if (!(val & BIT(position)))
137 return 0;
138 }
139
140 /*
141 * Delay is arbitrary - the specification doesn't say how long
142 * we are expected to wait. Extra check required to make sure
143 * we don't wait needlessly on the last iteration.
144 */
145 if (i - 1)
146 udelay(1);
147 }
148
149 return -EAGAIN;
150}
151
152
153static void etm_set_prog(struct etm_drvdata *drvdata)
154{
155 u32 etmcr;
156
157 etmcr = etm_readl(drvdata, ETMCR);
158 etmcr |= ETMCR_ETM_PRG;
159 etm_writel(drvdata, etmcr, ETMCR);
160 /*
161 * Recommended by spec for cp14 accesses to ensure etmcr write is
162 * complete before polling etmsr
163 */
164 isb();
165 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
166 dev_err(&drvdata->csdev->dev,
167 "%s: timeout observed when probing at offset %#x\n",
168 __func__, ETMSR);
169 }
170}
171
172static void etm_clr_prog(struct etm_drvdata *drvdata)
173{
174 u32 etmcr;
175
176 etmcr = etm_readl(drvdata, ETMCR);
177 etmcr &= ~ETMCR_ETM_PRG;
178 etm_writel(drvdata, etmcr, ETMCR);
179 /*
180 * Recommended by spec for cp14 accesses to ensure etmcr write is
181 * complete before polling etmsr
182 */
183 isb();
184 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
185 dev_err(&drvdata->csdev->dev,
186 "%s: timeout observed when probing at offset %#x\n",
187 __func__, ETMSR);
188 }
189}
190
191void etm_set_default(struct etm_config *config)
192{
193 int i;
194
195 if (WARN_ON_ONCE(!config))
196 return;
197
198 /*
199 * Taken verbatim from the TRM:
200 *
201 * To trace all memory:
202 * set bit [24] in register 0x009, the ETMTECR1, to 1
203 * set all other bits in register 0x009, the ETMTECR1, to 0
204 * set all bits in register 0x007, the ETMTECR2, to 0
205 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
206 */
207 config->enable_ctrl1 = ETMTECR1_INC_EXC;
208 config->enable_ctrl2 = 0x0;
209 config->enable_event = ETM_HARD_WIRE_RES_A;
210
211 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
212 config->enable_event = ETM_HARD_WIRE_RES_A;
213
214 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
215 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
216 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
220 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
221
222 for (i = 0; i < ETM_MAX_CNTR; i++) {
223 config->cntr_rld_val[i] = 0x0;
224 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
225 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
226 config->cntr_val[i] = 0x0;
227 }
228
229 config->seq_curr_state = 0x0;
230 config->ctxid_idx = 0x0;
231 for (i = 0; i < ETM_MAX_CTXID_CMP; i++)
232 config->ctxid_pid[i] = 0x0;
233
234 config->ctxid_mask = 0x0;
235 /* Setting default to 1024 as per TRM recommendation */
236 config->sync_freq = 0x400;
237}
238
239void etm_config_trace_mode(struct etm_config *config)
240{
241 u32 flags, mode;
242
243 mode = config->mode;
244
245 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
246
247 /* excluding kernel AND user space doesn't make sense */
248 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
249 return;
250
251 /* nothing to do if neither flags are set */
252 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
253 return;
254
255 flags = (1 << 0 | /* instruction execute */
256 3 << 3 | /* ARM instruction */
257 0 << 5 | /* No data value comparison */
258 0 << 7 | /* No exact mach */
259 0 << 8); /* Ignore context ID */
260
261 /* No need to worry about single address comparators. */
262 config->enable_ctrl2 = 0x0;
263
264 /* Bit 0 is address range comparator 1 */
265 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
266
267 /*
268 * On ETMv3.5:
269 * ETMACTRn[13,11] == Non-secure state comparison control
270 * ETMACTRn[12,10] == Secure state comparison control
271 *
272 * b00 == Match in all modes in this state
273 * b01 == Do not match in any more in this state
274 * b10 == Match in all modes excepts user mode in this state
275 * b11 == Match only in user mode in this state
276 */
277
278 /* Tracing in secure mode is not supported at this time */
279 flags |= (0 << 12 | 1 << 10);
280
281 if (mode & ETM_MODE_EXCL_USER) {
282 /* exclude user, match all modes except user mode */
283 flags |= (1 << 13 | 0 << 11);
284 } else {
285 /* exclude kernel, match only in user mode */
286 flags |= (1 << 13 | 1 << 11);
287 }
288
289 /*
290 * The ETMEEVR register is already set to "hard wire A". As such
291 * all there is to do is setup an address comparator that spans
292 * the entire address range and configure the state and mode bits.
293 */
294 config->addr_val[0] = (u32) 0x0;
295 config->addr_val[1] = (u32) ~0x0;
296 config->addr_acctype[0] = flags;
297 config->addr_acctype[1] = flags;
298 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
299 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
300}
301
302#define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \
303 ETMCR_TIMESTAMP_EN | \
304 ETMCR_RETURN_STACK)
305
306static int etm_parse_event_config(struct etm_drvdata *drvdata,
307 struct perf_event *event)
308{
309 struct etm_config *config = &drvdata->config;
310 struct perf_event_attr *attr = &event->attr;
311
312 if (!attr)
313 return -EINVAL;
314
315 /* Clear configuration from previous run */
316 memset(config, 0, sizeof(struct etm_config));
317
318 if (attr->exclude_kernel)
319 config->mode = ETM_MODE_EXCL_KERN;
320
321 if (attr->exclude_user)
322 config->mode = ETM_MODE_EXCL_USER;
323
324 /* Always start from the default config */
325 etm_set_default(config);
326
327 /*
328 * By default the tracers are configured to trace the whole address
329 * range. Narrow the field only if requested by user space.
330 */
331 if (config->mode)
332 etm_config_trace_mode(config);
333
334 /*
335 * At this time only cycle accurate, return stack and timestamp
336 * options are available.
337 */
338 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
339 return -EINVAL;
340
341 config->ctrl = attr->config;
342
343 /* Don't trace contextID when runs in non-root PID namespace */
344 if (!task_is_in_init_pid_ns(current))
345 config->ctrl &= ~ETMCR_CTXID_SIZE;
346
347 /*
348 * Possible to have cores with PTM (supports ret stack) and ETM
349 * (never has ret stack) on the same SoC. So if we have a request
350 * for return stack that can't be honoured on this core then
351 * clear the bit - trace will still continue normally
352 */
353 if ((config->ctrl & ETMCR_RETURN_STACK) &&
354 !(drvdata->etmccer & ETMCCER_RETSTACK))
355 config->ctrl &= ~ETMCR_RETURN_STACK;
356
357 return 0;
358}
359
360static int etm_enable_hw(struct etm_drvdata *drvdata)
361{
362 int i, rc;
363 u32 etmcr;
364 struct etm_config *config = &drvdata->config;
365 struct coresight_device *csdev = drvdata->csdev;
366
367 CS_UNLOCK(drvdata->base);
368
369 rc = coresight_claim_device_unlocked(csdev);
370 if (rc)
371 goto done;
372
373 /* Turn engine on */
374 etm_clr_pwrdwn(drvdata);
375 /* Apply power to trace registers */
376 etm_set_pwrup(drvdata);
377 /* Make sure all registers are accessible */
378 etm_os_unlock(drvdata);
379
380 etm_set_prog(drvdata);
381
382 etmcr = etm_readl(drvdata, ETMCR);
383 /* Clear setting from a previous run if need be */
384 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
385 etmcr |= drvdata->port_size;
386 etmcr |= ETMCR_ETM_EN;
387 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
388 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
389 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
390 etm_writel(drvdata, config->enable_event, ETMTEEVR);
391 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
392 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
393 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
394 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
395 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
396 }
397 for (i = 0; i < drvdata->nr_cntr; i++) {
398 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
399 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
400 etm_writel(drvdata, config->cntr_rld_event[i],
401 ETMCNTRLDEVRn(i));
402 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
403 }
404 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
405 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
406 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
407 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
408 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
409 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
410 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
411 for (i = 0; i < drvdata->nr_ext_out; i++)
412 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
413 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
414 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
415 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
416 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
417 /* No external input selected */
418 etm_writel(drvdata, 0x0, ETMEXTINSELR);
419 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
420 /* No auxiliary control selected */
421 etm_writel(drvdata, 0x0, ETMAUXCR);
422 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
423 /* No VMID comparator value selected */
424 etm_writel(drvdata, 0x0, ETMVMIDCVR);
425
426 etm_clr_prog(drvdata);
427
428done:
429 CS_LOCK(drvdata->base);
430
431 dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n",
432 drvdata->cpu, rc);
433 return rc;
434}
435
436struct etm_enable_arg {
437 struct etm_drvdata *drvdata;
438 int rc;
439};
440
441static void etm_enable_hw_smp_call(void *info)
442{
443 struct etm_enable_arg *arg = info;
444
445 if (WARN_ON(!arg))
446 return;
447 arg->rc = etm_enable_hw(arg->drvdata);
448}
449
450static int etm_cpu_id(struct coresight_device *csdev)
451{
452 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
453
454 return drvdata->cpu;
455}
456
457int etm_get_trace_id(struct etm_drvdata *drvdata)
458{
459 unsigned long flags;
460 int trace_id = -1;
461 struct device *etm_dev;
462
463 if (!drvdata)
464 goto out;
465
466 etm_dev = drvdata->csdev->dev.parent;
467 if (!local_read(&drvdata->mode))
468 return drvdata->traceid;
469
470 pm_runtime_get_sync(etm_dev);
471
472 spin_lock_irqsave(&drvdata->spinlock, flags);
473
474 CS_UNLOCK(drvdata->base);
475 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
476 CS_LOCK(drvdata->base);
477
478 spin_unlock_irqrestore(&drvdata->spinlock, flags);
479 pm_runtime_put(etm_dev);
480
481out:
482 return trace_id;
483
484}
485
486static int etm_trace_id(struct coresight_device *csdev)
487{
488 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
489
490 return etm_get_trace_id(drvdata);
491}
492
493static int etm_enable_perf(struct coresight_device *csdev,
494 struct perf_event *event)
495{
496 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
497
498 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
499 return -EINVAL;
500
501 /* Configure the tracer based on the session's specifics */
502 etm_parse_event_config(drvdata, event);
503 /* And enable it */
504 return etm_enable_hw(drvdata);
505}
506
507static int etm_enable_sysfs(struct coresight_device *csdev)
508{
509 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
510 struct etm_enable_arg arg = { };
511 int ret;
512
513 spin_lock(&drvdata->spinlock);
514
515 /*
516 * Configure the ETM only if the CPU is online. If it isn't online
517 * hw configuration will take place on the local CPU during bring up.
518 */
519 if (cpu_online(drvdata->cpu)) {
520 arg.drvdata = drvdata;
521 ret = smp_call_function_single(drvdata->cpu,
522 etm_enable_hw_smp_call, &arg, 1);
523 if (!ret)
524 ret = arg.rc;
525 if (!ret)
526 drvdata->sticky_enable = true;
527 } else {
528 ret = -ENODEV;
529 }
530
531 spin_unlock(&drvdata->spinlock);
532
533 if (!ret)
534 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
535 return ret;
536}
537
538static int etm_enable(struct coresight_device *csdev,
539 struct perf_event *event, u32 mode)
540{
541 int ret;
542 u32 val;
543 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
544
545 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
546
547 /* Someone is already using the tracer */
548 if (val)
549 return -EBUSY;
550
551 switch (mode) {
552 case CS_MODE_SYSFS:
553 ret = etm_enable_sysfs(csdev);
554 break;
555 case CS_MODE_PERF:
556 ret = etm_enable_perf(csdev, event);
557 break;
558 default:
559 ret = -EINVAL;
560 }
561
562 /* The tracer didn't start */
563 if (ret)
564 local_set(&drvdata->mode, CS_MODE_DISABLED);
565
566 return ret;
567}
568
569static void etm_disable_hw(void *info)
570{
571 int i;
572 struct etm_drvdata *drvdata = info;
573 struct etm_config *config = &drvdata->config;
574 struct coresight_device *csdev = drvdata->csdev;
575
576 CS_UNLOCK(drvdata->base);
577 etm_set_prog(drvdata);
578
579 /* Read back sequencer and counters for post trace analysis */
580 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
581
582 for (i = 0; i < drvdata->nr_cntr; i++)
583 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
584
585 etm_set_pwrdwn(drvdata);
586 coresight_disclaim_device_unlocked(csdev);
587
588 CS_LOCK(drvdata->base);
589
590 dev_dbg(&drvdata->csdev->dev,
591 "cpu: %d disable smp call done\n", drvdata->cpu);
592}
593
594static void etm_disable_perf(struct coresight_device *csdev)
595{
596 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
597
598 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
599 return;
600
601 CS_UNLOCK(drvdata->base);
602
603 /* Setting the prog bit disables tracing immediately */
604 etm_set_prog(drvdata);
605
606 /*
607 * There is no way to know when the tracer will be used again so
608 * power down the tracer.
609 */
610 etm_set_pwrdwn(drvdata);
611 coresight_disclaim_device_unlocked(csdev);
612
613 CS_LOCK(drvdata->base);
614}
615
616static void etm_disable_sysfs(struct coresight_device *csdev)
617{
618 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
619
620 /*
621 * Taking hotplug lock here protects from clocks getting disabled
622 * with tracing being left on (crash scenario) if user disable occurs
623 * after cpu online mask indicates the cpu is offline but before the
624 * DYING hotplug callback is serviced by the ETM driver.
625 */
626 cpus_read_lock();
627 spin_lock(&drvdata->spinlock);
628
629 /*
630 * Executing etm_disable_hw on the cpu whose ETM is being disabled
631 * ensures that register writes occur when cpu is powered.
632 */
633 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
634
635 spin_unlock(&drvdata->spinlock);
636 cpus_read_unlock();
637
638 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
639}
640
641static void etm_disable(struct coresight_device *csdev,
642 struct perf_event *event)
643{
644 u32 mode;
645 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
646
647 /*
648 * For as long as the tracer isn't disabled another entity can't
649 * change its status. As such we can read the status here without
650 * fearing it will change under us.
651 */
652 mode = local_read(&drvdata->mode);
653
654 switch (mode) {
655 case CS_MODE_DISABLED:
656 break;
657 case CS_MODE_SYSFS:
658 etm_disable_sysfs(csdev);
659 break;
660 case CS_MODE_PERF:
661 etm_disable_perf(csdev);
662 break;
663 default:
664 WARN_ON_ONCE(mode);
665 return;
666 }
667
668 if (mode)
669 local_set(&drvdata->mode, CS_MODE_DISABLED);
670}
671
672static const struct coresight_ops_source etm_source_ops = {
673 .cpu_id = etm_cpu_id,
674 .trace_id = etm_trace_id,
675 .enable = etm_enable,
676 .disable = etm_disable,
677};
678
679static const struct coresight_ops etm_cs_ops = {
680 .source_ops = &etm_source_ops,
681};
682
683static int etm_online_cpu(unsigned int cpu)
684{
685 if (!etmdrvdata[cpu])
686 return 0;
687
688 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
689 coresight_enable(etmdrvdata[cpu]->csdev);
690 return 0;
691}
692
693static int etm_starting_cpu(unsigned int cpu)
694{
695 if (!etmdrvdata[cpu])
696 return 0;
697
698 spin_lock(&etmdrvdata[cpu]->spinlock);
699 if (!etmdrvdata[cpu]->os_unlock) {
700 etm_os_unlock(etmdrvdata[cpu]);
701 etmdrvdata[cpu]->os_unlock = true;
702 }
703
704 if (local_read(&etmdrvdata[cpu]->mode))
705 etm_enable_hw(etmdrvdata[cpu]);
706 spin_unlock(&etmdrvdata[cpu]->spinlock);
707 return 0;
708}
709
710static int etm_dying_cpu(unsigned int cpu)
711{
712 if (!etmdrvdata[cpu])
713 return 0;
714
715 spin_lock(&etmdrvdata[cpu]->spinlock);
716 if (local_read(&etmdrvdata[cpu]->mode))
717 etm_disable_hw(etmdrvdata[cpu]);
718 spin_unlock(&etmdrvdata[cpu]->spinlock);
719 return 0;
720}
721
722static bool etm_arch_supported(u8 arch)
723{
724 switch (arch) {
725 case ETM_ARCH_V3_3:
726 break;
727 case ETM_ARCH_V3_5:
728 break;
729 case PFT_ARCH_V1_0:
730 break;
731 case PFT_ARCH_V1_1:
732 break;
733 default:
734 return false;
735 }
736 return true;
737}
738
739static void etm_init_arch_data(void *info)
740{
741 u32 etmidr;
742 u32 etmccr;
743 struct etm_drvdata *drvdata = info;
744
745 /* Make sure all registers are accessible */
746 etm_os_unlock(drvdata);
747
748 CS_UNLOCK(drvdata->base);
749
750 /* First dummy read */
751 (void)etm_readl(drvdata, ETMPDSR);
752 /* Provide power to ETM: ETMPDCR[3] == 1 */
753 etm_set_pwrup(drvdata);
754 /*
755 * Clear power down bit since when this bit is set writes to
756 * certain registers might be ignored.
757 */
758 etm_clr_pwrdwn(drvdata);
759 /*
760 * Set prog bit. It will be set from reset but this is included to
761 * ensure it is set
762 */
763 etm_set_prog(drvdata);
764
765 /* Find all capabilities */
766 etmidr = etm_readl(drvdata, ETMIDR);
767 drvdata->arch = BMVAL(etmidr, 4, 11);
768 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
769
770 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
771 etmccr = etm_readl(drvdata, ETMCCR);
772 drvdata->etmccr = etmccr;
773 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
774 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
775 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
776 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
777 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
778
779 etm_set_pwrdwn(drvdata);
780 etm_clr_pwrup(drvdata);
781 CS_LOCK(drvdata->base);
782}
783
784static void etm_init_trace_id(struct etm_drvdata *drvdata)
785{
786 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
787}
788
789static int __init etm_hp_setup(void)
790{
791 int ret;
792
793 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
794 "arm/coresight:starting",
795 etm_starting_cpu, etm_dying_cpu);
796
797 if (ret)
798 return ret;
799
800 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
801 "arm/coresight:online",
802 etm_online_cpu, NULL);
803
804 /* HP dyn state ID returned in ret on success */
805 if (ret > 0) {
806 hp_online = ret;
807 return 0;
808 }
809
810 /* failed dyn state - remove others */
811 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
812
813 return ret;
814}
815
816static void etm_hp_clear(void)
817{
818 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
819 if (hp_online) {
820 cpuhp_remove_state_nocalls(hp_online);
821 hp_online = 0;
822 }
823}
824
825static int etm_probe(struct amba_device *adev, const struct amba_id *id)
826{
827 int ret;
828 void __iomem *base;
829 struct device *dev = &adev->dev;
830 struct coresight_platform_data *pdata = NULL;
831 struct etm_drvdata *drvdata;
832 struct resource *res = &adev->res;
833 struct coresight_desc desc = { 0 };
834
835 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
836 if (!drvdata)
837 return -ENOMEM;
838
839 drvdata->use_cp14 = fwnode_property_read_bool(dev->fwnode, "arm,cp14");
840 dev_set_drvdata(dev, drvdata);
841
842 /* Validity for the resource is already checked by the AMBA core */
843 base = devm_ioremap_resource(dev, res);
844 if (IS_ERR(base))
845 return PTR_ERR(base);
846
847 drvdata->base = base;
848 desc.access = CSDEV_ACCESS_IOMEM(base);
849
850 spin_lock_init(&drvdata->spinlock);
851
852 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
853 if (!IS_ERR(drvdata->atclk)) {
854 ret = clk_prepare_enable(drvdata->atclk);
855 if (ret)
856 return ret;
857 }
858
859 drvdata->cpu = coresight_get_cpu(dev);
860 if (drvdata->cpu < 0)
861 return drvdata->cpu;
862
863 desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
864 if (!desc.name)
865 return -ENOMEM;
866
867 if (smp_call_function_single(drvdata->cpu,
868 etm_init_arch_data, drvdata, 1))
869 dev_err(dev, "ETM arch init failed\n");
870
871 if (etm_arch_supported(drvdata->arch) == false)
872 return -EINVAL;
873
874 etm_init_trace_id(drvdata);
875 etm_set_default(&drvdata->config);
876
877 pdata = coresight_get_platform_data(dev);
878 if (IS_ERR(pdata))
879 return PTR_ERR(pdata);
880
881 adev->dev.platform_data = pdata;
882
883 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
884 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
885 desc.ops = &etm_cs_ops;
886 desc.pdata = pdata;
887 desc.dev = dev;
888 desc.groups = coresight_etm_groups;
889 drvdata->csdev = coresight_register(&desc);
890 if (IS_ERR(drvdata->csdev))
891 return PTR_ERR(drvdata->csdev);
892
893 ret = etm_perf_symlink(drvdata->csdev, true);
894 if (ret) {
895 coresight_unregister(drvdata->csdev);
896 return ret;
897 }
898
899 etmdrvdata[drvdata->cpu] = drvdata;
900
901 pm_runtime_put(&adev->dev);
902 dev_info(&drvdata->csdev->dev,
903 "%s initialized\n", (char *)coresight_get_uci_data(id));
904 if (boot_enable) {
905 coresight_enable(drvdata->csdev);
906 drvdata->boot_enable = true;
907 }
908
909 return 0;
910}
911
912static void clear_etmdrvdata(void *info)
913{
914 int cpu = *(int *)info;
915
916 etmdrvdata[cpu] = NULL;
917}
918
919static void etm_remove(struct amba_device *adev)
920{
921 struct etm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
922
923 etm_perf_symlink(drvdata->csdev, false);
924
925 /*
926 * Taking hotplug lock here to avoid racing between etm_remove and
927 * CPU hotplug call backs.
928 */
929 cpus_read_lock();
930 /*
931 * The readers for etmdrvdata[] are CPU hotplug call backs
932 * and PM notification call backs. Change etmdrvdata[i] on
933 * CPU i ensures these call backs has consistent view
934 * inside one call back function.
935 */
936 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
937 etmdrvdata[drvdata->cpu] = NULL;
938
939 cpus_read_unlock();
940
941 coresight_unregister(drvdata->csdev);
942}
943
944#ifdef CONFIG_PM
945static int etm_runtime_suspend(struct device *dev)
946{
947 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
948
949 if (drvdata && !IS_ERR(drvdata->atclk))
950 clk_disable_unprepare(drvdata->atclk);
951
952 return 0;
953}
954
955static int etm_runtime_resume(struct device *dev)
956{
957 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
958
959 if (drvdata && !IS_ERR(drvdata->atclk))
960 clk_prepare_enable(drvdata->atclk);
961
962 return 0;
963}
964#endif
965
966static const struct dev_pm_ops etm_dev_pm_ops = {
967 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
968};
969
970static const struct amba_id etm_ids[] = {
971 /* ETM 3.3 */
972 CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"),
973 /* ETM 3.5 - Cortex-A5 */
974 CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"),
975 /* ETM 3.5 */
976 CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"),
977 /* PTM 1.0 */
978 CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"),
979 /* PTM 1.1 */
980 CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"),
981 /* PTM 1.1 Qualcomm */
982 CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"),
983 { 0, 0},
984};
985
986MODULE_DEVICE_TABLE(amba, etm_ids);
987
988static struct amba_driver etm_driver = {
989 .drv = {
990 .name = "coresight-etm3x",
991 .owner = THIS_MODULE,
992 .pm = &etm_dev_pm_ops,
993 .suppress_bind_attrs = true,
994 },
995 .probe = etm_probe,
996 .remove = etm_remove,
997 .id_table = etm_ids,
998};
999
1000static int __init etm_init(void)
1001{
1002 int ret;
1003
1004 ret = etm_hp_setup();
1005
1006 /* etm_hp_setup() does its own cleanup - exit on error */
1007 if (ret)
1008 return ret;
1009
1010 ret = amba_driver_register(&etm_driver);
1011 if (ret) {
1012 pr_err("Error registering etm3x driver\n");
1013 etm_hp_clear();
1014 }
1015
1016 return ret;
1017}
1018
1019static void __exit etm_exit(void)
1020{
1021 amba_driver_unregister(&etm_driver);
1022 etm_hp_clear();
1023}
1024
1025module_init(etm_init);
1026module_exit(etm_exit);
1027
1028MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1029MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1030MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace driver");
1031MODULE_LICENSE("GPL v2");