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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2015 Free Electrons
4 * Copyright (C) 2015 NextThing Co
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 */
8
9#include <linux/component.h>
10#include <linux/ioport.h>
11#include <linux/media-bus-format.h>
12#include <linux/module.h>
13#include <linux/of_address.h>
14#include <linux/of_device.h>
15#include <linux/of_irq.h>
16#include <linux/regmap.h>
17#include <linux/reset.h>
18
19#include <drm/drm_atomic_helper.h>
20#include <drm/drm_bridge.h>
21#include <drm/drm_connector.h>
22#include <drm/drm_crtc.h>
23#include <drm/drm_encoder.h>
24#include <drm/drm_modes.h>
25#include <drm/drm_of.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29#include <drm/drm_vblank.h>
30
31#include <uapi/drm/drm_mode.h>
32
33#include "sun4i_crtc.h"
34#include "sun4i_dotclock.h"
35#include "sun4i_drv.h"
36#include "sun4i_lvds.h"
37#include "sun4i_rgb.h"
38#include "sun4i_tcon.h"
39#include "sun6i_mipi_dsi.h"
40#include "sun8i_tcon_top.h"
41#include "sunxi_engine.h"
42
43static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
44{
45 struct drm_connector *connector;
46 struct drm_connector_list_iter iter;
47
48 drm_connector_list_iter_begin(encoder->dev, &iter);
49 drm_for_each_connector_iter(connector, &iter)
50 if (connector->encoder == encoder) {
51 drm_connector_list_iter_end(&iter);
52 return connector;
53 }
54 drm_connector_list_iter_end(&iter);
55
56 return NULL;
57}
58
59static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder)
60{
61 struct drm_connector *connector;
62 struct drm_display_info *info;
63
64 connector = sun4i_tcon_get_connector(encoder);
65 if (!connector)
66 return -EINVAL;
67
68 info = &connector->display_info;
69 if (info->num_bus_formats != 1)
70 return -EINVAL;
71
72 switch (info->bus_formats[0]) {
73 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
74 return 18;
75
76 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
77 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
78 return 24;
79 }
80
81 return -EINVAL;
82}
83
84static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
85 bool enabled)
86{
87 struct clk *clk;
88
89 switch (channel) {
90 case 0:
91 WARN_ON(!tcon->quirks->has_channel_0);
92 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
93 SUN4I_TCON0_CTL_TCON_ENABLE,
94 enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
95 clk = tcon->dclk;
96 break;
97 case 1:
98 WARN_ON(!tcon->quirks->has_channel_1);
99 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
100 SUN4I_TCON1_CTL_TCON_ENABLE,
101 enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0);
102 clk = tcon->sclk1;
103 break;
104 default:
105 DRM_WARN("Unknown channel... doing nothing\n");
106 return;
107 }
108
109 if (enabled) {
110 clk_prepare_enable(clk);
111 clk_rate_exclusive_get(clk);
112 } else {
113 clk_rate_exclusive_put(clk);
114 clk_disable_unprepare(clk);
115 }
116}
117
118static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
119 const struct drm_encoder *encoder)
120{
121 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
122 SUN4I_TCON0_LVDS_ANA0_CK_EN |
123 SUN4I_TCON0_LVDS_ANA0_REG_V |
124 SUN4I_TCON0_LVDS_ANA0_REG_C |
125 SUN4I_TCON0_LVDS_ANA0_EN_MB |
126 SUN4I_TCON0_LVDS_ANA0_PD |
127 SUN4I_TCON0_LVDS_ANA0_DCHS);
128
129 udelay(2); /* delay at least 1200 ns */
130 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
131 SUN4I_TCON0_LVDS_ANA1_INIT,
132 SUN4I_TCON0_LVDS_ANA1_INIT);
133 udelay(1); /* delay at least 120 ns */
134 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG,
135 SUN4I_TCON0_LVDS_ANA1_UPDATE,
136 SUN4I_TCON0_LVDS_ANA1_UPDATE);
137 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
138 SUN4I_TCON0_LVDS_ANA0_EN_MB,
139 SUN4I_TCON0_LVDS_ANA0_EN_MB);
140}
141
142static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon,
143 const struct drm_encoder *encoder)
144{
145 u8 val;
146
147 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
148 SUN6I_TCON0_LVDS_ANA0_C(2) |
149 SUN6I_TCON0_LVDS_ANA0_V(3) |
150 SUN6I_TCON0_LVDS_ANA0_PD(2) |
151 SUN6I_TCON0_LVDS_ANA0_EN_LDO);
152 udelay(2);
153
154 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
155 SUN6I_TCON0_LVDS_ANA0_EN_MB,
156 SUN6I_TCON0_LVDS_ANA0_EN_MB);
157 udelay(2);
158
159 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
160 SUN6I_TCON0_LVDS_ANA0_EN_DRVC,
161 SUN6I_TCON0_LVDS_ANA0_EN_DRVC);
162
163 if (sun4i_tcon_get_pixel_depth(encoder) == 18)
164 val = 7;
165 else
166 val = 0xf;
167
168 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG,
169 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf),
170 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val));
171}
172
173static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
174 const struct drm_encoder *encoder,
175 bool enabled)
176{
177 if (enabled) {
178 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
179 SUN4I_TCON0_LVDS_IF_EN,
180 SUN4I_TCON0_LVDS_IF_EN);
181 if (tcon->quirks->setup_lvds_phy)
182 tcon->quirks->setup_lvds_phy(tcon, encoder);
183 } else {
184 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG,
185 SUN4I_TCON0_LVDS_IF_EN, 0);
186 }
187}
188
189void sun4i_tcon_set_status(struct sun4i_tcon *tcon,
190 const struct drm_encoder *encoder,
191 bool enabled)
192{
193 bool is_lvds = false;
194 int channel;
195
196 switch (encoder->encoder_type) {
197 case DRM_MODE_ENCODER_LVDS:
198 is_lvds = true;
199 fallthrough;
200 case DRM_MODE_ENCODER_DSI:
201 case DRM_MODE_ENCODER_NONE:
202 channel = 0;
203 break;
204 case DRM_MODE_ENCODER_TMDS:
205 case DRM_MODE_ENCODER_TVDAC:
206 channel = 1;
207 break;
208 default:
209 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
210 return;
211 }
212
213 if (is_lvds && !enabled)
214 sun4i_tcon_lvds_set_status(tcon, encoder, false);
215
216 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
217 SUN4I_TCON_GCTL_TCON_ENABLE,
218 enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0);
219
220 if (is_lvds && enabled)
221 sun4i_tcon_lvds_set_status(tcon, encoder, true);
222
223 sun4i_tcon_channel_set_status(tcon, channel, enabled);
224}
225
226void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
227{
228 u32 mask, val = 0;
229
230 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis");
231
232 mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) |
233 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) |
234 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE;
235
236 if (enable)
237 val = mask;
238
239 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val);
240}
241EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
242
243/*
244 * This function is a helper for TCON output muxing. The TCON output
245 * muxing control register in earlier SoCs (without the TCON TOP block)
246 * are located in TCON0. This helper returns a pointer to TCON0's
247 * sun4i_tcon structure, or NULL if not found.
248 */
249static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm)
250{
251 struct sun4i_drv *drv = drm->dev_private;
252 struct sun4i_tcon *tcon;
253
254 list_for_each_entry(tcon, &drv->tcon_list, list)
255 if (tcon->id == 0)
256 return tcon;
257
258 dev_warn(drm->dev,
259 "TCON0 not found, display output muxing may not work\n");
260
261 return NULL;
262}
263
264static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel,
265 const struct drm_encoder *encoder)
266{
267 int ret = -ENOTSUPP;
268
269 if (tcon->quirks->set_mux)
270 ret = tcon->quirks->set_mux(tcon, encoder);
271
272 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n",
273 encoder->name, encoder->crtc->name, ret);
274}
275
276static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
277 int channel)
278{
279 int delay = mode->vtotal - mode->vdisplay;
280
281 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
282 delay /= 2;
283
284 if (channel == 1)
285 delay -= 2;
286
287 delay = min(delay, 30);
288
289 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay);
290
291 return delay;
292}
293
294static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
295 const struct drm_display_mode *mode)
296{
297 /* Configure the dot clock */
298 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
299
300 /* Set the resolution */
301 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
302 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
303 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
304}
305
306static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
307 const struct drm_connector *connector)
308{
309 u32 bus_format = 0;
310 u32 val = 0;
311
312 /* XXX Would this ever happen? */
313 if (!connector)
314 return;
315
316 /*
317 * FIXME: Undocumented bits
318 *
319 * The whole dithering process and these parameters are not
320 * explained in the vendor documents or BSP kernel code.
321 */
322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111);
323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111);
324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111);
325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111);
326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111);
327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111);
328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000);
329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111);
330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555);
331 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777);
332
333 /* Do dithering if panel only supports 6 bits per color */
334 if (connector->display_info.bpc == 6)
335 val |= SUN4I_TCON0_FRM_CTL_EN;
336
337 if (connector->display_info.num_bus_formats == 1)
338 bus_format = connector->display_info.bus_formats[0];
339
340 /* Check the connection format */
341 switch (bus_format) {
342 case MEDIA_BUS_FMT_RGB565_1X16:
343 /* R and B components are only 5 bits deep */
344 val |= SUN4I_TCON0_FRM_CTL_MODE_R;
345 val |= SUN4I_TCON0_FRM_CTL_MODE_B;
346 fallthrough;
347 case MEDIA_BUS_FMT_RGB666_1X18:
348 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
349 /* Fall through: enable dithering */
350 val |= SUN4I_TCON0_FRM_CTL_EN;
351 break;
352 }
353
354 /* Write dithering settings */
355 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
356}
357
358static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
359 const struct drm_encoder *encoder,
360 const struct drm_display_mode *mode)
361{
362 /* TODO support normal CPU interface modes */
363 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder);
364 struct mipi_dsi_device *device = dsi->device;
365 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
366 u8 lanes = device->lanes;
367 u32 block_space, start_delay;
368 u32 tcon_div;
369
370 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
371 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
372
373 sun4i_tcon0_mode_set_common(tcon, mode);
374
375 /* Set dithering if needed */
376 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
377
378 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
379 SUN4I_TCON0_CTL_IF_MASK,
380 SUN4I_TCON0_CTL_IF_8080);
381
382 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG,
383 SUN4I_TCON_ECC_FIFO_EN);
384
385 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG,
386 SUN4I_TCON0_CPU_IF_MODE_DSI |
387 SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH |
388 SUN4I_TCON0_CPU_IF_TRI_FIFO_EN |
389 SUN4I_TCON0_CPU_IF_TRI_EN);
390
391 /*
392 * This looks suspicious, but it works...
393 *
394 * The datasheet says that this should be set higher than 20 *
395 * pixel cycle, but it's not clear what a pixel cycle is.
396 */
397 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
398 tcon_div &= GENMASK(6, 0);
399 block_space = mode->htotal * bpp / (tcon_div * lanes);
400 block_space -= mode->hdisplay + 40;
401
402 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
403 SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) |
404 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay));
405
406 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG,
407 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay));
408
409 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1);
410 start_delay = start_delay * mode->crtc_htotal * 149;
411 start_delay = start_delay / (mode->crtc_clock / 1000) / 8;
412 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG,
413 SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) |
414 SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay));
415
416 /*
417 * The Allwinner BSP has a comment that the period should be
418 * the display clock * 15, but uses an hardcoded 3000...
419 */
420 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG,
421 SUN4I_TCON_SAFE_PERIOD_NUM(3000) |
422 SUN4I_TCON_SAFE_PERIOD_MODE(3));
423
424 /* Enable the output on the pins */
425 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG,
426 0xe0000000);
427}
428
429static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
430 const struct drm_encoder *encoder,
431 const struct drm_display_mode *mode)
432{
433 unsigned int bp;
434 u8 clk_delay;
435 u32 reg, val = 0;
436
437 WARN_ON(!tcon->quirks->has_channel_0);
438
439 tcon->dclk_min_div = 7;
440 tcon->dclk_max_div = 7;
441 sun4i_tcon0_mode_set_common(tcon, mode);
442
443 /* Set dithering if needed */
444 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
445
446 /* Adjust clock delay */
447 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
448 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
449 SUN4I_TCON0_CTL_CLK_DELAY_MASK,
450 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
451
452 /*
453 * This is called a backporch in the register documentation,
454 * but it really is the back porch + hsync
455 */
456 bp = mode->crtc_htotal - mode->crtc_hsync_start;
457 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
458 mode->crtc_htotal, bp);
459
460 /* Set horizontal display timings */
461 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
462 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) |
463 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
464
465 /*
466 * This is called a backporch in the register documentation,
467 * but it really is the back porch + hsync
468 */
469 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
470 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
471 mode->crtc_vtotal, bp);
472
473 /* Set vertical display timings */
474 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
475 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
476 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
477
478 reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0;
479 if (sun4i_tcon_get_pixel_depth(encoder) == 24)
480 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
481 else
482 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS;
483
484 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg);
485
486 /* Setup the polarity of the various signals */
487 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
488 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
489
490 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
491 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
492
493 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
494
495 /* Map output pins to channel 0 */
496 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
497 SUN4I_TCON_GCTL_IOMAP_MASK,
498 SUN4I_TCON_GCTL_IOMAP_TCON0);
499
500 /* Enable the output on the pins */
501 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000);
502}
503
504static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
505 const struct drm_encoder *encoder,
506 const struct drm_display_mode *mode)
507{
508 struct drm_connector *connector = sun4i_tcon_get_connector(encoder);
509 const struct drm_display_info *info = &connector->display_info;
510 unsigned int bp, hsync, vsync;
511 u8 clk_delay;
512 u32 val = 0;
513
514 WARN_ON(!tcon->quirks->has_channel_0);
515
516 tcon->dclk_min_div = tcon->quirks->dclk_min_div;
517 tcon->dclk_max_div = 127;
518 sun4i_tcon0_mode_set_common(tcon, mode);
519
520 /* Set dithering if needed */
521 sun4i_tcon0_mode_set_dithering(tcon, connector);
522
523 /* Adjust clock delay */
524 clk_delay = sun4i_tcon_get_clk_delay(mode, 0);
525 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
526 SUN4I_TCON0_CTL_CLK_DELAY_MASK,
527 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay));
528
529 /*
530 * This is called a backporch in the register documentation,
531 * but it really is the back porch + hsync
532 */
533 bp = mode->crtc_htotal - mode->crtc_hsync_start;
534 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
535 mode->crtc_htotal, bp);
536
537 /* Set horizontal display timings */
538 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG,
539 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) |
540 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp));
541
542 /*
543 * This is called a backporch in the register documentation,
544 * but it really is the back porch + hsync
545 */
546 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
547 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
548 mode->crtc_vtotal, bp);
549
550 /* Set vertical display timings */
551 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG,
552 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
553 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
554
555 /* Set Hsync and Vsync length */
556 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
557 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
558 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
559 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG,
560 SUN4I_TCON0_BASIC3_V_SYNC(vsync) |
561 SUN4I_TCON0_BASIC3_H_SYNC(hsync));
562
563 /* Setup the polarity of the various signals */
564 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
565 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
566
567 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
568 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
569
570 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
571 val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
572
573 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
574 val |= SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE;
575
576 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
577 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
578 SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
579 SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE |
580 SUN4I_TCON0_IO_POL_DE_NEGATIVE,
581 val);
582
583 /* Map output pins to channel 0 */
584 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
585 SUN4I_TCON_GCTL_IOMAP_MASK,
586 SUN4I_TCON_GCTL_IOMAP_TCON0);
587
588 /* Enable the output on the pins */
589 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0);
590}
591
592static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
593 const struct drm_display_mode *mode)
594{
595 unsigned int bp, hsync, vsync, vtotal;
596 u8 clk_delay;
597 u32 val;
598
599 WARN_ON(!tcon->quirks->has_channel_1);
600
601 /* Configure the dot clock */
602 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
603
604 /* Adjust clock delay */
605 clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
606 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
607 SUN4I_TCON1_CTL_CLK_DELAY_MASK,
608 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay));
609
610 /* Set interlaced mode */
611 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
612 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE;
613 else
614 val = 0;
615 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
616 SUN4I_TCON1_CTL_INTERLACE_ENABLE,
617 val);
618
619 /* Set the input resolution */
620 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
621 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
622 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
623
624 /* Set the upscaling resolution */
625 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
626 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
627 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
628
629 /* Set the output resolution */
630 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
631 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
632 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
633
634 /* Set horizontal display timings */
635 bp = mode->crtc_htotal - mode->crtc_hsync_start;
636 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
637 mode->htotal, bp);
638 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
639 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
640 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
641
642 bp = mode->crtc_vtotal - mode->crtc_vsync_start;
643 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
644 mode->crtc_vtotal, bp);
645
646 /*
647 * The vertical resolution needs to be doubled in all
648 * cases. We could use crtc_vtotal and always multiply by two,
649 * but that leads to a rounding error in interlace when vtotal
650 * is odd.
651 *
652 * This happens with TV's PAL for example, where vtotal will
653 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be
654 * 624, which apparently confuses the hardware.
655 *
656 * To work around this, we will always use vtotal, and
657 * multiply by two only if we're not in interlace.
658 */
659 vtotal = mode->vtotal;
660 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE))
661 vtotal = vtotal * 2;
662
663 /* Set vertical display timings */
664 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG,
665 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) |
666 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp));
667
668 /* Set Hsync and Vsync length */
669 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start;
670 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start;
671 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync);
672 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG,
673 SUN4I_TCON1_BASIC5_V_SYNC(vsync) |
674 SUN4I_TCON1_BASIC5_H_SYNC(hsync));
675
676 /* Setup the polarity of multiple signals */
677 if (tcon->quirks->polarity_in_ch0) {
678 val = 0;
679
680 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
681 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE;
682
683 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
684 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE;
685
686 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val);
687 } else {
688 /* according to vendor driver, this bit must be always set */
689 val = SUN4I_TCON1_IO_POL_UNKNOWN;
690
691 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
692 val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE;
693
694 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
695 val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE;
696
697 regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val);
698 }
699
700 /* Map output pins to channel 1 */
701 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
702 SUN4I_TCON_GCTL_IOMAP_MASK,
703 SUN4I_TCON_GCTL_IOMAP_TCON1);
704}
705
706void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
707 const struct drm_encoder *encoder,
708 const struct drm_display_mode *mode)
709{
710 switch (encoder->encoder_type) {
711 case DRM_MODE_ENCODER_DSI:
712 /* DSI is tied to special case of CPU interface */
713 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode);
714 break;
715 case DRM_MODE_ENCODER_LVDS:
716 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode);
717 break;
718 case DRM_MODE_ENCODER_NONE:
719 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode);
720 sun4i_tcon_set_mux(tcon, 0, encoder);
721 break;
722 case DRM_MODE_ENCODER_TVDAC:
723 case DRM_MODE_ENCODER_TMDS:
724 sun4i_tcon1_mode_set(tcon, mode);
725 sun4i_tcon_set_mux(tcon, 1, encoder);
726 break;
727 default:
728 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n");
729 }
730}
731EXPORT_SYMBOL(sun4i_tcon_mode_set);
732
733static void sun4i_tcon_finish_page_flip(struct drm_device *dev,
734 struct sun4i_crtc *scrtc)
735{
736 unsigned long flags;
737
738 spin_lock_irqsave(&dev->event_lock, flags);
739 if (scrtc->event) {
740 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event);
741 drm_crtc_vblank_put(&scrtc->crtc);
742 scrtc->event = NULL;
743 }
744 spin_unlock_irqrestore(&dev->event_lock, flags);
745}
746
747static irqreturn_t sun4i_tcon_handler(int irq, void *private)
748{
749 struct sun4i_tcon *tcon = private;
750 struct drm_device *drm = tcon->drm;
751 struct sun4i_crtc *scrtc = tcon->crtc;
752 struct sunxi_engine *engine = scrtc->engine;
753 unsigned int status;
754
755 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status);
756
757 if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
758 SUN4I_TCON_GINT0_VBLANK_INT(1) |
759 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT)))
760 return IRQ_NONE;
761
762 drm_crtc_handle_vblank(&scrtc->crtc);
763 sun4i_tcon_finish_page_flip(drm, scrtc);
764
765 /* Acknowledge the interrupt */
766 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG,
767 SUN4I_TCON_GINT0_VBLANK_INT(0) |
768 SUN4I_TCON_GINT0_VBLANK_INT(1) |
769 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT,
770 0);
771
772 if (engine->ops->vblank_quirk)
773 engine->ops->vblank_quirk(engine);
774
775 return IRQ_HANDLED;
776}
777
778static int sun4i_tcon_init_clocks(struct device *dev,
779 struct sun4i_tcon *tcon)
780{
781 tcon->clk = devm_clk_get(dev, "ahb");
782 if (IS_ERR(tcon->clk)) {
783 dev_err(dev, "Couldn't get the TCON bus clock\n");
784 return PTR_ERR(tcon->clk);
785 }
786 clk_prepare_enable(tcon->clk);
787
788 if (tcon->quirks->has_channel_0) {
789 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
790 if (IS_ERR(tcon->sclk0)) {
791 dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
792 return PTR_ERR(tcon->sclk0);
793 }
794 }
795 clk_prepare_enable(tcon->sclk0);
796
797 if (tcon->quirks->has_channel_1) {
798 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1");
799 if (IS_ERR(tcon->sclk1)) {
800 dev_err(dev, "Couldn't get the TCON channel 1 clock\n");
801 return PTR_ERR(tcon->sclk1);
802 }
803 }
804
805 return 0;
806}
807
808static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
809{
810 clk_disable_unprepare(tcon->sclk0);
811 clk_disable_unprepare(tcon->clk);
812}
813
814static int sun4i_tcon_init_irq(struct device *dev,
815 struct sun4i_tcon *tcon)
816{
817 struct platform_device *pdev = to_platform_device(dev);
818 int irq, ret;
819
820 irq = platform_get_irq(pdev, 0);
821 if (irq < 0)
822 return irq;
823
824 ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0,
825 dev_name(dev), tcon);
826 if (ret) {
827 dev_err(dev, "Couldn't request the IRQ\n");
828 return ret;
829 }
830
831 return 0;
832}
833
834static const struct regmap_config sun4i_tcon_regmap_config = {
835 .reg_bits = 32,
836 .val_bits = 32,
837 .reg_stride = 4,
838 .max_register = 0x800,
839};
840
841static int sun4i_tcon_init_regmap(struct device *dev,
842 struct sun4i_tcon *tcon)
843{
844 struct platform_device *pdev = to_platform_device(dev);
845 void __iomem *regs;
846
847 regs = devm_platform_ioremap_resource(pdev, 0);
848 if (IS_ERR(regs))
849 return PTR_ERR(regs);
850
851 tcon->regs = devm_regmap_init_mmio(dev, regs,
852 &sun4i_tcon_regmap_config);
853 if (IS_ERR(tcon->regs)) {
854 dev_err(dev, "Couldn't create the TCON regmap\n");
855 return PTR_ERR(tcon->regs);
856 }
857
858 /* Make sure the TCON is disabled and all IRQs are off */
859 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
860 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
861 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0);
862
863 /* Disable IO lines and set them to tristate */
864 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
865 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
866
867 return 0;
868}
869
870/*
871 * On SoCs with the old display pipeline design (Display Engine 1.0),
872 * the TCON is always tied to just one backend. Hence we can traverse
873 * the of_graph upwards to find the backend our tcon is connected to,
874 * and take its ID as our own.
875 *
876 * We can either identify backends from their compatible strings, which
877 * means maintaining a large list of them. Or, since the backend is
878 * registered and binded before the TCON, we can just go through the
879 * list of registered backends and compare the device node.
880 *
881 * As the structures now store engines instead of backends, here this
882 * function in fact searches the corresponding engine, and the ID is
883 * requested via the get_id function of the engine.
884 */
885static struct sunxi_engine *
886sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
887 struct device_node *node,
888 u32 port_id)
889{
890 struct device_node *port, *ep, *remote;
891 struct sunxi_engine *engine = ERR_PTR(-EINVAL);
892 u32 reg = 0;
893
894 port = of_graph_get_port_by_id(node, port_id);
895 if (!port)
896 return ERR_PTR(-EINVAL);
897
898 /*
899 * This only works if there is only one path from the TCON
900 * to any display engine. Otherwise the probe order of the
901 * TCONs and display engines is not guaranteed. They may
902 * either bind to the wrong one, or worse, bind to the same
903 * one if additional checks are not done.
904 *
905 * Bail out if there are multiple input connections.
906 */
907 if (of_get_available_child_count(port) != 1)
908 goto out_put_port;
909
910 /* Get the first connection without specifying an ID */
911 ep = of_get_next_available_child(port, NULL);
912 if (!ep)
913 goto out_put_port;
914
915 remote = of_graph_get_remote_port_parent(ep);
916 if (!remote)
917 goto out_put_ep;
918
919 /* does this node match any registered engines? */
920 list_for_each_entry(engine, &drv->engine_list, list)
921 if (remote == engine->node)
922 goto out_put_remote;
923
924 /*
925 * According to device tree binding input ports have even id
926 * number and output ports have odd id. Since component with
927 * more than one input and one output (TCON TOP) exits, correct
928 * remote input id has to be calculated by subtracting 1 from
929 * remote output id. If this for some reason can't be done, 0
930 * is used as input port id.
931 */
932 of_node_put(port);
933 port = of_graph_get_remote_port(ep);
934 if (!of_property_read_u32(port, "reg", ®) && reg > 0)
935 reg -= 1;
936
937 /* keep looking through upstream ports */
938 engine = sun4i_tcon_find_engine_traverse(drv, remote, reg);
939
940out_put_remote:
941 of_node_put(remote);
942out_put_ep:
943 of_node_put(ep);
944out_put_port:
945 of_node_put(port);
946
947 return engine;
948}
949
950/*
951 * The device tree binding says that the remote endpoint ID of any
952 * connection between components, up to and including the TCON, of
953 * the display pipeline should be equal to the actual ID of the local
954 * component. Thus we can look at any one of the input connections of
955 * the TCONs, and use that connection's remote endpoint ID as our own.
956 *
957 * Since the user of this function already finds the input port,
958 * the port is passed in directly without further checks.
959 */
960static int sun4i_tcon_of_get_id_from_port(struct device_node *port)
961{
962 struct device_node *ep;
963 int ret = -EINVAL;
964
965 /* try finding an upstream endpoint */
966 for_each_available_child_of_node(port, ep) {
967 struct device_node *remote;
968 u32 reg;
969
970 remote = of_graph_get_remote_endpoint(ep);
971 if (!remote)
972 continue;
973
974 ret = of_property_read_u32(remote, "reg", ®);
975 if (ret)
976 continue;
977
978 ret = reg;
979 }
980
981 return ret;
982}
983
984/*
985 * Once we know the TCON's id, we can look through the list of
986 * engines to find a matching one. We assume all engines have
987 * been probed and added to the list.
988 */
989static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv,
990 int id)
991{
992 struct sunxi_engine *engine;
993
994 list_for_each_entry(engine, &drv->engine_list, list)
995 if (engine->id == id)
996 return engine;
997
998 return ERR_PTR(-EINVAL);
999}
1000
1001static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node)
1002{
1003 struct device_node *remote;
1004 bool ret = false;
1005
1006 remote = of_graph_get_remote_node(node, 0, -1);
1007 if (remote) {
1008 ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
1009 of_match_node(sun8i_tcon_top_of_table, remote));
1010 of_node_put(remote);
1011 }
1012
1013 return ret;
1014}
1015
1016static int sun4i_tcon_get_index(struct sun4i_drv *drv)
1017{
1018 struct list_head *pos;
1019 int size = 0;
1020
1021 /*
1022 * Because TCON is added to the list at the end of the probe
1023 * (after this function is called), index of the current TCON
1024 * will be same as current TCON list size.
1025 */
1026 list_for_each(pos, &drv->tcon_list)
1027 ++size;
1028
1029 return size;
1030}
1031
1032/*
1033 * On SoCs with the old display pipeline design (Display Engine 1.0),
1034 * we assumed the TCON was always tied to just one backend. However
1035 * this proved not to be the case. On the A31, the TCON can select
1036 * either backend as its source. On the A20 (and likely on the A10),
1037 * the backend can choose which TCON to output to.
1038 *
1039 * The device tree binding says that the remote endpoint ID of any
1040 * connection between components, up to and including the TCON, of
1041 * the display pipeline should be equal to the actual ID of the local
1042 * component. Thus we should be able to look at any one of the input
1043 * connections of the TCONs, and use that connection's remote endpoint
1044 * ID as our own.
1045 *
1046 * However the connections between the backend and TCON were assumed
1047 * to be always singular, and their endpoit IDs were all incorrectly
1048 * set to 0. This means for these old device trees, we cannot just look
1049 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
1050 * incorrectly identified as TCON0.
1051 *
1052 * This function first checks if the TCON node has 2 input endpoints.
1053 * If so, then the device tree is a corrected version, and it will use
1054 * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above
1055 * to fetch the ID and engine directly. If not, then it is likely an
1056 * old device trees, where the endpoint IDs were incorrect, but did not
1057 * have endpoint connections between the backend and TCON across
1058 * different display pipelines. It will fall back to the old method of
1059 * traversing the of_graph to try and find a matching engine by device
1060 * node.
1061 *
1062 * In the case of single display pipeline device trees, either method
1063 * works.
1064 */
1065static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
1066 struct device_node *node)
1067{
1068 struct device_node *port;
1069 struct sunxi_engine *engine;
1070
1071 port = of_graph_get_port_by_id(node, 0);
1072 if (!port)
1073 return ERR_PTR(-EINVAL);
1074
1075 /*
1076 * Is this a corrected device tree with cross pipeline
1077 * connections between the backend and TCON?
1078 */
1079 if (of_get_child_count(port) > 1) {
1080 int id;
1081
1082 /*
1083 * When pipeline has the same number of TCONs and engines which
1084 * are represented by frontends/backends (DE1) or mixers (DE2),
1085 * we match them by their respective IDs. However, if pipeline
1086 * contains TCON TOP, chances are that there are either more
1087 * TCONs than engines (R40) or TCONs with non-consecutive ids.
1088 * (H6). In that case it's easier just use TCON index in list
1089 * as an id. That means that on R40, any 2 TCONs can be enabled
1090 * in DT out of 4 (there are 2 mixers). Due to the design of
1091 * TCON TOP, remaining 2 TCONs can't be connected to anything
1092 * anyway.
1093 */
1094 if (sun4i_tcon_connected_to_tcon_top(node))
1095 id = sun4i_tcon_get_index(drv);
1096 else
1097 id = sun4i_tcon_of_get_id_from_port(port);
1098
1099 /* Get our engine by matching our ID */
1100 engine = sun4i_tcon_get_engine_by_id(drv, id);
1101
1102 of_node_put(port);
1103 return engine;
1104 }
1105
1106 /* Fallback to old method by traversing input endpoints */
1107 of_node_put(port);
1108 return sun4i_tcon_find_engine_traverse(drv, node, 0);
1109}
1110
1111static int sun4i_tcon_bind(struct device *dev, struct device *master,
1112 void *data)
1113{
1114 struct drm_device *drm = data;
1115 struct sun4i_drv *drv = drm->dev_private;
1116 struct sunxi_engine *engine;
1117 struct device_node *remote;
1118 struct sun4i_tcon *tcon;
1119 struct reset_control *edp_rstc;
1120 bool has_lvds_rst, has_lvds_alt, can_lvds;
1121 int ret;
1122
1123 engine = sun4i_tcon_find_engine(drv, dev->of_node);
1124 if (IS_ERR(engine)) {
1125 dev_err(dev, "Couldn't find matching engine\n");
1126 return -EPROBE_DEFER;
1127 }
1128
1129 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL);
1130 if (!tcon)
1131 return -ENOMEM;
1132 dev_set_drvdata(dev, tcon);
1133 tcon->drm = drm;
1134 tcon->dev = dev;
1135 tcon->id = engine->id;
1136 tcon->quirks = of_device_get_match_data(dev);
1137
1138 tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
1139 if (IS_ERR(tcon->lcd_rst)) {
1140 dev_err(dev, "Couldn't get our reset line\n");
1141 return PTR_ERR(tcon->lcd_rst);
1142 }
1143
1144 if (tcon->quirks->needs_edp_reset) {
1145 edp_rstc = devm_reset_control_get_shared(dev, "edp");
1146 if (IS_ERR(edp_rstc)) {
1147 dev_err(dev, "Couldn't get edp reset line\n");
1148 return PTR_ERR(edp_rstc);
1149 }
1150
1151 ret = reset_control_deassert(edp_rstc);
1152 if (ret) {
1153 dev_err(dev, "Couldn't deassert edp reset line\n");
1154 return ret;
1155 }
1156 }
1157
1158 /* Make sure our TCON is reset */
1159 ret = reset_control_reset(tcon->lcd_rst);
1160 if (ret) {
1161 dev_err(dev, "Couldn't deassert our reset line\n");
1162 return ret;
1163 }
1164
1165 if (tcon->quirks->supports_lvds) {
1166 /*
1167 * This can only be made optional since we've had DT
1168 * nodes without the LVDS reset properties.
1169 *
1170 * If the property is missing, just disable LVDS, and
1171 * print a warning.
1172 */
1173 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds");
1174 if (IS_ERR(tcon->lvds_rst)) {
1175 dev_err(dev, "Couldn't get our reset line\n");
1176 return PTR_ERR(tcon->lvds_rst);
1177 } else if (tcon->lvds_rst) {
1178 has_lvds_rst = true;
1179 reset_control_reset(tcon->lvds_rst);
1180 } else {
1181 has_lvds_rst = false;
1182 }
1183
1184 /*
1185 * This can only be made optional since we've had DT
1186 * nodes without the LVDS reset properties.
1187 *
1188 * If the property is missing, just disable LVDS, and
1189 * print a warning.
1190 */
1191 if (tcon->quirks->has_lvds_alt) {
1192 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt");
1193 if (IS_ERR(tcon->lvds_pll)) {
1194 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) {
1195 has_lvds_alt = false;
1196 } else {
1197 dev_err(dev, "Couldn't get the LVDS PLL\n");
1198 return PTR_ERR(tcon->lvds_pll);
1199 }
1200 } else {
1201 has_lvds_alt = true;
1202 }
1203 }
1204
1205 if (!has_lvds_rst ||
1206 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) {
1207 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n");
1208 dev_warn(dev, "LVDS output disabled\n");
1209 can_lvds = false;
1210 } else {
1211 can_lvds = true;
1212 }
1213 } else {
1214 can_lvds = false;
1215 }
1216
1217 ret = sun4i_tcon_init_clocks(dev, tcon);
1218 if (ret) {
1219 dev_err(dev, "Couldn't init our TCON clocks\n");
1220 goto err_assert_reset;
1221 }
1222
1223 ret = sun4i_tcon_init_regmap(dev, tcon);
1224 if (ret) {
1225 dev_err(dev, "Couldn't init our TCON regmap\n");
1226 goto err_free_clocks;
1227 }
1228
1229 if (tcon->quirks->has_channel_0) {
1230 ret = sun4i_dclk_create(dev, tcon);
1231 if (ret) {
1232 dev_err(dev, "Couldn't create our TCON dot clock\n");
1233 goto err_free_clocks;
1234 }
1235 }
1236
1237 ret = sun4i_tcon_init_irq(dev, tcon);
1238 if (ret) {
1239 dev_err(dev, "Couldn't init our TCON interrupts\n");
1240 goto err_free_dotclock;
1241 }
1242
1243 tcon->crtc = sun4i_crtc_init(drm, engine, tcon);
1244 if (IS_ERR(tcon->crtc)) {
1245 dev_err(dev, "Couldn't create our CRTC\n");
1246 ret = PTR_ERR(tcon->crtc);
1247 goto err_free_dotclock;
1248 }
1249
1250 if (tcon->quirks->has_channel_0) {
1251 /*
1252 * If we have an LVDS panel connected to the TCON, we should
1253 * just probe the LVDS connector. Otherwise, just probe RGB as
1254 * we used to.
1255 */
1256 remote = of_graph_get_remote_node(dev->of_node, 1, 0);
1257 if (of_device_is_compatible(remote, "panel-lvds"))
1258 if (can_lvds)
1259 ret = sun4i_lvds_init(drm, tcon);
1260 else
1261 ret = -EINVAL;
1262 else
1263 ret = sun4i_rgb_init(drm, tcon);
1264 of_node_put(remote);
1265
1266 if (ret < 0)
1267 goto err_free_dotclock;
1268 }
1269
1270 if (tcon->quirks->needs_de_be_mux) {
1271 /*
1272 * We assume there is no dynamic muxing of backends
1273 * and TCONs, so we select the backend with same ID.
1274 *
1275 * While dynamic selection might be interesting, since
1276 * the CRTC is tied to the TCON, while the layers are
1277 * tied to the backends, this means, we will need to
1278 * switch between groups of layers. There might not be
1279 * a way to represent this constraint in DRM.
1280 */
1281 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
1282 SUN4I_TCON0_CTL_SRC_SEL_MASK,
1283 tcon->id);
1284 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG,
1285 SUN4I_TCON1_CTL_SRC_SEL_MASK,
1286 tcon->id);
1287 }
1288
1289 list_add_tail(&tcon->list, &drv->tcon_list);
1290
1291 return 0;
1292
1293err_free_dotclock:
1294 if (tcon->quirks->has_channel_0)
1295 sun4i_dclk_free(tcon);
1296err_free_clocks:
1297 sun4i_tcon_free_clocks(tcon);
1298err_assert_reset:
1299 reset_control_assert(tcon->lcd_rst);
1300 return ret;
1301}
1302
1303static void sun4i_tcon_unbind(struct device *dev, struct device *master,
1304 void *data)
1305{
1306 struct sun4i_tcon *tcon = dev_get_drvdata(dev);
1307
1308 list_del(&tcon->list);
1309 if (tcon->quirks->has_channel_0)
1310 sun4i_dclk_free(tcon);
1311 sun4i_tcon_free_clocks(tcon);
1312}
1313
1314static const struct component_ops sun4i_tcon_ops = {
1315 .bind = sun4i_tcon_bind,
1316 .unbind = sun4i_tcon_unbind,
1317};
1318
1319static int sun4i_tcon_probe(struct platform_device *pdev)
1320{
1321 struct device_node *node = pdev->dev.of_node;
1322 const struct sun4i_tcon_quirks *quirks;
1323 struct drm_bridge *bridge;
1324 struct drm_panel *panel;
1325 int ret;
1326
1327 quirks = of_device_get_match_data(&pdev->dev);
1328
1329 /* panels and bridges are present only on TCONs with channel 0 */
1330 if (quirks->has_channel_0) {
1331 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
1332 if (ret == -EPROBE_DEFER)
1333 return ret;
1334 }
1335
1336 return component_add(&pdev->dev, &sun4i_tcon_ops);
1337}
1338
1339static int sun4i_tcon_remove(struct platform_device *pdev)
1340{
1341 component_del(&pdev->dev, &sun4i_tcon_ops);
1342
1343 return 0;
1344}
1345
1346/* platform specific TCON muxing callbacks */
1347static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon,
1348 const struct drm_encoder *encoder)
1349{
1350 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1351 u32 shift;
1352
1353 if (!tcon0)
1354 return -EINVAL;
1355
1356 switch (encoder->encoder_type) {
1357 case DRM_MODE_ENCODER_TMDS:
1358 /* HDMI */
1359 shift = 8;
1360 break;
1361 default:
1362 return -EINVAL;
1363 }
1364
1365 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1366 0x3 << shift, tcon->id << shift);
1367
1368 return 0;
1369}
1370
1371static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon,
1372 const struct drm_encoder *encoder)
1373{
1374 u32 val;
1375
1376 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC)
1377 val = 1;
1378 else
1379 val = 0;
1380
1381 /*
1382 * FIXME: Undocumented bits
1383 */
1384 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val);
1385}
1386
1387static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
1388 const struct drm_encoder *encoder)
1389{
1390 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev);
1391 u32 shift;
1392
1393 if (!tcon0)
1394 return -EINVAL;
1395
1396 switch (encoder->encoder_type) {
1397 case DRM_MODE_ENCODER_TMDS:
1398 /* HDMI */
1399 shift = 8;
1400 break;
1401 default:
1402 /* TODO A31 has MIPI DSI but A31s does not */
1403 return -EINVAL;
1404 }
1405
1406 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG,
1407 0x3 << shift, tcon->id << shift);
1408
1409 return 0;
1410}
1411
1412static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon,
1413 const struct drm_encoder *encoder)
1414{
1415 struct device_node *port, *remote;
1416 struct platform_device *pdev;
1417 int id, ret;
1418
1419 /* find TCON TOP platform device and TCON id */
1420
1421 port = of_graph_get_port_by_id(tcon->dev->of_node, 0);
1422 if (!port)
1423 return -EINVAL;
1424
1425 id = sun4i_tcon_of_get_id_from_port(port);
1426 of_node_put(port);
1427
1428 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1);
1429 if (!remote)
1430 return -EINVAL;
1431
1432 pdev = of_find_device_by_node(remote);
1433 of_node_put(remote);
1434 if (!pdev)
1435 return -EINVAL;
1436
1437 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
1438 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) {
1439 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id);
1440 if (ret) {
1441 put_device(&pdev->dev);
1442 return ret;
1443 }
1444 }
1445
1446 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) {
1447 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id);
1448 if (ret) {
1449 put_device(&pdev->dev);
1450 return ret;
1451 }
1452 }
1453
1454 return 0;
1455}
1456
1457static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
1458 .has_channel_0 = true,
1459 .has_channel_1 = true,
1460 .dclk_min_div = 4,
1461 .set_mux = sun4i_a10_tcon_set_mux,
1462};
1463
1464static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
1465 .has_channel_0 = true,
1466 .has_channel_1 = true,
1467 .dclk_min_div = 4,
1468 .set_mux = sun5i_a13_tcon_set_mux,
1469};
1470
1471static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
1472 .has_channel_0 = true,
1473 .has_channel_1 = true,
1474 .has_lvds_alt = true,
1475 .needs_de_be_mux = true,
1476 .dclk_min_div = 1,
1477 .set_mux = sun6i_tcon_set_mux,
1478};
1479
1480static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
1481 .has_channel_0 = true,
1482 .has_channel_1 = true,
1483 .needs_de_be_mux = true,
1484 .dclk_min_div = 1,
1485};
1486
1487static const struct sun4i_tcon_quirks sun7i_a20_tcon0_quirks = {
1488 .supports_lvds = true,
1489 .has_channel_0 = true,
1490 .has_channel_1 = true,
1491 .dclk_min_div = 4,
1492 /* Same display pipeline structure as A10 */
1493 .set_mux = sun4i_a10_tcon_set_mux,
1494 .setup_lvds_phy = sun4i_tcon_setup_lvds_phy,
1495};
1496
1497static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
1498 .has_channel_0 = true,
1499 .has_channel_1 = true,
1500 .dclk_min_div = 4,
1501 /* Same display pipeline structure as A10 */
1502 .set_mux = sun4i_a10_tcon_set_mux,
1503};
1504
1505static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
1506 .has_channel_0 = true,
1507 .has_lvds_alt = true,
1508 .dclk_min_div = 1,
1509 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
1510 .supports_lvds = true,
1511};
1512
1513static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
1514 .supports_lvds = true,
1515 .has_channel_0 = true,
1516 .dclk_min_div = 1,
1517 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy,
1518};
1519
1520static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
1521 .has_channel_1 = true,
1522};
1523
1524static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
1525 .has_channel_1 = true,
1526 .polarity_in_ch0 = true,
1527 .set_mux = sun8i_r40_tcon_tv_set_mux,
1528};
1529
1530static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
1531 .has_channel_0 = true,
1532 .dclk_min_div = 1,
1533};
1534
1535static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = {
1536 .has_channel_0 = true,
1537 .needs_edp_reset = true,
1538 .dclk_min_div = 1,
1539};
1540
1541static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {
1542 .has_channel_1 = true,
1543 .needs_edp_reset = true,
1544};
1545
1546static const struct sun4i_tcon_quirks sun20i_d1_lcd_quirks = {
1547 .has_channel_0 = true,
1548 .dclk_min_div = 1,
1549 .set_mux = sun8i_r40_tcon_tv_set_mux,
1550};
1551
1552/* sun4i_drv uses this list to check if a device node is a TCON */
1553const struct of_device_id sun4i_tcon_of_table[] = {
1554 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1555 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1556 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1557 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1558 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1559 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks },
1560 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks },
1561 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks },
1562 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1563 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1564 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1565 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
1566 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1567 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1568 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1569 { .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
1570 { .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
1571 { }
1572};
1573MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
1574EXPORT_SYMBOL(sun4i_tcon_of_table);
1575
1576static struct platform_driver sun4i_tcon_platform_driver = {
1577 .probe = sun4i_tcon_probe,
1578 .remove = sun4i_tcon_remove,
1579 .driver = {
1580 .name = "sun4i-tcon",
1581 .of_match_table = sun4i_tcon_of_table,
1582 },
1583};
1584module_platform_driver(sun4i_tcon_platform_driver);
1585
1586MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1587MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver");
1588MODULE_LICENSE("GPL");