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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Author:Mark Yao <mark.yao@rock-chips.com>
5 */
6
7#ifndef _ROCKCHIP_DRM_VOP_H
8#define _ROCKCHIP_DRM_VOP_H
9
10/*
11 * major: IP major version, used for IP structure
12 * minor: big feature change under same structure
13 */
14#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
15#define VOP_MAJOR(version) ((version) >> 8)
16#define VOP_MINOR(version) ((version) & 0xff)
17
18#define NUM_YUV2YUV_COEFFICIENTS 12
19
20/* AFBC supports a number of configurable modes. Relevant to us is block size
21 * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like
22 * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode
23 * could be enabled via the hreg_block_split register, but is not currently
24 * handled. The colourspace transform is implicitly always assumed by the
25 * decoder, so consumers must use this transform as well.
26 *
27 * Failure to match modifiers will cause errors displaying AFBC buffers
28 * produced by conformant AFBC producers, including Mesa.
29 */
30#define ROCKCHIP_AFBC_MOD \
31 DRM_FORMAT_MOD_ARM_AFBC( \
32 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \
33 | AFBC_FORMAT_MOD_YTR \
34 )
35
36enum vop_data_format {
37 VOP_FMT_ARGB8888 = 0,
38 VOP_FMT_RGB888,
39 VOP_FMT_RGB565,
40 VOP_FMT_YUV420SP = 4,
41 VOP_FMT_YUV422SP,
42 VOP_FMT_YUV444SP,
43};
44
45struct vop_reg {
46 uint32_t mask;
47 uint16_t offset;
48 uint8_t shift;
49 bool write_mask;
50 bool relaxed;
51};
52
53struct vop_afbc {
54 struct vop_reg enable;
55 struct vop_reg win_sel;
56 struct vop_reg format;
57 struct vop_reg rb_swap;
58 struct vop_reg uv_swap;
59 struct vop_reg auto_gating_en;
60 struct vop_reg block_split_en;
61 struct vop_reg pic_vir_width;
62 struct vop_reg tile_num;
63 struct vop_reg hreg_block_split;
64 struct vop_reg pic_offset;
65 struct vop_reg pic_size;
66 struct vop_reg dsp_offset;
67 struct vop_reg transform_offset;
68 struct vop_reg hdr_ptr;
69 struct vop_reg half_block_en;
70 struct vop_reg xmirror;
71 struct vop_reg ymirror;
72 struct vop_reg rotate_270;
73 struct vop_reg rotate_90;
74 struct vop_reg rstn;
75};
76
77struct vop_modeset {
78 struct vop_reg htotal_pw;
79 struct vop_reg hact_st_end;
80 struct vop_reg hpost_st_end;
81 struct vop_reg vtotal_pw;
82 struct vop_reg vact_st_end;
83 struct vop_reg vpost_st_end;
84};
85
86struct vop_output {
87 struct vop_reg pin_pol;
88 struct vop_reg dp_pin_pol;
89 struct vop_reg dp_dclk_pol;
90 struct vop_reg edp_pin_pol;
91 struct vop_reg edp_dclk_pol;
92 struct vop_reg hdmi_pin_pol;
93 struct vop_reg hdmi_dclk_pol;
94 struct vop_reg mipi_pin_pol;
95 struct vop_reg mipi_dclk_pol;
96 struct vop_reg rgb_pin_pol;
97 struct vop_reg rgb_dclk_pol;
98 struct vop_reg dp_en;
99 struct vop_reg edp_en;
100 struct vop_reg hdmi_en;
101 struct vop_reg mipi_en;
102 struct vop_reg mipi_dual_channel_en;
103 struct vop_reg rgb_en;
104};
105
106struct vop_common {
107 struct vop_reg cfg_done;
108 struct vop_reg dsp_blank;
109 struct vop_reg data_blank;
110 struct vop_reg pre_dither_down;
111 struct vop_reg dither_down_sel;
112 struct vop_reg dither_down_mode;
113 struct vop_reg dither_down_en;
114 struct vop_reg dither_up;
115 struct vop_reg dsp_lut_en;
116 struct vop_reg update_gamma_lut;
117 struct vop_reg lut_buffer_index;
118 struct vop_reg gate_en;
119 struct vop_reg mmu_en;
120 struct vop_reg out_mode;
121 struct vop_reg standby;
122};
123
124struct vop_misc {
125 struct vop_reg global_regdone_en;
126};
127
128struct vop_intr {
129 const int *intrs;
130 uint32_t nintrs;
131
132 struct vop_reg line_flag_num[2];
133 struct vop_reg enable;
134 struct vop_reg clear;
135 struct vop_reg status;
136};
137
138struct vop_scl_extension {
139 struct vop_reg cbcr_vsd_mode;
140 struct vop_reg cbcr_vsu_mode;
141 struct vop_reg cbcr_hsd_mode;
142 struct vop_reg cbcr_ver_scl_mode;
143 struct vop_reg cbcr_hor_scl_mode;
144 struct vop_reg yrgb_vsd_mode;
145 struct vop_reg yrgb_vsu_mode;
146 struct vop_reg yrgb_hsd_mode;
147 struct vop_reg yrgb_ver_scl_mode;
148 struct vop_reg yrgb_hor_scl_mode;
149 struct vop_reg line_load_mode;
150 struct vop_reg cbcr_axi_gather_num;
151 struct vop_reg yrgb_axi_gather_num;
152 struct vop_reg vsd_cbcr_gt2;
153 struct vop_reg vsd_cbcr_gt4;
154 struct vop_reg vsd_yrgb_gt2;
155 struct vop_reg vsd_yrgb_gt4;
156 struct vop_reg bic_coe_sel;
157 struct vop_reg cbcr_axi_gather_en;
158 struct vop_reg yrgb_axi_gather_en;
159 struct vop_reg lb_mode;
160};
161
162struct vop_scl_regs {
163 const struct vop_scl_extension *ext;
164
165 struct vop_reg scale_yrgb_x;
166 struct vop_reg scale_yrgb_y;
167 struct vop_reg scale_cbcr_x;
168 struct vop_reg scale_cbcr_y;
169};
170
171struct vop_yuv2yuv_phy {
172 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];
173};
174
175struct vop_win_phy {
176 const struct vop_scl_regs *scl;
177 const uint32_t *data_formats;
178 uint32_t nformats;
179 const uint64_t *format_modifiers;
180
181 struct vop_reg enable;
182 struct vop_reg gate;
183 struct vop_reg format;
184 struct vop_reg rb_swap;
185 struct vop_reg uv_swap;
186 struct vop_reg act_info;
187 struct vop_reg dsp_info;
188 struct vop_reg dsp_st;
189 struct vop_reg yrgb_mst;
190 struct vop_reg uv_mst;
191 struct vop_reg yrgb_vir;
192 struct vop_reg uv_vir;
193 struct vop_reg y_mir_en;
194 struct vop_reg x_mir_en;
195
196 struct vop_reg dst_alpha_ctl;
197 struct vop_reg src_alpha_ctl;
198 struct vop_reg alpha_pre_mul;
199 struct vop_reg alpha_mode;
200 struct vop_reg alpha_en;
201 struct vop_reg channel;
202};
203
204struct vop_win_yuv2yuv_data {
205 uint32_t base;
206 const struct vop_yuv2yuv_phy *phy;
207 struct vop_reg y2r_en;
208};
209
210struct vop_win_data {
211 uint32_t base;
212 const struct vop_win_phy *phy;
213 enum drm_plane_type type;
214};
215
216struct vop_data {
217 uint32_t version;
218 const struct vop_intr *intr;
219 const struct vop_common *common;
220 const struct vop_misc *misc;
221 const struct vop_modeset *modeset;
222 const struct vop_output *output;
223 const struct vop_afbc *afbc;
224 const struct vop_win_yuv2yuv_data *win_yuv2yuv;
225 const struct vop_win_data *win;
226 unsigned int win_size;
227 unsigned int lut_size;
228
229#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)
230#define VOP_FEATURE_INTERNAL_RGB BIT(1)
231 u64 feature;
232};
233
234/* interrupt define */
235#define DSP_HOLD_VALID_INTR (1 << 0)
236#define FS_INTR (1 << 1)
237#define LINE_FLAG_INTR (1 << 2)
238#define BUS_ERROR_INTR (1 << 3)
239
240#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
241 LINE_FLAG_INTR | BUS_ERROR_INTR)
242
243#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
244#define FS_INTR_EN(x) ((x) << 5)
245#define LINE_FLAG_INTR_EN(x) ((x) << 6)
246#define BUS_ERROR_INTR_EN(x) ((x) << 7)
247#define DSP_HOLD_VALID_INTR_MASK (1 << 4)
248#define FS_INTR_MASK (1 << 5)
249#define LINE_FLAG_INTR_MASK (1 << 6)
250#define BUS_ERROR_INTR_MASK (1 << 7)
251
252#define INTR_CLR_SHIFT 8
253#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))
254#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))
255#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))
256#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))
257
258#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)
259#define DSP_LINE_NUM_MASK (0x1fff << 12)
260
261/* src alpha ctrl define */
262#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)
263#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)
264#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)
265#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)
266#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)
267#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)
268#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)
269#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)
270/* dst alpha ctrl define */
271#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)
272
273/*
274 * display output interface supported by rockchip lcdc
275 */
276#define ROCKCHIP_OUT_MODE_P888 0
277#define ROCKCHIP_OUT_MODE_P666 1
278#define ROCKCHIP_OUT_MODE_P565 2
279/* for use special outface */
280#define ROCKCHIP_OUT_MODE_AAAA 15
281
282/* output flags */
283#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0)
284
285enum alpha_mode {
286 ALPHA_STRAIGHT,
287 ALPHA_INVERSE,
288};
289
290enum global_blend_mode {
291 ALPHA_GLOBAL,
292 ALPHA_PER_PIX,
293 ALPHA_PER_PIX_GLOBAL,
294};
295
296enum alpha_cal_mode {
297 ALPHA_SATURATION,
298 ALPHA_NO_SATURATION,
299};
300
301enum color_mode {
302 ALPHA_SRC_PRE_MUL,
303 ALPHA_SRC_NO_PRE_MUL,
304};
305
306enum factor_mode {
307 ALPHA_ZERO,
308 ALPHA_ONE,
309 ALPHA_SRC,
310 ALPHA_SRC_INVERSE,
311 ALPHA_SRC_GLOBAL,
312};
313
314enum scale_mode {
315 SCALE_NONE = 0x0,
316 SCALE_UP = 0x1,
317 SCALE_DOWN = 0x2
318};
319
320enum lb_mode {
321 LB_YUV_3840X5 = 0x0,
322 LB_YUV_2560X8 = 0x1,
323 LB_RGB_3840X2 = 0x2,
324 LB_RGB_2560X4 = 0x3,
325 LB_RGB_1920X5 = 0x4,
326 LB_RGB_1280X8 = 0x5
327};
328
329enum sacle_up_mode {
330 SCALE_UP_BIL = 0x0,
331 SCALE_UP_BIC = 0x1
332};
333
334enum scale_down_mode {
335 SCALE_DOWN_BIL = 0x0,
336 SCALE_DOWN_AVG = 0x1
337};
338
339enum dither_down_mode {
340 RGB888_TO_RGB565 = 0x0,
341 RGB888_TO_RGB666 = 0x1
342};
343
344enum dither_down_mode_sel {
345 DITHER_DOWN_ALLEGRO = 0x0,
346 DITHER_DOWN_FRC = 0x1
347};
348
349enum vop_pol {
350 HSYNC_POSITIVE = 0,
351 VSYNC_POSITIVE = 1,
352 DEN_NEGATIVE = 2
353};
354
355#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
356#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
357#define SCL_MAX_VSKIPLINES 4
358#define MIN_SCL_FT_AFTER_VSKIP 1
359
360static inline uint16_t scl_cal_scale(int src, int dst, int shift)
361{
362 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);
363}
364
365static inline uint16_t scl_cal_scale2(int src, int dst)
366{
367 return ((src - 1) << 12) / (dst - 1);
368}
369
370#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)
371#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)
372#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)
373
374static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
375 int vskiplines)
376{
377 int act_height;
378
379 act_height = DIV_ROUND_UP(src_h, vskiplines);
380
381 if (act_height == dst_h)
382 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
383
384 return GET_SCL_FT_BILI_DN(act_height, dst_h);
385}
386
387static inline enum scale_mode scl_get_scl_mode(int src, int dst)
388{
389 if (src < dst)
390 return SCALE_UP;
391 else if (src > dst)
392 return SCALE_DOWN;
393
394 return SCALE_NONE;
395}
396
397static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)
398{
399 uint32_t vskiplines;
400
401 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)
402 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)
403 break;
404
405 return vskiplines;
406}
407
408static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
409{
410 int lb_mode;
411
412 if (is_yuv) {
413 if (width > 1280)
414 lb_mode = LB_YUV_3840X5;
415 else
416 lb_mode = LB_YUV_2560X8;
417 } else {
418 if (width > 2560)
419 lb_mode = LB_RGB_3840X2;
420 else if (width > 1920)
421 lb_mode = LB_RGB_2560X4;
422 else
423 lb_mode = LB_RGB_1920X5;
424 }
425
426 return lb_mode;
427}
428
429extern const struct component_ops vop_component_ops;
430#endif /* _ROCKCHIP_DRM_VOP_H */