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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * R-Car LVDS Encoder
4 *
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/io.h>
13#include <linux/media-bus-format.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/of_graph.h>
18#include <linux/platform_device.h>
19#include <linux/slab.h>
20#include <linux/sys_soc.h>
21
22#include <drm/drm_atomic.h>
23#include <drm/drm_atomic_helper.h>
24#include <drm/drm_bridge.h>
25#include <drm/drm_of.h>
26#include <drm/drm_panel.h>
27#include <drm/drm_print.h>
28#include <drm/drm_probe_helper.h>
29
30#include "rcar_lvds.h"
31#include "rcar_lvds_regs.h"
32
33struct rcar_lvds;
34
35/* Keep in sync with the LVDCR0.LVMD hardware register values. */
36enum rcar_lvds_mode {
37 RCAR_LVDS_MODE_JEIDA = 0,
38 RCAR_LVDS_MODE_MIRROR = 1,
39 RCAR_LVDS_MODE_VESA = 4,
40};
41
42enum rcar_lvds_link_type {
43 RCAR_LVDS_SINGLE_LINK = 0,
44 RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS = 1,
45 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS = 2,
46};
47
48#define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
49#define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */
50#define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */
51#define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
52#define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
53
54struct rcar_lvds_device_info {
55 unsigned int gen;
56 unsigned int quirks;
57 void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
58};
59
60struct rcar_lvds {
61 struct device *dev;
62 const struct rcar_lvds_device_info *info;
63
64 struct drm_bridge bridge;
65
66 struct drm_bridge *next_bridge;
67 struct drm_panel *panel;
68
69 void __iomem *mmio;
70 struct {
71 struct clk *mod; /* CPG module clock */
72 struct clk *extal; /* External clock */
73 struct clk *dotclkin[2]; /* External DU clocks */
74 } clocks;
75
76 struct drm_bridge *companion;
77 enum rcar_lvds_link_type link_type;
78};
79
80#define bridge_to_rcar_lvds(b) \
81 container_of(b, struct rcar_lvds, bridge)
82
83static void rcar_lvds_write(struct rcar_lvds *lvds, u32 reg, u32 data)
84{
85 iowrite32(data, lvds->mmio + reg);
86}
87
88/* -----------------------------------------------------------------------------
89 * PLL Setup
90 */
91
92static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
93{
94 u32 val;
95
96 if (freq < 39000000)
97 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
98 else if (freq < 61000000)
99 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
100 else if (freq < 121000000)
101 val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
102 else
103 val = LVDPLLCR_PLLDLYCNT_150M;
104
105 rcar_lvds_write(lvds, LVDPLLCR, val);
106}
107
108static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
109{
110 u32 val;
111
112 if (freq < 42000000)
113 val = LVDPLLCR_PLLDIVCNT_42M;
114 else if (freq < 85000000)
115 val = LVDPLLCR_PLLDIVCNT_85M;
116 else if (freq < 128000000)
117 val = LVDPLLCR_PLLDIVCNT_128M;
118 else
119 val = LVDPLLCR_PLLDIVCNT_148M;
120
121 rcar_lvds_write(lvds, LVDPLLCR, val);
122}
123
124struct pll_info {
125 unsigned long diff;
126 unsigned int pll_m;
127 unsigned int pll_n;
128 unsigned int pll_e;
129 unsigned int div;
130 u32 clksel;
131};
132
133static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
134 unsigned long target, struct pll_info *pll,
135 u32 clksel, bool dot_clock_only)
136{
137 unsigned int div7 = dot_clock_only ? 1 : 7;
138 unsigned long output;
139 unsigned long fin;
140 unsigned int m_min;
141 unsigned int m_max;
142 unsigned int m;
143 int error;
144
145 if (!clk)
146 return;
147
148 /*
149 * The LVDS PLL is made of a pre-divider and a multiplier (strangely
150 * enough called M and N respectively), followed by a post-divider E.
151 *
152 * ,-----. ,-----. ,-----. ,-----.
153 * Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
154 * `-----' ,-> | | `-----' | `-----'
155 * | `-----' |
156 * | ,-----. |
157 * `-------- | 1/N | <-------'
158 * `-----'
159 *
160 * The clock output by the PLL is then further divided by a programmable
161 * divider DIV to achieve the desired target frequency. Finally, an
162 * optional fixed /7 divider is used to convert the bit clock to a pixel
163 * clock (as LVDS transmits 7 bits per lane per clock sample).
164 *
165 * ,-------. ,-----. |\
166 * Fout --> | 1/DIV | --> | 1/7 | --> | |
167 * `-------' | `-----' | | --> dot clock
168 * `------------> | |
169 * |/
170 *
171 * The /7 divider is optional, it is enabled when the LVDS PLL is used
172 * to drive the LVDS encoder, and disabled when used to generate a dot
173 * clock for the DU RGB output, without using the LVDS encoder.
174 *
175 * The PLL allowed input frequency range is 12 MHz to 192 MHz.
176 */
177
178 fin = clk_get_rate(clk);
179 if (fin < 12000000 || fin > 192000000)
180 return;
181
182 /*
183 * The comparison frequency range is 12 MHz to 24 MHz, which limits the
184 * allowed values for the pre-divider M (normal range 1-8).
185 *
186 * Fpfd = Fin / M
187 */
188 m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
189 m_max = min_t(unsigned int, 8, fin / 12000000);
190
191 for (m = m_min; m <= m_max; ++m) {
192 unsigned long fpfd;
193 unsigned int n_min;
194 unsigned int n_max;
195 unsigned int n;
196
197 /*
198 * The VCO operating range is 900 Mhz to 1800 MHz, which limits
199 * the allowed values for the multiplier N (normal range
200 * 60-120).
201 *
202 * Fvco = Fin * N / M
203 */
204 fpfd = fin / m;
205 n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
206 n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
207
208 for (n = n_min; n < n_max; ++n) {
209 unsigned long fvco;
210 unsigned int e_min;
211 unsigned int e;
212
213 /*
214 * The output frequency is limited to 1039.5 MHz,
215 * limiting again the allowed values for the
216 * post-divider E (normal value 1, 2 or 4).
217 *
218 * Fout = Fvco / E
219 */
220 fvco = fpfd * n;
221 e_min = fvco > 1039500000 ? 1 : 0;
222
223 for (e = e_min; e < 3; ++e) {
224 unsigned long fout;
225 unsigned long diff;
226 unsigned int div;
227
228 /*
229 * Finally we have a programable divider after
230 * the PLL, followed by a an optional fixed /7
231 * divider.
232 */
233 fout = fvco / (1 << e) / div7;
234 div = max(1UL, DIV_ROUND_CLOSEST(fout, target));
235 diff = abs(fout / div - target);
236
237 if (diff < pll->diff) {
238 pll->diff = diff;
239 pll->pll_m = m;
240 pll->pll_n = n;
241 pll->pll_e = e;
242 pll->div = div;
243 pll->clksel = clksel;
244
245 if (diff == 0)
246 goto done;
247 }
248 }
249 }
250 }
251
252done:
253 output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
254 / div7 / pll->div;
255 error = (long)(output - target) * 10000 / (long)target;
256
257 dev_dbg(lvds->dev,
258 "%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
259 clk, fin, output, target, error / 100,
260 error < 0 ? -error % 100 : error % 100,
261 pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
262}
263
264static void __rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds,
265 unsigned int freq, bool dot_clock_only)
266{
267 struct pll_info pll = { .diff = (unsigned long)-1 };
268 u32 lvdpllcr;
269
270 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
271 LVDPLLCR_CKSEL_DU_DOTCLKIN(0), dot_clock_only);
272 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
273 LVDPLLCR_CKSEL_DU_DOTCLKIN(1), dot_clock_only);
274 rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
275 LVDPLLCR_CKSEL_EXTAL, dot_clock_only);
276
277 lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
278 | LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
279
280 if (pll.pll_e > 0)
281 lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
282 | LVDPLLCR_PLLE(pll.pll_e - 1);
283
284 if (dot_clock_only)
285 lvdpllcr |= LVDPLLCR_OCKSEL;
286
287 rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
288
289 if (pll.div > 1)
290 /*
291 * The DIVRESET bit is a misnomer, setting it to 1 deasserts the
292 * divisor reset.
293 */
294 rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
295 LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
296 else
297 rcar_lvds_write(lvds, LVDDIV, 0);
298}
299
300static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
301{
302 __rcar_lvds_pll_setup_d3_e3(lvds, freq, false);
303}
304
305/* -----------------------------------------------------------------------------
306 * Clock - D3/E3 only
307 */
308
309int rcar_lvds_pclk_enable(struct drm_bridge *bridge, unsigned long freq)
310{
311 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
312 int ret;
313
314 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
315 return -ENODEV;
316
317 dev_dbg(lvds->dev, "enabling LVDS PLL, freq=%luHz\n", freq);
318
319 ret = clk_prepare_enable(lvds->clocks.mod);
320 if (ret < 0)
321 return ret;
322
323 __rcar_lvds_pll_setup_d3_e3(lvds, freq, true);
324
325 return 0;
326}
327EXPORT_SYMBOL_GPL(rcar_lvds_pclk_enable);
328
329void rcar_lvds_pclk_disable(struct drm_bridge *bridge)
330{
331 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
332
333 if (WARN_ON(!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)))
334 return;
335
336 dev_dbg(lvds->dev, "disabling LVDS PLL\n");
337
338 rcar_lvds_write(lvds, LVDPLLCR, 0);
339
340 clk_disable_unprepare(lvds->clocks.mod);
341}
342EXPORT_SYMBOL_GPL(rcar_lvds_pclk_disable);
343
344/* -----------------------------------------------------------------------------
345 * Bridge
346 */
347
348static enum rcar_lvds_mode rcar_lvds_get_lvds_mode(struct rcar_lvds *lvds,
349 const struct drm_connector *connector)
350{
351 const struct drm_display_info *info;
352 enum rcar_lvds_mode mode;
353
354 /*
355 * There is no API yet to retrieve LVDS mode from a bridge, only panels
356 * are supported.
357 */
358 if (!lvds->panel)
359 return RCAR_LVDS_MODE_JEIDA;
360
361 info = &connector->display_info;
362 if (!info->num_bus_formats || !info->bus_formats) {
363 dev_warn(lvds->dev,
364 "no LVDS bus format reported, using JEIDA\n");
365 return RCAR_LVDS_MODE_JEIDA;
366 }
367
368 switch (info->bus_formats[0]) {
369 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
370 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
371 mode = RCAR_LVDS_MODE_JEIDA;
372 break;
373 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
374 mode = RCAR_LVDS_MODE_VESA;
375 break;
376 default:
377 dev_warn(lvds->dev,
378 "unsupported LVDS bus format 0x%04x, using JEIDA\n",
379 info->bus_formats[0]);
380 return RCAR_LVDS_MODE_JEIDA;
381 }
382
383 if (info->bus_flags & DRM_BUS_FLAG_DATA_LSB_TO_MSB)
384 mode |= RCAR_LVDS_MODE_MIRROR;
385
386 return mode;
387}
388
389static void __rcar_lvds_atomic_enable(struct drm_bridge *bridge,
390 struct drm_atomic_state *state,
391 struct drm_crtc *crtc,
392 struct drm_connector *connector)
393{
394 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
395 u32 lvdhcr;
396 u32 lvdcr0;
397 int ret;
398
399 ret = clk_prepare_enable(lvds->clocks.mod);
400 if (ret < 0)
401 return;
402
403 /* Enable the companion LVDS encoder in dual-link mode. */
404 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
405 __rcar_lvds_atomic_enable(lvds->companion, state, crtc,
406 connector);
407
408 /*
409 * Hardcode the channels and control signals routing for now.
410 *
411 * HSYNC -> CTRL0
412 * VSYNC -> CTRL1
413 * DISP -> CTRL2
414 * 0 -> CTRL3
415 */
416 rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
417 LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
418 LVDCTRCR_CTR0SEL_HSYNC);
419
420 if (lvds->info->quirks & RCAR_LVDS_QUIRK_LANES)
421 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
422 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
423 else
424 lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
425 | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
426
427 rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
428
429 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
430 u32 lvdstripe = 0;
431
432 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK) {
433 /*
434 * By default we generate even pixels from the primary
435 * encoder and odd pixels from the companion encoder.
436 * Swap pixels around if the sink requires odd pixels
437 * from the primary encoder and even pixels from the
438 * companion encoder.
439 */
440 bool swap_pixels = lvds->link_type ==
441 RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
442
443 /*
444 * Configure vertical stripe since we are dealing with
445 * an LVDS dual-link connection.
446 *
447 * ST_SWAP is reserved for the companion encoder, only
448 * set it in the primary encoder.
449 */
450 lvdstripe = LVDSTRIPE_ST_ON
451 | (lvds->companion && swap_pixels ?
452 LVDSTRIPE_ST_SWAP : 0);
453 }
454 rcar_lvds_write(lvds, LVDSTRIPE, lvdstripe);
455 }
456
457 /*
458 * PLL clock configuration on all instances but the companion in
459 * dual-link mode.
460 */
461 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK || lvds->companion) {
462 const struct drm_crtc_state *crtc_state =
463 drm_atomic_get_new_crtc_state(state, crtc);
464 const struct drm_display_mode *mode =
465 &crtc_state->adjusted_mode;
466
467 lvds->info->pll_setup(lvds, mode->clock * 1000);
468 }
469
470 /* Set the LVDS mode and select the input. */
471 lvdcr0 = rcar_lvds_get_lvds_mode(lvds, connector) << LVDCR0_LVMD_SHIFT;
472
473 if (lvds->bridge.encoder) {
474 if (drm_crtc_index(crtc) == 2)
475 lvdcr0 |= LVDCR0_DUSEL;
476 }
477
478 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
479
480 /* Turn all the channels on. */
481 rcar_lvds_write(lvds, LVDCR1,
482 LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
483 LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
484
485 if (lvds->info->gen < 3) {
486 /* Enable LVDS operation and turn the bias circuitry on. */
487 lvdcr0 |= LVDCR0_BEN | LVDCR0_LVEN;
488 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
489 }
490
491 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
492 /*
493 * Turn the PLL on (simple PLL only, extended PLL is fully
494 * controlled through LVDPLLCR).
495 */
496 lvdcr0 |= LVDCR0_PLLON;
497 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
498 }
499
500 if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
501 /* Set LVDS normal mode. */
502 lvdcr0 |= LVDCR0_PWD;
503 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
504 }
505
506 if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN3_LVEN) {
507 /*
508 * Turn on the LVDS PHY. On D3, the LVEN and LVRES bit must be
509 * set at the same time, so don't write the register yet.
510 */
511 lvdcr0 |= LVDCR0_LVEN;
512 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_PWD))
513 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
514 }
515
516 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
517 /* Wait for the PLL startup delay (simple PLL only). */
518 usleep_range(100, 150);
519 }
520
521 /* Turn the output on. */
522 lvdcr0 |= LVDCR0_LVRES;
523 rcar_lvds_write(lvds, LVDCR0, lvdcr0);
524}
525
526static void rcar_lvds_atomic_enable(struct drm_bridge *bridge,
527 struct drm_bridge_state *old_bridge_state)
528{
529 struct drm_atomic_state *state = old_bridge_state->base.state;
530 struct drm_connector *connector;
531 struct drm_crtc *crtc;
532
533 connector = drm_atomic_get_new_connector_for_encoder(state,
534 bridge->encoder);
535 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
536
537 __rcar_lvds_atomic_enable(bridge, state, crtc, connector);
538}
539
540static void rcar_lvds_atomic_disable(struct drm_bridge *bridge,
541 struct drm_bridge_state *old_bridge_state)
542{
543 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
544
545 rcar_lvds_write(lvds, LVDCR0, 0);
546 rcar_lvds_write(lvds, LVDCR1, 0);
547 rcar_lvds_write(lvds, LVDPLLCR, 0);
548
549 /* Disable the companion LVDS encoder in dual-link mode. */
550 if (lvds->link_type != RCAR_LVDS_SINGLE_LINK && lvds->companion)
551 lvds->companion->funcs->atomic_disable(lvds->companion,
552 old_bridge_state);
553
554 clk_disable_unprepare(lvds->clocks.mod);
555}
556
557static bool rcar_lvds_mode_fixup(struct drm_bridge *bridge,
558 const struct drm_display_mode *mode,
559 struct drm_display_mode *adjusted_mode)
560{
561 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
562 int min_freq;
563
564 /*
565 * The internal LVDS encoder has a restricted clock frequency operating
566 * range, from 5MHz to 148.5MHz on D3 and E3, and from 31MHz to
567 * 148.5MHz on all other platforms. Clamp the clock accordingly.
568 */
569 min_freq = lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL ? 5000 : 31000;
570 adjusted_mode->clock = clamp(adjusted_mode->clock, min_freq, 148500);
571
572 return true;
573}
574
575static int rcar_lvds_attach(struct drm_bridge *bridge,
576 enum drm_bridge_attach_flags flags)
577{
578 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
579
580 if (!lvds->next_bridge)
581 return 0;
582
583 return drm_bridge_attach(bridge->encoder, lvds->next_bridge, bridge,
584 flags);
585}
586
587static const struct drm_bridge_funcs rcar_lvds_bridge_ops = {
588 .attach = rcar_lvds_attach,
589 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
590 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
591 .atomic_reset = drm_atomic_helper_bridge_reset,
592 .atomic_enable = rcar_lvds_atomic_enable,
593 .atomic_disable = rcar_lvds_atomic_disable,
594 .mode_fixup = rcar_lvds_mode_fixup,
595};
596
597bool rcar_lvds_dual_link(struct drm_bridge *bridge)
598{
599 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
600
601 return lvds->link_type != RCAR_LVDS_SINGLE_LINK;
602}
603EXPORT_SYMBOL_GPL(rcar_lvds_dual_link);
604
605bool rcar_lvds_is_connected(struct drm_bridge *bridge)
606{
607 struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
608
609 return lvds->next_bridge != NULL;
610}
611EXPORT_SYMBOL_GPL(rcar_lvds_is_connected);
612
613/* -----------------------------------------------------------------------------
614 * Probe & Remove
615 */
616
617static int rcar_lvds_parse_dt_companion(struct rcar_lvds *lvds)
618{
619 const struct of_device_id *match;
620 struct device_node *companion;
621 struct device_node *port0, *port1;
622 struct rcar_lvds *companion_lvds;
623 struct device *dev = lvds->dev;
624 int dual_link;
625 int ret = 0;
626
627 /* Locate the companion LVDS encoder for dual-link operation, if any. */
628 companion = of_parse_phandle(dev->of_node, "renesas,companion", 0);
629 if (!companion)
630 return 0;
631
632 /*
633 * Sanity check: the companion encoder must have the same compatible
634 * string.
635 */
636 match = of_match_device(dev->driver->of_match_table, dev);
637 if (!of_device_is_compatible(companion, match->compatible)) {
638 dev_err(dev, "Companion LVDS encoder is invalid\n");
639 ret = -ENXIO;
640 goto done;
641 }
642
643 /*
644 * We need to work out if the sink is expecting us to function in
645 * dual-link mode. We do this by looking at the DT port nodes we are
646 * connected to, if they are marked as expecting even pixels and
647 * odd pixels than we need to enable vertical stripe output.
648 */
649 port0 = of_graph_get_port_by_id(dev->of_node, 1);
650 port1 = of_graph_get_port_by_id(companion, 1);
651 dual_link = drm_of_lvds_get_dual_link_pixel_order(port0, port1);
652 of_node_put(port0);
653 of_node_put(port1);
654
655 switch (dual_link) {
656 case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS:
657 lvds->link_type = RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS;
658 break;
659 case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS:
660 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
661 break;
662 default:
663 /*
664 * Early dual-link bridge specific implementations populate the
665 * timings field of drm_bridge. If the flag is set, we assume
666 * that we are expected to generate even pixels from the primary
667 * encoder, and odd pixels from the companion encoder.
668 */
669 if (lvds->next_bridge->timings &&
670 lvds->next_bridge->timings->dual_link)
671 lvds->link_type = RCAR_LVDS_DUAL_LINK_EVEN_ODD_PIXELS;
672 else
673 lvds->link_type = RCAR_LVDS_SINGLE_LINK;
674 }
675
676 if (lvds->link_type == RCAR_LVDS_SINGLE_LINK) {
677 dev_dbg(dev, "Single-link configuration detected\n");
678 goto done;
679 }
680
681 lvds->companion = of_drm_find_bridge(companion);
682 if (!lvds->companion) {
683 ret = -EPROBE_DEFER;
684 goto done;
685 }
686
687 dev_dbg(dev,
688 "Dual-link configuration detected (companion encoder %pOF)\n",
689 companion);
690
691 if (lvds->link_type == RCAR_LVDS_DUAL_LINK_ODD_EVEN_PIXELS)
692 dev_dbg(dev, "Data swapping required\n");
693
694 /*
695 * FIXME: We should not be messing with the companion encoder private
696 * data from the primary encoder, we should rather let the companion
697 * encoder work things out on its own. However, the companion encoder
698 * doesn't hold a reference to the primary encoder, and
699 * drm_of_lvds_get_dual_link_pixel_order needs to be given references
700 * to the output ports of both encoders, therefore leave it like this
701 * for the time being.
702 */
703 companion_lvds = bridge_to_rcar_lvds(lvds->companion);
704 companion_lvds->link_type = lvds->link_type;
705
706done:
707 of_node_put(companion);
708
709 return ret;
710}
711
712static int rcar_lvds_parse_dt(struct rcar_lvds *lvds)
713{
714 int ret;
715
716 ret = drm_of_find_panel_or_bridge(lvds->dev->of_node, 1, 0,
717 &lvds->panel, &lvds->next_bridge);
718 if (ret)
719 goto done;
720
721 if (lvds->panel) {
722 lvds->next_bridge = devm_drm_panel_bridge_add(lvds->dev,
723 lvds->panel);
724 if (IS_ERR_OR_NULL(lvds->next_bridge)) {
725 ret = -EINVAL;
726 goto done;
727 }
728 }
729
730 if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK)
731 ret = rcar_lvds_parse_dt_companion(lvds);
732
733done:
734 /*
735 * On D3/E3 the LVDS encoder provides a clock to the DU, which can be
736 * used for the DPAD output even when the LVDS output is not connected.
737 * Don't fail probe in that case as the DU will need the bridge to
738 * control the clock.
739 */
740 if (lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)
741 return ret == -ENODEV ? 0 : ret;
742
743 return ret;
744}
745
746static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
747 bool optional)
748{
749 struct clk *clk;
750
751 clk = devm_clk_get(lvds->dev, name);
752 if (!IS_ERR(clk))
753 return clk;
754
755 if (PTR_ERR(clk) == -ENOENT && optional)
756 return NULL;
757
758 dev_err_probe(lvds->dev, PTR_ERR(clk), "failed to get %s clock\n",
759 name ? name : "module");
760
761 return clk;
762}
763
764static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
765{
766 lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
767 if (IS_ERR(lvds->clocks.mod))
768 return PTR_ERR(lvds->clocks.mod);
769
770 /*
771 * LVDS encoders without an extended PLL have no external clock inputs.
772 */
773 if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
774 return 0;
775
776 lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
777 if (IS_ERR(lvds->clocks.extal))
778 return PTR_ERR(lvds->clocks.extal);
779
780 lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
781 if (IS_ERR(lvds->clocks.dotclkin[0]))
782 return PTR_ERR(lvds->clocks.dotclkin[0]);
783
784 lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
785 if (IS_ERR(lvds->clocks.dotclkin[1]))
786 return PTR_ERR(lvds->clocks.dotclkin[1]);
787
788 /* At least one input to the PLL must be available. */
789 if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
790 !lvds->clocks.dotclkin[1]) {
791 dev_err(lvds->dev,
792 "no input clock (extal, dclkin.0 or dclkin.1)\n");
793 return -EINVAL;
794 }
795
796 return 0;
797}
798
799static const struct rcar_lvds_device_info rcar_lvds_r8a7790es1_info = {
800 .gen = 2,
801 .quirks = RCAR_LVDS_QUIRK_LANES,
802 .pll_setup = rcar_lvds_pll_setup_gen2,
803};
804
805static const struct soc_device_attribute lvds_quirk_matches[] = {
806 {
807 .soc_id = "r8a7790", .revision = "ES1.*",
808 .data = &rcar_lvds_r8a7790es1_info,
809 },
810 { /* sentinel */ }
811};
812
813static int rcar_lvds_probe(struct platform_device *pdev)
814{
815 const struct soc_device_attribute *attr;
816 struct rcar_lvds *lvds;
817 int ret;
818
819 lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
820 if (lvds == NULL)
821 return -ENOMEM;
822
823 platform_set_drvdata(pdev, lvds);
824
825 lvds->dev = &pdev->dev;
826 lvds->info = of_device_get_match_data(&pdev->dev);
827
828 attr = soc_device_match(lvds_quirk_matches);
829 if (attr)
830 lvds->info = attr->data;
831
832 ret = rcar_lvds_parse_dt(lvds);
833 if (ret < 0)
834 return ret;
835
836 lvds->bridge.funcs = &rcar_lvds_bridge_ops;
837 lvds->bridge.of_node = pdev->dev.of_node;
838
839 lvds->mmio = devm_platform_ioremap_resource(pdev, 0);
840 if (IS_ERR(lvds->mmio))
841 return PTR_ERR(lvds->mmio);
842
843 ret = rcar_lvds_get_clocks(lvds);
844 if (ret < 0)
845 return ret;
846
847 drm_bridge_add(&lvds->bridge);
848
849 return 0;
850}
851
852static int rcar_lvds_remove(struct platform_device *pdev)
853{
854 struct rcar_lvds *lvds = platform_get_drvdata(pdev);
855
856 drm_bridge_remove(&lvds->bridge);
857
858 return 0;
859}
860
861static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
862 .gen = 2,
863 .pll_setup = rcar_lvds_pll_setup_gen2,
864};
865
866static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
867 .gen = 3,
868 .quirks = RCAR_LVDS_QUIRK_PWD,
869 .pll_setup = rcar_lvds_pll_setup_gen3,
870};
871
872static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
873 .gen = 3,
874 .quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
875 .pll_setup = rcar_lvds_pll_setup_gen2,
876};
877
878static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
879 .gen = 3,
880 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
881 | RCAR_LVDS_QUIRK_DUAL_LINK,
882 .pll_setup = rcar_lvds_pll_setup_d3_e3,
883};
884
885static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
886 .gen = 3,
887 .quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
888 | RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
889 .pll_setup = rcar_lvds_pll_setup_d3_e3,
890};
891
892static const struct of_device_id rcar_lvds_of_table[] = {
893 { .compatible = "renesas,r8a7742-lvds", .data = &rcar_lvds_gen2_info },
894 { .compatible = "renesas,r8a7743-lvds", .data = &rcar_lvds_gen2_info },
895 { .compatible = "renesas,r8a7744-lvds", .data = &rcar_lvds_gen2_info },
896 { .compatible = "renesas,r8a774a1-lvds", .data = &rcar_lvds_gen3_info },
897 { .compatible = "renesas,r8a774b1-lvds", .data = &rcar_lvds_gen3_info },
898 { .compatible = "renesas,r8a774c0-lvds", .data = &rcar_lvds_r8a77990_info },
899 { .compatible = "renesas,r8a774e1-lvds", .data = &rcar_lvds_gen3_info },
900 { .compatible = "renesas,r8a7790-lvds", .data = &rcar_lvds_gen2_info },
901 { .compatible = "renesas,r8a7791-lvds", .data = &rcar_lvds_gen2_info },
902 { .compatible = "renesas,r8a7793-lvds", .data = &rcar_lvds_gen2_info },
903 { .compatible = "renesas,r8a7795-lvds", .data = &rcar_lvds_gen3_info },
904 { .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
905 { .compatible = "renesas,r8a77961-lvds", .data = &rcar_lvds_gen3_info },
906 { .compatible = "renesas,r8a77965-lvds", .data = &rcar_lvds_gen3_info },
907 { .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
908 { .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
909 { .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
910 { .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
911 { }
912};
913
914MODULE_DEVICE_TABLE(of, rcar_lvds_of_table);
915
916static struct platform_driver rcar_lvds_platform_driver = {
917 .probe = rcar_lvds_probe,
918 .remove = rcar_lvds_remove,
919 .driver = {
920 .name = "rcar-lvds",
921 .of_match_table = rcar_lvds_of_table,
922 },
923};
924
925module_platform_driver(rcar_lvds_platform_driver);
926
927MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
928MODULE_DESCRIPTION("Renesas R-Car LVDS Encoder Driver");
929MODULE_LICENSE("GPL");