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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * R-Car Display Unit CRTCs
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#include <linux/clk.h>
11#include <linux/mutex.h>
12#include <linux/platform_device.h>
13#include <linux/sys_soc.h>
14
15#include <drm/drm_atomic.h>
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_bridge.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_device.h>
20#include <drm/drm_gem_dma_helper.h>
21#include <drm/drm_vblank.h>
22
23#include "rcar_cmm.h"
24#include "rcar_du_crtc.h"
25#include "rcar_du_drv.h"
26#include "rcar_du_encoder.h"
27#include "rcar_du_kms.h"
28#include "rcar_du_plane.h"
29#include "rcar_du_regs.h"
30#include "rcar_du_vsp.h"
31#include "rcar_lvds.h"
32#include "rcar_mipi_dsi.h"
33
34static u32 rcar_du_crtc_read(struct rcar_du_crtc *rcrtc, u32 reg)
35{
36 struct rcar_du_device *rcdu = rcrtc->dev;
37
38 return rcar_du_read(rcdu, rcrtc->mmio_offset + reg);
39}
40
41static void rcar_du_crtc_write(struct rcar_du_crtc *rcrtc, u32 reg, u32 data)
42{
43 struct rcar_du_device *rcdu = rcrtc->dev;
44
45 rcar_du_write(rcdu, rcrtc->mmio_offset + reg, data);
46}
47
48static void rcar_du_crtc_clr(struct rcar_du_crtc *rcrtc, u32 reg, u32 clr)
49{
50 struct rcar_du_device *rcdu = rcrtc->dev;
51
52 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
53 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) & ~clr);
54}
55
56static void rcar_du_crtc_set(struct rcar_du_crtc *rcrtc, u32 reg, u32 set)
57{
58 struct rcar_du_device *rcdu = rcrtc->dev;
59
60 rcar_du_write(rcdu, rcrtc->mmio_offset + reg,
61 rcar_du_read(rcdu, rcrtc->mmio_offset + reg) | set);
62}
63
64void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set)
65{
66 struct rcar_du_device *rcdu = rcrtc->dev;
67
68 rcrtc->dsysr = (rcrtc->dsysr & ~clr) | set;
69 rcar_du_write(rcdu, rcrtc->mmio_offset + DSYSR, rcrtc->dsysr);
70}
71
72/* -----------------------------------------------------------------------------
73 * Hardware Setup
74 */
75
76struct dpll_info {
77 unsigned int output;
78 unsigned int fdpll;
79 unsigned int n;
80 unsigned int m;
81};
82
83static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
84 struct dpll_info *dpll,
85 unsigned long input,
86 unsigned long target)
87{
88 unsigned long best_diff = (unsigned long)-1;
89 unsigned long diff;
90 unsigned int fdpll;
91 unsigned int m;
92 unsigned int n;
93
94 /*
95 * fin fvco fout fclkout
96 * in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
97 * +-> | | |
98 * | |
99 * +---------------- [1/N] <------------+
100 *
101 * fclkout = fvco / P / FDPLL -- (1)
102 *
103 * fin/M = fvco/P/N
104 *
105 * fvco = fin * P * N / M -- (2)
106 *
107 * (1) + (2) indicates
108 *
109 * fclkout = fin * N / M / FDPLL
110 *
111 * NOTES
112 * N : (n + 1)
113 * M : (m + 1)
114 * FDPLL : (fdpll + 1)
115 * P : 2
116 * 2kHz < fvco < 4096MHz
117 *
118 * To minimize the jitter,
119 * N : as large as possible
120 * M : as small as possible
121 */
122 for (m = 0; m < 4; m++) {
123 for (n = 119; n > 38; n--) {
124 /*
125 * This code only runs on 64-bit architectures, the
126 * unsigned long type can thus be used for 64-bit
127 * computation. It will still compile without any
128 * warning on 32-bit architectures.
129 *
130 * To optimize calculations, use fout instead of fvco
131 * to verify the VCO frequency constraint.
132 */
133 unsigned long fout = input * (n + 1) / (m + 1);
134
135 if (fout < 1000 || fout > 2048 * 1000 * 1000U)
136 continue;
137
138 for (fdpll = 1; fdpll < 32; fdpll++) {
139 unsigned long output;
140
141 output = fout / (fdpll + 1);
142 if (output >= 400 * 1000 * 1000)
143 continue;
144
145 diff = abs((long)output - (long)target);
146 if (best_diff > diff) {
147 best_diff = diff;
148 dpll->n = n;
149 dpll->m = m;
150 dpll->fdpll = fdpll;
151 dpll->output = output;
152 }
153
154 if (diff == 0)
155 goto done;
156 }
157 }
158 }
159
160done:
161 dev_dbg(rcrtc->dev->dev,
162 "output:%u, fdpll:%u, n:%u, m:%u, diff:%lu\n",
163 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff);
164}
165
166struct du_clk_params {
167 struct clk *clk;
168 unsigned long rate;
169 unsigned long diff;
170 u32 escr;
171};
172
173static void rcar_du_escr_divider(struct clk *clk, unsigned long target,
174 u32 escr, struct du_clk_params *params)
175{
176 unsigned long rate;
177 unsigned long diff;
178 u32 div;
179
180 /*
181 * If the target rate has already been achieved perfectly we can't do
182 * better.
183 */
184 if (params->diff == 0)
185 return;
186
187 /*
188 * Compute the input clock rate and internal divisor values to obtain
189 * the clock rate closest to the target frequency.
190 */
191 rate = clk_round_rate(clk, target);
192 div = clamp(DIV_ROUND_CLOSEST(rate, target), 1UL, 64UL) - 1;
193 diff = abs(rate / (div + 1) - target);
194
195 /*
196 * Store the parameters if the resulting frequency is better than any
197 * previously calculated value.
198 */
199 if (diff < params->diff) {
200 params->clk = clk;
201 params->rate = rate;
202 params->diff = diff;
203 params->escr = escr | div;
204 }
205}
206
207static const struct soc_device_attribute rcar_du_r8a7795_es1[] = {
208 { .soc_id = "r8a7795", .revision = "ES1.*" },
209 { /* sentinel */ }
210};
211
212static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
213{
214 const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
215 struct rcar_du_device *rcdu = rcrtc->dev;
216 unsigned long mode_clock = mode->clock * 1000;
217 unsigned int hdse_offset;
218 u32 dsmr;
219 u32 escr;
220
221 if (rcdu->info->dpll_mask & (1 << rcrtc->index)) {
222 unsigned long target = mode_clock;
223 struct dpll_info dpll = { 0 };
224 unsigned long extclk;
225 u32 dpllcr;
226 u32 div = 0;
227
228 /*
229 * DU channels that have a display PLL can't use the internal
230 * system clock, and have no internal clock divider.
231 */
232
233 /*
234 * The H3 ES1.x exhibits dot clock duty cycle stability issues.
235 * We can work around them by configuring the DPLL to twice the
236 * desired frequency, coupled with a /2 post-divider. Restrict
237 * the workaround to H3 ES1.x as ES2.0 and all other SoCs have
238 * no post-divider when a display PLL is present (as shown by
239 * the workaround breaking HDMI output on M3-W during testing).
240 */
241 if (soc_device_match(rcar_du_r8a7795_es1)) {
242 target *= 2;
243 div = 1;
244 }
245
246 extclk = clk_get_rate(rcrtc->extclock);
247 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target);
248
249 dpllcr = DPLLCR_CODE | DPLLCR_CLKE
250 | DPLLCR_FDPLL(dpll.fdpll)
251 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m)
252 | DPLLCR_STBY;
253
254 if (rcrtc->index == 1)
255 dpllcr |= DPLLCR_PLCS1
256 | DPLLCR_INCS_DOTCLKIN1;
257 else
258 dpllcr |= DPLLCR_PLCS0
259 | DPLLCR_INCS_DOTCLKIN0;
260
261 rcar_du_group_write(rcrtc->group, DPLLCR, dpllcr);
262
263 escr = ESCR_DCLKSEL_DCLKIN | div;
264 } else if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) ||
265 rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) {
266 /*
267 * Use the external LVDS or DSI PLL output as the dot clock when
268 * outputting to the LVDS or DSI encoder on an SoC that supports
269 * this clock routing option. We use the clock directly in that
270 * case, without any additional divider.
271 */
272 escr = ESCR_DCLKSEL_DCLKIN;
273 } else {
274 struct du_clk_params params = { .diff = (unsigned long)-1 };
275
276 rcar_du_escr_divider(rcrtc->clock, mode_clock,
277 ESCR_DCLKSEL_CLKS, ¶ms);
278 if (rcrtc->extclock)
279 rcar_du_escr_divider(rcrtc->extclock, mode_clock,
280 ESCR_DCLKSEL_DCLKIN, ¶ms);
281
282 dev_dbg(rcrtc->dev->dev, "mode clock %lu %s rate %lu\n",
283 mode_clock, params.clk == rcrtc->clock ? "cpg" : "ext",
284 params.rate);
285
286 clk_set_rate(params.clk, params.rate);
287 escr = params.escr;
288 }
289
290 dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
291
292 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
293 rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
294
295 /* Signal polarities */
296 dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)
297 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DSMR_HSL : 0)
298 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? DSMR_ODEV : 0)
299 | DSMR_DIPM_DISP | DSMR_CSPM;
300 rcar_du_crtc_write(rcrtc, DSMR, dsmr);
301
302 /*
303 * When the CMM is enabled, an additional offset of 25 pixels must be
304 * subtracted from the HDS (horizontal display start) and HDE
305 * (horizontal display end) registers.
306 */
307 hdse_offset = 19;
308 if (rcrtc->group->cmms_mask & BIT(rcrtc->index % 2))
309 hdse_offset += 25;
310
311 /* Display timings */
312 rcar_du_crtc_write(rcrtc, HDSR, mode->htotal - mode->hsync_start -
313 hdse_offset);
314 rcar_du_crtc_write(rcrtc, HDER, mode->htotal - mode->hsync_start +
315 mode->hdisplay - hdse_offset);
316 rcar_du_crtc_write(rcrtc, HSWR, mode->hsync_end -
317 mode->hsync_start - 1);
318 rcar_du_crtc_write(rcrtc, HCR, mode->htotal - 1);
319
320 rcar_du_crtc_write(rcrtc, VDSR, mode->crtc_vtotal -
321 mode->crtc_vsync_end - 2);
322 rcar_du_crtc_write(rcrtc, VDER, mode->crtc_vtotal -
323 mode->crtc_vsync_end +
324 mode->crtc_vdisplay - 2);
325 rcar_du_crtc_write(rcrtc, VSPR, mode->crtc_vtotal -
326 mode->crtc_vsync_end +
327 mode->crtc_vsync_start - 1);
328 rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1);
329
330 rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1);
331 rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay);
332}
333
334static unsigned int plane_zpos(struct rcar_du_plane *plane)
335{
336 return plane->plane.state->normalized_zpos;
337}
338
339static const struct rcar_du_format_info *
340plane_format(struct rcar_du_plane *plane)
341{
342 return to_rcar_plane_state(plane->plane.state)->format;
343}
344
345static void rcar_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
346{
347 struct rcar_du_plane *planes[RCAR_DU_NUM_HW_PLANES];
348 struct rcar_du_device *rcdu = rcrtc->dev;
349 unsigned int num_planes = 0;
350 unsigned int dptsr_planes;
351 unsigned int hwplanes = 0;
352 unsigned int prio = 0;
353 unsigned int i;
354 u32 dspr = 0;
355
356 for (i = 0; i < rcrtc->group->num_planes; ++i) {
357 struct rcar_du_plane *plane = &rcrtc->group->planes[i];
358 unsigned int j;
359
360 if (plane->plane.state->crtc != &rcrtc->crtc ||
361 !plane->plane.state->visible)
362 continue;
363
364 /* Insert the plane in the sorted planes array. */
365 for (j = num_planes++; j > 0; --j) {
366 if (plane_zpos(planes[j-1]) <= plane_zpos(plane))
367 break;
368 planes[j] = planes[j-1];
369 }
370
371 planes[j] = plane;
372 prio += plane_format(plane)->planes * 4;
373 }
374
375 for (i = 0; i < num_planes; ++i) {
376 struct rcar_du_plane *plane = planes[i];
377 struct drm_plane_state *state = plane->plane.state;
378 unsigned int index = to_rcar_plane_state(state)->hwindex;
379
380 prio -= 4;
381 dspr |= (index + 1) << prio;
382 hwplanes |= 1 << index;
383
384 if (plane_format(plane)->planes == 2) {
385 index = (index + 1) % 8;
386
387 prio -= 4;
388 dspr |= (index + 1) << prio;
389 hwplanes |= 1 << index;
390 }
391 }
392
393 /* If VSP+DU integration is enabled the plane assignment is fixed. */
394 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
395 if (rcdu->info->gen < 3) {
396 dspr = (rcrtc->index % 2) + 1;
397 hwplanes = 1 << (rcrtc->index % 2);
398 } else {
399 dspr = (rcrtc->index % 2) ? 3 : 1;
400 hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
401 }
402 }
403
404 /*
405 * Update the planes to display timing and dot clock generator
406 * associations.
407 *
408 * Updating the DPTSR register requires restarting the CRTC group,
409 * resulting in visible flicker. To mitigate the issue only update the
410 * association if needed by enabled planes. Planes being disabled will
411 * keep their current association.
412 */
413 mutex_lock(&rcrtc->group->lock);
414
415 dptsr_planes = rcrtc->index % 2 ? rcrtc->group->dptsr_planes | hwplanes
416 : rcrtc->group->dptsr_planes & ~hwplanes;
417
418 if (dptsr_planes != rcrtc->group->dptsr_planes) {
419 rcar_du_group_write(rcrtc->group, DPTSR,
420 (dptsr_planes << 16) | dptsr_planes);
421 rcrtc->group->dptsr_planes = dptsr_planes;
422
423 if (rcrtc->group->used_crtcs)
424 rcar_du_group_restart(rcrtc->group);
425 }
426
427 /* Restart the group if plane sources have changed. */
428 if (rcrtc->group->need_restart)
429 rcar_du_group_restart(rcrtc->group);
430
431 mutex_unlock(&rcrtc->group->lock);
432
433 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR,
434 dspr);
435}
436
437/* -----------------------------------------------------------------------------
438 * Page Flip
439 */
440
441void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
442{
443 struct drm_pending_vblank_event *event;
444 struct drm_device *dev = rcrtc->crtc.dev;
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev->event_lock, flags);
448 event = rcrtc->event;
449 rcrtc->event = NULL;
450 spin_unlock_irqrestore(&dev->event_lock, flags);
451
452 if (event == NULL)
453 return;
454
455 spin_lock_irqsave(&dev->event_lock, flags);
456 drm_crtc_send_vblank_event(&rcrtc->crtc, event);
457 wake_up(&rcrtc->flip_wait);
458 spin_unlock_irqrestore(&dev->event_lock, flags);
459
460 drm_crtc_vblank_put(&rcrtc->crtc);
461}
462
463static bool rcar_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
464{
465 struct drm_device *dev = rcrtc->crtc.dev;
466 unsigned long flags;
467 bool pending;
468
469 spin_lock_irqsave(&dev->event_lock, flags);
470 pending = rcrtc->event != NULL;
471 spin_unlock_irqrestore(&dev->event_lock, flags);
472
473 return pending;
474}
475
476static void rcar_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
477{
478 struct rcar_du_device *rcdu = rcrtc->dev;
479
480 if (wait_event_timeout(rcrtc->flip_wait,
481 !rcar_du_crtc_page_flip_pending(rcrtc),
482 msecs_to_jiffies(50)))
483 return;
484
485 dev_warn(rcdu->dev, "page flip timeout\n");
486
487 rcar_du_crtc_finish_page_flip(rcrtc);
488}
489
490/* -----------------------------------------------------------------------------
491 * Color Management Module (CMM)
492 */
493
494static int rcar_du_cmm_check(struct drm_crtc *crtc,
495 struct drm_crtc_state *state)
496{
497 struct drm_property_blob *drm_lut = state->gamma_lut;
498 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
499 struct device *dev = rcrtc->dev->dev;
500
501 if (!drm_lut)
502 return 0;
503
504 /* We only accept fully populated LUT tables. */
505 if (drm_color_lut_size(drm_lut) != CM2_LUT_SIZE) {
506 dev_err(dev, "invalid gamma lut size: %zu bytes\n",
507 drm_lut->length);
508 return -EINVAL;
509 }
510
511 return 0;
512}
513
514static void rcar_du_cmm_setup(struct drm_crtc *crtc)
515{
516 struct drm_property_blob *drm_lut = crtc->state->gamma_lut;
517 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
518 struct rcar_cmm_config cmm_config = {};
519
520 if (!rcrtc->cmm)
521 return;
522
523 if (drm_lut)
524 cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data;
525
526 rcar_cmm_setup(rcrtc->cmm, &cmm_config);
527}
528
529/* -----------------------------------------------------------------------------
530 * Start/Stop and Suspend/Resume
531 */
532
533static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
534{
535 /* Set display off and background to black */
536 rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
537 rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
538
539 /* Configure display timings and output routing */
540 rcar_du_crtc_set_display_timing(rcrtc);
541 rcar_du_group_set_routing(rcrtc->group);
542
543 /* Start with all planes disabled. */
544 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
545
546 /* Enable the VSP compositor. */
547 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
548 rcar_du_vsp_enable(rcrtc);
549
550 /* Turn vertical blanking interrupt reporting on. */
551 drm_crtc_vblank_on(&rcrtc->crtc);
552}
553
554static int rcar_du_crtc_get(struct rcar_du_crtc *rcrtc)
555{
556 int ret;
557
558 /*
559 * Guard against double-get, as the function is called from both the
560 * .atomic_enable() and .atomic_begin() handlers.
561 */
562 if (rcrtc->initialized)
563 return 0;
564
565 ret = clk_prepare_enable(rcrtc->clock);
566 if (ret < 0)
567 return ret;
568
569 ret = clk_prepare_enable(rcrtc->extclock);
570 if (ret < 0)
571 goto error_clock;
572
573 ret = rcar_du_group_get(rcrtc->group);
574 if (ret < 0)
575 goto error_group;
576
577 rcar_du_crtc_setup(rcrtc);
578 rcrtc->initialized = true;
579
580 return 0;
581
582error_group:
583 clk_disable_unprepare(rcrtc->extclock);
584error_clock:
585 clk_disable_unprepare(rcrtc->clock);
586 return ret;
587}
588
589static void rcar_du_crtc_put(struct rcar_du_crtc *rcrtc)
590{
591 rcar_du_group_put(rcrtc->group);
592
593 clk_disable_unprepare(rcrtc->extclock);
594 clk_disable_unprepare(rcrtc->clock);
595
596 rcrtc->initialized = false;
597}
598
599static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
600{
601 bool interlaced;
602
603 /*
604 * Select master sync mode. This enables display operation in master
605 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
606 * actively driven).
607 */
608 interlaced = rcrtc->crtc.mode.flags & DRM_MODE_FLAG_INTERLACE;
609 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK | DSYSR_SCM_MASK,
610 (interlaced ? DSYSR_SCM_INT_VIDEO : 0) |
611 DSYSR_TVM_MASTER);
612
613 rcar_du_group_start_stop(rcrtc->group, true);
614}
615
616static void rcar_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
617{
618 struct rcar_du_device *rcdu = rcrtc->dev;
619 struct drm_crtc *crtc = &rcrtc->crtc;
620 u32 status;
621
622 /* Make sure vblank interrupts are enabled. */
623 drm_crtc_vblank_get(crtc);
624
625 /*
626 * Disable planes and calculate how many vertical blanking interrupts we
627 * have to wait for. If a vertical blanking interrupt has been triggered
628 * but not processed yet, we don't know whether it occurred before or
629 * after the planes got disabled. We thus have to wait for two vblank
630 * interrupts in that case.
631 */
632 spin_lock_irq(&rcrtc->vblank_lock);
633 rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
634 status = rcar_du_crtc_read(rcrtc, DSSR);
635 rcrtc->vblank_count = status & DSSR_VBK ? 2 : 1;
636 spin_unlock_irq(&rcrtc->vblank_lock);
637
638 if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
639 msecs_to_jiffies(100)))
640 dev_warn(rcdu->dev, "vertical blanking timeout\n");
641
642 drm_crtc_vblank_put(crtc);
643}
644
645static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
646{
647 struct drm_crtc *crtc = &rcrtc->crtc;
648
649 /*
650 * Disable all planes and wait for the change to take effect. This is
651 * required as the plane enable registers are updated on vblank, and no
652 * vblank will occur once the CRTC is stopped. Disabling planes when
653 * starting the CRTC thus wouldn't be enough as it would start scanning
654 * out immediately from old frame buffers until the next vblank.
655 *
656 * This increases the CRTC stop delay, especially when multiple CRTCs
657 * are stopped in one operation as we now wait for one vblank per CRTC.
658 * Whether this can be improved needs to be researched.
659 */
660 rcar_du_crtc_disable_planes(rcrtc);
661
662 /*
663 * Disable vertical blanking interrupt reporting. We first need to wait
664 * for page flip completion before stopping the CRTC as userspace
665 * expects page flips to eventually complete.
666 */
667 rcar_du_crtc_wait_page_flip(rcrtc);
668 drm_crtc_vblank_off(crtc);
669
670 /* Disable the VSP compositor. */
671 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
672 rcar_du_vsp_disable(rcrtc);
673
674 if (rcrtc->cmm)
675 rcar_cmm_disable(rcrtc->cmm);
676
677 /*
678 * Select switch sync mode. This stops display operation and configures
679 * the HSYNC and VSYNC signals as inputs.
680 *
681 * TODO: Find another way to stop the display for DUs that don't support
682 * TVM sync.
683 */
684 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_TVM_SYNC))
685 rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_TVM_MASK,
686 DSYSR_TVM_SWITCH);
687
688 rcar_du_group_start_stop(rcrtc->group, false);
689}
690
691/* -----------------------------------------------------------------------------
692 * CRTC Functions
693 */
694
695static int rcar_du_crtc_atomic_check(struct drm_crtc *crtc,
696 struct drm_atomic_state *state)
697{
698 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
699 crtc);
700 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc_state);
701 struct drm_encoder *encoder;
702 int ret;
703
704 ret = rcar_du_cmm_check(crtc, crtc_state);
705 if (ret)
706 return ret;
707
708 /* Store the routes from the CRTC output to the DU outputs. */
709 rstate->outputs = 0;
710
711 drm_for_each_encoder_mask(encoder, crtc->dev,
712 crtc_state->encoder_mask) {
713 struct rcar_du_encoder *renc;
714
715 /* Skip the writeback encoder. */
716 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
717 continue;
718
719 renc = to_rcar_encoder(encoder);
720 rstate->outputs |= BIT(renc->output);
721 }
722
723 return 0;
724}
725
726static void rcar_du_crtc_atomic_enable(struct drm_crtc *crtc,
727 struct drm_atomic_state *state)
728{
729 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
730 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc->state);
731 struct rcar_du_device *rcdu = rcrtc->dev;
732
733 if (rcrtc->cmm)
734 rcar_cmm_enable(rcrtc->cmm);
735 rcar_du_crtc_get(rcrtc);
736
737 /*
738 * On D3/E3 the dot clock is provided by the LVDS encoder attached to
739 * the DU channel. We need to enable its clock output explicitly if
740 * the LVDS output is disabled.
741 */
742 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
743 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
744 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
745 const struct drm_display_mode *mode =
746 &crtc->state->adjusted_mode;
747
748 rcar_lvds_pclk_enable(bridge, mode->clock * 1000);
749 }
750
751 /*
752 * Similarly to LVDS, on V3U the dot clock is provided by the DSI
753 * encoder, and we need to enable the DSI clocks before enabling the CRTC.
754 */
755 if ((rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) &&
756 (rstate->outputs &
757 (BIT(RCAR_DU_OUTPUT_DSI0) | BIT(RCAR_DU_OUTPUT_DSI1)))) {
758 struct drm_bridge *bridge = rcdu->dsi[rcrtc->index];
759
760 rcar_mipi_dsi_pclk_enable(bridge, state);
761 }
762
763 rcar_du_crtc_start(rcrtc);
764
765 /*
766 * TODO: The chip manual indicates that CMM tables should be written
767 * after the DU channel has been activated. Investigate the impact
768 * of this restriction on the first displayed frame.
769 */
770 rcar_du_cmm_setup(crtc);
771}
772
773static void rcar_du_crtc_atomic_disable(struct drm_crtc *crtc,
774 struct drm_atomic_state *state)
775{
776 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
777 crtc);
778 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
779 struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(old_state);
780 struct rcar_du_device *rcdu = rcrtc->dev;
781
782 rcar_du_crtc_stop(rcrtc);
783 rcar_du_crtc_put(rcrtc);
784
785 if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index) &&
786 rstate->outputs == BIT(RCAR_DU_OUTPUT_DPAD0)) {
787 struct drm_bridge *bridge = rcdu->lvds[rcrtc->index];
788
789 /*
790 * Disable the LVDS clock output, see
791 * rcar_du_crtc_atomic_enable().
792 */
793 rcar_lvds_pclk_disable(bridge);
794 }
795
796 if ((rcdu->info->dsi_clk_mask & BIT(rcrtc->index)) &&
797 (rstate->outputs &
798 (BIT(RCAR_DU_OUTPUT_DSI0) | BIT(RCAR_DU_OUTPUT_DSI1)))) {
799 struct drm_bridge *bridge = rcdu->dsi[rcrtc->index];
800
801 /*
802 * Disable the DSI clock output, see
803 * rcar_du_crtc_atomic_enable().
804 */
805
806 rcar_mipi_dsi_pclk_disable(bridge);
807 }
808
809 spin_lock_irq(&crtc->dev->event_lock);
810 if (crtc->state->event) {
811 drm_crtc_send_vblank_event(crtc, crtc->state->event);
812 crtc->state->event = NULL;
813 }
814 spin_unlock_irq(&crtc->dev->event_lock);
815}
816
817static void rcar_du_crtc_atomic_begin(struct drm_crtc *crtc,
818 struct drm_atomic_state *state)
819{
820 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
821
822 WARN_ON(!crtc->state->enable);
823
824 /*
825 * If a mode set is in progress we can be called with the CRTC disabled.
826 * We thus need to first get and setup the CRTC in order to configure
827 * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
828 * kept awake until the .atomic_enable() call that will follow. The get
829 * operation in .atomic_enable() will in that case be a no-op, and the
830 * CRTC will be put later in .atomic_disable().
831 *
832 * If a mode set is not in progress the CRTC is enabled, and the
833 * following get call will be a no-op. There is thus no need to balance
834 * it in .atomic_flush() either.
835 */
836 rcar_du_crtc_get(rcrtc);
837
838 /* If the active state changed, we let .atomic_enable handle CMM. */
839 if (crtc->state->color_mgmt_changed && !crtc->state->active_changed)
840 rcar_du_cmm_setup(crtc);
841
842 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
843 rcar_du_vsp_atomic_begin(rcrtc);
844}
845
846static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
847 struct drm_atomic_state *state)
848{
849 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
850 struct drm_device *dev = rcrtc->crtc.dev;
851 unsigned long flags;
852
853 rcar_du_crtc_update_planes(rcrtc);
854
855 if (crtc->state->event) {
856 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
857
858 spin_lock_irqsave(&dev->event_lock, flags);
859 rcrtc->event = crtc->state->event;
860 crtc->state->event = NULL;
861 spin_unlock_irqrestore(&dev->event_lock, flags);
862 }
863
864 if (rcar_du_has(rcrtc->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
865 rcar_du_vsp_atomic_flush(rcrtc);
866}
867
868static enum drm_mode_status
869rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
870 const struct drm_display_mode *mode)
871{
872 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
873 struct rcar_du_device *rcdu = rcrtc->dev;
874 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
875 unsigned int min_sync_porch;
876 unsigned int vbp;
877
878 if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
879 return MODE_NO_INTERLACE;
880
881 /*
882 * The hardware requires a minimum combined horizontal sync and back
883 * porch of 20 pixels (when CMM isn't used) or 45 pixels (when CMM is
884 * used), and a minimum vertical back porch of 3 lines.
885 */
886 min_sync_porch = 20;
887 if (rcrtc->group->cmms_mask & BIT(rcrtc->index % 2))
888 min_sync_porch += 25;
889
890 if (mode->htotal - mode->hsync_start < min_sync_porch)
891 return MODE_HBLANK_NARROW;
892
893 vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
894 if (vbp < 3)
895 return MODE_VBLANK_NARROW;
896
897 return MODE_OK;
898}
899
900static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
901 .atomic_check = rcar_du_crtc_atomic_check,
902 .atomic_begin = rcar_du_crtc_atomic_begin,
903 .atomic_flush = rcar_du_crtc_atomic_flush,
904 .atomic_enable = rcar_du_crtc_atomic_enable,
905 .atomic_disable = rcar_du_crtc_atomic_disable,
906 .mode_valid = rcar_du_crtc_mode_valid,
907};
908
909static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
910{
911 struct rcar_du_device *rcdu = rcrtc->dev;
912 const char **sources;
913 unsigned int count;
914 int i = -1;
915
916 /* CRC available only on Gen3 HW. */
917 if (rcdu->info->gen < 3)
918 return;
919
920 /* Reserve 1 for "auto" source. */
921 count = rcrtc->vsp->num_planes + 1;
922
923 sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
924 if (!sources)
925 return;
926
927 sources[0] = kstrdup("auto", GFP_KERNEL);
928 if (!sources[0])
929 goto error;
930
931 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
932 struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
933 char name[16];
934
935 sprintf(name, "plane%u", plane->base.id);
936 sources[i + 1] = kstrdup(name, GFP_KERNEL);
937 if (!sources[i + 1])
938 goto error;
939 }
940
941 rcrtc->sources = sources;
942 rcrtc->sources_count = count;
943 return;
944
945error:
946 while (i >= 0) {
947 kfree(sources[i]);
948 i--;
949 }
950 kfree(sources);
951}
952
953static void rcar_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
954{
955 unsigned int i;
956
957 if (!rcrtc->sources)
958 return;
959
960 for (i = 0; i < rcrtc->sources_count; i++)
961 kfree(rcrtc->sources[i]);
962 kfree(rcrtc->sources);
963
964 rcrtc->sources = NULL;
965 rcrtc->sources_count = 0;
966}
967
968static struct drm_crtc_state *
969rcar_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
970{
971 struct rcar_du_crtc_state *state;
972 struct rcar_du_crtc_state *copy;
973
974 if (WARN_ON(!crtc->state))
975 return NULL;
976
977 state = to_rcar_crtc_state(crtc->state);
978 copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
979 if (copy == NULL)
980 return NULL;
981
982 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->state);
983
984 return ©->state;
985}
986
987static void rcar_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
988 struct drm_crtc_state *state)
989{
990 __drm_atomic_helper_crtc_destroy_state(state);
991 kfree(to_rcar_crtc_state(state));
992}
993
994static void rcar_du_crtc_cleanup(struct drm_crtc *crtc)
995{
996 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
997
998 rcar_du_crtc_crc_cleanup(rcrtc);
999
1000 return drm_crtc_cleanup(crtc);
1001}
1002
1003static void rcar_du_crtc_reset(struct drm_crtc *crtc)
1004{
1005 struct rcar_du_crtc_state *state;
1006
1007 if (crtc->state) {
1008 rcar_du_crtc_atomic_destroy_state(crtc, crtc->state);
1009 crtc->state = NULL;
1010 }
1011
1012 state = kzalloc(sizeof(*state), GFP_KERNEL);
1013 if (state == NULL)
1014 return;
1015
1016 state->crc.source = VSP1_DU_CRC_NONE;
1017 state->crc.index = 0;
1018
1019 __drm_atomic_helper_crtc_reset(crtc, &state->state);
1020}
1021
1022static int rcar_du_crtc_enable_vblank(struct drm_crtc *crtc)
1023{
1024 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1025
1026 rcar_du_crtc_write(rcrtc, DSRCR, DSRCR_VBCL);
1027 rcar_du_crtc_set(rcrtc, DIER, DIER_VBE);
1028 rcrtc->vblank_enable = true;
1029
1030 return 0;
1031}
1032
1033static void rcar_du_crtc_disable_vblank(struct drm_crtc *crtc)
1034{
1035 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1036
1037 rcar_du_crtc_clr(rcrtc, DIER, DIER_VBE);
1038 rcrtc->vblank_enable = false;
1039}
1040
1041static int rcar_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
1042 const char *source_name,
1043 enum vsp1_du_crc_source *source)
1044{
1045 unsigned int index;
1046 int ret;
1047
1048 /*
1049 * Parse the source name. Supported values are "plane%u" to compute the
1050 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
1051 * CRC on the composer (VSP) output.
1052 */
1053
1054 if (!source_name) {
1055 *source = VSP1_DU_CRC_NONE;
1056 return 0;
1057 } else if (!strcmp(source_name, "auto")) {
1058 *source = VSP1_DU_CRC_OUTPUT;
1059 return 0;
1060 } else if (strstarts(source_name, "plane")) {
1061 unsigned int i;
1062
1063 *source = VSP1_DU_CRC_PLANE;
1064
1065 ret = kstrtouint(source_name + strlen("plane"), 10, &index);
1066 if (ret < 0)
1067 return ret;
1068
1069 for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
1070 if (index == rcrtc->vsp->planes[i].plane.base.id)
1071 return i;
1072 }
1073 }
1074
1075 return -EINVAL;
1076}
1077
1078static int rcar_du_crtc_verify_crc_source(struct drm_crtc *crtc,
1079 const char *source_name,
1080 size_t *values_cnt)
1081{
1082 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1083 enum vsp1_du_crc_source source;
1084
1085 if (rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
1086 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
1087 return -EINVAL;
1088 }
1089
1090 *values_cnt = 1;
1091 return 0;
1092}
1093
1094static const char *const *
1095rcar_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
1096{
1097 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1098
1099 *count = rcrtc->sources_count;
1100 return rcrtc->sources;
1101}
1102
1103static int rcar_du_crtc_set_crc_source(struct drm_crtc *crtc,
1104 const char *source_name)
1105{
1106 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
1107 struct drm_modeset_acquire_ctx ctx;
1108 struct drm_crtc_state *crtc_state;
1109 struct drm_atomic_state *state;
1110 enum vsp1_du_crc_source source;
1111 unsigned int index;
1112 int ret;
1113
1114 ret = rcar_du_crtc_parse_crc_source(rcrtc, source_name, &source);
1115 if (ret < 0)
1116 return ret;
1117
1118 index = ret;
1119
1120 /* Perform an atomic commit to set the CRC source. */
1121 drm_modeset_acquire_init(&ctx, 0);
1122
1123 state = drm_atomic_state_alloc(crtc->dev);
1124 if (!state) {
1125 ret = -ENOMEM;
1126 goto unlock;
1127 }
1128
1129 state->acquire_ctx = &ctx;
1130
1131retry:
1132 crtc_state = drm_atomic_get_crtc_state(state, crtc);
1133 if (!IS_ERR(crtc_state)) {
1134 struct rcar_du_crtc_state *rcrtc_state;
1135
1136 rcrtc_state = to_rcar_crtc_state(crtc_state);
1137 rcrtc_state->crc.source = source;
1138 rcrtc_state->crc.index = index;
1139
1140 ret = drm_atomic_commit(state);
1141 } else {
1142 ret = PTR_ERR(crtc_state);
1143 }
1144
1145 if (ret == -EDEADLK) {
1146 drm_atomic_state_clear(state);
1147 drm_modeset_backoff(&ctx);
1148 goto retry;
1149 }
1150
1151 drm_atomic_state_put(state);
1152
1153unlock:
1154 drm_modeset_drop_locks(&ctx);
1155 drm_modeset_acquire_fini(&ctx);
1156
1157 return ret;
1158}
1159
1160static const struct drm_crtc_funcs crtc_funcs_gen2 = {
1161 .reset = rcar_du_crtc_reset,
1162 .destroy = drm_crtc_cleanup,
1163 .set_config = drm_atomic_helper_set_config,
1164 .page_flip = drm_atomic_helper_page_flip,
1165 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1166 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1167 .enable_vblank = rcar_du_crtc_enable_vblank,
1168 .disable_vblank = rcar_du_crtc_disable_vblank,
1169};
1170
1171static const struct drm_crtc_funcs crtc_funcs_gen3 = {
1172 .reset = rcar_du_crtc_reset,
1173 .destroy = rcar_du_crtc_cleanup,
1174 .set_config = drm_atomic_helper_set_config,
1175 .page_flip = drm_atomic_helper_page_flip,
1176 .atomic_duplicate_state = rcar_du_crtc_atomic_duplicate_state,
1177 .atomic_destroy_state = rcar_du_crtc_atomic_destroy_state,
1178 .enable_vblank = rcar_du_crtc_enable_vblank,
1179 .disable_vblank = rcar_du_crtc_disable_vblank,
1180 .set_crc_source = rcar_du_crtc_set_crc_source,
1181 .verify_crc_source = rcar_du_crtc_verify_crc_source,
1182 .get_crc_sources = rcar_du_crtc_get_crc_sources,
1183};
1184
1185/* -----------------------------------------------------------------------------
1186 * Interrupt Handling
1187 */
1188
1189static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
1190{
1191 struct rcar_du_crtc *rcrtc = arg;
1192 struct rcar_du_device *rcdu = rcrtc->dev;
1193 irqreturn_t ret = IRQ_NONE;
1194 u32 status;
1195
1196 spin_lock(&rcrtc->vblank_lock);
1197
1198 status = rcar_du_crtc_read(rcrtc, DSSR);
1199 rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
1200
1201 if (status & DSSR_VBK) {
1202 /*
1203 * Wake up the vblank wait if the counter reaches 0. This must
1204 * be protected by the vblank_lock to avoid races in
1205 * rcar_du_crtc_disable_planes().
1206 */
1207 if (rcrtc->vblank_count) {
1208 if (--rcrtc->vblank_count == 0)
1209 wake_up(&rcrtc->vblank_wait);
1210 }
1211 }
1212
1213 spin_unlock(&rcrtc->vblank_lock);
1214
1215 if (status & DSSR_VBK) {
1216 if (rcdu->info->gen < 3) {
1217 drm_crtc_handle_vblank(&rcrtc->crtc);
1218 rcar_du_crtc_finish_page_flip(rcrtc);
1219 }
1220
1221 ret = IRQ_HANDLED;
1222 }
1223
1224 return ret;
1225}
1226
1227/* -----------------------------------------------------------------------------
1228 * Initialization
1229 */
1230
1231int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
1232 unsigned int hwindex)
1233{
1234 static const unsigned int mmio_offsets[] = {
1235 DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
1236 };
1237
1238 struct rcar_du_device *rcdu = rgrp->dev;
1239 struct platform_device *pdev = to_platform_device(rcdu->dev);
1240 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
1241 struct drm_crtc *crtc = &rcrtc->crtc;
1242 struct drm_plane *primary;
1243 unsigned int irqflags;
1244 struct clk *clk;
1245 char clk_name[9];
1246 char *name;
1247 int irq;
1248 int ret;
1249
1250 /* Get the CRTC clock and the optional external clock. */
1251 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_CLOCK)) {
1252 sprintf(clk_name, "du.%u", hwindex);
1253 name = clk_name;
1254 } else {
1255 name = NULL;
1256 }
1257
1258 rcrtc->clock = devm_clk_get(rcdu->dev, name);
1259 if (IS_ERR(rcrtc->clock)) {
1260 dev_err(rcdu->dev, "no clock for DU channel %u\n", hwindex);
1261 return PTR_ERR(rcrtc->clock);
1262 }
1263
1264 sprintf(clk_name, "dclkin.%u", hwindex);
1265 clk = devm_clk_get(rcdu->dev, clk_name);
1266 if (!IS_ERR(clk)) {
1267 rcrtc->extclock = clk;
1268 } else if (PTR_ERR(clk) == -EPROBE_DEFER) {
1269 return -EPROBE_DEFER;
1270 } else if (rcdu->info->dpll_mask & BIT(hwindex)) {
1271 /*
1272 * DU channels that have a display PLL can't use the internal
1273 * system clock and thus require an external clock.
1274 */
1275 ret = PTR_ERR(clk);
1276 dev_err(rcdu->dev, "can't get dclkin.%u: %d\n", hwindex, ret);
1277 return ret;
1278 }
1279
1280 init_waitqueue_head(&rcrtc->flip_wait);
1281 init_waitqueue_head(&rcrtc->vblank_wait);
1282 spin_lock_init(&rcrtc->vblank_lock);
1283
1284 rcrtc->dev = rcdu;
1285 rcrtc->group = rgrp;
1286 rcrtc->mmio_offset = mmio_offsets[hwindex];
1287 rcrtc->index = hwindex;
1288 rcrtc->dsysr = rcrtc->index % 2 ? 0 : DSYSR_DRES;
1289
1290 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_TVM_SYNC))
1291 rcrtc->dsysr |= DSYSR_TVM_TVSYNC;
1292
1293 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
1294 primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
1295 else
1296 primary = &rgrp->planes[swindex % 2].plane;
1297
1298 ret = drm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
1299 rcdu->info->gen <= 2 ?
1300 &crtc_funcs_gen2 : &crtc_funcs_gen3,
1301 NULL);
1302 if (ret < 0)
1303 return ret;
1304
1305 /* CMM might be disabled for this CRTC. */
1306 if (rcdu->cmms[swindex]) {
1307 rcrtc->cmm = rcdu->cmms[swindex];
1308 rgrp->cmms_mask |= BIT(hwindex % 2);
1309
1310 drm_mode_crtc_set_gamma_size(crtc, CM2_LUT_SIZE);
1311 drm_crtc_enable_color_mgmt(crtc, 0, false, CM2_LUT_SIZE);
1312 }
1313
1314 drm_crtc_helper_add(crtc, &crtc_helper_funcs);
1315
1316 /* Register the interrupt handler. */
1317 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_CRTC_IRQ)) {
1318 /* The IRQ's are associated with the CRTC (sw)index. */
1319 irq = platform_get_irq(pdev, swindex);
1320 irqflags = 0;
1321 } else {
1322 irq = platform_get_irq(pdev, 0);
1323 irqflags = IRQF_SHARED;
1324 }
1325
1326 if (irq < 0) {
1327 dev_err(rcdu->dev, "no IRQ for CRTC %u\n", swindex);
1328 return irq;
1329 }
1330
1331 ret = devm_request_irq(rcdu->dev, irq, rcar_du_crtc_irq, irqflags,
1332 dev_name(rcdu->dev), rcrtc);
1333 if (ret < 0) {
1334 dev_err(rcdu->dev,
1335 "failed to register IRQ for CRTC %u\n", swindex);
1336 return ret;
1337 }
1338
1339 rcar_du_crtc_crc_init(rcrtc);
1340
1341 return 0;
1342}