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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
38#include "drmP.h"
39#include "radeon.h"
40#include "radeon_asic.h"
41#include "atom.h"
42#include "rs600d.h"
43
44#include "rs600_reg_safe.h"
45
46void rs600_gpu_init(struct radeon_device *rdev);
47int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48
49void rs600_pre_page_flip(struct radeon_device *rdev, int crtc)
50{
51 /* enable the pflip int */
52 radeon_irq_kms_pflip_irq_get(rdev, crtc);
53}
54
55void rs600_post_page_flip(struct radeon_device *rdev, int crtc)
56{
57 /* disable the pflip int */
58 radeon_irq_kms_pflip_irq_put(rdev, crtc);
59}
60
61u32 rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
62{
63 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
64 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
65
66 /* Lock the graphics update lock */
67 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
68 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
69
70 /* update the scanout addresses */
71 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
72 (u32)crtc_base);
73 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
74 (u32)crtc_base);
75
76 /* Wait for update_pending to go high. */
77 while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
78 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
79
80 /* Unlock the lock, so double-buffering can take place inside vblank */
81 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
82 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
83
84 /* Return current update_pending status: */
85 return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
86}
87
88void rs600_pm_misc(struct radeon_device *rdev)
89{
90 int requested_index = rdev->pm.requested_power_state_index;
91 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
92 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
93 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
94 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
95
96 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
97 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
98 tmp = RREG32(voltage->gpio.reg);
99 if (voltage->active_high)
100 tmp |= voltage->gpio.mask;
101 else
102 tmp &= ~(voltage->gpio.mask);
103 WREG32(voltage->gpio.reg, tmp);
104 if (voltage->delay)
105 udelay(voltage->delay);
106 } else {
107 tmp = RREG32(voltage->gpio.reg);
108 if (voltage->active_high)
109 tmp &= ~voltage->gpio.mask;
110 else
111 tmp |= voltage->gpio.mask;
112 WREG32(voltage->gpio.reg, tmp);
113 if (voltage->delay)
114 udelay(voltage->delay);
115 }
116 } else if (voltage->type == VOLTAGE_VDDC)
117 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
118
119 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
120 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
121 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
122 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
123 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
124 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
125 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
126 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
127 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
128 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
129 }
130 } else {
131 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
132 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
133 }
134 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
135
136 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
137 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
138 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
139 if (voltage->delay) {
140 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
141 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
142 } else
143 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
144 } else
145 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
146 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
147
148 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
149 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
150 hdp_dyn_cntl &= ~HDP_FORCEON;
151 else
152 hdp_dyn_cntl |= HDP_FORCEON;
153 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
154#if 0
155 /* mc_host_dyn seems to cause hangs from time to time */
156 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
157 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
158 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
159 else
160 mc_host_dyn_cntl |= MC_HOST_FORCEON;
161 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
162#endif
163 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
164 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
165 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
166 else
167 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
168 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
169
170 /* set pcie lanes */
171 if ((rdev->flags & RADEON_IS_PCIE) &&
172 !(rdev->flags & RADEON_IS_IGP) &&
173 rdev->asic->set_pcie_lanes &&
174 (ps->pcie_lanes !=
175 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
176 radeon_set_pcie_lanes(rdev,
177 ps->pcie_lanes);
178 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
179 }
180}
181
182void rs600_pm_prepare(struct radeon_device *rdev)
183{
184 struct drm_device *ddev = rdev->ddev;
185 struct drm_crtc *crtc;
186 struct radeon_crtc *radeon_crtc;
187 u32 tmp;
188
189 /* disable any active CRTCs */
190 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
191 radeon_crtc = to_radeon_crtc(crtc);
192 if (radeon_crtc->enabled) {
193 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
194 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
195 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
196 }
197 }
198}
199
200void rs600_pm_finish(struct radeon_device *rdev)
201{
202 struct drm_device *ddev = rdev->ddev;
203 struct drm_crtc *crtc;
204 struct radeon_crtc *radeon_crtc;
205 u32 tmp;
206
207 /* enable any active CRTCs */
208 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
209 radeon_crtc = to_radeon_crtc(crtc);
210 if (radeon_crtc->enabled) {
211 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
212 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
213 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
214 }
215 }
216}
217
218/* hpd for digital panel detect/disconnect */
219bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
220{
221 u32 tmp;
222 bool connected = false;
223
224 switch (hpd) {
225 case RADEON_HPD_1:
226 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
227 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
228 connected = true;
229 break;
230 case RADEON_HPD_2:
231 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
232 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
233 connected = true;
234 break;
235 default:
236 break;
237 }
238 return connected;
239}
240
241void rs600_hpd_set_polarity(struct radeon_device *rdev,
242 enum radeon_hpd_id hpd)
243{
244 u32 tmp;
245 bool connected = rs600_hpd_sense(rdev, hpd);
246
247 switch (hpd) {
248 case RADEON_HPD_1:
249 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
250 if (connected)
251 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
252 else
253 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
254 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
255 break;
256 case RADEON_HPD_2:
257 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
258 if (connected)
259 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
260 else
261 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
262 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
263 break;
264 default:
265 break;
266 }
267}
268
269void rs600_hpd_init(struct radeon_device *rdev)
270{
271 struct drm_device *dev = rdev->ddev;
272 struct drm_connector *connector;
273
274 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
275 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
276 switch (radeon_connector->hpd.hpd) {
277 case RADEON_HPD_1:
278 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
279 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
280 rdev->irq.hpd[0] = true;
281 break;
282 case RADEON_HPD_2:
283 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
284 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
285 rdev->irq.hpd[1] = true;
286 break;
287 default:
288 break;
289 }
290 }
291 if (rdev->irq.installed)
292 rs600_irq_set(rdev);
293}
294
295void rs600_hpd_fini(struct radeon_device *rdev)
296{
297 struct drm_device *dev = rdev->ddev;
298 struct drm_connector *connector;
299
300 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
301 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
302 switch (radeon_connector->hpd.hpd) {
303 case RADEON_HPD_1:
304 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
305 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
306 rdev->irq.hpd[0] = false;
307 break;
308 case RADEON_HPD_2:
309 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
310 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
311 rdev->irq.hpd[1] = false;
312 break;
313 default:
314 break;
315 }
316 }
317}
318
319void rs600_bm_disable(struct radeon_device *rdev)
320{
321 u32 tmp;
322
323 /* disable bus mastering */
324 pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
325 pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
326 mdelay(1);
327}
328
329int rs600_asic_reset(struct radeon_device *rdev)
330{
331 struct rv515_mc_save save;
332 u32 status, tmp;
333 int ret = 0;
334
335 status = RREG32(R_000E40_RBBM_STATUS);
336 if (!G_000E40_GUI_ACTIVE(status)) {
337 return 0;
338 }
339 /* Stops all mc clients */
340 rv515_mc_stop(rdev, &save);
341 status = RREG32(R_000E40_RBBM_STATUS);
342 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
343 /* stop CP */
344 WREG32(RADEON_CP_CSQ_CNTL, 0);
345 tmp = RREG32(RADEON_CP_RB_CNTL);
346 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
347 WREG32(RADEON_CP_RB_RPTR_WR, 0);
348 WREG32(RADEON_CP_RB_WPTR, 0);
349 WREG32(RADEON_CP_RB_CNTL, tmp);
350 pci_save_state(rdev->pdev);
351 /* disable bus mastering */
352 rs600_bm_disable(rdev);
353 /* reset GA+VAP */
354 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
355 S_0000F0_SOFT_RESET_GA(1));
356 RREG32(R_0000F0_RBBM_SOFT_RESET);
357 mdelay(500);
358 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
359 mdelay(1);
360 status = RREG32(R_000E40_RBBM_STATUS);
361 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
362 /* reset CP */
363 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
364 RREG32(R_0000F0_RBBM_SOFT_RESET);
365 mdelay(500);
366 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
367 mdelay(1);
368 status = RREG32(R_000E40_RBBM_STATUS);
369 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
370 /* reset MC */
371 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
372 RREG32(R_0000F0_RBBM_SOFT_RESET);
373 mdelay(500);
374 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
375 mdelay(1);
376 status = RREG32(R_000E40_RBBM_STATUS);
377 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
378 /* restore PCI & busmastering */
379 pci_restore_state(rdev->pdev);
380 /* Check if GPU is idle */
381 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
382 dev_err(rdev->dev, "failed to reset GPU\n");
383 rdev->gpu_lockup = true;
384 ret = -1;
385 } else
386 dev_info(rdev->dev, "GPU reset succeed\n");
387 rv515_mc_resume(rdev, &save);
388 return ret;
389}
390
391/*
392 * GART.
393 */
394void rs600_gart_tlb_flush(struct radeon_device *rdev)
395{
396 uint32_t tmp;
397
398 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
399 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
400 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
401
402 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
403 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
404 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
405
406 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
407 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
408 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
409 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
410}
411
412int rs600_gart_init(struct radeon_device *rdev)
413{
414 int r;
415
416 if (rdev->gart.table.vram.robj) {
417 WARN(1, "RS600 GART already initialized\n");
418 return 0;
419 }
420 /* Initialize common gart structure */
421 r = radeon_gart_init(rdev);
422 if (r) {
423 return r;
424 }
425 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
426 return radeon_gart_table_vram_alloc(rdev);
427}
428
429static int rs600_gart_enable(struct radeon_device *rdev)
430{
431 u32 tmp;
432 int r, i;
433
434 if (rdev->gart.table.vram.robj == NULL) {
435 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
436 return -EINVAL;
437 }
438 r = radeon_gart_table_vram_pin(rdev);
439 if (r)
440 return r;
441 radeon_gart_restore(rdev);
442 /* Enable bus master */
443 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
444 WREG32(RADEON_BUS_CNTL, tmp);
445 /* FIXME: setup default page */
446 WREG32_MC(R_000100_MC_PT0_CNTL,
447 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
448 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
449
450 for (i = 0; i < 19; i++) {
451 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
452 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
453 S_00016C_SYSTEM_ACCESS_MODE_MASK(
454 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
455 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
456 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
457 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
458 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
459 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
460 }
461 /* enable first context */
462 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
463 S_000102_ENABLE_PAGE_TABLE(1) |
464 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
465
466 /* disable all other contexts */
467 for (i = 1; i < 8; i++)
468 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
469
470 /* setup the page table */
471 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
472 rdev->gart.table_addr);
473 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
474 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
475 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
476
477 /* System context maps to VRAM space */
478 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
479 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
480
481 /* enable page tables */
482 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
483 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
484 tmp = RREG32_MC(R_000009_MC_CNTL1);
485 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
486 rs600_gart_tlb_flush(rdev);
487 rdev->gart.ready = true;
488 return 0;
489}
490
491void rs600_gart_disable(struct radeon_device *rdev)
492{
493 u32 tmp;
494 int r;
495
496 /* FIXME: disable out of gart access */
497 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
498 tmp = RREG32_MC(R_000009_MC_CNTL1);
499 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
500 if (rdev->gart.table.vram.robj) {
501 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
502 if (r == 0) {
503 radeon_bo_kunmap(rdev->gart.table.vram.robj);
504 radeon_bo_unpin(rdev->gart.table.vram.robj);
505 radeon_bo_unreserve(rdev->gart.table.vram.robj);
506 }
507 }
508}
509
510void rs600_gart_fini(struct radeon_device *rdev)
511{
512 radeon_gart_fini(rdev);
513 rs600_gart_disable(rdev);
514 radeon_gart_table_vram_free(rdev);
515}
516
517#define R600_PTE_VALID (1 << 0)
518#define R600_PTE_SYSTEM (1 << 1)
519#define R600_PTE_SNOOPED (1 << 2)
520#define R600_PTE_READABLE (1 << 5)
521#define R600_PTE_WRITEABLE (1 << 6)
522
523int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
524{
525 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
526
527 if (i < 0 || i > rdev->gart.num_gpu_pages) {
528 return -EINVAL;
529 }
530 addr = addr & 0xFFFFFFFFFFFFF000ULL;
531 addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
532 addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
533 writeq(addr, ptr + (i * 8));
534 return 0;
535}
536
537int rs600_irq_set(struct radeon_device *rdev)
538{
539 uint32_t tmp = 0;
540 uint32_t mode_int = 0;
541 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
542 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
543 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
544 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
545
546 if (!rdev->irq.installed) {
547 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
548 WREG32(R_000040_GEN_INT_CNTL, 0);
549 return -EINVAL;
550 }
551 if (rdev->irq.sw_int) {
552 tmp |= S_000040_SW_INT_EN(1);
553 }
554 if (rdev->irq.gui_idle) {
555 tmp |= S_000040_GUI_IDLE(1);
556 }
557 if (rdev->irq.crtc_vblank_int[0] ||
558 rdev->irq.pflip[0]) {
559 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
560 }
561 if (rdev->irq.crtc_vblank_int[1] ||
562 rdev->irq.pflip[1]) {
563 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
564 }
565 if (rdev->irq.hpd[0]) {
566 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
567 }
568 if (rdev->irq.hpd[1]) {
569 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
570 }
571 WREG32(R_000040_GEN_INT_CNTL, tmp);
572 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
573 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
574 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
575 return 0;
576}
577
578static inline u32 rs600_irq_ack(struct radeon_device *rdev)
579{
580 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
581 uint32_t irq_mask = S_000044_SW_INT(1);
582 u32 tmp;
583
584 /* the interrupt works, but the status bit is permanently asserted */
585 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
586 if (!rdev->irq.gui_idle_acked)
587 irq_mask |= S_000044_GUI_IDLE_STAT(1);
588 }
589
590 if (G_000044_DISPLAY_INT_STAT(irqs)) {
591 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
592 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
593 WREG32(R_006534_D1MODE_VBLANK_STATUS,
594 S_006534_D1MODE_VBLANK_ACK(1));
595 }
596 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
597 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
598 S_006D34_D2MODE_VBLANK_ACK(1));
599 }
600 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
601 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
602 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
603 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
604 }
605 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
606 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
607 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
608 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
609 }
610 } else {
611 rdev->irq.stat_regs.r500.disp_int = 0;
612 }
613
614 if (irqs) {
615 WREG32(R_000044_GEN_INT_STATUS, irqs);
616 }
617 return irqs & irq_mask;
618}
619
620void rs600_irq_disable(struct radeon_device *rdev)
621{
622 WREG32(R_000040_GEN_INT_CNTL, 0);
623 WREG32(R_006540_DxMODE_INT_MASK, 0);
624 /* Wait and acknowledge irq */
625 mdelay(1);
626 rs600_irq_ack(rdev);
627}
628
629int rs600_irq_process(struct radeon_device *rdev)
630{
631 u32 status, msi_rearm;
632 bool queue_hotplug = false;
633
634 /* reset gui idle ack. the status bit is broken */
635 rdev->irq.gui_idle_acked = false;
636
637 status = rs600_irq_ack(rdev);
638 if (!status && !rdev->irq.stat_regs.r500.disp_int) {
639 return IRQ_NONE;
640 }
641 while (status || rdev->irq.stat_regs.r500.disp_int) {
642 /* SW interrupt */
643 if (G_000044_SW_INT(status)) {
644 radeon_fence_process(rdev);
645 }
646 /* GUI idle */
647 if (G_000040_GUI_IDLE(status)) {
648 rdev->irq.gui_idle_acked = true;
649 rdev->pm.gui_idle = true;
650 wake_up(&rdev->irq.idle_queue);
651 }
652 /* Vertical blank interrupts */
653 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
654 if (rdev->irq.crtc_vblank_int[0]) {
655 drm_handle_vblank(rdev->ddev, 0);
656 rdev->pm.vblank_sync = true;
657 wake_up(&rdev->irq.vblank_queue);
658 }
659 if (rdev->irq.pflip[0])
660 radeon_crtc_handle_flip(rdev, 0);
661 }
662 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
663 if (rdev->irq.crtc_vblank_int[1]) {
664 drm_handle_vblank(rdev->ddev, 1);
665 rdev->pm.vblank_sync = true;
666 wake_up(&rdev->irq.vblank_queue);
667 }
668 if (rdev->irq.pflip[1])
669 radeon_crtc_handle_flip(rdev, 1);
670 }
671 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
672 queue_hotplug = true;
673 DRM_DEBUG("HPD1\n");
674 }
675 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
676 queue_hotplug = true;
677 DRM_DEBUG("HPD2\n");
678 }
679 status = rs600_irq_ack(rdev);
680 }
681 /* reset gui idle ack. the status bit is broken */
682 rdev->irq.gui_idle_acked = false;
683 if (queue_hotplug)
684 schedule_work(&rdev->hotplug_work);
685 if (rdev->msi_enabled) {
686 switch (rdev->family) {
687 case CHIP_RS600:
688 case CHIP_RS690:
689 case CHIP_RS740:
690 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
691 WREG32(RADEON_BUS_CNTL, msi_rearm);
692 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
693 break;
694 default:
695 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
696 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
697 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
698 break;
699 }
700 }
701 return IRQ_HANDLED;
702}
703
704u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
705{
706 if (crtc == 0)
707 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
708 else
709 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
710}
711
712int rs600_mc_wait_for_idle(struct radeon_device *rdev)
713{
714 unsigned i;
715
716 for (i = 0; i < rdev->usec_timeout; i++) {
717 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
718 return 0;
719 udelay(1);
720 }
721 return -1;
722}
723
724void rs600_gpu_init(struct radeon_device *rdev)
725{
726 r420_pipes_init(rdev);
727 /* Wait for mc idle */
728 if (rs600_mc_wait_for_idle(rdev))
729 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
730}
731
732void rs600_mc_init(struct radeon_device *rdev)
733{
734 u64 base;
735
736 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
737 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
738 rdev->mc.vram_is_ddr = true;
739 rdev->mc.vram_width = 128;
740 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
741 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
742 rdev->mc.visible_vram_size = rdev->mc.aper_size;
743 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
744 base = RREG32_MC(R_000004_MC_FB_LOCATION);
745 base = G_000004_MC_FB_START(base) << 16;
746 radeon_vram_location(rdev, &rdev->mc, base);
747 rdev->mc.gtt_base_align = 0;
748 radeon_gtt_location(rdev, &rdev->mc);
749 radeon_update_bandwidth_info(rdev);
750}
751
752void rs600_bandwidth_update(struct radeon_device *rdev)
753{
754 struct drm_display_mode *mode0 = NULL;
755 struct drm_display_mode *mode1 = NULL;
756 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
757 /* FIXME: implement full support */
758
759 radeon_update_display_priority(rdev);
760
761 if (rdev->mode_info.crtcs[0]->base.enabled)
762 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
763 if (rdev->mode_info.crtcs[1]->base.enabled)
764 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
765
766 rs690_line_buffer_adjust(rdev, mode0, mode1);
767
768 if (rdev->disp_priority == 2) {
769 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
770 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
771 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
772 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
773 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
774 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
775 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
776 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
777 }
778}
779
780uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
781{
782 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
783 S_000070_MC_IND_CITF_ARB0(1));
784 return RREG32(R_000074_MC_IND_DATA);
785}
786
787void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
788{
789 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
790 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
791 WREG32(R_000074_MC_IND_DATA, v);
792}
793
794void rs600_debugfs(struct radeon_device *rdev)
795{
796 if (r100_debugfs_rbbm_init(rdev))
797 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
798}
799
800void rs600_set_safe_registers(struct radeon_device *rdev)
801{
802 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
803 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
804}
805
806static void rs600_mc_program(struct radeon_device *rdev)
807{
808 struct rv515_mc_save save;
809
810 /* Stops all mc clients */
811 rv515_mc_stop(rdev, &save);
812
813 /* Wait for mc idle */
814 if (rs600_mc_wait_for_idle(rdev))
815 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
816
817 /* FIXME: What does AGP means for such chipset ? */
818 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
819 WREG32_MC(R_000006_AGP_BASE, 0);
820 WREG32_MC(R_000007_AGP_BASE_2, 0);
821 /* Program MC */
822 WREG32_MC(R_000004_MC_FB_LOCATION,
823 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
824 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
825 WREG32(R_000134_HDP_FB_LOCATION,
826 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
827
828 rv515_mc_resume(rdev, &save);
829}
830
831static int rs600_startup(struct radeon_device *rdev)
832{
833 int r;
834
835 rs600_mc_program(rdev);
836 /* Resume clock */
837 rv515_clock_startup(rdev);
838 /* Initialize GPU configuration (# pipes, ...) */
839 rs600_gpu_init(rdev);
840 /* Initialize GART (initialize after TTM so we can allocate
841 * memory through TTM but finalize after TTM) */
842 r = rs600_gart_enable(rdev);
843 if (r)
844 return r;
845
846 /* allocate wb buffer */
847 r = radeon_wb_init(rdev);
848 if (r)
849 return r;
850
851 /* Enable IRQ */
852 rs600_irq_set(rdev);
853 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
854 /* 1M ring buffer */
855 r = r100_cp_init(rdev, 1024 * 1024);
856 if (r) {
857 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
858 return r;
859 }
860 r = r100_ib_init(rdev);
861 if (r) {
862 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
863 return r;
864 }
865
866 r = r600_audio_init(rdev);
867 if (r) {
868 dev_err(rdev->dev, "failed initializing audio\n");
869 return r;
870 }
871
872 return 0;
873}
874
875int rs600_resume(struct radeon_device *rdev)
876{
877 /* Make sur GART are not working */
878 rs600_gart_disable(rdev);
879 /* Resume clock before doing reset */
880 rv515_clock_startup(rdev);
881 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
882 if (radeon_asic_reset(rdev)) {
883 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
884 RREG32(R_000E40_RBBM_STATUS),
885 RREG32(R_0007C0_CP_STAT));
886 }
887 /* post */
888 atom_asic_init(rdev->mode_info.atom_context);
889 /* Resume clock after posting */
890 rv515_clock_startup(rdev);
891 /* Initialize surface registers */
892 radeon_surface_init(rdev);
893 return rs600_startup(rdev);
894}
895
896int rs600_suspend(struct radeon_device *rdev)
897{
898 r600_audio_fini(rdev);
899 r100_cp_disable(rdev);
900 radeon_wb_disable(rdev);
901 rs600_irq_disable(rdev);
902 rs600_gart_disable(rdev);
903 return 0;
904}
905
906void rs600_fini(struct radeon_device *rdev)
907{
908 r600_audio_fini(rdev);
909 r100_cp_fini(rdev);
910 radeon_wb_fini(rdev);
911 r100_ib_fini(rdev);
912 radeon_gem_fini(rdev);
913 rs600_gart_fini(rdev);
914 radeon_irq_kms_fini(rdev);
915 radeon_fence_driver_fini(rdev);
916 radeon_bo_fini(rdev);
917 radeon_atombios_fini(rdev);
918 kfree(rdev->bios);
919 rdev->bios = NULL;
920}
921
922int rs600_init(struct radeon_device *rdev)
923{
924 int r;
925
926 /* Disable VGA */
927 rv515_vga_render_disable(rdev);
928 /* Initialize scratch registers */
929 radeon_scratch_init(rdev);
930 /* Initialize surface registers */
931 radeon_surface_init(rdev);
932 /* restore some register to sane defaults */
933 r100_restore_sanity(rdev);
934 /* BIOS */
935 if (!radeon_get_bios(rdev)) {
936 if (ASIC_IS_AVIVO(rdev))
937 return -EINVAL;
938 }
939 if (rdev->is_atom_bios) {
940 r = radeon_atombios_init(rdev);
941 if (r)
942 return r;
943 } else {
944 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
945 return -EINVAL;
946 }
947 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
948 if (radeon_asic_reset(rdev)) {
949 dev_warn(rdev->dev,
950 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
951 RREG32(R_000E40_RBBM_STATUS),
952 RREG32(R_0007C0_CP_STAT));
953 }
954 /* check if cards are posted or not */
955 if (radeon_boot_test_post_card(rdev) == false)
956 return -EINVAL;
957
958 /* Initialize clocks */
959 radeon_get_clock_info(rdev->ddev);
960 /* initialize memory controller */
961 rs600_mc_init(rdev);
962 rs600_debugfs(rdev);
963 /* Fence driver */
964 r = radeon_fence_driver_init(rdev);
965 if (r)
966 return r;
967 r = radeon_irq_kms_init(rdev);
968 if (r)
969 return r;
970 /* Memory manager */
971 r = radeon_bo_init(rdev);
972 if (r)
973 return r;
974 r = rs600_gart_init(rdev);
975 if (r)
976 return r;
977 rs600_set_safe_registers(rdev);
978 rdev->accel_working = true;
979 r = rs600_startup(rdev);
980 if (r) {
981 /* Somethings want wront with the accel init stop accel */
982 dev_err(rdev->dev, "Disabling GPU acceleration\n");
983 r100_cp_fini(rdev);
984 radeon_wb_fini(rdev);
985 r100_ib_fini(rdev);
986 rs600_gart_fini(rdev);
987 radeon_irq_kms_fini(rdev);
988 rdev->accel_working = false;
989 }
990 return 0;
991}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28/* RS600 / Radeon X1250/X1270 integrated GPU
29 *
30 * This file gather function specific to RS600 which is the IGP of
31 * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32 * is the X1250/X1270 supporting AMD CPU). The display engine are
33 * the avivo one, bios is an atombios, 3D block are the one of the
34 * R4XX family. The GART is different from the RS400 one and is very
35 * close to the one of the R600 family (R600 likely being an evolution
36 * of the RS600 GART block).
37 */
38
39#include <linux/io-64-nonatomic-lo-hi.h>
40#include <linux/pci.h>
41
42#include <drm/drm_device.h>
43#include <drm/drm_vblank.h>
44#include <drm/drm_fourcc.h>
45#include <drm/drm_framebuffer.h>
46
47#include "atom.h"
48#include "radeon.h"
49#include "radeon_asic.h"
50#include "radeon_audio.h"
51#include "rs600_reg_safe.h"
52#include "rs600d.h"
53
54static void rs600_gpu_init(struct radeon_device *rdev);
55int rs600_mc_wait_for_idle(struct radeon_device *rdev);
56
57static const u32 crtc_offsets[2] =
58{
59 0,
60 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
61};
62
63static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
64{
65 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
66 return true;
67 else
68 return false;
69}
70
71static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
72{
73 u32 pos1, pos2;
74
75 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
76 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
77
78 if (pos1 != pos2)
79 return true;
80 else
81 return false;
82}
83
84/**
85 * avivo_wait_for_vblank - vblank wait asic callback.
86 *
87 * @rdev: radeon_device pointer
88 * @crtc: crtc to wait for vblank on
89 *
90 * Wait for vblank on the requested crtc (r5xx-r7xx).
91 */
92void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
93{
94 unsigned i = 0;
95
96 if (crtc >= rdev->num_crtc)
97 return;
98
99 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
100 return;
101
102 /* depending on when we hit vblank, we may be close to active; if so,
103 * wait for another frame.
104 */
105 while (avivo_is_in_vblank(rdev, crtc)) {
106 if (i++ % 100 == 0) {
107 if (!avivo_is_counter_moving(rdev, crtc))
108 break;
109 }
110 }
111
112 while (!avivo_is_in_vblank(rdev, crtc)) {
113 if (i++ % 100 == 0) {
114 if (!avivo_is_counter_moving(rdev, crtc))
115 break;
116 }
117 }
118}
119
120void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)
121{
122 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
123 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;
124 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
125 int i;
126
127 /* Lock the graphics update lock */
128 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
129 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
130
131 /* flip at hsync for async, default is vsync */
132 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,
133 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);
134 /* update pitch */
135 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,
136 fb->pitches[0] / fb->format->cpp[0]);
137 /* update the scanout addresses */
138 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
139 (u32)crtc_base);
140 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
141 (u32)crtc_base);
142
143 /* Wait for update_pending to go high. */
144 for (i = 0; i < rdev->usec_timeout; i++) {
145 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
146 break;
147 udelay(1);
148 }
149 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
150
151 /* Unlock the lock, so double-buffering can take place inside vblank */
152 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
153 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
154}
155
156bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)
157{
158 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
159
160 /* Return current update_pending status: */
161 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &
162 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);
163}
164
165void avivo_program_fmt(struct drm_encoder *encoder)
166{
167 struct drm_device *dev = encoder->dev;
168 struct radeon_device *rdev = dev->dev_private;
169 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
170 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
171 int bpc = 0;
172 u32 tmp = 0;
173 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
174
175 if (connector) {
176 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
177 bpc = radeon_get_monitor_bpc(connector);
178 dither = radeon_connector->dither;
179 }
180
181 /* LVDS FMT is set up by atom */
182 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
183 return;
184
185 if (bpc == 0)
186 return;
187
188 switch (bpc) {
189 case 6:
190 if (dither == RADEON_FMT_DITHER_ENABLE)
191 /* XXX sort out optimal dither settings */
192 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
193 else
194 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;
195 break;
196 case 8:
197 if (dither == RADEON_FMT_DITHER_ENABLE)
198 /* XXX sort out optimal dither settings */
199 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |
200 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);
201 else
202 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |
203 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);
204 break;
205 case 10:
206 default:
207 /* not needed */
208 break;
209 }
210
211 switch (radeon_encoder->encoder_id) {
212 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
213 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);
214 break;
215 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
216 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);
217 break;
218 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
219 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);
220 break;
221 case ENCODER_OBJECT_ID_INTERNAL_DDI:
222 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);
223 break;
224 default:
225 break;
226 }
227}
228
229void rs600_pm_misc(struct radeon_device *rdev)
230{
231 int requested_index = rdev->pm.requested_power_state_index;
232 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
233 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
234 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
235 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
236
237 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
238 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
239 tmp = RREG32(voltage->gpio.reg);
240 if (voltage->active_high)
241 tmp |= voltage->gpio.mask;
242 else
243 tmp &= ~(voltage->gpio.mask);
244 WREG32(voltage->gpio.reg, tmp);
245 if (voltage->delay)
246 udelay(voltage->delay);
247 } else {
248 tmp = RREG32(voltage->gpio.reg);
249 if (voltage->active_high)
250 tmp &= ~voltage->gpio.mask;
251 else
252 tmp |= voltage->gpio.mask;
253 WREG32(voltage->gpio.reg, tmp);
254 if (voltage->delay)
255 udelay(voltage->delay);
256 }
257 } else if (voltage->type == VOLTAGE_VDDC)
258 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);
259
260 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
261 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
262 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
263 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
264 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
265 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
266 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
267 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
268 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
269 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
270 }
271 } else {
272 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
273 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
274 }
275 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
276
277 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
278 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
279 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
280 if (voltage->delay) {
281 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
282 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
283 } else
284 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
285 } else
286 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
287 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
288
289 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
290 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
291 hdp_dyn_cntl &= ~HDP_FORCEON;
292 else
293 hdp_dyn_cntl |= HDP_FORCEON;
294 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
295#if 0
296 /* mc_host_dyn seems to cause hangs from time to time */
297 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
298 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
299 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
300 else
301 mc_host_dyn_cntl |= MC_HOST_FORCEON;
302 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
303#endif
304 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
305 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
306 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
307 else
308 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
309 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
310
311 /* set pcie lanes */
312 if ((rdev->flags & RADEON_IS_PCIE) &&
313 !(rdev->flags & RADEON_IS_IGP) &&
314 rdev->asic->pm.set_pcie_lanes &&
315 (ps->pcie_lanes !=
316 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
317 radeon_set_pcie_lanes(rdev,
318 ps->pcie_lanes);
319 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
320 }
321}
322
323void rs600_pm_prepare(struct radeon_device *rdev)
324{
325 struct drm_device *ddev = rdev->ddev;
326 struct drm_crtc *crtc;
327 struct radeon_crtc *radeon_crtc;
328 u32 tmp;
329
330 /* disable any active CRTCs */
331 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
332 radeon_crtc = to_radeon_crtc(crtc);
333 if (radeon_crtc->enabled) {
334 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
335 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
336 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
337 }
338 }
339}
340
341void rs600_pm_finish(struct radeon_device *rdev)
342{
343 struct drm_device *ddev = rdev->ddev;
344 struct drm_crtc *crtc;
345 struct radeon_crtc *radeon_crtc;
346 u32 tmp;
347
348 /* enable any active CRTCs */
349 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
350 radeon_crtc = to_radeon_crtc(crtc);
351 if (radeon_crtc->enabled) {
352 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
353 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
354 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
355 }
356 }
357}
358
359/* hpd for digital panel detect/disconnect */
360bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
361{
362 u32 tmp;
363 bool connected = false;
364
365 switch (hpd) {
366 case RADEON_HPD_1:
367 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
368 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
369 connected = true;
370 break;
371 case RADEON_HPD_2:
372 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
373 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
374 connected = true;
375 break;
376 default:
377 break;
378 }
379 return connected;
380}
381
382void rs600_hpd_set_polarity(struct radeon_device *rdev,
383 enum radeon_hpd_id hpd)
384{
385 u32 tmp;
386 bool connected = rs600_hpd_sense(rdev, hpd);
387
388 switch (hpd) {
389 case RADEON_HPD_1:
390 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
391 if (connected)
392 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
393 else
394 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
395 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
396 break;
397 case RADEON_HPD_2:
398 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
399 if (connected)
400 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
401 else
402 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
403 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
404 break;
405 default:
406 break;
407 }
408}
409
410void rs600_hpd_init(struct radeon_device *rdev)
411{
412 struct drm_device *dev = rdev->ddev;
413 struct drm_connector *connector;
414 unsigned enable = 0;
415
416 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
417 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
418 switch (radeon_connector->hpd.hpd) {
419 case RADEON_HPD_1:
420 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
421 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
422 break;
423 case RADEON_HPD_2:
424 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
425 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
426 break;
427 default:
428 break;
429 }
430 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
431 enable |= 1 << radeon_connector->hpd.hpd;
432 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
433 }
434 radeon_irq_kms_enable_hpd(rdev, enable);
435}
436
437void rs600_hpd_fini(struct radeon_device *rdev)
438{
439 struct drm_device *dev = rdev->ddev;
440 struct drm_connector *connector;
441 unsigned disable = 0;
442
443 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
444 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
445 switch (radeon_connector->hpd.hpd) {
446 case RADEON_HPD_1:
447 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
448 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
449 break;
450 case RADEON_HPD_2:
451 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
452 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
453 break;
454 default:
455 break;
456 }
457 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
458 disable |= 1 << radeon_connector->hpd.hpd;
459 }
460 radeon_irq_kms_disable_hpd(rdev, disable);
461}
462
463int rs600_asic_reset(struct radeon_device *rdev, bool hard)
464{
465 struct rv515_mc_save save;
466 u32 status, tmp;
467 int ret = 0;
468
469 status = RREG32(R_000E40_RBBM_STATUS);
470 if (!G_000E40_GUI_ACTIVE(status)) {
471 return 0;
472 }
473 /* Stops all mc clients */
474 rv515_mc_stop(rdev, &save);
475 status = RREG32(R_000E40_RBBM_STATUS);
476 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
477 /* stop CP */
478 WREG32(RADEON_CP_CSQ_CNTL, 0);
479 tmp = RREG32(RADEON_CP_RB_CNTL);
480 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
481 WREG32(RADEON_CP_RB_RPTR_WR, 0);
482 WREG32(RADEON_CP_RB_WPTR, 0);
483 WREG32(RADEON_CP_RB_CNTL, tmp);
484 pci_save_state(rdev->pdev);
485 /* disable bus mastering */
486 pci_clear_master(rdev->pdev);
487 mdelay(1);
488 /* reset GA+VAP */
489 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
490 S_0000F0_SOFT_RESET_GA(1));
491 RREG32(R_0000F0_RBBM_SOFT_RESET);
492 mdelay(500);
493 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
494 mdelay(1);
495 status = RREG32(R_000E40_RBBM_STATUS);
496 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
497 /* reset CP */
498 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
499 RREG32(R_0000F0_RBBM_SOFT_RESET);
500 mdelay(500);
501 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
502 mdelay(1);
503 status = RREG32(R_000E40_RBBM_STATUS);
504 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
505 /* reset MC */
506 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
507 RREG32(R_0000F0_RBBM_SOFT_RESET);
508 mdelay(500);
509 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
510 mdelay(1);
511 status = RREG32(R_000E40_RBBM_STATUS);
512 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
513 /* restore PCI & busmastering */
514 pci_restore_state(rdev->pdev);
515 /* Check if GPU is idle */
516 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
517 dev_err(rdev->dev, "failed to reset GPU\n");
518 ret = -1;
519 } else
520 dev_info(rdev->dev, "GPU reset succeed\n");
521 rv515_mc_resume(rdev, &save);
522 return ret;
523}
524
525/*
526 * GART.
527 */
528void rs600_gart_tlb_flush(struct radeon_device *rdev)
529{
530 uint32_t tmp;
531
532 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
533 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
534 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
535
536 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
537 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
538 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
539
540 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
541 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
542 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
543 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
544}
545
546static int rs600_gart_init(struct radeon_device *rdev)
547{
548 int r;
549
550 if (rdev->gart.robj) {
551 WARN(1, "RS600 GART already initialized\n");
552 return 0;
553 }
554 /* Initialize common gart structure */
555 r = radeon_gart_init(rdev);
556 if (r) {
557 return r;
558 }
559 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
560 return radeon_gart_table_vram_alloc(rdev);
561}
562
563static int rs600_gart_enable(struct radeon_device *rdev)
564{
565 u32 tmp;
566 int r, i;
567
568 if (rdev->gart.robj == NULL) {
569 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
570 return -EINVAL;
571 }
572 r = radeon_gart_table_vram_pin(rdev);
573 if (r)
574 return r;
575 /* Enable bus master */
576 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
577 WREG32(RADEON_BUS_CNTL, tmp);
578 /* FIXME: setup default page */
579 WREG32_MC(R_000100_MC_PT0_CNTL,
580 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
581 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
582
583 for (i = 0; i < 19; i++) {
584 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
585 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
586 S_00016C_SYSTEM_ACCESS_MODE_MASK(
587 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
588 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
589 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
590 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
591 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
592 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
593 }
594 /* enable first context */
595 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
596 S_000102_ENABLE_PAGE_TABLE(1) |
597 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
598
599 /* disable all other contexts */
600 for (i = 1; i < 8; i++)
601 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
602
603 /* setup the page table */
604 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
605 rdev->gart.table_addr);
606 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
607 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
608 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
609
610 /* System context maps to VRAM space */
611 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
612 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
613
614 /* enable page tables */
615 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
616 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
617 tmp = RREG32_MC(R_000009_MC_CNTL1);
618 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
619 rs600_gart_tlb_flush(rdev);
620 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
621 (unsigned)(rdev->mc.gtt_size >> 20),
622 (unsigned long long)rdev->gart.table_addr);
623 rdev->gart.ready = true;
624 return 0;
625}
626
627static void rs600_gart_disable(struct radeon_device *rdev)
628{
629 u32 tmp;
630
631 /* FIXME: disable out of gart access */
632 WREG32_MC(R_000100_MC_PT0_CNTL, 0);
633 tmp = RREG32_MC(R_000009_MC_CNTL1);
634 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
635 radeon_gart_table_vram_unpin(rdev);
636}
637
638static void rs600_gart_fini(struct radeon_device *rdev)
639{
640 radeon_gart_fini(rdev);
641 rs600_gart_disable(rdev);
642 radeon_gart_table_vram_free(rdev);
643}
644
645uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)
646{
647 addr = addr & 0xFFFFFFFFFFFFF000ULL;
648 addr |= R600_PTE_SYSTEM;
649 if (flags & RADEON_GART_PAGE_VALID)
650 addr |= R600_PTE_VALID;
651 if (flags & RADEON_GART_PAGE_READ)
652 addr |= R600_PTE_READABLE;
653 if (flags & RADEON_GART_PAGE_WRITE)
654 addr |= R600_PTE_WRITEABLE;
655 if (flags & RADEON_GART_PAGE_SNOOP)
656 addr |= R600_PTE_SNOOPED;
657 return addr;
658}
659
660void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
661 uint64_t entry)
662{
663 void __iomem *ptr = (void *)rdev->gart.ptr;
664 writeq(entry, ptr + (i * 8));
665}
666
667int rs600_irq_set(struct radeon_device *rdev)
668{
669 uint32_t tmp = 0;
670 uint32_t mode_int = 0;
671 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
672 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
673 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
674 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
675 u32 hdmi0;
676 if (ASIC_IS_DCE2(rdev))
677 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
678 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
679 else
680 hdmi0 = 0;
681
682 if (!rdev->irq.installed) {
683 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
684 WREG32(R_000040_GEN_INT_CNTL, 0);
685 return -EINVAL;
686 }
687 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
688 tmp |= S_000040_SW_INT_EN(1);
689 }
690 if (rdev->irq.crtc_vblank_int[0] ||
691 atomic_read(&rdev->irq.pflip[0])) {
692 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
693 }
694 if (rdev->irq.crtc_vblank_int[1] ||
695 atomic_read(&rdev->irq.pflip[1])) {
696 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
697 }
698 if (rdev->irq.hpd[0]) {
699 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
700 }
701 if (rdev->irq.hpd[1]) {
702 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
703 }
704 if (rdev->irq.afmt[0]) {
705 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
706 }
707 WREG32(R_000040_GEN_INT_CNTL, tmp);
708 WREG32(R_006540_DxMODE_INT_MASK, mode_int);
709 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
710 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
711 if (ASIC_IS_DCE2(rdev))
712 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
713
714 /* posting read */
715 RREG32(R_000040_GEN_INT_CNTL);
716
717 return 0;
718}
719
720static inline u32 rs600_irq_ack(struct radeon_device *rdev)
721{
722 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
723 uint32_t irq_mask = S_000044_SW_INT(1);
724 u32 tmp;
725
726 if (G_000044_DISPLAY_INT_STAT(irqs)) {
727 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
728 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
729 WREG32(R_006534_D1MODE_VBLANK_STATUS,
730 S_006534_D1MODE_VBLANK_ACK(1));
731 }
732 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
733 WREG32(R_006D34_D2MODE_VBLANK_STATUS,
734 S_006D34_D2MODE_VBLANK_ACK(1));
735 }
736 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
737 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
738 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
739 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
740 }
741 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
742 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
743 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
744 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
745 }
746 } else {
747 rdev->irq.stat_regs.r500.disp_int = 0;
748 }
749
750 if (ASIC_IS_DCE2(rdev)) {
751 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &
752 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);
753 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
754 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);
755 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);
756 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);
757 }
758 } else
759 rdev->irq.stat_regs.r500.hdmi0_status = 0;
760
761 if (irqs) {
762 WREG32(R_000044_GEN_INT_STATUS, irqs);
763 }
764 return irqs & irq_mask;
765}
766
767void rs600_irq_disable(struct radeon_device *rdev)
768{
769 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &
770 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);
771 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);
772 WREG32(R_000040_GEN_INT_CNTL, 0);
773 WREG32(R_006540_DxMODE_INT_MASK, 0);
774 /* Wait and acknowledge irq */
775 mdelay(1);
776 rs600_irq_ack(rdev);
777}
778
779int rs600_irq_process(struct radeon_device *rdev)
780{
781 u32 status, msi_rearm;
782 bool queue_hotplug = false;
783 bool queue_hdmi = false;
784
785 status = rs600_irq_ack(rdev);
786 if (!status &&
787 !rdev->irq.stat_regs.r500.disp_int &&
788 !rdev->irq.stat_regs.r500.hdmi0_status) {
789 return IRQ_NONE;
790 }
791 while (status ||
792 rdev->irq.stat_regs.r500.disp_int ||
793 rdev->irq.stat_regs.r500.hdmi0_status) {
794 /* SW interrupt */
795 if (G_000044_SW_INT(status)) {
796 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
797 }
798 /* Vertical blank interrupts */
799 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
800 if (rdev->irq.crtc_vblank_int[0]) {
801 drm_handle_vblank(rdev->ddev, 0);
802 rdev->pm.vblank_sync = true;
803 wake_up(&rdev->irq.vblank_queue);
804 }
805 if (atomic_read(&rdev->irq.pflip[0]))
806 radeon_crtc_handle_vblank(rdev, 0);
807 }
808 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
809 if (rdev->irq.crtc_vblank_int[1]) {
810 drm_handle_vblank(rdev->ddev, 1);
811 rdev->pm.vblank_sync = true;
812 wake_up(&rdev->irq.vblank_queue);
813 }
814 if (atomic_read(&rdev->irq.pflip[1]))
815 radeon_crtc_handle_vblank(rdev, 1);
816 }
817 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
818 queue_hotplug = true;
819 DRM_DEBUG("HPD1\n");
820 }
821 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
822 queue_hotplug = true;
823 DRM_DEBUG("HPD2\n");
824 }
825 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {
826 queue_hdmi = true;
827 DRM_DEBUG("HDMI0\n");
828 }
829 status = rs600_irq_ack(rdev);
830 }
831 if (queue_hotplug)
832 schedule_delayed_work(&rdev->hotplug_work, 0);
833 if (queue_hdmi)
834 schedule_work(&rdev->audio_work);
835 if (rdev->msi_enabled) {
836 switch (rdev->family) {
837 case CHIP_RS600:
838 case CHIP_RS690:
839 case CHIP_RS740:
840 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
841 WREG32(RADEON_BUS_CNTL, msi_rearm);
842 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
843 break;
844 default:
845 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
846 break;
847 }
848 }
849 return IRQ_HANDLED;
850}
851
852u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
853{
854 if (crtc == 0)
855 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
856 else
857 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
858}
859
860int rs600_mc_wait_for_idle(struct radeon_device *rdev)
861{
862 unsigned i;
863
864 for (i = 0; i < rdev->usec_timeout; i++) {
865 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
866 return 0;
867 udelay(1);
868 }
869 return -1;
870}
871
872static void rs600_gpu_init(struct radeon_device *rdev)
873{
874 r420_pipes_init(rdev);
875 /* Wait for mc idle */
876 if (rs600_mc_wait_for_idle(rdev))
877 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
878}
879
880static void rs600_mc_init(struct radeon_device *rdev)
881{
882 u64 base;
883
884 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
885 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
886 rdev->mc.vram_is_ddr = true;
887 rdev->mc.vram_width = 128;
888 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
889 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
890 rdev->mc.visible_vram_size = rdev->mc.aper_size;
891 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
892 base = RREG32_MC(R_000004_MC_FB_LOCATION);
893 base = G_000004_MC_FB_START(base) << 16;
894 radeon_vram_location(rdev, &rdev->mc, base);
895 rdev->mc.gtt_base_align = 0;
896 radeon_gtt_location(rdev, &rdev->mc);
897 radeon_update_bandwidth_info(rdev);
898}
899
900void rs600_bandwidth_update(struct radeon_device *rdev)
901{
902 struct drm_display_mode *mode0 = NULL;
903 struct drm_display_mode *mode1 = NULL;
904 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
905 /* FIXME: implement full support */
906
907 if (!rdev->mode_info.mode_config_initialized)
908 return;
909
910 radeon_update_display_priority(rdev);
911
912 if (rdev->mode_info.crtcs[0]->base.enabled)
913 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
914 if (rdev->mode_info.crtcs[1]->base.enabled)
915 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
916
917 rs690_line_buffer_adjust(rdev, mode0, mode1);
918
919 if (rdev->disp_priority == 2) {
920 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
921 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
922 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
923 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
924 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
925 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
926 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
927 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
928 }
929}
930
931uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
932{
933 unsigned long flags;
934 u32 r;
935
936 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
937 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
938 S_000070_MC_IND_CITF_ARB0(1));
939 r = RREG32(R_000074_MC_IND_DATA);
940 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
941 return r;
942}
943
944void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
945{
946 unsigned long flags;
947
948 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
949 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
950 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
951 WREG32(R_000074_MC_IND_DATA, v);
952 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
953}
954
955void rs600_set_safe_registers(struct radeon_device *rdev)
956{
957 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
958 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
959}
960
961static void rs600_mc_program(struct radeon_device *rdev)
962{
963 struct rv515_mc_save save;
964
965 /* Stops all mc clients */
966 rv515_mc_stop(rdev, &save);
967
968 /* Wait for mc idle */
969 if (rs600_mc_wait_for_idle(rdev))
970 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
971
972 /* FIXME: What does AGP means for such chipset ? */
973 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
974 WREG32_MC(R_000006_AGP_BASE, 0);
975 WREG32_MC(R_000007_AGP_BASE_2, 0);
976 /* Program MC */
977 WREG32_MC(R_000004_MC_FB_LOCATION,
978 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
979 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
980 WREG32(R_000134_HDP_FB_LOCATION,
981 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
982
983 rv515_mc_resume(rdev, &save);
984}
985
986static int rs600_startup(struct radeon_device *rdev)
987{
988 int r;
989
990 rs600_mc_program(rdev);
991 /* Resume clock */
992 rv515_clock_startup(rdev);
993 /* Initialize GPU configuration (# pipes, ...) */
994 rs600_gpu_init(rdev);
995 /* Initialize GART (initialize after TTM so we can allocate
996 * memory through TTM but finalize after TTM) */
997 r = rs600_gart_enable(rdev);
998 if (r)
999 return r;
1000
1001 /* allocate wb buffer */
1002 r = radeon_wb_init(rdev);
1003 if (r)
1004 return r;
1005
1006 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1007 if (r) {
1008 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1009 return r;
1010 }
1011
1012 /* Enable IRQ */
1013 if (!rdev->irq.installed) {
1014 r = radeon_irq_kms_init(rdev);
1015 if (r)
1016 return r;
1017 }
1018
1019 rs600_irq_set(rdev);
1020 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1021 /* 1M ring buffer */
1022 r = r100_cp_init(rdev, 1024 * 1024);
1023 if (r) {
1024 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
1025 return r;
1026 }
1027
1028 r = radeon_ib_pool_init(rdev);
1029 if (r) {
1030 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1031 return r;
1032 }
1033
1034 r = radeon_audio_init(rdev);
1035 if (r) {
1036 dev_err(rdev->dev, "failed initializing audio\n");
1037 return r;
1038 }
1039
1040 return 0;
1041}
1042
1043int rs600_resume(struct radeon_device *rdev)
1044{
1045 int r;
1046
1047 /* Make sur GART are not working */
1048 rs600_gart_disable(rdev);
1049 /* Resume clock before doing reset */
1050 rv515_clock_startup(rdev);
1051 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1052 if (radeon_asic_reset(rdev)) {
1053 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1054 RREG32(R_000E40_RBBM_STATUS),
1055 RREG32(R_0007C0_CP_STAT));
1056 }
1057 /* post */
1058 atom_asic_init(rdev->mode_info.atom_context);
1059 /* Resume clock after posting */
1060 rv515_clock_startup(rdev);
1061 /* Initialize surface registers */
1062 radeon_surface_init(rdev);
1063
1064 rdev->accel_working = true;
1065 r = rs600_startup(rdev);
1066 if (r) {
1067 rdev->accel_working = false;
1068 }
1069 return r;
1070}
1071
1072int rs600_suspend(struct radeon_device *rdev)
1073{
1074 radeon_pm_suspend(rdev);
1075 radeon_audio_fini(rdev);
1076 r100_cp_disable(rdev);
1077 radeon_wb_disable(rdev);
1078 rs600_irq_disable(rdev);
1079 rs600_gart_disable(rdev);
1080 return 0;
1081}
1082
1083void rs600_fini(struct radeon_device *rdev)
1084{
1085 radeon_pm_fini(rdev);
1086 radeon_audio_fini(rdev);
1087 r100_cp_fini(rdev);
1088 radeon_wb_fini(rdev);
1089 radeon_ib_pool_fini(rdev);
1090 radeon_gem_fini(rdev);
1091 rs600_gart_fini(rdev);
1092 radeon_irq_kms_fini(rdev);
1093 radeon_fence_driver_fini(rdev);
1094 radeon_bo_fini(rdev);
1095 radeon_atombios_fini(rdev);
1096 kfree(rdev->bios);
1097 rdev->bios = NULL;
1098}
1099
1100int rs600_init(struct radeon_device *rdev)
1101{
1102 int r;
1103
1104 /* Disable VGA */
1105 rv515_vga_render_disable(rdev);
1106 /* Initialize scratch registers */
1107 radeon_scratch_init(rdev);
1108 /* Initialize surface registers */
1109 radeon_surface_init(rdev);
1110 /* restore some register to sane defaults */
1111 r100_restore_sanity(rdev);
1112 /* BIOS */
1113 if (!radeon_get_bios(rdev)) {
1114 if (ASIC_IS_AVIVO(rdev))
1115 return -EINVAL;
1116 }
1117 if (rdev->is_atom_bios) {
1118 r = radeon_atombios_init(rdev);
1119 if (r)
1120 return r;
1121 } else {
1122 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
1123 return -EINVAL;
1124 }
1125 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1126 if (radeon_asic_reset(rdev)) {
1127 dev_warn(rdev->dev,
1128 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1129 RREG32(R_000E40_RBBM_STATUS),
1130 RREG32(R_0007C0_CP_STAT));
1131 }
1132 /* check if cards are posted or not */
1133 if (radeon_boot_test_post_card(rdev) == false)
1134 return -EINVAL;
1135
1136 /* Initialize clocks */
1137 radeon_get_clock_info(rdev->ddev);
1138 /* initialize memory controller */
1139 rs600_mc_init(rdev);
1140 r100_debugfs_rbbm_init(rdev);
1141 /* Fence driver */
1142 radeon_fence_driver_init(rdev);
1143 /* Memory manager */
1144 r = radeon_bo_init(rdev);
1145 if (r)
1146 return r;
1147 r = rs600_gart_init(rdev);
1148 if (r)
1149 return r;
1150 rs600_set_safe_registers(rdev);
1151
1152 /* Initialize power management */
1153 radeon_pm_init(rdev);
1154
1155 rdev->accel_working = true;
1156 r = rs600_startup(rdev);
1157 if (r) {
1158 /* Somethings want wront with the accel init stop accel */
1159 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1160 r100_cp_fini(rdev);
1161 radeon_wb_fini(rdev);
1162 radeon_ib_pool_fini(rdev);
1163 rs600_gart_fini(rdev);
1164 radeon_irq_kms_fini(rdev);
1165 rdev->accel_working = false;
1166 }
1167 return 0;
1168}