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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon_reg.h"
30#include "radeon.h"
31#include "atom.h"
32
33#include <linux/vga_switcheroo.h>
34#include <linux/slab.h>
35/*
36 * BIOS.
37 */
38
39/* If you boot an IGP board with a discrete card as the primary,
40 * the IGP rom is not accessible via the rom bar as the IGP rom is
41 * part of the system bios. On boot, the system bios puts a
42 * copy of the igp rom at the start of vram if a discrete card is
43 * present.
44 */
45static bool igp_read_bios_from_vram(struct radeon_device *rdev)
46{
47 uint8_t __iomem *bios;
48 resource_size_t vram_base;
49 resource_size_t size = 256 * 1024; /* ??? */
50
51 if (!(rdev->flags & RADEON_IS_IGP))
52 if (!radeon_card_posted(rdev))
53 return false;
54
55 rdev->bios = NULL;
56 vram_base = pci_resource_start(rdev->pdev, 0);
57 bios = ioremap(vram_base, size);
58 if (!bios) {
59 return false;
60 }
61
62 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
63 iounmap(bios);
64 return false;
65 }
66 rdev->bios = kmalloc(size, GFP_KERNEL);
67 if (rdev->bios == NULL) {
68 iounmap(bios);
69 return false;
70 }
71 memcpy_fromio(rdev->bios, bios, size);
72 iounmap(bios);
73 return true;
74}
75
76static bool radeon_read_bios(struct radeon_device *rdev)
77{
78 uint8_t __iomem *bios;
79 size_t size;
80
81 rdev->bios = NULL;
82 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
83 bios = pci_map_rom(rdev->pdev, &size);
84 if (!bios) {
85 return false;
86 }
87
88 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
89 pci_unmap_rom(rdev->pdev, bios);
90 return false;
91 }
92 rdev->bios = kmemdup(bios, size, GFP_KERNEL);
93 if (rdev->bios == NULL) {
94 pci_unmap_rom(rdev->pdev, bios);
95 return false;
96 }
97 pci_unmap_rom(rdev->pdev, bios);
98 return true;
99}
100
101/* ATRM is used to get the BIOS on the discrete cards in
102 * dual-gpu systems.
103 */
104static bool radeon_atrm_get_bios(struct radeon_device *rdev)
105{
106 int ret;
107 int size = 256 * 1024;
108 int i;
109
110 if (!radeon_atrm_supported(rdev->pdev))
111 return false;
112
113 rdev->bios = kmalloc(size, GFP_KERNEL);
114 if (!rdev->bios) {
115 DRM_ERROR("Unable to allocate bios\n");
116 return false;
117 }
118
119 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
120 ret = radeon_atrm_get_bios_chunk(rdev->bios,
121 (i * ATRM_BIOS_PAGE),
122 ATRM_BIOS_PAGE);
123 if (ret <= 0)
124 break;
125 }
126
127 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
128 kfree(rdev->bios);
129 return false;
130 }
131 return true;
132}
133
134static bool ni_read_disabled_bios(struct radeon_device *rdev)
135{
136 u32 bus_cntl;
137 u32 d1vga_control;
138 u32 d2vga_control;
139 u32 vga_render_control;
140 u32 rom_cntl;
141 bool r;
142
143 bus_cntl = RREG32(R600_BUS_CNTL);
144 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
145 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
146 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
147 rom_cntl = RREG32(R600_ROM_CNTL);
148
149 /* enable the rom */
150 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
151 /* Disable VGA mode */
152 WREG32(AVIVO_D1VGA_CONTROL,
153 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
154 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
155 WREG32(AVIVO_D2VGA_CONTROL,
156 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
157 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
158 WREG32(AVIVO_VGA_RENDER_CONTROL,
159 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
160 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
161
162 r = radeon_read_bios(rdev);
163
164 /* restore regs */
165 WREG32(R600_BUS_CNTL, bus_cntl);
166 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
167 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
168 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
169 WREG32(R600_ROM_CNTL, rom_cntl);
170 return r;
171}
172
173static bool r700_read_disabled_bios(struct radeon_device *rdev)
174{
175 uint32_t viph_control;
176 uint32_t bus_cntl;
177 uint32_t d1vga_control;
178 uint32_t d2vga_control;
179 uint32_t vga_render_control;
180 uint32_t rom_cntl;
181 uint32_t cg_spll_func_cntl = 0;
182 uint32_t cg_spll_status;
183 bool r;
184
185 viph_control = RREG32(RADEON_VIPH_CONTROL);
186 bus_cntl = RREG32(R600_BUS_CNTL);
187 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
188 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
189 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
190 rom_cntl = RREG32(R600_ROM_CNTL);
191
192 /* disable VIP */
193 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
194 /* enable the rom */
195 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
196 /* Disable VGA mode */
197 WREG32(AVIVO_D1VGA_CONTROL,
198 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
199 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
200 WREG32(AVIVO_D2VGA_CONTROL,
201 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
202 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
203 WREG32(AVIVO_VGA_RENDER_CONTROL,
204 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
205
206 if (rdev->family == CHIP_RV730) {
207 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
208
209 /* enable bypass mode */
210 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
211 R600_SPLL_BYPASS_EN));
212
213 /* wait for SPLL_CHG_STATUS to change to 1 */
214 cg_spll_status = 0;
215 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
216 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
217
218 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
219 } else
220 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
221
222 r = radeon_read_bios(rdev);
223
224 /* restore regs */
225 if (rdev->family == CHIP_RV730) {
226 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
227
228 /* wait for SPLL_CHG_STATUS to change to 1 */
229 cg_spll_status = 0;
230 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
231 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
232 }
233 WREG32(RADEON_VIPH_CONTROL, viph_control);
234 WREG32(R600_BUS_CNTL, bus_cntl);
235 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
236 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
237 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
238 WREG32(R600_ROM_CNTL, rom_cntl);
239 return r;
240}
241
242static bool r600_read_disabled_bios(struct radeon_device *rdev)
243{
244 uint32_t viph_control;
245 uint32_t bus_cntl;
246 uint32_t d1vga_control;
247 uint32_t d2vga_control;
248 uint32_t vga_render_control;
249 uint32_t rom_cntl;
250 uint32_t general_pwrmgt;
251 uint32_t low_vid_lower_gpio_cntl;
252 uint32_t medium_vid_lower_gpio_cntl;
253 uint32_t high_vid_lower_gpio_cntl;
254 uint32_t ctxsw_vid_lower_gpio_cntl;
255 uint32_t lower_gpio_enable;
256 bool r;
257
258 viph_control = RREG32(RADEON_VIPH_CONTROL);
259 bus_cntl = RREG32(R600_BUS_CNTL);
260 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
261 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
262 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
263 rom_cntl = RREG32(R600_ROM_CNTL);
264 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
265 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
266 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
267 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
268 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
269 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
270
271 /* disable VIP */
272 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
273 /* enable the rom */
274 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
275 /* Disable VGA mode */
276 WREG32(AVIVO_D1VGA_CONTROL,
277 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
278 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
279 WREG32(AVIVO_D2VGA_CONTROL,
280 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
281 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
282 WREG32(AVIVO_VGA_RENDER_CONTROL,
283 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
284
285 WREG32(R600_ROM_CNTL,
286 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
287 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
288 R600_SCK_OVERWRITE));
289
290 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
291 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
292 (low_vid_lower_gpio_cntl & ~0x400));
293 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
294 (medium_vid_lower_gpio_cntl & ~0x400));
295 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
296 (high_vid_lower_gpio_cntl & ~0x400));
297 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
298 (ctxsw_vid_lower_gpio_cntl & ~0x400));
299 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
300
301 r = radeon_read_bios(rdev);
302
303 /* restore regs */
304 WREG32(RADEON_VIPH_CONTROL, viph_control);
305 WREG32(R600_BUS_CNTL, bus_cntl);
306 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
307 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
308 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
309 WREG32(R600_ROM_CNTL, rom_cntl);
310 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
311 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
312 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
313 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
314 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
315 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
316 return r;
317}
318
319static bool avivo_read_disabled_bios(struct radeon_device *rdev)
320{
321 uint32_t seprom_cntl1;
322 uint32_t viph_control;
323 uint32_t bus_cntl;
324 uint32_t d1vga_control;
325 uint32_t d2vga_control;
326 uint32_t vga_render_control;
327 uint32_t gpiopad_a;
328 uint32_t gpiopad_en;
329 uint32_t gpiopad_mask;
330 bool r;
331
332 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
333 viph_control = RREG32(RADEON_VIPH_CONTROL);
334 bus_cntl = RREG32(RV370_BUS_CNTL);
335 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
336 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
337 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
338 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
339 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
340 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
341
342 WREG32(RADEON_SEPROM_CNTL1,
343 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
344 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
345 WREG32(RADEON_GPIOPAD_A, 0);
346 WREG32(RADEON_GPIOPAD_EN, 0);
347 WREG32(RADEON_GPIOPAD_MASK, 0);
348
349 /* disable VIP */
350 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
351
352 /* enable the rom */
353 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
354
355 /* Disable VGA mode */
356 WREG32(AVIVO_D1VGA_CONTROL,
357 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
358 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
359 WREG32(AVIVO_D2VGA_CONTROL,
360 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
361 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
362 WREG32(AVIVO_VGA_RENDER_CONTROL,
363 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
364
365 r = radeon_read_bios(rdev);
366
367 /* restore regs */
368 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
369 WREG32(RADEON_VIPH_CONTROL, viph_control);
370 WREG32(RV370_BUS_CNTL, bus_cntl);
371 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
372 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
373 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
374 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
375 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
376 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
377 return r;
378}
379
380static bool legacy_read_disabled_bios(struct radeon_device *rdev)
381{
382 uint32_t seprom_cntl1;
383 uint32_t viph_control;
384 uint32_t bus_cntl;
385 uint32_t crtc_gen_cntl;
386 uint32_t crtc2_gen_cntl;
387 uint32_t crtc_ext_cntl;
388 uint32_t fp2_gen_cntl;
389 bool r;
390
391 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
392 viph_control = RREG32(RADEON_VIPH_CONTROL);
393 if (rdev->flags & RADEON_IS_PCIE)
394 bus_cntl = RREG32(RV370_BUS_CNTL);
395 else
396 bus_cntl = RREG32(RADEON_BUS_CNTL);
397 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
398 crtc2_gen_cntl = 0;
399 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
400 fp2_gen_cntl = 0;
401
402 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
403 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
404 }
405
406 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
407 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
408 }
409
410 WREG32(RADEON_SEPROM_CNTL1,
411 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
412 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
413
414 /* disable VIP */
415 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
416
417 /* enable the rom */
418 if (rdev->flags & RADEON_IS_PCIE)
419 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
420 else
421 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
422
423 /* Turn off mem requests and CRTC for both controllers */
424 WREG32(RADEON_CRTC_GEN_CNTL,
425 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
426 (RADEON_CRTC_DISP_REQ_EN_B |
427 RADEON_CRTC_EXT_DISP_EN)));
428 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
429 WREG32(RADEON_CRTC2_GEN_CNTL,
430 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
431 RADEON_CRTC2_DISP_REQ_EN_B));
432 }
433 /* Turn off CRTC */
434 WREG32(RADEON_CRTC_EXT_CNTL,
435 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
436 (RADEON_CRTC_SYNC_TRISTAT |
437 RADEON_CRTC_DISPLAY_DIS)));
438
439 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
440 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
441 }
442
443 r = radeon_read_bios(rdev);
444
445 /* restore regs */
446 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
447 WREG32(RADEON_VIPH_CONTROL, viph_control);
448 if (rdev->flags & RADEON_IS_PCIE)
449 WREG32(RV370_BUS_CNTL, bus_cntl);
450 else
451 WREG32(RADEON_BUS_CNTL, bus_cntl);
452 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
453 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
454 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
455 }
456 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
457 if (rdev->ddev->pci_device == PCI_DEVICE_ID_ATI_RADEON_QY) {
458 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
459 }
460 return r;
461}
462
463static bool radeon_read_disabled_bios(struct radeon_device *rdev)
464{
465 if (rdev->flags & RADEON_IS_IGP)
466 return igp_read_bios_from_vram(rdev);
467 else if (rdev->family >= CHIP_BARTS)
468 return ni_read_disabled_bios(rdev);
469 else if (rdev->family >= CHIP_RV770)
470 return r700_read_disabled_bios(rdev);
471 else if (rdev->family >= CHIP_R600)
472 return r600_read_disabled_bios(rdev);
473 else if (rdev->family >= CHIP_RS600)
474 return avivo_read_disabled_bios(rdev);
475 else
476 return legacy_read_disabled_bios(rdev);
477}
478
479
480bool radeon_get_bios(struct radeon_device *rdev)
481{
482 bool r;
483 uint16_t tmp;
484
485 r = radeon_atrm_get_bios(rdev);
486 if (r == false)
487 r = igp_read_bios_from_vram(rdev);
488 if (r == false)
489 r = radeon_read_bios(rdev);
490 if (r == false) {
491 r = radeon_read_disabled_bios(rdev);
492 }
493 if (r == false || rdev->bios == NULL) {
494 DRM_ERROR("Unable to locate a BIOS ROM\n");
495 rdev->bios = NULL;
496 return false;
497 }
498 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
499 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
500 goto free_bios;
501 }
502
503 tmp = RBIOS16(0x18);
504 if (RBIOS8(tmp + 0x14) != 0x0) {
505 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
506 goto free_bios;
507 }
508
509 rdev->bios_header_start = RBIOS16(0x48);
510 if (!rdev->bios_header_start) {
511 goto free_bios;
512 }
513 tmp = rdev->bios_header_start + 4;
514 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
515 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
516 rdev->is_atom_bios = true;
517 } else {
518 rdev->is_atom_bios = false;
519 }
520
521 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
522 return true;
523free_bios:
524 kfree(rdev->bios);
525 rdev->bios = NULL;
526 return false;
527}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/acpi.h>
30#include <linux/pci.h>
31#include <linux/slab.h>
32
33#include <drm/drm_device.h>
34
35#include "atom.h"
36#include "radeon.h"
37#include "radeon_reg.h"
38
39/*
40 * BIOS.
41 */
42
43/* If you boot an IGP board with a discrete card as the primary,
44 * the IGP rom is not accessible via the rom bar as the IGP rom is
45 * part of the system bios. On boot, the system bios puts a
46 * copy of the igp rom at the start of vram if a discrete card is
47 * present.
48 */
49static bool igp_read_bios_from_vram(struct radeon_device *rdev)
50{
51 uint8_t __iomem *bios;
52 resource_size_t vram_base;
53 resource_size_t size = 256 * 1024; /* ??? */
54
55 if (!(rdev->flags & RADEON_IS_IGP))
56 if (!radeon_card_posted(rdev))
57 return false;
58
59 rdev->bios = NULL;
60 vram_base = pci_resource_start(rdev->pdev, 0);
61 bios = ioremap(vram_base, size);
62 if (!bios) {
63 return false;
64 }
65
66 if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
67 iounmap(bios);
68 return false;
69 }
70 rdev->bios = kmalloc(size, GFP_KERNEL);
71 if (rdev->bios == NULL) {
72 iounmap(bios);
73 return false;
74 }
75 memcpy_fromio(rdev->bios, bios, size);
76 iounmap(bios);
77 return true;
78}
79
80static bool radeon_read_bios(struct radeon_device *rdev)
81{
82 uint8_t __iomem *bios, val1, val2;
83 size_t size;
84
85 rdev->bios = NULL;
86 /* XXX: some cards may return 0 for rom size? ddx has a workaround */
87 bios = pci_map_rom(rdev->pdev, &size);
88 if (!bios) {
89 return false;
90 }
91
92 val1 = readb(&bios[0]);
93 val2 = readb(&bios[1]);
94
95 if (size == 0 || val1 != 0x55 || val2 != 0xaa) {
96 pci_unmap_rom(rdev->pdev, bios);
97 return false;
98 }
99 rdev->bios = kzalloc(size, GFP_KERNEL);
100 if (rdev->bios == NULL) {
101 pci_unmap_rom(rdev->pdev, bios);
102 return false;
103 }
104 memcpy_fromio(rdev->bios, bios, size);
105 pci_unmap_rom(rdev->pdev, bios);
106 return true;
107}
108
109static bool radeon_read_platform_bios(struct radeon_device *rdev)
110{
111 phys_addr_t rom = rdev->pdev->rom;
112 size_t romlen = rdev->pdev->romlen;
113 void __iomem *bios;
114
115 rdev->bios = NULL;
116
117 if (!rom || romlen == 0)
118 return false;
119
120 rdev->bios = kzalloc(romlen, GFP_KERNEL);
121 if (!rdev->bios)
122 return false;
123
124 bios = ioremap(rom, romlen);
125 if (!bios)
126 goto free_bios;
127
128 memcpy_fromio(rdev->bios, bios, romlen);
129 iounmap(bios);
130
131 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
132 goto free_bios;
133
134 return true;
135free_bios:
136 kfree(rdev->bios);
137 return false;
138}
139
140#ifdef CONFIG_ACPI
141/* ATRM is used to get the BIOS on the discrete cards in
142 * dual-gpu systems.
143 */
144/* retrieve the ROM in 4k blocks */
145#define ATRM_BIOS_PAGE 4096
146/**
147 * radeon_atrm_call - fetch a chunk of the vbios
148 *
149 * @atrm_handle: acpi ATRM handle
150 * @bios: vbios image pointer
151 * @offset: offset of vbios image data to fetch
152 * @len: length of vbios image data to fetch
153 *
154 * Executes ATRM to fetch a chunk of the discrete
155 * vbios image on PX systems (all asics).
156 * Returns the length of the buffer fetched.
157 */
158static int radeon_atrm_call(acpi_handle atrm_handle, uint8_t *bios,
159 int offset, int len)
160{
161 acpi_status status;
162 union acpi_object atrm_arg_elements[2], *obj;
163 struct acpi_object_list atrm_arg;
164 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL};
165
166 atrm_arg.count = 2;
167 atrm_arg.pointer = &atrm_arg_elements[0];
168
169 atrm_arg_elements[0].type = ACPI_TYPE_INTEGER;
170 atrm_arg_elements[0].integer.value = offset;
171
172 atrm_arg_elements[1].type = ACPI_TYPE_INTEGER;
173 atrm_arg_elements[1].integer.value = len;
174
175 status = acpi_evaluate_object(atrm_handle, NULL, &atrm_arg, &buffer);
176 if (ACPI_FAILURE(status)) {
177 printk("failed to evaluate ATRM got %s\n", acpi_format_exception(status));
178 return -ENODEV;
179 }
180
181 obj = (union acpi_object *)buffer.pointer;
182 memcpy(bios+offset, obj->buffer.pointer, obj->buffer.length);
183 len = obj->buffer.length;
184 kfree(buffer.pointer);
185 return len;
186}
187
188static bool radeon_atrm_get_bios(struct radeon_device *rdev)
189{
190 int ret;
191 int size = 256 * 1024;
192 int i;
193 struct pci_dev *pdev = NULL;
194 acpi_handle dhandle, atrm_handle;
195 acpi_status status;
196 bool found = false;
197
198 /* ATRM is for the discrete card only */
199 if (rdev->flags & RADEON_IS_IGP)
200 return false;
201
202 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
203 dhandle = ACPI_HANDLE(&pdev->dev);
204 if (!dhandle)
205 continue;
206
207 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
208 if (ACPI_SUCCESS(status)) {
209 found = true;
210 break;
211 }
212 }
213
214 if (!found) {
215 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) {
216 dhandle = ACPI_HANDLE(&pdev->dev);
217 if (!dhandle)
218 continue;
219
220 status = acpi_get_handle(dhandle, "ATRM", &atrm_handle);
221 if (ACPI_SUCCESS(status)) {
222 found = true;
223 break;
224 }
225 }
226 }
227
228 if (!found)
229 return false;
230 pci_dev_put(pdev);
231
232 rdev->bios = kmalloc(size, GFP_KERNEL);
233 if (!rdev->bios) {
234 DRM_ERROR("Unable to allocate bios\n");
235 return false;
236 }
237
238 for (i = 0; i < size / ATRM_BIOS_PAGE; i++) {
239 ret = radeon_atrm_call(atrm_handle,
240 rdev->bios,
241 (i * ATRM_BIOS_PAGE),
242 ATRM_BIOS_PAGE);
243 if (ret < ATRM_BIOS_PAGE)
244 break;
245 }
246
247 if (i == 0 || rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
248 kfree(rdev->bios);
249 return false;
250 }
251 return true;
252}
253#else
254static inline bool radeon_atrm_get_bios(struct radeon_device *rdev)
255{
256 return false;
257}
258#endif
259
260static bool ni_read_disabled_bios(struct radeon_device *rdev)
261{
262 u32 bus_cntl;
263 u32 d1vga_control;
264 u32 d2vga_control;
265 u32 vga_render_control;
266 u32 rom_cntl;
267 bool r;
268
269 bus_cntl = RREG32(R600_BUS_CNTL);
270 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
271 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
272 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
273 rom_cntl = RREG32(R600_ROM_CNTL);
274
275 /* enable the rom */
276 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
277 if (!ASIC_IS_NODCE(rdev)) {
278 /* Disable VGA mode */
279 WREG32(AVIVO_D1VGA_CONTROL,
280 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
281 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
282 WREG32(AVIVO_D2VGA_CONTROL,
283 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
284 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
285 WREG32(AVIVO_VGA_RENDER_CONTROL,
286 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
287 }
288 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE);
289
290 r = radeon_read_bios(rdev);
291
292 /* restore regs */
293 WREG32(R600_BUS_CNTL, bus_cntl);
294 if (!ASIC_IS_NODCE(rdev)) {
295 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
296 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
297 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
298 }
299 WREG32(R600_ROM_CNTL, rom_cntl);
300 return r;
301}
302
303static bool r700_read_disabled_bios(struct radeon_device *rdev)
304{
305 uint32_t viph_control;
306 uint32_t bus_cntl;
307 uint32_t d1vga_control;
308 uint32_t d2vga_control;
309 uint32_t vga_render_control;
310 uint32_t rom_cntl;
311 uint32_t cg_spll_func_cntl = 0;
312 uint32_t cg_spll_status;
313 bool r;
314
315 viph_control = RREG32(RADEON_VIPH_CONTROL);
316 bus_cntl = RREG32(R600_BUS_CNTL);
317 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
318 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
319 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
320 rom_cntl = RREG32(R600_ROM_CNTL);
321
322 /* disable VIP */
323 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
324 /* enable the rom */
325 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
326 /* Disable VGA mode */
327 WREG32(AVIVO_D1VGA_CONTROL,
328 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
329 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
330 WREG32(AVIVO_D2VGA_CONTROL,
331 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
332 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
333 WREG32(AVIVO_VGA_RENDER_CONTROL,
334 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
335
336 if (rdev->family == CHIP_RV730) {
337 cg_spll_func_cntl = RREG32(R600_CG_SPLL_FUNC_CNTL);
338
339 /* enable bypass mode */
340 WREG32(R600_CG_SPLL_FUNC_CNTL, (cg_spll_func_cntl |
341 R600_SPLL_BYPASS_EN));
342
343 /* wait for SPLL_CHG_STATUS to change to 1 */
344 cg_spll_status = 0;
345 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
346 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
347
348 WREG32(R600_ROM_CNTL, (rom_cntl & ~R600_SCK_OVERWRITE));
349 } else
350 WREG32(R600_ROM_CNTL, (rom_cntl | R600_SCK_OVERWRITE));
351
352 r = radeon_read_bios(rdev);
353
354 /* restore regs */
355 if (rdev->family == CHIP_RV730) {
356 WREG32(R600_CG_SPLL_FUNC_CNTL, cg_spll_func_cntl);
357
358 /* wait for SPLL_CHG_STATUS to change to 1 */
359 cg_spll_status = 0;
360 while (!(cg_spll_status & R600_SPLL_CHG_STATUS))
361 cg_spll_status = RREG32(R600_CG_SPLL_STATUS);
362 }
363 WREG32(RADEON_VIPH_CONTROL, viph_control);
364 WREG32(R600_BUS_CNTL, bus_cntl);
365 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
366 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
367 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
368 WREG32(R600_ROM_CNTL, rom_cntl);
369 return r;
370}
371
372static bool r600_read_disabled_bios(struct radeon_device *rdev)
373{
374 uint32_t viph_control;
375 uint32_t bus_cntl;
376 uint32_t d1vga_control;
377 uint32_t d2vga_control;
378 uint32_t vga_render_control;
379 uint32_t rom_cntl;
380 uint32_t general_pwrmgt;
381 uint32_t low_vid_lower_gpio_cntl;
382 uint32_t medium_vid_lower_gpio_cntl;
383 uint32_t high_vid_lower_gpio_cntl;
384 uint32_t ctxsw_vid_lower_gpio_cntl;
385 uint32_t lower_gpio_enable;
386 bool r;
387
388 viph_control = RREG32(RADEON_VIPH_CONTROL);
389 bus_cntl = RREG32(R600_BUS_CNTL);
390 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
391 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
392 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
393 rom_cntl = RREG32(R600_ROM_CNTL);
394 general_pwrmgt = RREG32(R600_GENERAL_PWRMGT);
395 low_vid_lower_gpio_cntl = RREG32(R600_LOW_VID_LOWER_GPIO_CNTL);
396 medium_vid_lower_gpio_cntl = RREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL);
397 high_vid_lower_gpio_cntl = RREG32(R600_HIGH_VID_LOWER_GPIO_CNTL);
398 ctxsw_vid_lower_gpio_cntl = RREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL);
399 lower_gpio_enable = RREG32(R600_LOWER_GPIO_ENABLE);
400
401 /* disable VIP */
402 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
403 /* enable the rom */
404 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS));
405 /* Disable VGA mode */
406 WREG32(AVIVO_D1VGA_CONTROL,
407 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
408 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
409 WREG32(AVIVO_D2VGA_CONTROL,
410 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
411 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
412 WREG32(AVIVO_VGA_RENDER_CONTROL,
413 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
414
415 WREG32(R600_ROM_CNTL,
416 ((rom_cntl & ~R600_SCK_PRESCALE_CRYSTAL_CLK_MASK) |
417 (1 << R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT) |
418 R600_SCK_OVERWRITE));
419
420 WREG32(R600_GENERAL_PWRMGT, (general_pwrmgt & ~R600_OPEN_DRAIN_PADS));
421 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL,
422 (low_vid_lower_gpio_cntl & ~0x400));
423 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL,
424 (medium_vid_lower_gpio_cntl & ~0x400));
425 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL,
426 (high_vid_lower_gpio_cntl & ~0x400));
427 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL,
428 (ctxsw_vid_lower_gpio_cntl & ~0x400));
429 WREG32(R600_LOWER_GPIO_ENABLE, (lower_gpio_enable | 0x400));
430
431 r = radeon_read_bios(rdev);
432
433 /* restore regs */
434 WREG32(RADEON_VIPH_CONTROL, viph_control);
435 WREG32(R600_BUS_CNTL, bus_cntl);
436 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
437 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
438 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
439 WREG32(R600_ROM_CNTL, rom_cntl);
440 WREG32(R600_GENERAL_PWRMGT, general_pwrmgt);
441 WREG32(R600_LOW_VID_LOWER_GPIO_CNTL, low_vid_lower_gpio_cntl);
442 WREG32(R600_MEDIUM_VID_LOWER_GPIO_CNTL, medium_vid_lower_gpio_cntl);
443 WREG32(R600_HIGH_VID_LOWER_GPIO_CNTL, high_vid_lower_gpio_cntl);
444 WREG32(R600_CTXSW_VID_LOWER_GPIO_CNTL, ctxsw_vid_lower_gpio_cntl);
445 WREG32(R600_LOWER_GPIO_ENABLE, lower_gpio_enable);
446 return r;
447}
448
449static bool avivo_read_disabled_bios(struct radeon_device *rdev)
450{
451 uint32_t seprom_cntl1;
452 uint32_t viph_control;
453 uint32_t bus_cntl;
454 uint32_t d1vga_control;
455 uint32_t d2vga_control;
456 uint32_t vga_render_control;
457 uint32_t gpiopad_a;
458 uint32_t gpiopad_en;
459 uint32_t gpiopad_mask;
460 bool r;
461
462 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
463 viph_control = RREG32(RADEON_VIPH_CONTROL);
464 bus_cntl = RREG32(RV370_BUS_CNTL);
465 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL);
466 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL);
467 vga_render_control = RREG32(AVIVO_VGA_RENDER_CONTROL);
468 gpiopad_a = RREG32(RADEON_GPIOPAD_A);
469 gpiopad_en = RREG32(RADEON_GPIOPAD_EN);
470 gpiopad_mask = RREG32(RADEON_GPIOPAD_MASK);
471
472 WREG32(RADEON_SEPROM_CNTL1,
473 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
474 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
475 WREG32(RADEON_GPIOPAD_A, 0);
476 WREG32(RADEON_GPIOPAD_EN, 0);
477 WREG32(RADEON_GPIOPAD_MASK, 0);
478
479 /* disable VIP */
480 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
481
482 /* enable the rom */
483 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
484
485 /* Disable VGA mode */
486 WREG32(AVIVO_D1VGA_CONTROL,
487 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
488 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
489 WREG32(AVIVO_D2VGA_CONTROL,
490 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE |
491 AVIVO_DVGA_CONTROL_TIMING_SELECT)));
492 WREG32(AVIVO_VGA_RENDER_CONTROL,
493 (vga_render_control & ~AVIVO_VGA_VSTATUS_CNTL_MASK));
494
495 r = radeon_read_bios(rdev);
496
497 /* restore regs */
498 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
499 WREG32(RADEON_VIPH_CONTROL, viph_control);
500 WREG32(RV370_BUS_CNTL, bus_cntl);
501 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control);
502 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control);
503 WREG32(AVIVO_VGA_RENDER_CONTROL, vga_render_control);
504 WREG32(RADEON_GPIOPAD_A, gpiopad_a);
505 WREG32(RADEON_GPIOPAD_EN, gpiopad_en);
506 WREG32(RADEON_GPIOPAD_MASK, gpiopad_mask);
507 return r;
508}
509
510static bool legacy_read_disabled_bios(struct radeon_device *rdev)
511{
512 uint32_t seprom_cntl1;
513 uint32_t viph_control;
514 uint32_t bus_cntl;
515 uint32_t crtc_gen_cntl;
516 uint32_t crtc2_gen_cntl;
517 uint32_t crtc_ext_cntl;
518 uint32_t fp2_gen_cntl;
519 bool r;
520
521 seprom_cntl1 = RREG32(RADEON_SEPROM_CNTL1);
522 viph_control = RREG32(RADEON_VIPH_CONTROL);
523 if (rdev->flags & RADEON_IS_PCIE)
524 bus_cntl = RREG32(RV370_BUS_CNTL);
525 else
526 bus_cntl = RREG32(RADEON_BUS_CNTL);
527 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
528 crtc2_gen_cntl = 0;
529 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
530 fp2_gen_cntl = 0;
531
532 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
533 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
534 }
535
536 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
537 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
538 }
539
540 WREG32(RADEON_SEPROM_CNTL1,
541 ((seprom_cntl1 & ~RADEON_SCK_PRESCALE_MASK) |
542 (0xc << RADEON_SCK_PRESCALE_SHIFT)));
543
544 /* disable VIP */
545 WREG32(RADEON_VIPH_CONTROL, (viph_control & ~RADEON_VIPH_EN));
546
547 /* enable the rom */
548 if (rdev->flags & RADEON_IS_PCIE)
549 WREG32(RV370_BUS_CNTL, (bus_cntl & ~RV370_BUS_BIOS_DIS_ROM));
550 else
551 WREG32(RADEON_BUS_CNTL, (bus_cntl & ~RADEON_BUS_BIOS_DIS_ROM));
552
553 /* Turn off mem requests and CRTC for both controllers */
554 WREG32(RADEON_CRTC_GEN_CNTL,
555 ((crtc_gen_cntl & ~RADEON_CRTC_EN) |
556 (RADEON_CRTC_DISP_REQ_EN_B |
557 RADEON_CRTC_EXT_DISP_EN)));
558 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
559 WREG32(RADEON_CRTC2_GEN_CNTL,
560 ((crtc2_gen_cntl & ~RADEON_CRTC2_EN) |
561 RADEON_CRTC2_DISP_REQ_EN_B));
562 }
563 /* Turn off CRTC */
564 WREG32(RADEON_CRTC_EXT_CNTL,
565 ((crtc_ext_cntl & ~RADEON_CRTC_CRT_ON) |
566 (RADEON_CRTC_SYNC_TRISTAT |
567 RADEON_CRTC_DISPLAY_DIS)));
568
569 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
570 WREG32(RADEON_FP2_GEN_CNTL, (fp2_gen_cntl & ~RADEON_FP2_ON));
571 }
572
573 r = radeon_read_bios(rdev);
574
575 /* restore regs */
576 WREG32(RADEON_SEPROM_CNTL1, seprom_cntl1);
577 WREG32(RADEON_VIPH_CONTROL, viph_control);
578 if (rdev->flags & RADEON_IS_PCIE)
579 WREG32(RV370_BUS_CNTL, bus_cntl);
580 else
581 WREG32(RADEON_BUS_CNTL, bus_cntl);
582 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
583 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
584 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
585 }
586 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
587 if (rdev->pdev->device == PCI_DEVICE_ID_ATI_RADEON_QY) {
588 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
589 }
590 return r;
591}
592
593static bool radeon_read_disabled_bios(struct radeon_device *rdev)
594{
595 if (rdev->flags & RADEON_IS_IGP)
596 return igp_read_bios_from_vram(rdev);
597 else if (rdev->family >= CHIP_BARTS)
598 return ni_read_disabled_bios(rdev);
599 else if (rdev->family >= CHIP_RV770)
600 return r700_read_disabled_bios(rdev);
601 else if (rdev->family >= CHIP_R600)
602 return r600_read_disabled_bios(rdev);
603 else if (rdev->family >= CHIP_RS600)
604 return avivo_read_disabled_bios(rdev);
605 else
606 return legacy_read_disabled_bios(rdev);
607}
608
609#ifdef CONFIG_ACPI
610static bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
611{
612 struct acpi_table_header *hdr;
613 acpi_size tbl_size;
614 UEFI_ACPI_VFCT *vfct;
615 unsigned offset;
616 bool r = false;
617
618 if (!ACPI_SUCCESS(acpi_get_table("VFCT", 1, &hdr)))
619 return false;
620 tbl_size = hdr->length;
621 if (tbl_size < sizeof(UEFI_ACPI_VFCT)) {
622 DRM_ERROR("ACPI VFCT table present but broken (too short #1)\n");
623 goto out;
624 }
625
626 vfct = (UEFI_ACPI_VFCT *)hdr;
627 offset = vfct->VBIOSImageOffset;
628
629 while (offset < tbl_size) {
630 GOP_VBIOS_CONTENT *vbios = (GOP_VBIOS_CONTENT *)((char *)hdr + offset);
631 VFCT_IMAGE_HEADER *vhdr = &vbios->VbiosHeader;
632
633 offset += sizeof(VFCT_IMAGE_HEADER);
634 if (offset > tbl_size) {
635 DRM_ERROR("ACPI VFCT image header truncated\n");
636 goto out;
637 }
638
639 offset += vhdr->ImageLength;
640 if (offset > tbl_size) {
641 DRM_ERROR("ACPI VFCT image truncated\n");
642 goto out;
643 }
644
645 if (vhdr->ImageLength &&
646 vhdr->PCIBus == rdev->pdev->bus->number &&
647 vhdr->PCIDevice == PCI_SLOT(rdev->pdev->devfn) &&
648 vhdr->PCIFunction == PCI_FUNC(rdev->pdev->devfn) &&
649 vhdr->VendorID == rdev->pdev->vendor &&
650 vhdr->DeviceID == rdev->pdev->device) {
651 rdev->bios = kmemdup(&vbios->VbiosContent,
652 vhdr->ImageLength,
653 GFP_KERNEL);
654 if (rdev->bios)
655 r = true;
656
657 goto out;
658 }
659 }
660
661 DRM_ERROR("ACPI VFCT table present but broken (too short #2)\n");
662
663out:
664 acpi_put_table(hdr);
665 return r;
666}
667#else
668static inline bool radeon_acpi_vfct_bios(struct radeon_device *rdev)
669{
670 return false;
671}
672#endif
673
674bool radeon_get_bios(struct radeon_device *rdev)
675{
676 bool r;
677 uint16_t tmp;
678
679 r = radeon_atrm_get_bios(rdev);
680 if (!r)
681 r = radeon_acpi_vfct_bios(rdev);
682 if (!r)
683 r = igp_read_bios_from_vram(rdev);
684 if (!r)
685 r = radeon_read_bios(rdev);
686 if (!r)
687 r = radeon_read_disabled_bios(rdev);
688 if (!r)
689 r = radeon_read_platform_bios(rdev);
690 if (!r || rdev->bios == NULL) {
691 DRM_ERROR("Unable to locate a BIOS ROM\n");
692 rdev->bios = NULL;
693 return false;
694 }
695 if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa) {
696 printk("BIOS signature incorrect %x %x\n", rdev->bios[0], rdev->bios[1]);
697 goto free_bios;
698 }
699
700 tmp = RBIOS16(0x18);
701 if (RBIOS8(tmp + 0x14) != 0x0) {
702 DRM_INFO("Not an x86 BIOS ROM, not using.\n");
703 goto free_bios;
704 }
705
706 rdev->bios_header_start = RBIOS16(0x48);
707 if (!rdev->bios_header_start) {
708 goto free_bios;
709 }
710 tmp = rdev->bios_header_start + 4;
711 if (!memcmp(rdev->bios + tmp, "ATOM", 4) ||
712 !memcmp(rdev->bios + tmp, "MOTA", 4)) {
713 rdev->is_atom_bios = true;
714 } else {
715 rdev->is_atom_bios = false;
716 }
717
718 DRM_DEBUG("%sBIOS detected\n", rdev->is_atom_bios ? "ATOM" : "COM");
719 return true;
720free_bios:
721 kfree(rdev->bios);
722 rdev->bios = NULL;
723 return false;
724}